java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_3_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-c17473d-m [2018-02-04 19:31:43,959 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-04 19:31:43,960 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-04 19:31:43,972 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-04 19:31:43,972 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-04 19:31:43,973 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-04 19:31:43,974 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-04 19:31:43,975 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-04 19:31:43,977 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-04 19:31:43,977 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-04 19:31:43,978 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-04 19:31:43,978 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-04 19:31:43,979 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-04 19:31:43,980 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-04 19:31:43,981 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-04 19:31:43,983 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-04 19:31:43,984 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-04 19:31:43,986 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-04 19:31:43,987 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-04 19:31:43,988 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-04 19:31:43,989 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-02-04 19:31:43,989 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-02-04 19:31:43,990 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-02-04 19:31:43,990 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-02-04 19:31:43,991 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-02-04 19:31:43,992 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-02-04 19:31:43,992 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-02-04 19:31:43,992 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-02-04 19:31:43,993 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-02-04 19:31:43,993 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-04 19:31:43,993 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-04 19:31:43,993 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf [2018-02-04 19:31:44,019 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-04 19:31:44,019 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-04 19:31:44,020 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-04 19:31:44,020 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-04 19:31:44,020 INFO L133 SettingsManager]: * Use SBE=true [2018-02-04 19:31:44,021 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-04 19:31:44,021 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-04 19:31:44,021 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-04 19:31:44,021 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-04 19:31:44,021 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-04 19:31:44,021 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-04 19:31:44,022 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-04 19:31:44,022 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-04 19:31:44,022 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-04 19:31:44,022 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-04 19:31:44,022 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-04 19:31:44,022 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-04 19:31:44,023 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-04 19:31:44,023 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-04 19:31:44,023 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 19:31:44,023 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-04 19:31:44,023 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-02-04 19:31:44,023 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-02-04 19:31:44,023 INFO L133 SettingsManager]: * Trace refinement strategy=SMTINTERPOL [2018-02-04 19:31:44,049 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-04 19:31:44,099 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-04 19:31:44,101 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-04 19:31:44,103 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-04 19:31:44,103 INFO L276 PluginConnector]: CDTParser initialized [2018-02-04 19:31:44,103 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_3_true-valid-memsafety_true-termination.i [2018-02-04 19:31:44,261 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-04 19:31:44,262 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-04 19:31:44,263 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-04 19:31:44,263 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-04 19:31:44,267 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-04 19:31:44,268 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 07:31:44" (1/1) ... [2018-02-04 19:31:44,270 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4b089594 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:31:44, skipping insertion in model container [2018-02-04 19:31:44,270 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 07:31:44" (1/1) ... [2018-02-04 19:31:44,280 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 19:31:44,314 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 19:31:44,413 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 19:31:44,435 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 19:31:44,445 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:31:44 WrapperNode [2018-02-04 19:31:44,445 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-04 19:31:44,446 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-04 19:31:44,446 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-04 19:31:44,446 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-04 19:31:44,454 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:31:44" (1/1) ... [2018-02-04 19:31:44,454 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:31:44" (1/1) ... [2018-02-04 19:31:44,463 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:31:44" (1/1) ... [2018-02-04 19:31:44,464 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:31:44" (1/1) ... [2018-02-04 19:31:44,471 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:31:44" (1/1) ... [2018-02-04 19:31:44,474 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:31:44" (1/1) ... [2018-02-04 19:31:44,476 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:31:44" (1/1) ... [2018-02-04 19:31:44,478 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-04 19:31:44,479 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-04 19:31:44,479 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-04 19:31:44,479 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-04 19:31:44,480 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:31:44" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 19:31:44,516 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-04 19:31:44,516 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-04 19:31:44,516 INFO L136 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2018-02-04 19:31:44,516 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-02-04 19:31:44,516 INFO L136 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-02-04 19:31:44,516 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_atomic_add_return [2018-02-04 19:31:44,516 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_atomic_sub_return [2018-02-04 19:31:44,516 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_sub [2018-02-04 19:31:44,516 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_init [2018-02-04 19:31:44,516 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_get [2018-02-04 19:31:44,517 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_put [2018-02-04 19:31:44,517 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-02-04 19:31:44,517 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-02-04 19:31:44,517 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_put [2018-02-04 19:31:44,517 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_get [2018-02-04 19:31:44,517 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init_internal [2018-02-04 19:31:44,517 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init [2018-02-04 19:31:44,517 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_create [2018-02-04 19:31:44,517 INFO L136 BoogieDeclarations]: Found implementation of procedure f_22_get [2018-02-04 19:31:44,517 INFO L136 BoogieDeclarations]: Found implementation of procedure f_22_put [2018-02-04 19:31:44,517 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-02-04 19:31:44,517 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-04 19:31:44,517 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-02-04 19:31:44,518 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-02-04 19:31:44,518 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-04 19:31:44,518 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-04 19:31:44,518 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-04 19:31:44,518 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-04 19:31:44,518 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-04 19:31:44,518 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-02-04 19:31:44,518 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-02-04 19:31:44,518 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-02-04 19:31:44,518 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-02-04 19:31:44,518 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-04 19:31:44,518 INFO L128 BoogieDeclarations]: Found specification of procedure memset [2018-02-04 19:31:44,518 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-02-04 19:31:44,519 INFO L128 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-02-04 19:31:44,519 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_atomic_add_return [2018-02-04 19:31:44,519 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_atomic_sub_return [2018-02-04 19:31:44,519 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_sub [2018-02-04 19:31:44,519 INFO L128 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2018-02-04 19:31:44,519 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_init [2018-02-04 19:31:44,519 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_get [2018-02-04 19:31:44,519 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_put [2018-02-04 19:31:44,519 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-02-04 19:31:44,519 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-02-04 19:31:44,519 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_put [2018-02-04 19:31:44,519 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_get [2018-02-04 19:31:44,519 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init_internal [2018-02-04 19:31:44,519 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init [2018-02-04 19:31:44,519 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_create [2018-02-04 19:31:44,520 INFO L128 BoogieDeclarations]: Found specification of procedure f_22_get [2018-02-04 19:31:44,520 INFO L128 BoogieDeclarations]: Found specification of procedure f_22_put [2018-02-04 19:31:44,520 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-02-04 19:31:44,520 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-04 19:31:44,520 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-04 19:31:44,520 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-04 19:31:44,705 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-02-04 19:31:44,841 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-04 19:31:44,842 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 07:31:44 BoogieIcfgContainer [2018-02-04 19:31:44,842 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-04 19:31:44,842 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-04 19:31:44,842 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-04 19:31:44,844 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-04 19:31:44,845 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 04.02 07:31:44" (1/3) ... [2018-02-04 19:31:44,845 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1478a71 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 07:31:44, skipping insertion in model container [2018-02-04 19:31:44,845 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:31:44" (2/3) ... [2018-02-04 19:31:44,845 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1478a71 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 07:31:44, skipping insertion in model container [2018-02-04 19:31:44,846 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 07:31:44" (3/3) ... [2018-02-04 19:31:44,847 INFO L107 eAbstractionObserver]: Analyzing ICFG memleaks_test22_3_true-valid-memsafety_true-termination.i [2018-02-04 19:31:44,853 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-02-04 19:31:44,865 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2018-02-04 19:31:44,896 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-04 19:31:44,896 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-04 19:31:44,896 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-02-04 19:31:44,896 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-02-04 19:31:44,896 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-04 19:31:44,897 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-04 19:31:44,897 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-04 19:31:44,897 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-04 19:31:44,897 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-04 19:31:44,910 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states. [2018-02-04 19:31:44,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-02-04 19:31:44,918 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:44,919 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:44,919 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:44,923 INFO L82 PathProgramCache]: Analyzing trace with hash 1245228870, now seen corresponding path program 1 times [2018-02-04 19:31:44,925 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:44,925 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:44,974 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:44,974 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:44,974 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:45,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:45,019 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:45,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:45,179 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:45,179 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 19:31:45,181 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 19:31:45,192 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 19:31:45,193 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 19:31:45,195 INFO L87 Difference]: Start difference. First operand 151 states. Second operand 5 states. [2018-02-04 19:31:45,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:45,246 INFO L93 Difference]: Finished difference Result 157 states and 166 transitions. [2018-02-04 19:31:45,247 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 19:31:45,247 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-02-04 19:31:45,248 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:45,255 INFO L225 Difference]: With dead ends: 157 [2018-02-04 19:31:45,255 INFO L226 Difference]: Without dead ends: 154 [2018-02-04 19:31:45,257 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 19:31:45,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2018-02-04 19:31:45,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 152. [2018-02-04 19:31:45,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152 states. [2018-02-04 19:31:45,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 161 transitions. [2018-02-04 19:31:45,292 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 161 transitions. Word has length 17 [2018-02-04 19:31:45,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:45,292 INFO L432 AbstractCegarLoop]: Abstraction has 152 states and 161 transitions. [2018-02-04 19:31:45,292 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 19:31:45,293 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 161 transitions. [2018-02-04 19:31:45,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-02-04 19:31:45,293 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:45,293 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:45,293 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:45,293 INFO L82 PathProgramCache]: Analyzing trace with hash -1572748952, now seen corresponding path program 1 times [2018-02-04 19:31:45,293 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:45,293 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:45,294 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:45,295 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:45,295 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:45,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:45,309 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:45,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:45,353 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:45,353 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 19:31:45,354 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 19:31:45,355 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 19:31:45,355 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 19:31:45,355 INFO L87 Difference]: Start difference. First operand 152 states and 161 transitions. Second operand 6 states. [2018-02-04 19:31:45,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:45,493 INFO L93 Difference]: Finished difference Result 153 states and 162 transitions. [2018-02-04 19:31:45,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 19:31:45,493 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 19 [2018-02-04 19:31:45,494 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:45,494 INFO L225 Difference]: With dead ends: 153 [2018-02-04 19:31:45,495 INFO L226 Difference]: Without dead ends: 153 [2018-02-04 19:31:45,495 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 19:31:45,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2018-02-04 19:31:45,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 151. [2018-02-04 19:31:45,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-02-04 19:31:45,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 160 transitions. [2018-02-04 19:31:45,501 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 160 transitions. Word has length 19 [2018-02-04 19:31:45,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:45,501 INFO L432 AbstractCegarLoop]: Abstraction has 151 states and 160 transitions. [2018-02-04 19:31:45,501 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 19:31:45,501 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 160 transitions. [2018-02-04 19:31:45,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-02-04 19:31:45,502 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:45,502 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:45,502 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:45,502 INFO L82 PathProgramCache]: Analyzing trace with hash -1572748951, now seen corresponding path program 1 times [2018-02-04 19:31:45,502 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:45,502 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:45,503 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:45,503 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:45,503 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:45,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:45,516 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:45,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:45,681 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:45,681 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 19:31:45,682 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 19:31:45,682 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 19:31:45,682 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 19:31:45,682 INFO L87 Difference]: Start difference. First operand 151 states and 160 transitions. Second operand 7 states. [2018-02-04 19:31:45,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:45,866 INFO L93 Difference]: Finished difference Result 152 states and 161 transitions. [2018-02-04 19:31:45,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 19:31:45,868 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 19 [2018-02-04 19:31:45,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:45,870 INFO L225 Difference]: With dead ends: 152 [2018-02-04 19:31:45,870 INFO L226 Difference]: Without dead ends: 152 [2018-02-04 19:31:45,870 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-02-04 19:31:45,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-02-04 19:31:45,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 150. [2018-02-04 19:31:45,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-02-04 19:31:45,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 159 transitions. [2018-02-04 19:31:45,879 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 159 transitions. Word has length 19 [2018-02-04 19:31:45,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:45,879 INFO L432 AbstractCegarLoop]: Abstraction has 150 states and 159 transitions. [2018-02-04 19:31:45,879 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 19:31:45,879 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 159 transitions. [2018-02-04 19:31:45,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-04 19:31:45,880 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:45,880 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:45,880 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:45,881 INFO L82 PathProgramCache]: Analyzing trace with hash -336004596, now seen corresponding path program 1 times [2018-02-04 19:31:45,881 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:45,881 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:45,882 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:45,882 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:45,882 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:45,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:45,897 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:45,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:45,989 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:45,989 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-04 19:31:45,990 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-04 19:31:45,990 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-04 19:31:45,990 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-02-04 19:31:45,990 INFO L87 Difference]: Start difference. First operand 150 states and 159 transitions. Second operand 9 states. [2018-02-04 19:31:46,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:46,056 INFO L93 Difference]: Finished difference Result 171 states and 182 transitions. [2018-02-04 19:31:46,056 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 19:31:46,056 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 29 [2018-02-04 19:31:46,056 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:46,058 INFO L225 Difference]: With dead ends: 171 [2018-02-04 19:31:46,058 INFO L226 Difference]: Without dead ends: 171 [2018-02-04 19:31:46,058 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-02-04 19:31:46,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-02-04 19:31:46,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 164. [2018-02-04 19:31:46,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 164 states. [2018-02-04 19:31:46,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 173 transitions. [2018-02-04 19:31:46,069 INFO L78 Accepts]: Start accepts. Automaton has 164 states and 173 transitions. Word has length 29 [2018-02-04 19:31:46,069 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:46,069 INFO L432 AbstractCegarLoop]: Abstraction has 164 states and 173 transitions. [2018-02-04 19:31:46,069 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-04 19:31:46,069 INFO L276 IsEmpty]: Start isEmpty. Operand 164 states and 173 transitions. [2018-02-04 19:31:46,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-02-04 19:31:46,070 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:46,070 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:46,070 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:46,071 INFO L82 PathProgramCache]: Analyzing trace with hash 610577100, now seen corresponding path program 1 times [2018-02-04 19:31:46,071 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:46,071 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:46,072 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:46,072 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:46,072 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:46,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:46,086 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:46,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:46,147 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:46,147 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-04 19:31:46,148 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 19:31:46,148 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 19:31:46,148 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-02-04 19:31:46,148 INFO L87 Difference]: Start difference. First operand 164 states and 173 transitions. Second operand 10 states. [2018-02-04 19:31:46,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:46,324 INFO L93 Difference]: Finished difference Result 163 states and 172 transitions. [2018-02-04 19:31:46,325 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 19:31:46,325 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 34 [2018-02-04 19:31:46,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:46,326 INFO L225 Difference]: With dead ends: 163 [2018-02-04 19:31:46,326 INFO L226 Difference]: Without dead ends: 163 [2018-02-04 19:31:46,326 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-04 19:31:46,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-02-04 19:31:46,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 163. [2018-02-04 19:31:46,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 163 states. [2018-02-04 19:31:46,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 172 transitions. [2018-02-04 19:31:46,333 INFO L78 Accepts]: Start accepts. Automaton has 163 states and 172 transitions. Word has length 34 [2018-02-04 19:31:46,333 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:46,333 INFO L432 AbstractCegarLoop]: Abstraction has 163 states and 172 transitions. [2018-02-04 19:31:46,333 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 19:31:46,333 INFO L276 IsEmpty]: Start isEmpty. Operand 163 states and 172 transitions. [2018-02-04 19:31:46,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-02-04 19:31:46,334 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:46,334 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:46,335 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:46,335 INFO L82 PathProgramCache]: Analyzing trace with hash 610577101, now seen corresponding path program 1 times [2018-02-04 19:31:46,335 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:46,335 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:46,336 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:46,336 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:46,336 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:46,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:46,350 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:46,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:46,373 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:46,373 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-04 19:31:46,373 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-04 19:31:46,373 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-04 19:31:46,374 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-04 19:31:46,374 INFO L87 Difference]: Start difference. First operand 163 states and 172 transitions. Second operand 4 states. [2018-02-04 19:31:46,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:46,386 INFO L93 Difference]: Finished difference Result 166 states and 175 transitions. [2018-02-04 19:31:46,387 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-04 19:31:46,387 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 34 [2018-02-04 19:31:46,387 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:46,388 INFO L225 Difference]: With dead ends: 166 [2018-02-04 19:31:46,388 INFO L226 Difference]: Without dead ends: 164 [2018-02-04 19:31:46,388 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-04 19:31:46,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164 states. [2018-02-04 19:31:46,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164 to 164. [2018-02-04 19:31:46,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 164 states. [2018-02-04 19:31:46,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 173 transitions. [2018-02-04 19:31:46,394 INFO L78 Accepts]: Start accepts. Automaton has 164 states and 173 transitions. Word has length 34 [2018-02-04 19:31:46,395 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:46,395 INFO L432 AbstractCegarLoop]: Abstraction has 164 states and 173 transitions. [2018-02-04 19:31:46,395 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-04 19:31:46,395 INFO L276 IsEmpty]: Start isEmpty. Operand 164 states and 173 transitions. [2018-02-04 19:31:46,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-02-04 19:31:46,396 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:46,396 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:46,396 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:46,396 INFO L82 PathProgramCache]: Analyzing trace with hash -838244594, now seen corresponding path program 1 times [2018-02-04 19:31:46,396 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:46,397 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:46,398 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:46,398 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:46,398 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:46,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:46,412 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:46,439 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:46,439 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:31:46,439 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:31:46,440 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:46,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:46,469 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:31:46,495 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:46,495 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:31:46,495 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 6 [2018-02-04 19:31:46,496 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 19:31:46,496 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 19:31:46,496 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-02-04 19:31:46,496 INFO L87 Difference]: Start difference. First operand 164 states and 173 transitions. Second operand 6 states. [2018-02-04 19:31:46,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:46,516 INFO L93 Difference]: Finished difference Result 167 states and 176 transitions. [2018-02-04 19:31:46,517 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 19:31:46,517 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35 [2018-02-04 19:31:46,517 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:46,518 INFO L225 Difference]: With dead ends: 167 [2018-02-04 19:31:46,518 INFO L226 Difference]: Without dead ends: 165 [2018-02-04 19:31:46,518 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 35 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-02-04 19:31:46,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-02-04 19:31:46,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 165. [2018-02-04 19:31:46,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-02-04 19:31:46,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 174 transitions. [2018-02-04 19:31:46,524 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 174 transitions. Word has length 35 [2018-02-04 19:31:46,524 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:46,524 INFO L432 AbstractCegarLoop]: Abstraction has 165 states and 174 transitions. [2018-02-04 19:31:46,524 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 19:31:46,525 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 174 transitions. [2018-02-04 19:31:46,525 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-04 19:31:46,525 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:46,525 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:46,526 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:46,526 INFO L82 PathProgramCache]: Analyzing trace with hash 1492923117, now seen corresponding path program 2 times [2018-02-04 19:31:46,526 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:46,526 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:46,527 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:46,527 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:46,527 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:46,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:46,539 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:46,568 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:46,568 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:31:46,569 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:31:46,570 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 19:31:46,592 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 19:31:46,593 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:31:46,596 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:31:46,626 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 13 [2018-02-04 19:31:46,628 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:31:46,643 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 19:31:46,644 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:31:46,654 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 19:31:46,654 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:32, output treesize:30 [2018-02-04 19:31:46,869 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 19:31:46,869 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:31:46,870 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [15] imperfect sequences [6] total 20 [2018-02-04 19:31:46,870 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-04 19:31:46,870 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-04 19:31:46,871 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=329, Unknown=0, NotChecked=0, Total=380 [2018-02-04 19:31:46,871 INFO L87 Difference]: Start difference. First operand 165 states and 174 transitions. Second operand 20 states. [2018-02-04 19:31:47,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:47,519 INFO L93 Difference]: Finished difference Result 243 states and 255 transitions. [2018-02-04 19:31:47,519 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-04 19:31:47,519 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 36 [2018-02-04 19:31:47,520 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:47,520 INFO L225 Difference]: With dead ends: 243 [2018-02-04 19:31:47,520 INFO L226 Difference]: Without dead ends: 241 [2018-02-04 19:31:47,521 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 102 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=104, Invalid=708, Unknown=0, NotChecked=0, Total=812 [2018-02-04 19:31:47,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 241 states. [2018-02-04 19:31:47,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 241 to 165. [2018-02-04 19:31:47,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-02-04 19:31:47,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 174 transitions. [2018-02-04 19:31:47,526 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 174 transitions. Word has length 36 [2018-02-04 19:31:47,526 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:47,526 INFO L432 AbstractCegarLoop]: Abstraction has 165 states and 174 transitions. [2018-02-04 19:31:47,526 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-04 19:31:47,526 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 174 transitions. [2018-02-04 19:31:47,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-04 19:31:47,527 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:47,528 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:47,528 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:47,528 INFO L82 PathProgramCache]: Analyzing trace with hash 278126369, now seen corresponding path program 1 times [2018-02-04 19:31:47,528 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:47,528 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:47,529 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:47,530 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:31:47,530 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:47,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:47,538 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:47,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:47,614 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:47,615 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-04 19:31:47,615 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-04 19:31:47,615 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-04 19:31:47,615 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-02-04 19:31:47,615 INFO L87 Difference]: Start difference. First operand 165 states and 174 transitions. Second operand 9 states. [2018-02-04 19:31:47,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:47,682 INFO L93 Difference]: Finished difference Result 179 states and 190 transitions. [2018-02-04 19:31:47,683 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 19:31:47,683 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 42 [2018-02-04 19:31:47,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:47,684 INFO L225 Difference]: With dead ends: 179 [2018-02-04 19:31:47,684 INFO L226 Difference]: Without dead ends: 179 [2018-02-04 19:31:47,684 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-02-04 19:31:47,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-02-04 19:31:47,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 175. [2018-02-04 19:31:47,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175 states. [2018-02-04 19:31:47,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 185 transitions. [2018-02-04 19:31:47,687 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 185 transitions. Word has length 42 [2018-02-04 19:31:47,687 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:47,688 INFO L432 AbstractCegarLoop]: Abstraction has 175 states and 185 transitions. [2018-02-04 19:31:47,688 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-04 19:31:47,688 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 185 transitions. [2018-02-04 19:31:47,688 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-04 19:31:47,688 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:47,688 INFO L351 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:47,688 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:47,689 INFO L82 PathProgramCache]: Analyzing trace with hash 2131974142, now seen corresponding path program 1 times [2018-02-04 19:31:47,689 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:47,689 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:47,689 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:47,690 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:47,690 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:47,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:47,700 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:47,753 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 19:31:47,753 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:47,754 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-04 19:31:47,754 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 19:31:47,754 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 19:31:47,754 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-02-04 19:31:47,754 INFO L87 Difference]: Start difference. First operand 175 states and 185 transitions. Second operand 10 states. [2018-02-04 19:31:47,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:47,953 INFO L93 Difference]: Finished difference Result 173 states and 183 transitions. [2018-02-04 19:31:47,953 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 19:31:47,954 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-02-04 19:31:47,954 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:47,955 INFO L225 Difference]: With dead ends: 173 [2018-02-04 19:31:47,955 INFO L226 Difference]: Without dead ends: 173 [2018-02-04 19:31:47,955 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-04 19:31:47,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states. [2018-02-04 19:31:47,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 173. [2018-02-04 19:31:47,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-02-04 19:31:47,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 183 transitions. [2018-02-04 19:31:47,960 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 183 transitions. Word has length 42 [2018-02-04 19:31:47,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:47,961 INFO L432 AbstractCegarLoop]: Abstraction has 173 states and 183 transitions. [2018-02-04 19:31:47,961 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 19:31:47,961 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 183 transitions. [2018-02-04 19:31:47,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-04 19:31:47,962 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:47,962 INFO L351 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:47,962 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:47,962 INFO L82 PathProgramCache]: Analyzing trace with hash 2131974143, now seen corresponding path program 1 times [2018-02-04 19:31:47,962 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:47,962 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:47,963 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:47,964 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:47,964 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:47,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:47,976 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:48,009 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:48,009 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:31:48,009 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:31:48,010 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:48,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:48,040 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:31:48,051 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:48,052 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:31:48,052 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 8 [2018-02-04 19:31:48,052 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 19:31:48,052 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 19:31:48,052 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-02-04 19:31:48,052 INFO L87 Difference]: Start difference. First operand 173 states and 183 transitions. Second operand 8 states. [2018-02-04 19:31:48,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:48,066 INFO L93 Difference]: Finished difference Result 176 states and 186 transitions. [2018-02-04 19:31:48,067 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 19:31:48,067 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 42 [2018-02-04 19:31:48,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:48,067 INFO L225 Difference]: With dead ends: 176 [2018-02-04 19:31:48,067 INFO L226 Difference]: Without dead ends: 174 [2018-02-04 19:31:48,068 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 42 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-02-04 19:31:48,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-02-04 19:31:48,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 174. [2018-02-04 19:31:48,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-02-04 19:31:48,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 184 transitions. [2018-02-04 19:31:48,072 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 184 transitions. Word has length 42 [2018-02-04 19:31:48,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:48,072 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 184 transitions. [2018-02-04 19:31:48,072 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 19:31:48,072 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 184 transitions. [2018-02-04 19:31:48,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-02-04 19:31:48,073 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:48,073 INFO L351 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:48,073 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:48,073 INFO L82 PathProgramCache]: Analyzing trace with hash 731661120, now seen corresponding path program 2 times [2018-02-04 19:31:48,073 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:48,073 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:48,074 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:48,074 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:48,074 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:48,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:48,083 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:48,112 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:48,112 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:31:48,112 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:31:48,113 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 19:31:48,126 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 19:31:48,126 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:31:48,129 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:31:48,139 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 19:31:48,139 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:31:48,150 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-04 19:31:48,151 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:31:48,164 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 19:31:48,165 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:38, output treesize:36 [2018-02-04 19:31:48,405 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 19:31:48,406 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:31:48,406 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [15] imperfect sequences [8] total 22 [2018-02-04 19:31:48,406 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-04 19:31:48,406 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-04 19:31:48,407 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=400, Unknown=0, NotChecked=0, Total=462 [2018-02-04 19:31:48,407 INFO L87 Difference]: Start difference. First operand 174 states and 184 transitions. Second operand 22 states. [2018-02-04 19:31:49,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:49,004 INFO L93 Difference]: Finished difference Result 203 states and 213 transitions. [2018-02-04 19:31:49,004 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-04 19:31:49,004 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 43 [2018-02-04 19:31:49,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:49,005 INFO L225 Difference]: With dead ends: 203 [2018-02-04 19:31:49,005 INFO L226 Difference]: Without dead ends: 201 [2018-02-04 19:31:49,005 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 28 SyntacticMatches, 2 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 170 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=139, Invalid=917, Unknown=0, NotChecked=0, Total=1056 [2018-02-04 19:31:49,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2018-02-04 19:31:49,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 173. [2018-02-04 19:31:49,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-02-04 19:31:49,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 183 transitions. [2018-02-04 19:31:49,009 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 183 transitions. Word has length 43 [2018-02-04 19:31:49,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:49,009 INFO L432 AbstractCegarLoop]: Abstraction has 173 states and 183 transitions. [2018-02-04 19:31:49,009 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-04 19:31:49,009 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 183 transitions. [2018-02-04 19:31:49,009 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-04 19:31:49,009 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:49,009 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:49,009 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:49,010 INFO L82 PathProgramCache]: Analyzing trace with hash 689381786, now seen corresponding path program 1 times [2018-02-04 19:31:49,010 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:49,010 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:49,011 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:49,011 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:31:49,011 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:49,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:49,018 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:49,042 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 19:31:49,043 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:49,043 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 19:31:49,043 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 19:31:49,043 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 19:31:49,043 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 19:31:49,044 INFO L87 Difference]: Start difference. First operand 173 states and 183 transitions. Second operand 3 states. [2018-02-04 19:31:49,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:49,101 INFO L93 Difference]: Finished difference Result 192 states and 205 transitions. [2018-02-04 19:31:49,101 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 19:31:49,101 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 47 [2018-02-04 19:31:49,101 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:49,102 INFO L225 Difference]: With dead ends: 192 [2018-02-04 19:31:49,102 INFO L226 Difference]: Without dead ends: 179 [2018-02-04 19:31:49,102 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 19:31:49,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-02-04 19:31:49,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 169. [2018-02-04 19:31:49,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 169 states. [2018-02-04 19:31:49,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 178 transitions. [2018-02-04 19:31:49,108 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 178 transitions. Word has length 47 [2018-02-04 19:31:49,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:49,108 INFO L432 AbstractCegarLoop]: Abstraction has 169 states and 178 transitions. [2018-02-04 19:31:49,108 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 19:31:49,108 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 178 transitions. [2018-02-04 19:31:49,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-02-04 19:31:49,109 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:49,109 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:49,109 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:49,109 INFO L82 PathProgramCache]: Analyzing trace with hash 2000778853, now seen corresponding path program 1 times [2018-02-04 19:31:49,110 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:49,110 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:49,110 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:49,111 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:49,111 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:49,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:49,119 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:49,168 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-02-04 19:31:49,169 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:49,169 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-04 19:31:49,169 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 19:31:49,169 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 19:31:49,169 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-04 19:31:49,170 INFO L87 Difference]: Start difference. First operand 169 states and 178 transitions. Second operand 8 states. [2018-02-04 19:31:49,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:49,203 INFO L93 Difference]: Finished difference Result 147 states and 153 transitions. [2018-02-04 19:31:49,203 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 19:31:49,203 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 49 [2018-02-04 19:31:49,203 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:49,204 INFO L225 Difference]: With dead ends: 147 [2018-02-04 19:31:49,204 INFO L226 Difference]: Without dead ends: 145 [2018-02-04 19:31:49,204 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-02-04 19:31:49,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-02-04 19:31:49,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 145. [2018-02-04 19:31:49,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-02-04 19:31:49,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 151 transitions. [2018-02-04 19:31:49,208 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 151 transitions. Word has length 49 [2018-02-04 19:31:49,208 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:49,208 INFO L432 AbstractCegarLoop]: Abstraction has 145 states and 151 transitions. [2018-02-04 19:31:49,208 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 19:31:49,209 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 151 transitions. [2018-02-04 19:31:49,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-02-04 19:31:49,209 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:49,209 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:49,209 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:49,210 INFO L82 PathProgramCache]: Analyzing trace with hash 2066481475, now seen corresponding path program 1 times [2018-02-04 19:31:49,210 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:49,210 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:49,210 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:49,211 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:49,211 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:49,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:49,219 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:49,271 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-02-04 19:31:49,271 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:49,271 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-02-04 19:31:49,272 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 19:31:49,272 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 19:31:49,272 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-02-04 19:31:49,272 INFO L87 Difference]: Start difference. First operand 145 states and 151 transitions. Second operand 10 states. [2018-02-04 19:31:49,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:49,317 INFO L93 Difference]: Finished difference Result 149 states and 154 transitions. [2018-02-04 19:31:49,319 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 19:31:49,319 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 54 [2018-02-04 19:31:49,319 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:49,320 INFO L225 Difference]: With dead ends: 149 [2018-02-04 19:31:49,320 INFO L226 Difference]: Without dead ends: 145 [2018-02-04 19:31:49,320 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-04 19:31:49,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-02-04 19:31:49,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 145. [2018-02-04 19:31:49,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-02-04 19:31:49,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 150 transitions. [2018-02-04 19:31:49,323 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 150 transitions. Word has length 54 [2018-02-04 19:31:49,324 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:49,324 INFO L432 AbstractCegarLoop]: Abstraction has 145 states and 150 transitions. [2018-02-04 19:31:49,324 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 19:31:49,324 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 150 transitions. [2018-02-04 19:31:49,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-02-04 19:31:49,325 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:49,325 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:49,325 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:49,325 INFO L82 PathProgramCache]: Analyzing trace with hash 1850180082, now seen corresponding path program 1 times [2018-02-04 19:31:49,325 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:49,325 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:49,326 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:49,326 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:49,326 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:49,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:49,337 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:49,466 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-02-04 19:31:49,466 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:49,466 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [14] imperfect sequences [] total 14 [2018-02-04 19:31:49,466 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-04 19:31:49,467 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-04 19:31:49,467 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=183, Unknown=0, NotChecked=0, Total=210 [2018-02-04 19:31:49,467 INFO L87 Difference]: Start difference. First operand 145 states and 150 transitions. Second operand 15 states. [2018-02-04 19:31:49,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:49,684 INFO L93 Difference]: Finished difference Result 143 states and 148 transitions. [2018-02-04 19:31:49,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-04 19:31:49,685 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 65 [2018-02-04 19:31:49,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:49,685 INFO L225 Difference]: With dead ends: 143 [2018-02-04 19:31:49,685 INFO L226 Difference]: Without dead ends: 143 [2018-02-04 19:31:49,686 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=333, Unknown=0, NotChecked=0, Total=380 [2018-02-04 19:31:49,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-02-04 19:31:49,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 143. [2018-02-04 19:31:49,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-02-04 19:31:49,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 148 transitions. [2018-02-04 19:31:49,689 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 148 transitions. Word has length 65 [2018-02-04 19:31:49,689 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:49,689 INFO L432 AbstractCegarLoop]: Abstraction has 143 states and 148 transitions. [2018-02-04 19:31:49,689 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-04 19:31:49,689 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 148 transitions. [2018-02-04 19:31:49,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-02-04 19:31:49,690 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:49,690 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:49,690 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:49,690 INFO L82 PathProgramCache]: Analyzing trace with hash 1850180083, now seen corresponding path program 1 times [2018-02-04 19:31:49,690 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:49,691 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:49,691 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:49,692 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:49,692 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:49,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:49,705 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:49,767 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:49,767 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:31:49,767 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:31:49,768 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:49,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:49,789 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:31:49,806 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:49,806 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:31:49,806 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-02-04 19:31:49,807 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 19:31:49,807 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 19:31:49,807 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-02-04 19:31:49,807 INFO L87 Difference]: Start difference. First operand 143 states and 148 transitions. Second operand 10 states. [2018-02-04 19:31:49,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:49,832 INFO L93 Difference]: Finished difference Result 146 states and 151 transitions. [2018-02-04 19:31:49,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 19:31:49,833 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 65 [2018-02-04 19:31:49,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:49,834 INFO L225 Difference]: With dead ends: 146 [2018-02-04 19:31:49,834 INFO L226 Difference]: Without dead ends: 144 [2018-02-04 19:31:49,834 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=42, Invalid=68, Unknown=0, NotChecked=0, Total=110 [2018-02-04 19:31:49,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-02-04 19:31:49,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 144. [2018-02-04 19:31:49,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-02-04 19:31:49,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 149 transitions. [2018-02-04 19:31:49,837 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 149 transitions. Word has length 65 [2018-02-04 19:31:49,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:49,838 INFO L432 AbstractCegarLoop]: Abstraction has 144 states and 149 transitions. [2018-02-04 19:31:49,838 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 19:31:49,838 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 149 transitions. [2018-02-04 19:31:49,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-02-04 19:31:49,839 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:49,839 INFO L351 BasicCegarLoop]: trace histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:49,839 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:49,839 INFO L82 PathProgramCache]: Analyzing trace with hash -1823769198, now seen corresponding path program 2 times [2018-02-04 19:31:49,839 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:49,839 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:49,840 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:49,840 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:49,840 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:49,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:49,853 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:49,905 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:49,905 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:31:49,906 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:31:49,908 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 19:31:49,927 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 19:31:49,927 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:31:49,932 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:31:49,944 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-04 19:31:49,945 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:31:49,960 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 19:31:49,960 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:31:49,973 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 19:31:49,974 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:38, output treesize:36 [2018-02-04 19:31:50,405 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-02-04 19:31:50,405 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:31:50,405 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [20] imperfect sequences [10] total 29 [2018-02-04 19:31:50,406 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-02-04 19:31:50,406 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-02-04 19:31:50,406 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=720, Unknown=0, NotChecked=0, Total=812 [2018-02-04 19:31:50,406 INFO L87 Difference]: Start difference. First operand 144 states and 149 transitions. Second operand 29 states. [2018-02-04 19:31:51,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:51,335 INFO L93 Difference]: Finished difference Result 145 states and 150 transitions. [2018-02-04 19:31:51,335 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-04 19:31:51,335 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 66 [2018-02-04 19:31:51,335 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:51,336 INFO L225 Difference]: With dead ends: 145 [2018-02-04 19:31:51,336 INFO L226 Difference]: Without dead ends: 143 [2018-02-04 19:31:51,336 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 90 GetRequests, 47 SyntacticMatches, 1 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 295 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=212, Invalid=1680, Unknown=0, NotChecked=0, Total=1892 [2018-02-04 19:31:51,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-02-04 19:31:51,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 143. [2018-02-04 19:31:51,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-02-04 19:31:51,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 148 transitions. [2018-02-04 19:31:51,339 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 148 transitions. Word has length 66 [2018-02-04 19:31:51,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:51,340 INFO L432 AbstractCegarLoop]: Abstraction has 143 states and 148 transitions. [2018-02-04 19:31:51,340 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-02-04 19:31:51,340 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 148 transitions. [2018-02-04 19:31:51,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-02-04 19:31:51,340 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:51,341 INFO L351 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:51,341 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:51,341 INFO L82 PathProgramCache]: Analyzing trace with hash -920668901, now seen corresponding path program 1 times [2018-02-04 19:31:51,341 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:51,341 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:51,342 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:51,342 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:31:51,342 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:51,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:51,356 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:51,455 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-02-04 19:31:51,455 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:51,455 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2018-02-04 19:31:51,456 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-04 19:31:51,456 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-04 19:31:51,456 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=133, Unknown=0, NotChecked=0, Total=156 [2018-02-04 19:31:51,456 INFO L87 Difference]: Start difference. First operand 143 states and 148 transitions. Second operand 13 states. [2018-02-04 19:31:51,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:51,537 INFO L93 Difference]: Finished difference Result 149 states and 153 transitions. [2018-02-04 19:31:51,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-02-04 19:31:51,538 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 80 [2018-02-04 19:31:51,538 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:51,539 INFO L225 Difference]: With dead ends: 149 [2018-02-04 19:31:51,539 INFO L226 Difference]: Without dead ends: 143 [2018-02-04 19:31:51,539 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=233, Unknown=0, NotChecked=0, Total=272 [2018-02-04 19:31:51,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-02-04 19:31:51,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 143. [2018-02-04 19:31:51,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-02-04 19:31:51,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 147 transitions. [2018-02-04 19:31:51,543 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 147 transitions. Word has length 80 [2018-02-04 19:31:51,543 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:51,543 INFO L432 AbstractCegarLoop]: Abstraction has 143 states and 147 transitions. [2018-02-04 19:31:51,543 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-04 19:31:51,543 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 147 transitions. [2018-02-04 19:31:51,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-02-04 19:31:51,544 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:51,544 INFO L351 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:51,544 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:51,544 INFO L82 PathProgramCache]: Analyzing trace with hash -773057741, now seen corresponding path program 1 times [2018-02-04 19:31:51,544 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:51,544 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:51,545 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:51,545 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:51,545 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:51,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:51,562 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:51,760 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-02-04 19:31:51,760 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:51,760 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [] total 21 [2018-02-04 19:31:51,761 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-04 19:31:51,761 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-04 19:31:51,761 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=419, Unknown=0, NotChecked=0, Total=462 [2018-02-04 19:31:51,761 INFO L87 Difference]: Start difference. First operand 143 states and 147 transitions. Second operand 22 states. [2018-02-04 19:31:52,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:52,073 INFO L93 Difference]: Finished difference Result 170 states and 179 transitions. [2018-02-04 19:31:52,073 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-02-04 19:31:52,073 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 93 [2018-02-04 19:31:52,073 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:52,074 INFO L225 Difference]: With dead ends: 170 [2018-02-04 19:31:52,074 INFO L226 Difference]: Without dead ends: 170 [2018-02-04 19:31:52,074 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 65 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=75, Invalid=795, Unknown=0, NotChecked=0, Total=870 [2018-02-04 19:31:52,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2018-02-04 19:31:52,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 165. [2018-02-04 19:31:52,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-02-04 19:31:52,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 175 transitions. [2018-02-04 19:31:52,078 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 175 transitions. Word has length 93 [2018-02-04 19:31:52,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:52,079 INFO L432 AbstractCegarLoop]: Abstraction has 165 states and 175 transitions. [2018-02-04 19:31:52,079 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-04 19:31:52,079 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 175 transitions. [2018-02-04 19:31:52,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-02-04 19:31:52,080 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:52,080 INFO L351 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:52,080 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:52,080 INFO L82 PathProgramCache]: Analyzing trace with hash -773057740, now seen corresponding path program 1 times [2018-02-04 19:31:52,080 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:52,080 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:52,081 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:52,081 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:52,081 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:52,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:52,094 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:52,150 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:52,150 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:31:52,150 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:31:52,151 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:52,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:52,182 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:31:52,214 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:52,214 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:31:52,214 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 12 [2018-02-04 19:31:52,215 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-04 19:31:52,215 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-04 19:31:52,215 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=75, Unknown=0, NotChecked=0, Total=132 [2018-02-04 19:31:52,215 INFO L87 Difference]: Start difference. First operand 165 states and 175 transitions. Second operand 12 states. [2018-02-04 19:31:52,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:52,237 INFO L93 Difference]: Finished difference Result 168 states and 178 transitions. [2018-02-04 19:31:52,238 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 19:31:52,238 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 93 [2018-02-04 19:31:52,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:52,239 INFO L225 Difference]: With dead ends: 168 [2018-02-04 19:31:52,239 INFO L226 Difference]: Without dead ends: 166 [2018-02-04 19:31:52,239 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 93 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=61, Invalid=95, Unknown=0, NotChecked=0, Total=156 [2018-02-04 19:31:52,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states. [2018-02-04 19:31:52,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 166. [2018-02-04 19:31:52,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-02-04 19:31:52,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 176 transitions. [2018-02-04 19:31:52,243 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 176 transitions. Word has length 93 [2018-02-04 19:31:52,243 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:52,243 INFO L432 AbstractCegarLoop]: Abstraction has 166 states and 176 transitions. [2018-02-04 19:31:52,243 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-04 19:31:52,244 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 176 transitions. [2018-02-04 19:31:52,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-02-04 19:31:52,244 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:52,244 INFO L351 BasicCegarLoop]: trace histogram [8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:52,245 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:52,245 INFO L82 PathProgramCache]: Analyzing trace with hash 572029523, now seen corresponding path program 2 times [2018-02-04 19:31:52,245 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:52,245 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:52,246 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:52,246 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:52,246 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:52,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:52,264 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:52,363 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:52,364 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:31:52,364 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:31:52,365 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 19:31:52,394 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 19:31:52,394 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:31:52,401 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:31:52,417 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 13 [2018-02-04 19:31:52,417 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:31:52,431 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 19:31:52,431 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:31:52,440 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 19:31:52,441 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:32, output treesize:30 [2018-02-04 19:31:52,942 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-02-04 19:31:52,943 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:31:52,943 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [22] imperfect sequences [12] total 33 [2018-02-04 19:31:52,943 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-02-04 19:31:52,943 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-02-04 19:31:52,943 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=117, Invalid=939, Unknown=0, NotChecked=0, Total=1056 [2018-02-04 19:31:52,943 INFO L87 Difference]: Start difference. First operand 166 states and 176 transitions. Second operand 33 states. [2018-02-04 19:31:53,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:53,885 INFO L93 Difference]: Finished difference Result 167 states and 175 transitions. [2018-02-04 19:31:53,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-02-04 19:31:53,886 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 94 [2018-02-04 19:31:53,886 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:53,887 INFO L225 Difference]: With dead ends: 167 [2018-02-04 19:31:53,887 INFO L226 Difference]: Without dead ends: 165 [2018-02-04 19:31:53,888 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 71 SyntacticMatches, 3 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 436 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=282, Invalid=2268, Unknown=0, NotChecked=0, Total=2550 [2018-02-04 19:31:53,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-02-04 19:31:53,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 165. [2018-02-04 19:31:53,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-02-04 19:31:53,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 173 transitions. [2018-02-04 19:31:53,892 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 173 transitions. Word has length 94 [2018-02-04 19:31:53,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:53,892 INFO L432 AbstractCegarLoop]: Abstraction has 165 states and 173 transitions. [2018-02-04 19:31:53,892 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-02-04 19:31:53,892 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 173 transitions. [2018-02-04 19:31:53,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-02-04 19:31:53,893 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:53,893 INFO L351 BasicCegarLoop]: trace histogram [9, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:53,893 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:53,893 INFO L82 PathProgramCache]: Analyzing trace with hash 700888674, now seen corresponding path program 1 times [2018-02-04 19:31:53,894 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:53,894 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:53,895 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:53,895 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:31:53,895 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:53,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:53,908 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:54,011 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-02-04 19:31:54,011 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:54,011 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2018-02-04 19:31:54,012 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-04 19:31:54,012 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-04 19:31:54,012 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=133, Unknown=0, NotChecked=0, Total=156 [2018-02-04 19:31:54,012 INFO L87 Difference]: Start difference. First operand 165 states and 173 transitions. Second operand 13 states. [2018-02-04 19:31:54,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:54,118 INFO L93 Difference]: Finished difference Result 169 states and 175 transitions. [2018-02-04 19:31:54,118 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-02-04 19:31:54,119 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 102 [2018-02-04 19:31:54,119 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:54,119 INFO L225 Difference]: With dead ends: 169 [2018-02-04 19:31:54,119 INFO L226 Difference]: Without dead ends: 163 [2018-02-04 19:31:54,119 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=233, Unknown=0, NotChecked=0, Total=272 [2018-02-04 19:31:54,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-02-04 19:31:54,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 163. [2018-02-04 19:31:54,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 163 states. [2018-02-04 19:31:54,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 169 transitions. [2018-02-04 19:31:54,121 INFO L78 Accepts]: Start accepts. Automaton has 163 states and 169 transitions. Word has length 102 [2018-02-04 19:31:54,122 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:54,122 INFO L432 AbstractCegarLoop]: Abstraction has 163 states and 169 transitions. [2018-02-04 19:31:54,122 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-04 19:31:54,122 INFO L276 IsEmpty]: Start isEmpty. Operand 163 states and 169 transitions. [2018-02-04 19:31:54,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-02-04 19:31:54,122 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:54,122 INFO L351 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:54,122 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:54,122 INFO L82 PathProgramCache]: Analyzing trace with hash 1156968532, now seen corresponding path program 1 times [2018-02-04 19:31:54,122 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:54,123 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:54,123 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:54,123 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:54,123 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:54,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:54,133 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:54,365 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-02-04 19:31:54,366 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:31:54,366 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [24] imperfect sequences [] total 24 [2018-02-04 19:31:54,366 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-02-04 19:31:54,366 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-02-04 19:31:54,366 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=553, Unknown=0, NotChecked=0, Total=600 [2018-02-04 19:31:54,367 INFO L87 Difference]: Start difference. First operand 163 states and 169 transitions. Second operand 25 states. [2018-02-04 19:31:54,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:54,921 INFO L93 Difference]: Finished difference Result 173 states and 182 transitions. [2018-02-04 19:31:54,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-02-04 19:31:54,922 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 109 [2018-02-04 19:31:54,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:54,922 INFO L225 Difference]: With dead ends: 173 [2018-02-04 19:31:54,922 INFO L226 Difference]: Without dead ends: 173 [2018-02-04 19:31:54,923 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 55 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=91, Invalid=1169, Unknown=0, NotChecked=0, Total=1260 [2018-02-04 19:31:54,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states. [2018-02-04 19:31:54,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 169. [2018-02-04 19:31:54,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 169 states. [2018-02-04 19:31:54,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 179 transitions. [2018-02-04 19:31:54,927 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 179 transitions. Word has length 109 [2018-02-04 19:31:54,927 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:54,927 INFO L432 AbstractCegarLoop]: Abstraction has 169 states and 179 transitions. [2018-02-04 19:31:54,927 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-02-04 19:31:54,927 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 179 transitions. [2018-02-04 19:31:54,928 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-02-04 19:31:54,928 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:54,928 INFO L351 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:54,928 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:54,928 INFO L82 PathProgramCache]: Analyzing trace with hash 1156968533, now seen corresponding path program 1 times [2018-02-04 19:31:54,928 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:54,928 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:54,929 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:54,929 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:54,929 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:54,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:54,946 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:55,048 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:55,049 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:31:55,049 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:31:55,050 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:55,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:55,103 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:31:55,116 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:55,116 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:31:55,117 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 14 [2018-02-04 19:31:55,117 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-04 19:31:55,117 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-04 19:31:55,117 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=102, Unknown=0, NotChecked=0, Total=182 [2018-02-04 19:31:55,117 INFO L87 Difference]: Start difference. First operand 169 states and 179 transitions. Second operand 14 states. [2018-02-04 19:31:55,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:55,144 INFO L93 Difference]: Finished difference Result 172 states and 182 transitions. [2018-02-04 19:31:55,144 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-02-04 19:31:55,144 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 109 [2018-02-04 19:31:55,144 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:55,145 INFO L225 Difference]: With dead ends: 172 [2018-02-04 19:31:55,145 INFO L226 Difference]: Without dead ends: 170 [2018-02-04 19:31:55,145 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 122 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=84, Invalid=126, Unknown=0, NotChecked=0, Total=210 [2018-02-04 19:31:55,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2018-02-04 19:31:55,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 170. [2018-02-04 19:31:55,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-02-04 19:31:55,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 180 transitions. [2018-02-04 19:31:55,149 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 180 transitions. Word has length 109 [2018-02-04 19:31:55,149 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:55,149 INFO L432 AbstractCegarLoop]: Abstraction has 170 states and 180 transitions. [2018-02-04 19:31:55,149 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-04 19:31:55,149 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 180 transitions. [2018-02-04 19:31:55,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-02-04 19:31:55,151 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:55,151 INFO L351 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:55,151 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:55,151 INFO L82 PathProgramCache]: Analyzing trace with hash -637126284, now seen corresponding path program 2 times [2018-02-04 19:31:55,151 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:55,151 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:55,152 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:55,152 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:55,152 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:55,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:55,169 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:55,267 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:55,267 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:31:55,267 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:31:55,268 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 19:31:55,298 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 19:31:55,298 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:31:55,305 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:31:55,326 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 13 [2018-02-04 19:31:55,327 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:31:55,337 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 19:31:55,338 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:31:55,347 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 19:31:55,347 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:32, output treesize:30 [2018-02-04 19:31:55,962 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-02-04 19:31:55,962 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:31:55,962 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [26] imperfect sequences [14] total 39 [2018-02-04 19:31:55,962 INFO L409 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-02-04 19:31:55,963 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-02-04 19:31:55,963 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=152, Invalid=1330, Unknown=0, NotChecked=0, Total=1482 [2018-02-04 19:31:55,963 INFO L87 Difference]: Start difference. First operand 170 states and 180 transitions. Second operand 39 states. [2018-02-04 19:31:57,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:57,254 INFO L93 Difference]: Finished difference Result 171 states and 180 transitions. [2018-02-04 19:31:57,255 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-02-04 19:31:57,255 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 110 [2018-02-04 19:31:57,255 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:57,255 INFO L225 Difference]: With dead ends: 171 [2018-02-04 19:31:57,255 INFO L226 Difference]: Without dead ends: 169 [2018-02-04 19:31:57,256 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 145 GetRequests, 81 SyntacticMatches, 5 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 660 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=375, Invalid=3285, Unknown=0, NotChecked=0, Total=3660 [2018-02-04 19:31:57,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states. [2018-02-04 19:31:57,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 169. [2018-02-04 19:31:57,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 169 states. [2018-02-04 19:31:57,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 178 transitions. [2018-02-04 19:31:57,259 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 178 transitions. Word has length 110 [2018-02-04 19:31:57,259 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:57,259 INFO L432 AbstractCegarLoop]: Abstraction has 169 states and 178 transitions. [2018-02-04 19:31:57,260 INFO L433 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-02-04 19:31:57,260 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 178 transitions. [2018-02-04 19:31:57,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-02-04 19:31:57,260 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:57,260 INFO L351 BasicCegarLoop]: trace histogram [11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:57,261 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:57,261 INFO L82 PathProgramCache]: Analyzing trace with hash 1817608758, now seen corresponding path program 1 times [2018-02-04 19:31:57,261 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:57,261 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:57,262 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:57,262 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:31:57,262 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:57,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:57,280 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:57,408 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:57,409 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:31:57,409 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:31:57,410 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:57,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:57,442 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:31:57,466 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:57,466 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:31:57,466 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 16 [2018-02-04 19:31:57,467 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-04 19:31:57,467 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-04 19:31:57,467 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=133, Unknown=0, NotChecked=0, Total=240 [2018-02-04 19:31:57,467 INFO L87 Difference]: Start difference. First operand 169 states and 178 transitions. Second operand 16 states. [2018-02-04 19:31:57,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:31:57,508 INFO L93 Difference]: Finished difference Result 172 states and 181 transitions. [2018-02-04 19:31:57,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-04 19:31:57,509 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 115 [2018-02-04 19:31:57,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:31:57,510 INFO L225 Difference]: With dead ends: 172 [2018-02-04 19:31:57,510 INFO L226 Difference]: Without dead ends: 170 [2018-02-04 19:31:57,510 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 130 GetRequests, 115 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=111, Invalid=161, Unknown=0, NotChecked=0, Total=272 [2018-02-04 19:31:57,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2018-02-04 19:31:57,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 170. [2018-02-04 19:31:57,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-02-04 19:31:57,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 179 transitions. [2018-02-04 19:31:57,514 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 179 transitions. Word has length 115 [2018-02-04 19:31:57,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:31:57,514 INFO L432 AbstractCegarLoop]: Abstraction has 170 states and 179 transitions. [2018-02-04 19:31:57,514 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-04 19:31:57,514 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 179 transitions. [2018-02-04 19:31:57,515 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-02-04 19:31:57,515 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:31:57,515 INFO L351 BasicCegarLoop]: trace histogram [12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:31:57,515 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:31:57,515 INFO L82 PathProgramCache]: Analyzing trace with hash 70072341, now seen corresponding path program 2 times [2018-02-04 19:31:57,515 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:31:57,516 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:31:57,516 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:57,516 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:31:57,516 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:31:57,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:31:57,532 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:31:57,680 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:31:57,680 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:31:57,680 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:31:57,681 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 19:31:57,726 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 19:31:57,726 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:31:57,734 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:31:57,868 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-02-04 19:31:57,869 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-02-04 19:31:57,869 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:31:57,870 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:31:57,871 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:31:57,871 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:11, output treesize:7 [2018-02-04 19:31:57,946 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:31:57,948 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:31:57,951 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 19:31:57,951 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:38, output treesize:26 [2018-02-04 19:31:57,954 WARN L1033 $PredicateComparison]: unable to prove that (exists ((LDV_INIT_LIST_HEAD_~list.offset Int) (v_DerPreprocessor_2 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_LDV_INIT_LIST_HEAD_#in~list.base| (let ((.cse0 (+ LDV_INIT_LIST_HEAD_~list.offset 4))) (store (store (select |c_old(#memory_int)| |c_LDV_INIT_LIST_HEAD_#in~list.base|) LDV_INIT_LIST_HEAD_~list.offset v_DerPreprocessor_2) .cse0 (select (select |c_#memory_int| |c_LDV_INIT_LIST_HEAD_#in~list.base|) .cse0))))) (<= LDV_INIT_LIST_HEAD_~list.offset |c_LDV_INIT_LIST_HEAD_#in~list.offset|))) is different from true [2018-02-04 19:31:57,966 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 27 [2018-02-04 19:31:57,968 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:31:57,980 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 35 [2018-02-04 19:31:57,982 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:31:57,983 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:31:57,985 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 37 [2018-02-04 19:31:57,986 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 19:31:57,990 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:31:57,993 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:31:57,997 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:31:57,997 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:37, output treesize:9 [2018-02-04 19:31:58,360 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:31:58,360 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 28 [2018-02-04 19:31:58,362 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:31:58,363 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 7 [2018-02-04 19:31:58,363 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:31:58,364 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:31:58,365 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:31:58,365 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:25, output treesize:7 [2018-02-04 19:31:58,748 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 13 [2018-02-04 19:31:58,753 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 1 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 19:31:58,753 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-02-04 19:31:58,755 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 19:31:58,757 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 2 xjuncts. [2018-02-04 19:31:58,758 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:17, output treesize:10 [2018-02-04 19:31:59,047 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 78 trivial. 0 not checked. [2018-02-04 19:31:59,047 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:31:59,047 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [53] imperfect sequences [16] total 67 [2018-02-04 19:31:59,047 INFO L409 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-02-04 19:31:59,047 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-02-04 19:31:59,048 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=224, Invalid=4069, Unknown=1, NotChecked=128, Total=4422 [2018-02-04 19:31:59,048 INFO L87 Difference]: Start difference. First operand 170 states and 179 transitions. Second operand 67 states. [2018-02-04 19:32:01,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:32:01,420 INFO L93 Difference]: Finished difference Result 175 states and 178 transitions. [2018-02-04 19:32:01,421 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-02-04 19:32:01,421 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 116 [2018-02-04 19:32:01,421 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:32:01,421 INFO L225 Difference]: With dead ends: 175 [2018-02-04 19:32:01,421 INFO L226 Difference]: Without dead ends: 164 [2018-02-04 19:32:01,423 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 66 SyntacticMatches, 0 SemanticMatches, 96 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 1605 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=384, Invalid=8931, Unknown=1, NotChecked=190, Total=9506 [2018-02-04 19:32:01,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164 states. [2018-02-04 19:32:01,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164 to 164. [2018-02-04 19:32:01,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 164 states. [2018-02-04 19:32:01,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 167 transitions. [2018-02-04 19:32:01,425 INFO L78 Accepts]: Start accepts. Automaton has 164 states and 167 transitions. Word has length 116 [2018-02-04 19:32:01,425 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:32:01,425 INFO L432 AbstractCegarLoop]: Abstraction has 164 states and 167 transitions. [2018-02-04 19:32:01,425 INFO L433 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-02-04 19:32:01,425 INFO L276 IsEmpty]: Start isEmpty. Operand 164 states and 167 transitions. [2018-02-04 19:32:01,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-02-04 19:32:01,425 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:32:01,426 INFO L351 BasicCegarLoop]: trace histogram [13, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:32:01,426 INFO L371 AbstractCegarLoop]: === Iteration 29 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:32:01,426 INFO L82 PathProgramCache]: Analyzing trace with hash -2129620089, now seen corresponding path program 1 times [2018-02-04 19:32:01,426 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:32:01,426 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:32:01,427 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:32:01,427 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:32:01,427 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:32:01,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:32:01,447 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:32:02,075 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 91 trivial. 0 not checked. [2018-02-04 19:32:02,075 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:32:02,075 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:32:02,076 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:32:02,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:32:02,108 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:32:02,542 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 19:32:02,543 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:32:02,543 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 17] total 36 [2018-02-04 19:32:02,543 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-02-04 19:32:02,543 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-02-04 19:32:02,544 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=162, Invalid=1098, Unknown=0, NotChecked=0, Total=1260 [2018-02-04 19:32:02,544 INFO L87 Difference]: Start difference. First operand 164 states and 167 transitions. Second operand 36 states. [2018-02-04 19:32:03,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:32:03,826 INFO L93 Difference]: Finished difference Result 179 states and 181 transitions. [2018-02-04 19:32:03,826 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-02-04 19:32:03,826 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 126 [2018-02-04 19:32:03,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:32:03,826 INFO L225 Difference]: With dead ends: 179 [2018-02-04 19:32:03,827 INFO L226 Difference]: Without dead ends: 177 [2018-02-04 19:32:03,827 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 118 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 586 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=492, Invalid=4064, Unknown=0, NotChecked=0, Total=4556 [2018-02-04 19:32:03,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-02-04 19:32:03,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 167. [2018-02-04 19:32:03,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-02-04 19:32:03,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 169 transitions. [2018-02-04 19:32:03,830 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 169 transitions. Word has length 126 [2018-02-04 19:32:03,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:32:03,830 INFO L432 AbstractCegarLoop]: Abstraction has 167 states and 169 transitions. [2018-02-04 19:32:03,830 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-02-04 19:32:03,830 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 169 transitions. [2018-02-04 19:32:03,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 142 [2018-02-04 19:32:03,831 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:32:03,831 INFO L351 BasicCegarLoop]: trace histogram [14, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:32:03,831 INFO L371 AbstractCegarLoop]: === Iteration 30 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:32:03,831 INFO L82 PathProgramCache]: Analyzing trace with hash 1333200073, now seen corresponding path program 1 times [2018-02-04 19:32:03,831 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:32:03,831 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:32:03,832 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:32:03,832 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:32:03,832 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:32:03,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:32:03,853 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:32:04,140 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-02-04 19:32:04,140 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:32:04,141 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:32:04,141 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:32:04,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:32:04,176 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:32:04,455 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-02-04 19:32:04,455 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:32:04,455 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 18] total 40 [2018-02-04 19:32:04,456 INFO L409 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-02-04 19:32:04,456 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-02-04 19:32:04,456 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=182, Invalid=1378, Unknown=0, NotChecked=0, Total=1560 [2018-02-04 19:32:04,456 INFO L87 Difference]: Start difference. First operand 167 states and 169 transitions. Second operand 40 states. [2018-02-04 19:32:05,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:32:05,600 INFO L93 Difference]: Finished difference Result 179 states and 181 transitions. [2018-02-04 19:32:05,600 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-02-04 19:32:05,600 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 141 [2018-02-04 19:32:05,600 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:32:05,600 INFO L225 Difference]: With dead ends: 179 [2018-02-04 19:32:05,601 INFO L226 Difference]: Without dead ends: 177 [2018-02-04 19:32:05,602 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 206 GetRequests, 132 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 633 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=558, Invalid=5142, Unknown=0, NotChecked=0, Total=5700 [2018-02-04 19:32:05,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-02-04 19:32:05,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 167. [2018-02-04 19:32:05,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-02-04 19:32:05,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 169 transitions. [2018-02-04 19:32:05,605 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 169 transitions. Word has length 141 [2018-02-04 19:32:05,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:32:05,605 INFO L432 AbstractCegarLoop]: Abstraction has 167 states and 169 transitions. [2018-02-04 19:32:05,605 INFO L433 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-02-04 19:32:05,605 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 169 transitions. [2018-02-04 19:32:05,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-02-04 19:32:05,606 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:32:05,606 INFO L351 BasicCegarLoop]: trace histogram [15, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:32:05,606 INFO L371 AbstractCegarLoop]: === Iteration 31 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:32:05,606 INFO L82 PathProgramCache]: Analyzing trace with hash -1992522262, now seen corresponding path program 1 times [2018-02-04 19:32:05,607 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:32:05,607 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:32:05,607 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:32:05,607 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:32:05,607 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:32:05,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:32:05,628 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:32:05,826 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 9 proven. 120 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-02-04 19:32:05,826 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:32:05,827 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:32:05,827 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:32:05,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:32:05,865 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:32:05,885 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-02-04 19:32:05,886 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:32:05,886 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 20 [2018-02-04 19:32:05,886 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-04 19:32:05,886 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-04 19:32:05,886 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=173, Invalid=207, Unknown=0, NotChecked=0, Total=380 [2018-02-04 19:32:05,887 INFO L87 Difference]: Start difference. First operand 167 states and 169 transitions. Second operand 20 states. [2018-02-04 19:32:05,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:32:05,925 INFO L93 Difference]: Finished difference Result 170 states and 172 transitions. [2018-02-04 19:32:05,925 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-04 19:32:05,925 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 146 [2018-02-04 19:32:05,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:32:05,926 INFO L225 Difference]: With dead ends: 170 [2018-02-04 19:32:05,926 INFO L226 Difference]: Without dead ends: 168 [2018-02-04 19:32:05,927 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 146 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=177, Invalid=243, Unknown=0, NotChecked=0, Total=420 [2018-02-04 19:32:05,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168 states. [2018-02-04 19:32:05,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168 to 168. [2018-02-04 19:32:05,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 168 states. [2018-02-04 19:32:05,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168 states to 168 states and 170 transitions. [2018-02-04 19:32:05,930 INFO L78 Accepts]: Start accepts. Automaton has 168 states and 170 transitions. Word has length 146 [2018-02-04 19:32:05,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:32:05,931 INFO L432 AbstractCegarLoop]: Abstraction has 168 states and 170 transitions. [2018-02-04 19:32:05,931 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-04 19:32:05,931 INFO L276 IsEmpty]: Start isEmpty. Operand 168 states and 170 transitions. [2018-02-04 19:32:05,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 148 [2018-02-04 19:32:05,932 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:32:05,932 INFO L351 BasicCegarLoop]: trace histogram [16, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:32:05,932 INFO L371 AbstractCegarLoop]: === Iteration 32 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 19:32:05,932 INFO L82 PathProgramCache]: Analyzing trace with hash 903271467, now seen corresponding path program 2 times [2018-02-04 19:32:05,932 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:32:05,932 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:32:05,933 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:32:05,933 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:32:05,933 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:32:06,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:32:06,015 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:32:06,047 INFO L430 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-02-04 19:32:06,047 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:32:06,047 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:32:06,048 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 19:32:06,176 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-02-04 19:32:06,176 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:32:06,188 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:32:06,208 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 19:32:06,211 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 19:32:06,212 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:32:06,213 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:32:06,217 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:32:06,217 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:17, output treesize:13 [2018-02-04 19:32:06,234 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 20 [2018-02-04 19:32:06,237 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,237 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 27 [2018-02-04 19:32:06,238 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:32:06,244 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:32:06,251 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:32:06,251 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:33, output treesize:29 [2018-02-04 19:32:06,278 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 29 [2018-02-04 19:32:06,288 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,289 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,290 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,291 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 52 [2018-02-04 19:32:06,291 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:32:06,301 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:32:06,315 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 19:32:06,316 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:49, output treesize:45 [2018-02-04 19:32:06,360 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 38 [2018-02-04 19:32:06,363 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,364 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,366 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,367 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,368 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,369 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,370 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 85 [2018-02-04 19:32:06,370 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:32:06,386 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:32:06,399 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-02-04 19:32:06,400 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:65, output treesize:61 [2018-02-04 19:32:06,437 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 47 [2018-02-04 19:32:06,441 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,442 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,443 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,444 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,445 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,446 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,447 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,448 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,452 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,453 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,454 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 126 [2018-02-04 19:32:06,455 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:32:06,484 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:32:06,505 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-2 vars, End of recursive call: 4 dim-0 vars, and 1 xjuncts. [2018-02-04 19:32:06,505 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 5 variables, input treesize:81, output treesize:77 [2018-02-04 19:32:06,559 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 56 [2018-02-04 19:32:06,565 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,566 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,567 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,568 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,569 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,570 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,570 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,571 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,571 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,572 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,573 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,573 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,574 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,574 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,575 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:06,577 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 175 [2018-02-04 19:32:06,577 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:32:06,604 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:32:06,653 INFO L267 ElimStorePlain]: Start of recursive call 1: 5 dim-0 vars, 1 dim-2 vars, End of recursive call: 5 dim-0 vars, and 1 xjuncts. [2018-02-04 19:32:06,654 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 6 variables, input treesize:97, output treesize:93 [2018-02-04 19:32:10,741 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 80 treesize of output 65 [2018-02-04 19:32:10,746 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,747 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,748 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,749 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,751 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,752 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,753 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,754 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,755 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,756 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,757 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,758 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,759 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,760 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,760 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,761 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,762 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,769 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,770 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,771 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,772 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:10,773 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 21 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 232 [2018-02-04 19:32:10,773 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:32:10,816 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:32:10,838 INFO L267 ElimStorePlain]: Start of recursive call 1: 6 dim-0 vars, 1 dim-2 vars, End of recursive call: 6 dim-0 vars, and 1 xjuncts. [2018-02-04 19:32:10,838 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 7 variables, input treesize:113, output treesize:109 [2018-02-04 19:32:14,227 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 74 [2018-02-04 19:32:14,230 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,231 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,232 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,232 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,233 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,234 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,235 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,235 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,236 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,236 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,237 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,238 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,238 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,239 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,240 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,241 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,241 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,242 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,243 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,243 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,244 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,245 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,245 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,246 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,247 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,248 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,248 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,249 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:14,250 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 28 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 297 [2018-02-04 19:32:14,251 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:32:14,295 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:32:14,316 INFO L267 ElimStorePlain]: Start of recursive call 1: 7 dim-0 vars, 1 dim-2 vars, End of recursive call: 7 dim-0 vars, and 1 xjuncts. [2018-02-04 19:32:14,317 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 8 variables, input treesize:129, output treesize:125 [2018-02-04 19:32:18,380 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 102 treesize of output 83 [2018-02-04 19:32:18,383 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,384 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,385 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,385 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,386 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,387 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,388 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,388 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,389 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,389 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,390 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,391 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,391 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,392 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,392 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,393 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,394 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,394 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,395 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,395 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,396 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,397 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,397 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,398 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,398 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,399 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,399 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,400 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,401 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,401 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,402 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,402 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,403 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,403 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,404 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,405 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:18,405 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 36 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 370 [2018-02-04 19:32:18,406 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:32:18,470 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:32:18,507 INFO L267 ElimStorePlain]: Start of recursive call 1: 8 dim-0 vars, 1 dim-2 vars, End of recursive call: 8 dim-0 vars, and 1 xjuncts. [2018-02-04 19:32:18,507 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 9 variables, input treesize:145, output treesize:141 [2018-02-04 19:32:22,588 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 113 treesize of output 92 [2018-02-04 19:32:22,592 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,593 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,594 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,595 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,595 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,596 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,597 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,597 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,598 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,599 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,600 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,601 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,601 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,602 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,603 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,604 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,605 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,606 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,606 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,607 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,608 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,609 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,609 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,610 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,611 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,612 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,613 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,613 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,614 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,615 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,615 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,616 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,618 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,619 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,620 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,621 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,622 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,623 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,624 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,625 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,625 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,626 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,627 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,628 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,629 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:22,630 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 45 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 451 [2018-02-04 19:32:22,631 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:32:22,737 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:32:22,768 INFO L267 ElimStorePlain]: Start of recursive call 1: 9 dim-0 vars, 1 dim-2 vars, End of recursive call: 9 dim-0 vars, and 1 xjuncts. [2018-02-04 19:32:22,769 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 10 variables, input treesize:161, output treesize:157 [2018-02-04 19:32:25,420 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 124 treesize of output 101 [2018-02-04 19:32:25,424 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,425 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,426 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,427 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,428 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,428 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,429 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,430 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,431 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,432 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,433 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,433 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,434 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,435 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,436 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,437 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,438 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,438 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,439 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,440 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,441 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,441 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,442 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,443 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,444 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,444 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,445 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,446 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,447 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,448 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,448 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,449 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,450 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,451 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,451 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,452 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,453 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,454 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,454 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,455 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,456 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,457 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,457 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,458 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,459 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,460 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,460 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,461 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,462 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,463 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,463 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,464 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,465 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,466 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,467 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:25,468 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 55 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 101 treesize of output 540 [2018-02-04 19:32:25,468 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:32:25,580 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:32:25,611 INFO L267 ElimStorePlain]: Start of recursive call 1: 10 dim-0 vars, 1 dim-2 vars, End of recursive call: 10 dim-0 vars, and 1 xjuncts. [2018-02-04 19:32:25,612 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 11 variables, input treesize:177, output treesize:173 [2018-02-04 19:32:33,616 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 135 treesize of output 110 [2018-02-04 19:32:33,620 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,621 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,622 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,623 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,626 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,627 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,628 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,629 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,629 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,630 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,631 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,632 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,632 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,633 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,634 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,634 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,635 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,636 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,636 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,637 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,637 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,638 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,639 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,639 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,640 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,640 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,641 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,642 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,642 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,643 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,644 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,644 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,645 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,645 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,646 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,647 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,647 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,648 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,648 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,649 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,650 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,650 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,651 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,652 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,652 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,653 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,653 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,654 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,655 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,655 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,656 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,657 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,657 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,658 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,659 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,659 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,660 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,661 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,661 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,662 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,662 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,663 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,664 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,664 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,665 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,665 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:33,667 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 11 select indices, 11 select index equivalence classes, 66 disjoint index pairs (out of 55 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 110 treesize of output 637 [2018-02-04 19:32:33,668 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:32:33,814 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:32:33,863 INFO L267 ElimStorePlain]: Start of recursive call 1: 11 dim-0 vars, 1 dim-2 vars, End of recursive call: 11 dim-0 vars, and 1 xjuncts. [2018-02-04 19:32:33,863 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 12 variables, input treesize:193, output treesize:189 [2018-02-04 19:32:46,022 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 147 treesize of output 120 [2018-02-04 19:32:46,039 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,040 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,041 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,042 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,043 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,044 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,045 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,046 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,047 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,048 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,049 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,050 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,051 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,052 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,053 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,054 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,055 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,056 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,057 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,058 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,059 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,060 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,061 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,062 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,063 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,064 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,065 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,066 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,067 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,067 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,068 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,069 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,070 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,071 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,072 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,073 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,074 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,075 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,076 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,077 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,078 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,079 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,080 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,081 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,082 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,082 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,083 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,084 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,085 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,086 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,087 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,088 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,089 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,090 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,091 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,092 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,093 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,094 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,095 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,096 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,097 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,097 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,099 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,100 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,101 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,102 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,103 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,104 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,105 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,106 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,107 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,108 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,109 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,110 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,111 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,112 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,113 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,113 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:46,115 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 12 select indices, 12 select index equivalence classes, 78 disjoint index pairs (out of 66 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 120 treesize of output 755 [2018-02-04 19:32:46,116 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:32:46,320 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:32:46,371 INFO L267 ElimStorePlain]: Start of recursive call 1: 11 dim-0 vars, 1 dim-2 vars, End of recursive call: 11 dim-0 vars, and 1 xjuncts. [2018-02-04 19:32:46,371 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 12 variables, input treesize:205, output treesize:201 [2018-02-04 19:32:53,245 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 159 treesize of output 130 [2018-02-04 19:32:53,250 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,251 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,252 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,253 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,254 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,255 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,256 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,257 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,258 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,259 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,261 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,262 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,263 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,264 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,265 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,266 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,267 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,268 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,269 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,270 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,271 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,272 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,273 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,274 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,275 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,276 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,277 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,278 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,280 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,281 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,282 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,283 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,284 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,285 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,286 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,287 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,288 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,289 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,290 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,291 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,292 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,293 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,294 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,295 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,296 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,297 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,298 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,299 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,300 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,301 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,302 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,303 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,304 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,305 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,306 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,307 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,308 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,309 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,311 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,311 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,313 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,313 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,314 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,315 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,316 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,317 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,318 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,319 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,320 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,321 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,322 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,323 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,324 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,325 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,326 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,327 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,329 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,330 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,330 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,331 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,332 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,333 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,334 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,336 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,337 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,338 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,339 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,340 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,341 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,342 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,343 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:32:53,345 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 13 select indices, 13 select index equivalence classes, 91 disjoint index pairs (out of 78 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 130 treesize of output 883 [2018-02-04 19:32:53,346 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:32:53,647 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:32:53,701 INFO L267 ElimStorePlain]: Start of recursive call 1: 11 dim-0 vars, 1 dim-2 vars, End of recursive call: 11 dim-0 vars, and 1 xjuncts. [2018-02-04 19:32:53,702 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 12 variables, input treesize:217, output treesize:213 [2018-02-04 19:33:04,766 WARN L143 SmtUtils]: Spent 543ms on a formula simplification that was a NOOP. DAG size: 90 [2018-02-04 19:33:04,775 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 140 [2018-02-04 19:33:04,782 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,784 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,785 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,786 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,788 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,789 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,791 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,792 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,794 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,795 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,797 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,798 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,800 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,801 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,802 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,803 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,804 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,805 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,807 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,808 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,809 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,810 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,811 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,812 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,814 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,815 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,816 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,817 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,818 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,819 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,820 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,821 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,823 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,824 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,825 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,826 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,827 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,828 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,829 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,830 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,831 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,832 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,833 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,835 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,836 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,837 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,838 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,839 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,840 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,841 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,842 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,844 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,845 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,846 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,847 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,848 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,849 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,850 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,851 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,853 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,854 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,855 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,856 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,857 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,858 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,859 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,860 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,861 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,862 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,864 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,865 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,866 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,867 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,868 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,869 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,870 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,871 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,872 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,873 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,874 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,875 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,876 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,877 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,879 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,880 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,881 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,882 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,883 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,884 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,885 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,886 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,887 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,888 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,889 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,890 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,891 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,892 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,893 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,895 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,896 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,897 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,898 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,899 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,900 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,901 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:04,902 INFO L303 Elim1Store]: Index analysis took 124 ms [2018-02-04 19:33:04,903 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 14 select indices, 14 select index equivalence classes, 105 disjoint index pairs (out of 91 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 140 treesize of output 1021 [2018-02-04 19:33:04,904 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:33:05,199 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:33:05,251 INFO L267 ElimStorePlain]: Start of recursive call 1: 11 dim-0 vars, 1 dim-2 vars, End of recursive call: 11 dim-0 vars, and 1 xjuncts. [2018-02-04 19:33:05,251 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 12 variables, input treesize:229, output treesize:225 [2018-02-04 19:33:24,888 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 182 treesize of output 149 [2018-02-04 19:33:24,895 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,896 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,897 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,898 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,899 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,900 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,901 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,902 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,903 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,904 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,905 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,906 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,907 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,908 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,909 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,910 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,911 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,912 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,913 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,914 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,915 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,916 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,917 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,918 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,919 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,919 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,920 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,921 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,922 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,923 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,924 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,925 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,926 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,927 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,928 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,929 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,930 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,931 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,932 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,933 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,934 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,934 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,935 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,936 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,937 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,938 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,939 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,940 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,941 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,942 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,943 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,944 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,944 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,945 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,946 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,947 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,948 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,949 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,950 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,951 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,952 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,953 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,954 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,955 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,956 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,957 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,958 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,959 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,960 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,961 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,962 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,963 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,963 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,964 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,965 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,966 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,967 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,968 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,969 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,970 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,971 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,972 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,973 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,974 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,975 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,976 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,977 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,978 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,979 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,980 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,981 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,982 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,982 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,983 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,984 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,985 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,986 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,987 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,988 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,989 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,990 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,991 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,992 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,993 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,994 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,996 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,997 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,998 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:24,999 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:25,000 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:25,015 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:25,016 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:25,017 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:25,018 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:25,019 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:25,020 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:25,021 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:25,022 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:25,023 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:25,024 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:25,024 INFO L303 Elim1Store]: Index analysis took 134 ms [2018-02-04 19:33:25,026 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 15 select indices, 15 select index equivalence classes, 120 disjoint index pairs (out of 105 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 149 treesize of output 1153 [2018-02-04 19:33:25,028 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:33:25,380 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:33:25,432 INFO L267 ElimStorePlain]: Start of recursive call 1: 12 dim-0 vars, 1 dim-2 vars, End of recursive call: 12 dim-0 vars, and 1 xjuncts. [2018-02-04 19:33:25,432 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 13 variables, input treesize:248, output treesize:244 [2018-02-04 19:33:35,972 WARN L1033 $PredicateComparison]: unable to prove that (exists ((LDV_INIT_LIST_HEAD_~list.offset Int)) (and (= (store |c_old(#memory_$Pointer$.offset)| |c_LDV_INIT_LIST_HEAD_#in~list.base| (store (store (select |c_old(#memory_$Pointer$.offset)| |c_LDV_INIT_LIST_HEAD_#in~list.base|) LDV_INIT_LIST_HEAD_~list.offset LDV_INIT_LIST_HEAD_~list.offset) (+ LDV_INIT_LIST_HEAD_~list.offset 4) LDV_INIT_LIST_HEAD_~list.offset)) |c_#memory_$Pointer$.offset|) (<= |c_LDV_INIT_LIST_HEAD_#in~list.offset| LDV_INIT_LIST_HEAD_~list.offset))) is different from true [2018-02-04 19:33:35,974 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:33:35,976 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:33:35,979 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 19:33:35,979 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:41, output treesize:27 [2018-02-04 19:33:35,981 WARN L1033 $PredicateComparison]: unable to prove that (exists ((LDV_INIT_LIST_HEAD_~list.offset Int) (v_DerPreprocessor_4 Int)) (and (<= (+ |c_ldv_kobject_init_internal_#in~kobj.offset| 4) LDV_INIT_LIST_HEAD_~list.offset) (= (store |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_internal_#in~kobj.base| (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_internal_#in~kobj.base|) (+ |c_ldv_kobject_init_internal_#in~kobj.offset| 12) v_DerPreprocessor_4) LDV_INIT_LIST_HEAD_~list.offset LDV_INIT_LIST_HEAD_~list.offset) (+ LDV_INIT_LIST_HEAD_~list.offset 4) LDV_INIT_LIST_HEAD_~list.offset)) |c_#memory_$Pointer$.offset|))) is different from true [2018-02-04 19:33:35,984 WARN L1033 $PredicateComparison]: unable to prove that (exists ((LDV_INIT_LIST_HEAD_~list.offset Int) (v_DerPreprocessor_4 Int)) (and (= |c_#memory_$Pointer$.offset| (store |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_#in~kobj.base| (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_#in~kobj.base|) (+ |c_ldv_kobject_init_#in~kobj.offset| 12) v_DerPreprocessor_4) LDV_INIT_LIST_HEAD_~list.offset LDV_INIT_LIST_HEAD_~list.offset) (+ LDV_INIT_LIST_HEAD_~list.offset 4) LDV_INIT_LIST_HEAD_~list.offset))) (<= (+ |c_ldv_kobject_init_#in~kobj.offset| 4) LDV_INIT_LIST_HEAD_~list.offset))) is different from true [2018-02-04 19:33:36,003 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 167 treesize of output 132 [2018-02-04 19:33:36,015 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,020 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,025 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,030 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,036 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,040 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,044 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,047 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,048 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,051 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,053 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,056 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,059 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,062 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,064 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,067 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,068 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,072 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,074 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,078 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,082 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,085 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,088 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,090 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,091 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,094 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,097 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,100 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,103 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,106 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,109 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,111 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,114 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,115 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,116 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,118 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,120 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,123 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,125 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,130 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,132 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,137 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,142 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,145 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,146 INFO L682 Elim1Store]: detected equality via solver [2018-02-04 19:33:36,149 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,153 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,155 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,158 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,161 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,162 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,168 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,174 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,179 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,181 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,184 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,187 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,190 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,192 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,196 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,198 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,201 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,203 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,205 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,209 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,212 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,215 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,218 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,220 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,222 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,227 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,232 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,236 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,238 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,243 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,246 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,248 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,250 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,252 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,254 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,256 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,258 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,260 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,262 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,265 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,266 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,269 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,273 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,278 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,280 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,282 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,285 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,287 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,290 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,293 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,296 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,299 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,301 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,304 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,308 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,311 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,314 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,317 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,320 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,324 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,327 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,330 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,333 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,336 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,341 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,343 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,346 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,348 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,349 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,352 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,354 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,359 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,362 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,365 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,367 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,369 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,372 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,377 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,472 INFO L303 Elim1Store]: Index analysis took 465 ms [2018-02-04 19:33:36,473 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 16 select indices, 16 select index equivalence classes, 120 disjoint index pairs (out of 120 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 132 treesize of output 1233 [2018-02-04 19:33:36,495 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,498 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,501 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,503 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,504 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,506 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,510 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,515 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,517 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,519 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,521 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,523 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,528 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,532 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,534 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,536 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,538 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,540 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,542 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,545 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,549 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,553 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,554 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,558 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,561 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,562 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,567 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,569 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,572 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,574 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,582 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,585 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,586 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,589 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,590 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,593 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,595 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,598 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,603 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,605 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,611 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,613 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,616 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,620 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,624 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,626 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,628 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,630 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,632 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,637 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,639 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,641 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,644 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,648 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,650 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,660 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,663 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,665 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,668 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,669 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,671 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,673 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,676 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,678 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,680 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,681 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,688 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,692 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,693 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,695 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,696 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,697 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,699 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,702 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,705 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,707 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,711 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,713 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,716 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,720 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,721 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,724 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,726 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,730 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,734 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,736 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,739 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,741 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,743 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,745 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,747 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,749 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,751 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,756 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,764 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,769 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,773 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,775 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,779 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,781 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,784 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,793 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,796 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,798 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,800 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,802 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,806 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,809 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,811 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,813 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,817 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,819 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,820 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,829 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,831 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,835 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,837 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,849 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,851 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,854 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,864 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,865 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,880 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,886 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:33:36,955 INFO L303 Elim1Store]: Index analysis took 469 ms [2018-02-04 19:33:37,178 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 16 select indices, 16 select index equivalence classes, 124 disjoint index pairs (out of 120 index pairs), introduced 1 new quantified variables, introduced 24 case distinctions, treesize of input 127 treesize of output 1204 [2018-02-04 19:33:37,179 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 12 [2018-02-04 19:33:49,106 WARN L307 Elim1Store]: Array PQE input equivalent to false [2018-02-04 19:33:49,106 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. Received shutdown request... [2018-02-04 19:35:09,898 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-02-04 19:35:09,898 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-04 19:35:09,901 WARN L185 ceAbstractionStarter]: Timeout [2018-02-04 19:35:09,901 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 04.02 07:35:09 BoogieIcfgContainer [2018-02-04 19:35:09,901 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-04 19:35:09,902 INFO L168 Benchmark]: Toolchain (without parser) took 205640.30 ms. Allocated memory was 404.8 MB in the beginning and 979.9 MB in the end (delta: 575.1 MB). Free memory was 361.6 MB in the beginning and 605.2 MB in the end (delta: -243.6 MB). Peak memory consumption was 2.0 GB. Max. memory is 5.3 GB. [2018-02-04 19:35:09,903 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 404.8 MB. Free memory is still 368.2 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-04 19:35:09,903 INFO L168 Benchmark]: CACSL2BoogieTranslator took 182.67 ms. Allocated memory is still 404.8 MB. Free memory was 361.6 MB in the beginning and 347.1 MB in the end (delta: 14.5 MB). Peak memory consumption was 14.5 MB. Max. memory is 5.3 GB. [2018-02-04 19:35:09,903 INFO L168 Benchmark]: Boogie Preprocessor took 32.81 ms. Allocated memory is still 404.8 MB. Free memory was 347.1 MB in the beginning and 345.8 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. [2018-02-04 19:35:09,903 INFO L168 Benchmark]: RCFGBuilder took 363.17 ms. Allocated memory is still 404.8 MB. Free memory was 345.8 MB in the beginning and 307.8 MB in the end (delta: 37.9 MB). Peak memory consumption was 37.9 MB. Max. memory is 5.3 GB. [2018-02-04 19:35:09,904 INFO L168 Benchmark]: TraceAbstraction took 205059.14 ms. Allocated memory was 404.8 MB in the beginning and 979.9 MB in the end (delta: 575.1 MB). Free memory was 307.8 MB in the beginning and 605.2 MB in the end (delta: -297.4 MB). Peak memory consumption was 2.0 GB. Max. memory is 5.3 GB. [2018-02-04 19:35:09,904 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 404.8 MB. Free memory is still 368.2 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 182.67 ms. Allocated memory is still 404.8 MB. Free memory was 361.6 MB in the beginning and 347.1 MB in the end (delta: 14.5 MB). Peak memory consumption was 14.5 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 32.81 ms. Allocated memory is still 404.8 MB. Free memory was 347.1 MB in the beginning and 345.8 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. * RCFGBuilder took 363.17 ms. Allocated memory is still 404.8 MB. Free memory was 345.8 MB in the beginning and 307.8 MB in the end (delta: 37.9 MB). Peak memory consumption was 37.9 MB. Max. memory is 5.3 GB. * TraceAbstraction took 205059.14 ms. Allocated memory was 404.8 MB in the beginning and 979.9 MB in the end (delta: 575.1 MB). Free memory was 307.8 MB in the beginning and 605.2 MB in the end (delta: -297.4 MB). Peak memory consumption was 2.0 GB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1294). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1294). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1411). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1411). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1265). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1265). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1267). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1267). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1256). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1256). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1258). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1258). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1452]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 1452). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was analyzing trace of length 148 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 106769. - StatisticsResult: Ultimate Automizer benchmark data CFG has 23 procedures, 151 locations, 23 error locations. TIMEOUT Result, 205.0s OverallTime, 32 OverallIterations, 16 TraceHistogramMax, 11.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4136 SDtfs, 1238 SDslu, 39746 SDs, 0 SdLazy, 19517 SolverSat, 363 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1930 GetRequests, 1208 SyntacticMatches, 11 SemanticMatches, 711 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 4786 ImplicationChecksByTransitivity, 9.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=175occurred in iteration=9, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 31 MinimizatonAttempts, 160 StatesRemovedByMinimization, 12 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.6s SatisfiabilityAnalysisTime, 7.9s InterpolantComputationTime, 3509 NumberOfCodeBlocks, 3467 NumberOfCodeBlocksAsserted, 46 NumberOfCheckSat, 3463 ConstructedInterpolants, 174 QuantifiedInterpolants, 813481 SizeOfPredicates, 120 NumberOfNonLiveVariables, 6316 ConjunctsInSsa, 601 ConjunctsInUnsatCore, 46 InterpolantComputations, 22 PerfectInterpolantSequences, 668/1645 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test22_3_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-04_19-35-09-909.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test22_3_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-04_19-35-09-909.csv Completed graceful shutdown