java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv --cacsl2boogietranslator.bitprecise.bitfields false -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf -i ../../../trunk/examples/svcomp/array-memsafety/cstrcat-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-666feb3-m [2018-04-11 12:48:02,412 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-04-11 12:48:02,413 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-04-11 12:48:02,427 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-04-11 12:48:02,427 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-04-11 12:48:02,428 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-04-11 12:48:02,429 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-04-11 12:48:02,431 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-04-11 12:48:02,433 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-04-11 12:48:02,434 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-04-11 12:48:02,435 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-04-11 12:48:02,435 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-04-11 12:48:02,436 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-04-11 12:48:02,437 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-04-11 12:48:02,438 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-04-11 12:48:02,440 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-04-11 12:48:02,441 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-04-11 12:48:02,443 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-04-11 12:48:02,444 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-04-11 12:48:02,445 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-04-11 12:48:02,447 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-04-11 12:48:02,448 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-04-11 12:48:02,448 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-04-11 12:48:02,449 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-04-11 12:48:02,450 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-04-11 12:48:02,451 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-04-11 12:48:02,451 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-04-11 12:48:02,452 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-04-11 12:48:02,453 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-04-11 12:48:02,453 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-04-11 12:48:02,453 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-04-11 12:48:02,454 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf [2018-04-11 12:48:02,482 INFO L110 SettingsManager]: Loading preferences was successful [2018-04-11 12:48:02,482 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-04-11 12:48:02,488 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-04-11 12:48:02,489 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-04-11 12:48:02,489 INFO L133 SettingsManager]: * Use SBE=true [2018-04-11 12:48:02,489 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-04-11 12:48:02,489 INFO L133 SettingsManager]: * sizeof long=4 [2018-04-11 12:48:02,489 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-04-11 12:48:02,489 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-04-11 12:48:02,490 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-04-11 12:48:02,490 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-04-11 12:48:02,490 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-04-11 12:48:02,490 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-04-11 12:48:02,490 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-04-11 12:48:02,490 INFO L133 SettingsManager]: * sizeof long double=12 [2018-04-11 12:48:02,491 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-04-11 12:48:02,491 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-04-11 12:48:02,491 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-04-11 12:48:02,491 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-04-11 12:48:02,491 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-11 12:48:02,491 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-04-11 12:48:02,491 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_TreeInterpolation Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Bitprecise bitfields -> false [2018-04-11 12:48:02,523 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-04-11 12:48:02,534 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully (re)initialized [2018-04-11 12:48:02,538 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-04-11 12:48:02,540 INFO L271 PluginConnector]: Initializing CDTParser... [2018-04-11 12:48:02,540 INFO L276 PluginConnector]: CDTParser initialized [2018-04-11 12:48:02,540 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,831 INFO L225 CDTParser]: Created temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGd319d343a [2018-04-11 12:48:02,967 INFO L287 CDTParser]: IsIndexed: true [2018-04-11 12:48:02,967 INFO L288 CDTParser]: Found 1 translation units. [2018-04-11 12:48:02,968 INFO L168 CDTParser]: Scanning cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,974 INFO L210 ultiparseSymbolTable]: Include resolver: [2018-04-11 12:48:02,974 INFO L215 ultiparseSymbolTable]: [2018-04-11 12:48:02,975 INFO L218 ultiparseSymbolTable]: Function table: [2018-04-11 12:48:02,975 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____bswap_32 ('__bswap_32') in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,975 INFO L221 ultiparseSymbolTable]: Function definition of null ('main') in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,975 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__ ('') in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,975 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____bswap_64 ('__bswap_64') in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,975 INFO L227 ultiparseSymbolTable]: Global variable table: [2018-04-11 12:48:02,975 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__fsblkcnt_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,975 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__time_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,975 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____suseconds_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,976 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____rlim64_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,976 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__uid_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,976 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____qaddr_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,976 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__u_int in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,976 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____blksize_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,976 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__blksize_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,976 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__pthread_rwlock_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,976 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__pthread_key_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,976 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____int32_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,976 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____uint32_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,977 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____syscall_ulong_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,977 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____id_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,977 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__div_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,977 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____caddr_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,977 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____u_short in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,977 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____dev_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,977 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__key_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,977 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__caddr_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,977 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__mode_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,977 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__fsfilcnt_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,977 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__int32_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,978 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__fd_set in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,978 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__pid_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,978 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__ulong in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,978 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____blkcnt64_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,978 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____int16_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,978 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__u_short in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,978 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__gid_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,978 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__off_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,978 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____socklen_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,978 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____nlink_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,978 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____ssize_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,978 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__timer_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,978 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____mode_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__u_int32_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__u_char in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__blkcnt_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____gid_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____u_long in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____intptr_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__pthread_once_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__pthread_mutexattr_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__size_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____timer_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__pthread_attr_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____off64_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____fsblkcnt64_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__int16_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____pid_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____quad_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____pthread_list_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,979 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__lldiv_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__wchar_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____rlim_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____u_char in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__pthread_barrier_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____u_quad_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__dev_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____uint8_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__id_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__u_int8_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____u_int in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____useconds_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__loff_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____daddr_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__clockid_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____clockid_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__fsid_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__quad_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__pthread_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,980 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__u_int16_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,981 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__pthread_cond_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,981 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__pthread_spinlock_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,981 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____fd_mask in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,981 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__pthread_condattr_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,981 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____blkcnt_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,981 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____clock_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,981 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____uid_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,981 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____loff_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,981 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____ino64_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,981 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__suseconds_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,981 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____ino_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,982 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____sigset_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,982 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____sig_atomic_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,982 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____fsid_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,982 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__nlink_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,982 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____off_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,982 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__clock_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,982 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__uint in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,982 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__u_long in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,982 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__fd_mask in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,982 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____uint64_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,982 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__ssize_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,982 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__pthread_rwlockattr_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,983 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____fsword_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,983 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__u_int64_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,983 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__sigset_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,983 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____int8_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,983 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____uint16_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,983 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__daddr_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,983 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____WAIT_STATUS in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,983 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__u_quad_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,983 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__ushort in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,983 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____time_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,983 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__int64_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,984 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____fsfilcnt_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,984 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____syscall_slong_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,984 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____fsblkcnt_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,984 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__pthread_barrierattr_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,984 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__int8_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,984 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__register_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,984 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____fsfilcnt64_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,984 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__pthread_mutex_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,984 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__ino_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,984 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____key_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,984 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____int64_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,985 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i__ldiv_t in cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:02,998 INFO L330 CDTParser]: Deleted temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGd319d343a [2018-04-11 12:48:03,000 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-04-11 12:48:03,001 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-04-11 12:48:03,002 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-04-11 12:48:03,002 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-04-11 12:48:03,006 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-04-11 12:48:03,006 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 11.04 12:48:02" (1/1) ... [2018-04-11 12:48:03,008 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@270d2e7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:48:03, skipping insertion in model container [2018-04-11 12:48:03,008 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 11.04 12:48:02" (1/1) ... [2018-04-11 12:48:03,019 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-11 12:48:03,039 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-11 12:48:03,180 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-11 12:48:03,217 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-11 12:48:03,222 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-11 12:48:03,252 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:48:03 WrapperNode [2018-04-11 12:48:03,252 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-04-11 12:48:03,252 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-04-11 12:48:03,252 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-04-11 12:48:03,252 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-04-11 12:48:03,259 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:48:03" (1/1) ... [2018-04-11 12:48:03,259 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:48:03" (1/1) ... [2018-04-11 12:48:03,270 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:48:03" (1/1) ... [2018-04-11 12:48:03,270 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:48:03" (1/1) ... [2018-04-11 12:48:03,279 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:48:03" (1/1) ... [2018-04-11 12:48:03,284 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:48:03" (1/1) ... [2018-04-11 12:48:03,287 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:48:03" (1/1) ... [2018-04-11 12:48:03,291 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-04-11 12:48:03,291 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-04-11 12:48:03,291 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-04-11 12:48:03,291 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-04-11 12:48:03,292 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:48:03" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-11 12:48:03,385 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-04-11 12:48:03,385 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-04-11 12:48:03,385 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-11 12:48:03,385 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-11 12:48:03,385 INFO L136 BoogieDeclarations]: Found implementation of procedure cstrcat [2018-04-11 12:48:03,386 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-04-11 12:48:03,386 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-11 12:48:03,386 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fcstrcat_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-11 12:48:03,386 INFO L128 BoogieDeclarations]: Found specification of procedure __ctype_get_mb_cur_max [2018-04-11 12:48:03,386 INFO L128 BoogieDeclarations]: Found specification of procedure atof [2018-04-11 12:48:03,386 INFO L128 BoogieDeclarations]: Found specification of procedure atoi [2018-04-11 12:48:03,386 INFO L128 BoogieDeclarations]: Found specification of procedure atol [2018-04-11 12:48:03,386 INFO L128 BoogieDeclarations]: Found specification of procedure atoll [2018-04-11 12:48:03,386 INFO L128 BoogieDeclarations]: Found specification of procedure strtod [2018-04-11 12:48:03,387 INFO L128 BoogieDeclarations]: Found specification of procedure strtof [2018-04-11 12:48:03,387 INFO L128 BoogieDeclarations]: Found specification of procedure strtold [2018-04-11 12:48:03,387 INFO L128 BoogieDeclarations]: Found specification of procedure strtol [2018-04-11 12:48:03,387 INFO L128 BoogieDeclarations]: Found specification of procedure strtoul [2018-04-11 12:48:03,387 INFO L128 BoogieDeclarations]: Found specification of procedure strtoq [2018-04-11 12:48:03,387 INFO L128 BoogieDeclarations]: Found specification of procedure strtouq [2018-04-11 12:48:03,387 INFO L128 BoogieDeclarations]: Found specification of procedure strtoll [2018-04-11 12:48:03,387 INFO L128 BoogieDeclarations]: Found specification of procedure strtoull [2018-04-11 12:48:03,388 INFO L128 BoogieDeclarations]: Found specification of procedure l64a [2018-04-11 12:48:03,388 INFO L128 BoogieDeclarations]: Found specification of procedure a64l [2018-04-11 12:48:03,388 INFO L128 BoogieDeclarations]: Found specification of procedure select [2018-04-11 12:48:03,388 INFO L128 BoogieDeclarations]: Found specification of procedure pselect [2018-04-11 12:48:03,388 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_major [2018-04-11 12:48:03,388 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_minor [2018-04-11 12:48:03,388 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_makedev [2018-04-11 12:48:03,388 INFO L128 BoogieDeclarations]: Found specification of procedure random [2018-04-11 12:48:03,389 INFO L128 BoogieDeclarations]: Found specification of procedure srandom [2018-04-11 12:48:03,389 INFO L128 BoogieDeclarations]: Found specification of procedure initstate [2018-04-11 12:48:03,389 INFO L128 BoogieDeclarations]: Found specification of procedure setstate [2018-04-11 12:48:03,389 INFO L128 BoogieDeclarations]: Found specification of procedure random_r [2018-04-11 12:48:03,389 INFO L128 BoogieDeclarations]: Found specification of procedure srandom_r [2018-04-11 12:48:03,389 INFO L128 BoogieDeclarations]: Found specification of procedure initstate_r [2018-04-11 12:48:03,389 INFO L128 BoogieDeclarations]: Found specification of procedure setstate_r [2018-04-11 12:48:03,389 INFO L128 BoogieDeclarations]: Found specification of procedure rand [2018-04-11 12:48:03,389 INFO L128 BoogieDeclarations]: Found specification of procedure srand [2018-04-11 12:48:03,390 INFO L128 BoogieDeclarations]: Found specification of procedure rand_r [2018-04-11 12:48:03,390 INFO L128 BoogieDeclarations]: Found specification of procedure drand48 [2018-04-11 12:48:03,390 INFO L128 BoogieDeclarations]: Found specification of procedure erand48 [2018-04-11 12:48:03,390 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48 [2018-04-11 12:48:03,390 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48 [2018-04-11 12:48:03,390 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48 [2018-04-11 12:48:03,390 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48 [2018-04-11 12:48:03,390 INFO L128 BoogieDeclarations]: Found specification of procedure srand48 [2018-04-11 12:48:03,391 INFO L128 BoogieDeclarations]: Found specification of procedure seed48 [2018-04-11 12:48:03,391 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48 [2018-04-11 12:48:03,391 INFO L128 BoogieDeclarations]: Found specification of procedure drand48_r [2018-04-11 12:48:03,391 INFO L128 BoogieDeclarations]: Found specification of procedure erand48_r [2018-04-11 12:48:03,391 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48_r [2018-04-11 12:48:03,391 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48_r [2018-04-11 12:48:03,391 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48_r [2018-04-11 12:48:03,391 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48_r [2018-04-11 12:48:03,391 INFO L128 BoogieDeclarations]: Found specification of procedure srand48_r [2018-04-11 12:48:03,391 INFO L128 BoogieDeclarations]: Found specification of procedure seed48_r [2018-04-11 12:48:03,392 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48_r [2018-04-11 12:48:03,392 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-04-11 12:48:03,392 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-04-11 12:48:03,392 INFO L128 BoogieDeclarations]: Found specification of procedure realloc [2018-04-11 12:48:03,392 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-04-11 12:48:03,392 INFO L128 BoogieDeclarations]: Found specification of procedure cfree [2018-04-11 12:48:03,392 INFO L128 BoogieDeclarations]: Found specification of procedure alloca [2018-04-11 12:48:03,392 INFO L128 BoogieDeclarations]: Found specification of procedure valloc [2018-04-11 12:48:03,392 INFO L128 BoogieDeclarations]: Found specification of procedure posix_memalign [2018-04-11 12:48:03,393 INFO L128 BoogieDeclarations]: Found specification of procedure abort [2018-04-11 12:48:03,393 INFO L128 BoogieDeclarations]: Found specification of procedure atexit [2018-04-11 12:48:03,393 INFO L128 BoogieDeclarations]: Found specification of procedure on_exit [2018-04-11 12:48:03,393 INFO L128 BoogieDeclarations]: Found specification of procedure exit [2018-04-11 12:48:03,393 INFO L128 BoogieDeclarations]: Found specification of procedure _Exit [2018-04-11 12:48:03,393 INFO L128 BoogieDeclarations]: Found specification of procedure getenv [2018-04-11 12:48:03,393 INFO L128 BoogieDeclarations]: Found specification of procedure putenv [2018-04-11 12:48:03,393 INFO L128 BoogieDeclarations]: Found specification of procedure setenv [2018-04-11 12:48:03,393 INFO L128 BoogieDeclarations]: Found specification of procedure unsetenv [2018-04-11 12:48:03,393 INFO L128 BoogieDeclarations]: Found specification of procedure clearenv [2018-04-11 12:48:03,394 INFO L128 BoogieDeclarations]: Found specification of procedure mktemp [2018-04-11 12:48:03,394 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemp [2018-04-11 12:48:03,394 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemps [2018-04-11 12:48:03,394 INFO L128 BoogieDeclarations]: Found specification of procedure mkdtemp [2018-04-11 12:48:03,394 INFO L128 BoogieDeclarations]: Found specification of procedure system [2018-04-11 12:48:03,394 INFO L128 BoogieDeclarations]: Found specification of procedure realpath [2018-04-11 12:48:03,394 INFO L128 BoogieDeclarations]: Found specification of procedure bsearch [2018-04-11 12:48:03,394 INFO L128 BoogieDeclarations]: Found specification of procedure qsort [2018-04-11 12:48:03,394 INFO L128 BoogieDeclarations]: Found specification of procedure abs [2018-04-11 12:48:03,394 INFO L128 BoogieDeclarations]: Found specification of procedure labs [2018-04-11 12:48:03,395 INFO L128 BoogieDeclarations]: Found specification of procedure llabs [2018-04-11 12:48:03,395 INFO L128 BoogieDeclarations]: Found specification of procedure div [2018-04-11 12:48:03,395 INFO L128 BoogieDeclarations]: Found specification of procedure ldiv [2018-04-11 12:48:03,395 INFO L128 BoogieDeclarations]: Found specification of procedure lldiv [2018-04-11 12:48:03,395 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt [2018-04-11 12:48:03,395 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt [2018-04-11 12:48:03,395 INFO L128 BoogieDeclarations]: Found specification of procedure gcvt [2018-04-11 12:48:03,395 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt [2018-04-11 12:48:03,395 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt [2018-04-11 12:48:03,395 INFO L128 BoogieDeclarations]: Found specification of procedure qgcvt [2018-04-11 12:48:03,396 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt_r [2018-04-11 12:48:03,396 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt_r [2018-04-11 12:48:03,396 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt_r [2018-04-11 12:48:03,396 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt_r [2018-04-11 12:48:03,396 INFO L128 BoogieDeclarations]: Found specification of procedure mblen [2018-04-11 12:48:03,396 INFO L128 BoogieDeclarations]: Found specification of procedure mbtowc [2018-04-11 12:48:03,396 INFO L128 BoogieDeclarations]: Found specification of procedure wctomb [2018-04-11 12:48:03,396 INFO L128 BoogieDeclarations]: Found specification of procedure mbstowcs [2018-04-11 12:48:03,396 INFO L128 BoogieDeclarations]: Found specification of procedure wcstombs [2018-04-11 12:48:03,396 INFO L128 BoogieDeclarations]: Found specification of procedure rpmatch [2018-04-11 12:48:03,396 INFO L128 BoogieDeclarations]: Found specification of procedure getsubopt [2018-04-11 12:48:03,397 INFO L128 BoogieDeclarations]: Found specification of procedure getloadavg [2018-04-11 12:48:03,397 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-04-11 12:48:03,397 INFO L128 BoogieDeclarations]: Found specification of procedure cstrcat [2018-04-11 12:48:03,397 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-04-11 12:48:03,397 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-04-11 12:48:03,397 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-04-11 12:48:03,397 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-04-11 12:48:03,397 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-04-11 12:48:03,397 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-04-11 12:48:03,397 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-04-11 12:48:03,398 INFO L128 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-04-11 12:48:03,648 INFO L259 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-04-11 12:48:03,649 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.04 12:48:03 BoogieIcfgContainer [2018-04-11 12:48:03,649 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-04-11 12:48:03,649 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-04-11 12:48:03,649 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-04-11 12:48:03,651 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-04-11 12:48:03,651 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 11.04 12:48:02" (1/3) ... [2018-04-11 12:48:03,652 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3d9b08f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.04 12:48:03, skipping insertion in model container [2018-04-11 12:48:03,652 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:48:03" (2/3) ... [2018-04-11 12:48:03,652 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3d9b08f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.04 12:48:03, skipping insertion in model container [2018-04-11 12:48:03,652 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.04 12:48:03" (3/3) ... [2018-04-11 12:48:03,653 INFO L107 eAbstractionObserver]: Analyzing ICFG cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:48:03,658 INFO L131 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_TreeInterpolation Determinization: PREDICATE_ABSTRACTION [2018-04-11 12:48:03,663 INFO L143 ceAbstractionStarter]: Appying trace abstraction to program that has 11 error locations. [2018-04-11 12:48:03,688 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-04-11 12:48:03,689 INFO L369 AbstractCegarLoop]: Interprodecural is true [2018-04-11 12:48:03,689 INFO L370 AbstractCegarLoop]: Hoare is false [2018-04-11 12:48:03,689 INFO L371 AbstractCegarLoop]: Compute interpolants for Craig_TreeInterpolation [2018-04-11 12:48:03,689 INFO L372 AbstractCegarLoop]: Backedges is CANONICAL [2018-04-11 12:48:03,689 INFO L373 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-04-11 12:48:03,689 INFO L374 AbstractCegarLoop]: Difference is false [2018-04-11 12:48:03,689 INFO L375 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-04-11 12:48:03,689 INFO L380 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-04-11 12:48:03,690 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-04-11 12:48:03,698 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states. [2018-04-11 12:48:03,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-04-11 12:48:03,832 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:03,832 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:03,832 INFO L408 AbstractCegarLoop]: === Iteration 1 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:03,835 INFO L82 PathProgramCache]: Analyzing trace with hash -58907273, now seen corresponding path program 1 times [2018-04-11 12:48:03,866 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:03,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:03,894 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:03,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:03,943 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:03,943 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-11 12:48:03,944 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:03,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:03,944 INFO L182 omatonBuilderFactory]: Interpolants [52#true, 53#false, 54#(<= main_~length1~0 1), 55#(and (<= (+ main_~length1~0 1) main_~length2~0) (<= 2 main_~length2~0)), 56#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0))] [2018-04-11 12:48:03,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:03,945 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-11 12:48:03,954 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-11 12:48:03,954 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-04-11 12:48:03,956 INFO L87 Difference]: Start difference. First operand 49 states. Second operand 5 states. [2018-04-11 12:48:04,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:04,092 INFO L93 Difference]: Finished difference Result 91 states and 101 transitions. [2018-04-11 12:48:04,094 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-11 12:48:04,095 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 11 [2018-04-11 12:48:04,095 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:04,102 INFO L225 Difference]: With dead ends: 91 [2018-04-11 12:48:04,102 INFO L226 Difference]: Without dead ends: 86 [2018-04-11 12:48:04,103 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-04-11 12:48:04,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states. [2018-04-11 12:48:04,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 49. [2018-04-11 12:48:04,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-04-11 12:48:04,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 56 transitions. [2018-04-11 12:48:04,132 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 56 transitions. Word has length 11 [2018-04-11 12:48:04,132 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:04,132 INFO L459 AbstractCegarLoop]: Abstraction has 49 states and 56 transitions. [2018-04-11 12:48:04,132 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-11 12:48:04,132 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 56 transitions. [2018-04-11 12:48:04,132 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-04-11 12:48:04,132 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:04,133 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:04,133 INFO L408 AbstractCegarLoop]: === Iteration 2 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:04,133 INFO L82 PathProgramCache]: Analyzing trace with hash -58905351, now seen corresponding path program 1 times [2018-04-11 12:48:04,134 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:04,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:04,143 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:04,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,157 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:04,157 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-04-11 12:48:04,157 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:04,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,158 INFO L182 omatonBuilderFactory]: Interpolants [201#true, 202#false, 203#(= |#valid| |old(#valid)|)] [2018-04-11 12:48:04,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,158 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-11 12:48:04,159 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-11 12:48:04,159 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-11 12:48:04,159 INFO L87 Difference]: Start difference. First operand 49 states and 56 transitions. Second operand 3 states. [2018-04-11 12:48:04,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:04,195 INFO L93 Difference]: Finished difference Result 50 states and 56 transitions. [2018-04-11 12:48:04,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-11 12:48:04,195 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-04-11 12:48:04,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:04,196 INFO L225 Difference]: With dead ends: 50 [2018-04-11 12:48:04,196 INFO L226 Difference]: Without dead ends: 49 [2018-04-11 12:48:04,197 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-11 12:48:04,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-04-11 12:48:04,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 46. [2018-04-11 12:48:04,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-04-11 12:48:04,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 50 transitions. [2018-04-11 12:48:04,201 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 50 transitions. Word has length 11 [2018-04-11 12:48:04,201 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:04,201 INFO L459 AbstractCegarLoop]: Abstraction has 46 states and 50 transitions. [2018-04-11 12:48:04,201 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-11 12:48:04,201 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 50 transitions. [2018-04-11 12:48:04,202 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-04-11 12:48:04,202 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:04,202 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:04,202 INFO L408 AbstractCegarLoop]: === Iteration 3 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:04,202 INFO L82 PathProgramCache]: Analyzing trace with hash -2034104824, now seen corresponding path program 1 times [2018-04-11 12:48:04,203 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:04,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:04,219 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:04,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,262 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:04,262 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-11 12:48:04,262 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:04,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,262 INFO L182 omatonBuilderFactory]: Interpolants [300#true, 301#false, 302#(= (select |#valid| |main_#t~malloc10.base|) 1), 303#(= 1 (select |#valid| main_~nondetString1~0.base))] [2018-04-11 12:48:04,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,262 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-11 12:48:04,262 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-11 12:48:04,262 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-11 12:48:04,263 INFO L87 Difference]: Start difference. First operand 46 states and 50 transitions. Second operand 4 states. [2018-04-11 12:48:04,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:04,316 INFO L93 Difference]: Finished difference Result 45 states and 49 transitions. [2018-04-11 12:48:04,316 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-11 12:48:04,316 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2018-04-11 12:48:04,316 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:04,317 INFO L225 Difference]: With dead ends: 45 [2018-04-11 12:48:04,317 INFO L226 Difference]: Without dead ends: 45 [2018-04-11 12:48:04,317 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-11 12:48:04,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2018-04-11 12:48:04,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2018-04-11 12:48:04,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-04-11 12:48:04,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 49 transitions. [2018-04-11 12:48:04,319 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 49 transitions. Word has length 15 [2018-04-11 12:48:04,319 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:04,319 INFO L459 AbstractCegarLoop]: Abstraction has 45 states and 49 transitions. [2018-04-11 12:48:04,320 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-11 12:48:04,320 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 49 transitions. [2018-04-11 12:48:04,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-04-11 12:48:04,320 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:04,320 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:04,320 INFO L408 AbstractCegarLoop]: === Iteration 4 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:04,320 INFO L82 PathProgramCache]: Analyzing trace with hash -2034104823, now seen corresponding path program 1 times [2018-04-11 12:48:04,321 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:04,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:04,333 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:04,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,398 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:04,398 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-11 12:48:04,398 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:04,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,398 INFO L182 omatonBuilderFactory]: Interpolants [400#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 401#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 396#true, 397#false, 398#(<= 1 main_~length1~0), 399#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length1~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1))] [2018-04-11 12:48:04,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,399 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-11 12:48:04,399 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-11 12:48:04,399 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-04-11 12:48:04,399 INFO L87 Difference]: Start difference. First operand 45 states and 49 transitions. Second operand 6 states. [2018-04-11 12:48:04,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:04,463 INFO L93 Difference]: Finished difference Result 44 states and 48 transitions. [2018-04-11 12:48:04,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-11 12:48:04,463 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 15 [2018-04-11 12:48:04,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:04,464 INFO L225 Difference]: With dead ends: 44 [2018-04-11 12:48:04,464 INFO L226 Difference]: Without dead ends: 44 [2018-04-11 12:48:04,464 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2018-04-11 12:48:04,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-04-11 12:48:04,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2018-04-11 12:48:04,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-04-11 12:48:04,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 48 transitions. [2018-04-11 12:48:04,466 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 48 transitions. Word has length 15 [2018-04-11 12:48:04,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:04,467 INFO L459 AbstractCegarLoop]: Abstraction has 44 states and 48 transitions. [2018-04-11 12:48:04,467 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-11 12:48:04,467 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 48 transitions. [2018-04-11 12:48:04,467 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-04-11 12:48:04,467 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:04,467 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:04,468 INFO L408 AbstractCegarLoop]: === Iteration 5 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:04,468 INFO L82 PathProgramCache]: Analyzing trace with hash 1367259900, now seen corresponding path program 1 times [2018-04-11 12:48:04,468 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:04,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:04,479 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:04,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,511 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:04,511 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-11 12:48:04,511 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:04,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,512 INFO L182 omatonBuilderFactory]: Interpolants [492#true, 493#false, 494#(= 1 (select |#valid| |main_#t~malloc11.base|)), 495#(= 1 (select |#valid| main_~nondetString2~0.base))] [2018-04-11 12:48:04,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,512 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-11 12:48:04,512 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-11 12:48:04,512 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-11 12:48:04,512 INFO L87 Difference]: Start difference. First operand 44 states and 48 transitions. Second operand 4 states. [2018-04-11 12:48:04,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:04,546 INFO L93 Difference]: Finished difference Result 43 states and 47 transitions. [2018-04-11 12:48:04,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-11 12:48:04,546 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-04-11 12:48:04,546 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:04,547 INFO L225 Difference]: With dead ends: 43 [2018-04-11 12:48:04,547 INFO L226 Difference]: Without dead ends: 43 [2018-04-11 12:48:04,547 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-11 12:48:04,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2018-04-11 12:48:04,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 43. [2018-04-11 12:48:04,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2018-04-11 12:48:04,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 47 transitions. [2018-04-11 12:48:04,550 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 47 transitions. Word has length 16 [2018-04-11 12:48:04,550 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:04,550 INFO L459 AbstractCegarLoop]: Abstraction has 43 states and 47 transitions. [2018-04-11 12:48:04,550 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-11 12:48:04,551 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 47 transitions. [2018-04-11 12:48:04,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-04-11 12:48:04,551 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:04,551 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:04,551 INFO L408 AbstractCegarLoop]: === Iteration 6 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:04,551 INFO L82 PathProgramCache]: Analyzing trace with hash 1367259901, now seen corresponding path program 1 times [2018-04-11 12:48:04,552 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:04,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:04,563 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:04,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,620 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:04,620 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-11 12:48:04,620 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:04,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,620 INFO L182 omatonBuilderFactory]: Interpolants [584#true, 585#false, 586#(<= 2 main_~length2~0), 587#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 588#(and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 589#(and (= main_~nondetString2~0.offset 0) (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))] [2018-04-11 12:48:04,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,621 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-11 12:48:04,621 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-11 12:48:04,621 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-04-11 12:48:04,621 INFO L87 Difference]: Start difference. First operand 43 states and 47 transitions. Second operand 6 states. [2018-04-11 12:48:04,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:04,747 INFO L93 Difference]: Finished difference Result 58 states and 62 transitions. [2018-04-11 12:48:04,747 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-11 12:48:04,747 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 16 [2018-04-11 12:48:04,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:04,747 INFO L225 Difference]: With dead ends: 58 [2018-04-11 12:48:04,747 INFO L226 Difference]: Without dead ends: 58 [2018-04-11 12:48:04,748 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-04-11 12:48:04,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-04-11 12:48:04,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 50. [2018-04-11 12:48:04,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-04-11 12:48:04,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-04-11 12:48:04,750 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 16 [2018-04-11 12:48:04,750 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:04,750 INFO L459 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-04-11 12:48:04,750 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-11 12:48:04,750 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-04-11 12:48:04,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-04-11 12:48:04,750 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:04,750 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:04,750 INFO L408 AbstractCegarLoop]: === Iteration 7 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:04,751 INFO L82 PathProgramCache]: Analyzing trace with hash 557913275, now seen corresponding path program 1 times [2018-04-11 12:48:04,751 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:04,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:04,761 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:04,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,818 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:04,818 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-11 12:48:04,819 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:04,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,819 INFO L182 omatonBuilderFactory]: Interpolants [704#true, 705#false, 706#(<= 1 main_~length3~0), 707#(and (<= 1 main_~length3~0) (<= main_~length3~0 main_~length2~0)), 708#(and (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= main_~length3~0 (select |#length| |main_#t~malloc11.base|))), 709#(and (= main_~nondetString2~0.offset 0) (<= main_~length3~0 (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))] [2018-04-11 12:48:04,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,819 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-11 12:48:04,819 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-11 12:48:04,819 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-04-11 12:48:04,819 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 6 states. [2018-04-11 12:48:04,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:04,880 INFO L93 Difference]: Finished difference Result 49 states and 53 transitions. [2018-04-11 12:48:04,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-11 12:48:04,880 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 16 [2018-04-11 12:48:04,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:04,883 INFO L225 Difference]: With dead ends: 49 [2018-04-11 12:48:04,883 INFO L226 Difference]: Without dead ends: 49 [2018-04-11 12:48:04,883 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2018-04-11 12:48:04,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-04-11 12:48:04,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 42. [2018-04-11 12:48:04,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-04-11 12:48:04,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 46 transitions. [2018-04-11 12:48:04,886 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 46 transitions. Word has length 16 [2018-04-11 12:48:04,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:04,886 INFO L459 AbstractCegarLoop]: Abstraction has 42 states and 46 transitions. [2018-04-11 12:48:04,886 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-11 12:48:04,886 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 46 transitions. [2018-04-11 12:48:04,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-04-11 12:48:04,887 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:04,887 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:04,887 INFO L408 AbstractCegarLoop]: === Iteration 8 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:04,887 INFO L82 PathProgramCache]: Analyzing trace with hash -1383367435, now seen corresponding path program 1 times [2018-04-11 12:48:04,888 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:04,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:04,897 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:04,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,923 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:04,923 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-11 12:48:04,923 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:04,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,923 INFO L182 omatonBuilderFactory]: Interpolants [807#true, 808#false, 809#(= 1 (select |#valid| main_~nondetString2~0.base)), 810#(= 1 (select |#valid| |cstrcat_#in~s1.base|)), 811#(= 1 (select |#valid| cstrcat_~s~0.base))] [2018-04-11 12:48:04,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:04,924 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-11 12:48:04,924 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-11 12:48:04,924 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-04-11 12:48:04,924 INFO L87 Difference]: Start difference. First operand 42 states and 46 transitions. Second operand 5 states. [2018-04-11 12:48:04,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:04,972 INFO L93 Difference]: Finished difference Result 41 states and 45 transitions. [2018-04-11 12:48:04,972 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-11 12:48:04,972 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 20 [2018-04-11 12:48:04,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:04,973 INFO L225 Difference]: With dead ends: 41 [2018-04-11 12:48:04,973 INFO L226 Difference]: Without dead ends: 41 [2018-04-11 12:48:04,973 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-04-11 12:48:04,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2018-04-11 12:48:04,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 41. [2018-04-11 12:48:04,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-04-11 12:48:04,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 45 transitions. [2018-04-11 12:48:04,975 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 45 transitions. Word has length 20 [2018-04-11 12:48:04,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:04,976 INFO L459 AbstractCegarLoop]: Abstraction has 41 states and 45 transitions. [2018-04-11 12:48:04,976 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-11 12:48:04,976 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 45 transitions. [2018-04-11 12:48:04,976 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-04-11 12:48:04,976 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:04,976 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:04,976 INFO L408 AbstractCegarLoop]: === Iteration 9 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:04,977 INFO L82 PathProgramCache]: Analyzing trace with hash -1383367434, now seen corresponding path program 1 times [2018-04-11 12:48:04,977 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:04,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:04,986 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:05,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,031 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:05,031 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-04-11 12:48:05,031 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:05,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,035 INFO L182 omatonBuilderFactory]: Interpolants [896#true, 897#false, 898#(<= 2 main_~length2~0), 899#(and (<= 2 (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 900#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base))), 901#(and (<= 2 (select |#length| |cstrcat_#in~s1.base|)) (= 0 |cstrcat_#in~s1.offset|)), 902#(and (<= 2 (select |#length| cstrcat_~s~0.base)) (= cstrcat_~s~0.offset 0))] [2018-04-11 12:48:05,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,035 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-04-11 12:48:05,035 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-04-11 12:48:05,035 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-04-11 12:48:05,035 INFO L87 Difference]: Start difference. First operand 41 states and 45 transitions. Second operand 7 states. [2018-04-11 12:48:05,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:05,103 INFO L93 Difference]: Finished difference Result 46 states and 51 transitions. [2018-04-11 12:48:05,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-11 12:48:05,103 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 20 [2018-04-11 12:48:05,103 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:05,103 INFO L225 Difference]: With dead ends: 46 [2018-04-11 12:48:05,103 INFO L226 Difference]: Without dead ends: 46 [2018-04-11 12:48:05,104 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2018-04-11 12:48:05,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2018-04-11 12:48:05,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 43. [2018-04-11 12:48:05,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2018-04-11 12:48:05,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 47 transitions. [2018-04-11 12:48:05,106 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 47 transitions. Word has length 20 [2018-04-11 12:48:05,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:05,106 INFO L459 AbstractCegarLoop]: Abstraction has 43 states and 47 transitions. [2018-04-11 12:48:05,106 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-04-11 12:48:05,106 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 47 transitions. [2018-04-11 12:48:05,107 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-04-11 12:48:05,107 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:05,107 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:05,107 INFO L408 AbstractCegarLoop]: === Iteration 10 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:05,107 INFO L82 PathProgramCache]: Analyzing trace with hash -1688021460, now seen corresponding path program 1 times [2018-04-11 12:48:05,108 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:05,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:05,116 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:05,172 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,172 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:05,172 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-04-11 12:48:05,172 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:05,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,172 INFO L182 omatonBuilderFactory]: Interpolants [1000#true, 1001#false, 1002#(<= 2 main_~length2~0), 1003#(and (<= 2 (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 1004#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base))), 1005#(and (<= 2 (select |#length| |cstrcat_#in~s1.base|)) (= 0 |cstrcat_#in~s1.offset|)), 1006#(and (<= 2 (select |#length| cstrcat_~s~0.base)) (= cstrcat_~s~0.offset 0)), 1007#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))] [2018-04-11 12:48:05,172 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,173 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-11 12:48:05,173 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-11 12:48:05,173 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-04-11 12:48:05,173 INFO L87 Difference]: Start difference. First operand 43 states and 47 transitions. Second operand 8 states. [2018-04-11 12:48:05,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:05,333 INFO L93 Difference]: Finished difference Result 61 states and 68 transitions. [2018-04-11 12:48:05,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-04-11 12:48:05,333 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 23 [2018-04-11 12:48:05,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:05,335 INFO L225 Difference]: With dead ends: 61 [2018-04-11 12:48:05,335 INFO L226 Difference]: Without dead ends: 61 [2018-04-11 12:48:05,335 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2018-04-11 12:48:05,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-04-11 12:48:05,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 46. [2018-04-11 12:48:05,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-04-11 12:48:05,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 51 transitions. [2018-04-11 12:48:05,338 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 51 transitions. Word has length 23 [2018-04-11 12:48:05,338 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:05,338 INFO L459 AbstractCegarLoop]: Abstraction has 46 states and 51 transitions. [2018-04-11 12:48:05,338 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-11 12:48:05,338 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 51 transitions. [2018-04-11 12:48:05,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-04-11 12:48:05,339 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:05,339 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:05,339 INFO L408 AbstractCegarLoop]: === Iteration 11 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:05,339 INFO L82 PathProgramCache]: Analyzing trace with hash -789102402, now seen corresponding path program 1 times [2018-04-11 12:48:05,339 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:05,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:05,346 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:05,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,384 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:05,384 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-11 12:48:05,384 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:05,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,385 INFO L182 omatonBuilderFactory]: Interpolants [1125#true, 1126#false, 1127#(= 1 (select |#valid| main_~nondetString1~0.base)), 1128#(= 1 (select |#valid| |cstrcat_#in~s2.base|)), 1129#(= 1 (select |#valid| cstrcat_~s2.base)), 1130#(= 1 (select |#valid| |cstrcat_#t~post5.base|))] [2018-04-11 12:48:05,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,385 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-11 12:48:05,385 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-11 12:48:05,385 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-04-11 12:48:05,385 INFO L87 Difference]: Start difference. First operand 46 states and 51 transitions. Second operand 6 states. [2018-04-11 12:48:05,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:05,436 INFO L93 Difference]: Finished difference Result 45 states and 50 transitions. [2018-04-11 12:48:05,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-11 12:48:05,437 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 24 [2018-04-11 12:48:05,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:05,437 INFO L225 Difference]: With dead ends: 45 [2018-04-11 12:48:05,437 INFO L226 Difference]: Without dead ends: 45 [2018-04-11 12:48:05,438 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-04-11 12:48:05,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2018-04-11 12:48:05,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2018-04-11 12:48:05,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-04-11 12:48:05,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 50 transitions. [2018-04-11 12:48:05,440 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 50 transitions. Word has length 24 [2018-04-11 12:48:05,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:05,440 INFO L459 AbstractCegarLoop]: Abstraction has 45 states and 50 transitions. [2018-04-11 12:48:05,441 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-11 12:48:05,441 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 50 transitions. [2018-04-11 12:48:05,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-04-11 12:48:05,441 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:05,441 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:05,441 INFO L408 AbstractCegarLoop]: === Iteration 12 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:05,442 INFO L82 PathProgramCache]: Analyzing trace with hash -789102401, now seen corresponding path program 1 times [2018-04-11 12:48:05,442 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:05,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:05,457 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:05,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,544 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:05,544 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-04-11 12:48:05,544 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:05,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,544 INFO L182 omatonBuilderFactory]: Interpolants [1232#(and (= 0 cstrcat_~s2.offset) (<= 1 (select |#length| cstrcat_~s2.base))), 1233#(and (= |cstrcat_#t~post5.offset| 0) (<= 1 (select |#length| |cstrcat_#t~post5.base|))), 1225#true, 1226#false, 1227#(<= 1 main_~length1~0), 1228#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length1~0)), 1229#(and (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 1230#(and (<= (+ main_~nondetString1~0.offset 1) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 1231#(and (= 0 |cstrcat_#in~s2.offset|) (<= 1 (select |#length| |cstrcat_#in~s2.base|)))] [2018-04-11 12:48:05,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,545 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-11 12:48:05,545 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-11 12:48:05,545 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-04-11 12:48:05,545 INFO L87 Difference]: Start difference. First operand 45 states and 50 transitions. Second operand 9 states. [2018-04-11 12:48:05,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:05,627 INFO L93 Difference]: Finished difference Result 52 states and 58 transitions. [2018-04-11 12:48:05,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-11 12:48:05,628 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 24 [2018-04-11 12:48:05,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:05,628 INFO L225 Difference]: With dead ends: 52 [2018-04-11 12:48:05,628 INFO L226 Difference]: Without dead ends: 52 [2018-04-11 12:48:05,628 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=43, Invalid=139, Unknown=0, NotChecked=0, Total=182 [2018-04-11 12:48:05,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-04-11 12:48:05,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 48. [2018-04-11 12:48:05,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-04-11 12:48:05,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 53 transitions. [2018-04-11 12:48:05,630 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 53 transitions. Word has length 24 [2018-04-11 12:48:05,630 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:05,630 INFO L459 AbstractCegarLoop]: Abstraction has 48 states and 53 transitions. [2018-04-11 12:48:05,630 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-11 12:48:05,631 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 53 transitions. [2018-04-11 12:48:05,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-04-11 12:48:05,631 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:05,631 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:05,631 INFO L408 AbstractCegarLoop]: === Iteration 13 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:05,631 INFO L82 PathProgramCache]: Analyzing trace with hash 1307629356, now seen corresponding path program 1 times [2018-04-11 12:48:05,632 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:05,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:05,640 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:05,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,668 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:05,668 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-11 12:48:05,668 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:05,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,668 INFO L182 omatonBuilderFactory]: Interpolants [1344#true, 1345#false, 1346#(= 1 (select |#valid| main_~nondetString2~0.base)), 1347#(= 1 (select |#valid| |cstrcat_#in~s1.base|)), 1348#(= 1 (select |#valid| cstrcat_~s~0.base)), 1349#(= 1 (select |#valid| |cstrcat_#t~post4.base|))] [2018-04-11 12:48:05,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,669 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-11 12:48:05,669 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-11 12:48:05,669 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-04-11 12:48:05,669 INFO L87 Difference]: Start difference. First operand 48 states and 53 transitions. Second operand 6 states. [2018-04-11 12:48:05,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:05,718 INFO L93 Difference]: Finished difference Result 47 states and 52 transitions. [2018-04-11 12:48:05,718 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-11 12:48:05,718 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2018-04-11 12:48:05,719 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:05,719 INFO L225 Difference]: With dead ends: 47 [2018-04-11 12:48:05,719 INFO L226 Difference]: Without dead ends: 47 [2018-04-11 12:48:05,719 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-04-11 12:48:05,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-04-11 12:48:05,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2018-04-11 12:48:05,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-04-11 12:48:05,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 52 transitions. [2018-04-11 12:48:05,721 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 52 transitions. Word has length 25 [2018-04-11 12:48:05,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:05,721 INFO L459 AbstractCegarLoop]: Abstraction has 47 states and 52 transitions. [2018-04-11 12:48:05,721 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-11 12:48:05,721 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 52 transitions. [2018-04-11 12:48:05,721 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-04-11 12:48:05,721 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:05,721 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:05,721 INFO L408 AbstractCegarLoop]: === Iteration 14 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:05,721 INFO L82 PathProgramCache]: Analyzing trace with hash 1307629357, now seen corresponding path program 1 times [2018-04-11 12:48:05,722 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:05,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:05,730 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:05,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,785 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:05,785 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-04-11 12:48:05,785 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:05,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,785 INFO L182 omatonBuilderFactory]: Interpolants [1448#true, 1449#false, 1450#(<= 2 main_~length2~0), 1451#(and (<= 2 (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 1452#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base))), 1453#(and (<= 2 (select |#length| |cstrcat_#in~s1.base|)) (= 0 |cstrcat_#in~s1.offset|)), 1454#(and (<= 2 (select |#length| cstrcat_~s~0.base)) (= 0 cstrcat_~s~0.offset)), 1455#(and (<= 2 (select |#length| |cstrcat_#t~post4.base|)) (= |cstrcat_#t~post4.offset| 0))] [2018-04-11 12:48:05,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,786 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-11 12:48:05,786 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-11 12:48:05,786 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-04-11 12:48:05,786 INFO L87 Difference]: Start difference. First operand 47 states and 52 transitions. Second operand 8 states. [2018-04-11 12:48:05,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:05,875 INFO L93 Difference]: Finished difference Result 52 states and 58 transitions. [2018-04-11 12:48:05,875 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-04-11 12:48:05,875 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 25 [2018-04-11 12:48:05,875 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:05,876 INFO L225 Difference]: With dead ends: 52 [2018-04-11 12:48:05,876 INFO L226 Difference]: Without dead ends: 52 [2018-04-11 12:48:05,876 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2018-04-11 12:48:05,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-04-11 12:48:05,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2018-04-11 12:48:05,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-04-11 12:48:05,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 56 transitions. [2018-04-11 12:48:05,878 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 56 transitions. Word has length 25 [2018-04-11 12:48:05,878 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:05,878 INFO L459 AbstractCegarLoop]: Abstraction has 51 states and 56 transitions. [2018-04-11 12:48:05,878 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-11 12:48:05,878 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 56 transitions. [2018-04-11 12:48:05,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-04-11 12:48:05,879 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:05,879 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:05,879 INFO L408 AbstractCegarLoop]: === Iteration 15 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:05,879 INFO L82 PathProgramCache]: Analyzing trace with hash 1924753718, now seen corresponding path program 2 times [2018-04-11 12:48:05,880 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:05,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:05,889 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:05,983 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-11 12:48:05,983 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:05,983 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-04-11 12:48:05,983 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:05,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:05,984 INFO L182 omatonBuilderFactory]: Interpolants [1569#true, 1570#false, 1571#(and (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1572#(and (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= main_~length3~0 1)), 1573#(and (= main_~nondetString2~0.offset 0) (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1574#(and (= main_~nondetString2~0.offset 0) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset))), 1575#(= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)), 1576#(= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)), 1577#(= |cstrcat_#t~mem2| 0)] [2018-04-11 12:48:05,984 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-11 12:48:05,984 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-11 12:48:05,984 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-11 12:48:05,984 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-04-11 12:48:05,984 INFO L87 Difference]: Start difference. First operand 51 states and 56 transitions. Second operand 9 states. [2018-04-11 12:48:06,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:06,046 INFO L93 Difference]: Finished difference Result 74 states and 79 transitions. [2018-04-11 12:48:06,046 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-11 12:48:06,046 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 26 [2018-04-11 12:48:06,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:06,047 INFO L225 Difference]: With dead ends: 74 [2018-04-11 12:48:06,047 INFO L226 Difference]: Without dead ends: 74 [2018-04-11 12:48:06,047 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2018-04-11 12:48:06,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-04-11 12:48:06,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 63. [2018-04-11 12:48:06,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-04-11 12:48:06,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 69 transitions. [2018-04-11 12:48:06,050 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 69 transitions. Word has length 26 [2018-04-11 12:48:06,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:06,050 INFO L459 AbstractCegarLoop]: Abstraction has 63 states and 69 transitions. [2018-04-11 12:48:06,050 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-11 12:48:06,050 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 69 transitions. [2018-04-11 12:48:06,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-04-11 12:48:06,051 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:06,051 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:06,051 INFO L408 AbstractCegarLoop]: === Iteration 16 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:06,051 INFO L82 PathProgramCache]: Analyzing trace with hash -69390988, now seen corresponding path program 1 times [2018-04-11 12:48:06,052 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:06,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:06,060 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:06,154 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-11 12:48:06,154 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:06,154 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-04-11 12:48:06,155 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:06,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:06,155 INFO L182 omatonBuilderFactory]: Interpolants [1728#(and (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1729#(and (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= main_~length3~0 1)), 1730#(and (= main_~nondetString2~0.offset 0) (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1731#(and (= main_~nondetString2~0.offset 0) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset))), 1732#(= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)), 1733#(= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)), 1734#(= |cstrcat_#t~mem2| 0), 1723#true, 1724#false, 1725#(<= 1 main_~length1~0), 1726#(<= main_~length2~0 (+ main_~length1~0 1)), 1727#(and (<= main_~length2~0 (+ main_~length1~0 1)) (<= 1 main_~length3~0))] [2018-04-11 12:48:06,155 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-11 12:48:06,155 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-04-11 12:48:06,155 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-04-11 12:48:06,156 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2018-04-11 12:48:06,156 INFO L87 Difference]: Start difference. First operand 63 states and 69 transitions. Second operand 12 states. [2018-04-11 12:48:06,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:06,298 INFO L93 Difference]: Finished difference Result 102 states and 109 transitions. [2018-04-11 12:48:06,298 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-04-11 12:48:06,298 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 26 [2018-04-11 12:48:06,298 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:06,298 INFO L225 Difference]: With dead ends: 102 [2018-04-11 12:48:06,298 INFO L226 Difference]: Without dead ends: 102 [2018-04-11 12:48:06,299 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 103 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=150, Invalid=500, Unknown=0, NotChecked=0, Total=650 [2018-04-11 12:48:06,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-04-11 12:48:06,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 64. [2018-04-11 12:48:06,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-04-11 12:48:06,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 71 transitions. [2018-04-11 12:48:06,300 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 71 transitions. Word has length 26 [2018-04-11 12:48:06,301 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:06,301 INFO L459 AbstractCegarLoop]: Abstraction has 64 states and 71 transitions. [2018-04-11 12:48:06,301 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-04-11 12:48:06,301 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 71 transitions. [2018-04-11 12:48:06,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-04-11 12:48:06,301 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:06,301 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:06,301 INFO L408 AbstractCegarLoop]: === Iteration 17 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:06,302 INFO L82 PathProgramCache]: Analyzing trace with hash -1758334730, now seen corresponding path program 1 times [2018-04-11 12:48:06,302 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:06,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:06,309 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:06,438 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:06,438 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:06,438 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-04-11 12:48:06,438 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:06,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:06,439 INFO L182 omatonBuilderFactory]: Interpolants [1929#true, 1930#false, 1931#(<= 1 main_~length1~0), 1932#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 1933#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 1934#(and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 1935#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) 1) (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)))), 1936#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= 3 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 1937#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (<= 3 (select |#length| |cstrcat_#in~s1.base|))) (= 0 |cstrcat_#in~s1.offset|)), 1938#(and (or (<= 3 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 0)), 1939#(and (or (<= 3 (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem2| 0)) (= cstrcat_~s~0.offset 0)), 1940#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 1941#(and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))] [2018-04-11 12:48:06,439 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:06,439 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-04-11 12:48:06,439 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-04-11 12:48:06,439 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=132, Unknown=0, NotChecked=0, Total=156 [2018-04-11 12:48:06,439 INFO L87 Difference]: Start difference. First operand 64 states and 71 transitions. Second operand 13 states. [2018-04-11 12:48:06,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:06,735 INFO L93 Difference]: Finished difference Result 83 states and 93 transitions. [2018-04-11 12:48:06,735 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-04-11 12:48:06,735 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 26 [2018-04-11 12:48:06,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:06,736 INFO L225 Difference]: With dead ends: 83 [2018-04-11 12:48:06,736 INFO L226 Difference]: Without dead ends: 83 [2018-04-11 12:48:06,736 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=83, Invalid=379, Unknown=0, NotChecked=0, Total=462 [2018-04-11 12:48:06,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-04-11 12:48:06,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 75. [2018-04-11 12:48:06,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2018-04-11 12:48:06,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 85 transitions. [2018-04-11 12:48:06,739 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 85 transitions. Word has length 26 [2018-04-11 12:48:06,740 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:06,740 INFO L459 AbstractCegarLoop]: Abstraction has 75 states and 85 transitions. [2018-04-11 12:48:06,740 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-04-11 12:48:06,740 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 85 transitions. [2018-04-11 12:48:06,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-04-11 12:48:06,741 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:06,741 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:06,741 INFO L408 AbstractCegarLoop]: === Iteration 18 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:06,741 INFO L82 PathProgramCache]: Analyzing trace with hash -1838913673, now seen corresponding path program 1 times [2018-04-11 12:48:06,742 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:06,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:06,750 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:06,809 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:06,810 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:06,810 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-04-11 12:48:06,810 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:06,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:06,810 INFO L182 omatonBuilderFactory]: Interpolants [2118#true, 2119#false, 2120#(= 0 |main_#t~malloc11.offset|), 2121#(= 0 main_~nondetString2~0.offset), 2122#(= 0 |cstrcat_#in~s1.offset|), 2123#(= cstrcat_~s~0.offset 0), 2124#(<= 1 cstrcat_~s~0.offset), 2125#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 2126#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:48:06,810 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:06,810 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-11 12:48:06,811 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-11 12:48:06,811 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2018-04-11 12:48:06,811 INFO L87 Difference]: Start difference. First operand 75 states and 85 transitions. Second operand 9 states. [2018-04-11 12:48:06,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:06,896 INFO L93 Difference]: Finished difference Result 77 states and 87 transitions. [2018-04-11 12:48:06,897 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-11 12:48:06,897 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 28 [2018-04-11 12:48:06,897 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:06,898 INFO L225 Difference]: With dead ends: 77 [2018-04-11 12:48:06,898 INFO L226 Difference]: Without dead ends: 77 [2018-04-11 12:48:06,898 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=142, Unknown=0, NotChecked=0, Total=182 [2018-04-11 12:48:06,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2018-04-11 12:48:06,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 72. [2018-04-11 12:48:06,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-04-11 12:48:06,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 81 transitions. [2018-04-11 12:48:06,901 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 81 transitions. Word has length 28 [2018-04-11 12:48:06,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:06,901 INFO L459 AbstractCegarLoop]: Abstraction has 72 states and 81 transitions. [2018-04-11 12:48:06,901 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-11 12:48:06,901 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 81 transitions. [2018-04-11 12:48:06,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-04-11 12:48:06,902 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:06,902 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:06,902 INFO L408 AbstractCegarLoop]: === Iteration 19 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:06,902 INFO L82 PathProgramCache]: Analyzing trace with hash -1372572863, now seen corresponding path program 1 times [2018-04-11 12:48:06,907 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:06,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:06,921 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:07,059 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:07,059 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:07,059 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-04-11 12:48:07,059 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:07,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:07,060 INFO L182 omatonBuilderFactory]: Interpolants [2288#(and (<= 1 main_~length1~0) (<= main_~length1~0 1)), 2289#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length1~0) (<= main_~length1~0 1) (= (select |#valid| |main_#t~malloc10.base|) 1)), 2290#(and (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length1~0) (<= main_~length1~0 1) (= main_~nondetString1~0.offset 0)), 2291#(and (not (= main_~nondetString1~0.base |main_#t~malloc11.base|)) (<= 1 main_~length1~0) (<= main_~length1~0 1) (= main_~nondetString1~0.offset 0)), 2292#(and (<= 1 main_~length1~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (<= main_~length1~0 1) (= main_~nondetString1~0.offset 0)), 2293#(and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 2294#(= 0 (select (select |#memory_int| |cstrcat_#in~s2.base|) |cstrcat_#in~s2.offset|)), 2295#(= 0 (select (select |#memory_int| cstrcat_~s2.base) cstrcat_~s2.offset)), 2296#(= 0 (select (select |#memory_int| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 2297#(= |cstrcat_#t~mem6| 0), 2286#true, 2287#false] [2018-04-11 12:48:07,060 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:07,060 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-04-11 12:48:07,060 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-04-11 12:48:07,060 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2018-04-11 12:48:07,060 INFO L87 Difference]: Start difference. First operand 72 states and 81 transitions. Second operand 12 states. [2018-04-11 12:48:07,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:07,216 INFO L93 Difference]: Finished difference Result 131 states and 146 transitions. [2018-04-11 12:48:07,216 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-11 12:48:07,216 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 29 [2018-04-11 12:48:07,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:07,217 INFO L225 Difference]: With dead ends: 131 [2018-04-11 12:48:07,217 INFO L226 Difference]: Without dead ends: 131 [2018-04-11 12:48:07,218 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=85, Invalid=335, Unknown=0, NotChecked=0, Total=420 [2018-04-11 12:48:07,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states. [2018-04-11 12:48:07,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 123. [2018-04-11 12:48:07,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 123 states. [2018-04-11 12:48:07,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 140 transitions. [2018-04-11 12:48:07,222 INFO L78 Accepts]: Start accepts. Automaton has 123 states and 140 transitions. Word has length 29 [2018-04-11 12:48:07,222 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:07,222 INFO L459 AbstractCegarLoop]: Abstraction has 123 states and 140 transitions. [2018-04-11 12:48:07,222 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-04-11 12:48:07,222 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 140 transitions. [2018-04-11 12:48:07,223 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-04-11 12:48:07,223 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:07,223 INFO L355 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:07,223 INFO L408 AbstractCegarLoop]: === Iteration 20 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:07,224 INFO L82 PathProgramCache]: Analyzing trace with hash -1128799700, now seen corresponding path program 2 times [2018-04-11 12:48:07,224 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:07,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:07,236 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:07,488 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:07,488 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:07,488 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-04-11 12:48:07,488 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:07,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:07,489 INFO L182 omatonBuilderFactory]: Interpolants [2570#true, 2571#false, 2572#(<= 1 main_~length1~0), 2573#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 2574#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 2575#(and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 2576#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (or (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2))), 2577#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 2578#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 2579#(and (= cstrcat_~s~0.offset 0) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 2580#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (<= 4 (select |#length| cstrcat_~s~0.base))) (= cstrcat_~s~0.offset 0)), 2581#(and (= cstrcat_~s~0.offset 1) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 2582#(and (or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= cstrcat_~s~0.offset 1)), 2583#(<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)), 2584#(and (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (<= 0 cstrcat_~s~0.offset)), 2585#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))] [2018-04-11 12:48:07,489 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:07,489 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-11 12:48:07,489 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-11 12:48:07,489 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=209, Unknown=0, NotChecked=0, Total=240 [2018-04-11 12:48:07,489 INFO L87 Difference]: Start difference. First operand 123 states and 140 transitions. Second operand 16 states. [2018-04-11 12:48:07,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:07,872 INFO L93 Difference]: Finished difference Result 157 states and 179 transitions. [2018-04-11 12:48:07,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-04-11 12:48:07,872 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 29 [2018-04-11 12:48:07,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:07,873 INFO L225 Difference]: With dead ends: 157 [2018-04-11 12:48:07,873 INFO L226 Difference]: Without dead ends: 157 [2018-04-11 12:48:07,874 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 88 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=113, Invalid=643, Unknown=0, NotChecked=0, Total=756 [2018-04-11 12:48:07,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-04-11 12:48:07,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 129. [2018-04-11 12:48:07,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-04-11 12:48:07,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 148 transitions. [2018-04-11 12:48:07,879 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 148 transitions. Word has length 29 [2018-04-11 12:48:07,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:07,879 INFO L459 AbstractCegarLoop]: Abstraction has 129 states and 148 transitions. [2018-04-11 12:48:07,879 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-11 12:48:07,879 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 148 transitions. [2018-04-11 12:48:07,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-04-11 12:48:07,880 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:07,880 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:07,880 INFO L408 AbstractCegarLoop]: === Iteration 21 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:07,880 INFO L82 PathProgramCache]: Analyzing trace with hash 1116956099, now seen corresponding path program 1 times [2018-04-11 12:48:07,881 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:07,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:07,891 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:08,017 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:08,017 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:08,017 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2018-04-11 12:48:08,018 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:08,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:08,018 INFO L182 omatonBuilderFactory]: Interpolants [2896#true, 2897#false, 2898#(<= 1 main_~length1~0), 2899#(and (<= 1 main_~length1~0) (<= main_~length2~0 2)), 2900#(and (<= main_~length2~0 (+ main_~length3~0 1)) (<= 1 main_~length1~0)), 2901#(and (<= 1 main_~length1~0) (<= main_~length1~0 1)), 2902#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length1~0) (<= main_~length1~0 1) (= (select |#valid| |main_#t~malloc10.base|) 1)), 2903#(and (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length1~0) (<= main_~length1~0 1) (= main_~nondetString1~0.offset 0)), 2904#(and (not (= main_~nondetString1~0.base |main_#t~malloc11.base|)) (<= 1 main_~length1~0) (<= main_~length1~0 1) (= main_~nondetString1~0.offset 0)), 2905#(and (<= 1 main_~length1~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (<= main_~length1~0 1) (= main_~nondetString1~0.offset 0)), 2906#(and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 2907#(= 0 (select (select |#memory_int| |cstrcat_#in~s2.base|) |cstrcat_#in~s2.offset|)), 2908#(= 0 (select (select |#memory_int| cstrcat_~s2.base) cstrcat_~s2.offset)), 2909#(= 0 (select (select |#memory_int| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 2910#(= |cstrcat_#t~mem6| 0)] [2018-04-11 12:48:08,018 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:08,018 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-04-11 12:48:08,018 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-04-11 12:48:08,018 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=172, Unknown=0, NotChecked=0, Total=210 [2018-04-11 12:48:08,018 INFO L87 Difference]: Start difference. First operand 129 states and 148 transitions. Second operand 15 states. [2018-04-11 12:48:08,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:08,316 INFO L93 Difference]: Finished difference Result 172 states and 189 transitions. [2018-04-11 12:48:08,317 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-04-11 12:48:08,317 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 29 [2018-04-11 12:48:08,317 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:08,317 INFO L225 Difference]: With dead ends: 172 [2018-04-11 12:48:08,317 INFO L226 Difference]: Without dead ends: 172 [2018-04-11 12:48:08,318 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=233, Invalid=889, Unknown=0, NotChecked=0, Total=1122 [2018-04-11 12:48:08,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-04-11 12:48:08,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 149. [2018-04-11 12:48:08,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-04-11 12:48:08,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 168 transitions. [2018-04-11 12:48:08,321 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 168 transitions. Word has length 29 [2018-04-11 12:48:08,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:08,321 INFO L459 AbstractCegarLoop]: Abstraction has 149 states and 168 transitions. [2018-04-11 12:48:08,321 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-04-11 12:48:08,321 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 168 transitions. [2018-04-11 12:48:08,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-04-11 12:48:08,322 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:08,322 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:08,322 INFO L408 AbstractCegarLoop]: === Iteration 22 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:08,322 INFO L82 PathProgramCache]: Analyzing trace with hash 1335810817, now seen corresponding path program 1 times [2018-04-11 12:48:08,323 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:08,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:08,330 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:08,469 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:08,469 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:08,469 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-04-11 12:48:08,470 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:08,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:08,470 INFO L182 omatonBuilderFactory]: Interpolants [3270#true, 3271#false, 3272#(<= 1 main_~length1~0), 3273#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length1~0) (= (select |#valid| |main_#t~malloc10.base|) 1)), 3274#(and (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) 1)) (= (select |#valid| main_~nondetString1~0.base) 1)) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 3275#(and (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) 1)) (not (= main_~nondetString1~0.base |main_#t~malloc11.base|))) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 3276#(and (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) 1)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 3277#(and (= 0 main_~nondetString1~0.offset) (or (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (<= 2 (select |#length| main_~nondetString1~0.base)))), 3278#(and (= 0 |cstrcat_#in~s2.offset|) (or (<= 2 (select |#length| |cstrcat_#in~s2.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s2.base|) |cstrcat_#in~s2.offset|)))), 3279#(and (or (<= 2 (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s2.base) cstrcat_~s2.offset))) (= 0 cstrcat_~s2.offset)), 3280#(and (<= (+ |cstrcat_#t~post5.offset| 1) cstrcat_~s2.offset) (= |cstrcat_#t~post5.offset| 0) (or (= 0 (select (select |#memory_int| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)) (<= (+ cstrcat_~s2.offset 1) (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)))) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)), 3281#(and (or (= |cstrcat_#t~mem6| 0) (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base))) (<= 1 cstrcat_~s2.offset)), 3282#(and (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base)) (<= 1 cstrcat_~s2.offset)), 3283#(and (<= (+ |cstrcat_#t~post5.offset| 1) (select |#length| |cstrcat_#t~post5.base|)) (<= 1 |cstrcat_#t~post5.offset|))] [2018-04-11 12:48:08,470 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:08,470 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-04-11 12:48:08,470 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-04-11 12:48:08,470 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=152, Unknown=0, NotChecked=0, Total=182 [2018-04-11 12:48:08,470 INFO L87 Difference]: Start difference. First operand 149 states and 168 transitions. Second operand 14 states. [2018-04-11 12:48:08,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:08,713 INFO L93 Difference]: Finished difference Result 156 states and 177 transitions. [2018-04-11 12:48:08,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-04-11 12:48:08,713 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 29 [2018-04-11 12:48:08,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:08,714 INFO L225 Difference]: With dead ends: 156 [2018-04-11 12:48:08,714 INFO L226 Difference]: Without dead ends: 156 [2018-04-11 12:48:08,714 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 82 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=88, Invalid=418, Unknown=0, NotChecked=0, Total=506 [2018-04-11 12:48:08,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-04-11 12:48:08,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 153. [2018-04-11 12:48:08,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 153 states. [2018-04-11 12:48:08,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 173 transitions. [2018-04-11 12:48:08,717 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 173 transitions. Word has length 29 [2018-04-11 12:48:08,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:08,718 INFO L459 AbstractCegarLoop]: Abstraction has 153 states and 173 transitions. [2018-04-11 12:48:08,718 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-04-11 12:48:08,718 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 173 transitions. [2018-04-11 12:48:08,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-04-11 12:48:08,718 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:08,719 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:08,719 INFO L408 AbstractCegarLoop]: === Iteration 23 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:08,719 INFO L82 PathProgramCache]: Analyzing trace with hash -1539537621, now seen corresponding path program 1 times [2018-04-11 12:48:08,719 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:08,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:08,726 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:08,797 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:08,797 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:08,797 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-04-11 12:48:08,797 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:08,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:08,797 INFO L182 omatonBuilderFactory]: Interpolants [3616#(and (<= 2 (select |#length| |cstrcat_#in~s1.base|)) (= 0 |cstrcat_#in~s1.offset|)), 3617#(and (<= 2 (select |#length| cstrcat_~s~0.base)) (= 0 cstrcat_~s~0.offset)), 3618#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (= |cstrcat_#t~post4.offset| 0) (<= (+ cstrcat_~s~0.offset 1) (+ |cstrcat_#t~post4.offset| (select |#length| cstrcat_~s~0.base)))), 3619#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 3620#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))), 3611#true, 3612#false, 3613#(<= 2 main_~length2~0), 3614#(and (<= 2 (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 3615#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base)))] [2018-04-11 12:48:08,797 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:08,797 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-11 12:48:08,797 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-11 12:48:08,798 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2018-04-11 12:48:08,798 INFO L87 Difference]: Start difference. First operand 153 states and 173 transitions. Second operand 10 states. [2018-04-11 12:48:08,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:08,934 INFO L93 Difference]: Finished difference Result 184 states and 208 transitions. [2018-04-11 12:48:08,934 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-11 12:48:08,934 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 30 [2018-04-11 12:48:08,934 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:08,935 INFO L225 Difference]: With dead ends: 184 [2018-04-11 12:48:08,935 INFO L226 Difference]: Without dead ends: 184 [2018-04-11 12:48:08,935 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=51, Invalid=221, Unknown=0, NotChecked=0, Total=272 [2018-04-11 12:48:08,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-04-11 12:48:08,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 162. [2018-04-11 12:48:08,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-04-11 12:48:08,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 183 transitions. [2018-04-11 12:48:08,939 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 183 transitions. Word has length 30 [2018-04-11 12:48:08,940 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:08,940 INFO L459 AbstractCegarLoop]: Abstraction has 162 states and 183 transitions. [2018-04-11 12:48:08,940 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-11 12:48:08,940 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 183 transitions. [2018-04-11 12:48:08,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-04-11 12:48:08,940 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:08,941 INFO L355 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:08,941 INFO L408 AbstractCegarLoop]: === Iteration 24 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:08,941 INFO L82 PathProgramCache]: Analyzing trace with hash 1522064694, now seen corresponding path program 3 times [2018-04-11 12:48:08,941 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:08,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:08,951 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:09,232 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:09,232 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:09,232 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-04-11 12:48:09,233 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:09,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:09,233 INFO L182 omatonBuilderFactory]: Interpolants [3981#true, 3982#false, 3983#(<= 1 main_~length1~0), 3984#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 3985#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 3986#(and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 3987#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1))), 3988#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- 1)) (+ main_~nondetString2~0.offset (- 1))))) (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))))), 3989#(and (or (and (or (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1))))) (<= 4 (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 3990#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 0)), 3991#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))))) (= cstrcat_~s~0.offset 0)), 3992#(and (= cstrcat_~s~0.offset 1) (or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 3993#(and (= cstrcat_~s~0.offset 1) (or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0))), 3994#(or (and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 3995#(or (and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0)), 3996#(and (<= 3 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 3997#(and (<= 4 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))] [2018-04-11 12:48:09,233 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:09,233 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-04-11 12:48:09,233 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-04-11 12:48:09,233 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=240, Unknown=0, NotChecked=0, Total=272 [2018-04-11 12:48:09,233 INFO L87 Difference]: Start difference. First operand 162 states and 183 transitions. Second operand 17 states. [2018-04-11 12:48:09,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:09,772 INFO L93 Difference]: Finished difference Result 198 states and 224 transitions. [2018-04-11 12:48:09,772 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-04-11 12:48:09,772 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 32 [2018-04-11 12:48:09,772 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:09,773 INFO L225 Difference]: With dead ends: 198 [2018-04-11 12:48:09,773 INFO L226 Difference]: Without dead ends: 198 [2018-04-11 12:48:09,774 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 90 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=111, Invalid=759, Unknown=0, NotChecked=0, Total=870 [2018-04-11 12:48:09,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states. [2018-04-11 12:48:09,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 168. [2018-04-11 12:48:09,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 168 states. [2018-04-11 12:48:09,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168 states to 168 states and 191 transitions. [2018-04-11 12:48:09,778 INFO L78 Accepts]: Start accepts. Automaton has 168 states and 191 transitions. Word has length 32 [2018-04-11 12:48:09,778 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:09,778 INFO L459 AbstractCegarLoop]: Abstraction has 168 states and 191 transitions. [2018-04-11 12:48:09,778 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-04-11 12:48:09,778 INFO L276 IsEmpty]: Start isEmpty. Operand 168 states and 191 transitions. [2018-04-11 12:48:09,779 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-04-11 12:48:09,779 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:09,779 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:09,779 INFO L408 AbstractCegarLoop]: === Iteration 25 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:09,779 INFO L82 PathProgramCache]: Analyzing trace with hash 1308976227, now seen corresponding path program 1 times [2018-04-11 12:48:09,780 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:09,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:09,785 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:09,945 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:09,946 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:09,946 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-04-11 12:48:09,946 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:09,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:09,946 INFO L182 omatonBuilderFactory]: Interpolants [4390#true, 4391#false, 4392#(<= 1 main_~length3~0), 4393#(<= (+ main_~length1~0 1) main_~length2~0), 4394#(and (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length1~0 1) main_~length2~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 4395#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= (+ main_~length1~0 1) main_~length2~0)), 4396#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length1~0 1) (select |#length| |main_#t~malloc11.base|))), 4397#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length1~0 1) (select |#length| main_~nondetString2~0.base))), 4398#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ (select |#length| main_~nondetString1~0.base) 1) (select |#length| main_~nondetString2~0.base))), 4399#(and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 1) (select |#length| |cstrcat_#in~s1.base|)) (= 0 |cstrcat_#in~s2.offset|) (= 0 |cstrcat_#in~s1.offset|)), 4400#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) 1) (select |#length| cstrcat_~s~0.base)) (= cstrcat_~s~0.offset 0)), 4401#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))), 4402#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (= |cstrcat_#t~post5.offset| 0) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)), 4403#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 4404#(and (<= 1 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 4405#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post4.offset|) (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post4.base|)))), 4406#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:48:09,946 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:09,946 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-04-11 12:48:09,946 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-04-11 12:48:09,946 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2018-04-11 12:48:09,947 INFO L87 Difference]: Start difference. First operand 168 states and 191 transitions. Second operand 17 states. [2018-04-11 12:48:10,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:10,369 INFO L93 Difference]: Finished difference Result 196 states and 221 transitions. [2018-04-11 12:48:10,369 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-04-11 12:48:10,369 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 33 [2018-04-11 12:48:10,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:10,370 INFO L225 Difference]: With dead ends: 196 [2018-04-11 12:48:10,370 INFO L226 Difference]: Without dead ends: 196 [2018-04-11 12:48:10,370 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 142 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=156, Invalid=836, Unknown=0, NotChecked=0, Total=992 [2018-04-11 12:48:10,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states. [2018-04-11 12:48:10,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 172. [2018-04-11 12:48:10,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2018-04-11 12:48:10,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 197 transitions. [2018-04-11 12:48:10,373 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 197 transitions. Word has length 33 [2018-04-11 12:48:10,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:10,373 INFO L459 AbstractCegarLoop]: Abstraction has 172 states and 197 transitions. [2018-04-11 12:48:10,373 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-04-11 12:48:10,373 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 197 transitions. [2018-04-11 12:48:10,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-04-11 12:48:10,373 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:10,373 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:10,373 INFO L408 AbstractCegarLoop]: === Iteration 26 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:10,374 INFO L82 PathProgramCache]: Analyzing trace with hash 2061021759, now seen corresponding path program 2 times [2018-04-11 12:48:10,374 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:10,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:10,382 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:10,639 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:10,639 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:10,639 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-04-11 12:48:10,639 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:10,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:10,639 INFO L182 omatonBuilderFactory]: Interpolants [4805#true, 4806#false, 4807#(and (= 0 |main_#t~malloc10.offset|) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 4808#(and (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1) (or (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (+ main_~nondetString1~0.offset main_~length1~0) 2))), 4809#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc11.base|)) (or (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (+ main_~nondetString1~0.offset main_~length1~0) 2))), 4810#(and (= 0 main_~nondetString1~0.offset) (or (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (+ main_~nondetString1~0.offset main_~length1~0) 2)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 4811#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (<= 3 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (<= (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)) 1))), 4812#(and (or (<= (select |#length| |cstrcat_#in~s2.base|) 1) (= 0 (select (select |#memory_int| |cstrcat_#in~s2.base|) 1)) (<= 3 (select |#length| |cstrcat_#in~s2.base|))) (not (= |cstrcat_#in~s2.base| |cstrcat_#in~s1.base|)) (= 0 |cstrcat_#in~s2.offset|)), 4813#(and (= 0 cstrcat_~s2.offset) (not (= cstrcat_~s2.base cstrcat_~s~0.base)) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s2.base) 1)) (<= 3 (select |#length| cstrcat_~s2.base)))), 4814#(and (<= cstrcat_~s2.offset (+ |cstrcat_#t~post5.offset| 1)) (not (= |cstrcat_#t~post4.base| cstrcat_~s2.base)) (<= (+ |cstrcat_#t~post5.offset| 1) cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s2.base) 1)) (and (or (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) cstrcat_~s2.offset) (<= (+ cstrcat_~s2.offset 2) (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)))) (= |cstrcat_#t~post5.base| cstrcat_~s2.base))) (= |cstrcat_#t~post5.offset| 0)), 4815#(and (not (= |cstrcat_#t~post4.base| cstrcat_~s2.base)) (<= cstrcat_~s2.offset 1) (or (<= (+ cstrcat_~s2.offset 2) (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s2.base) 1)) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)) (<= 1 cstrcat_~s2.offset)), 4816#(and (<= cstrcat_~s2.offset 1) (or (<= (+ cstrcat_~s2.offset 2) (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s2.base) 1)) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)) (<= 1 cstrcat_~s2.offset)), 4817#(and (or (= 0 (select (select |#memory_int| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)) (and (or (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base)) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)) (<= 2 cstrcat_~s2.offset))) (= 1 |cstrcat_#t~post5.offset|)), 4818#(or (= |cstrcat_#t~mem6| 0) (and (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base)) (<= 2 cstrcat_~s2.offset))), 4819#(and (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base)) (<= 2 cstrcat_~s2.offset)), 4820#(and (<= 2 |cstrcat_#t~post5.offset|) (<= (+ |cstrcat_#t~post5.offset| 1) (select |#length| |cstrcat_#t~post5.base|)))] [2018-04-11 12:48:10,639 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:10,639 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-11 12:48:10,640 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-11 12:48:10,640 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-04-11 12:48:10,640 INFO L87 Difference]: Start difference. First operand 172 states and 197 transitions. Second operand 16 states. [2018-04-11 12:48:10,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:10,925 INFO L93 Difference]: Finished difference Result 194 states and 224 transitions. [2018-04-11 12:48:10,926 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-04-11 12:48:10,926 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 34 [2018-04-11 12:48:10,926 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:10,927 INFO L225 Difference]: With dead ends: 194 [2018-04-11 12:48:10,927 INFO L226 Difference]: Without dead ends: 194 [2018-04-11 12:48:10,927 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=81, Invalid=471, Unknown=0, NotChecked=0, Total=552 [2018-04-11 12:48:10,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194 states. [2018-04-11 12:48:10,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194 to 182. [2018-04-11 12:48:10,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-04-11 12:48:10,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 210 transitions. [2018-04-11 12:48:10,930 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 210 transitions. Word has length 34 [2018-04-11 12:48:10,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:10,930 INFO L459 AbstractCegarLoop]: Abstraction has 182 states and 210 transitions. [2018-04-11 12:48:10,931 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-11 12:48:10,931 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 210 transitions. [2018-04-11 12:48:10,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-04-11 12:48:10,931 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:10,931 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:10,931 INFO L408 AbstractCegarLoop]: === Iteration 27 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:10,931 INFO L82 PathProgramCache]: Analyzing trace with hash -4260326, now seen corresponding path program 1 times [2018-04-11 12:48:10,932 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:10,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:10,937 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:10,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:10,991 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:48:10,991 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-11 12:48:10,991 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:10,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:10,991 INFO L182 omatonBuilderFactory]: Interpolants [5216#(and (= |old(#valid)| (store |#valid| |main_#t~malloc10.base| 0)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 5217#(and (not (= |main_#t~malloc10.base| |main_#t~malloc11.base|)) (= |old(#valid)| (store (store |#valid| |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0))), 5218#(= |old(#valid)| (store |#valid| |main_#t~malloc11.base| 0)), 5213#true, 5214#false, 5215#(= |#valid| |old(#valid)|)] [2018-04-11 12:48:10,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:10,991 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-11 12:48:10,991 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-11 12:48:10,992 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-04-11 12:48:10,992 INFO L87 Difference]: Start difference. First operand 182 states and 210 transitions. Second operand 6 states. [2018-04-11 12:48:11,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:11,045 INFO L93 Difference]: Finished difference Result 181 states and 209 transitions. [2018-04-11 12:48:11,045 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-11 12:48:11,045 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35 [2018-04-11 12:48:11,045 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:11,046 INFO L225 Difference]: With dead ends: 181 [2018-04-11 12:48:11,046 INFO L226 Difference]: Without dead ends: 119 [2018-04-11 12:48:11,046 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-04-11 12:48:11,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-04-11 12:48:11,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 114. [2018-04-11 12:48:11,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-04-11 12:48:11,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 124 transitions. [2018-04-11 12:48:11,048 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 124 transitions. Word has length 35 [2018-04-11 12:48:11,048 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:11,048 INFO L459 AbstractCegarLoop]: Abstraction has 114 states and 124 transitions. [2018-04-11 12:48:11,048 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-11 12:48:11,048 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 124 transitions. [2018-04-11 12:48:11,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-04-11 12:48:11,048 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:11,048 INFO L355 BasicCegarLoop]: trace histogram [6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:11,048 INFO L408 AbstractCegarLoop]: === Iteration 28 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:11,049 INFO L82 PathProgramCache]: Analyzing trace with hash 1859554796, now seen corresponding path program 4 times [2018-04-11 12:48:11,049 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:11,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:11,059 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:11,504 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:11,504 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:11,504 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-04-11 12:48:11,504 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:11,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:11,504 INFO L182 omatonBuilderFactory]: Interpolants [5536#(and (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (<= 0 cstrcat_~s~0.offset)), 5537#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 5518#true, 5519#false, 5520#(<= 1 main_~length1~0), 5521#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5522#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 5523#(and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 5524#(and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))) (= 0 main_~nondetString2~0.offset)), 5525#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- 1)) (+ main_~nondetString2~0.offset (- 1))))) (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))))), 5526#(and (or (and (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s1.base|)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 5527#(and (or (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (or (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= 5 (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 0)), 5528#(and (= cstrcat_~s~0.offset 0) (or (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (or (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= 5 (select |#length| cstrcat_~s~0.base))))), 5529#(and (or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 1)), 5530#(and (or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))))) (= cstrcat_~s~0.offset 1)), 5531#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 5532#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0)), 5533#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 5534#(or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 5535#(<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))] [2018-04-11 12:48:11,505 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:11,505 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-04-11 12:48:11,505 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-04-11 12:48:11,505 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=335, Unknown=0, NotChecked=0, Total=380 [2018-04-11 12:48:11,505 INFO L87 Difference]: Start difference. First operand 114 states and 124 transitions. Second operand 20 states. [2018-04-11 12:48:12,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:12,302 INFO L93 Difference]: Finished difference Result 137 states and 149 transitions. [2018-04-11 12:48:12,302 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-04-11 12:48:12,302 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 35 [2018-04-11 12:48:12,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:12,303 INFO L225 Difference]: With dead ends: 137 [2018-04-11 12:48:12,303 INFO L226 Difference]: Without dead ends: 137 [2018-04-11 12:48:12,303 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 152 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=172, Invalid=1018, Unknown=0, NotChecked=0, Total=1190 [2018-04-11 12:48:12,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2018-04-11 12:48:12,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 120. [2018-04-11 12:48:12,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-04-11 12:48:12,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 131 transitions. [2018-04-11 12:48:12,305 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 131 transitions. Word has length 35 [2018-04-11 12:48:12,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:12,305 INFO L459 AbstractCegarLoop]: Abstraction has 120 states and 131 transitions. [2018-04-11 12:48:12,305 INFO L460 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-04-11 12:48:12,306 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 131 transitions. [2018-04-11 12:48:12,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-04-11 12:48:12,306 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:12,306 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:12,306 INFO L408 AbstractCegarLoop]: === Iteration 29 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:12,306 INFO L82 PathProgramCache]: Analyzing trace with hash 1280639017, now seen corresponding path program 2 times [2018-04-11 12:48:12,306 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:12,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:12,320 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:12,620 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:12,621 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:12,621 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-04-11 12:48:12,621 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:12,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:12,621 INFO L182 omatonBuilderFactory]: Interpolants [5825#true, 5826#false, 5827#(<= 1 main_~length3~0), 5828#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 5829#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 5830#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 5831#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|))), 5832#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) 1) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base))) (<= 1 main_~length3~0)), 5833#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) 1) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))) (<= 1 main_~length3~0)), 5834#(and (= main_~nondetString2~0.offset 0) (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= (+ (select |#length| main_~nondetString1~0.base) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 5835#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 2) (select |#length| |cstrcat_#in~s1.base|)) (= 0 |cstrcat_#in~s1.offset|))) (= 0 |cstrcat_#in~s2.offset|)), 5836#(and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (select |#length| cstrcat_~s2.base) 2) (select |#length| cstrcat_~s~0.base)) (= cstrcat_~s~0.offset 0)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 5837#(and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (select |#length| cstrcat_~s2.base) 2) (select |#length| cstrcat_~s~0.base)) (= cstrcat_~s~0.offset 0)) (= |cstrcat_#t~mem2| 0))), 5838#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 5839#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))), 5840#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (= |cstrcat_#t~post5.offset| 0) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)), 5841#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 5842#(and (<= 1 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 5843#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post4.offset|) (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post4.base|)))), 5844#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:48:12,621 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:12,621 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-04-11 12:48:12,622 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-04-11 12:48:12,622 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=332, Unknown=0, NotChecked=0, Total=380 [2018-04-11 12:48:12,622 INFO L87 Difference]: Start difference. First operand 120 states and 131 transitions. Second operand 20 states. [2018-04-11 12:48:13,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:13,074 INFO L93 Difference]: Finished difference Result 157 states and 169 transitions. [2018-04-11 12:48:13,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-04-11 12:48:13,074 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 36 [2018-04-11 12:48:13,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:13,075 INFO L225 Difference]: With dead ends: 157 [2018-04-11 12:48:13,075 INFO L226 Difference]: Without dead ends: 157 [2018-04-11 12:48:13,075 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 215 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=149, Invalid=907, Unknown=0, NotChecked=0, Total=1056 [2018-04-11 12:48:13,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-04-11 12:48:13,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 120. [2018-04-11 12:48:13,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-04-11 12:48:13,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 131 transitions. [2018-04-11 12:48:13,078 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 131 transitions. Word has length 36 [2018-04-11 12:48:13,078 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:13,078 INFO L459 AbstractCegarLoop]: Abstraction has 120 states and 131 transitions. [2018-04-11 12:48:13,078 INFO L460 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-04-11 12:48:13,079 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 131 transitions. [2018-04-11 12:48:13,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-11 12:48:13,079 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:13,079 INFO L355 BasicCegarLoop]: trace histogram [7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:13,079 INFO L408 AbstractCegarLoop]: === Iteration 30 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:13,080 INFO L82 PathProgramCache]: Analyzing trace with hash 1508743542, now seen corresponding path program 5 times [2018-04-11 12:48:13,080 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:13,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:13,105 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:13,785 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:13,785 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:13,785 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-04-11 12:48:13,785 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:13,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:13,785 INFO L182 omatonBuilderFactory]: Interpolants [6148#true, 6149#false, 6150#(<= 1 main_~length1~0), 6151#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 6152#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 6153#(and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 6154#(and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))) (= 0 main_~nondetString2~0.offset)), 6155#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (- 1)) (- 1)))))) (and (or (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- 2)) (+ main_~nondetString2~0.offset (- 1)))))) (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))))), 6156#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= 6 (select |#length| |cstrcat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 2)) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s1.base|)))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s1.offset|)), 6157#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (or (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (= cstrcat_~s~0.offset 0)), 6158#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (or (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1)))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (= cstrcat_~s~0.offset 0)), 6159#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))) (= cstrcat_~s~0.offset 1)), 6160#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))) (= cstrcat_~s~0.offset 1)), 6161#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))), 6162#(or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))), 6163#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 6164#(or (= |cstrcat_#t~mem2| 0) (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 6165#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 6166#(or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (<= 0 cstrcat_~s~0.offset))), 6167#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 6168#(and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))] [2018-04-11 12:48:13,786 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:13,786 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-04-11 12:48:13,786 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-04-11 12:48:13,786 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=370, Unknown=0, NotChecked=0, Total=420 [2018-04-11 12:48:13,786 INFO L87 Difference]: Start difference. First operand 120 states and 131 transitions. Second operand 21 states. [2018-04-11 12:48:14,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:14,732 INFO L93 Difference]: Finished difference Result 150 states and 163 transitions. [2018-04-11 12:48:14,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-04-11 12:48:14,732 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 38 [2018-04-11 12:48:14,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:14,732 INFO L225 Difference]: With dead ends: 150 [2018-04-11 12:48:14,732 INFO L226 Difference]: Without dead ends: 150 [2018-04-11 12:48:14,733 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=193, Invalid=1139, Unknown=0, NotChecked=0, Total=1332 [2018-04-11 12:48:14,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-04-11 12:48:14,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 126. [2018-04-11 12:48:14,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-04-11 12:48:14,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 138 transitions. [2018-04-11 12:48:14,735 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 138 transitions. Word has length 38 [2018-04-11 12:48:14,735 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:14,735 INFO L459 AbstractCegarLoop]: Abstraction has 126 states and 138 transitions. [2018-04-11 12:48:14,735 INFO L460 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-04-11 12:48:14,735 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 138 transitions. [2018-04-11 12:48:14,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-04-11 12:48:14,736 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:14,736 INFO L355 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:14,736 INFO L408 AbstractCegarLoop]: === Iteration 31 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:14,736 INFO L82 PathProgramCache]: Analyzing trace with hash -1225150015, now seen corresponding path program 3 times [2018-04-11 12:48:14,737 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:14,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:14,747 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:14,968 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-11 12:48:14,968 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:14,968 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17] total 17 [2018-04-11 12:48:14,968 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:14,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:14,968 INFO L182 omatonBuilderFactory]: Interpolants [6477#true, 6478#false, 6479#(and (= 0 |main_#t~malloc10.offset|) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 6480#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 6481#(and (not (= main_~nondetString1~0.base |main_#t~malloc11.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 6482#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 6483#(and (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))) (= main_~nondetString1~0.offset 0)), 6484#(and (not (= |cstrcat_#in~s2.base| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s2.base|) (+ (select |#length| |cstrcat_#in~s2.base|) (- 1))))), 6485#(and (not (= cstrcat_~s2.base cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s2.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))), 6486#(and (not (= |cstrcat_#t~post4.base| cstrcat_~s2.base)) (not (= cstrcat_~s2.base cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s2.base) (+ (select |#length| |cstrcat_#t~post5.base|) (- 1)))) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)), 6487#(and (not (= |cstrcat_#t~post4.base| cstrcat_~s2.base)) (not (= cstrcat_~s2.base cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s2.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))), 6488#(and (not (= |cstrcat_#t~post5.base| |cstrcat_#t~post4.base|)) (= |cstrcat_#t~post5.base| cstrcat_~s2.base) (= 0 (select (select |#memory_int| |cstrcat_#t~post5.base|) (+ (select |#length| cstrcat_~s2.base) (- 1))))), 6489#(and (not (= |cstrcat_#t~post4.base| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s2.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))), 6490#(= 0 (select (select |#memory_int| cstrcat_~s2.base) (+ (select |#length| cstrcat_~s2.base) (- 1)))), 6491#(or (= 0 (select (select |#memory_int| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)) (and (or (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base)) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)) (<= (+ |cstrcat_#t~post5.offset| 1) cstrcat_~s2.offset))), 6492#(or (= |cstrcat_#t~mem6| 0) (and (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base)) (<= 1 cstrcat_~s2.offset))), 6493#(and (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base)) (<= 1 cstrcat_~s2.offset)), 6494#(and (<= (+ |cstrcat_#t~post5.offset| 1) (select |#length| |cstrcat_#t~post5.base|)) (<= 1 |cstrcat_#t~post5.offset|))] [2018-04-11 12:48:14,968 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-11 12:48:14,968 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-04-11 12:48:14,969 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-04-11 12:48:14,969 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=260, Unknown=0, NotChecked=0, Total=306 [2018-04-11 12:48:14,969 INFO L87 Difference]: Start difference. First operand 126 states and 138 transitions. Second operand 18 states. [2018-04-11 12:48:15,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:15,324 INFO L93 Difference]: Finished difference Result 125 states and 136 transitions. [2018-04-11 12:48:15,324 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-04-11 12:48:15,325 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 39 [2018-04-11 12:48:15,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:15,325 INFO L225 Difference]: With dead ends: 125 [2018-04-11 12:48:15,325 INFO L226 Difference]: Without dead ends: 95 [2018-04-11 12:48:15,326 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 92 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=143, Invalid=669, Unknown=0, NotChecked=0, Total=812 [2018-04-11 12:48:15,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2018-04-11 12:48:15,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 86. [2018-04-11 12:48:15,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-04-11 12:48:15,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 92 transitions. [2018-04-11 12:48:15,328 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 92 transitions. Word has length 39 [2018-04-11 12:48:15,328 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:15,328 INFO L459 AbstractCegarLoop]: Abstraction has 86 states and 92 transitions. [2018-04-11 12:48:15,328 INFO L460 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-04-11 12:48:15,328 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 92 transitions. [2018-04-11 12:48:15,328 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-04-11 12:48:15,329 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:15,329 INFO L355 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:15,329 INFO L408 AbstractCegarLoop]: === Iteration 32 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:15,329 INFO L82 PathProgramCache]: Analyzing trace with hash -1099594077, now seen corresponding path program 3 times [2018-04-11 12:48:15,329 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:15,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:15,340 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:15,920 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:15,920 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:15,920 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21] total 21 [2018-04-11 12:48:15,921 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:15,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:15,921 INFO L182 omatonBuilderFactory]: Interpolants [6728#true, 6729#false, 6730#(<= 1 main_~length3~0), 6731#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 6732#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 6733#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 6734#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|))), 6735#(and (= 0 main_~nondetString2~0.offset) (or (and (<= 1 main_~length3~0) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base))))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1))), 6736#(and (= 0 main_~nondetString2~0.offset) (or (and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)))) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1))), 6737#(or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))))), 6738#(or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|)) (= 0 |cstrcat_#in~s2.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|))), 6739#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 6740#(or (= |cstrcat_#t~mem2| 0) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0))), 6741#(and (or (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 1)), 6742#(and (= cstrcat_~s~0.offset 1) (or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))))), 6743#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 6744#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 6745#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (and (= |cstrcat_#t~post5.offset| 0) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) cstrcat_~s2.offset) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 6746#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 6747#(and (or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= 1 cstrcat_~s~0.offset)), 6748#(and (<= 1 |cstrcat_#t~post4.offset|) (or (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|))), 6749#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:48:15,921 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:15,922 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-04-11 12:48:15,922 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-04-11 12:48:15,922 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=409, Unknown=0, NotChecked=0, Total=462 [2018-04-11 12:48:15,922 INFO L87 Difference]: Start difference. First operand 86 states and 92 transitions. Second operand 22 states. [2018-04-11 12:48:16,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:16,456 INFO L93 Difference]: Finished difference Result 96 states and 102 transitions. [2018-04-11 12:48:16,457 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-04-11 12:48:16,457 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 39 [2018-04-11 12:48:16,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:16,457 INFO L225 Difference]: With dead ends: 96 [2018-04-11 12:48:16,459 INFO L226 Difference]: Without dead ends: 96 [2018-04-11 12:48:16,460 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 223 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=133, Invalid=989, Unknown=0, NotChecked=0, Total=1122 [2018-04-11 12:48:16,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-04-11 12:48:16,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 91. [2018-04-11 12:48:16,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2018-04-11 12:48:16,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 97 transitions. [2018-04-11 12:48:16,462 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 97 transitions. Word has length 39 [2018-04-11 12:48:16,462 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:16,463 INFO L459 AbstractCegarLoop]: Abstraction has 91 states and 97 transitions. [2018-04-11 12:48:16,463 INFO L460 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-04-11 12:48:16,463 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 97 transitions. [2018-04-11 12:48:16,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-04-11 12:48:16,463 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:16,463 INFO L355 BasicCegarLoop]: trace histogram [8, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:16,463 INFO L408 AbstractCegarLoop]: === Iteration 33 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:16,463 INFO L82 PathProgramCache]: Analyzing trace with hash 146106796, now seen corresponding path program 6 times [2018-04-11 12:48:16,464 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:16,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:16,477 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:17,407 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:17,407 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:17,407 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-04-11 12:48:17,407 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:17,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:17,408 INFO L182 omatonBuilderFactory]: Interpolants [6976#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 6977#(or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))))), 6978#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 6979#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0)), 6980#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 6981#(or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 6982#(<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)), 6983#(and (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (<= 0 cstrcat_~s~0.offset)), 6984#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 6961#true, 6962#false, 6963#(<= 1 main_~length1~0), 6964#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 6965#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 6966#(and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 6967#(and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))) (= 0 main_~nondetString2~0.offset)), 6968#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (- 1)) (- 1))))) (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 5) (- 1))))) (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))))), 6969#(and (or (and (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (<= 7 (select |#length| |cstrcat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1)))) (<= 8 (select |#length| |cstrcat_#in~s1.base|)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= 6 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1)))))) (= 0 |cstrcat_#in~s1.offset|)), 6970#(and (or (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (<= 7 (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 6971#(and (or (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (<= 7 (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 6972#(and (= cstrcat_~s~0.offset 1) (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))))), 6973#(and (= cstrcat_~s~0.offset 1) (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))))), 6974#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 6975#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))] [2018-04-11 12:48:17,408 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:17,408 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-04-11 12:48:17,408 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-04-11 12:48:17,408 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=485, Unknown=0, NotChecked=0, Total=552 [2018-04-11 12:48:17,409 INFO L87 Difference]: Start difference. First operand 91 states and 97 transitions. Second operand 24 states. [2018-04-11 12:48:17,893 WARN L151 SmtUtils]: Spent 113ms on a formula simplification. DAG size of input: 89 DAG size of output 88 [2018-04-11 12:48:18,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:18,607 INFO L93 Difference]: Finished difference Result 116 states and 124 transitions. [2018-04-11 12:48:18,607 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-04-11 12:48:18,608 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 41 [2018-04-11 12:48:18,608 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:18,608 INFO L225 Difference]: With dead ends: 116 [2018-04-11 12:48:18,608 INFO L226 Difference]: Without dead ends: 116 [2018-04-11 12:48:18,609 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 235 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=260, Invalid=1462, Unknown=0, NotChecked=0, Total=1722 [2018-04-11 12:48:18,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-04-11 12:48:18,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 97. [2018-04-11 12:48:18,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-04-11 12:48:18,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 104 transitions. [2018-04-11 12:48:18,610 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 104 transitions. Word has length 41 [2018-04-11 12:48:18,610 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:18,610 INFO L459 AbstractCegarLoop]: Abstraction has 97 states and 104 transitions. [2018-04-11 12:48:18,610 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-04-11 12:48:18,611 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 104 transitions. [2018-04-11 12:48:18,611 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-04-11 12:48:18,611 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:18,611 INFO L355 BasicCegarLoop]: trace histogram [5, 5, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:18,611 INFO L408 AbstractCegarLoop]: === Iteration 34 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:18,611 INFO L82 PathProgramCache]: Analyzing trace with hash -713640471, now seen corresponding path program 4 times [2018-04-11 12:48:18,612 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:18,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:18,618 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:19,301 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:19,301 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:19,301 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-04-11 12:48:19,301 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:19,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:19,302 INFO L182 omatonBuilderFactory]: Interpolants [7234#true, 7235#false, 7236#(<= 1 main_~length3~0), 7237#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 7238#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 7239#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 7240#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|))), 7241#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1))), 7242#(and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)))) (= 0 main_~nondetString2~0.offset)), 7243#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= 3 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (select |#length| main_~nondetString1~0.base))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 7244#(and (or (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|)) (= 0 |cstrcat_#in~s2.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (select |#length| |cstrcat_#in~s2.base|))) (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 2) (select |#length| |cstrcat_#in~s1.base|)) (<= 3 (select |#length| |cstrcat_#in~s2.base|)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 7245#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base)) (<= 3 (select |#length| cstrcat_~s2.base))))) (= cstrcat_~s~0.offset 0)), 7246#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base)) (<= 3 (select |#length| cstrcat_~s2.base))))) (= cstrcat_~s~0.offset 0)), 7247#(or (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))))) (<= 3 (select |#length| cstrcat_~s2.base)))) (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 7248#(or (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))))) (<= 3 (select |#length| cstrcat_~s2.base)))) (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset))), 7249#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 7250#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 7251#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 7252#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 7253#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (and (= |cstrcat_#t~post5.offset| 0) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) cstrcat_~s2.offset) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 7254#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 7255#(and (or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= 1 cstrcat_~s~0.offset)), 7256#(and (<= 1 |cstrcat_#t~post4.offset|) (or (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|))), 7257#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:48:19,302 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:19,302 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-04-11 12:48:19,302 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-04-11 12:48:19,302 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=493, Unknown=0, NotChecked=0, Total=552 [2018-04-11 12:48:19,302 INFO L87 Difference]: Start difference. First operand 97 states and 104 transitions. Second operand 24 states. [2018-04-11 12:48:20,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:20,004 INFO L93 Difference]: Finished difference Result 111 states and 118 transitions. [2018-04-11 12:48:20,004 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-04-11 12:48:20,004 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 42 [2018-04-11 12:48:20,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:20,005 INFO L225 Difference]: With dead ends: 111 [2018-04-11 12:48:20,005 INFO L226 Difference]: Without dead ends: 111 [2018-04-11 12:48:20,006 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 292 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=158, Invalid=1248, Unknown=0, NotChecked=0, Total=1406 [2018-04-11 12:48:20,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-04-11 12:48:20,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 97. [2018-04-11 12:48:20,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-04-11 12:48:20,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 104 transitions. [2018-04-11 12:48:20,008 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 104 transitions. Word has length 42 [2018-04-11 12:48:20,008 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:20,008 INFO L459 AbstractCegarLoop]: Abstraction has 97 states and 104 transitions. [2018-04-11 12:48:20,008 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-04-11 12:48:20,008 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 104 transitions. [2018-04-11 12:48:20,009 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-04-11 12:48:20,009 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:20,009 INFO L355 BasicCegarLoop]: trace histogram [9, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:20,009 INFO L408 AbstractCegarLoop]: === Iteration 35 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:20,009 INFO L82 PathProgramCache]: Analyzing trace with hash 1865688502, now seen corresponding path program 7 times [2018-04-11 12:48:20,009 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:20,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:20,024 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:20,412 WARN L151 SmtUtils]: Spent 149ms on a formula simplification. DAG size of input: 101 DAG size of output 61 [2018-04-11 12:48:20,563 WARN L151 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 78 DAG size of output 53 [2018-04-11 12:48:20,715 WARN L151 SmtUtils]: Spent 131ms on a formula simplification. DAG size of input: 78 DAG size of output 53 [2018-04-11 12:48:20,863 WARN L151 SmtUtils]: Spent 124ms on a formula simplification. DAG size of input: 80 DAG size of output 53 [2018-04-11 12:48:21,031 WARN L151 SmtUtils]: Spent 128ms on a formula simplification. DAG size of input: 96 DAG size of output 59 [2018-04-11 12:48:21,159 WARN L151 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 98 DAG size of output 59 [2018-04-11 12:48:21,425 WARN L151 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 68 DAG size of output 51 [2018-04-11 12:48:21,786 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:21,786 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:21,786 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24] total 24 [2018-04-11 12:48:21,786 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:21,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:21,786 INFO L182 omatonBuilderFactory]: Interpolants [7494#true, 7495#false, 7496#(<= 1 main_~length1~0), 7497#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 7498#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 7499#(and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 7500#(and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))) (= 0 main_~nondetString2~0.offset)), 7501#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 5) (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- 1)) (+ main_~nondetString2~0.offset (- 1))))) (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (- 2)) (- 1))))) (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))))), 7502#(and (or (and (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= 7 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1))))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 2)) (- 1)))) (<= 9 (select |#length| |cstrcat_#in~s1.base|))) (<= 8 (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s1.offset|)), 7503#(and (or (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (<= 8 (select |#length| cstrcat_~s~0.base)) (or (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1)))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1)))))) (= cstrcat_~s~0.offset 0)), 7504#(and (or (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (<= 8 (select |#length| cstrcat_~s~0.base)) (or (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1)))))) (= |cstrcat_#t~mem2| 0) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1)))))) (= cstrcat_~s~0.offset 0)), 7505#(and (or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 1)), 7506#(and (= cstrcat_~s~0.offset 1) (or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))))), 7507#(or (and (<= 2 cstrcat_~s~0.offset) (or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 7508#(or (and (<= 2 cstrcat_~s~0.offset) (or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))) (= |cstrcat_#t~mem2| 0)), 7509#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= 3 cstrcat_~s~0.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))))), 7510#(or (= |cstrcat_#t~mem2| 0) (and (<= 3 cstrcat_~s~0.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))))), 7511#(and (or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))) (<= 4 cstrcat_~s~0.offset)), 7512#(and (or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))) (<= 4 cstrcat_~s~0.offset)), 7513#(or (and (<= 5 cstrcat_~s~0.offset) (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 7514#(or (= |cstrcat_#t~mem2| 0) (and (<= 5 cstrcat_~s~0.offset) (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 7515#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= 6 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 7516#(or (= |cstrcat_#t~mem2| 0) (and (<= 6 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 7517#(and (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (<= 7 cstrcat_~s~0.offset)), 7518#(and (<= 8 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))] [2018-04-11 12:48:21,787 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:21,787 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-04-11 12:48:21,787 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-04-11 12:48:21,787 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=552, Unknown=0, NotChecked=0, Total=600 [2018-04-11 12:48:21,787 INFO L87 Difference]: Start difference. First operand 97 states and 104 transitions. Second operand 25 states. [2018-04-11 12:48:23,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:23,289 INFO L93 Difference]: Finished difference Result 124 states and 133 transitions. [2018-04-11 12:48:23,289 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-04-11 12:48:23,289 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 44 [2018-04-11 12:48:23,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:23,289 INFO L225 Difference]: With dead ends: 124 [2018-04-11 12:48:23,290 INFO L226 Difference]: Without dead ends: 124 [2018-04-11 12:48:23,290 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 214 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=158, Invalid=1822, Unknown=0, NotChecked=0, Total=1980 [2018-04-11 12:48:23,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-04-11 12:48:23,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 103. [2018-04-11 12:48:23,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-04-11 12:48:23,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 111 transitions. [2018-04-11 12:48:23,292 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 111 transitions. Word has length 44 [2018-04-11 12:48:23,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:23,292 INFO L459 AbstractCegarLoop]: Abstraction has 103 states and 111 transitions. [2018-04-11 12:48:23,292 INFO L460 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-04-11 12:48:23,292 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 111 transitions. [2018-04-11 12:48:23,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-04-11 12:48:23,293 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:23,293 INFO L355 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:23,293 INFO L408 AbstractCegarLoop]: === Iteration 36 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:23,293 INFO L82 PathProgramCache]: Analyzing trace with hash -1019035851, now seen corresponding path program 5 times [2018-04-11 12:48:23,293 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:23,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:23,304 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:23,713 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:23,714 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:23,714 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-04-11 12:48:23,714 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:23,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:23,714 INFO L182 omatonBuilderFactory]: Interpolants [7808#(or (and (<= 2 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 7809#(and (<= 2 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))), 7786#true, 7787#false, 7788#(<= 1 main_~length3~0), 7789#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 7790#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 7791#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 7792#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|))), 7793#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))))), 7794#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0)))), 7795#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 7796#(and (or (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|))) (= 0 |cstrcat_#in~s2.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 7797#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))))) (= cstrcat_~s~0.offset 0)), 7798#(and (or (and (= 0 cstrcat_~s2.offset) (or (= |cstrcat_#t~mem2| 0) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1))) (= cstrcat_~s~0.offset 0)), 7799#(and (or (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 1)), 7800#(and (= cstrcat_~s~0.offset 1) (or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))))), 7801#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 7802#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))), 7803#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (= |cstrcat_#t~post5.offset| 0) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)), 7804#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 7805#(and (<= 1 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 7806#(and (<= (+ (select |#length| cstrcat_~s2.base) |cstrcat_#t~post4.offset| 1) (+ cstrcat_~s2.offset (select |#length| |cstrcat_#t~post4.base|))) (<= 2 cstrcat_~s~0.offset) (<= (+ (select |#length| |cstrcat_#t~post4.base|) cstrcat_~s~0.offset) (+ |cstrcat_#t~post4.offset| (select |#length| cstrcat_~s~0.base) 1))), 7807#(or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))))] [2018-04-11 12:48:23,714 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:23,715 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-04-11 12:48:23,715 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-04-11 12:48:23,715 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=493, Unknown=0, NotChecked=0, Total=552 [2018-04-11 12:48:23,715 INFO L87 Difference]: Start difference. First operand 103 states and 111 transitions. Second operand 24 states. [2018-04-11 12:48:24,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:24,367 INFO L93 Difference]: Finished difference Result 121 states and 129 transitions. [2018-04-11 12:48:24,367 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-04-11 12:48:24,367 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 44 [2018-04-11 12:48:24,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:24,367 INFO L225 Difference]: With dead ends: 121 [2018-04-11 12:48:24,367 INFO L226 Difference]: Without dead ends: 107 [2018-04-11 12:48:24,368 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 308 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=183, Invalid=1299, Unknown=0, NotChecked=0, Total=1482 [2018-04-11 12:48:24,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-04-11 12:48:24,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 103. [2018-04-11 12:48:24,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-04-11 12:48:24,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 110 transitions. [2018-04-11 12:48:24,369 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 110 transitions. Word has length 44 [2018-04-11 12:48:24,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:24,369 INFO L459 AbstractCegarLoop]: Abstraction has 103 states and 110 transitions. [2018-04-11 12:48:24,369 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-04-11 12:48:24,369 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 110 transitions. [2018-04-11 12:48:24,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-04-11 12:48:24,370 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:24,370 INFO L355 BasicCegarLoop]: trace histogram [6, 6, 5, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:24,370 INFO L408 AbstractCegarLoop]: === Iteration 37 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:24,370 INFO L82 PathProgramCache]: Analyzing trace with hash -397215517, now seen corresponding path program 6 times [2018-04-11 12:48:24,370 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:24,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:24,384 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:25,604 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:25,605 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:25,605 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25] total 25 [2018-04-11 12:48:25,605 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:25,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:25,606 INFO L182 omatonBuilderFactory]: Interpolants [8064#true, 8065#false, 8066#(<= 1 main_~length3~0), 8067#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 8068#(and (<= (select |#length| |main_#t~malloc10.base|) main_~length1~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (or (= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (<= (+ (select |#length| |main_#t~malloc10.base|) main_~length3~0 2) main_~length2~0)) (<= (+ (select |#length| |main_#t~malloc10.base|) main_~length3~0) main_~length2~0) (= (select |#valid| |main_#t~malloc10.base|) 1)), 8069#(and (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (<= (select |#length| main_~nondetString1~0.base) main_~length1~0) (= main_~nondetString1~0.offset 0) (or (and (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base) 1) main_~length2~0) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base) 2) main_~length2~0) (<= main_~length1~0 (select |#length| main_~nondetString1~0.base)))) (= (+ main_~length3~0 main_~length1~0) main_~length2~0))), 8070#(and (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (select |#length| main_~nondetString1~0.base) main_~length1~0) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base) 2) (select |#length| |main_#t~malloc11.base|)) (<= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|))) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| |main_#t~malloc11.base|)) (= main_~nondetString1~0.offset 0)), 8071#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (or (and (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base) 1) (select |#length| main_~nondetString2~0.base)) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base) 2) (select |#length| main_~nondetString2~0.base)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)))) (< (+ main_~length1~0 1) (+ main_~nondetString2~0.offset main_~length3~0)) (and (= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base) 1) (select |#length| main_~nondetString2~0.base)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))))) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) (+ main_~length1~0 1)) (and (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (select |#length| main_~nondetString1~0.base) main_~length1~0)))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 8072#(and (= 0 main_~nondetString2~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 8073#(and (= 0 main_~nondetString2~0.offset) (or (and (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (- 3))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (- 3))) (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= main_~nondetString1~0.offset 0)), 8074#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (or (and (or (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 3) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1))))) (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 2) (select |#length| |cstrcat_#in~s1.base|))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (select |#length| |cstrcat_#in~s1.base|) (- 3)))) (<= 7 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 3)) (- 1))))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s2.offset|))) (= 0 |cstrcat_#in~s1.offset|)), 8075#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 cstrcat_~s2.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 3)) (- 1)))) (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s~0.base) (- 3))))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 0)), 8076#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (<= 3 (select |#length| cstrcat_~s2.base))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 3)) (- 1)))) (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s~0.base) (- 3))))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base)))))) (= cstrcat_~s~0.offset 0)), 8077#(or (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))))) (<= 3 (select |#length| cstrcat_~s2.base))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 3)) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s~0.base) (- 3))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))))), 8078#(or (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))))) (<= 3 (select |#length| cstrcat_~s2.base))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 3)) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s~0.base) (- 3))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))))), 8079#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s~0.base) (- 3)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))))), 8080#(and (or (<= (select |#length| cstrcat_~s2.base) 1) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s~0.base) (- 3)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))))) (= 0 cstrcat_~s2.offset)), 8081#(or (and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 1) (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 8082#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 1) (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))))), 8083#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 1) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 8084#(and (or (<= (select |#length| cstrcat_~s2.base) 1) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= 0 cstrcat_~s2.offset)), 8085#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (= |cstrcat_#t~post5.offset| 0) (or (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)), 8086#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 8087#(and (or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= 1 cstrcat_~s~0.offset)), 8088#(and (<= 1 |cstrcat_#t~post4.offset|) (or (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|))), 8089#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:48:25,606 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:25,606 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-04-11 12:48:25,606 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-04-11 12:48:25,606 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=587, Unknown=0, NotChecked=0, Total=650 [2018-04-11 12:48:25,607 INFO L87 Difference]: Start difference. First operand 103 states and 110 transitions. Second operand 26 states. [2018-04-11 12:48:26,067 WARN L151 SmtUtils]: Spent 155ms on a formula simplification. DAG size of input: 112 DAG size of output 92 [2018-04-11 12:48:26,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:26,865 INFO L93 Difference]: Finished difference Result 117 states and 124 transitions. [2018-04-11 12:48:26,865 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-04-11 12:48:26,865 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 45 [2018-04-11 12:48:26,865 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:26,866 INFO L225 Difference]: With dead ends: 117 [2018-04-11 12:48:26,866 INFO L226 Difference]: Without dead ends: 117 [2018-04-11 12:48:26,866 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 358 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=195, Invalid=1611, Unknown=0, NotChecked=0, Total=1806 [2018-04-11 12:48:26,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-04-11 12:48:26,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 103. [2018-04-11 12:48:26,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-04-11 12:48:26,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 110 transitions. [2018-04-11 12:48:26,868 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 110 transitions. Word has length 45 [2018-04-11 12:48:26,868 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:26,868 INFO L459 AbstractCegarLoop]: Abstraction has 103 states and 110 transitions. [2018-04-11 12:48:26,868 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-04-11 12:48:26,868 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 110 transitions. [2018-04-11 12:48:26,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-04-11 12:48:26,868 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:26,869 INFO L355 BasicCegarLoop]: trace histogram [10, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:26,869 INFO L408 AbstractCegarLoop]: === Iteration 38 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:26,869 INFO L82 PathProgramCache]: Analyzing trace with hash -445614740, now seen corresponding path program 8 times [2018-04-11 12:48:26,869 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:26,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:26,880 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:27,318 WARN L151 SmtUtils]: Spent 147ms on a formula simplification. DAG size of input: 193 DAG size of output 67 [2018-04-11 12:48:27,469 WARN L151 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 142 DAG size of output 60 [2018-04-11 12:48:27,834 WARN L151 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 158 DAG size of output 65 [2018-04-11 12:48:28,016 WARN L151 SmtUtils]: Spent 152ms on a formula simplification. DAG size of input: 160 DAG size of output 65 [2018-04-11 12:48:28,713 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:28,714 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:28,714 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27] total 27 [2018-04-11 12:48:28,714 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:28,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:28,714 INFO L182 omatonBuilderFactory]: Interpolants [8344#true, 8345#false, 8346#(<= 1 main_~length1~0), 8347#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 8348#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 8349#(and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 8350#(and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))) (= 0 main_~nondetString2~0.offset)), 8351#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 1) (- 1))))) (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) (+ main_~nondetString2~0.offset (- 1))))) (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))))), 8352#(and (or (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 5 2) 1) (- 1)))) (<= 10 (select |#length| |cstrcat_#in~s1.base|))) (<= 9 (select |#length| |cstrcat_#in~s1.base|))) (and (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 1) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= 6 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 2) (- 1)))) (<= 8 (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s1.offset|)), 8353#(and (or (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 2) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (or (<= 10 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 1) (- 1))))))) (= cstrcat_~s~0.offset 0)), 8354#(and (or (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 2) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (or (<= 10 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 1) (- 1))))))) (= cstrcat_~s~0.offset 0)), 8355#(and (= cstrcat_~s~0.offset 1) (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))))), 8356#(and (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1)))))) (= cstrcat_~s~0.offset 1)), 8357#(or (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 8358#(or (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 8359#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))))), 8360#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))))), 8361#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 8362#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 8363#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))), 8364#(or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))), 8365#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 8366#(or (= |cstrcat_#t~mem2| 0) (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 8367#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 8368#(or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 8369#(<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)), 8370#(and (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (<= 0 cstrcat_~s~0.offset)), 8371#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))] [2018-04-11 12:48:28,716 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:28,716 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-04-11 12:48:28,716 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-04-11 12:48:28,717 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=659, Unknown=0, NotChecked=0, Total=756 [2018-04-11 12:48:28,717 INFO L87 Difference]: Start difference. First operand 103 states and 110 transitions. Second operand 28 states. [2018-04-11 12:48:29,395 WARN L151 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 117 DAG size of output 116 [2018-04-11 12:48:29,637 WARN L151 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 112 DAG size of output 109 [2018-04-11 12:48:30,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:30,768 INFO L93 Difference]: Finished difference Result 130 states and 139 transitions. [2018-04-11 12:48:30,769 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-04-11 12:48:30,769 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 47 [2018-04-11 12:48:30,769 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:30,769 INFO L225 Difference]: With dead ends: 130 [2018-04-11 12:48:30,769 INFO L226 Difference]: Without dead ends: 130 [2018-04-11 12:48:30,770 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 361 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=390, Invalid=2060, Unknown=0, NotChecked=0, Total=2450 [2018-04-11 12:48:30,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2018-04-11 12:48:30,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 109. [2018-04-11 12:48:30,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-04-11 12:48:30,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 117 transitions. [2018-04-11 12:48:30,771 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 117 transitions. Word has length 47 [2018-04-11 12:48:30,771 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:30,771 INFO L459 AbstractCegarLoop]: Abstraction has 109 states and 117 transitions. [2018-04-11 12:48:30,771 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-04-11 12:48:30,772 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 117 transitions. [2018-04-11 12:48:30,772 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-04-11 12:48:30,772 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:30,772 INFO L355 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:30,772 INFO L408 AbstractCegarLoop]: === Iteration 39 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:30,772 INFO L82 PathProgramCache]: Analyzing trace with hash -1877333073, now seen corresponding path program 7 times [2018-04-11 12:48:30,773 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:30,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:30,783 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:31,571 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 43 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:31,572 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:31,572 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25] total 25 [2018-04-11 12:48:31,572 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:31,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:31,572 INFO L182 omatonBuilderFactory]: Interpolants [8655#true, 8656#false, 8657#(<= 1 main_~length3~0), 8658#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 8659#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 8660#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 8661#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|)) (= main_~nondetString1~0.offset 0)), 8662#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)))), 8663#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0)), 8664#(and (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 main_~nondetString2~0.offset) (or (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 1) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))))), 8665#(and (= 0 |cstrcat_#in~s2.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (and (or (<= 4 (select |#length| |cstrcat_#in~s2.base|)) (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 1) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (select |#length| |cstrcat_#in~s2.base|) (- 1))))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)))), 8666#(and (= 0 cstrcat_~s2.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 8667#(and (= 0 cstrcat_~s2.offset) (or (= |cstrcat_#t~mem2| 0) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)))), 8668#(and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (<= 4 (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base)))) (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))))), 8669#(and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (<= 4 (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base)))) (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset)))), 8670#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 8671#(and (or (<= 4 (select |#length| cstrcat_~s2.base)) (= |cstrcat_#t~mem2| 0) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1))) (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 8672#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base)) (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (select |#length| cstrcat_~s2.base) 2) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 8673#(and (= 0 cstrcat_~s2.offset) (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (select |#length| cstrcat_~s2.base) 2) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1))), 8674#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (<= (+ cstrcat_~s2.offset 3) (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|))) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base))) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) (+ cstrcat_~s2.offset 1))) (= |cstrcat_#t~post5.offset| 0) (= |cstrcat_#t~post5.base| cstrcat_~s2.base) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base) 1))), 8675#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s2.offset 3) (select |#length| cstrcat_~s2.base)) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base) 1))), 8676#(and (or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s2.offset 3) (select |#length| cstrcat_~s2.base)) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))) (<= 1 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base) 1))), 8677#(and (<= 2 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) |cstrcat_#t~post4.offset|) (+ (select |#length| |cstrcat_#t~post4.base|) cstrcat_~s2.offset)) (<= (+ (select |#length| |cstrcat_#t~post4.base|) cstrcat_~s~0.offset) (+ |cstrcat_#t~post4.offset| (select |#length| cstrcat_~s~0.base) 1)) (or (<= (+ cstrcat_~s2.offset 2) (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) |cstrcat_#t~post4.offset|) (+ (* 2 cstrcat_~s2.offset) (select |#length| |cstrcat_#t~post4.base|))))), 8678#(or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 8679#(or (and (<= 2 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 8680#(and (<= 2 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:48:31,572 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 43 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:31,573 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-04-11 12:48:31,573 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-04-11 12:48:31,573 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=584, Unknown=0, NotChecked=0, Total=650 [2018-04-11 12:48:31,573 INFO L87 Difference]: Start difference. First operand 109 states and 117 transitions. Second operand 26 states. [2018-04-11 12:48:32,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:32,292 INFO L93 Difference]: Finished difference Result 128 states and 136 transitions. [2018-04-11 12:48:32,292 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-04-11 12:48:32,292 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 47 [2018-04-11 12:48:32,292 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:32,292 INFO L225 Difference]: With dead ends: 128 [2018-04-11 12:48:32,292 INFO L226 Difference]: Without dead ends: 128 [2018-04-11 12:48:32,293 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 304 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=162, Invalid=1398, Unknown=0, NotChecked=0, Total=1560 [2018-04-11 12:48:32,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-04-11 12:48:32,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 114. [2018-04-11 12:48:32,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-04-11 12:48:32,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 122 transitions. [2018-04-11 12:48:32,294 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 122 transitions. Word has length 47 [2018-04-11 12:48:32,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:32,294 INFO L459 AbstractCegarLoop]: Abstraction has 114 states and 122 transitions. [2018-04-11 12:48:32,294 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-04-11 12:48:32,294 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 122 transitions. [2018-04-11 12:48:32,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-04-11 12:48:32,295 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:32,295 INFO L355 BasicCegarLoop]: trace histogram [7, 7, 6, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:32,295 INFO L408 AbstractCegarLoop]: === Iteration 40 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:32,295 INFO L82 PathProgramCache]: Analyzing trace with hash -1234625623, now seen corresponding path program 8 times [2018-04-11 12:48:32,295 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:32,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:32,306 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:33,030 WARN L151 SmtUtils]: Spent 160ms on a formula simplification. DAG size of input: 129 DAG size of output 76 [2018-04-11 12:48:33,166 WARN L151 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 108 DAG size of output 61 [2018-04-11 12:48:33,309 WARN L151 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 108 DAG size of output 67 [2018-04-11 12:48:33,470 WARN L151 SmtUtils]: Spent 143ms on a formula simplification. DAG size of input: 110 DAG size of output 67 [2018-04-11 12:48:33,698 WARN L151 SmtUtils]: Spent 203ms on a formula simplification. DAG size of input: 136 DAG size of output 98 [2018-04-11 12:48:33,920 WARN L151 SmtUtils]: Spent 194ms on a formula simplification. DAG size of input: 138 DAG size of output 98 [2018-04-11 12:48:34,359 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 0 proven. 67 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:34,359 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:34,359 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-04-11 12:48:34,359 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:34,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:34,360 INFO L182 omatonBuilderFactory]: Interpolants [8960#(and (= 0 main_~nondetString2~0.offset) (or (and (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ main_~nondetString2~0.offset (+ (- main_~nondetString2~0.offset) 3)) (- main_~nondetString2~0.offset)) (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 main_~nondetString1~0.offset) (or (and (or (<= (+ (select |#length| main_~nondetString1~0.base) 1) (div (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (- 2))) 2)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (select |#length| main_~nondetString2~0.base) (+ (- (+ (- main_~nondetString2~0.offset) 3)) (- 1)))))) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (- (+ (select |#length| main_~nondetString2~0.base) (- (+ (- main_~nondetString2~0.offset) 3))))) (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 8961#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (select |#length| |cstrcat_#in~s1.base|) (+ (- 3) (- 1))))) (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1))))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 1) (div (+ (select |#length| |cstrcat_#in~s1.base|) (- 2)) 2))) (or (<= (+ (select |#length| |cstrcat_#in~s2.base|) 5) (select |#length| |cstrcat_#in~s1.base|)) (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1))))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s2.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s1.base|))) (<= 8 (select |#length| |cstrcat_#in~s1.base|))) (= 0 |cstrcat_#in~s1.offset|)), 8962#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 cstrcat_~s2.offset) (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base)))) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s~0.base) (+ (- 3) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 1) (div (+ (select |#length| cstrcat_~s~0.base) (- 2)) 2)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (+ (select |#length| cstrcat_~s~0.base) (- 3)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))))) (<= 8 (select |#length| cstrcat_~s~0.base))) (= cstrcat_~s~0.offset 0)), 8963#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (and (= 0 cstrcat_~s2.offset) (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base)))) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s~0.base) (+ (- 3) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 1) (div (+ (select |#length| cstrcat_~s~0.base) (- 2)) 2)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (+ (select |#length| cstrcat_~s~0.base) (- 3)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))))) (<= 8 (select |#length| cstrcat_~s~0.base))) (= cstrcat_~s~0.offset 0)), 8964#(or (and (= 0 cstrcat_~s2.offset) (<= cstrcat_~s~0.offset 1) (or (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset 2)) (- 2)))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ (* 2 cstrcat_~s~0.offset) (- 4))) 2) 1)) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (div (+ (select |#length| cstrcat_~s~0.base) (+ (* 2 cstrcat_~s~0.offset) (- 4))) 2)))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 2)))) (- 1)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (and (or (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset 2)) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ (* 2 cstrcat_~s~0.offset) (- 4))) 2) 1)) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (div (+ (select |#length| cstrcat_~s~0.base) (+ (* 2 cstrcat_~s~0.offset) (- 4))) 2)))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset 2)) (- 1))))) (+ cstrcat_~s~0.offset (- 1)))) (- 1))))))) (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))), 8965#(or (and (= 0 cstrcat_~s2.offset) (<= cstrcat_~s~0.offset 1) (or (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset 2)) (- 2)))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ (* 2 cstrcat_~s~0.offset) (- 4))) 2) 1)) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (div (+ (select |#length| cstrcat_~s~0.base) (+ (* 2 cstrcat_~s~0.offset) (- 4))) 2)))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 2)))) (- 1)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (and (or (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset 2)) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ (* 2 cstrcat_~s~0.offset) (- 4))) 2) 1)) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (div (+ (select |#length| cstrcat_~s~0.base) (+ (* 2 cstrcat_~s~0.offset) (- 4))) 2)))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset 2)) (- 1))))) (+ cstrcat_~s~0.offset (- 1)))) (- 1))))))) (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))), 8966#(or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1) (<= cstrcat_~s~0.offset 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 3)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 8967#(or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1) (<= cstrcat_~s~0.offset 2)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 3)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 8968#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1) (<= cstrcat_~s~0.offset 3)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 8969#(or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1) (<= cstrcat_~s~0.offset 3)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 8970#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1) (<= cstrcat_~s~0.offset 4)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 8971#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1) (<= cstrcat_~s~0.offset 4))), 8972#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1) (<= cstrcat_~s~0.offset 5)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 8973#(or (and (<= cstrcat_~s~0.offset 6) (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 8974#(or (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1) (<= (select |#length| cstrcat_~s~0.base) 7))), 8975#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (and (<= (+ |cstrcat_#t~post5.offset| 1) cstrcat_~s2.offset) (<= (select |#length| |cstrcat_#t~post5.base|) 1) (= |cstrcat_#t~post5.offset| 0) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)))), 8976#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 8977#(and (or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= 1 cstrcat_~s~0.offset)), 8978#(and (<= 1 |cstrcat_#t~post4.offset|) (or (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|))), 8979#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))), 8951#true, 8952#false, 8953#(<= 1 main_~length3~0), 8954#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 8955#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 8956#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 8957#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|))), 8958#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (or (<= (+ main_~nondetString2~0.offset (* 2 main_~length3~0)) (select |#length| main_~nondetString2~0.base)) (and (= 0 main_~nondetString1~0.offset) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base))))), 8959#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))) (<= (+ main_~nondetString2~0.offset (* 2 main_~length3~0)) (select |#length| main_~nondetString2~0.base))) (<= 1 main_~length3~0))] [2018-04-11 12:48:34,360 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 0 proven. 67 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:34,360 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-04-11 12:48:34,360 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-04-11 12:48:34,360 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=731, Unknown=0, NotChecked=0, Total=812 [2018-04-11 12:48:34,361 INFO L87 Difference]: Start difference. First operand 114 states and 122 transitions. Second operand 29 states. [2018-04-11 12:48:35,150 WARN L151 SmtUtils]: Spent 172ms on a formula simplification. DAG size of input: 151 DAG size of output 150 [2018-04-11 12:48:35,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:35,845 INFO L93 Difference]: Finished difference Result 137 states and 145 transitions. [2018-04-11 12:48:35,845 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-04-11 12:48:35,845 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 48 [2018-04-11 12:48:35,846 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:35,846 INFO L225 Difference]: With dead ends: 137 [2018-04-11 12:48:35,846 INFO L226 Difference]: Without dead ends: 137 [2018-04-11 12:48:35,846 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 469 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=248, Invalid=1914, Unknown=0, NotChecked=0, Total=2162 [2018-04-11 12:48:35,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2018-04-11 12:48:35,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 114. [2018-04-11 12:48:35,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-04-11 12:48:35,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 122 transitions. [2018-04-11 12:48:35,848 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 122 transitions. Word has length 48 [2018-04-11 12:48:35,848 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:35,848 INFO L459 AbstractCegarLoop]: Abstraction has 114 states and 122 transitions. [2018-04-11 12:48:35,848 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-04-11 12:48:35,848 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 122 transitions. [2018-04-11 12:48:35,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-04-11 12:48:35,848 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:35,848 INFO L355 BasicCegarLoop]: trace histogram [11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:35,848 INFO L408 AbstractCegarLoop]: === Iteration 41 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:35,848 INFO L82 PathProgramCache]: Analyzing trace with hash 435192310, now seen corresponding path program 9 times [2018-04-11 12:48:35,849 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:35,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:35,864 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:36,517 WARN L151 SmtUtils]: Spent 217ms on a formula simplification. DAG size of input: 221 DAG size of output 74 [2018-04-11 12:48:36,716 WARN L151 SmtUtils]: Spent 172ms on a formula simplification. DAG size of input: 199 DAG size of output 67 [2018-04-11 12:48:36,906 WARN L151 SmtUtils]: Spent 162ms on a formula simplification. DAG size of input: 199 DAG size of output 67 [2018-04-11 12:48:37,093 WARN L151 SmtUtils]: Spent 154ms on a formula simplification. DAG size of input: 201 DAG size of output 67 [2018-04-11 12:48:37,308 WARN L151 SmtUtils]: Spent 178ms on a formula simplification. DAG size of input: 216 DAG size of output 73 [2018-04-11 12:48:37,519 WARN L151 SmtUtils]: Spent 171ms on a formula simplification. DAG size of input: 218 DAG size of output 73 [2018-04-11 12:48:37,675 WARN L151 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 145 DAG size of output 64 [2018-04-11 12:48:37,847 WARN L151 SmtUtils]: Spent 137ms on a formula simplification. DAG size of input: 147 DAG size of output 64 [2018-04-11 12:48:38,543 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:38,543 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:38,544 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-04-11 12:48:38,544 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:38,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:38,544 INFO L182 omatonBuilderFactory]: Interpolants [9280#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))))), 9281#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))))), 9282#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 9283#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1)))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 9284#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1))))))), 9285#(or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1))))))), 9286#(or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 9287#(or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 9288#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))), 9289#(or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))), 9290#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 9291#(or (= |cstrcat_#t~mem2| 0) (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 9292#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 9293#(or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (<= 0 cstrcat_~s~0.offset))), 9294#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 9295#(and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 9267#true, 9268#false, 9269#(<= 1 main_~length1~0), 9270#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 9271#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 9272#(and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 9273#(and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))) (= 0 main_~nondetString2~0.offset)), 9274#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) (+ main_~nondetString2~0.offset (- 1))))) (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (- 1)) (- 1))))) (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= 11 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 1) (+ main_~nondetString2~0.offset (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))))), 9275#(and (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1)))) (<= 8 (select |#length| |cstrcat_#in~s1.base|))) (and (<= 10 (select |#length| |cstrcat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 5 2) 1) (- 1)))) (<= 11 (select |#length| |cstrcat_#in~s1.base|)))) (and (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 1) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s1.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 2) (- 1)))) (<= 9 (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= 6 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1)))))) (= 0 |cstrcat_#in~s1.offset|)), 9276#(and (or (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 10 (select |#length| cstrcat_~s~0.base)) (or (<= 11 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 1) (- 1)))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 9277#(and (or (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 10 (select |#length| cstrcat_~s~0.base)) (or (<= 11 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 1) (- 1)))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 2) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 9278#(and (= cstrcat_~s~0.offset 1) (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))))), 9279#(and (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))))) (= cstrcat_~s~0.offset 1))] [2018-04-11 12:48:38,544 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:38,544 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-04-11 12:48:38,544 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-04-11 12:48:38,545 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=106, Invalid=706, Unknown=0, NotChecked=0, Total=812 [2018-04-11 12:48:38,545 INFO L87 Difference]: Start difference. First operand 114 states and 122 transitions. Second operand 29 states. [2018-04-11 12:48:39,319 WARN L151 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 123 DAG size of output 117 [2018-04-11 12:48:39,484 WARN L151 SmtUtils]: Spent 143ms on a formula simplification. DAG size of input: 129 DAG size of output 123 [2018-04-11 12:48:39,741 WARN L151 SmtUtils]: Spent 112ms on a formula simplification. DAG size of input: 121 DAG size of output 115 [2018-04-11 12:48:39,995 WARN L151 SmtUtils]: Spent 124ms on a formula simplification. DAG size of input: 115 DAG size of output 109 [2018-04-11 12:48:40,257 WARN L151 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 108 DAG size of output 102 [2018-04-11 12:48:41,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:41,103 INFO L93 Difference]: Finished difference Result 148 states and 158 transitions. [2018-04-11 12:48:41,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-04-11 12:48:41,103 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 50 [2018-04-11 12:48:41,103 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:41,103 INFO L225 Difference]: With dead ends: 148 [2018-04-11 12:48:41,103 INFO L226 Difference]: Without dead ends: 148 [2018-04-11 12:48:41,104 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 413 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=441, Invalid=2315, Unknown=0, NotChecked=0, Total=2756 [2018-04-11 12:48:41,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-04-11 12:48:41,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 120. [2018-04-11 12:48:41,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-04-11 12:48:41,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 129 transitions. [2018-04-11 12:48:41,105 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 129 transitions. Word has length 50 [2018-04-11 12:48:41,105 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:41,106 INFO L459 AbstractCegarLoop]: Abstraction has 120 states and 129 transitions. [2018-04-11 12:48:41,106 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-04-11 12:48:41,106 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 129 transitions. [2018-04-11 12:48:41,106 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-04-11 12:48:41,106 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:41,106 INFO L355 BasicCegarLoop]: trace histogram [6, 6, 5, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:41,106 INFO L408 AbstractCegarLoop]: === Iteration 42 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:41,106 INFO L82 PathProgramCache]: Analyzing trace with hash 825406709, now seen corresponding path program 9 times [2018-04-11 12:48:41,106 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:41,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:41,117 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:42,097 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:42,097 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:42,097 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27] total 27 [2018-04-11 12:48:42,097 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:42,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:42,097 INFO L182 omatonBuilderFactory]: Interpolants [9612#true, 9613#false, 9614#(<= 1 main_~length3~0), 9615#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 9616#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 9617#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= (select |#length| main_~nondetString1~0.base) main_~length1~0) (= main_~nondetString1~0.offset 0)), 9618#(and (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (= (select |#length| main_~nondetString1~0.base) main_~length1~0) (or (<= (+ main_~length3~0 main_~length1~0 1) (select |#length| |main_#t~malloc11.base|)) (= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|))) (= main_~nondetString1~0.offset 0)), 9619#(and (= 0 main_~nondetString2~0.offset) (or (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 9620#(and (= 0 main_~nondetString2~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 9621#(and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (or (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (- 1)))))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) (select |#length| main_~nondetString1~0.base)) (- 1))))) (<= 4 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (select |#length| main_~nondetString1~0.base))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))))))) (= main_~nondetString1~0.offset 0)), 9622#(or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (select |#length| |cstrcat_#in~s2.base|))) (<= 4 (select |#length| |cstrcat_#in~s2.base|)) (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 2) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (select |#length| |cstrcat_#in~s2.base|) (- 1))))) (or (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1))))) (= 0 |cstrcat_#in~s2.offset|) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s1.offset|))), 9623#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (or (<= 4 (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 9624#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (or (<= 4 (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)) (= |cstrcat_#t~mem2| 0)), 9625#(or (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (and (= 0 cstrcat_~s2.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset)) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (and (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (+ (select |#length| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) (- 1))))) (= 1 cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))))))))), 9626#(or (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset)) (and (= 0 cstrcat_~s2.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset)) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (and (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (+ (select |#length| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) (- 1))))) (= 1 cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))))))))), 9627#(or (and (= 0 cstrcat_~s2.offset) (or (and (= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 4) (+ (select |#length| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s~0.base) (- 4)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 9628#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (and (= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 4) (+ (select |#length| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s~0.base) (- 4)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 9629#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 9630#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 9631#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))), 9632#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 9633#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (and (= |cstrcat_#t~post5.offset| 0) (= |cstrcat_#t~post5.base| cstrcat_~s2.base) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) (+ cstrcat_~s2.offset 1))) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 9634#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 9635#(and (or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (<= 1 cstrcat_~s~0.offset)), 9636#(and (<= 2 cstrcat_~s~0.offset) (or (<= (+ |cstrcat_#t~post4.offset| 2) (select |#length| |cstrcat_#t~post4.base|)) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)) (<= (+ (select |#length| |cstrcat_#t~post4.base|) cstrcat_~s~0.offset) (+ |cstrcat_#t~post4.offset| (select |#length| cstrcat_~s~0.base) 1))), 9637#(or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 9638#(or (and (<= 2 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 9639#(and (<= 2 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:48:42,098 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:42,098 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-04-11 12:48:42,098 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-04-11 12:48:42,098 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=686, Unknown=0, NotChecked=0, Total=756 [2018-04-11 12:48:42,098 INFO L87 Difference]: Start difference. First operand 120 states and 129 transitions. Second operand 28 states. [2018-04-11 12:48:42,678 WARN L151 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 105 DAG size of output 104 [2018-04-11 12:48:43,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:43,123 INFO L93 Difference]: Finished difference Result 148 states and 157 transitions. [2018-04-11 12:48:43,123 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-04-11 12:48:43,123 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 50 [2018-04-11 12:48:43,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:43,124 INFO L225 Difference]: With dead ends: 148 [2018-04-11 12:48:43,124 INFO L226 Difference]: Without dead ends: 148 [2018-04-11 12:48:43,124 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 375 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=193, Invalid=1699, Unknown=0, NotChecked=0, Total=1892 [2018-04-11 12:48:43,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-04-11 12:48:43,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 120. [2018-04-11 12:48:43,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-04-11 12:48:43,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 129 transitions. [2018-04-11 12:48:43,126 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 129 transitions. Word has length 50 [2018-04-11 12:48:43,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:43,126 INFO L459 AbstractCegarLoop]: Abstraction has 120 states and 129 transitions. [2018-04-11 12:48:43,126 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-04-11 12:48:43,126 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 129 transitions. [2018-04-11 12:48:43,126 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-04-11 12:48:43,126 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:43,126 INFO L355 BasicCegarLoop]: trace histogram [8, 8, 7, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:43,126 INFO L408 AbstractCegarLoop]: === Iteration 43 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:43,126 INFO L82 PathProgramCache]: Analyzing trace with hash 945928995, now seen corresponding path program 10 times [2018-04-11 12:48:43,127 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:43,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:43,139 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:43,500 WARN L151 SmtUtils]: Spent 152ms on a formula simplification. DAG size of input: 88 DAG size of output 66 [2018-04-11 12:48:43,748 WARN L151 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 68 DAG size of output 55 [2018-04-11 12:48:43,878 WARN L151 SmtUtils]: Spent 115ms on a formula simplification. DAG size of input: 70 DAG size of output 55 [2018-04-11 12:48:44,005 WARN L151 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 83 DAG size of output 58 [2018-04-11 12:48:44,127 WARN L151 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 85 DAG size of output 58 [2018-04-11 12:48:44,616 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 0 proven. 88 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:44,616 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:44,616 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-04-11 12:48:44,616 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:44,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:44,617 INFO L182 omatonBuilderFactory]: Interpolants [9940#true, 9941#false, 9942#(<= 1 main_~length3~0), 9943#(and (<= 1 main_~length3~0) (or (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (< 8 main_~length2~0))), 9944#(and (<= 1 main_~length3~0) (or (and (= 0 |main_#t~malloc10.offset|) (<= (+ (select |#length| |main_#t~malloc10.base|) main_~length3~0) main_~length2~0)) (< 8 main_~length2~0)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 9945#(and (or (and (= 0 main_~nondetString1~0.offset) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) main_~length2~0)) (< 8 main_~length2~0)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 9946#(and (or (and (= 0 main_~nondetString1~0.offset) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) 8)) (<= 9 (select |#length| |main_#t~malloc11.base|))) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|)), 9947#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (or (and (= 0 main_~nondetString1~0.offset) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) 8)) (<= 9 (select |#length| main_~nondetString2~0.base)))), 9948#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (or (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 2)) (or (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 1)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- (select |#length| main_~nondetString1~0.base)) 7) (- 1))))))) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 5)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 3) (- 1)))))) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 4)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 3)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) 8) (+ main_~nondetString2~0.offset (- 1)))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (<= 9 (select |#length| main_~nondetString2~0.base)))), 9949#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (= 0 |cstrcat_#in~s2.offset|) (or (and (<= (select |#length| |cstrcat_#in~s2.base|) 2) (or (<= (select |#length| |cstrcat_#in~s2.base|) 1) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) 7) (- 1)))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1)))) (<= (select |#length| |cstrcat_#in~s2.base|) 5)) (and (<= (select |#length| |cstrcat_#in~s2.base|) 4) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) 8) (- 1)))) (<= (select |#length| |cstrcat_#in~s2.base|) 3)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (<= 9 (select |#length| |cstrcat_#in~s1.base|))) (= 0 |cstrcat_#in~s1.offset|)), 9950#(and (or (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) 7) (- 1)))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) 8) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 0)), 9951#(and (or (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) 7) (- 1)))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) 8) (- 1)))))))) (= cstrcat_~s~0.offset 0)), 9952#(or (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 6)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 7)) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))))), 9953#(or (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 6)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 7)) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))))), 9954#(or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 6)) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 5)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 9955#(or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 6)) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 5)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))))), 9956#(or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 5)) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 4)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))))), 9957#(or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (or (= |cstrcat_#t~mem2| 0) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 5)) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 4)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2))))), 9958#(or (and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 4)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 9959#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 4)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 9960#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 9961#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 9962#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 9963#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 9964#(and (or (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (and (<= (select |#length| cstrcat_~s2.base) 1) (<= (+ |cstrcat_#t~post5.offset| 1) cstrcat_~s2.offset) (= |cstrcat_#t~post5.offset| 0))) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)), 9965#(or (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 9966#(or (and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 9967#(or (and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 9968#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:48:44,617 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 0 proven. 88 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:44,617 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-04-11 12:48:44,617 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-04-11 12:48:44,617 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=749, Unknown=0, NotChecked=0, Total=812 [2018-04-11 12:48:44,617 INFO L87 Difference]: Start difference. First operand 120 states and 129 transitions. Second operand 29 states. [2018-04-11 12:48:44,950 WARN L151 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 100 DAG size of output 96 [2018-04-11 12:48:46,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:46,162 INFO L93 Difference]: Finished difference Result 145 states and 154 transitions. [2018-04-11 12:48:46,162 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-04-11 12:48:46,162 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 51 [2018-04-11 12:48:46,162 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:46,163 INFO L225 Difference]: With dead ends: 145 [2018-04-11 12:48:46,163 INFO L226 Difference]: Without dead ends: 145 [2018-04-11 12:48:46,163 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 408 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=188, Invalid=2262, Unknown=0, NotChecked=0, Total=2450 [2018-04-11 12:48:46,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-04-11 12:48:46,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 120. [2018-04-11 12:48:46,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-04-11 12:48:46,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 129 transitions. [2018-04-11 12:48:46,165 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 129 transitions. Word has length 51 [2018-04-11 12:48:46,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:46,165 INFO L459 AbstractCegarLoop]: Abstraction has 120 states and 129 transitions. [2018-04-11 12:48:46,165 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-04-11 12:48:46,165 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 129 transitions. [2018-04-11 12:48:46,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-04-11 12:48:46,165 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:46,165 INFO L355 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:46,165 INFO L408 AbstractCegarLoop]: === Iteration 44 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:46,165 INFO L82 PathProgramCache]: Analyzing trace with hash -63479383, now seen corresponding path program 11 times [2018-04-11 12:48:46,166 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:46,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:46,175 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:46,719 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:46,719 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:46,719 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25] total 25 [2018-04-11 12:48:46,719 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:46,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:46,720 INFO L182 omatonBuilderFactory]: Interpolants [10276#true, 10277#false, 10278#(<= 1 main_~length3~0), 10279#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 10280#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 10281#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 10282#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|)) (= main_~nondetString1~0.offset 0)), 10283#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 10284#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)))) (= main_~nondetString1~0.offset 0)), 10285#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (= main_~nondetString1~0.offset 0)), 10286#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1))))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s2.offset|) (= 0 |cstrcat_#in~s1.offset|)), 10287#(and (= 0 cstrcat_~s2.offset) (= cstrcat_~s~0.offset 0) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 10288#(and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0)) (= cstrcat_~s~0.offset 0)), 10289#(and (or (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))))) (= 0 cstrcat_~s2.offset)), 10290#(and (= 0 cstrcat_~s2.offset) (or (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset)) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))))), 10291#(and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 10292#(and (= 0 cstrcat_~s2.offset) (or (= |cstrcat_#t~mem2| 0) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 10293#(or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 10294#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset))), 10295#(or (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (and (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) (+ cstrcat_~s2.offset 2)) (= |cstrcat_#t~post5.offset| 0) (= |cstrcat_#t~post5.base| cstrcat_~s2.base))), 10296#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 2)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 10297#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 10298#(or (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ (select |#length| |cstrcat_#t~post4.base|) cstrcat_~s~0.offset) (+ |cstrcat_#t~post4.offset| (select |#length| cstrcat_~s~0.base) 1)) (<= (+ |cstrcat_#t~post4.offset| 2) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 10299#(or (and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 10300#(or (and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 10301#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:48:46,720 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:46,720 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-04-11 12:48:46,720 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-04-11 12:48:46,720 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=587, Unknown=0, NotChecked=0, Total=650 [2018-04-11 12:48:46,720 INFO L87 Difference]: Start difference. First operand 120 states and 129 transitions. Second operand 26 states. [2018-04-11 12:48:47,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:47,424 INFO L93 Difference]: Finished difference Result 148 states and 157 transitions. [2018-04-11 12:48:47,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-04-11 12:48:47,424 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 52 [2018-04-11 12:48:47,424 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:47,424 INFO L225 Difference]: With dead ends: 148 [2018-04-11 12:48:47,425 INFO L226 Difference]: Without dead ends: 148 [2018-04-11 12:48:47,425 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 314 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=167, Invalid=1393, Unknown=0, NotChecked=0, Total=1560 [2018-04-11 12:48:47,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-04-11 12:48:47,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 125. [2018-04-11 12:48:47,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-04-11 12:48:47,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 134 transitions. [2018-04-11 12:48:47,426 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 134 transitions. Word has length 52 [2018-04-11 12:48:47,426 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:47,427 INFO L459 AbstractCegarLoop]: Abstraction has 125 states and 134 transitions. [2018-04-11 12:48:47,427 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-04-11 12:48:47,427 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 134 transitions. [2018-04-11 12:48:47,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-04-11 12:48:47,427 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:47,427 INFO L355 BasicCegarLoop]: trace histogram [12, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:47,427 INFO L408 AbstractCegarLoop]: === Iteration 45 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:47,427 INFO L82 PathProgramCache]: Analyzing trace with hash -1692159700, now seen corresponding path program 10 times [2018-04-11 12:48:47,427 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:47,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:47,436 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:48,341 WARN L151 SmtUtils]: Spent 297ms on a formula simplification. DAG size of input: 288 DAG size of output 81 [2018-04-11 12:48:48,598 WARN L151 SmtUtils]: Spent 229ms on a formula simplification. DAG size of input: 216 DAG size of output 74 [2018-04-11 12:48:48,855 WARN L151 SmtUtils]: Spent 205ms on a formula simplification. DAG size of input: 216 DAG size of output 74 [2018-04-11 12:48:49,102 WARN L151 SmtUtils]: Spent 213ms on a formula simplification. DAG size of input: 218 DAG size of output 74 [2018-04-11 12:48:49,386 WARN L151 SmtUtils]: Spent 244ms on a formula simplification. DAG size of input: 234 DAG size of output 81 [2018-04-11 12:48:49,663 WARN L151 SmtUtils]: Spent 232ms on a formula simplification. DAG size of input: 236 DAG size of output 81 [2018-04-11 12:48:49,871 WARN L151 SmtUtils]: Spent 169ms on a formula simplification. DAG size of input: 161 DAG size of output 72 [2018-04-11 12:48:50,088 WARN L151 SmtUtils]: Spent 178ms on a formula simplification. DAG size of input: 163 DAG size of output 72 [2018-04-11 12:48:51,019 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:51,019 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:51,019 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-04-11 12:48:51,019 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:51,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:51,020 INFO L182 omatonBuilderFactory]: Interpolants [10624#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 10625#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))), 10626#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 10627#(or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))))), 10628#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 10629#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0)), 10630#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 10631#(or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 10632#(<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)), 10633#(and (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (<= 0 cstrcat_~s~0.offset)), 10634#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 10603#true, 10604#false, 10605#(<= 1 main_~length1~0), 10606#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 10607#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 10608#(and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 10609#(and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))) (= 0 main_~nondetString2~0.offset)), 10610#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 2) (+ main_~nondetString2~0.offset (- 1))))) (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (or (<= 12 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- 1)) (+ main_~nondetString2~0.offset (- 1)))))) (<= 11 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 1) (- 1))))) (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) (+ main_~nondetString2~0.offset (- 1))))) (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))))), 10611#(and (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 5 2) 1) (- 1)))) (<= 9 (select |#length| |cstrcat_#in~s1.base|))) (and (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 5 2) 2) (- 1)))) (<= 10 (select |#length| |cstrcat_#in~s1.base|))) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 1) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s1.base|))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1)))) (<= 12 (select |#length| |cstrcat_#in~s1.base|))) (<= 11 (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= 6 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 2) (- 1)))) (<= 8 (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s1.offset|)), 10612#(and (or (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 1) (- 1))))) (and (<= 11 (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= 12 (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 2) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 10 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 2) (- 1)))))) (= cstrcat_~s~0.offset 0)), 10613#(and (or (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 1) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= 11 (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= 12 (select |#length| cstrcat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 2) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 10 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 2) (- 1)))))) (= cstrcat_~s~0.offset 0)), 10614#(and (= cstrcat_~s~0.offset 1) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))))), 10615#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1)))))) (= cstrcat_~s~0.offset 1)), 10616#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 10617#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) (- 1)))))), 10618#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1)))))), 10619#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1)))))), 10620#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 10621#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))))), 10622#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))))), 10623#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))))] [2018-04-11 12:48:51,020 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:51,020 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-11 12:48:51,020 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-11 12:48:51,020 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=857, Unknown=0, NotChecked=0, Total=992 [2018-04-11 12:48:51,021 INFO L87 Difference]: Start difference. First operand 125 states and 134 transitions. Second operand 32 states. [2018-04-11 12:48:51,712 WARN L151 SmtUtils]: Spent 143ms on a formula simplification. DAG size of input: 145 DAG size of output 144 [2018-04-11 12:48:51,847 WARN L151 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 137 DAG size of output 131 [2018-04-11 12:48:52,012 WARN L151 SmtUtils]: Spent 136ms on a formula simplification. DAG size of input: 140 DAG size of output 137 [2018-04-11 12:48:52,298 WARN L151 SmtUtils]: Spent 133ms on a formula simplification. DAG size of input: 132 DAG size of output 129 [2018-04-11 12:48:52,553 WARN L151 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 126 DAG size of output 123 [2018-04-11 12:48:52,825 WARN L151 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 118 DAG size of output 115 [2018-04-11 12:48:53,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:53,932 INFO L93 Difference]: Finished difference Result 166 states and 177 transitions. [2018-04-11 12:48:53,932 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-04-11 12:48:53,932 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 53 [2018-04-11 12:48:53,932 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:53,933 INFO L225 Difference]: With dead ends: 166 [2018-04-11 12:48:53,933 INFO L226 Difference]: Without dead ends: 166 [2018-04-11 12:48:53,933 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 512 ImplicationChecksByTransitivity, 5.6s TimeCoverageRelationStatistics Valid=552, Invalid=2754, Unknown=0, NotChecked=0, Total=3306 [2018-04-11 12:48:53,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states. [2018-04-11 12:48:53,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 131. [2018-04-11 12:48:53,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-04-11 12:48:53,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 141 transitions. [2018-04-11 12:48:53,935 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 141 transitions. Word has length 53 [2018-04-11 12:48:53,935 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:53,935 INFO L459 AbstractCegarLoop]: Abstraction has 131 states and 141 transitions. [2018-04-11 12:48:53,935 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-11 12:48:53,935 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 141 transitions. [2018-04-11 12:48:53,935 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-04-11 12:48:53,935 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:53,935 INFO L355 BasicCegarLoop]: trace histogram [7, 7, 6, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:53,935 INFO L408 AbstractCegarLoop]: === Iteration 46 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:53,935 INFO L82 PathProgramCache]: Analyzing trace with hash 394354159, now seen corresponding path program 12 times [2018-04-11 12:48:53,936 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:53,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:53,943 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:54,736 WARN L151 SmtUtils]: Spent 202ms on a formula simplification. DAG size of input: 182 DAG size of output 89 [2018-04-11 12:48:54,931 WARN L151 SmtUtils]: Spent 172ms on a formula simplification. DAG size of input: 145 DAG size of output 68 [2018-04-11 12:48:55,128 WARN L151 SmtUtils]: Spent 176ms on a formula simplification. DAG size of input: 145 DAG size of output 68 [2018-04-11 12:48:55,328 WARN L151 SmtUtils]: Spent 177ms on a formula simplification. DAG size of input: 147 DAG size of output 68 [2018-04-11 12:48:55,549 WARN L151 SmtUtils]: Spent 189ms on a formula simplification. DAG size of input: 173 DAG size of output 79 [2018-04-11 12:48:55,777 WARN L151 SmtUtils]: Spent 193ms on a formula simplification. DAG size of input: 175 DAG size of output 81 [2018-04-11 12:48:56,387 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 0 proven. 76 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:56,387 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:56,387 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-04-11 12:48:56,388 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:56,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:56,388 INFO L182 omatonBuilderFactory]: Interpolants [11008#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 11009#(and (or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (<= 1 cstrcat_~s~0.offset)), 11010#(and (<= 2 cstrcat_~s~0.offset) (or (<= (+ |cstrcat_#t~post4.offset| 2) (select |#length| |cstrcat_#t~post4.base|)) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)) (<= (+ (select |#length| |cstrcat_#t~post4.base|) cstrcat_~s~0.offset) (+ |cstrcat_#t~post4.offset| (select |#length| cstrcat_~s~0.base) 1))), 11011#(or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 11012#(or (and (<= 2 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 11013#(and (<= 2 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))), 10984#true, 10985#false, 10986#(<= 1 main_~length3~0), 10987#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 10988#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 10989#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= (select |#length| main_~nondetString1~0.base) main_~length1~0) (= main_~nondetString1~0.offset 0)), 10990#(and (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|)) (= (select |#length| main_~nondetString1~0.base) main_~length1~0) (= main_~nondetString1~0.offset 0)), 10991#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (= 0 main_~nondetString1~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0)))), 10992#(and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (= 0 main_~nondetString1~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))) (<= 1 main_~length3~0))) (= 0 main_~nondetString2~0.offset)), 10993#(or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (or (<= 4 (+ main_~nondetString2~0.offset (div (+ (select |#length| main_~nondetString2~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset (- 1)))) 2))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (div (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString2~0.offset) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString1~0.offset 2)))) 2) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (div (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString2~0.offset) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString1~0.offset 4)))) 2) (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (+ (select |#length| main_~nondetString1~0.base) (- 1))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (div (+ (select |#length| main_~nondetString2~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset (- 1)))) 2) (+ main_~nondetString2~0.offset (- 1)))))) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= 4 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString1~0.base) (- main_~nondetString2~0.offset)) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) (+ (select |#length| main_~nondetString1~0.base) 2)) (+ main_~nondetString2~0.offset (- 1)))))))))), 10994#(or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (div (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) 2) (- 1)))) (<= 4 (div (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) 2)) (<= (+ (select |#length| |cstrcat_#in~s2.base|) (div (+ 3 (+ (select |#length| |cstrcat_#in~s2.base|) 2)) 2) 1) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (div (+ 3 (+ (select |#length| |cstrcat_#in~s2.base|) 2)) 2) (- 1)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (select |#length| |cstrcat_#in~s2.base|) (- 1))))) (or (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 3) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (select |#length| |cstrcat_#in~s2.base|))) (<= 4 (select |#length| |cstrcat_#in~s2.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s2.base|) 2) (- 1)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (select |#length| |cstrcat_#in~s2.base|) (- 1))))) (or (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1))))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s2.offset|) (= 0 |cstrcat_#in~s1.offset|))), 10995#(or (and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ 3 (+ (select |#length| cstrcat_~s2.base) 2)) 2) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) (div (+ 3 (+ (select |#length| cstrcat_~s2.base) 2)) 2) 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1)))) (<= 4 (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2))) (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) 2) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 10996#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ 3 (+ (select |#length| cstrcat_~s2.base) 2)) 2) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) (div (+ 3 (+ (select |#length| cstrcat_~s2.base) 2)) 2) 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1)))) (<= 4 (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2))) (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) 2) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0))), 10997#(and (= 0 cstrcat_~s2.offset) (= cstrcat_~s~0.offset 1) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1)))) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 2))) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 2))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (+ cstrcat_~s~0.offset 2) (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1))) 2)) 2) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) (div (+ (+ cstrcat_~s~0.offset 2) (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1))) 4)) 2)) (select |#length| cstrcat_~s~0.base))) (or (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) 1)) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 10998#(and (= 0 cstrcat_~s2.offset) (or (= |cstrcat_#t~mem2| 0) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1)))) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (or (and (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s2.base)) (or (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) 1)) (- 1))))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 2))) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 2))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (+ cstrcat_~s~0.offset 2) (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1))) 2)) 2) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) (div (+ (+ cstrcat_~s~0.offset 2) (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1))) 4)) 2)) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 1)), 10999#(or (and (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 4)) (- 1)))) (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset 1)) (<= (select |#length| cstrcat_~s2.base) 2)) (or (= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base)) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (or (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (select |#length| cstrcat_~s2.base)) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))) (= 0 cstrcat_~s2.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 11000#(or (and (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 4)) (- 1)))) (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset 1)) (<= (select |#length| cstrcat_~s2.base) 2)) (or (= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base)) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (or (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (select |#length| cstrcat_~s2.base)) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))) (= 0 cstrcat_~s2.offset)) (= |cstrcat_#t~mem2| 0)), 11001#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 2) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (not (= (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset))) (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))))), 11002#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 2) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (and (or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (or (= |cstrcat_#t~mem2| 0) (not (= (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset)))))), 11003#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 2) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 11004#(and (= 0 cstrcat_~s2.offset) (or (= |cstrcat_#t~mem2| 0) (<= (select |#length| cstrcat_~s2.base) 2) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 11005#(and (= 0 cstrcat_~s2.offset) (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (<= (select |#length| cstrcat_~s2.base) 2))), 11006#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 2) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 11007#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (= |cstrcat_#t~post5.offset| 0) (or (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) (+ cstrcat_~s2.offset 1))) (= |cstrcat_#t~post5.base| cstrcat_~s2.base))] [2018-04-11 12:48:56,388 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 0 proven. 76 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:56,388 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-04-11 12:48:56,388 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-04-11 12:48:56,389 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=76, Invalid=794, Unknown=0, NotChecked=0, Total=870 [2018-04-11 12:48:56,389 INFO L87 Difference]: Start difference. First operand 131 states and 141 transitions. Second operand 30 states. [2018-04-11 12:48:56,706 WARN L151 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 116 DAG size of output 113 [2018-04-11 12:48:57,330 WARN L151 SmtUtils]: Spent 155ms on a formula simplification. DAG size of input: 148 DAG size of output 133 [2018-04-11 12:48:57,538 WARN L151 SmtUtils]: Spent 179ms on a formula simplification. DAG size of input: 155 DAG size of output 137 [2018-04-11 12:48:58,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:48:58,184 INFO L93 Difference]: Finished difference Result 169 states and 179 transitions. [2018-04-11 12:48:58,184 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-04-11 12:48:58,184 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 53 [2018-04-11 12:48:58,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:48:58,185 INFO L225 Difference]: With dead ends: 169 [2018-04-11 12:48:58,185 INFO L226 Difference]: Without dead ends: 169 [2018-04-11 12:48:58,186 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 460 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=240, Invalid=2016, Unknown=0, NotChecked=0, Total=2256 [2018-04-11 12:48:58,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states. [2018-04-11 12:48:58,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 131. [2018-04-11 12:48:58,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-04-11 12:48:58,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 141 transitions. [2018-04-11 12:48:58,188 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 141 transitions. Word has length 53 [2018-04-11 12:48:58,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:48:58,189 INFO L459 AbstractCegarLoop]: Abstraction has 131 states and 141 transitions. [2018-04-11 12:48:58,189 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-04-11 12:48:58,189 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 141 transitions. [2018-04-11 12:48:58,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-04-11 12:48:58,189 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:48:58,189 INFO L355 BasicCegarLoop]: trace histogram [9, 9, 8, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:48:58,190 INFO L408 AbstractCegarLoop]: === Iteration 47 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:48:58,190 INFO L82 PathProgramCache]: Analyzing trace with hash 468201833, now seen corresponding path program 13 times [2018-04-11 12:48:58,190 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:48:58,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:48:58,210 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:48:58,608 WARN L151 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 108 DAG size of output 73 [2018-04-11 12:48:58,832 WARN L151 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 86 DAG size of output 61 [2018-04-11 12:48:58,949 WARN L151 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 88 DAG size of output 61 [2018-04-11 12:48:59,111 WARN L151 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 101 DAG size of output 65 [2018-04-11 12:48:59,943 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:59,943 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:48:59,943 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30] total 30 [2018-04-11 12:48:59,944 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:48:59,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:59,944 INFO L182 omatonBuilderFactory]: Interpolants [11350#true, 11351#false, 11352#(<= 1 main_~length3~0), 11353#(and (or (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (< 9 main_~length2~0)) (<= 1 main_~length3~0)), 11354#(and (or (and (= 0 |main_#t~malloc10.offset|) (<= (+ (select |#length| |main_#t~malloc10.base|) main_~length3~0) main_~length2~0)) (< 9 main_~length2~0)) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc10.base|) 1)), 11355#(and (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (or (and (= 0 main_~nondetString1~0.offset) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) main_~length2~0)) (< 9 main_~length2~0))), 11356#(and (or (and (= 0 main_~nondetString1~0.offset) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) 9)) (<= 10 (select |#length| |main_#t~malloc11.base|))) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|)), 11357#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (or (and (= 0 main_~nondetString1~0.offset) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) 9)) (<= 10 (select |#length| main_~nondetString2~0.base)))))), 11358#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) 9) (+ main_~nondetString2~0.offset (- 1))))) (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 4))) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 2)) (or (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 1)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) 8) (+ main_~nondetString2~0.offset (- 1))))))) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 6)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 5) (- 1))))) (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 3))) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 5)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (<= 10 (select |#length| main_~nondetString2~0.base)))), 11359#(and (or (<= 10 (select |#length| |cstrcat_#in~s1.base|)) (and (or (and (<= (select |#length| |cstrcat_#in~s2.base|) 5) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1)))) (<= (select |#length| |cstrcat_#in~s2.base|) 3)) (and (<= (select |#length| |cstrcat_#in~s2.base|) 6) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) 9) (- 1)))) (<= (select |#length| |cstrcat_#in~s2.base|) 4)) (and (<= (select |#length| |cstrcat_#in~s2.base|) 2) (or (<= (select |#length| |cstrcat_#in~s2.base|) 1) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) 8) (- 1))))))) (= 0 |cstrcat_#in~s2.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 11360#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (<= 10 (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) 9) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 4)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) 8) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2))))) (= cstrcat_~s~0.offset 0)), 11361#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (<= 10 (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) 9) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 4)) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) 8) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2))))) (= cstrcat_~s~0.offset 0)), 11362#(and (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 7)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 8)) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 1)), 11363#(and (or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 7)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 8)) (- 1)))))))) (= cstrcat_~s~0.offset 1)), 11364#(or (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 7)) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 6)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base))), 11365#(or (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 7)) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 6)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base))), 11366#(or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (and (or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 6)) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 5)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2))) (= 0 cstrcat_~s2.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 11367#(or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem2| 0) (and (or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 6)) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 5)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2))) (= 0 cstrcat_~s2.offset))), 11368#(or (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))), 11369#(or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2))))), 11370#(or (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 11371#(or (= |cstrcat_#t~mem2| 0) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 11372#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))))), 11373#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 1) (= |cstrcat_#t~mem2| 0)))), 11374#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 11375#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 11376#(and (or (and (= |cstrcat_#t~post5.offset| 0) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) cstrcat_~s2.offset)) (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)), 11377#(or (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 11378#(or (and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 11379#(or (and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 11380#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:48:59,944 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:48:59,944 INFO L442 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-04-11 12:48:59,945 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-04-11 12:48:59,945 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=863, Unknown=0, NotChecked=0, Total=930 [2018-04-11 12:48:59,945 INFO L87 Difference]: Start difference. First operand 131 states and 141 transitions. Second operand 31 states. [2018-04-11 12:49:00,549 WARN L151 SmtUtils]: Spent 113ms on a formula simplification. DAG size of input: 110 DAG size of output 109 [2018-04-11 12:49:00,772 WARN L151 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 122 DAG size of output 120 [2018-04-11 12:49:00,989 WARN L151 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 111 DAG size of output 110 [2018-04-11 12:49:02,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:49:02,008 INFO L93 Difference]: Finished difference Result 160 states and 170 transitions. [2018-04-11 12:49:02,008 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-04-11 12:49:02,009 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 54 [2018-04-11 12:49:02,009 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:49:02,009 INFO L225 Difference]: With dead ends: 160 [2018-04-11 12:49:02,009 INFO L226 Difference]: Without dead ends: 160 [2018-04-11 12:49:02,010 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 472 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=203, Invalid=2659, Unknown=0, NotChecked=0, Total=2862 [2018-04-11 12:49:02,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-04-11 12:49:02,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 131. [2018-04-11 12:49:02,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-04-11 12:49:02,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 141 transitions. [2018-04-11 12:49:02,011 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 141 transitions. Word has length 54 [2018-04-11 12:49:02,012 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:49:02,012 INFO L459 AbstractCegarLoop]: Abstraction has 131 states and 141 transitions. [2018-04-11 12:49:02,012 INFO L460 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-04-11 12:49:02,012 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 141 transitions. [2018-04-11 12:49:02,012 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-04-11 12:49:02,012 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:49:02,012 INFO L355 BasicCegarLoop]: trace histogram [6, 6, 5, 4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:49:02,012 INFO L408 AbstractCegarLoop]: === Iteration 48 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:49:02,012 INFO L82 PathProgramCache]: Analyzing trace with hash -1988119517, now seen corresponding path program 14 times [2018-04-11 12:49:02,013 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:49:02,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:49:02,027 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:49:02,664 WARN L151 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 71 DAG size of output 57 [2018-04-11 12:49:03,213 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:03,213 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:49:03,213 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27] total 27 [2018-04-11 12:49:03,214 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:49:03,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:03,214 INFO L182 omatonBuilderFactory]: Interpolants [11718#true, 11719#false, 11720#(<= 1 main_~length3~0), 11721#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 11722#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 11723#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 11724#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|)) (= main_~nondetString1~0.offset 0)), 11725#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))) (= main_~nondetString1~0.offset 0)), 11726#(and (= 0 main_~nondetString2~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 11727#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (- 3)))) (select |#length| main_~nondetString2~0.base)) (- 1)))))) (or (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 1) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1)))) (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (= main_~nondetString1~0.offset 0)), 11728#(and (or (and (or (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (+ (select |#length| |cstrcat_#in~s1.base|) (- 3))) (select |#length| |cstrcat_#in~s1.base|)) (- 1))))) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s2.base|) (- 1)) (- 1)))) (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 1) (select |#length| |cstrcat_#in~s1.base|)) (<= 5 (select |#length| |cstrcat_#in~s2.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (select |#length| |cstrcat_#in~s2.base|) (- 1))))) (= 0 |cstrcat_#in~s2.offset|) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 11729#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 cstrcat_~s2.offset) (or (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s~0.base) (- 3))) (select |#length| cstrcat_~s~0.base)) (- 1))))) (or (<= 5 (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (- 1)) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 0)), 11730#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (+ (select |#length| cstrcat_~s~0.base) (- 3)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (= 0 cstrcat_~s2.offset) (or (<= 5 (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (- 1)) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 11731#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s~0.base) (- 3))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (<= 5 (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) (- 1)) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base)))) (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 11732#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s~0.base) (- 3))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (<= 5 (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) (- 1)) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base)))) (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset))), 11733#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (<= 5 (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 2))) (- 1))))))), 11734#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (<= 5 (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 2))) (- 1))))))), 11735#(or (and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))), 11736#(or (and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 3) (= |cstrcat_#t~mem2| 0))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))), 11737#(or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 11738#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset))), 11739#(or (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (and (<= (+ |cstrcat_#t~post5.offset| 1) cstrcat_~s2.offset) (= |cstrcat_#t~post5.offset| 0) (<= (select |#length| |cstrcat_#t~post5.base|) 3) (= |cstrcat_#t~post5.base| cstrcat_~s2.base))), 11740#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 2)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 11741#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 11742#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (<= (+ |cstrcat_#t~post4.offset| 2) (select |#length| |cstrcat_#t~post4.base|)) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)) (<= (+ (select |#length| |cstrcat_#t~post4.base|) cstrcat_~s~0.offset) (+ |cstrcat_#t~post4.offset| (select |#length| cstrcat_~s~0.base) 1))), 11743#(or (and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 11744#(or (and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 11745#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:49:03,214 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:03,214 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-04-11 12:49:03,215 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-04-11 12:49:03,215 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=689, Unknown=0, NotChecked=0, Total=756 [2018-04-11 12:49:03,215 INFO L87 Difference]: Start difference. First operand 131 states and 141 transitions. Second operand 28 states. [2018-04-11 12:49:04,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:49:04,362 INFO L93 Difference]: Finished difference Result 173 states and 183 transitions. [2018-04-11 12:49:04,362 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-04-11 12:49:04,362 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 55 [2018-04-11 12:49:04,362 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:49:04,362 INFO L225 Difference]: With dead ends: 173 [2018-04-11 12:49:04,362 INFO L226 Difference]: Without dead ends: 173 [2018-04-11 12:49:04,363 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 377 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=197, Invalid=1695, Unknown=0, NotChecked=0, Total=1892 [2018-04-11 12:49:04,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states. [2018-04-11 12:49:04,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 131. [2018-04-11 12:49:04,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-04-11 12:49:04,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 141 transitions. [2018-04-11 12:49:04,364 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 141 transitions. Word has length 55 [2018-04-11 12:49:04,364 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:49:04,364 INFO L459 AbstractCegarLoop]: Abstraction has 131 states and 141 transitions. [2018-04-11 12:49:04,364 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-04-11 12:49:04,365 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 141 transitions. [2018-04-11 12:49:04,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-04-11 12:49:04,365 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:49:04,365 INFO L355 BasicCegarLoop]: trace histogram [13, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:49:04,365 INFO L408 AbstractCegarLoop]: === Iteration 49 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:49:04,365 INFO L82 PathProgramCache]: Analyzing trace with hash -1098469834, now seen corresponding path program 11 times [2018-04-11 12:49:04,365 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:49:04,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:49:04,378 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:49:05,771 WARN L151 SmtUtils]: Spent 427ms on a formula simplification. DAG size of input: 379 DAG size of output 93 [2018-04-11 12:49:06,191 WARN L151 SmtUtils]: Spent 381ms on a formula simplification. DAG size of input: 301 DAG size of output 81 [2018-04-11 12:49:06,645 WARN L151 SmtUtils]: Spent 411ms on a formula simplification. DAG size of input: 301 DAG size of output 81 [2018-04-11 12:49:07,091 WARN L151 SmtUtils]: Spent 400ms on a formula simplification. DAG size of input: 303 DAG size of output 81 [2018-04-11 12:49:07,507 WARN L151 SmtUtils]: Spent 361ms on a formula simplification. DAG size of input: 320 DAG size of output 91 [2018-04-11 12:49:07,944 WARN L151 SmtUtils]: Spent 373ms on a formula simplification. DAG size of input: 322 DAG size of output 91 [2018-04-11 12:49:08,317 WARN L151 SmtUtils]: Spent 313ms on a formula simplification. DAG size of input: 224 DAG size of output 79 [2018-04-11 12:49:08,659 WARN L151 SmtUtils]: Spent 290ms on a formula simplification. DAG size of input: 226 DAG size of output 79 [2018-04-11 12:49:08,881 WARN L151 SmtUtils]: Spent 177ms on a formula simplification. DAG size of input: 158 DAG size of output 72 [2018-04-11 12:49:09,109 WARN L151 SmtUtils]: Spent 182ms on a formula simplification. DAG size of input: 160 DAG size of output 72 [2018-04-11 12:49:09,282 WARN L151 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 120 DAG size of output 65 [2018-04-11 12:49:09,447 WARN L151 SmtUtils]: Spent 120ms on a formula simplification. DAG size of input: 122 DAG size of output 65 [2018-04-11 12:49:10,244 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:10,244 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:49:10,244 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2018-04-11 12:49:10,244 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:49:10,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:10,245 INFO L182 omatonBuilderFactory]: Interpolants [12096#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)))), 12097#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))))), 12098#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))))), 12099#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))))), 12100#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1)))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))))), 12101#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 12102#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 12103#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))))), 12104#(or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))))), 12105#(or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))), 12106#(or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))), 12107#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))), 12108#(and (or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))) (<= 0 cstrcat_~s~0.offset)), 12109#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 12110#(or (= |cstrcat_#t~mem2| 0) (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 12111#(and (<= 2 cstrcat_~s~0.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 12112#(and (<= 2 cstrcat_~s~0.offset) (or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 12113#(and (<= 3 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 12114#(and (<= 4 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 12082#true, 12083#false, 12084#(<= 1 main_~length1~0), 12085#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 12086#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 12087#(and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 12088#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1))), 12089#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 1) (+ main_~nondetString2~0.offset (- 1))))) (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 11 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 2) (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) (- 1))))) (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- 1)) (+ main_~nondetString2~0.offset (- 1))))) (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 5) (- 1))))) (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 12 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= 13 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- 2)) (+ main_~nondetString2~0.offset (- 1))))))))), 12090#(and (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 5 2) 1) (- 1)))) (<= 9 (select |#length| |cstrcat_#in~s1.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1)))) (<= 8 (select |#length| |cstrcat_#in~s1.base|))) (and (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 1) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s1.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 2) (- 1)))) (<= 9 (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= 12 (select |#length| |cstrcat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 2)) (- 1)))) (<= 13 (select |#length| |cstrcat_#in~s1.base|)))) (and (<= 6 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 5 2) 2) (- 1)))) (<= 11 (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s1.offset|)), 12091#(and (or (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 1) (- 1))))) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 2) (- 1))))) (and (<= 11 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 2) (- 1))))) (and (or (<= 13 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= 12 (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 12092#(and (or (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 1) (- 1))))) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 2) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= 11 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 2) (- 1))))) (and (or (<= 13 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= 12 (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 12093#(and (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 12) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1)))))) (= cstrcat_~s~0.offset 1)), 12094#(and (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 12) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1)))))) (= cstrcat_~s~0.offset 1)), 12095#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))))] [2018-04-11 12:49:10,245 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:10,245 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-04-11 12:49:10,245 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-04-11 12:49:10,245 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=116, Invalid=940, Unknown=0, NotChecked=0, Total=1056 [2018-04-11 12:49:10,245 INFO L87 Difference]: Start difference. First operand 131 states and 141 transitions. Second operand 33 states. [2018-04-11 12:49:11,192 WARN L151 SmtUtils]: Spent 141ms on a formula simplification. DAG size of input: 150 DAG size of output 139 [2018-04-11 12:49:11,446 WARN L151 SmtUtils]: Spent 225ms on a formula simplification. DAG size of input: 159 DAG size of output 148 [2018-04-11 12:49:11,613 WARN L151 SmtUtils]: Spent 120ms on a formula simplification. DAG size of input: 146 DAG size of output 137 [2018-04-11 12:49:11,817 WARN L151 SmtUtils]: Spent 171ms on a formula simplification. DAG size of input: 155 DAG size of output 143 [2018-04-11 12:49:11,964 WARN L151 SmtUtils]: Spent 107ms on a formula simplification. DAG size of input: 142 DAG size of output 130 [2018-04-11 12:49:12,146 WARN L151 SmtUtils]: Spent 147ms on a formula simplification. DAG size of input: 151 DAG size of output 136 [2018-04-11 12:49:12,309 WARN L151 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 134 DAG size of output 120 [2018-04-11 12:49:12,499 WARN L151 SmtUtils]: Spent 146ms on a formula simplification. DAG size of input: 143 DAG size of output 128 [2018-04-11 12:49:12,723 WARN L151 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 128 DAG size of output 116 [2018-04-11 12:49:12,933 WARN L151 SmtUtils]: Spent 139ms on a formula simplification. DAG size of input: 137 DAG size of output 122 [2018-04-11 12:49:13,230 WARN L151 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 135 DAG size of output 116 [2018-04-11 12:49:13,372 WARN L151 SmtUtils]: Spent 100ms on a formula simplification. DAG size of input: 114 DAG size of output 106 [2018-04-11 12:49:13,519 WARN L151 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 120 DAG size of output 108 [2018-04-11 12:49:14,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:49:14,129 INFO L93 Difference]: Finished difference Result 174 states and 186 transitions. [2018-04-11 12:49:14,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-04-11 12:49:14,129 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 56 [2018-04-11 12:49:14,129 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:49:14,130 INFO L225 Difference]: With dead ends: 174 [2018-04-11 12:49:14,130 INFO L226 Difference]: Without dead ends: 174 [2018-04-11 12:49:14,130 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 577 ImplicationChecksByTransitivity, 8.4s TimeCoverageRelationStatistics Valid=521, Invalid=3139, Unknown=0, NotChecked=0, Total=3660 [2018-04-11 12:49:14,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-04-11 12:49:14,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 137. [2018-04-11 12:49:14,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-04-11 12:49:14,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 148 transitions. [2018-04-11 12:49:14,132 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 148 transitions. Word has length 56 [2018-04-11 12:49:14,132 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:49:14,132 INFO L459 AbstractCegarLoop]: Abstraction has 137 states and 148 transitions. [2018-04-11 12:49:14,132 INFO L460 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-04-11 12:49:14,132 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 148 transitions. [2018-04-11 12:49:14,132 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-04-11 12:49:14,133 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:49:14,133 INFO L355 BasicCegarLoop]: trace histogram [8, 8, 7, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:49:14,133 INFO L408 AbstractCegarLoop]: === Iteration 50 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:49:14,133 INFO L82 PathProgramCache]: Analyzing trace with hash 860052149, now seen corresponding path program 15 times [2018-04-11 12:49:14,133 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:49:14,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:49:14,143 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:49:14,617 WARN L151 SmtUtils]: Spent 169ms on a formula simplification. DAG size of input: 97 DAG size of output 62 [2018-04-11 12:49:15,581 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 97 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:15,581 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:49:15,581 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-04-11 12:49:15,581 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:49:15,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:15,582 INFO L182 omatonBuilderFactory]: Interpolants [12482#true, 12483#false, 12484#(<= 1 main_~length3~0), 12485#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 12486#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 12487#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 12488#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|)) (= main_~nondetString1~0.offset 0)), 12489#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 12490#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 12491#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (or (<= (+ (select |#length| main_~nondetString1~0.base) 7) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (select |#length| main_~nondetString2~0.base) (+ (- (select |#length| main_~nondetString1~0.base)) (- 1))) (- 1)) (+ main_~nondetString2~0.offset (- 1)))))) (<= (+ (select |#length| main_~nondetString1~0.base) 6) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (- 1)))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ (- (select |#length| main_~nondetString1~0.base)) (- 1))) (+ main_~nondetString2~0.offset (- 1))))))) (= main_~nondetString1~0.offset 0)), 12492#(and (or (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) (+ (select |#length| |cstrcat_#in~s1.base|) (- 1))) (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 6) (select |#length| |cstrcat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) (+ (select |#length| |cstrcat_#in~s1.base|) (- 1))) (- 1)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 7) (select |#length| |cstrcat_#in~s1.base|)))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 5) (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) (select |#length| |cstrcat_#in~s1.base|)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s2.offset|) (= 0 |cstrcat_#in~s1.offset|)), 12493#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (- 1))) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 7) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 6) (select |#length| cstrcat_~s~0.base)))) (= 0 cstrcat_~s2.offset) (= cstrcat_~s~0.offset 0)), 12494#(and (= 0 cstrcat_~s2.offset) (= cstrcat_~s~0.offset 0) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (- 1))) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 7) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 6) (select |#length| cstrcat_~s~0.base))))), 12495#(and (= 0 cstrcat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ (select |#length| cstrcat_~s~0.base) (- 1))) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ (select |#length| cstrcat_~s~0.base) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))))), 12496#(and (= 0 cstrcat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ (select |#length| cstrcat_~s~0.base) (- 1))) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ (select |#length| cstrcat_~s~0.base) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))))), 12497#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 3)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 12498#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 3)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 12499#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 3)) (- 1)))) (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base))))), 12500#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 3)) (- 1)))) (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base))))), 12501#(or (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 3)) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 12502#(or (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 3)) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (= |cstrcat_#t~mem2| 0)), 12503#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 12504#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 12505#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))), 12506#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 12507#(or (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (and (= |cstrcat_#t~post5.offset| 0) (= |cstrcat_#t~post5.base| cstrcat_~s2.base) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) (+ cstrcat_~s2.offset 1)))), 12508#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 12509#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 12510#(or (and (<= 2 cstrcat_~s~0.offset) (<= (+ (select |#length| |cstrcat_#t~post4.base|) cstrcat_~s~0.offset) (+ |cstrcat_#t~post4.offset| (select |#length| cstrcat_~s~0.base) 1)) (<= (+ |cstrcat_#t~post4.offset| 2) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 12511#(or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 12512#(or (and (<= 2 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 12513#(and (<= 2 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:49:15,582 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 0 proven. 97 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:15,582 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-11 12:49:15,582 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-11 12:49:15,582 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=898, Unknown=0, NotChecked=0, Total=992 [2018-04-11 12:49:15,582 INFO L87 Difference]: Start difference. First operand 137 states and 148 transitions. Second operand 32 states. [2018-04-11 12:49:17,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:49:17,066 INFO L93 Difference]: Finished difference Result 177 states and 188 transitions. [2018-04-11 12:49:17,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-04-11 12:49:17,066 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 56 [2018-04-11 12:49:17,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:49:17,066 INFO L225 Difference]: With dead ends: 177 [2018-04-11 12:49:17,066 INFO L226 Difference]: Without dead ends: 177 [2018-04-11 12:49:17,067 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 577 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=292, Invalid=2360, Unknown=0, NotChecked=0, Total=2652 [2018-04-11 12:49:17,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-04-11 12:49:17,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 137. [2018-04-11 12:49:17,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-04-11 12:49:17,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 148 transitions. [2018-04-11 12:49:17,069 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 148 transitions. Word has length 56 [2018-04-11 12:49:17,069 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:49:17,069 INFO L459 AbstractCegarLoop]: Abstraction has 137 states and 148 transitions. [2018-04-11 12:49:17,069 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-11 12:49:17,069 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 148 transitions. [2018-04-11 12:49:17,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-04-11 12:49:17,070 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:49:17,070 INFO L355 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:49:17,070 INFO L408 AbstractCegarLoop]: === Iteration 51 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:49:17,070 INFO L82 PathProgramCache]: Analyzing trace with hash -1246832657, now seen corresponding path program 16 times [2018-04-11 12:49:17,071 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:49:17,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:49:17,084 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:49:17,670 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 24 proven. 52 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:17,670 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:49:17,670 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-04-11 12:49:17,671 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:49:17,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:17,671 INFO L182 omatonBuilderFactory]: Interpolants [12868#true, 12869#false, 12870#(<= 1 main_~length3~0), 12871#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 12872#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 12873#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 12874#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|))), 12875#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)))) (= (+ main_~nondetString2~0.offset main_~length3~0) 2))), 12876#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))))))), 12877#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString2~0.offset (- 1))))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 12878#(and (or (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) (select |#length| |cstrcat_#in~s1.base|)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s2.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 12879#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= 0 cstrcat_~s2.offset))) (= cstrcat_~s~0.offset 0)), 12880#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 cstrcat_~s2.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0)))) (= cstrcat_~s~0.offset 0)), 12881#(and (= cstrcat_~s~0.offset 1) (or (and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 12882#(and (or (and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0)) (= cstrcat_~s~0.offset 1)), 12883#(and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 12884#(and (= 0 cstrcat_~s2.offset) (or (= |cstrcat_#t~mem2| 0) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 12885#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 12886#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))), 12887#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (= |cstrcat_#t~post5.offset| 0) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)), 12888#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 12889#(and (<= 1 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 12890#(and (<= 2 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 12891#(and (<= 3 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 12892#(and (<= 4 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 12893#(and (<= 4 |cstrcat_#t~post4.offset|) (<= (+ (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post4.offset|) (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post4.base|)))), 12894#(and (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)) (<= 4 |cstrcat_#t~post4.offset|))] [2018-04-11 12:49:17,671 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 24 proven. 52 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:17,671 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-04-11 12:49:17,671 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-04-11 12:49:17,672 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=634, Unknown=0, NotChecked=0, Total=702 [2018-04-11 12:49:17,672 INFO L87 Difference]: Start difference. First operand 137 states and 148 transitions. Second operand 27 states. [2018-04-11 12:49:18,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:49:18,556 INFO L93 Difference]: Finished difference Result 173 states and 184 transitions. [2018-04-11 12:49:18,557 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-04-11 12:49:18,557 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 57 [2018-04-11 12:49:18,557 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:49:18,557 INFO L225 Difference]: With dead ends: 173 [2018-04-11 12:49:18,557 INFO L226 Difference]: Without dead ends: 149 [2018-04-11 12:49:18,558 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 381 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=217, Invalid=1675, Unknown=0, NotChecked=0, Total=1892 [2018-04-11 12:49:18,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-04-11 12:49:18,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 137. [2018-04-11 12:49:18,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-04-11 12:49:18,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 147 transitions. [2018-04-11 12:49:18,560 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 147 transitions. Word has length 57 [2018-04-11 12:49:18,560 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:49:18,560 INFO L459 AbstractCegarLoop]: Abstraction has 137 states and 147 transitions. [2018-04-11 12:49:18,560 INFO L460 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-04-11 12:49:18,561 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 147 transitions. [2018-04-11 12:49:18,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-04-11 12:49:18,561 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:49:18,561 INFO L355 BasicCegarLoop]: trace histogram [10, 10, 9, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:49:18,561 INFO L408 AbstractCegarLoop]: === Iteration 52 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:49:18,561 INFO L82 PathProgramCache]: Analyzing trace with hash 2019937635, now seen corresponding path program 17 times [2018-04-11 12:49:18,562 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:49:18,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:49:18,575 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:49:19,868 INFO L134 CoverageAnalysis]: Checked inductivity of 139 backedges. 0 proven. 139 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:19,868 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:49:19,868 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33] total 33 [2018-04-11 12:49:19,869 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:49:19,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:19,869 INFO L182 omatonBuilderFactory]: Interpolants [13248#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) 1) (- 1))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ main_~nondetString1~0.offset 8) (+ main_~nondetString2~0.offset (- 1))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) (+ main_~nondetString2~0.offset (- 1))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) 1) 1) (+ main_~nondetString2~0.offset (- 1))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (<= (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)) 1) (<= 11 (select |#length| main_~nondetString2~0.base)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) 1) 1) 1) (+ main_~nondetString2~0.offset (- 1)))))) (= main_~nondetString1~0.offset 0)), 13249#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ (+ (+ 3 1) 1) 1) 1) (- 1)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 3 1) (- 1)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= (select |#length| |cstrcat_#in~s2.base|) 1) (= 0 |cstrcat_#in~s2.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ (+ 3 1) 1) 1) (- 1)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 3 1) 1) (- 1)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 8 (- 1)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (<= 11 (select |#length| |cstrcat_#in~s1.base|))) (= 0 |cstrcat_#in~s1.offset|)), 13250#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 3 1) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ 3 1) 1) 1) (- 1)))) (<= 11 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 3 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ 3 1) 1) 1) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 8 (- 1))))) (= cstrcat_~s~0.offset 0)), 13251#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 3 1) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ 3 1) 1) 1) (- 1)))) (= |cstrcat_#t~mem2| 0) (<= 11 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 3 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ 3 1) 1) 1) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 8 (- 1))))) (= cstrcat_~s~0.offset 0)), 13252#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 7) (- 1)))) (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) 1) (- 1)))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) 1) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))), 13253#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 7) (- 1)))) (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) 1) (- 1)))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) 1) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))), 13254#(or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 6) (- 1)))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))), 13255#(or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 6) (- 1)))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))), 13256#(or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 5) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))), 13257#(or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 5) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))), 13258#(or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))), 13259#(or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))), 13260#(or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))), 13261#(or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))), 13262#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))), 13263#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))), 13264#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 13265#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 13266#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 13267#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 13268#(or (and (= |cstrcat_#t~post5.offset| 0) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) cstrcat_~s2.offset) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)) (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 13269#(or (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 13270#(or (and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 13271#(or (and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 13272#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))), 13239#true, 13240#false, 13241#(or (<= 1 main_~length3~0) (< 10 main_~length2~0)), 13242#(or (< 10 main_~length2~0) (and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0))), 13243#(and (or (and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)) (< 10 main_~length2~0)) (= 0 |main_#t~malloc10.offset|)), 13244#(and (or (< 10 main_~length2~0) (and (or (< 1 (+ main_~nondetString1~0.offset main_~length1~0)) (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1))) (or (<= (+ main_~nondetString1~0.offset main_~length1~0) 1) (and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0))))) (= main_~nondetString1~0.offset 0)), 13245#(and (= 0 |main_#t~malloc11.offset|) (or (<= 11 (select |#length| |main_#t~malloc11.base|)) (and (or (< 1 (+ main_~nondetString1~0.offset main_~length1~0)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))) (or (<= (+ main_~nondetString1~0.offset main_~length1~0) 1) (and (<= (+ main_~length3~0 main_~length1~0) 10) (<= 1 main_~length3~0))))) (= main_~nondetString1~0.offset 0)), 13246#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (or (< 1 (+ main_~nondetString1~0.offset main_~length1~0)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))) (or (<= (+ main_~nondetString1~0.offset main_~length1~0) 1) (and (<= (+ main_~length3~0 main_~length1~0) 10) (<= 1 main_~length3~0)))) (<= 11 (select |#length| main_~nondetString2~0.base))) (= main_~nondetString1~0.offset 0)), 13247#(and (= 0 main_~nondetString2~0.offset) (or (and (<= 1 main_~length3~0) (<= main_~length3~0 (+ main_~nondetString1~0.offset 8))) (<= (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)) 1) (<= 11 (select |#length| main_~nondetString2~0.base))) (= main_~nondetString1~0.offset 0))] [2018-04-11 12:49:19,869 INFO L134 CoverageAnalysis]: Checked inductivity of 139 backedges. 0 proven. 139 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:19,869 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-04-11 12:49:19,869 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-04-11 12:49:19,870 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=1050, Unknown=0, NotChecked=0, Total=1122 [2018-04-11 12:49:19,870 INFO L87 Difference]: Start difference. First operand 137 states and 147 transitions. Second operand 34 states. [2018-04-11 12:49:20,720 WARN L151 SmtUtils]: Spent 100ms on a formula simplification. DAG size of input: 96 DAG size of output 95 [2018-04-11 12:49:21,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:49:21,905 INFO L93 Difference]: Finished difference Result 166 states and 176 transitions. [2018-04-11 12:49:21,905 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-04-11 12:49:21,905 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 57 [2018-04-11 12:49:21,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:49:21,906 INFO L225 Difference]: With dead ends: 166 [2018-04-11 12:49:21,906 INFO L226 Difference]: Without dead ends: 166 [2018-04-11 12:49:21,906 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 417 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=210, Invalid=3096, Unknown=0, NotChecked=0, Total=3306 [2018-04-11 12:49:21,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states. [2018-04-11 12:49:21,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 137. [2018-04-11 12:49:21,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-04-11 12:49:21,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 147 transitions. [2018-04-11 12:49:21,908 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 147 transitions. Word has length 57 [2018-04-11 12:49:21,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:49:21,908 INFO L459 AbstractCegarLoop]: Abstraction has 137 states and 147 transitions. [2018-04-11 12:49:21,908 INFO L460 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-04-11 12:49:21,908 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 147 transitions. [2018-04-11 12:49:21,908 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-04-11 12:49:21,908 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:49:21,908 INFO L355 BasicCegarLoop]: trace histogram [7, 7, 6, 4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:49:21,908 INFO L408 AbstractCegarLoop]: === Iteration 53 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:49:21,909 INFO L82 PathProgramCache]: Analyzing trace with hash -1128949911, now seen corresponding path program 18 times [2018-04-11 12:49:21,909 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:49:21,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:49:21,918 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:49:22,631 WARN L151 SmtUtils]: Spent 149ms on a formula simplification. DAG size of input: 189 DAG size of output 63 [2018-04-11 12:49:23,248 WARN L151 SmtUtils]: Spent 214ms on a formula simplification. DAG size of input: 180 DAG size of output 72 [2018-04-11 12:49:23,483 WARN L151 SmtUtils]: Spent 202ms on a formula simplification. DAG size of input: 182 DAG size of output 72 [2018-04-11 12:49:24,052 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:24,052 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:49:24,052 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-04-11 12:49:24,053 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:49:24,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:24,053 INFO L182 omatonBuilderFactory]: Interpolants [13632#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 13633#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (or (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (+ (select |#length| main_~nondetString1~0.base) 1))) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (+ (- (+ (select |#length| main_~nondetString1~0.base) 1)) (- 1))) (- 1))))))) (= main_~nondetString1~0.offset 0)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 13634#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (+ (select |#length| |cstrcat_#in~s1.base|) (- 3)))) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (+ (+ (+ (select |#length| |cstrcat_#in~s1.base|) (+ (- 3) (- 1))) (- 1)) 1))) (- 1)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (select |#length| |cstrcat_#in~s2.base|))) (<= 10 (select |#length| |cstrcat_#in~s1.base|)) (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 2) (select |#length| |cstrcat_#in~s1.base|))) (or (<= (+ (select |#length| |cstrcat_#in~s2.base|) 5) (select |#length| |cstrcat_#in~s1.base|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|)))))) (= 0 |cstrcat_#in~s2.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 13635#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (or (<= 10 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (+ (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- 3) (- 1))) (- 1)) 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (+ (select |#length| cstrcat_~s~0.base) (- 3)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= 0 cstrcat_~s2.offset))) (= cstrcat_~s~0.offset 0)), 13636#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (or (<= 10 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (+ (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- 3) (- 1))) (- 1)) 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (+ (select |#length| cstrcat_~s~0.base) (- 3)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= 0 cstrcat_~s2.offset))) (= cstrcat_~s~0.offset 0)), 13637#(or (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (and (= 0 cstrcat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (- 1)))) (= 1 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) 1)) (- 2)))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) 1)) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (= 1 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (+ (select |#length| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))))))), 13638#(or (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset)) (and (= 0 cstrcat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (- 1)))) (= 1 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) 1)) (- 2)))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) 1)) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (= 1 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (+ (select |#length| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))))))), 13639#(or (and (= 0 cstrcat_~s2.offset) (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 2))) 1)) (- 2)))) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (= 2 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 4) (+ (select |#length| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset 3)) (- 2)))) (- 1)))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 2))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 2))) (- 1))))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 2)))) (- 2)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 13640#(or (and (= 0 cstrcat_~s2.offset) (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 2))) 1)) (- 2)))) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (= 2 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 4) (+ (select |#length| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset 3)) (- 2)))) (- 1)))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 2))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 2))) (- 1))))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 2)))) (- 2)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))))) (= |cstrcat_#t~mem2| 0)), 13641#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 3) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 3))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= 3 cstrcat_~s~0.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))))), 13642#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 3) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem2| 0))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 3))))) (= |cstrcat_#t~mem2| 0)) (or (= |cstrcat_#t~mem2| 0) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (= 3 cstrcat_~s~0.offset)))), 13643#(and (or (<= (select |#length| cstrcat_~s2.base) 3) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (= cstrcat_~s~0.offset (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))) (= 0 cstrcat_~s2.offset)), 13644#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 3) (and (= cstrcat_~s~0.offset (select |#length| cstrcat_~s2.base)) (= |cstrcat_#t~mem2| 0)) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)))), 13645#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 3) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 13646#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 3) (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)))), 13647#(and (= |cstrcat_#t~post5.offset| 0) (= |cstrcat_#t~post5.base| cstrcat_~s2.base) (or (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) (+ cstrcat_~s2.offset 2)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 13648#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 2)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 13649#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 13650#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (<= (+ |cstrcat_#t~post4.offset| 2) (select |#length| |cstrcat_#t~post4.base|)) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)) (<= (+ (select |#length| |cstrcat_#t~post4.base|) cstrcat_~s~0.offset) (+ |cstrcat_#t~post4.offset| (select |#length| cstrcat_~s~0.base) 1))), 13651#(or (and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 13652#(or (and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 13653#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))), 13624#true, 13625#false, 13626#(<= 1 main_~length3~0), 13627#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 13628#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 13629#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 13630#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (or (<= (+ main_~length3~0 main_~length1~0 1) (select |#length| |main_#t~malloc11.base|)) (= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|))) (= main_~nondetString1~0.offset 0)), 13631#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0))] [2018-04-11 12:49:24,053 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:24,053 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-04-11 12:49:24,053 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-04-11 12:49:24,054 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=797, Unknown=0, NotChecked=0, Total=870 [2018-04-11 12:49:24,054 INFO L87 Difference]: Start difference. First operand 137 states and 147 transitions. Second operand 30 states. [2018-04-11 12:49:24,709 WARN L151 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 127 DAG size of output 126 [2018-04-11 12:49:24,861 WARN L151 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 139 DAG size of output 138 [2018-04-11 12:49:25,178 WARN L151 SmtUtils]: Spent 117ms on a formula simplification. DAG size of input: 113 DAG size of output 110 [2018-04-11 12:49:25,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:49:25,696 INFO L93 Difference]: Finished difference Result 179 states and 189 transitions. [2018-04-11 12:49:25,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-04-11 12:49:25,696 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 58 [2018-04-11 12:49:25,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:49:25,697 INFO L225 Difference]: With dead ends: 179 [2018-04-11 12:49:25,697 INFO L226 Difference]: Without dead ends: 179 [2018-04-11 12:49:25,697 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 422 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=212, Invalid=2044, Unknown=0, NotChecked=0, Total=2256 [2018-04-11 12:49:25,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-04-11 12:49:25,699 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 137. [2018-04-11 12:49:25,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-04-11 12:49:25,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 147 transitions. [2018-04-11 12:49:25,699 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 147 transitions. Word has length 58 [2018-04-11 12:49:25,699 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:49:25,700 INFO L459 AbstractCegarLoop]: Abstraction has 137 states and 147 transitions. [2018-04-11 12:49:25,700 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-04-11 12:49:25,700 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 147 transitions. [2018-04-11 12:49:25,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-04-11 12:49:25,700 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:49:25,700 INFO L355 BasicCegarLoop]: trace histogram [14, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:49:25,700 INFO L408 AbstractCegarLoop]: === Iteration 54 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:49:25,700 INFO L82 PathProgramCache]: Analyzing trace with hash -1158996756, now seen corresponding path program 12 times [2018-04-11 12:49:25,701 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:49:25,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:49:25,712 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:49:27,942 WARN L151 SmtUtils]: Spent 804ms on a formula simplification. DAG size of input: 843 DAG size of output 97 [2018-04-11 12:49:28,613 WARN L151 SmtUtils]: Spent 611ms on a formula simplification. DAG size of input: 618 DAG size of output 88 [2018-04-11 12:49:29,308 WARN L151 SmtUtils]: Spent 629ms on a formula simplification. DAG size of input: 618 DAG size of output 88 [2018-04-11 12:49:30,001 WARN L151 SmtUtils]: Spent 619ms on a formula simplification. DAG size of input: 620 DAG size of output 88 [2018-04-11 12:49:30,729 WARN L151 SmtUtils]: Spent 640ms on a formula simplification. DAG size of input: 638 DAG size of output 97 [2018-04-11 12:49:31,491 WARN L151 SmtUtils]: Spent 666ms on a formula simplification. DAG size of input: 640 DAG size of output 97 [2018-04-11 12:49:31,971 WARN L151 SmtUtils]: Spent 395ms on a formula simplification. DAG size of input: 428 DAG size of output 88 [2018-04-11 12:49:32,436 WARN L151 SmtUtils]: Spent 388ms on a formula simplification. DAG size of input: 430 DAG size of output 88 [2018-04-11 12:49:32,738 WARN L151 SmtUtils]: Spent 241ms on a formula simplification. DAG size of input: 304 DAG size of output 79 [2018-04-11 12:49:33,049 WARN L151 SmtUtils]: Spent 247ms on a formula simplification. DAG size of input: 306 DAG size of output 79 [2018-04-11 12:49:33,270 WARN L151 SmtUtils]: Spent 167ms on a formula simplification. DAG size of input: 212 DAG size of output 72 [2018-04-11 12:49:33,494 WARN L151 SmtUtils]: Spent 168ms on a formula simplification. DAG size of input: 214 DAG size of output 72 [2018-04-11 12:49:34,517 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:34,517 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:49:34,517 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35] total 35 [2018-04-11 12:49:34,517 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:49:34,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:34,518 INFO L182 omatonBuilderFactory]: Interpolants [14016#(and (or (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 1) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ 5 2) 2) 2) (- 1)))) (<= 12 (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 2) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 11 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ 5 2) 2) 1) (- 1))))) (and (<= 10 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 2) (- 1))))) (and (<= 13 (select |#length| cstrcat_~s~0.base)) (or (<= 14 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ 5 2) 2) 2) 1) (- 1))))))) (= cstrcat_~s~0.offset 0)), 14017#(and (or (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 12) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 13) (select |#length| cstrcat_~s~0.base)))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 1)), 14018#(and (or (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 12) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 13) (select |#length| cstrcat_~s~0.base)))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 1)), 14019#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 12) (select |#length| cstrcat_~s~0.base))))), 14020#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 12) (select |#length| cstrcat_~s~0.base))))), 14021#(or (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1)))))), 14022#(or (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1)))))), 14023#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 14024#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) (- 1)))))), 14025#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1)))))), 14026#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1)))))), 14027#(or (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 14028#(or (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 14029#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))))), 14030#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))))), 14031#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 14032#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 14033#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))), 14034#(or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))), 14035#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 14036#(or (= |cstrcat_#t~mem2| 0) (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 14037#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 14038#(or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 14039#(<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)), 14040#(and (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (<= 0 cstrcat_~s~0.offset)), 14041#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 14006#true, 14007#false, 14008#(<= 1 main_~length1~0), 14009#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 14010#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 14011#(and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 14012#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1))), 14013#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 2) (+ main_~nondetString2~0.offset (- 1))))) (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 12 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 2) 2) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 5) (- 1))))) (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 1) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 2) 1) (+ main_~nondetString2~0.offset (- 1))))) (<= 11 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) (+ main_~nondetString2~0.offset (- 1))))) (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 2) 2) 1) (- 1))))) (<= 14 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= 13 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))))), 14014#(and (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 5 2) 1) (- 1)))) (<= 9 (select |#length| |cstrcat_#in~s1.base|))) (and (<= 12 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ (+ 5 2) 2) 2) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ (+ 5 2) 2) 1) (- 1)))) (<= 11 (select |#length| |cstrcat_#in~s1.base|))) (and (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 5 2) 2) (- 1)))) (<= 10 (select |#length| |cstrcat_#in~s1.base|))) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 1) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= 6 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 2) (- 1)))) (<= 8 (select |#length| |cstrcat_#in~s1.base|))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ (+ (+ 5 2) 2) 2) 1) (- 1)))) (<= 14 (select |#length| |cstrcat_#in~s1.base|))) (<= 13 (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s1.offset|)), 14015#(and (or (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 1) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ 5 2) 2) 2) (- 1)))) (<= 12 (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 2) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 11 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ 5 2) 2) 1) (- 1))))) (and (<= 10 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 2) (- 1))))) (and (<= 13 (select |#length| cstrcat_~s~0.base)) (or (<= 14 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ 5 2) 2) 2) 1) (- 1))))))) (= cstrcat_~s~0.offset 0))] [2018-04-11 12:49:34,518 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:34,518 INFO L442 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-04-11 12:49:34,518 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-04-11 12:49:34,518 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=181, Invalid=1079, Unknown=0, NotChecked=0, Total=1260 [2018-04-11 12:49:34,519 INFO L87 Difference]: Start difference. First operand 137 states and 147 transitions. Second operand 36 states. [2018-04-11 12:49:35,506 WARN L151 SmtUtils]: Spent 255ms on a formula simplification. DAG size of input: 173 DAG size of output 172 [2018-04-11 12:49:35,676 WARN L151 SmtUtils]: Spent 125ms on a formula simplification. DAG size of input: 165 DAG size of output 162 [2018-04-11 12:49:35,889 WARN L151 SmtUtils]: Spent 188ms on a formula simplification. DAG size of input: 168 DAG size of output 165 [2018-04-11 12:49:36,053 WARN L151 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 157 DAG size of output 154 [2018-04-11 12:49:36,249 WARN L151 SmtUtils]: Spent 172ms on a formula simplification. DAG size of input: 160 DAG size of output 157 [2018-04-11 12:49:36,407 WARN L151 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 151 DAG size of output 148 [2018-04-11 12:49:36,594 WARN L151 SmtUtils]: Spent 159ms on a formula simplification. DAG size of input: 154 DAG size of output 151 [2018-04-11 12:49:36,735 WARN L151 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 143 DAG size of output 140 [2018-04-11 12:49:36,911 WARN L151 SmtUtils]: Spent 143ms on a formula simplification. DAG size of input: 146 DAG size of output 143 [2018-04-11 12:49:37,059 WARN L151 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 137 DAG size of output 134 [2018-04-11 12:49:37,252 WARN L151 SmtUtils]: Spent 138ms on a formula simplification. DAG size of input: 140 DAG size of output 137 [2018-04-11 12:49:37,670 WARN L151 SmtUtils]: Spent 112ms on a formula simplification. DAG size of input: 132 DAG size of output 129 [2018-04-11 12:49:37,957 WARN L151 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 126 DAG size of output 123 [2018-04-11 12:49:38,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:49:38,937 INFO L93 Difference]: Finished difference Result 180 states and 192 transitions. [2018-04-11 12:49:38,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-04-11 12:49:38,937 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 59 [2018-04-11 12:49:38,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:49:38,938 INFO L225 Difference]: With dead ends: 180 [2018-04-11 12:49:38,938 INFO L226 Difference]: Without dead ends: 180 [2018-04-11 12:49:38,938 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 694 ImplicationChecksByTransitivity, 11.3s TimeCoverageRelationStatistics Valid=746, Invalid=3544, Unknown=0, NotChecked=0, Total=4290 [2018-04-11 12:49:38,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-04-11 12:49:38,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 143. [2018-04-11 12:49:38,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-04-11 12:49:38,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 154 transitions. [2018-04-11 12:49:38,940 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 154 transitions. Word has length 59 [2018-04-11 12:49:38,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:49:38,941 INFO L459 AbstractCegarLoop]: Abstraction has 143 states and 154 transitions. [2018-04-11 12:49:38,941 INFO L460 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-04-11 12:49:38,941 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 154 transitions. [2018-04-11 12:49:38,941 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-04-11 12:49:38,941 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:49:38,941 INFO L355 BasicCegarLoop]: trace histogram [9, 9, 8, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:49:38,941 INFO L408 AbstractCegarLoop]: === Iteration 55 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:49:38,942 INFO L82 PathProgramCache]: Analyzing trace with hash 1724506159, now seen corresponding path program 19 times [2018-04-11 12:49:38,942 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:49:38,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:49:38,957 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:49:39,564 WARN L151 SmtUtils]: Spent 156ms on a formula simplification. DAG size of input: 101 DAG size of output 70 [2018-04-11 12:49:39,725 WARN L151 SmtUtils]: Spent 150ms on a formula simplification. DAG size of input: 85 DAG size of output 63 [2018-04-11 12:49:39,887 WARN L151 SmtUtils]: Spent 148ms on a formula simplification. DAG size of input: 85 DAG size of output 63 [2018-04-11 12:49:40,040 WARN L151 SmtUtils]: Spent 137ms on a formula simplification. DAG size of input: 87 DAG size of output 63 [2018-04-11 12:49:40,181 WARN L151 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 95 DAG size of output 62 [2018-04-11 12:49:40,335 WARN L151 SmtUtils]: Spent 131ms on a formula simplification. DAG size of input: 97 DAG size of output 62 [2018-04-11 12:49:41,029 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 0 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:41,029 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:49:41,029 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2018-04-11 12:49:41,029 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:49:41,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:41,030 INFO L182 omatonBuilderFactory]: Interpolants [14425#true, 14426#false, 14427#(<= 1 main_~length3~0), 14428#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 14429#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|)) (= (select |#valid| |main_#t~malloc10.base|) 1)), 14430#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 14431#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|))), 14432#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1))), 14433#(and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)))) (= 0 main_~nondetString2~0.offset)), 14434#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 main_~nondetString1~0.offset) (or (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (- 1)) (- 1)) (- 1)) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 8) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= (+ (select |#length| main_~nondetString1~0.base) 7) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (- 1)) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (- 1)) (- 1)) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 6) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 14435#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1)) (- 1))))) (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 7) (select |#length| |cstrcat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 8) (select |#length| |cstrcat_#in~s1.base|)))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1)) (- 1)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 5) (select |#length| |cstrcat_#in~s1.base|))) (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 6) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s2.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 14436#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 cstrcat_~s2.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 8) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 7) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)) (- 1)) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 0)), 14437#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 8) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 7) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)) (- 1)) (- 1)))))))) (= cstrcat_~s~0.offset 0)), 14438#(and (= cstrcat_~s~0.offset 1) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))))))), 14439#(and (or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))))) (= cstrcat_~s~0.offset 1)), 14440#(or (and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 14441#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))))), 14442#(or (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))))) (= 0 cstrcat_~s2.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 14443#(or (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))))) (= 0 cstrcat_~s2.offset)) (= |cstrcat_#t~mem2| 0)), 14444#(or (and (= 0 cstrcat_~s2.offset) (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 14445#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))))), 14446#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 14447#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 14448#(or (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 14449#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 14450#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))), 14451#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 14452#(or (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (and (= |cstrcat_#t~post5.offset| 0) (= |cstrcat_#t~post5.base| cstrcat_~s2.base) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) (+ cstrcat_~s2.offset 1)))), 14453#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 14454#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 14455#(or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 14456#(or (and (<= 2 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 14457#(and (<= 2 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:49:41,030 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 0 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:41,030 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-04-11 12:49:41,030 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-04-11 12:49:41,030 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=951, Unknown=0, NotChecked=0, Total=1056 [2018-04-11 12:49:41,030 INFO L87 Difference]: Start difference. First operand 143 states and 154 transitions. Second operand 33 states. [2018-04-11 12:49:41,829 WARN L151 SmtUtils]: Spent 111ms on a formula simplification. DAG size of input: 125 DAG size of output 123 [2018-04-11 12:49:41,970 WARN L151 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 128 DAG size of output 126 [2018-04-11 12:49:42,113 WARN L151 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 118 DAG size of output 116 [2018-04-11 12:49:42,246 WARN L151 SmtUtils]: Spent 111ms on a formula simplification. DAG size of input: 121 DAG size of output 119 [2018-04-11 12:49:42,502 WARN L151 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 114 DAG size of output 112 [2018-04-11 12:49:43,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:49:43,656 INFO L93 Difference]: Finished difference Result 183 states and 194 transitions. [2018-04-11 12:49:43,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-04-11 12:49:43,656 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 59 [2018-04-11 12:49:43,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:49:43,657 INFO L225 Difference]: With dead ends: 183 [2018-04-11 12:49:43,657 INFO L226 Difference]: Without dead ends: 183 [2018-04-11 12:49:43,657 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 848 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=435, Invalid=3225, Unknown=0, NotChecked=0, Total=3660 [2018-04-11 12:49:43,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183 states. [2018-04-11 12:49:43,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183 to 143. [2018-04-11 12:49:43,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-04-11 12:49:43,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 154 transitions. [2018-04-11 12:49:43,659 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 154 transitions. Word has length 59 [2018-04-11 12:49:43,659 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:49:43,659 INFO L459 AbstractCegarLoop]: Abstraction has 143 states and 154 transitions. [2018-04-11 12:49:43,659 INFO L460 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-04-11 12:49:43,659 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 154 transitions. [2018-04-11 12:49:43,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-04-11 12:49:43,659 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:49:43,659 INFO L355 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:49:43,659 INFO L408 AbstractCegarLoop]: === Iteration 56 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:49:43,659 INFO L82 PathProgramCache]: Analyzing trace with hash -218562123, now seen corresponding path program 20 times [2018-04-11 12:49:43,660 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:49:43,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:49:43,668 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:49:44,351 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 24 proven. 67 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:44,351 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:49:44,352 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-04-11 12:49:44,352 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:49:44,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:44,352 INFO L182 omatonBuilderFactory]: Interpolants [14848#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (or (and (= 0 main_~nondetString1~0.offset) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2))), 14849#(and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1))))))))) (= 0 main_~nondetString2~0.offset)), 14850#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|))) (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) (select |#length| |cstrcat_#in~s1.base|)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 5) (select |#length| |cstrcat_#in~s1.base|))))) (= 0 |cstrcat_#in~s2.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 14851#(and (= cstrcat_~s~0.offset 0) (or (and (= 0 cstrcat_~s2.offset) (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 14852#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (and (or (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base)))) (= 0 cstrcat_~s2.offset))) (= cstrcat_~s~0.offset 0)), 14853#(and (or (and (= 0 cstrcat_~s2.offset) (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 1)), 14854#(and (or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))))) (= cstrcat_~s~0.offset 1)), 14855#(or (and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 14856#(or (and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0)), 14857#(or (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 14858#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 14859#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 14860#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))), 14861#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (= |cstrcat_#t~post5.offset| 0) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)), 14862#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 14863#(and (<= 1 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 14864#(and (<= 2 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 14865#(and (<= 3 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 14866#(and (<= 4 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 14867#(and (<= 4 |cstrcat_#t~post4.offset|) (<= (+ (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post4.offset|) (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post4.base|)))), 14868#(and (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)) (<= 4 |cstrcat_#t~post4.offset|)), 14840#true, 14841#false, 14842#(<= 1 main_~length3~0), 14843#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 14844#(and (= 1 (select |#valid| |main_#t~malloc10.base|)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|))), 14845#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= 1 (select |#valid| main_~nondetString1~0.base))), 14846#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|))), 14847#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (< 2 (+ main_~nondetString2~0.offset main_~length3~0))) (or (and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base))) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)))))] [2018-04-11 12:49:44,352 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 24 proven. 67 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:44,352 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-04-11 12:49:44,352 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-04-11 12:49:44,353 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=734, Unknown=0, NotChecked=0, Total=812 [2018-04-11 12:49:44,353 INFO L87 Difference]: Start difference. First operand 143 states and 154 transitions. Second operand 29 states. [2018-04-11 12:49:45,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:49:45,466 INFO L93 Difference]: Finished difference Result 179 states and 190 transitions. [2018-04-11 12:49:45,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-04-11 12:49:45,466 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 60 [2018-04-11 12:49:45,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:49:45,466 INFO L225 Difference]: With dead ends: 179 [2018-04-11 12:49:45,466 INFO L226 Difference]: Without dead ends: 155 [2018-04-11 12:49:45,467 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 485 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=259, Invalid=1997, Unknown=0, NotChecked=0, Total=2256 [2018-04-11 12:49:45,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states. [2018-04-11 12:49:45,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 143. [2018-04-11 12:49:45,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-04-11 12:49:45,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 153 transitions. [2018-04-11 12:49:45,468 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 153 transitions. Word has length 60 [2018-04-11 12:49:45,468 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:49:45,468 INFO L459 AbstractCegarLoop]: Abstraction has 143 states and 153 transitions. [2018-04-11 12:49:45,468 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-04-11 12:49:45,468 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 153 transitions. [2018-04-11 12:49:45,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-04-11 12:49:45,469 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:49:45,469 INFO L355 BasicCegarLoop]: trace histogram [11, 11, 10, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:49:45,469 INFO L408 AbstractCegarLoop]: === Iteration 57 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:49:45,469 INFO L82 PathProgramCache]: Analyzing trace with hash -1246759127, now seen corresponding path program 21 times [2018-04-11 12:49:45,469 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:49:45,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:49:45,483 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:49:46,505 WARN L151 SmtUtils]: Spent 310ms on a formula simplification. DAG size of input: 147 DAG size of output 87 [2018-04-11 12:49:46,794 WARN L151 SmtUtils]: Spent 274ms on a formula simplification. DAG size of input: 121 DAG size of output 75 [2018-04-11 12:49:47,043 WARN L151 SmtUtils]: Spent 230ms on a formula simplification. DAG size of input: 121 DAG size of output 75 [2018-04-11 12:49:47,288 WARN L151 SmtUtils]: Spent 224ms on a formula simplification. DAG size of input: 123 DAG size of output 75 [2018-04-11 12:49:47,561 WARN L151 SmtUtils]: Spent 245ms on a formula simplification. DAG size of input: 136 DAG size of output 78 [2018-04-11 12:49:47,853 WARN L151 SmtUtils]: Spent 263ms on a formula simplification. DAG size of input: 138 DAG size of output 78 [2018-04-11 12:49:48,027 WARN L151 SmtUtils]: Spent 148ms on a formula simplification. DAG size of input: 102 DAG size of output 69 [2018-04-11 12:49:48,215 WARN L151 SmtUtils]: Spent 159ms on a formula simplification. DAG size of input: 104 DAG size of output 69 [2018-04-11 12:49:48,374 WARN L151 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 84 DAG size of output 62 [2018-04-11 12:49:48,527 WARN L151 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 86 DAG size of output 62 [2018-04-11 12:49:49,329 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 0 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:49,330 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:49:49,330 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34] total 34 [2018-04-11 12:49:49,330 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:49:49,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:49,330 INFO L182 omatonBuilderFactory]: Interpolants [15232#(and (or (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (< 11 main_~length2~0)) (<= 1 main_~length3~0)), 15233#(and (= 1 (select |#valid| |main_#t~malloc10.base|)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (or (< 11 main_~length2~0) (<= (+ (select |#length| |main_#t~malloc10.base|) main_~length3~0) main_~length2~0))), 15234#(and (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) main_~length2~0) (< 11 main_~length2~0)) (<= 1 main_~length3~0) (= 1 (select |#valid| main_~nondetString1~0.base))), 15235#(and (= 0 main_~nondetString1~0.offset) (<= 1 main_~length3~0) (or (<= 12 (select |#length| |main_#t~malloc11.base|)) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) 11)) (= 0 |main_#t~malloc11.offset|)), 15236#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) 11) (<= 12 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0)), 15237#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 8)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) 11) (+ main_~nondetString2~0.offset (- 1))))) (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 3))) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 6)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) 1) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 4)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) 1) 1) 1) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 7)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) (+ main_~nondetString2~0.offset (- 1)))))) (and (or (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 1)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- (select |#length| main_~nondetString1~0.base)) 10) (- 1)))))) (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 2))) (<= 12 (select |#length| main_~nondetString2~0.base)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) 1) 1) (+ main_~nondetString2~0.offset (- 1))))) (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 5))))), 15238#(and (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ (+ (+ 3 1) 1) 1) 1) (- 1)))) (<= (select |#length| |cstrcat_#in~s2.base|) 4)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) 11) (- 1)))) (<= (select |#length| |cstrcat_#in~s2.base|) 3)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= (select |#length| |cstrcat_#in~s2.base|) 2) (or (<= (select |#length| |cstrcat_#in~s2.base|) 1) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) 10) (- 1)))))) (<= 12 (select |#length| |cstrcat_#in~s1.base|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 3 1) (- 1)))) (<= (select |#length| |cstrcat_#in~s2.base|) 7)) (and (<= (select |#length| |cstrcat_#in~s2.base|) 6) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 3 1) 1) (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= (select |#length| |cstrcat_#in~s2.base|) 8) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ (+ 3 1) 1) 1) (- 1)))) (<= (select |#length| |cstrcat_#in~s2.base|) 5))) (= 0 |cstrcat_#in~s2.offset|) (= 0 |cstrcat_#in~s1.offset|)), 15239#(and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 3 1) 1) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 6)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ 3 1) 1) 1) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 5)) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ 3 1) 1) 1) 1) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) 10) (- 1)))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) 11) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 7) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 3 1) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 8) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= 12 (select |#length| cstrcat_~s~0.base))) (= cstrcat_~s~0.offset 0)), 15240#(and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 3 1) 1) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 6)) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ 3 1) 1) 1) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 5)) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ 3 1) 1) 1) 1) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) 10) (- 1)))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) 11) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 7) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 3 1) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 8) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (<= 12 (select |#length| cstrcat_~s~0.base))) (= cstrcat_~s~0.offset 0)), 15241#(and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 8) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 9)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (select |#length| cstrcat_~s2.base) 7) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) 1) 1) (- 1))))) (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) 1) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 5)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 10)) (- 1))))))), 15242#(and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 8) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 9)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (select |#length| cstrcat_~s2.base) 7) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) 1) 1) (- 1))))) (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset)) (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) 1) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 5)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 10)) (- 1))))))), 15243#(and (= 0 cstrcat_~s2.offset) (or (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 8)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 9)) (- 1))))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 7) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) 1) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 4)))), 15244#(and (= 0 cstrcat_~s2.offset) (or (= |cstrcat_#t~mem2| 0) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 8)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 9)) (- 1))))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 7) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) 1) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 4)))), 15245#(and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 7)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 8)) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 15246#(and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 7)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 8)) (- 1))))))), 15247#(and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 7)) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 6)) (- 1)))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))), 15248#(and (or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 7)) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 6)) (- 1)))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))) (= 0 cstrcat_~s2.offset)), 15249#(and (= 0 cstrcat_~s2.offset) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 6)) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 5)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))), 15250#(and (= 0 cstrcat_~s2.offset) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem2| 0) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 6)) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 5)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))), 15251#(and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 5)) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 4)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= 0 cstrcat_~s2.offset)), 15252#(and (= 0 cstrcat_~s2.offset) (or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 5)) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 4)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)))), 15253#(and (= 0 cstrcat_~s2.offset) (or (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 4)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 15254#(and (= 0 cstrcat_~s2.offset) (or (= |cstrcat_#t~mem2| 0) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 4)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 15255#(and (or (<= (select |#length| cstrcat_~s2.base) 1) (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= 0 cstrcat_~s2.offset)), 15256#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 1) (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem2| 0))), 15257#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 1) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 15258#(and (or (<= (select |#length| cstrcat_~s2.base) 1) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= 0 cstrcat_~s2.offset)), 15259#(and (or (<= (select |#length| cstrcat_~s2.base) 1) (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))) (<= (+ |cstrcat_#t~post5.offset| 1) cstrcat_~s2.offset) (= |cstrcat_#t~post5.offset| 0) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)), 15260#(or (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 15261#(or (and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 15262#(or (and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 15263#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))), 15229#true, 15230#false, 15231#(<= 1 main_~length3~0)] [2018-04-11 12:49:49,331 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 0 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:49,331 INFO L442 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-04-11 12:49:49,331 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-04-11 12:49:49,331 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=1115, Unknown=0, NotChecked=0, Total=1190 [2018-04-11 12:49:49,331 INFO L87 Difference]: Start difference. First operand 143 states and 153 transitions. Second operand 35 states. [2018-04-11 12:49:50,243 WARN L151 SmtUtils]: Spent 148ms on a formula simplification. DAG size of input: 142 DAG size of output 141 [2018-04-11 12:49:51,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:49:51,994 INFO L93 Difference]: Finished difference Result 172 states and 182 transitions. [2018-04-11 12:49:51,994 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-04-11 12:49:51,994 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 60 [2018-04-11 12:49:51,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:49:51,995 INFO L225 Difference]: With dead ends: 172 [2018-04-11 12:49:51,995 INFO L226 Difference]: Without dead ends: 172 [2018-04-11 12:49:51,995 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 612 ImplicationChecksByTransitivity, 5.0s TimeCoverageRelationStatistics Valid=230, Invalid=3552, Unknown=0, NotChecked=0, Total=3782 [2018-04-11 12:49:51,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-04-11 12:49:51,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 143. [2018-04-11 12:49:51,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-04-11 12:49:51,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 153 transitions. [2018-04-11 12:49:51,997 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 153 transitions. Word has length 60 [2018-04-11 12:49:51,998 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:49:51,998 INFO L459 AbstractCegarLoop]: Abstraction has 143 states and 153 transitions. [2018-04-11 12:49:51,998 INFO L460 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-04-11 12:49:51,998 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 153 transitions. [2018-04-11 12:49:51,998 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-04-11 12:49:51,998 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:49:51,999 INFO L355 BasicCegarLoop]: trace histogram [8, 8, 7, 4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:49:51,999 INFO L408 AbstractCegarLoop]: === Iteration 58 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:49:51,999 INFO L82 PathProgramCache]: Analyzing trace with hash 682665571, now seen corresponding path program 22 times [2018-04-11 12:49:51,999 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:49:52,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:49:52,013 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:49:52,731 WARN L151 SmtUtils]: Spent 215ms on a formula simplification. DAG size of input: 221 DAG size of output 94 [2018-04-11 12:49:52,962 WARN L151 SmtUtils]: Spent 211ms on a formula simplification. DAG size of input: 181 DAG size of output 79 [2018-04-11 12:49:53,184 WARN L151 SmtUtils]: Spent 198ms on a formula simplification. DAG size of input: 181 DAG size of output 83 [2018-04-11 12:49:53,417 WARN L151 SmtUtils]: Spent 207ms on a formula simplification. DAG size of input: 183 DAG size of output 83 [2018-04-11 12:49:53,691 WARN L151 SmtUtils]: Spent 237ms on a formula simplification. DAG size of input: 218 DAG size of output 99 [2018-04-11 12:49:53,962 WARN L151 SmtUtils]: Spent 228ms on a formula simplification. DAG size of input: 220 DAG size of output 99 [2018-04-11 12:49:54,166 WARN L151 SmtUtils]: Spent 160ms on a formula simplification. DAG size of input: 146 DAG size of output 92 [2018-04-11 12:49:54,337 WARN L151 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 148 DAG size of output 96 [2018-04-11 12:49:54,861 INFO L134 CoverageAnalysis]: Checked inductivity of 111 backedges. 0 proven. 111 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:54,861 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:49:54,861 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-04-11 12:49:54,861 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:49:54,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:54,862 INFO L182 omatonBuilderFactory]: Interpolants [15633#true, 15634#false, 15635#(<= 1 main_~length3~0), 15636#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 15637#(and (= 1 (select |#valid| |main_#t~malloc10.base|)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|))), 15638#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= 1 (select |#valid| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 15639#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|)) (= main_~nondetString1~0.offset 0)), 15640#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 15641#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 15642#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (or (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (or (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 1) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (and (<= 4 (+ main_~nondetString2~0.offset (div (+ (select |#length| main_~nondetString2~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset (- 1)))) 2))) (or (<= 5 (+ main_~nondetString2~0.offset (div (+ (select |#length| main_~nondetString2~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset (- 1)))) 2))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (div (+ (select |#length| main_~nondetString2~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset (- 1)))) 2) (+ main_~nondetString2~0.offset (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1)))))))) (or (and (<= 4 (+ main_~nondetString2~0.offset (div (+ (select |#length| main_~nondetString2~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset (- 1)))) 2))) (or (<= 5 (+ main_~nondetString2~0.offset (div (+ (select |#length| main_~nondetString2~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset (- 1)))) 2))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (div (+ (select |#length| main_~nondetString2~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset (- 1)))) 2) (+ main_~nondetString2~0.offset (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ (- (+ (- main_~nondetString2~0.offset) 4)) (- 1))) (+ main_~nondetString1~0.offset (- 1))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (+ (select |#length| main_~nondetString2~0.base) (- (+ (- main_~nondetString2~0.offset) 4))))) (+ main_~nondetString2~0.offset (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (- 1))))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= main_~nondetString1~0.offset 0)), 15643#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (and (or (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 3) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1))))) (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 2) (select |#length| |cstrcat_#in~s1.base|))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (select |#length| |cstrcat_#in~s2.base|))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (div (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) 2) (- 1)))) (<= 5 (div (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) 2))) (<= 4 (div (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) 2))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (+ (select |#length| |cstrcat_#in~s1.base|) (- 4)))) (- 1)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (+ (- 4) (- 1))) (- 1))))) (or (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 5) (select |#length| |cstrcat_#in~s1.base|))) (or (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (div (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) 2) (- 1)))) (<= 5 (div (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) 2))) (<= 4 (div (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) 2))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1)))) (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 2) (select |#length| |cstrcat_#in~s1.base|)))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|)))))) (= 0 |cstrcat_#in~s2.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 15644#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (or (and (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1)))) (and (or (<= 5 (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2) (- 1))))) (<= 4 (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- 4) (- 1))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (+ (select |#length| cstrcat_~s~0.base) (- 4)))) (- 1)))) (and (or (<= 5 (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2) (- 1))))) (<= 4 (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2))))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base)))) (= 0 cstrcat_~s2.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 0)), 15645#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (or (and (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1)))) (and (or (<= 5 (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2) (- 1))))) (<= 4 (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- 4) (- 1))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (+ (select |#length| cstrcat_~s~0.base) (- 4)))) (- 1)))) (and (or (<= 5 (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2) (- 1))))) (<= 4 (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2))))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base)))) (= 0 cstrcat_~s2.offset))) (= cstrcat_~s~0.offset 0)), 15646#(or (and (= 0 cstrcat_~s2.offset) (<= cstrcat_~s~0.offset 1) (or (and (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1)))) (- 1)))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))) (and (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset (- 1)))) (- 1))))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 2))) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 4) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 2))) 2)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ cstrcat_~s~0.offset 3)) (+ cstrcat_~s~0.offset (- 2)))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ cstrcat_~s~0.offset 3)) (+ cstrcat_~s~0.offset (- 1))))) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))))) (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 15647#(or (and (= 0 cstrcat_~s2.offset) (<= cstrcat_~s~0.offset 1) (or (and (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1)))) (- 1)))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))) (and (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset (- 1)))) (- 1))))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 2))) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 4) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 2))) 2)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ cstrcat_~s~0.offset 3)) (+ cstrcat_~s~0.offset (- 2)))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ cstrcat_~s~0.offset 3)) (+ cstrcat_~s~0.offset (- 1))))) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))))) (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset))), 15648#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 cstrcat_~s2.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 2)))) (- 2)))) (- 1)))) (and (or (<= (+ cstrcat_~s~0.offset 3) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 2) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (or (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset (- 2)))) (- 1))))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ cstrcat_~s~0.offset 2)) (+ cstrcat_~s~0.offset (- 3)))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ cstrcat_~s~0.offset 2)) (+ cstrcat_~s~0.offset (- 2))))) (+ cstrcat_~s~0.offset (- 2)))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (and (or (<= (+ cstrcat_~s~0.offset 3) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 2) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 2)))) (- 2)))) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base)))) (<= cstrcat_~s~0.offset 2))), 15649#(or (= |cstrcat_#t~mem2| 0) (and (or (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 2)))) (- 2)))) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 2)))) (- 2)))) (- 1)))) (and (or (<= (+ cstrcat_~s~0.offset 3) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 2) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ cstrcat_~s~0.offset 2)) (+ cstrcat_~s~0.offset (- 2))))) (+ cstrcat_~s~0.offset (- 2)))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ cstrcat_~s~0.offset 2)) (+ cstrcat_~s~0.offset (- 3)))) (- 1)))) (and (or (<= (+ cstrcat_~s~0.offset 3) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 2) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2)))))) (or (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset (- 2)))) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base)))) (= 0 cstrcat_~s2.offset) (<= cstrcat_~s~0.offset 2))), 15650#(or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s2.base)) (or (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 4)) (- 1)))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 5)) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base)))) (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)))))), 15651#(or (and (or (and (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (or (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 5)) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 4)) (- 1)))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base))))) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s2.base))) (= |cstrcat_#t~mem2| 0) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset))), 15652#(or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 4)) (- 1)))) (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base))))), 15653#(or (= |cstrcat_#t~mem2| 0) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset)) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 4)) (- 1)))) (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base))))), 15654#(or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 15655#(or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset))), 15656#(or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 15657#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset))), 15658#(or (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (and (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) (+ cstrcat_~s2.offset 2)) (= |cstrcat_#t~post5.offset| 0) (= |cstrcat_#t~post5.base| cstrcat_~s2.base))), 15659#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 2)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 15660#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 15661#(or (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ (select |#length| |cstrcat_#t~post4.base|) cstrcat_~s~0.offset) (+ |cstrcat_#t~post4.offset| (select |#length| cstrcat_~s~0.base) 1)) (<= (+ |cstrcat_#t~post4.offset| 2) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 15662#(or (and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 15663#(or (and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 15664#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:49:54,862 INFO L134 CoverageAnalysis]: Checked inductivity of 111 backedges. 0 proven. 111 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:49:54,862 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-11 12:49:54,862 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-11 12:49:54,862 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=905, Unknown=0, NotChecked=0, Total=992 [2018-04-11 12:49:54,862 INFO L87 Difference]: Start difference. First operand 143 states and 153 transitions. Second operand 32 states. [2018-04-11 12:49:55,306 WARN L151 SmtUtils]: Spent 229ms on a formula simplification. DAG size of input: 115 DAG size of output 91 [2018-04-11 12:49:55,611 WARN L148 SmtUtils]: Spent 101ms on a formula simplification that was a NOOP. DAG size: 149 [2018-04-11 12:49:55,767 WARN L148 SmtUtils]: Spent 105ms on a formula simplification that was a NOOP. DAG size: 166 [2018-04-11 12:49:56,024 WARN L151 SmtUtils]: Spent 210ms on a formula simplification. DAG size of input: 170 DAG size of output 169 [2018-04-11 12:49:56,194 WARN L148 SmtUtils]: Spent 115ms on a formula simplification that was a NOOP. DAG size: 170 [2018-04-11 12:49:56,401 WARN L148 SmtUtils]: Spent 168ms on a formula simplification that was a NOOP. DAG size: 182 [2018-04-11 12:49:56,788 WARN L151 SmtUtils]: Spent 111ms on a formula simplification. DAG size of input: 106 DAG size of output 102 [2018-04-11 12:49:57,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:49:57,508 INFO L93 Difference]: Finished difference Result 185 states and 195 transitions. [2018-04-11 12:49:57,508 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-04-11 12:49:57,508 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 61 [2018-04-11 12:49:57,508 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:49:57,509 INFO L225 Difference]: With dead ends: 185 [2018-04-11 12:49:57,509 INFO L226 Difference]: Without dead ends: 185 [2018-04-11 12:49:57,509 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 526 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=280, Invalid=2372, Unknown=0, NotChecked=0, Total=2652 [2018-04-11 12:49:57,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 185 states. [2018-04-11 12:49:57,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 185 to 143. [2018-04-11 12:49:57,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-04-11 12:49:57,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 153 transitions. [2018-04-11 12:49:57,511 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 153 transitions. Word has length 61 [2018-04-11 12:49:57,511 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:49:57,511 INFO L459 AbstractCegarLoop]: Abstraction has 143 states and 153 transitions. [2018-04-11 12:49:57,511 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-11 12:49:57,511 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 153 transitions. [2018-04-11 12:49:57,511 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-04-11 12:49:57,511 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:49:57,511 INFO L355 BasicCegarLoop]: trace histogram [15, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:49:57,512 INFO L408 AbstractCegarLoop]: === Iteration 59 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:49:57,512 INFO L82 PathProgramCache]: Analyzing trace with hash -430265738, now seen corresponding path program 13 times [2018-04-11 12:49:57,512 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:49:57,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:49:57,525 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:50:01,581 WARN L151 SmtUtils]: Spent 1629ms on a formula simplification. DAG size of input: 1089 DAG size of output 105 [2018-04-11 12:50:03,158 WARN L151 SmtUtils]: Spent 1491ms on a formula simplification. DAG size of input: 873 DAG size of output 96 [2018-04-11 12:50:04,498 WARN L151 SmtUtils]: Spent 1234ms on a formula simplification. DAG size of input: 873 DAG size of output 94 [2018-04-11 12:50:05,821 WARN L151 SmtUtils]: Spent 1214ms on a formula simplification. DAG size of input: 875 DAG size of output 94 [2018-04-11 12:50:07,298 WARN L151 SmtUtils]: Spent 1354ms on a formula simplification. DAG size of input: 894 DAG size of output 103 [2018-04-11 12:50:08,880 WARN L151 SmtUtils]: Spent 1443ms on a formula simplification. DAG size of input: 896 DAG size of output 103 [2018-04-11 12:50:09,799 WARN L151 SmtUtils]: Spent 812ms on a formula simplification. DAG size of input: 601 DAG size of output 97 [2018-04-11 12:50:10,709 WARN L151 SmtUtils]: Spent 804ms on a formula simplification. DAG size of input: 603 DAG size of output 97 [2018-04-11 12:50:11,264 WARN L151 SmtUtils]: Spent 471ms on a formula simplification. DAG size of input: 428 DAG size of output 85 [2018-04-11 12:50:11,852 WARN L151 SmtUtils]: Spent 499ms on a formula simplification. DAG size of input: 430 DAG size of output 85 [2018-04-11 12:50:12,276 WARN L151 SmtUtils]: Spent 344ms on a formula simplification. DAG size of input: 297 DAG size of output 78 [2018-04-11 12:50:12,713 WARN L151 SmtUtils]: Spent 361ms on a formula simplification. DAG size of input: 299 DAG size of output 78 [2018-04-11 12:50:12,943 WARN L151 SmtUtils]: Spent 169ms on a formula simplification. DAG size of input: 203 DAG size of output 71 [2018-04-11 12:50:13,177 WARN L151 SmtUtils]: Spent 170ms on a formula simplification. DAG size of input: 205 DAG size of output 71 [2018-04-11 12:50:13,351 WARN L151 SmtUtils]: Spent 120ms on a formula simplification. DAG size of input: 145 DAG size of output 64 [2018-04-11 12:50:13,525 WARN L151 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 147 DAG size of output 64 [2018-04-11 12:50:14,431 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:50:14,431 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:50:14,465 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36] total 36 [2018-04-11 12:50:14,465 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:50:14,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:50:14,466 INFO L182 omatonBuilderFactory]: Interpolants [16064#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 16065#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0)), 16066#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 16067#(and (or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= 0 cstrcat_~s~0.offset)), 16068#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 16069#(and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 16033#true, 16034#false, 16035#(<= 1 main_~length1~0), 16036#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 16037#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 16038#(and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|)), 16039#(and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))) (= 0 main_~nondetString2~0.offset)), 16040#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 2) 2) (+ main_~nondetString2~0.offset (- 1))))) (<= 13 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= 11 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 2) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 5) (- 1))))) (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 2) 1) (+ main_~nondetString2~0.offset (- 1))))) (<= 12 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 2) 2) 1) (- 1))))) (<= 15 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= 14 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 1) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- 1)) (+ main_~nondetString2~0.offset (- 1))))) (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) (+ main_~nondetString2~0.offset (- 1))))) (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))))), 16041#(and (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1)))) (<= 8 (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 1) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s1.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 2) (- 1)))) (<= 9 (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= 6 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1))))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ (+ (+ 5 2) 2) 2) 1) (- 1)))) (<= 15 (select |#length| |cstrcat_#in~s1.base|))) (<= 14 (select |#length| |cstrcat_#in~s1.base|))) (and (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (and (<= 13 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ (+ 5 2) 2) 2) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 5 2) 1) (- 1)))) (<= 10 (select |#length| |cstrcat_#in~s1.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 5 2) 2) (- 1)))) (<= 11 (select |#length| |cstrcat_#in~s1.base|))) (and (<= 12 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ (+ 5 2) 2) 1) (- 1)))))) (= 0 |cstrcat_#in~s1.offset|)), 16042#(and (= cstrcat_~s~0.offset 0) (or (and (<= 14 (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ 5 2) 2) 2) 1) (- 1)))) (<= 15 (select |#length| cstrcat_~s~0.base)))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (<= 11 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 2) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 10 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ 5 2) 2) 2) (- 1)))) (<= 13 (select |#length| cstrcat_~s~0.base))) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 1) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (<= 11 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ 5 2) 2) 1) (- 1))))))), 16043#(and (= cstrcat_~s~0.offset 0) (or (and (<= 14 (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ 5 2) 2) 2) 1) (- 1)))) (<= 15 (select |#length| cstrcat_~s~0.base)))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (<= 11 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 2) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 10 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ 5 2) 2) 2) (- 1)))) (<= 13 (select |#length| cstrcat_~s~0.base))) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 2) 1) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (<= 11 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ 5 2) 2) 1) (- 1))))))), 16044#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 14) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 13) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 12) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 1)), 16045#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 14) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 13) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 12) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 1)), 16046#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 13) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 12) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)))), 16047#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 13) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 12) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)))), 16048#(or (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 12) (select |#length| cstrcat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)))), 16049#(or (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 12) (select |#length| cstrcat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)))), 16050#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))))), 16051#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 2) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))))), 16052#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))))), 16053#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 2) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))))), 16054#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))))), 16055#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 2) 1) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))))), 16056#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 16057#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1)))))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 16058#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1))))))), 16059#(or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1))))))), 16060#(or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 16061#(or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 16062#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 16063#(or (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))))] [2018-04-11 12:50:14,466 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:50:14,466 INFO L442 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-04-11 12:50:14,466 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-04-11 12:50:14,466 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=194, Invalid=1138, Unknown=0, NotChecked=0, Total=1332 [2018-04-11 12:50:14,466 INFO L87 Difference]: Start difference. First operand 143 states and 153 transitions. Second operand 37 states. [2018-04-11 12:50:15,268 WARN L148 SmtUtils]: Spent 103ms on a formula simplification that was a NOOP. DAG size: 182 [2018-04-11 12:50:15,460 WARN L151 SmtUtils]: Spent 149ms on a formula simplification. DAG size of input: 179 DAG size of output 173 [2018-04-11 12:50:15,700 WARN L151 SmtUtils]: Spent 211ms on a formula simplification. DAG size of input: 184 DAG size of output 179 [2018-04-11 12:50:15,892 WARN L151 SmtUtils]: Spent 143ms on a formula simplification. DAG size of input: 169 DAG size of output 163 [2018-04-11 12:50:16,113 WARN L151 SmtUtils]: Spent 192ms on a formula simplification. DAG size of input: 174 DAG size of output 169 [2018-04-11 12:50:16,287 WARN L151 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 163 DAG size of output 157 [2018-04-11 12:50:16,498 WARN L151 SmtUtils]: Spent 180ms on a formula simplification. DAG size of input: 168 DAG size of output 163 [2018-04-11 12:50:16,676 WARN L151 SmtUtils]: Spent 129ms on a formula simplification. DAG size of input: 157 DAG size of output 151 [2018-04-11 12:50:16,880 WARN L151 SmtUtils]: Spent 168ms on a formula simplification. DAG size of input: 162 DAG size of output 157 [2018-04-11 12:50:17,052 WARN L151 SmtUtils]: Spent 126ms on a formula simplification. DAG size of input: 151 DAG size of output 145 [2018-04-11 12:50:17,249 WARN L151 SmtUtils]: Spent 155ms on a formula simplification. DAG size of input: 156 DAG size of output 151 [2018-04-11 12:50:17,416 WARN L151 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 143 DAG size of output 137 [2018-04-11 12:50:17,612 WARN L151 SmtUtils]: Spent 139ms on a formula simplification. DAG size of input: 148 DAG size of output 143 [2018-04-11 12:50:17,853 WARN L151 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 137 DAG size of output 131 [2018-04-11 12:50:18,050 WARN L151 SmtUtils]: Spent 134ms on a formula simplification. DAG size of input: 142 DAG size of output 137 [2018-04-11 12:50:18,371 WARN L151 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 135 DAG size of output 130 [2018-04-11 12:50:18,680 WARN L151 SmtUtils]: Spent 111ms on a formula simplification. DAG size of input: 129 DAG size of output 124 [2018-04-11 12:50:19,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:50:19,429 INFO L93 Difference]: Finished difference Result 186 states and 198 transitions. [2018-04-11 12:50:19,429 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-04-11 12:50:19,429 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 62 [2018-04-11 12:50:19,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:50:19,429 INFO L225 Difference]: With dead ends: 186 [2018-04-11 12:50:19,429 INFO L226 Difference]: Without dead ends: 186 [2018-04-11 12:50:19,430 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 773 ImplicationChecksByTransitivity, 19.1s TimeCoverageRelationStatistics Valid=817, Invalid=3875, Unknown=0, NotChecked=0, Total=4692 [2018-04-11 12:50:19,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-04-11 12:50:19,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 149. [2018-04-11 12:50:19,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-04-11 12:50:19,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 160 transitions. [2018-04-11 12:50:19,468 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 160 transitions. Word has length 62 [2018-04-11 12:50:19,468 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:50:19,468 INFO L459 AbstractCegarLoop]: Abstraction has 149 states and 160 transitions. [2018-04-11 12:50:19,468 INFO L460 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-04-11 12:50:19,468 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 160 transitions. [2018-04-11 12:50:19,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-04-11 12:50:19,469 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:50:19,469 INFO L355 BasicCegarLoop]: trace histogram [10, 10, 9, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:50:19,469 INFO L408 AbstractCegarLoop]: === Iteration 60 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:50:19,469 INFO L82 PathProgramCache]: Analyzing trace with hash 2050011253, now seen corresponding path program 23 times [2018-04-11 12:50:19,469 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:50:19,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:50:19,480 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:50:20,019 WARN L151 SmtUtils]: Spent 145ms on a formula simplification. DAG size of input: 177 DAG size of output 76 [2018-04-11 12:50:20,184 WARN L151 SmtUtils]: Spent 149ms on a formula simplification. DAG size of input: 142 DAG size of output 69 [2018-04-11 12:50:20,314 WARN L151 SmtUtils]: Spent 112ms on a formula simplification. DAG size of input: 142 DAG size of output 69 [2018-04-11 12:50:20,457 WARN L151 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 144 DAG size of output 69 [2018-04-11 12:50:20,659 WARN L151 SmtUtils]: Spent 175ms on a formula simplification. DAG size of input: 156 DAG size of output 71 [2018-04-11 12:50:20,856 WARN L151 SmtUtils]: Spent 166ms on a formula simplification. DAG size of input: 158 DAG size of output 71 [2018-04-11 12:50:20,982 WARN L151 SmtUtils]: Spent 100ms on a formula simplification. DAG size of input: 104 DAG size of output 64 [2018-04-11 12:50:21,755 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:50:21,755 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:50:21,755 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34] total 34 [2018-04-11 12:50:21,755 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:50:21,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:50:21,755 INFO L182 omatonBuilderFactory]: Interpolants [16469#true, 16470#false, 16471#(<= 1 main_~length3~0), 16472#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 16473#(and (= 1 (select |#valid| |main_#t~malloc10.base|)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|))), 16474#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= 1 (select |#valid| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 16475#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|)) (= main_~nondetString1~0.offset 0)), 16476#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 16477#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 16478#(and (= 0 main_~nondetString2~0.offset) (or (and (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 1) 1) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 9) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= (+ (select |#length| main_~nondetString1~0.base) 8) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 6) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 7) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 1) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 3) (- 1))))))) (= main_~nondetString1~0.offset 0)), 16479#(and (= 0 |cstrcat_#in~s2.offset|) (or (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 5) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 5 1) 1) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 7) (select |#length| |cstrcat_#in~s1.base|))) (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 8) (select |#length| |cstrcat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ (+ 5 1) 1) 1) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 9) (select |#length| |cstrcat_#in~s1.base|)))) (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 6) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 1) (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s1.offset|)), 16480#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 6) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 7) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (and (or (<= (+ (select |#length| cstrcat_~s2.base) 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ 5 1) 1) 1) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 8) (select |#length| cstrcat_~s~0.base)))) (= 0 cstrcat_~s2.offset) (= cstrcat_~s~0.offset 0)), 16481#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 6) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 7) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (and (or (<= (+ (select |#length| cstrcat_~s2.base) 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ 5 1) 1) 1) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 8) (select |#length| cstrcat_~s~0.base)))) (= 0 cstrcat_~s2.offset) (= cstrcat_~s~0.offset 0)), 16482#(and (= 0 cstrcat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 1) 1) 1) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))), 16483#(and (= 0 cstrcat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset)) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 4) 1) 1) 1) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))), 16484#(or (and (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 1) 1) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))))), 16485#(or (and (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 3) 1) 1) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))))), 16486#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) 1) (- 1))))))), 16487#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) 1) (- 1))))))), 16488#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1))))))), 16489#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) 1) (- 1))))))), 16490#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)))), 16491#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (= |cstrcat_#t~mem2| 0) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)))), 16492#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 16493#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))), 16494#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 16495#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 16496#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))), 16497#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 16498#(or (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (and (= |cstrcat_#t~post5.offset| 0) (= |cstrcat_#t~post5.base| cstrcat_~s2.base) (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) (+ cstrcat_~s2.offset 1)))), 16499#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 16500#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 16501#(or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 16502#(or (and (<= 2 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 16503#(and (<= 2 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:50:21,756 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 0 proven. 148 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:50:21,756 INFO L442 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-04-11 12:50:21,756 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-04-11 12:50:21,756 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=121, Invalid=1069, Unknown=0, NotChecked=0, Total=1190 [2018-04-11 12:50:21,756 INFO L87 Difference]: Start difference. First operand 149 states and 160 transitions. Second operand 35 states. [2018-04-11 12:50:22,458 WARN L151 SmtUtils]: Spent 133ms on a formula simplification. DAG size of input: 132 DAG size of output 131 [2018-04-11 12:50:23,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:50:23,697 INFO L93 Difference]: Finished difference Result 189 states and 200 transitions. [2018-04-11 12:50:23,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-04-11 12:50:23,698 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 62 [2018-04-11 12:50:23,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:50:23,698 INFO L225 Difference]: With dead ends: 189 [2018-04-11 12:50:23,698 INFO L226 Difference]: Without dead ends: 189 [2018-04-11 12:50:23,699 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 763 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=415, Invalid=3007, Unknown=0, NotChecked=0, Total=3422 [2018-04-11 12:50:23,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-04-11 12:50:23,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 149. [2018-04-11 12:50:23,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-04-11 12:50:23,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 160 transitions. [2018-04-11 12:50:23,700 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 160 transitions. Word has length 62 [2018-04-11 12:50:23,700 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:50:23,700 INFO L459 AbstractCegarLoop]: Abstraction has 149 states and 160 transitions. [2018-04-11 12:50:23,700 INFO L460 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-04-11 12:50:23,701 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 160 transitions. [2018-04-11 12:50:23,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-04-11 12:50:23,701 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:50:23,701 INFO L355 BasicCegarLoop]: trace histogram [7, 7, 6, 5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:50:23,701 INFO L408 AbstractCegarLoop]: === Iteration 61 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:50:23,701 INFO L82 PathProgramCache]: Analyzing trace with hash 1282161199, now seen corresponding path program 24 times [2018-04-11 12:50:23,701 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:50:23,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:50:23,710 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:50:24,892 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 109 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:50:24,892 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:50:24,892 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-04-11 12:50:24,892 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:50:24,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:50:24,893 INFO L182 omatonBuilderFactory]: Interpolants [16896#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|)) (= main_~nondetString1~0.offset 0)), 16897#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 16898#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 16899#(and (= 0 main_~nondetString2~0.offset) (or (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))))) (+ main_~nondetString1~0.offset (- 1))))) (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 1) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (<= 5 (+ main_~nondetString2~0.offset (div (+ (select |#length| main_~nondetString2~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset (- 1)))) 2))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (div (+ (select |#length| main_~nondetString2~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset (- 1)))) 2) (+ main_~nondetString2~0.offset (- 1)))))) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1))))))) (= main_~nondetString1~0.offset 0)), 16900#(and (or (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (div (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) 2) (- 1)))) (<= 5 (div (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) 2)) (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 1) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))))) (- 1))))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 5) (select |#length| |cstrcat_#in~s1.base|)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s2.offset|) (= 0 |cstrcat_#in~s1.offset|)), 16901#(and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (<= 5 (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2) (- 1))))) (or (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 16902#(and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (<= 5 (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (- 1)) 2) (- 1))))) (or (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 16903#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 2))) 2) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1)))) (- 1))))) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ cstrcat_~s~0.offset 4) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 2))) 2)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1)))) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))) (= 0 cstrcat_~s2.offset)), 16904#(and (= 0 cstrcat_~s2.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 2))) 2) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1)))) (- 1))))) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ cstrcat_~s~0.offset 4) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 2))) 2)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1)))) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset)) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))), 16905#(and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 2)))) (- 2))))) (+ cstrcat_~s~0.offset (- 2)))) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 2)))) (- 2)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))))), 16906#(and (or (= |cstrcat_#t~mem2| 0) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 2)))) (- 2))))) (+ cstrcat_~s~0.offset (- 2)))) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 3))) 2) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 2)))) (- 2)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))))) (= 0 cstrcat_~s2.offset)), 16907#(and (= 0 cstrcat_~s2.offset) (or (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 2)) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 5)) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 16908#(and (= 0 cstrcat_~s2.offset) (or (= |cstrcat_#t~mem2| 0) (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 2)) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 5)) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))))), 16909#(and (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= 0 cstrcat_~s2.offset)), 16910#(and (= 0 cstrcat_~s2.offset) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem2| 0) (<= (select |#length| cstrcat_~s2.base) 4))), 16911#(and (= 0 cstrcat_~s2.offset) (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (<= (select |#length| cstrcat_~s2.base) 4))), 16912#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 4) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 16913#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) (+ cstrcat_~s2.offset 3)) (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~post5.offset| 0) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)), 16914#(and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 3)))), 16915#(and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 3))) (<= 1 cstrcat_~s~0.offset)), 16916#(and (<= 2 cstrcat_~s~0.offset) (or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 2)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 16917#(and (<= 3 cstrcat_~s~0.offset) (or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 16918#(and (or (<= (+ |cstrcat_#t~post4.offset| 2) (select |#length| |cstrcat_#t~post4.base|)) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)) (<= (+ (select |#length| |cstrcat_#t~post4.base|) cstrcat_~s~0.offset) (+ |cstrcat_#t~post4.offset| (select |#length| cstrcat_~s~0.base) 1)) (<= 4 cstrcat_~s~0.offset)), 16919#(or (and (<= 4 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 16920#(or (and (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)) (<= 4 |cstrcat_#t~post4.offset|)) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 16921#(and (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)) (<= 4 |cstrcat_#t~post4.offset|)), 16890#true, 16891#false, 16892#(<= 1 main_~length3~0), 16893#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 16894#(and (= 1 (select |#valid| |main_#t~malloc10.base|)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|))), 16895#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= 1 (select |#valid| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0))] [2018-04-11 12:50:24,893 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 109 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:50:24,893 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-11 12:50:24,893 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-11 12:50:24,893 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=86, Invalid=906, Unknown=0, NotChecked=0, Total=992 [2018-04-11 12:50:24,893 INFO L87 Difference]: Start difference. First operand 149 states and 160 transitions. Second operand 32 states. [2018-04-11 12:50:26,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:50:26,263 INFO L93 Difference]: Finished difference Result 186 states and 197 transitions. [2018-04-11 12:50:26,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-04-11 12:50:26,263 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 63 [2018-04-11 12:50:26,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:50:26,264 INFO L225 Difference]: With dead ends: 186 [2018-04-11 12:50:26,264 INFO L226 Difference]: Without dead ends: 186 [2018-04-11 12:50:26,264 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 513 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=245, Invalid=2205, Unknown=0, NotChecked=0, Total=2450 [2018-04-11 12:50:26,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-04-11 12:50:26,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 154. [2018-04-11 12:50:26,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-04-11 12:50:26,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 165 transitions. [2018-04-11 12:50:26,266 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 165 transitions. Word has length 63 [2018-04-11 12:50:26,266 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:50:26,266 INFO L459 AbstractCegarLoop]: Abstraction has 154 states and 165 transitions. [2018-04-11 12:50:26,266 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-11 12:50:26,267 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 165 transitions. [2018-04-11 12:50:26,267 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-04-11 12:50:26,267 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:50:26,267 INFO L355 BasicCegarLoop]: trace histogram [12, 12, 11, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:50:26,268 INFO L408 AbstractCegarLoop]: === Iteration 62 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:50:26,268 INFO L82 PathProgramCache]: Analyzing trace with hash 253964195, now seen corresponding path program 25 times [2018-04-11 12:50:26,268 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:50:26,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:50:26,288 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:50:27,326 WARN L151 SmtUtils]: Spent 275ms on a formula simplification. DAG size of input: 371 DAG size of output 96 [2018-04-11 12:50:27,578 WARN L151 SmtUtils]: Spent 224ms on a formula simplification. DAG size of input: 298 DAG size of output 81 [2018-04-11 12:50:27,896 WARN L151 SmtUtils]: Spent 285ms on a formula simplification. DAG size of input: 298 DAG size of output 81 [2018-04-11 12:50:28,198 WARN L151 SmtUtils]: Spent 220ms on a formula simplification. DAG size of input: 300 DAG size of output 81 [2018-04-11 12:50:28,491 WARN L151 SmtUtils]: Spent 248ms on a formula simplification. DAG size of input: 312 DAG size of output 84 [2018-04-11 12:50:28,784 WARN L151 SmtUtils]: Spent 245ms on a formula simplification. DAG size of input: 314 DAG size of output 84 [2018-04-11 12:50:28,990 WARN L151 SmtUtils]: Spent 165ms on a formula simplification. DAG size of input: 210 DAG size of output 74 [2018-04-11 12:50:29,200 WARN L151 SmtUtils]: Spent 165ms on a formula simplification. DAG size of input: 212 DAG size of output 74 [2018-04-11 12:50:29,365 WARN L151 SmtUtils]: Spent 131ms on a formula simplification. DAG size of input: 130 DAG size of output 68 [2018-04-11 12:50:29,532 WARN L151 SmtUtils]: Spent 128ms on a formula simplification. DAG size of input: 132 DAG size of output 68 [2018-04-11 12:50:30,660 INFO L134 CoverageAnalysis]: Checked inductivity of 202 backedges. 0 proven. 202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:50:30,660 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:50:30,660 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37] total 37 [2018-04-11 12:50:30,660 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:50:30,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:50:30,661 INFO L182 omatonBuilderFactory]: Interpolants [17298#true, 17299#false, 17300#(<= 1 main_~length3~0), 17301#(and (or (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (< 12 main_~length2~0)) (<= 1 main_~length3~0)), 17302#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (or (< 12 main_~length2~0) (and (= 1 (select |#valid| |main_#t~malloc10.base|)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|))))), 17303#(and (= 0 main_~nondetString1~0.offset) (or (< 12 main_~length2~0) (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 1 (select |#valid| main_~nondetString1~0.base)))) (<= 1 main_~length3~0)), 17304#(and (= 0 main_~nondetString1~0.offset) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (or (and (<= (+ main_~length3~0 main_~length1~0) 12) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))) (<= 13 (select |#length| |main_#t~malloc11.base|)))), 17305#(and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~length3~0) (or (<= 13 (select |#length| main_~nondetString2~0.base)) (and (<= (+ main_~length3~0 main_~length1~0) 12) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= 0 main_~nondetString2~0.offset)), 17306#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~length3~0) (or (<= 13 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) 12))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1))), 17307#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 6)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (+ main_~nondetString2~0.offset (- 1)))))) (<= 13 (select |#length| main_~nondetString2~0.base)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) (+ main_~nondetString2~0.offset (- 1))))) (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 5))) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 7)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 8)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 3)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 9)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 4)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) 12) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 2)) (or (<= (select |#length| main_~nondetString1~0.base) (+ main_~nondetString2~0.offset 1)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 3) 1) (- 1))))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 17308#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (and (<= (select |#length| |cstrcat_#in~s2.base|) 7) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 3) (- 1)))) (<= (select |#length| |cstrcat_#in~s2.base|) 3)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) 12) (- 1)))) (<= (select |#length| |cstrcat_#in~s2.base|) 4)) (and (<= (select |#length| |cstrcat_#in~s2.base|) 5) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 2) (- 1))))) (and (<= (select |#length| |cstrcat_#in~s2.base|) 9) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (and (<= (select |#length| |cstrcat_#in~s2.base|) 2) (or (<= (select |#length| |cstrcat_#in~s2.base|) 1) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 5 3) 1) (- 1)))))) (and (<= (select |#length| |cstrcat_#in~s2.base|) 8) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (<= 13 (select |#length| |cstrcat_#in~s1.base|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 1) (- 1)))) (<= (select |#length| |cstrcat_#in~s2.base|) 6))) (= 0 |cstrcat_#in~s2.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 17309#(and (= cstrcat_~s~0.offset 0) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 8) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 9) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 7) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 3) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 3)) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) 12) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 3) 1) (- 1)))))) (<= 13 (select |#length| cstrcat_~s~0.base)))))), 17310#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 8) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 9) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 7) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 3) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 3)) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) 12) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 3) 1) (- 1)))))) (<= 13 (select |#length| cstrcat_~s~0.base))))) (= cstrcat_~s~0.offset 0)), 17311#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 2) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 3) 1) (- 1)))))) (and (<= (select |#length| cstrcat_~s2.base) 7) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 9) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 11)) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 3) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 8) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (+ cstrcat_~s~0.offset 12) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1)))))))) (= cstrcat_~s~0.offset 1)), 17312#(and (or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 2) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 3) 1) (- 1)))))) (and (<= (select |#length| cstrcat_~s2.base) 7) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 9) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 11)) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 3) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 8) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (+ cstrcat_~s~0.offset 12) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1)))))))) (= cstrcat_~s~0.offset 1)), 17313#(and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 7) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 8) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 5)) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 3) 1) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 1))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 3) (- 1))))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 10)) (- 1))))))), 17314#(and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 7) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 8) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 5)) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 3) 1) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 1))) (= |cstrcat_#t~mem2| 0) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 3) (- 1))))) (<= (+ cstrcat_~s~0.offset 11) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 10)) (- 1))))))), 17315#(or (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 9)) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 5) 1) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 1))) (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 7) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 5) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 17316#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 9)) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 5) 1) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 1))) (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 7) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 5) (- 1)))))))), 17317#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1)))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 8)) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 4))) (= 0 cstrcat_~s2.offset))), 17318#(or (= |cstrcat_#t~mem2| 0) (and (or (and (<= (select |#length| cstrcat_~s2.base) 6) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1)))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 8)) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 4))) (= 0 cstrcat_~s2.offset))), 17319#(or (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 2) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 1))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 7)) (- 1))))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 17320#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 2) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (select |#length| cstrcat_~s2.base) 1))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 7)) (- 1))))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 5) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))))), 17321#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 6)) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2))))), 17322#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 4) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 6)) (- 1))))) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2))))), 17323#(or (and (or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 5)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2))) (= 0 cstrcat_~s2.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 17324#(or (and (or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (select |#length| cstrcat_~s2.base)) 5)) (- 1))))) (<= (select |#length| cstrcat_~s2.base) 2))) (= 0 cstrcat_~s2.offset)) (= |cstrcat_#t~mem2| 0)), 17325#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 cstrcat_~s2.offset) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 4)) (- 1))))))))), 17326#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 2) (or (<= (select |#length| cstrcat_~s2.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ cstrcat_~s~0.offset 4)) (- 1))))))))), 17327#(or (and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 1) (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 17328#(or (= |cstrcat_#t~mem2| 0) (and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 1) (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))))), 17329#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 1) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 17330#(and (or (<= (select |#length| cstrcat_~s2.base) 1) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= 0 cstrcat_~s2.offset)), 17331#(and (or (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| |cstrcat_#t~post5.base|) 1)) (<= (+ |cstrcat_#t~post5.offset| 1) cstrcat_~s2.offset) (= |cstrcat_#t~post5.offset| 0) (= |cstrcat_#t~post5.base| cstrcat_~s2.base)), 17332#(or (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 17333#(or (and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 17334#(or (and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 17335#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:50:30,661 INFO L134 CoverageAnalysis]: Checked inductivity of 202 backedges. 0 proven. 202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:50:30,661 INFO L442 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-04-11 12:50:30,662 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-04-11 12:50:30,662 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=1321, Unknown=0, NotChecked=0, Total=1406 [2018-04-11 12:50:30,662 INFO L87 Difference]: Start difference. First operand 154 states and 165 transitions. Second operand 38 states. [2018-04-11 12:50:31,116 WARN L151 SmtUtils]: Spent 114ms on a formula simplification. DAG size of input: 132 DAG size of output 130 [2018-04-11 12:50:31,696 WARN L151 SmtUtils]: Spent 152ms on a formula simplification. DAG size of input: 159 DAG size of output 157 [2018-04-11 12:50:33,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:50:33,935 INFO L93 Difference]: Finished difference Result 187 states and 198 transitions. [2018-04-11 12:50:33,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-04-11 12:50:33,935 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 63 [2018-04-11 12:50:33,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:50:33,936 INFO L225 Difference]: With dead ends: 187 [2018-04-11 12:50:33,936 INFO L226 Difference]: Without dead ends: 187 [2018-04-11 12:50:33,936 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 751 ImplicationChecksByTransitivity, 6.0s TimeCoverageRelationStatistics Valid=244, Invalid=4046, Unknown=0, NotChecked=0, Total=4290 [2018-04-11 12:50:33,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states. [2018-04-11 12:50:33,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 154. [2018-04-11 12:50:33,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-04-11 12:50:33,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 165 transitions. [2018-04-11 12:50:33,938 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 165 transitions. Word has length 63 [2018-04-11 12:50:33,938 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:50:33,938 INFO L459 AbstractCegarLoop]: Abstraction has 154 states and 165 transitions. [2018-04-11 12:50:33,938 INFO L460 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-04-11 12:50:33,938 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 165 transitions. [2018-04-11 12:50:33,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-04-11 12:50:33,939 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:50:33,939 INFO L355 BasicCegarLoop]: trace histogram [9, 9, 8, 4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:50:33,939 INFO L408 AbstractCegarLoop]: === Iteration 63 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:50:33,939 INFO L82 PathProgramCache]: Analyzing trace with hash -39551703, now seen corresponding path program 26 times [2018-04-11 12:50:33,939 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:50:33,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:50:33,956 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:50:34,394 WARN L151 SmtUtils]: Spent 125ms on a formula simplification. DAG size of input: 108 DAG size of output 69 [2018-04-11 12:50:34,540 WARN L151 SmtUtils]: Spent 133ms on a formula simplification. DAG size of input: 100 DAG size of output 64 [2018-04-11 12:50:34,679 WARN L151 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 100 DAG size of output 64 [2018-04-11 12:50:34,826 WARN L151 SmtUtils]: Spent 129ms on a formula simplification. DAG size of input: 102 DAG size of output 64 [2018-04-11 12:50:34,952 WARN L151 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 113 DAG size of output 65 [2018-04-11 12:50:35,082 WARN L151 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 115 DAG size of output 65 [2018-04-11 12:50:35,827 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 0 proven. 135 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:50:35,827 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:50:35,827 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33] total 33 [2018-04-11 12:50:35,827 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:50:35,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:50:35,827 INFO L182 omatonBuilderFactory]: Interpolants [17733#true, 17734#false, 17735#(<= 1 main_~length3~0), 17736#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 17737#(and (= 1 (select |#valid| |main_#t~malloc10.base|)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= main_~length1~0 (select |#length| |main_#t~malloc10.base|))), 17738#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= 1 (select |#valid| main_~nondetString1~0.base))), 17739#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= 0 |main_#t~malloc11.offset|) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc11.base|))), 17740#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)), 17741#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))), 17742#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (or (<= (+ (select |#length| main_~nondetString1~0.base) 8) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 4) 1) (+ main_~nondetString2~0.offset (- 1)))))) (<= (+ (select |#length| main_~nondetString1~0.base) 7) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 6) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ (- (select |#length| main_~nondetString1~0.base)) (- 1))) (+ main_~nondetString2~0.offset (- 1)))))))), 17743#(and (or (and (or (<= (+ (select |#length| |cstrcat_#in~s2.base|) 8) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 4 1) (- 1))))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 7) (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) (+ (select |#length| |cstrcat_#in~s1.base|) (- 1))) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 5) (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 6) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) (select |#length| |cstrcat_#in~s1.base|)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s2.offset|) (= 0 |cstrcat_#in~s1.offset|)), 17744#(and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (select |#length| cstrcat_~s2.base) 7) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 4 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 8) (select |#length| cstrcat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 6) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 0)), 17745#(and (or (and (<= (+ (select |#length| cstrcat_~s2.base) 7) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 4 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 8) (select |#length| cstrcat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 6) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= 0 cstrcat_~s2.offset) (= cstrcat_~s~0.offset 0)), 17746#(and (= 0 cstrcat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (= 1 cstrcat_~s~0.offset) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)))))), 17747#(and (= 0 cstrcat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (= |cstrcat_#t~mem2| 0) (= 1 cstrcat_~s~0.offset)) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)))))), 17748#(and (or (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))) (= 0 cstrcat_~s2.offset)), 17749#(and (or (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)))) (= |cstrcat_#t~mem2| 0) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))) (= 0 cstrcat_~s2.offset)), 17750#(and (= 0 cstrcat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 17751#(and (or (= |cstrcat_#t~mem2| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (select |#length| cstrcat_~s2.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))))) (= 0 cstrcat_~s2.offset)), 17752#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))), 17753#(or (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem2| 0) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset)) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))), 17754#(or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)))), 17755#(or (= |cstrcat_#t~mem2| 0) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset)) (and (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)))), 17756#(or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 17757#(or (= |cstrcat_#t~mem2| 0) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset))), 17758#(or (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))), 17759#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (and (<= (select |#length| cstrcat_~s2.base) 3) (= 0 cstrcat_~s2.offset))), 17760#(or (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (and (<= (+ |cstrcat_#t~post5.offset| (select |#length| |cstrcat_#t~post5.base|)) (+ cstrcat_~s2.offset 2)) (= |cstrcat_#t~post5.offset| 0) (= |cstrcat_#t~post5.base| cstrcat_~s2.base))), 17761#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 2)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 17762#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 17763#(or (and (<= (+ |cstrcat_#t~post4.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 17764#(or (and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 17765#(or (and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|))) (<= (select |#length| |cstrcat_#t~post5.base|) |cstrcat_#t~post5.offset|)), 17766#(and (<= 1 |cstrcat_#t~post4.offset|) (<= (+ |cstrcat_#t~post4.offset| 1) (select |#length| |cstrcat_#t~post4.base|)))] [2018-04-11 12:50:35,828 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 0 proven. 135 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:50:35,828 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-04-11 12:50:35,828 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-04-11 12:50:35,828 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=1015, Unknown=0, NotChecked=0, Total=1122 [2018-04-11 12:50:35,828 INFO L87 Difference]: Start difference. First operand 154 states and 165 transitions. Second operand 34 states. [2018-04-11 12:50:36,480 WARN L151 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 122 DAG size of output 121 [2018-04-11 12:50:36,751 WARN L151 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 126 DAG size of output 125 [2018-04-11 12:50:36,999 WARN L151 SmtUtils]: Spent 107ms on a formula simplification. DAG size of input: 119 DAG size of output 118 [2018-04-11 12:50:37,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:50:37,733 INFO L93 Difference]: Finished difference Result 211 states and 222 transitions. [2018-04-11 12:50:37,733 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-04-11 12:50:37,734 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 64 [2018-04-11 12:50:37,734 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:50:37,734 INFO L225 Difference]: With dead ends: 211 [2018-04-11 12:50:37,734 INFO L226 Difference]: Without dead ends: 211 [2018-04-11 12:50:37,734 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 676 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=361, Invalid=2719, Unknown=0, NotChecked=0, Total=3080 [2018-04-11 12:50:37,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states. [2018-04-11 12:50:37,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 154. [2018-04-11 12:50:37,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-04-11 12:50:37,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 165 transitions. [2018-04-11 12:50:37,736 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 165 transitions. Word has length 64 [2018-04-11 12:50:37,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:50:37,736 INFO L459 AbstractCegarLoop]: Abstraction has 154 states and 165 transitions. [2018-04-11 12:50:37,736 INFO L460 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-04-11 12:50:37,736 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 165 transitions. [2018-04-11 12:50:37,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-04-11 12:50:37,736 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:50:37,737 INFO L355 BasicCegarLoop]: trace histogram [16, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:50:37,737 INFO L408 AbstractCegarLoop]: === Iteration 64 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation]=== [2018-04-11 12:50:37,737 INFO L82 PathProgramCache]: Analyzing trace with hash -1864189780, now seen corresponding path program 14 times [2018-04-11 12:50:37,737 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:50:37,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:50:37,748 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:50:44,409 WARN L151 SmtUtils]: Spent 2287ms on a formula simplification. DAG size of input: 1570 DAG size of output 111 [2018-04-11 12:50:46,685 WARN L151 SmtUtils]: Spent 2142ms on a formula simplification. DAG size of input: 1261 DAG size of output 102 [2018-04-11 12:50:48,921 WARN L151 SmtUtils]: Spent 2071ms on a formula simplification. DAG size of input: 1261 DAG size of output 102 [2018-04-11 12:50:51,098 WARN L151 SmtUtils]: Spent 2020ms on a formula simplification. DAG size of input: 1263 DAG size of output 102 [2018-04-11 12:50:53,388 WARN L151 SmtUtils]: Spent 2106ms on a formula simplification. DAG size of input: 1283 DAG size of output 113 [2018-04-11 12:50:55,718 WARN L151 SmtUtils]: Spent 2125ms on a formula simplification. DAG size of input: 1285 DAG size of output 113 [2018-04-11 12:50:57,118 WARN L151 SmtUtils]: Spent 1256ms on a formula simplification. DAG size of input: 860 DAG size of output 104 [2018-04-11 12:50:58,465 WARN L151 SmtUtils]: Spent 1202ms on a formula simplification. DAG size of input: 862 DAG size of output 104 [2018-04-11 12:50:59,253 WARN L151 SmtUtils]: Spent 663ms on a formula simplification. DAG size of input: 625 DAG size of output 95 [2018-04-11 12:51:00,068 WARN L151 SmtUtils]: Spent 686ms on a formula simplification. DAG size of input: 627 DAG size of output 95 [2018-04-11 12:51:00,604 WARN L151 SmtUtils]: Spent 434ms on a formula simplification. DAG size of input: 428 DAG size of output 88 Received shutdown request... [2018-04-11 12:51:00,758 WARN L519 AbstractCegarLoop]: Verification canceled [2018-04-11 12:51:00,760 WARN L197 ceAbstractionStarter]: Timeout [2018-04-11 12:51:00,761 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 11.04 12:51:00 BoogieIcfgContainer [2018-04-11 12:51:00,761 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-04-11 12:51:00,761 INFO L168 Benchmark]: Toolchain (without parser) took 177760.37 ms. Allocated memory was 403.7 MB in the beginning and 2.2 GB in the end (delta: 1.8 GB). Free memory was 337.3 MB in the beginning and 1.8 GB in the end (delta: -1.5 GB). Peak memory consumption was 330.0 MB. Max. memory is 5.3 GB. [2018-04-11 12:51:00,762 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 403.7 MB. Free memory is still 364.1 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-04-11 12:51:00,762 INFO L168 Benchmark]: CACSL2BoogieTranslator took 249.99 ms. Allocated memory is still 403.7 MB. Free memory was 336.0 MB in the beginning and 312.1 MB in the end (delta: 23.9 MB). Peak memory consumption was 23.9 MB. Max. memory is 5.3 GB. [2018-04-11 12:51:00,762 INFO L168 Benchmark]: Boogie Preprocessor took 38.58 ms. Allocated memory is still 403.7 MB. Free memory was 312.1 MB in the beginning and 309.5 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. [2018-04-11 12:51:00,763 INFO L168 Benchmark]: RCFGBuilder took 357.53 ms. Allocated memory was 403.7 MB in the beginning and 583.5 MB in the end (delta: 179.8 MB). Free memory was 309.5 MB in the beginning and 519.3 MB in the end (delta: -209.9 MB). Peak memory consumption was 23.2 MB. Max. memory is 5.3 GB. [2018-04-11 12:51:00,763 INFO L168 Benchmark]: TraceAbstraction took 177111.55 ms. Allocated memory was 583.5 MB in the beginning and 2.2 GB in the end (delta: 1.7 GB). Free memory was 519.3 MB in the beginning and 1.8 GB in the end (delta: -1.3 GB). Peak memory consumption was 332.2 MB. Max. memory is 5.3 GB. [2018-04-11 12:51:00,764 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 403.7 MB. Free memory is still 364.1 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 249.99 ms. Allocated memory is still 403.7 MB. Free memory was 336.0 MB in the beginning and 312.1 MB in the end (delta: 23.9 MB). Peak memory consumption was 23.9 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 38.58 ms. Allocated memory is still 403.7 MB. Free memory was 312.1 MB in the beginning and 309.5 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 357.53 ms. Allocated memory was 403.7 MB in the beginning and 583.5 MB in the end (delta: 179.8 MB). Free memory was 309.5 MB in the beginning and 519.3 MB in the end (delta: -209.9 MB). Peak memory consumption was 23.2 MB. Max. memory is 5.3 GB. * TraceAbstraction took 177111.55 ms. Allocated memory was 583.5 MB in the beginning and 2.2 GB in the end (delta: 1.7 GB). Free memory was 519.3 MB in the beginning and 1.8 GB in the end (delta: -1.3 GB). Peak memory consumption was 332.2 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 543]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 543). Cancelled while BasicCegarLoop was analyzing trace of length 66 with TraceHistMax 16, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 430. - TimeoutResultAtElement [Line: 545]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 66 with TraceHistMax 16, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 430. - TimeoutResultAtElement [Line: 543]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 543). Cancelled while BasicCegarLoop was analyzing trace of length 66 with TraceHistMax 16, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 430. - TimeoutResultAtElement [Line: 545]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 66 with TraceHistMax 16, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 430. - TimeoutResultAtElement [Line: 545]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 66 with TraceHistMax 16, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 430. - TimeoutResultAtElement [Line: 545]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 66 with TraceHistMax 16, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 430. - TimeoutResultAtElement [Line: 566]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 566). Cancelled while BasicCegarLoop was analyzing trace of length 66 with TraceHistMax 16, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 430. - TimeoutResultAtElement [Line: 565]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 565). Cancelled while BasicCegarLoop was analyzing trace of length 66 with TraceHistMax 16, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 430. - TimeoutResultAtElement [Line: 566]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 566). Cancelled while BasicCegarLoop was analyzing trace of length 66 with TraceHistMax 16, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 430. - TimeoutResultAtElement [Line: 549]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 549). Cancelled while BasicCegarLoop was analyzing trace of length 66 with TraceHistMax 16, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 430. - TimeoutResultAtElement [Line: 565]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 565). Cancelled while BasicCegarLoop was analyzing trace of length 66 with TraceHistMax 16, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 430. - StatisticsResult: Ultimate Automizer benchmark data CFG has 6 procedures, 55 locations, 11 error locations. TIMEOUT Result, 177.0s OverallTime, 64 OverallIterations, 16 TraceHistogramMax, 67.5s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1760 SDtfs, 4457 SDslu, 18752 SDs, 0 SdLazy, 24666 SolverSat, 1588 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 12.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2130 GetRequests, 90 SyntacticMatches, 1 SemanticMatches, 2039 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16677 ImplicationChecksByTransitivity, 124.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=182occurred in iteration=26, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 70/3857 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 63 MinimizatonAttempts, 1284 StatesRemovedByMinimization, 57 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 84.7s InterpolantComputationTime, 2507 NumberOfCodeBlocks, 2507 NumberOfCodeBlocksAsserted, 63 NumberOfCheckSat, 2444 ConstructedInterpolants, 0 QuantifiedInterpolants, 4666238 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 63 InterpolantComputations, 18 PerfectInterpolantSequences, 70/3857 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrcat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-Benchmark-0-2018-04-11_12-51-00-769.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrcat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-04-11_12-51-00-769.csv Completed graceful shutdown