java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv --cacsl2boogietranslator.bitprecise.bitfields false -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf -i ../../../trunk/examples/svcomp/array-memsafety/cstrncat-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-666feb3-m [2018-04-11 12:51:09,969 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-04-11 12:51:09,970 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-04-11 12:51:09,980 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-04-11 12:51:09,980 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-04-11 12:51:09,980 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-04-11 12:51:09,981 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-04-11 12:51:09,982 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-04-11 12:51:09,984 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-04-11 12:51:09,984 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-04-11 12:51:09,985 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-04-11 12:51:09,985 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-04-11 12:51:09,985 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-04-11 12:51:09,986 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-04-11 12:51:09,986 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-04-11 12:51:09,987 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-04-11 12:51:09,989 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-04-11 12:51:09,989 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-04-11 12:51:09,990 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-04-11 12:51:09,991 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-04-11 12:51:09,992 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-04-11 12:51:09,996 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf [2018-04-11 12:51:10,015 INFO L110 SettingsManager]: Loading preferences was successful [2018-04-11 12:51:10,016 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-04-11 12:51:10,017 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-04-11 12:51:10,017 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-04-11 12:51:10,017 INFO L133 SettingsManager]: * Use SBE=true [2018-04-11 12:51:10,018 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-04-11 12:51:10,018 INFO L133 SettingsManager]: * sizeof long=4 [2018-04-11 12:51:10,018 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-04-11 12:51:10,018 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-04-11 12:51:10,018 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-04-11 12:51:10,019 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-04-11 12:51:10,019 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-04-11 12:51:10,019 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-04-11 12:51:10,019 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-04-11 12:51:10,019 INFO L133 SettingsManager]: * sizeof long double=12 [2018-04-11 12:51:10,019 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-04-11 12:51:10,020 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-04-11 12:51:10,020 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-04-11 12:51:10,020 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-04-11 12:51:10,020 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-11 12:51:10,020 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-04-11 12:51:10,020 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_TreeInterpolation Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Bitprecise bitfields -> false [2018-04-11 12:51:10,050 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-04-11 12:51:10,058 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully (re)initialized [2018-04-11 12:51:10,061 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-04-11 12:51:10,062 INFO L271 PluginConnector]: Initializing CDTParser... [2018-04-11 12:51:10,062 INFO L276 PluginConnector]: CDTParser initialized [2018-04-11 12:51:10,063 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,432 INFO L225 CDTParser]: Created temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAG5bc8d44a7 [2018-04-11 12:51:10,561 INFO L287 CDTParser]: IsIndexed: true [2018-04-11 12:51:10,561 INFO L288 CDTParser]: Found 1 translation units. [2018-04-11 12:51:10,562 INFO L168 CDTParser]: Scanning cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,569 INFO L210 ultiparseSymbolTable]: Include resolver: [2018-04-11 12:51:10,569 INFO L215 ultiparseSymbolTable]: [2018-04-11 12:51:10,569 INFO L218 ultiparseSymbolTable]: Function table: [2018-04-11 12:51:10,570 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____bswap_64 ('__bswap_64') in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,570 INFO L221 ultiparseSymbolTable]: Function definition of null ('main') in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,570 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____bswap_32 ('__bswap_32') in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,570 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__ ('') in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,570 INFO L227 ultiparseSymbolTable]: Global variable table: [2018-04-11 12:51:10,570 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__u_quad_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,570 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____u_char in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,571 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____off64_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,571 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__u_int32_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,571 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__pthread_key_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,571 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____id_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,571 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__sigset_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,571 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____syscall_ulong_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,571 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____rlim64_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,571 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____blksize_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,571 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____uint32_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,571 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__blksize_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,571 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____u_long in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,571 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____qaddr_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,571 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__fsblkcnt_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,571 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____int32_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,572 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__ulong in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,572 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__daddr_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,572 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__clock_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,572 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____dev_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,572 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__key_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,572 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__pthread_rwlockattr_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,572 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__mode_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,572 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__u_long in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,572 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____u_short in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,572 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____off_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,572 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____caddr_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,572 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__fd_set in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,572 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__size_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,572 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__pthread_barrier_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,572 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____intptr_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,573 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____u_quad_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,573 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____pid_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,573 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____ino_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,573 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__pthread_mutexattr_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,573 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____quad_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,573 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____fsid_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,573 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__u_int in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,573 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__pthread_cond_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,573 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__caddr_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,573 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____sigset_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,573 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____gid_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,574 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__pthread_spinlock_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,574 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____mode_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,574 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____timer_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,574 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__off_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,574 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____int16_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,574 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__div_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,574 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__u_char in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,574 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____clockid_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,574 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__u_int16_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,575 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__quad_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,575 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____suseconds_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,575 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__blkcnt_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,575 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__lldiv_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,575 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____pthread_list_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,575 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____socklen_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,575 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__uid_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,575 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__int16_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,575 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__wchar_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,576 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____rlim_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,576 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____uid_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,576 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__pthread_attr_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,576 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____sig_atomic_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,576 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__ssize_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,576 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____fsblkcnt64_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,576 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____fd_mask in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,576 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__pthread_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,576 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__id_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,576 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__pthread_condattr_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,576 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__pthread_once_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,576 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__u_short in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,576 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__gid_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,576 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____nlink_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,577 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____clock_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,577 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__u_int8_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,577 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__clockid_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,577 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__uint in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,577 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____int8_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,577 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__int32_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,577 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__nlink_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,577 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__pid_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,577 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__fsfilcnt_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,577 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__timer_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,577 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____ssize_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,578 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____uint64_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,578 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____fsword_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,578 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____blkcnt64_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,578 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__suseconds_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,578 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__fd_mask in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,578 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____syscall_slong_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,578 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__ushort in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,578 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____ino64_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,578 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____loff_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,578 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____time_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,578 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__int8_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,578 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____uint16_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,579 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____blkcnt_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,579 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__fsid_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,579 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____fsfilcnt_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,579 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____daddr_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,579 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____WAIT_STATUS in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,579 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__int64_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,579 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____uint8_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,579 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____key_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,579 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__dev_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,579 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__ldiv_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,579 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__u_int64_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,580 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__loff_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,580 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__pthread_rwlock_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,580 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____u_int in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,580 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__time_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,580 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__ino_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,580 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__pthread_barrierattr_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,580 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____fsblkcnt_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,580 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____int64_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,580 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____useconds_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,580 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__register_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,580 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i__pthread_mutex_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,581 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____fsfilcnt64_t in cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:10,595 INFO L330 CDTParser]: Deleted temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAG5bc8d44a7 [2018-04-11 12:51:10,602 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-04-11 12:51:10,603 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-04-11 12:51:10,604 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-04-11 12:51:10,604 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-04-11 12:51:10,608 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-04-11 12:51:10,609 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 11.04 12:51:10" (1/1) ... [2018-04-11 12:51:10,611 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@65e7e3d3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:51:10, skipping insertion in model container [2018-04-11 12:51:10,611 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 11.04 12:51:10" (1/1) ... [2018-04-11 12:51:10,624 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-11 12:51:10,650 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-11 12:51:10,785 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-11 12:51:10,813 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-11 12:51:10,819 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-11 12:51:10,851 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:51:10 WrapperNode [2018-04-11 12:51:10,851 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-04-11 12:51:10,852 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-04-11 12:51:10,852 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-04-11 12:51:10,852 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-04-11 12:51:10,863 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:51:10" (1/1) ... [2018-04-11 12:51:10,863 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:51:10" (1/1) ... [2018-04-11 12:51:10,871 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:51:10" (1/1) ... [2018-04-11 12:51:10,871 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:51:10" (1/1) ... [2018-04-11 12:51:10,876 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:51:10" (1/1) ... [2018-04-11 12:51:10,879 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:51:10" (1/1) ... [2018-04-11 12:51:10,881 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:51:10" (1/1) ... [2018-04-11 12:51:10,884 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-04-11 12:51:10,884 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-04-11 12:51:10,884 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-04-11 12:51:10,884 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-04-11 12:51:10,885 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:51:10" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-11 12:51:10,965 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-04-11 12:51:10,965 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-04-11 12:51:10,965 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-11 12:51:10,965 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-11 12:51:10,965 INFO L136 BoogieDeclarations]: Found implementation of procedure cstrncat [2018-04-11 12:51:10,965 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-04-11 12:51:10,965 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fcstrncat_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure __ctype_get_mb_cur_max [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure atof [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure atoi [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure atol [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure atoll [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure strtod [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure strtof [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure strtold [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure strtol [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure strtoul [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure strtoq [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure strtouq [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure strtoll [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure strtoull [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure l64a [2018-04-11 12:51:10,966 INFO L128 BoogieDeclarations]: Found specification of procedure a64l [2018-04-11 12:51:10,967 INFO L128 BoogieDeclarations]: Found specification of procedure select [2018-04-11 12:51:10,967 INFO L128 BoogieDeclarations]: Found specification of procedure pselect [2018-04-11 12:51:10,967 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_major [2018-04-11 12:51:10,967 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_minor [2018-04-11 12:51:10,967 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_makedev [2018-04-11 12:51:10,967 INFO L128 BoogieDeclarations]: Found specification of procedure random [2018-04-11 12:51:10,967 INFO L128 BoogieDeclarations]: Found specification of procedure srandom [2018-04-11 12:51:10,967 INFO L128 BoogieDeclarations]: Found specification of procedure initstate [2018-04-11 12:51:10,967 INFO L128 BoogieDeclarations]: Found specification of procedure setstate [2018-04-11 12:51:10,968 INFO L128 BoogieDeclarations]: Found specification of procedure random_r [2018-04-11 12:51:10,968 INFO L128 BoogieDeclarations]: Found specification of procedure srandom_r [2018-04-11 12:51:10,968 INFO L128 BoogieDeclarations]: Found specification of procedure initstate_r [2018-04-11 12:51:10,968 INFO L128 BoogieDeclarations]: Found specification of procedure setstate_r [2018-04-11 12:51:10,968 INFO L128 BoogieDeclarations]: Found specification of procedure rand [2018-04-11 12:51:10,968 INFO L128 BoogieDeclarations]: Found specification of procedure srand [2018-04-11 12:51:10,968 INFO L128 BoogieDeclarations]: Found specification of procedure rand_r [2018-04-11 12:51:10,968 INFO L128 BoogieDeclarations]: Found specification of procedure drand48 [2018-04-11 12:51:10,968 INFO L128 BoogieDeclarations]: Found specification of procedure erand48 [2018-04-11 12:51:10,968 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48 [2018-04-11 12:51:10,969 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48 [2018-04-11 12:51:10,969 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48 [2018-04-11 12:51:10,969 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48 [2018-04-11 12:51:10,969 INFO L128 BoogieDeclarations]: Found specification of procedure srand48 [2018-04-11 12:51:10,969 INFO L128 BoogieDeclarations]: Found specification of procedure seed48 [2018-04-11 12:51:10,969 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48 [2018-04-11 12:51:10,969 INFO L128 BoogieDeclarations]: Found specification of procedure drand48_r [2018-04-11 12:51:10,969 INFO L128 BoogieDeclarations]: Found specification of procedure erand48_r [2018-04-11 12:51:10,969 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48_r [2018-04-11 12:51:10,969 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48_r [2018-04-11 12:51:10,969 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48_r [2018-04-11 12:51:10,969 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48_r [2018-04-11 12:51:10,969 INFO L128 BoogieDeclarations]: Found specification of procedure srand48_r [2018-04-11 12:51:10,969 INFO L128 BoogieDeclarations]: Found specification of procedure seed48_r [2018-04-11 12:51:10,970 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48_r [2018-04-11 12:51:10,970 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-04-11 12:51:10,970 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-04-11 12:51:10,970 INFO L128 BoogieDeclarations]: Found specification of procedure realloc [2018-04-11 12:51:10,970 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-04-11 12:51:10,970 INFO L128 BoogieDeclarations]: Found specification of procedure cfree [2018-04-11 12:51:10,970 INFO L128 BoogieDeclarations]: Found specification of procedure alloca [2018-04-11 12:51:10,970 INFO L128 BoogieDeclarations]: Found specification of procedure valloc [2018-04-11 12:51:10,970 INFO L128 BoogieDeclarations]: Found specification of procedure posix_memalign [2018-04-11 12:51:10,970 INFO L128 BoogieDeclarations]: Found specification of procedure abort [2018-04-11 12:51:10,970 INFO L128 BoogieDeclarations]: Found specification of procedure atexit [2018-04-11 12:51:10,970 INFO L128 BoogieDeclarations]: Found specification of procedure on_exit [2018-04-11 12:51:10,970 INFO L128 BoogieDeclarations]: Found specification of procedure exit [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure _Exit [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure getenv [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure putenv [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure setenv [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure unsetenv [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure clearenv [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure mktemp [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemp [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemps [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure mkdtemp [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure system [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure realpath [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure bsearch [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure qsort [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure abs [2018-04-11 12:51:10,971 INFO L128 BoogieDeclarations]: Found specification of procedure labs [2018-04-11 12:51:10,972 INFO L128 BoogieDeclarations]: Found specification of procedure llabs [2018-04-11 12:51:10,972 INFO L128 BoogieDeclarations]: Found specification of procedure div [2018-04-11 12:51:10,972 INFO L128 BoogieDeclarations]: Found specification of procedure ldiv [2018-04-11 12:51:10,972 INFO L128 BoogieDeclarations]: Found specification of procedure lldiv [2018-04-11 12:51:10,972 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt [2018-04-11 12:51:10,972 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt [2018-04-11 12:51:10,972 INFO L128 BoogieDeclarations]: Found specification of procedure gcvt [2018-04-11 12:51:10,972 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt [2018-04-11 12:51:10,972 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt [2018-04-11 12:51:10,972 INFO L128 BoogieDeclarations]: Found specification of procedure qgcvt [2018-04-11 12:51:10,972 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt_r [2018-04-11 12:51:10,972 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt_r [2018-04-11 12:51:10,972 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt_r [2018-04-11 12:51:10,973 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt_r [2018-04-11 12:51:10,973 INFO L128 BoogieDeclarations]: Found specification of procedure mblen [2018-04-11 12:51:10,973 INFO L128 BoogieDeclarations]: Found specification of procedure mbtowc [2018-04-11 12:51:10,973 INFO L128 BoogieDeclarations]: Found specification of procedure wctomb [2018-04-11 12:51:10,973 INFO L128 BoogieDeclarations]: Found specification of procedure mbstowcs [2018-04-11 12:51:10,973 INFO L128 BoogieDeclarations]: Found specification of procedure wcstombs [2018-04-11 12:51:10,973 INFO L128 BoogieDeclarations]: Found specification of procedure rpmatch [2018-04-11 12:51:10,973 INFO L128 BoogieDeclarations]: Found specification of procedure getsubopt [2018-04-11 12:51:10,973 INFO L128 BoogieDeclarations]: Found specification of procedure getloadavg [2018-04-11 12:51:10,973 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-04-11 12:51:10,974 INFO L128 BoogieDeclarations]: Found specification of procedure cstrncat [2018-04-11 12:51:10,974 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-04-11 12:51:10,974 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-04-11 12:51:10,974 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-04-11 12:51:10,974 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-04-11 12:51:10,974 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-04-11 12:51:10,974 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-04-11 12:51:10,974 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-04-11 12:51:10,974 INFO L128 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-04-11 12:51:11,300 INFO L259 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-04-11 12:51:11,301 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.04 12:51:11 BoogieIcfgContainer [2018-04-11 12:51:11,301 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-04-11 12:51:11,301 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-04-11 12:51:11,301 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-04-11 12:51:11,303 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-04-11 12:51:11,304 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 11.04 12:51:10" (1/3) ... [2018-04-11 12:51:11,304 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@746e9b0a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.04 12:51:11, skipping insertion in model container [2018-04-11 12:51:11,304 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 12:51:10" (2/3) ... [2018-04-11 12:51:11,304 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@746e9b0a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.04 12:51:11, skipping insertion in model container [2018-04-11 12:51:11,304 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.04 12:51:11" (3/3) ... [2018-04-11 12:51:11,306 INFO L107 eAbstractionObserver]: Analyzing ICFG cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-04-11 12:51:11,312 INFO L131 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_TreeInterpolation Determinization: PREDICATE_ABSTRACTION [2018-04-11 12:51:11,318 INFO L143 ceAbstractionStarter]: Appying trace abstraction to program that has 15 error locations. [2018-04-11 12:51:11,342 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-04-11 12:51:11,343 INFO L369 AbstractCegarLoop]: Interprodecural is true [2018-04-11 12:51:11,343 INFO L370 AbstractCegarLoop]: Hoare is false [2018-04-11 12:51:11,343 INFO L371 AbstractCegarLoop]: Compute interpolants for Craig_TreeInterpolation [2018-04-11 12:51:11,343 INFO L372 AbstractCegarLoop]: Backedges is CANONICAL [2018-04-11 12:51:11,343 INFO L373 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-04-11 12:51:11,343 INFO L374 AbstractCegarLoop]: Difference is false [2018-04-11 12:51:11,343 INFO L375 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-04-11 12:51:11,344 INFO L380 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-04-11 12:51:11,344 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-04-11 12:51:11,354 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states. [2018-04-11 12:51:11,361 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-04-11 12:51:11,361 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:11,362 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:11,362 INFO L408 AbstractCegarLoop]: === Iteration 1 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:11,364 INFO L82 PathProgramCache]: Analyzing trace with hash 281371018, now seen corresponding path program 1 times [2018-04-11 12:51:11,403 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:11,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:11,437 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:11,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:11,467 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:51:11,468 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-04-11 12:51:11,468 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:11,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:11,469 INFO L182 omatonBuilderFactory]: Interpolants [61#true, 62#false, 63#(= |#valid| |old(#valid)|)] [2018-04-11 12:51:11,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:11,470 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-11 12:51:11,482 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-11 12:51:11,482 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-11 12:51:11,484 INFO L87 Difference]: Start difference. First operand 58 states. Second operand 3 states. [2018-04-11 12:51:11,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:11,542 INFO L93 Difference]: Finished difference Result 59 states and 66 transitions. [2018-04-11 12:51:11,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-11 12:51:11,543 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-04-11 12:51:11,543 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:11,550 INFO L225 Difference]: With dead ends: 59 [2018-04-11 12:51:11,550 INFO L226 Difference]: Without dead ends: 55 [2018-04-11 12:51:11,552 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-11 12:51:11,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-04-11 12:51:11,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 55. [2018-04-11 12:51:11,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-04-11 12:51:11,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 61 transitions. [2018-04-11 12:51:11,578 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 61 transitions. Word has length 11 [2018-04-11 12:51:11,579 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:11,579 INFO L459 AbstractCegarLoop]: Abstraction has 55 states and 61 transitions. [2018-04-11 12:51:11,579 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-11 12:51:11,579 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 61 transitions. [2018-04-11 12:51:11,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-04-11 12:51:11,579 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:11,580 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:11,580 INFO L408 AbstractCegarLoop]: === Iteration 2 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:11,580 INFO L82 PathProgramCache]: Analyzing trace with hash -2051881253, now seen corresponding path program 1 times [2018-04-11 12:51:11,581 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:11,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:11,591 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:11,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:11,662 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:51:11,663 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-11 12:51:11,663 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:11,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:11,663 INFO L182 omatonBuilderFactory]: Interpolants [178#true, 179#false, 180#(<= main_~length1~0 1), 181#(<= main_~length1~0 main_~length2~0), 182#(<= (+ main_~length1~0 1) (+ main_~n~0 main_~length2~0))] [2018-04-11 12:51:11,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:11,665 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-11 12:51:11,665 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-11 12:51:11,665 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-04-11 12:51:11,665 INFO L87 Difference]: Start difference. First operand 55 states and 61 transitions. Second operand 5 states. [2018-04-11 12:51:11,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:11,762 INFO L93 Difference]: Finished difference Result 58 states and 65 transitions. [2018-04-11 12:51:11,762 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-11 12:51:11,762 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 15 [2018-04-11 12:51:11,762 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:11,763 INFO L225 Difference]: With dead ends: 58 [2018-04-11 12:51:11,763 INFO L226 Difference]: Without dead ends: 55 [2018-04-11 12:51:11,764 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-04-11 12:51:11,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-04-11 12:51:11,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 55. [2018-04-11 12:51:11,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-04-11 12:51:11,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 60 transitions. [2018-04-11 12:51:11,768 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 60 transitions. Word has length 15 [2018-04-11 12:51:11,768 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:11,768 INFO L459 AbstractCegarLoop]: Abstraction has 55 states and 60 transitions. [2018-04-11 12:51:11,768 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-11 12:51:11,769 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 60 transitions. [2018-04-11 12:51:11,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-04-11 12:51:11,769 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:11,769 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:11,769 INFO L408 AbstractCegarLoop]: === Iteration 3 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:11,769 INFO L82 PathProgramCache]: Analyzing trace with hash -1371822883, now seen corresponding path program 1 times [2018-04-11 12:51:11,770 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:11,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:11,785 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:11,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:11,831 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:51:11,831 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-11 12:51:11,831 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:11,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:11,831 INFO L182 omatonBuilderFactory]: Interpolants [300#true, 301#false, 302#(= 1 (select |#valid| |main_#t~malloc13.base|)), 303#(= 1 (select |#valid| main_~nondetString1~0.base))] [2018-04-11 12:51:11,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:11,832 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-11 12:51:11,832 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-11 12:51:11,832 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-11 12:51:11,832 INFO L87 Difference]: Start difference. First operand 55 states and 60 transitions. Second operand 4 states. [2018-04-11 12:51:11,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:11,893 INFO L93 Difference]: Finished difference Result 54 states and 59 transitions. [2018-04-11 12:51:11,894 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-11 12:51:11,894 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2018-04-11 12:51:11,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:11,895 INFO L225 Difference]: With dead ends: 54 [2018-04-11 12:51:11,895 INFO L226 Difference]: Without dead ends: 54 [2018-04-11 12:51:11,895 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-11 12:51:11,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-04-11 12:51:11,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2018-04-11 12:51:11,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-04-11 12:51:11,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 59 transitions. [2018-04-11 12:51:11,899 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 59 transitions. Word has length 15 [2018-04-11 12:51:11,899 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:11,900 INFO L459 AbstractCegarLoop]: Abstraction has 54 states and 59 transitions. [2018-04-11 12:51:11,900 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-11 12:51:11,900 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 59 transitions. [2018-04-11 12:51:11,900 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-04-11 12:51:11,900 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:11,900 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:11,900 INFO L408 AbstractCegarLoop]: === Iteration 4 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:11,901 INFO L82 PathProgramCache]: Analyzing trace with hash -1371822882, now seen corresponding path program 1 times [2018-04-11 12:51:11,901 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:11,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:11,914 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:12,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,020 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:51:12,020 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-04-11 12:51:12,020 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:12,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,021 INFO L182 omatonBuilderFactory]: Interpolants [416#(<= 1 main_~length2~0), 417#(and (<= 1 main_~length2~0) (<= 1 main_~n~0)), 418#(and (<= 1 main_~n~0) (<= (+ main_~n~0 1) main_~length1~0)), 419#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 1) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 420#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 1) main_~length1~0)), 421#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 1) main_~length1~0)), 414#true, 415#false] [2018-04-11 12:51:12,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,021 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-11 12:51:12,021 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-11 12:51:12,021 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-04-11 12:51:12,022 INFO L87 Difference]: Start difference. First operand 54 states and 59 transitions. Second operand 8 states. [2018-04-11 12:51:12,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:12,117 INFO L93 Difference]: Finished difference Result 53 states and 58 transitions. [2018-04-11 12:51:12,118 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-11 12:51:12,118 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 15 [2018-04-11 12:51:12,118 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:12,118 INFO L225 Difference]: With dead ends: 53 [2018-04-11 12:51:12,118 INFO L226 Difference]: Without dead ends: 53 [2018-04-11 12:51:12,118 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=84, Unknown=0, NotChecked=0, Total=132 [2018-04-11 12:51:12,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2018-04-11 12:51:12,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 53. [2018-04-11 12:51:12,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-04-11 12:51:12,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 58 transitions. [2018-04-11 12:51:12,122 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 58 transitions. Word has length 15 [2018-04-11 12:51:12,122 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:12,122 INFO L459 AbstractCegarLoop]: Abstraction has 53 states and 58 transitions. [2018-04-11 12:51:12,122 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-11 12:51:12,122 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 58 transitions. [2018-04-11 12:51:12,123 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-04-11 12:51:12,123 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:12,123 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:12,123 INFO L408 AbstractCegarLoop]: === Iteration 5 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:12,123 INFO L82 PathProgramCache]: Analyzing trace with hash 423163648, now seen corresponding path program 1 times [2018-04-11 12:51:12,123 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:12,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:12,138 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:12,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,159 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:51:12,159 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-11 12:51:12,159 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:12,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,160 INFO L182 omatonBuilderFactory]: Interpolants [536#true, 537#false, 538#(= 1 (select |#valid| |main_#t~malloc14.base|)), 539#(= 1 (select |#valid| main_~nondetString2~0.base))] [2018-04-11 12:51:12,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,160 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-11 12:51:12,160 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-11 12:51:12,160 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-11 12:51:12,160 INFO L87 Difference]: Start difference. First operand 53 states and 58 transitions. Second operand 4 states. [2018-04-11 12:51:12,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:12,190 INFO L93 Difference]: Finished difference Result 52 states and 57 transitions. [2018-04-11 12:51:12,190 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-11 12:51:12,190 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-04-11 12:51:12,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:12,191 INFO L225 Difference]: With dead ends: 52 [2018-04-11 12:51:12,191 INFO L226 Difference]: Without dead ends: 52 [2018-04-11 12:51:12,191 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-11 12:51:12,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-04-11 12:51:12,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 52. [2018-04-11 12:51:12,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-04-11 12:51:12,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 57 transitions. [2018-04-11 12:51:12,194 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 57 transitions. Word has length 16 [2018-04-11 12:51:12,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:12,194 INFO L459 AbstractCegarLoop]: Abstraction has 52 states and 57 transitions. [2018-04-11 12:51:12,194 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-11 12:51:12,194 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 57 transitions. [2018-04-11 12:51:12,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-04-11 12:51:12,194 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:12,194 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:12,194 INFO L408 AbstractCegarLoop]: === Iteration 6 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:12,194 INFO L82 PathProgramCache]: Analyzing trace with hash 423163649, now seen corresponding path program 1 times [2018-04-11 12:51:12,195 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:12,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:12,209 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:12,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,265 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:51:12,265 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-11 12:51:12,265 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:12,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,265 INFO L182 omatonBuilderFactory]: Interpolants [646#true, 647#false, 648#(<= 1 main_~length2~0), 649#(and (= 0 |main_#t~malloc14.offset|) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|))), 650#(and (= main_~nondetString2~0.offset 0) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)))] [2018-04-11 12:51:12,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,265 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-11 12:51:12,265 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-11 12:51:12,265 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-11 12:51:12,266 INFO L87 Difference]: Start difference. First operand 52 states and 57 transitions. Second operand 5 states. [2018-04-11 12:51:12,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:12,288 INFO L93 Difference]: Finished difference Result 51 states and 56 transitions. [2018-04-11 12:51:12,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-11 12:51:12,288 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 16 [2018-04-11 12:51:12,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:12,288 INFO L225 Difference]: With dead ends: 51 [2018-04-11 12:51:12,288 INFO L226 Difference]: Without dead ends: 51 [2018-04-11 12:51:12,289 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=16, Unknown=0, NotChecked=0, Total=30 [2018-04-11 12:51:12,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-04-11 12:51:12,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2018-04-11 12:51:12,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-04-11 12:51:12,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 56 transitions. [2018-04-11 12:51:12,291 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 56 transitions. Word has length 16 [2018-04-11 12:51:12,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:12,292 INFO L459 AbstractCegarLoop]: Abstraction has 51 states and 56 transitions. [2018-04-11 12:51:12,292 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-11 12:51:12,292 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 56 transitions. [2018-04-11 12:51:12,292 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-04-11 12:51:12,292 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:12,292 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:12,292 INFO L408 AbstractCegarLoop]: === Iteration 7 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:12,292 INFO L82 PathProgramCache]: Analyzing trace with hash 1443369787, now seen corresponding path program 1 times [2018-04-11 12:51:12,293 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:12,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:12,302 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:12,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,326 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:51:12,326 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-11 12:51:12,326 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:12,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,327 INFO L182 omatonBuilderFactory]: Interpolants [755#true, 756#false, 757#(= 1 (select |#valid| main_~nondetString1~0.base)), 758#(= 1 (select |#valid| |cstrncat_#in~s1.base|)), 759#(= 1 (select |#valid| cstrncat_~s~0.base))] [2018-04-11 12:51:12,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,327 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-11 12:51:12,327 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-11 12:51:12,327 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-04-11 12:51:12,328 INFO L87 Difference]: Start difference. First operand 51 states and 56 transitions. Second operand 5 states. [2018-04-11 12:51:12,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:12,391 INFO L93 Difference]: Finished difference Result 47 states and 52 transitions. [2018-04-11 12:51:12,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-11 12:51:12,391 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 20 [2018-04-11 12:51:12,391 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:12,391 INFO L225 Difference]: With dead ends: 47 [2018-04-11 12:51:12,391 INFO L226 Difference]: Without dead ends: 47 [2018-04-11 12:51:12,391 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-04-11 12:51:12,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-04-11 12:51:12,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2018-04-11 12:51:12,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-04-11 12:51:12,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 52 transitions. [2018-04-11 12:51:12,393 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 52 transitions. Word has length 20 [2018-04-11 12:51:12,393 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:12,393 INFO L459 AbstractCegarLoop]: Abstraction has 47 states and 52 transitions. [2018-04-11 12:51:12,393 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-11 12:51:12,393 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 52 transitions. [2018-04-11 12:51:12,394 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-04-11 12:51:12,394 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:12,394 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:12,394 INFO L408 AbstractCegarLoop]: === Iteration 8 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:12,394 INFO L82 PathProgramCache]: Analyzing trace with hash 1443369788, now seen corresponding path program 1 times [2018-04-11 12:51:12,394 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:12,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:12,404 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:12,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,511 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:51:12,511 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-04-11 12:51:12,511 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:12,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,511 INFO L182 omatonBuilderFactory]: Interpolants [864#(and (= cstrncat_~s~0.offset 0) (<= 1 (select |#length| cstrncat_~s~0.base))), 856#true, 857#false, 858#(<= 1 main_~length2~0), 859#(<= (+ main_~n~0 1) main_~length1~0), 860#(and (<= (+ main_~n~0 1) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 861#(and (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 1) main_~length1~0)), 862#(and (<= (+ main_~nondetString1~0.offset 1) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 863#(and (= 0 |cstrncat_#in~s1.offset|) (<= 1 (select |#length| |cstrncat_#in~s1.base|)))] [2018-04-11 12:51:12,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,512 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-11 12:51:12,512 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-11 12:51:12,512 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-04-11 12:51:12,512 INFO L87 Difference]: Start difference. First operand 47 states and 52 transitions. Second operand 9 states. [2018-04-11 12:51:12,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:12,617 INFO L93 Difference]: Finished difference Result 65 states and 74 transitions. [2018-04-11 12:51:12,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-11 12:51:12,617 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 20 [2018-04-11 12:51:12,617 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:12,620 INFO L225 Difference]: With dead ends: 65 [2018-04-11 12:51:12,620 INFO L226 Difference]: Without dead ends: 65 [2018-04-11 12:51:12,620 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2018-04-11 12:51:12,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2018-04-11 12:51:12,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 60. [2018-04-11 12:51:12,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-04-11 12:51:12,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 71 transitions. [2018-04-11 12:51:12,625 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 71 transitions. Word has length 20 [2018-04-11 12:51:12,625 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:12,625 INFO L459 AbstractCegarLoop]: Abstraction has 60 states and 71 transitions. [2018-04-11 12:51:12,625 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-11 12:51:12,625 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 71 transitions. [2018-04-11 12:51:12,626 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-04-11 12:51:12,626 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:12,626 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:12,626 INFO L408 AbstractCegarLoop]: === Iteration 9 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:12,626 INFO L82 PathProgramCache]: Analyzing trace with hash -1783256229, now seen corresponding path program 1 times [2018-04-11 12:51:12,627 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:12,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:12,638 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:12,762 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,763 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:12,763 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11] total 11 [2018-04-11 12:51:12,763 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:12,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,763 INFO L182 omatonBuilderFactory]: Interpolants [1008#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 2 main_~length1~0)), 1009#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 2 main_~length1~0)), 1010#(and (= 0 main_~nondetString1~0.offset) (<= 2 (select |#length| main_~nondetString1~0.base))), 1011#(and (= 0 |cstrncat_#in~s1.offset|) (<= 2 (select |#length| |cstrncat_#in~s1.base|))), 1012#(and (<= 2 (select |#length| cstrncat_~s~0.base)) (= cstrncat_~s~0.offset 0)), 1013#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 1002#true, 1003#false, 1004#(<= 1 main_~length2~0), 1005#(<= 2 (+ main_~n~0 main_~length2~0)), 1006#(<= 2 main_~length1~0), 1007#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 2 main_~length1~0) (= 0 |main_#t~malloc13.offset|))] [2018-04-11 12:51:12,763 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:12,763 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-04-11 12:51:12,763 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-04-11 12:51:12,763 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2018-04-11 12:51:12,764 INFO L87 Difference]: Start difference. First operand 60 states and 71 transitions. Second operand 12 states. [2018-04-11 12:51:12,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:12,977 INFO L93 Difference]: Finished difference Result 83 states and 96 transitions. [2018-04-11 12:51:12,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-11 12:51:12,977 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 23 [2018-04-11 12:51:12,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:12,978 INFO L225 Difference]: With dead ends: 83 [2018-04-11 12:51:12,978 INFO L226 Difference]: Without dead ends: 83 [2018-04-11 12:51:12,979 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=75, Invalid=267, Unknown=0, NotChecked=0, Total=342 [2018-04-11 12:51:12,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-04-11 12:51:12,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 70. [2018-04-11 12:51:12,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-04-11 12:51:12,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 86 transitions. [2018-04-11 12:51:12,983 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 86 transitions. Word has length 23 [2018-04-11 12:51:12,983 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:12,984 INFO L459 AbstractCegarLoop]: Abstraction has 70 states and 86 transitions. [2018-04-11 12:51:12,984 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-04-11 12:51:12,984 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 86 transitions. [2018-04-11 12:51:12,984 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-04-11 12:51:12,984 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:12,985 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:12,985 INFO L408 AbstractCegarLoop]: === Iteration 10 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:12,985 INFO L82 PathProgramCache]: Analyzing trace with hash -18671751, now seen corresponding path program 1 times [2018-04-11 12:51:12,986 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:12,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:12,997 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:13,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:13,032 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:51:13,033 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-11 12:51:13,033 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:13,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:13,033 INFO L182 omatonBuilderFactory]: Interpolants [1184#(= 1 (select |#valid| |cstrncat_#in~s2.base|)), 1185#(= 1 (select |#valid| cstrncat_~s2.base)), 1186#(= 1 (select |#valid| |cstrncat_#t~post4.base|)), 1181#true, 1182#false, 1183#(= 1 (select |#valid| main_~nondetString2~0.base))] [2018-04-11 12:51:13,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:13,033 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-11 12:51:13,033 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-11 12:51:13,034 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-04-11 12:51:13,034 INFO L87 Difference]: Start difference. First operand 70 states and 86 transitions. Second operand 6 states. [2018-04-11 12:51:13,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:13,078 INFO L93 Difference]: Finished difference Result 72 states and 89 transitions. [2018-04-11 12:51:13,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-11 12:51:13,078 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2018-04-11 12:51:13,078 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:13,080 INFO L225 Difference]: With dead ends: 72 [2018-04-11 12:51:13,080 INFO L226 Difference]: Without dead ends: 72 [2018-04-11 12:51:13,080 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-04-11 12:51:13,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-04-11 12:51:13,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 69. [2018-04-11 12:51:13,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-04-11 12:51:13,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 83 transitions. [2018-04-11 12:51:13,089 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 83 transitions. Word has length 25 [2018-04-11 12:51:13,089 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:13,089 INFO L459 AbstractCegarLoop]: Abstraction has 69 states and 83 transitions. [2018-04-11 12:51:13,089 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-11 12:51:13,089 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 83 transitions. [2018-04-11 12:51:13,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-04-11 12:51:13,090 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:13,090 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:13,090 INFO L408 AbstractCegarLoop]: === Iteration 11 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:13,090 INFO L82 PathProgramCache]: Analyzing trace with hash -18671750, now seen corresponding path program 1 times [2018-04-11 12:51:13,090 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:13,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:13,099 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:13,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:13,152 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:51:13,152 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-04-11 12:51:13,152 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:13,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:13,152 INFO L182 omatonBuilderFactory]: Interpolants [1332#true, 1333#false, 1334#(<= 1 main_~length2~0), 1335#(and (= 0 |main_#t~malloc14.offset|) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|))), 1336#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 1337#(and (= 0 main_~nondetString2~0.offset) (<= 1 (select |#length| main_~nondetString2~0.base))), 1338#(and (= 0 |cstrncat_#in~s2.offset|) (<= 1 (select |#length| |cstrncat_#in~s2.base|))), 1339#(and (<= 1 (select |#length| cstrncat_~s2.base)) (= 0 cstrncat_~s2.offset)), 1340#(and (<= 1 (select |#length| |cstrncat_#t~post4.base|)) (= |cstrncat_#t~post4.offset| 0))] [2018-04-11 12:51:13,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:13,152 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-11 12:51:13,153 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-11 12:51:13,153 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-04-11 12:51:13,153 INFO L87 Difference]: Start difference. First operand 69 states and 83 transitions. Second operand 9 states. [2018-04-11 12:51:13,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:13,227 INFO L93 Difference]: Finished difference Result 98 states and 120 transitions. [2018-04-11 12:51:13,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-04-11 12:51:13,227 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 25 [2018-04-11 12:51:13,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:13,228 INFO L225 Difference]: With dead ends: 98 [2018-04-11 12:51:13,228 INFO L226 Difference]: Without dead ends: 98 [2018-04-11 12:51:13,228 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2018-04-11 12:51:13,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-04-11 12:51:13,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 80. [2018-04-11 12:51:13,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-04-11 12:51:13,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 98 transitions. [2018-04-11 12:51:13,231 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 98 transitions. Word has length 25 [2018-04-11 12:51:13,231 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:13,231 INFO L459 AbstractCegarLoop]: Abstraction has 80 states and 98 transitions. [2018-04-11 12:51:13,231 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-11 12:51:13,232 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 98 transitions. [2018-04-11 12:51:13,232 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-04-11 12:51:13,232 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:13,232 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:13,232 INFO L408 AbstractCegarLoop]: === Iteration 12 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:13,232 INFO L82 PathProgramCache]: Analyzing trace with hash -535876900, now seen corresponding path program 2 times [2018-04-11 12:51:13,233 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:13,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:13,249 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:13,520 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:13,520 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:13,520 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-04-11 12:51:13,520 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:13,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:13,520 INFO L182 omatonBuilderFactory]: Interpolants [1536#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base))), 1537#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)), 1525#true, 1526#false, 1527#(<= 1 main_~n~0), 1528#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 1529#(and (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)))), 1530#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)))), 1531#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 1532#(and (= 0 main_~nondetString1~0.offset) (or (<= 3 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 1533#(and (= 0 |cstrncat_#in~s1.offset|) (or (<= 3 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 1534#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= 3 (select |#length| cstrncat_~s~0.base))) (= cstrncat_~s~0.offset 0)), 1535#(and (or (<= 3 (select |#length| cstrncat_~s~0.base)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (= cstrncat_~s~0.offset 0))] [2018-04-11 12:51:13,521 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:13,521 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-04-11 12:51:13,521 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-04-11 12:51:13,521 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=131, Unknown=0, NotChecked=0, Total=156 [2018-04-11 12:51:13,521 INFO L87 Difference]: Start difference. First operand 80 states and 98 transitions. Second operand 13 states. [2018-04-11 12:51:13,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:13,985 INFO L93 Difference]: Finished difference Result 149 states and 181 transitions. [2018-04-11 12:51:13,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-04-11 12:51:13,985 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 26 [2018-04-11 12:51:13,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:13,986 INFO L225 Difference]: With dead ends: 149 [2018-04-11 12:51:13,986 INFO L226 Difference]: Without dead ends: 149 [2018-04-11 12:51:13,986 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=106, Invalid=494, Unknown=0, NotChecked=0, Total=600 [2018-04-11 12:51:13,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-04-11 12:51:13,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 83. [2018-04-11 12:51:13,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2018-04-11 12:51:13,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 102 transitions. [2018-04-11 12:51:13,990 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 102 transitions. Word has length 26 [2018-04-11 12:51:13,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:13,990 INFO L459 AbstractCegarLoop]: Abstraction has 83 states and 102 transitions. [2018-04-11 12:51:13,990 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-04-11 12:51:13,990 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 102 transitions. [2018-04-11 12:51:13,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-04-11 12:51:13,991 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:13,991 INFO L355 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:13,991 INFO L408 AbstractCegarLoop]: === Iteration 13 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:13,991 INFO L82 PathProgramCache]: Analyzing trace with hash 84668347, now seen corresponding path program 3 times [2018-04-11 12:51:13,991 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:13,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:13,999 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:14,262 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:14,262 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:14,262 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14] total 14 [2018-04-11 12:51:14,262 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:14,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:14,263 INFO L182 omatonBuilderFactory]: Interpolants [1794#true, 1795#false, 1796#(and (<= 1 main_~n~0) (<= main_~n~0 1)), 1797#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= main_~n~0 1) (= 0 |main_#t~malloc13.offset|)), 1798#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= main_~n~0 1))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= (select |#valid| main_~nondetString1~0.base) 1)), 1799#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= main_~n~0 1))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 1800#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= main_~n~0 1))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 1801#(and (or (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (<= (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)) 2)) (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 1802#(and (or (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (<= (select |#length| |cstrncat_#in~s1.base|) 2)) (= 0 |cstrncat_#in~s1.offset|)), 1803#(and (= cstrncat_~s~0.offset 0) (or (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (<= 4 (select |#length| cstrncat_~s~0.base)))), 1804#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 1 cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 1805#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 1 cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 1806#(or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 1807#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 1808#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))] [2018-04-11 12:51:14,263 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:14,263 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-04-11 12:51:14,263 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-04-11 12:51:14,263 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=180, Unknown=0, NotChecked=0, Total=210 [2018-04-11 12:51:14,263 INFO L87 Difference]: Start difference. First operand 83 states and 102 transitions. Second operand 15 states. [2018-04-11 12:51:14,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:14,898 INFO L93 Difference]: Finished difference Result 236 states and 289 transitions. [2018-04-11 12:51:14,898 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-04-11 12:51:14,898 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 29 [2018-04-11 12:51:14,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:14,899 INFO L225 Difference]: With dead ends: 236 [2018-04-11 12:51:14,899 INFO L226 Difference]: Without dead ends: 236 [2018-04-11 12:51:14,899 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 130 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=121, Invalid=691, Unknown=0, NotChecked=0, Total=812 [2018-04-11 12:51:14,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-04-11 12:51:14,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 162. [2018-04-11 12:51:14,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-04-11 12:51:14,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 211 transitions. [2018-04-11 12:51:14,905 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 211 transitions. Word has length 29 [2018-04-11 12:51:14,905 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:14,905 INFO L459 AbstractCegarLoop]: Abstraction has 162 states and 211 transitions. [2018-04-11 12:51:14,905 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-04-11 12:51:14,905 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 211 transitions. [2018-04-11 12:51:14,906 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-04-11 12:51:14,906 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:14,906 INFO L355 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:14,906 INFO L408 AbstractCegarLoop]: === Iteration 14 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:14,906 INFO L82 PathProgramCache]: Analyzing trace with hash 507370173, now seen corresponding path program 1 times [2018-04-11 12:51:14,906 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:14,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:14,914 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:15,212 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:15,213 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:15,213 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-04-11 12:51:15,213 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:15,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:15,214 INFO L182 omatonBuilderFactory]: Interpolants [2240#(and (= 0 main_~nondetString1~0.offset) (or (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (and (or (<= 1 main_~n~0) (< (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 3))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)))) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|))), 2241#(and (= 0 main_~nondetString1~0.offset) (or (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (and (or (<= 1 main_~n~0) (< (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 3))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 2242#(and (= 0 main_~nondetString1~0.offset) (or (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 2243#(and (= 0 |cstrncat_#in~s1.offset|) (or (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 2244#(and (= cstrncat_~s~0.offset 0) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (<= 4 (select |#length| cstrncat_~s~0.base)))), 2245#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (<= 4 (select |#length| cstrncat_~s~0.base))) (= cstrncat_~s~0.offset 0)), 2246#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 1 cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 2247#(or (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 1 cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 2248#(<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)), 2249#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 2250#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 2235#true, 2236#false, 2237#(<= 1 main_~n~0), 2238#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 2239#(and (= 0 main_~nondetString1~0.offset) (or (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (and (or (<= 1 main_~n~0) (< (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 3))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)))) (= (select |#valid| main_~nondetString1~0.base) 1))] [2018-04-11 12:51:15,214 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:15,214 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-11 12:51:15,214 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-11 12:51:15,214 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-04-11 12:51:15,214 INFO L87 Difference]: Start difference. First operand 162 states and 211 transitions. Second operand 16 states. [2018-04-11 12:51:15,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:15,809 INFO L93 Difference]: Finished difference Result 298 states and 376 transitions. [2018-04-11 12:51:15,809 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-04-11 12:51:15,809 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 29 [2018-04-11 12:51:15,809 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:15,810 INFO L225 Difference]: With dead ends: 298 [2018-04-11 12:51:15,810 INFO L226 Difference]: Without dead ends: 298 [2018-04-11 12:51:15,811 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=130, Invalid=800, Unknown=0, NotChecked=0, Total=930 [2018-04-11 12:51:15,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 298 states. [2018-04-11 12:51:15,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 298 to 86. [2018-04-11 12:51:15,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-04-11 12:51:15,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 106 transitions. [2018-04-11 12:51:15,816 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 106 transitions. Word has length 29 [2018-04-11 12:51:15,816 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:15,816 INFO L459 AbstractCegarLoop]: Abstraction has 86 states and 106 transitions. [2018-04-11 12:51:15,816 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-11 12:51:15,816 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 106 transitions. [2018-04-11 12:51:15,817 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-04-11 12:51:15,817 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:15,817 INFO L355 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:15,817 INFO L408 AbstractCegarLoop]: === Iteration 15 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:15,818 INFO L82 PathProgramCache]: Analyzing trace with hash 1208879740, now seen corresponding path program 4 times [2018-04-11 12:51:15,818 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:15,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:15,830 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:16,050 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:16,050 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:16,050 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-04-11 12:51:16,050 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:16,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:16,051 INFO L182 omatonBuilderFactory]: Interpolants [2665#true, 2666#false, 2667#(and (<= 1 main_~n~0) (<= main_~n~0 1)), 2668#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= main_~n~0 1) (= 0 |main_#t~malloc13.offset|)), 2669#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (<= main_~n~0 1) (= main_~nondetString1~0.offset 0)), 2670#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (<= main_~n~0 1) (= main_~nondetString1~0.offset 0)), 2671#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (<= main_~n~0 1) (= main_~nondetString1~0.offset 0)), 2672#(and (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (+ (select |#length| main_~nondetString1~0.base) (+ main_~n~0 (- 1))) (+ main_~nondetString1~0.offset (+ (- main_~n~0) (- 1)))))) (= main_~nondetString1~0.offset 0)), 2673#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1))))), 2674#(and (= cstrncat_~s~0.offset 0) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))), 2675#(and (<= 1 cstrncat_~s~0.offset) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))), 2676#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (<= 2 cstrncat_~s~0.offset))), 2677#(or (and (or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (<= 2 cstrncat_~s~0.offset)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 2678#(and (<= 3 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset))), 2679#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 3 cstrncat_~s~0.offset)), 2680#(and (<= 4 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))] [2018-04-11 12:51:16,051 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:16,051 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-11 12:51:16,051 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-11 12:51:16,051 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=205, Unknown=0, NotChecked=0, Total=240 [2018-04-11 12:51:16,051 INFO L87 Difference]: Start difference. First operand 86 states and 106 transitions. Second operand 16 states. [2018-04-11 12:51:16,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:16,684 INFO L93 Difference]: Finished difference Result 265 states and 322 transitions. [2018-04-11 12:51:16,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-04-11 12:51:16,685 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 32 [2018-04-11 12:51:16,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:16,686 INFO L225 Difference]: With dead ends: 265 [2018-04-11 12:51:16,686 INFO L226 Difference]: Without dead ends: 265 [2018-04-11 12:51:16,687 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 329 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=220, Invalid=1186, Unknown=0, NotChecked=0, Total=1406 [2018-04-11 12:51:16,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states. [2018-04-11 12:51:16,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 147. [2018-04-11 12:51:16,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-04-11 12:51:16,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 189 transitions. [2018-04-11 12:51:16,690 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 189 transitions. Word has length 32 [2018-04-11 12:51:16,690 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:16,690 INFO L459 AbstractCegarLoop]: Abstraction has 147 states and 189 transitions. [2018-04-11 12:51:16,690 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-11 12:51:16,690 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 189 transitions. [2018-04-11 12:51:16,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-04-11 12:51:16,691 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:16,691 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:16,691 INFO L408 AbstractCegarLoop]: === Iteration 16 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:16,692 INFO L82 PathProgramCache]: Analyzing trace with hash -751050763, now seen corresponding path program 1 times [2018-04-11 12:51:16,692 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:16,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:16,704 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:16,760 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:16,760 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:16,760 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-04-11 12:51:16,760 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:16,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:16,761 INFO L182 omatonBuilderFactory]: Interpolants [3137#true, 3138#false, 3139#(and (<= 1 main_~n~0) (<= main_~n~0 1)), 3140#(and (<= |cstrncat_#in~n| 1) (<= 1 |cstrncat_#in~n|)), 3141#(and (<= 1 cstrncat_~n) (<= cstrncat_~n 1)), 3142#(and (<= cstrncat_~n 0) (<= 0 cstrncat_~n)), 3143#(not |cstrncat_#t~short6|)] [2018-04-11 12:51:16,761 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:16,761 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-04-11 12:51:16,761 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-04-11 12:51:16,761 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-04-11 12:51:16,761 INFO L87 Difference]: Start difference. First operand 147 states and 189 transitions. Second operand 7 states. [2018-04-11 12:51:16,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:16,819 INFO L93 Difference]: Finished difference Result 164 states and 192 transitions. [2018-04-11 12:51:16,819 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-04-11 12:51:16,819 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 32 [2018-04-11 12:51:16,819 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:16,820 INFO L225 Difference]: With dead ends: 164 [2018-04-11 12:51:16,820 INFO L226 Difference]: Without dead ends: 164 [2018-04-11 12:51:16,821 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=79, Unknown=0, NotChecked=0, Total=110 [2018-04-11 12:51:16,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164 states. [2018-04-11 12:51:16,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164 to 114. [2018-04-11 12:51:16,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-04-11 12:51:16,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 135 transitions. [2018-04-11 12:51:16,824 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 135 transitions. Word has length 32 [2018-04-11 12:51:16,824 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:16,824 INFO L459 AbstractCegarLoop]: Abstraction has 114 states and 135 transitions. [2018-04-11 12:51:16,824 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-04-11 12:51:16,825 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 135 transitions. [2018-04-11 12:51:16,825 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-04-11 12:51:16,825 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:16,825 INFO L355 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:16,825 INFO L408 AbstractCegarLoop]: === Iteration 17 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:16,826 INFO L82 PathProgramCache]: Analyzing trace with hash 1074866234, now seen corresponding path program 2 times [2018-04-11 12:51:16,826 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:16,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:16,838 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:17,174 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:17,174 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:17,174 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-04-11 12:51:17,174 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:17,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:17,174 INFO L182 omatonBuilderFactory]: Interpolants [3430#true, 3431#false, 3432#(<= 1 main_~n~0), 3433#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 3434#(and (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 3435#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 3436#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 3437#(and (= 0 main_~nondetString1~0.offset) (or (and (<= 4 (select |#length| main_~nondetString1~0.base)) (or (<= 5 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1)))))))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 3438#(and (= 0 |cstrncat_#in~s1.offset|) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (or (<= 5 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- 3)) (- 1)))))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 3439#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (<= 4 (select |#length| cstrncat_~s~0.base)))) (= cstrncat_~s~0.offset 0)), 3440#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (<= 4 (select |#length| cstrncat_~s~0.base)))) (= cstrncat_~s~0.offset 0)), 3441#(and (= cstrncat_~s~0.offset 1) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)))))), 3442#(and (or (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))))) (= cstrncat_~s~0.offset 1)), 3443#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (<= 2 cstrncat_~s~0.offset)), 3444#(and (or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (<= 2 cstrncat_~s~0.offset)), 3445#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 3 cstrncat_~s~0.offset)), 3446#(and (<= 4 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))] [2018-04-11 12:51:17,174 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:17,174 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-04-11 12:51:17,175 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-04-11 12:51:17,175 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=237, Unknown=0, NotChecked=0, Total=272 [2018-04-11 12:51:17,175 INFO L87 Difference]: Start difference. First operand 114 states and 135 transitions. Second operand 17 states. [2018-04-11 12:51:17,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:17,990 INFO L93 Difference]: Finished difference Result 304 states and 356 transitions. [2018-04-11 12:51:17,990 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-04-11 12:51:17,990 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 32 [2018-04-11 12:51:17,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:17,991 INFO L225 Difference]: With dead ends: 304 [2018-04-11 12:51:17,991 INFO L226 Difference]: Without dead ends: 304 [2018-04-11 12:51:17,991 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 223 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=150, Invalid=1040, Unknown=0, NotChecked=0, Total=1190 [2018-04-11 12:51:17,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304 states. [2018-04-11 12:51:17,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304 to 117. [2018-04-11 12:51:17,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-04-11 12:51:17,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 139 transitions. [2018-04-11 12:51:17,995 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 139 transitions. Word has length 32 [2018-04-11 12:51:17,995 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:17,995 INFO L459 AbstractCegarLoop]: Abstraction has 117 states and 139 transitions. [2018-04-11 12:51:17,995 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-04-11 12:51:17,995 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 139 transitions. [2018-04-11 12:51:17,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-04-11 12:51:17,996 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:17,996 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:17,996 INFO L408 AbstractCegarLoop]: === Iteration 18 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:17,997 INFO L82 PathProgramCache]: Analyzing trace with hash -885064269, now seen corresponding path program 1 times [2018-04-11 12:51:17,998 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:18,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:18,006 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:18,081 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:18,081 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:51:18,081 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-04-11 12:51:18,082 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:18,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:18,082 INFO L182 omatonBuilderFactory]: Interpolants [3904#true, 3905#false, 3906#(and (<= main_~length2~0 1) (<= 1 main_~length2~0)), 3907#(and (<= main_~length2~0 1) (= 0 |main_#t~malloc14.offset|) (<= 1 main_~length2~0)), 3908#(and (= main_~nondetString2~0.offset 0) (= (+ main_~nondetString2~0.offset main_~length2~0) 1)), 3909#(and (= main_~nondetString2~0.offset 0) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset))), 3910#(= 0 (select (select |#memory_int| |cstrncat_#in~s2.base|) |cstrncat_#in~s2.offset|)), 3911#(= 0 (select (select |#memory_int| cstrncat_~s2.base) cstrncat_~s2.offset)), 3912#(= 0 (select (select |#memory_int| |cstrncat_#t~post4.base|) |cstrncat_#t~post4.offset|)), 3913#(= 0 |cstrncat_#t~mem5|), 3914#(not |cstrncat_#t~short6|)] [2018-04-11 12:51:18,082 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:18,082 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-11 12:51:18,082 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-11 12:51:18,082 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2018-04-11 12:51:18,082 INFO L87 Difference]: Start difference. First operand 117 states and 139 transitions. Second operand 11 states. [2018-04-11 12:51:18,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:18,213 INFO L93 Difference]: Finished difference Result 231 states and 270 transitions. [2018-04-11 12:51:18,213 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-11 12:51:18,213 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 32 [2018-04-11 12:51:18,213 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:18,214 INFO L225 Difference]: With dead ends: 231 [2018-04-11 12:51:18,214 INFO L226 Difference]: Without dead ends: 231 [2018-04-11 12:51:18,214 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=67, Invalid=275, Unknown=0, NotChecked=0, Total=342 [2018-04-11 12:51:18,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231 states. [2018-04-11 12:51:18,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231 to 193. [2018-04-11 12:51:18,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 193 states. [2018-04-11 12:51:18,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 233 transitions. [2018-04-11 12:51:18,220 INFO L78 Accepts]: Start accepts. Automaton has 193 states and 233 transitions. Word has length 32 [2018-04-11 12:51:18,220 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:18,220 INFO L459 AbstractCegarLoop]: Abstraction has 193 states and 233 transitions. [2018-04-11 12:51:18,220 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-11 12:51:18,220 INFO L276 IsEmpty]: Start isEmpty. Operand 193 states and 233 transitions. [2018-04-11 12:51:18,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-04-11 12:51:18,220 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:18,221 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:18,221 INFO L408 AbstractCegarLoop]: === Iteration 19 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:18,221 INFO L82 PathProgramCache]: Analyzing trace with hash -744515659, now seen corresponding path program 1 times [2018-04-11 12:51:18,221 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:18,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:18,230 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:18,356 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:18,356 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:18,356 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-04-11 12:51:18,357 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:18,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:18,357 INFO L182 omatonBuilderFactory]: Interpolants [4355#true, 4356#false, 4357#(<= 1 main_~length2~0), 4358#(and (= 0 |main_#t~malloc14.offset|) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|))), 4359#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length2~0) 1) (and (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))))), 4360#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= 2 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 4361#(and (= 0 |cstrncat_#in~s2.offset|) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s2.base|) |cstrncat_#in~s2.offset|)) (<= 2 (select |#length| |cstrncat_#in~s2.base|)))), 4362#(and (= 0 cstrncat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrncat_~s2.base) cstrncat_~s2.offset)) (<= 2 (select |#length| cstrncat_~s2.base)))), 4363#(and (= |cstrncat_#t~post4.offset| 0) (or (= 0 (select (select |#memory_int| |cstrncat_#t~post4.base|) |cstrncat_#t~post4.offset|)) (and (<= (+ cstrncat_~s2.offset 1) (+ |cstrncat_#t~post4.offset| (select |#length| cstrncat_~s2.base))) (<= (+ |cstrncat_#t~post4.offset| 1) cstrncat_~s2.offset)))), 4364#(or (and (<= 1 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base))) (= 0 |cstrncat_#t~mem5|)), 4365#(or (and (<= 1 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base))) (not |cstrncat_#t~short6|)), 4366#(and (<= 1 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base))), 4367#(and (<= 1 |cstrncat_#t~post4.offset|) (<= (+ |cstrncat_#t~post4.offset| 1) (select |#length| |cstrncat_#t~post4.base|)))] [2018-04-11 12:51:18,357 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:18,357 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-04-11 12:51:18,357 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-04-11 12:51:18,357 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2018-04-11 12:51:18,358 INFO L87 Difference]: Start difference. First operand 193 states and 233 transitions. Second operand 13 states. [2018-04-11 12:51:18,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:18,656 INFO L93 Difference]: Finished difference Result 271 states and 324 transitions. [2018-04-11 12:51:18,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-04-11 12:51:18,656 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 32 [2018-04-11 12:51:18,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:18,657 INFO L225 Difference]: With dead ends: 271 [2018-04-11 12:51:18,657 INFO L226 Difference]: Without dead ends: 271 [2018-04-11 12:51:18,657 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=76, Invalid=386, Unknown=0, NotChecked=0, Total=462 [2018-04-11 12:51:18,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states. [2018-04-11 12:51:18,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 203. [2018-04-11 12:51:18,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-04-11 12:51:18,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 246 transitions. [2018-04-11 12:51:18,660 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 246 transitions. Word has length 32 [2018-04-11 12:51:18,661 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:18,661 INFO L459 AbstractCegarLoop]: Abstraction has 203 states and 246 transitions. [2018-04-11 12:51:18,661 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-04-11 12:51:18,661 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 246 transitions. [2018-04-11 12:51:18,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-04-11 12:51:18,661 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:18,661 INFO L355 BasicCegarLoop]: trace histogram [6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:18,661 INFO L408 AbstractCegarLoop]: === Iteration 20 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:18,661 INFO L82 PathProgramCache]: Analyzing trace with hash -1936224867, now seen corresponding path program 3 times [2018-04-11 12:51:18,662 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:18,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:18,670 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:19,148 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:19,148 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:19,148 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-04-11 12:51:19,149 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:19,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:19,149 INFO L182 omatonBuilderFactory]: Interpolants [4864#(and (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 4865#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 4866#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 4867#(and (= 0 main_~nondetString1~0.offset) (or (and (<= 4 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (or (<= 6 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1)))) (+ main_~nondetString1~0.offset (- 1))))))) (<= 5 (select |#length| main_~nondetString1~0.base)))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 4868#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- 3)) (- 1))))) (and (<= 5 (select |#length| |cstrncat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1)) (- 1)))) (<= 6 (select |#length| |cstrncat_#in~s1.base|)))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 4869#(and (= cstrncat_~s~0.offset 0) (or (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~s~0.base))) (<= 5 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))))), 4870#(and (= cstrncat_~s~0.offset 0) (or (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~s~0.base))) (<= 5 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))))), 4871#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (= cstrncat_~s~0.offset 1)), 4872#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (= cstrncat_~s~0.offset 1)), 4873#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 4874#(or (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 4875#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 4876#(or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 4877#(<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)), 4878#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 4879#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 4860#true, 4861#false, 4862#(<= 1 main_~n~0), 4863#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|))] [2018-04-11 12:51:19,149 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:19,149 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-04-11 12:51:19,150 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-04-11 12:51:19,150 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=328, Unknown=0, NotChecked=0, Total=380 [2018-04-11 12:51:19,150 INFO L87 Difference]: Start difference. First operand 203 states and 246 transitions. Second operand 20 states. [2018-04-11 12:51:20,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:20,358 INFO L93 Difference]: Finished difference Result 722 states and 847 transitions. [2018-04-11 12:51:20,358 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-04-11 12:51:20,358 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 35 [2018-04-11 12:51:20,358 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:20,359 INFO L225 Difference]: With dead ends: 722 [2018-04-11 12:51:20,360 INFO L226 Difference]: Without dead ends: 722 [2018-04-11 12:51:20,360 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 465 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=271, Invalid=1709, Unknown=0, NotChecked=0, Total=1980 [2018-04-11 12:51:20,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 722 states. [2018-04-11 12:51:20,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 722 to 209. [2018-04-11 12:51:20,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 209 states. [2018-04-11 12:51:20,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209 states to 209 states and 254 transitions. [2018-04-11 12:51:20,368 INFO L78 Accepts]: Start accepts. Automaton has 209 states and 254 transitions. Word has length 35 [2018-04-11 12:51:20,368 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:20,368 INFO L459 AbstractCegarLoop]: Abstraction has 209 states and 254 transitions. [2018-04-11 12:51:20,368 INFO L460 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-04-11 12:51:20,369 INFO L276 IsEmpty]: Start isEmpty. Operand 209 states and 254 transitions. [2018-04-11 12:51:20,369 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-04-11 12:51:20,369 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:20,369 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:20,369 INFO L408 AbstractCegarLoop]: === Iteration 21 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:20,369 INFO L82 PathProgramCache]: Analyzing trace with hash 1826876010, now seen corresponding path program 1 times [2018-04-11 12:51:20,370 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:20,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:20,373 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:20,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:20,397 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:51:20,397 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-04-11 12:51:20,397 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:20,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:20,397 INFO L182 omatonBuilderFactory]: Interpolants [5861#true, 5862#false, 5863#(<= 1 main_~n~0), 5864#(<= |cstrncat_#in~n| cstrncat_~n), 5865#(or (<= |cstrncat_#in~n| 0) |cstrncat_#t~short6|), 5866#(<= |cstrncat_#in~n| 0)] [2018-04-11 12:51:20,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:20,398 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-11 12:51:20,398 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-11 12:51:20,398 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-04-11 12:51:20,398 INFO L87 Difference]: Start difference. First operand 209 states and 254 transitions. Second operand 6 states. [2018-04-11 12:51:20,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:20,425 INFO L93 Difference]: Finished difference Result 265 states and 316 transitions. [2018-04-11 12:51:20,425 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-11 12:51:20,425 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 36 [2018-04-11 12:51:20,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:20,426 INFO L225 Difference]: With dead ends: 265 [2018-04-11 12:51:20,426 INFO L226 Difference]: Without dead ends: 237 [2018-04-11 12:51:20,426 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-04-11 12:51:20,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237 states. [2018-04-11 12:51:20,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237 to 213. [2018-04-11 12:51:20,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 213 states. [2018-04-11 12:51:20,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 254 transitions. [2018-04-11 12:51:20,429 INFO L78 Accepts]: Start accepts. Automaton has 213 states and 254 transitions. Word has length 36 [2018-04-11 12:51:20,429 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:20,429 INFO L459 AbstractCegarLoop]: Abstraction has 213 states and 254 transitions. [2018-04-11 12:51:20,429 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-11 12:51:20,429 INFO L276 IsEmpty]: Start isEmpty. Operand 213 states and 254 transitions. [2018-04-11 12:51:20,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-11 12:51:20,430 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:20,430 INFO L355 BasicCegarLoop]: trace histogram [7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:20,430 INFO L408 AbstractCegarLoop]: === Iteration 22 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:20,430 INFO L82 PathProgramCache]: Analyzing trace with hash -664270502, now seen corresponding path program 4 times [2018-04-11 12:51:20,430 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:20,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:20,439 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:21,282 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:21,282 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:21,282 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-04-11 12:51:21,282 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:21,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:21,282 INFO L182 omatonBuilderFactory]: Interpolants [6368#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base))), 6369#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)), 6349#true, 6350#false, 6351#(<= 1 main_~n~0), 6352#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 6353#(and (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 6354#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 6355#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 6356#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (<= 5 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (<= 4 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1)))) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 6 (select |#length| main_~nondetString1~0.base)) (or (<= 7 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1)) (+ main_~nondetString1~0.offset (- 1)))))))))), 6357#(and (= 0 |cstrncat_#in~s1.offset|) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1)) (- 1))))) (and (<= 6 (select |#length| |cstrncat_#in~s1.base|)) (or (<= 7 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1)) (- 1)))))) (and (<= 5 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- 3)) (- 1))))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 6358#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (or (<= 7 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base)))) (= cstrncat_~s~0.offset 0)), 6359#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (or (<= 7 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (= cstrncat_~s~0.offset 0)), 6360#(and (= cstrncat_~s~0.offset 1) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))))), 6361#(and (= cstrncat_~s~0.offset 1) (or (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))))), 6362#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1))))))), 6363#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1))))))), 6364#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))))), 6365#(or (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))))), 6366#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 6367#(or (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))))] [2018-04-11 12:51:21,283 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:21,283 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-04-11 12:51:21,283 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-04-11 12:51:21,283 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=359, Unknown=0, NotChecked=0, Total=420 [2018-04-11 12:51:21,283 INFO L87 Difference]: Start difference. First operand 213 states and 254 transitions. Second operand 21 states. [2018-04-11 12:51:22,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:22,478 INFO L93 Difference]: Finished difference Result 516 states and 588 transitions. [2018-04-11 12:51:22,483 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-04-11 12:51:22,483 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 38 [2018-04-11 12:51:22,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:22,484 INFO L225 Difference]: With dead ends: 516 [2018-04-11 12:51:22,484 INFO L226 Difference]: Without dead ends: 512 [2018-04-11 12:51:22,484 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 377 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=248, Invalid=1474, Unknown=0, NotChecked=0, Total=1722 [2018-04-11 12:51:22,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 512 states. [2018-04-11 12:51:22,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 512 to 219. [2018-04-11 12:51:22,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 219 states. [2018-04-11 12:51:22,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 262 transitions. [2018-04-11 12:51:22,488 INFO L78 Accepts]: Start accepts. Automaton has 219 states and 262 transitions. Word has length 38 [2018-04-11 12:51:22,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:22,488 INFO L459 AbstractCegarLoop]: Abstraction has 219 states and 262 transitions. [2018-04-11 12:51:22,488 INFO L460 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-04-11 12:51:22,488 INFO L276 IsEmpty]: Start isEmpty. Operand 219 states and 262 transitions. [2018-04-11 12:51:22,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-04-11 12:51:22,489 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:22,489 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:22,489 INFO L408 AbstractCegarLoop]: === Iteration 23 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:22,489 INFO L82 PathProgramCache]: Analyzing trace with hash -709485801, now seen corresponding path program 1 times [2018-04-11 12:51:22,490 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:22,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:22,495 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:22,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:22,548 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 12:51:22,548 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-11 12:51:22,548 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:22,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:22,548 INFO L182 omatonBuilderFactory]: Interpolants [7152#(= (store |#valid| |main_#t~malloc14.base| 0) |old(#valid)|), 7147#true, 7148#false, 7149#(= |#valid| |old(#valid)|), 7150#(and (= (select |#valid| |main_#t~malloc13.base|) 1) (= |old(#valid)| (store |#valid| |main_#t~malloc13.base| 0))), 7151#(and (= (store (store |#valid| |main_#t~malloc14.base| 0) |main_#t~malloc13.base| 0) |old(#valid)|) (not (= |main_#t~malloc13.base| |main_#t~malloc14.base|)))] [2018-04-11 12:51:22,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:22,548 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-11 12:51:22,549 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-11 12:51:22,549 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-04-11 12:51:22,549 INFO L87 Difference]: Start difference. First operand 219 states and 262 transitions. Second operand 6 states. [2018-04-11 12:51:22,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:22,643 INFO L93 Difference]: Finished difference Result 218 states and 261 transitions. [2018-04-11 12:51:22,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-11 12:51:22,644 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 39 [2018-04-11 12:51:22,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:22,644 INFO L225 Difference]: With dead ends: 218 [2018-04-11 12:51:22,644 INFO L226 Difference]: Without dead ends: 138 [2018-04-11 12:51:22,645 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-04-11 12:51:22,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-04-11 12:51:22,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 130. [2018-04-11 12:51:22,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-04-11 12:51:22,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 148 transitions. [2018-04-11 12:51:22,648 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 148 transitions. Word has length 39 [2018-04-11 12:51:22,648 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:22,648 INFO L459 AbstractCegarLoop]: Abstraction has 130 states and 148 transitions. [2018-04-11 12:51:22,648 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-11 12:51:22,648 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 148 transitions. [2018-04-11 12:51:22,648 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-04-11 12:51:22,648 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:22,648 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:22,649 INFO L408 AbstractCegarLoop]: === Iteration 24 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:22,649 INFO L82 PathProgramCache]: Analyzing trace with hash -95111334, now seen corresponding path program 2 times [2018-04-11 12:51:22,649 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:22,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:22,659 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:23,006 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:23,007 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:23,007 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-04-11 12:51:23,007 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:23,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:23,008 INFO L182 omatonBuilderFactory]: Interpolants [7520#(and (<= 2 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base))), 7521#(and (<= 2 |cstrncat_#t~post4.offset|) (<= (+ |cstrncat_#t~post4.offset| 1) (select |#length| |cstrncat_#t~post4.base|))), 7505#true, 7506#false, 7507#(= (select |#valid| |main_#t~malloc13.base|) 1), 7508#(= (select |#valid| main_~nondetString1~0.base) 1), 7509#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= 0 |main_#t~malloc14.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|))), 7510#(and (= 0 main_~nondetString2~0.offset) (or (not (= (+ main_~nondetString2~0.offset main_~length2~0) 2)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 7511#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (<= (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)) 1) (<= 3 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 7512#(and (= 0 |cstrncat_#in~s2.offset|) (or (and (not (= |cstrncat_#in~s1.base| |cstrncat_#in~s2.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s2.base|) 1))) (<= (select |#length| |cstrncat_#in~s2.base|) 1) (<= 3 (select |#length| |cstrncat_#in~s2.base|)))), 7513#(and (= 0 cstrncat_~s2.offset) (or (<= 3 (select |#length| cstrncat_~s2.base)) (<= (select |#length| cstrncat_~s2.base) 1) (and (= 0 (select (select |#memory_int| cstrncat_~s2.base) 1)) (not (= cstrncat_~s~0.base cstrncat_~s2.base))))), 7514#(and (or (and (<= (+ |cstrncat_#t~post4.offset| 1) cstrncat_~s2.offset) (or (<= (+ cstrncat_~s2.offset 2) (+ |cstrncat_#t~post4.offset| (select |#length| cstrncat_~s2.base))) (<= (+ |cstrncat_#t~post4.offset| (select |#length| cstrncat_~s2.base)) cstrncat_~s2.offset))) (and (= |cstrncat_#t~post4.base| cstrncat_~s2.base) (<= cstrncat_~s2.offset (+ |cstrncat_#t~post4.offset| 1)) (not (= |cstrncat_#t~post4.base| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| |cstrncat_#t~post4.base|) 1)) (<= (+ |cstrncat_#t~post4.offset| 1) cstrncat_~s2.offset))) (= |cstrncat_#t~post4.offset| 0)), 7515#(or (and (<= 1 cstrncat_~s2.offset) (or (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 2) (select |#length| cstrncat_~s2.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s2.base) 1)) (<= 1 cstrncat_~s2.offset) (not (= cstrncat_~s~0.base cstrncat_~s2.base)) (<= cstrncat_~s2.offset 1))), 7516#(or (and (<= 1 cstrncat_~s2.offset) (or (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 2) (select |#length| cstrncat_~s2.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s2.base) 1)) (<= 1 cstrncat_~s2.offset) (<= cstrncat_~s2.offset 1))), 7517#(or (and (<= 2 cstrncat_~s2.offset) (or (<= (select |#length| |cstrncat_#t~post4.base|) |cstrncat_#t~post4.offset|) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base)))) (and (= 0 (select (select |#memory_int| |cstrncat_#t~post4.base|) |cstrncat_#t~post4.offset|)) (= 1 |cstrncat_#t~post4.offset|))), 7518#(or (= 0 |cstrncat_#t~mem5|) (and (<= 2 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base)))), 7519#(or (not |cstrncat_#t~short6|) (and (<= 2 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base))))] [2018-04-11 12:51:23,008 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:23,008 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-04-11 12:51:23,008 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-04-11 12:51:23,008 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2018-04-11 12:51:23,008 INFO L87 Difference]: Start difference. First operand 130 states and 148 transitions. Second operand 17 states. [2018-04-11 12:51:23,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:23,444 INFO L93 Difference]: Finished difference Result 162 states and 179 transitions. [2018-04-11 12:51:23,444 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-04-11 12:51:23,444 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 39 [2018-04-11 12:51:23,445 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:23,445 INFO L225 Difference]: With dead ends: 162 [2018-04-11 12:51:23,445 INFO L226 Difference]: Without dead ends: 162 [2018-04-11 12:51:23,445 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 57 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=98, Invalid=604, Unknown=0, NotChecked=0, Total=702 [2018-04-11 12:51:23,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-04-11 12:51:23,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 137. [2018-04-11 12:51:23,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-04-11 12:51:23,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 158 transitions. [2018-04-11 12:51:23,448 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 158 transitions. Word has length 39 [2018-04-11 12:51:23,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:23,448 INFO L459 AbstractCegarLoop]: Abstraction has 137 states and 158 transitions. [2018-04-11 12:51:23,449 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-04-11 12:51:23,449 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 158 transitions. [2018-04-11 12:51:23,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-04-11 12:51:23,449 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:23,449 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:23,449 INFO L408 AbstractCegarLoop]: === Iteration 25 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:23,450 INFO L82 PathProgramCache]: Analyzing trace with hash 1346524950, now seen corresponding path program 1 times [2018-04-11 12:51:23,450 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:23,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:23,468 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:23,752 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:23,752 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:23,752 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-04-11 12:51:23,752 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:23,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:23,753 INFO L182 omatonBuilderFactory]: Interpolants [7841#true, 7842#false, 7843#(<= (+ main_~n~0 main_~length2~0) main_~length1~0), 7844#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 7845#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7846#(and (= 0 main_~nondetString1~0.offset) (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7847#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7848#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))), 7849#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base))), 7850#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~s1.base|))), 7851#(and (= 0 cstrncat_~s2.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base)) (select |#length| cstrncat_~s~0.base)) (= cstrncat_~s~0.offset 0)), 7852#(and (<= (+ cstrncat_~n |cstrncat_#t~post4.offset| (select |#length| cstrncat_~s2.base) 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)) (= |cstrncat_#t~post4.offset| 0) (= cstrncat_~s~0.offset 0)), 7853#(and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)) (= cstrncat_~s~0.offset 0)), 7854#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 7855#(and (<= 1 cstrncat_~s~0.offset) (<= (+ (select |#length| |cstrncat_#t~post4.base|) cstrncat_~n cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post4.offset|))), 7856#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base))), 7857#(and (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)), 7858#(and (or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) |cstrncat_#t~short6|) (<= 2 cstrncat_~s~0.offset)), 7859#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset))] [2018-04-11 12:51:23,753 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:23,753 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-04-11 12:51:23,753 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-04-11 12:51:23,753 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=297, Unknown=0, NotChecked=0, Total=342 [2018-04-11 12:51:23,753 INFO L87 Difference]: Start difference. First operand 137 states and 158 transitions. Second operand 19 states. [2018-04-11 12:51:24,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:24,148 INFO L93 Difference]: Finished difference Result 173 states and 195 transitions. [2018-04-11 12:51:24,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-04-11 12:51:24,148 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 40 [2018-04-11 12:51:24,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:24,149 INFO L225 Difference]: With dead ends: 173 [2018-04-11 12:51:24,149 INFO L226 Difference]: Without dead ends: 169 [2018-04-11 12:51:24,149 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 190 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=147, Invalid=845, Unknown=0, NotChecked=0, Total=992 [2018-04-11 12:51:24,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states. [2018-04-11 12:51:24,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 162. [2018-04-11 12:51:24,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-04-11 12:51:24,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 186 transitions. [2018-04-11 12:51:24,151 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 186 transitions. Word has length 40 [2018-04-11 12:51:24,151 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:24,152 INFO L459 AbstractCegarLoop]: Abstraction has 162 states and 186 transitions. [2018-04-11 12:51:24,152 INFO L460 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-04-11 12:51:24,152 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 186 transitions. [2018-04-11 12:51:24,152 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-04-11 12:51:24,152 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:24,152 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:24,152 INFO L408 AbstractCegarLoop]: === Iteration 26 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:24,153 INFO L82 PathProgramCache]: Analyzing trace with hash 1346515914, now seen corresponding path program 1 times [2018-04-11 12:51:24,153 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:24,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:24,163 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:24,355 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:24,355 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:24,355 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17] total 17 [2018-04-11 12:51:24,356 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:24,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:24,356 INFO L182 omatonBuilderFactory]: Interpolants [8224#(and (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 8225#(and (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 8226#(and (= 0 |main_#t~malloc14.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 8227#(and (= 0 main_~nondetString2~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 8228#(and (= 0 main_~nondetString2~0.offset) (<= (+ main_~nondetString1~0.offset main_~length2~0) (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 8229#(and (= 0 main_~nondetString2~0.offset) (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 8230#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (<= (select |#length| |cstrncat_#in~s2.base|) (select |#length| |cstrncat_#in~s1.base|))), 8231#(and (= 0 cstrncat_~s2.offset) (= cstrncat_~s~0.offset 0) (<= (select |#length| cstrncat_~s2.base) (select |#length| cstrncat_~s~0.base))), 8232#(and (= |cstrncat_#t~post4.offset| 0) (<= (+ |cstrncat_#t~post4.offset| (select |#length| cstrncat_~s2.base) 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)) (= cstrncat_~s~0.offset 0)), 8233#(and (<= (+ (select |#length| cstrncat_~s2.base) 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)) (= cstrncat_~s~0.offset 0)), 8234#(and (<= 1 cstrncat_~s~0.offset) (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 8235#(and (<= 1 cstrncat_~s~0.offset) (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 8236#(and (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)) (<= 2 cstrncat_~s~0.offset)), 8237#(and (<= (+ (select |#length| |cstrncat_#t~post4.base|) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post4.offset|)) (<= 2 cstrncat_~s~0.offset)), 8238#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)), 8221#true, 8222#false, 8223#(<= (+ main_~n~0 main_~length2~0) main_~length1~0)] [2018-04-11 12:51:24,356 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:24,356 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-04-11 12:51:24,356 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-04-11 12:51:24,357 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=263, Unknown=0, NotChecked=0, Total=306 [2018-04-11 12:51:24,357 INFO L87 Difference]: Start difference. First operand 162 states and 186 transitions. Second operand 18 states. [2018-04-11 12:51:24,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:24,666 INFO L93 Difference]: Finished difference Result 166 states and 187 transitions. [2018-04-11 12:51:24,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-04-11 12:51:24,666 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 40 [2018-04-11 12:51:24,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:24,667 INFO L225 Difference]: With dead ends: 166 [2018-04-11 12:51:24,667 INFO L226 Difference]: Without dead ends: 163 [2018-04-11 12:51:24,667 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 154 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=134, Invalid=736, Unknown=0, NotChecked=0, Total=870 [2018-04-11 12:51:24,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-04-11 12:51:24,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 162. [2018-04-11 12:51:24,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-04-11 12:51:24,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 184 transitions. [2018-04-11 12:51:24,670 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 184 transitions. Word has length 40 [2018-04-11 12:51:24,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:24,670 INFO L459 AbstractCegarLoop]: Abstraction has 162 states and 184 transitions. [2018-04-11 12:51:24,670 INFO L460 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-04-11 12:51:24,670 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 184 transitions. [2018-04-11 12:51:24,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-04-11 12:51:24,671 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:24,671 INFO L355 BasicCegarLoop]: trace histogram [8, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:24,671 INFO L408 AbstractCegarLoop]: === Iteration 27 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:24,671 INFO L82 PathProgramCache]: Analyzing trace with hash 1926731901, now seen corresponding path program 5 times [2018-04-11 12:51:24,672 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:24,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:24,685 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:25,120 WARN L151 SmtUtils]: Spent 138ms on a formula simplification. DAG size of input: 82 DAG size of output 66 [2018-04-11 12:51:25,262 WARN L151 SmtUtils]: Spent 115ms on a formula simplification. DAG size of input: 65 DAG size of output 52 [2018-04-11 12:51:25,494 WARN L151 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 68 DAG size of output 55 [2018-04-11 12:51:25,639 WARN L151 SmtUtils]: Spent 126ms on a formula simplification. DAG size of input: 81 DAG size of output 57 [2018-04-11 12:51:25,775 WARN L151 SmtUtils]: Spent 111ms on a formula simplification. DAG size of input: 84 DAG size of output 60 [2018-04-11 12:51:26,085 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:26,085 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:26,085 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-04-11 12:51:26,085 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:26,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:26,086 INFO L182 omatonBuilderFactory]: Interpolants [8608#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 8609#(or (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 8610#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 8611#(or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 8612#(<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)), 8613#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 8614#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 8591#true, 8592#false, 8593#(<= 1 main_~n~0), 8594#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 8595#(and (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 8596#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 8597#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 8598#(and (= 0 main_~nondetString1~0.offset) (or (and (<= 5 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (<= 4 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1)))) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 6 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1))))))) (and (or (<= 8 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (<= 7 (select |#length| main_~nondetString1~0.base)))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 8599#(and (= 0 |cstrncat_#in~s1.offset|) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1)) (- 1))))) (and (<= 6 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- 3)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1)) (- 1)))) (<= 5 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 7 (select |#length| |cstrncat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1)) (- 1)))) (<= 8 (select |#length| |cstrncat_#in~s1.base|)))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 8600#(and (or (and (or (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (<= 7 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 6 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base)))) (= cstrncat_~s~0.offset 0)), 8601#(and (or (and (or (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (<= 7 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 6 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (= cstrncat_~s~0.offset 0)), 8602#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))) (= cstrncat_~s~0.offset 1)), 8603#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (= cstrncat_~s~0.offset 1)), 8604#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))))), 8605#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 8606#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))), 8607#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))))] [2018-04-11 12:51:26,086 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:26,086 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-04-11 12:51:26,086 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-04-11 12:51:26,086 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=469, Unknown=0, NotChecked=0, Total=552 [2018-04-11 12:51:26,086 INFO L87 Difference]: Start difference. First operand 162 states and 184 transitions. Second operand 24 states. [2018-04-11 12:51:27,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:27,444 INFO L93 Difference]: Finished difference Result 232 states and 257 transitions. [2018-04-11 12:51:27,444 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-04-11 12:51:27,444 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 41 [2018-04-11 12:51:27,444 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:27,445 INFO L225 Difference]: With dead ends: 232 [2018-04-11 12:51:27,445 INFO L226 Difference]: Without dead ends: 218 [2018-04-11 12:51:27,445 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 413 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=302, Invalid=1590, Unknown=0, NotChecked=0, Total=1892 [2018-04-11 12:51:27,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states. [2018-04-11 12:51:27,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 168. [2018-04-11 12:51:27,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 168 states. [2018-04-11 12:51:27,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168 states to 168 states and 191 transitions. [2018-04-11 12:51:27,447 INFO L78 Accepts]: Start accepts. Automaton has 168 states and 191 transitions. Word has length 41 [2018-04-11 12:51:27,447 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:27,447 INFO L459 AbstractCegarLoop]: Abstraction has 168 states and 191 transitions. [2018-04-11 12:51:27,447 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-04-11 12:51:27,447 INFO L276 IsEmpty]: Start isEmpty. Operand 168 states and 191 transitions. [2018-04-11 12:51:27,448 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-04-11 12:51:27,448 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:27,448 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:27,448 INFO L408 AbstractCegarLoop]: === Iteration 28 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:27,448 INFO L82 PathProgramCache]: Analyzing trace with hash -103177675, now seen corresponding path program 1 times [2018-04-11 12:51:27,448 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:27,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:27,454 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:27,716 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:27,716 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:27,716 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-04-11 12:51:27,716 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:27,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:27,716 INFO L182 omatonBuilderFactory]: Interpolants [9056#false, 9057#(<= (+ main_~n~0 main_~length2~0) main_~length1~0), 9058#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 9059#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9060#(and (= 0 main_~nondetString1~0.offset) (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9061#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9062#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))), 9063#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base))), 9064#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~s1.base|))), 9065#(and (= 0 cstrncat_~s2.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base)) (select |#length| cstrncat_~s~0.base)) (= cstrncat_~s~0.offset 0)), 9066#(and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 1)) (= 0 cstrncat_~s2.offset)), 9067#(and (= |cstrncat_#t~post4.offset| 0) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) |cstrncat_#t~post4.offset| cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 9068#(<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)), 9069#(<= (+ (select |#length| |cstrncat_#t~post4.base|) cstrncat_~n cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post4.offset|)), 9070#(<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)), 9071#(and (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 9072#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 9073#(or (and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))) |cstrncat_#t~short6|), 9074#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 9055#true] [2018-04-11 12:51:27,717 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:27,717 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-04-11 12:51:27,717 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-04-11 12:51:27,717 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=329, Unknown=0, NotChecked=0, Total=380 [2018-04-11 12:51:27,717 INFO L87 Difference]: Start difference. First operand 168 states and 191 transitions. Second operand 20 states. [2018-04-11 12:51:28,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:28,264 INFO L93 Difference]: Finished difference Result 199 states and 224 transitions. [2018-04-11 12:51:28,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-04-11 12:51:28,264 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 43 [2018-04-11 12:51:28,265 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:28,265 INFO L225 Difference]: With dead ends: 199 [2018-04-11 12:51:28,265 INFO L226 Difference]: Without dead ends: 195 [2018-04-11 12:51:28,265 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 420 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=275, Invalid=1447, Unknown=0, NotChecked=0, Total=1722 [2018-04-11 12:51:28,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states. [2018-04-11 12:51:28,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 193. [2018-04-11 12:51:28,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 193 states. [2018-04-11 12:51:28,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 218 transitions. [2018-04-11 12:51:28,267 INFO L78 Accepts]: Start accepts. Automaton has 193 states and 218 transitions. Word has length 43 [2018-04-11 12:51:28,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:28,268 INFO L459 AbstractCegarLoop]: Abstraction has 193 states and 218 transitions. [2018-04-11 12:51:28,268 INFO L460 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-04-11 12:51:28,268 INFO L276 IsEmpty]: Start isEmpty. Operand 193 states and 218 transitions. [2018-04-11 12:51:28,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-04-11 12:51:28,268 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:28,268 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:28,268 INFO L408 AbstractCegarLoop]: === Iteration 29 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:28,268 INFO L82 PathProgramCache]: Analyzing trace with hash -103186711, now seen corresponding path program 1 times [2018-04-11 12:51:28,269 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:28,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:28,275 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:28,528 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 5 proven. 14 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-04-11 12:51:28,528 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:28,528 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-04-11 12:51:28,528 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:28,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:28,528 INFO L182 omatonBuilderFactory]: Interpolants [9511#true, 9512#false, 9513#(<= 1 main_~n~0), 9514#(<= (+ main_~length2~0 1) main_~length1~0), 9515#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (<= (+ main_~length2~0 1) main_~length1~0) (= (select |#valid| |main_#t~malloc13.base|) 1) (= 0 |main_#t~malloc13.offset|)), 9516#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length2~0 1) main_~length1~0) (= (select |#valid| main_~nondetString1~0.base) 1)), 9517#(and (= 0 main_~nondetString1~0.offset) (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length2~0 1) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|))), 9518#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length2~0 1) main_~length1~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 9519#(and (<= (+ main_~length2~0 1) (select |#length| main_~nondetString1~0.base)) (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 9520#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base))), 9521#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (<= (+ (select |#length| |cstrncat_#in~s2.base|) 1) (select |#length| |cstrncat_#in~s1.base|))), 9522#(and (<= (+ (select |#length| cstrncat_~s2.base) 1) (select |#length| cstrncat_~s~0.base)) (= 0 cstrncat_~s2.offset) (= cstrncat_~s~0.offset 0)), 9523#(and (= 0 cstrncat_~s2.offset) (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))), 9524#(and (= |cstrncat_#t~post4.offset| 0) (<= (+ (select |#length| cstrncat_~s2.base) |cstrncat_#t~post4.offset| cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 9525#(<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)), 9526#(<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)), 9527#(and (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)) (<= 0 cstrncat_~s~0.offset)), 9528#(and (<= 1 cstrncat_~s~0.offset) (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 9529#(and (<= 1 cstrncat_~s~0.offset) (<= (+ (select |#length| |cstrncat_#t~post4.base|) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post4.offset|))), 9530#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))] [2018-04-11 12:51:28,529 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 5 proven. 14 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-04-11 12:51:28,529 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-04-11 12:51:28,529 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-04-11 12:51:28,529 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=325, Unknown=0, NotChecked=0, Total=380 [2018-04-11 12:51:28,529 INFO L87 Difference]: Start difference. First operand 193 states and 218 transitions. Second operand 20 states. [2018-04-11 12:51:28,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:28,985 INFO L93 Difference]: Finished difference Result 194 states and 217 transitions. [2018-04-11 12:51:28,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-04-11 12:51:28,985 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 43 [2018-04-11 12:51:28,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:28,986 INFO L225 Difference]: With dead ends: 194 [2018-04-11 12:51:28,986 INFO L226 Difference]: Without dead ends: 194 [2018-04-11 12:51:28,986 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=167, Invalid=889, Unknown=0, NotChecked=0, Total=1056 [2018-04-11 12:51:28,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194 states. [2018-04-11 12:51:28,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194 to 168. [2018-04-11 12:51:28,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 168 states. [2018-04-11 12:51:28,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168 states to 168 states and 191 transitions. [2018-04-11 12:51:28,989 INFO L78 Accepts]: Start accepts. Automaton has 168 states and 191 transitions. Word has length 43 [2018-04-11 12:51:28,989 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:28,989 INFO L459 AbstractCegarLoop]: Abstraction has 168 states and 191 transitions. [2018-04-11 12:51:28,989 INFO L460 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-04-11 12:51:28,989 INFO L276 IsEmpty]: Start isEmpty. Operand 168 states and 191 transitions. [2018-04-11 12:51:28,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-04-11 12:51:28,990 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:28,990 INFO L355 BasicCegarLoop]: trace histogram [9, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:28,990 INFO L408 AbstractCegarLoop]: === Iteration 30 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:28,990 INFO L82 PathProgramCache]: Analyzing trace with hash 1327075962, now seen corresponding path program 6 times [2018-04-11 12:51:28,990 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:29,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:29,004 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:29,551 WARN L151 SmtUtils]: Spent 178ms on a formula simplification. DAG size of input: 100 DAG size of output 75 [2018-04-11 12:51:29,717 WARN L151 SmtUtils]: Spent 143ms on a formula simplification. DAG size of input: 82 DAG size of output 60 [2018-04-11 12:51:29,870 WARN L151 SmtUtils]: Spent 137ms on a formula simplification. DAG size of input: 82 DAG size of output 60 [2018-04-11 12:51:30,045 WARN L151 SmtUtils]: Spent 159ms on a formula simplification. DAG size of input: 85 DAG size of output 63 [2018-04-11 12:51:30,205 WARN L151 SmtUtils]: Spent 130ms on a formula simplification. DAG size of input: 101 DAG size of output 67 [2018-04-11 12:51:30,379 WARN L151 SmtUtils]: Spent 141ms on a formula simplification. DAG size of input: 104 DAG size of output 70 [2018-04-11 12:51:30,621 WARN L151 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 76 DAG size of output 63 [2018-04-11 12:51:31,050 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:31,050 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:31,050 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24] total 24 [2018-04-11 12:51:31,050 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:31,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:31,051 INFO L182 omatonBuilderFactory]: Interpolants [9920#false, 9921#(<= 1 main_~n~0), 9922#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 9923#(and (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 9924#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 9925#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 9926#(and (= 0 main_~nondetString1~0.offset) (or (and (<= 5 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (and (<= 6 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (<= 4 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1)))) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 7 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 8 (select |#length| main_~nondetString1~0.base)) (or (<= 9 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 9927#(and (= 0 |cstrncat_#in~s1.offset|) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (<= 8 (select |#length| |cstrncat_#in~s1.base|)) (or (<= 9 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1)) (- 1)))))) (and (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1)) (- 1)))) (<= 6 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 7 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- 3)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1)) (- 1)))) (<= 5 (select |#length| |cstrncat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 9928#(and (or (and (or (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (<= 8 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base)))) (= cstrncat_~s~0.offset 0)), 9929#(and (or (and (or (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (<= 8 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (= cstrncat_~s~0.offset 0)), 9930#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))) (= cstrncat_~s~0.offset 1)), 9931#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))) (= cstrncat_~s~0.offset 1)), 9932#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))) (<= 2 cstrncat_~s~0.offset))), 9933#(or (and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))) (<= 2 cstrncat_~s~0.offset)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 9934#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= 3 cstrncat_~s~0.offset) (or (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))))), 9935#(or (and (<= 3 cstrncat_~s~0.offset) (or (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 9936#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= 4 cstrncat_~s~0.offset) (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))))))), 9937#(or (and (<= 4 cstrncat_~s~0.offset) (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 9938#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))) (<= 5 cstrncat_~s~0.offset)), 9939#(and (<= 5 cstrncat_~s~0.offset) (or (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))))), 9940#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= 6 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 9941#(or (and (<= 6 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 9942#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 7 cstrncat_~s~0.offset)), 9943#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 8 cstrncat_~s~0.offset)), 9919#true] [2018-04-11 12:51:31,051 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:31,051 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-04-11 12:51:31,051 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-04-11 12:51:31,051 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=545, Unknown=0, NotChecked=0, Total=600 [2018-04-11 12:51:31,052 INFO L87 Difference]: Start difference. First operand 168 states and 191 transitions. Second operand 25 states. [2018-04-11 12:51:32,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:32,598 INFO L93 Difference]: Finished difference Result 240 states and 271 transitions. [2018-04-11 12:51:32,598 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-04-11 12:51:32,598 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 44 [2018-04-11 12:51:32,598 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:32,599 INFO L225 Difference]: With dead ends: 240 [2018-04-11 12:51:32,599 INFO L226 Difference]: Without dead ends: 230 [2018-04-11 12:51:32,599 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 396 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=165, Invalid=1815, Unknown=0, NotChecked=0, Total=1980 [2018-04-11 12:51:32,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230 states. [2018-04-11 12:51:32,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230 to 174. [2018-04-11 12:51:32,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-04-11 12:51:32,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 198 transitions. [2018-04-11 12:51:32,601 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 198 transitions. Word has length 44 [2018-04-11 12:51:32,601 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:32,602 INFO L459 AbstractCegarLoop]: Abstraction has 174 states and 198 transitions. [2018-04-11 12:51:32,602 INFO L460 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-04-11 12:51:32,602 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 198 transitions. [2018-04-11 12:51:32,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-04-11 12:51:32,602 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:32,602 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:32,602 INFO L408 AbstractCegarLoop]: === Iteration 31 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:32,602 INFO L82 PathProgramCache]: Analyzing trace with hash 1997049526, now seen corresponding path program 2 times [2018-04-11 12:51:32,603 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:32,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:32,611 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:33,040 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 5 proven. 19 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:33,041 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:33,041 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21] total 21 [2018-04-11 12:51:33,041 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:33,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:33,041 INFO L182 omatonBuilderFactory]: Interpolants [10400#(<= (+ main_~n~0 main_~length2~0) main_~length1~0), 10401#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 10402#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 10403#(and (or (not (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|))) (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (and (or (<= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|))) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (= main_~nondetString1~0.offset 0)), 10404#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (and (or (<= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (or (not (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (= main_~nondetString1~0.offset 0)), 10405#(and (= 0 main_~nondetString2~0.offset) (or (and (or (<= (+ main_~n~0 3) (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (<= (+ main_~nondetString1~0.offset main_~length2~0) 1)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)))) (= main_~nondetString1~0.offset 0)), 10406#(and (= 0 main_~nondetString2~0.offset) (or (<= (+ main_~n~0 3) (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset) 1) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)))) (= main_~nondetString1~0.offset 0)), 10407#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (or (<= (select |#length| |cstrncat_#in~s2.base|) 1) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (<= (+ |cstrncat_#in~n| 3) (select |#length| |cstrncat_#in~s1.base|)))), 10408#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (<= (+ cstrncat_~n 3) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 1)) (= 0 cstrncat_~s2.offset) (= cstrncat_~s~0.offset 0)), 10409#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 1 cstrncat_~s~0.offset)) (and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 1)))) (= 0 cstrncat_~s2.offset)), 10410#(and (= 0 cstrncat_~s2.offset) (or (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 1 cstrncat_~s~0.offset)) (and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 1))))), 10411#(and (or (<= (select |#length| cstrncat_~s2.base) 1) (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))) (= 0 cstrncat_~s2.offset) (<= 2 cstrncat_~s~0.offset)), 10412#(and (= |cstrncat_#t~post4.offset| 0) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (+ (select |#length| cstrncat_~s2.base) |cstrncat_#t~post4.offset|) cstrncat_~s2.offset)) (<= 2 cstrncat_~s~0.offset)), 10413#(and (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)) (<= 2 cstrncat_~s~0.offset)), 10414#(and (<= 3 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset))), 10415#(and (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| |cstrncat_#t~post4.base|) |cstrncat_#t~post4.offset|)) (<= 3 cstrncat_~s~0.offset)), 10416#(and (<= 3 cstrncat_~s~0.offset) (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 10417#(and (<= 4 cstrncat_~s~0.offset) (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 10418#(and (<= 4 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) |cstrncat_#t~short6|)), 10419#(and (<= 4 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 10398#true, 10399#false] [2018-04-11 12:51:33,041 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 5 proven. 19 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:33,041 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-04-11 12:51:33,041 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-04-11 12:51:33,042 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=408, Unknown=0, NotChecked=0, Total=462 [2018-04-11 12:51:33,042 INFO L87 Difference]: Start difference. First operand 174 states and 198 transitions. Second operand 22 states. [2018-04-11 12:51:33,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:33,692 INFO L93 Difference]: Finished difference Result 215 states and 239 transitions. [2018-04-11 12:51:33,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-04-11 12:51:33,693 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 46 [2018-04-11 12:51:33,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:33,693 INFO L225 Difference]: With dead ends: 215 [2018-04-11 12:51:33,693 INFO L226 Difference]: Without dead ends: 211 [2018-04-11 12:51:33,694 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 202 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=170, Invalid=1162, Unknown=0, NotChecked=0, Total=1332 [2018-04-11 12:51:33,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states. [2018-04-11 12:51:33,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 199. [2018-04-11 12:51:33,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 199 states. [2018-04-11 12:51:33,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 225 transitions. [2018-04-11 12:51:33,696 INFO L78 Accepts]: Start accepts. Automaton has 199 states and 225 transitions. Word has length 46 [2018-04-11 12:51:33,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:33,696 INFO L459 AbstractCegarLoop]: Abstraction has 199 states and 225 transitions. [2018-04-11 12:51:33,696 INFO L460 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-04-11 12:51:33,697 INFO L276 IsEmpty]: Start isEmpty. Operand 199 states and 225 transitions. [2018-04-11 12:51:33,697 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-04-11 12:51:33,697 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:33,697 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:33,697 INFO L408 AbstractCegarLoop]: === Iteration 32 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:33,697 INFO L82 PathProgramCache]: Analyzing trace with hash 1997040490, now seen corresponding path program 2 times [2018-04-11 12:51:33,698 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:33,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:33,706 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:34,056 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 3 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:34,056 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:34,056 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21] total 21 [2018-04-11 12:51:34,056 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:34,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:34,056 INFO L182 omatonBuilderFactory]: Interpolants [10880#(and (or (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 1)) (<= cstrncat_~n 0)) (<= 3 cstrncat_~s~0.offset) (<= 0 cstrncat_~n)), 10881#(or (and (<= 3 cstrncat_~s~0.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 1)) (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n)) (not |cstrncat_#t~short6|)), 10882#(and (<= 3 cstrncat_~s~0.offset) (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 10883#(and (<= 4 cstrncat_~s~0.offset) (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 10884#(and (<= 4 cstrncat_~s~0.offset) (<= (+ (select |#length| |cstrncat_#t~post4.base|) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post4.offset|))), 10885#(and (<= 4 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 10864#true, 10865#false, 10866#(<= 1 main_~n~0), 10867#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 10868#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 10869#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 10870#(and (= 0 main_~nondetString1~0.offset) (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 10871#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 10872#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))), 10873#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)), 10874#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~s1.base|)) (<= 1 |cstrncat_#in~n|)), 10875#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base)) (select |#length| cstrncat_~s~0.base)) (= cstrncat_~s~0.offset 0)), 10876#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 1)) (= 0 cstrncat_~s2.offset)), 10877#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 2)) (= 0 cstrncat_~s2.offset) (<= 2 cstrncat_~s~0.offset)), 10878#(and (<= 1 cstrncat_~n) (= |cstrncat_#t~post4.offset| 0) (<= (+ cstrncat_~n |cstrncat_#t~post4.offset| (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 1)) (<= 2 cstrncat_~s~0.offset)), 10879#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 1)) (<= 2 cstrncat_~s~0.offset))] [2018-04-11 12:51:34,056 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 3 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:34,057 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-04-11 12:51:34,057 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-04-11 12:51:34,057 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=403, Unknown=0, NotChecked=0, Total=462 [2018-04-11 12:51:34,057 INFO L87 Difference]: Start difference. First operand 199 states and 225 transitions. Second operand 22 states. [2018-04-11 12:51:34,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:34,582 INFO L93 Difference]: Finished difference Result 204 states and 228 transitions. [2018-04-11 12:51:34,582 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-04-11 12:51:34,582 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 46 [2018-04-11 12:51:34,583 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:34,583 INFO L225 Difference]: With dead ends: 204 [2018-04-11 12:51:34,583 INFO L226 Difference]: Without dead ends: 204 [2018-04-11 12:51:34,583 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 309 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=175, Invalid=1157, Unknown=0, NotChecked=0, Total=1332 [2018-04-11 12:51:34,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states. [2018-04-11 12:51:34,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 174. [2018-04-11 12:51:34,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-04-11 12:51:34,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 198 transitions. [2018-04-11 12:51:34,586 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 198 transitions. Word has length 46 [2018-04-11 12:51:34,586 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:34,586 INFO L459 AbstractCegarLoop]: Abstraction has 174 states and 198 transitions. [2018-04-11 12:51:34,586 INFO L460 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-04-11 12:51:34,587 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 198 transitions. [2018-04-11 12:51:34,587 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-04-11 12:51:34,587 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:34,587 INFO L355 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:34,587 INFO L408 AbstractCegarLoop]: === Iteration 33 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:34,587 INFO L82 PathProgramCache]: Analyzing trace with hash 110142485, now seen corresponding path program 3 times [2018-04-11 12:51:34,588 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:34,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:34,597 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:34,786 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-04-11 12:51:34,786 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:34,786 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-04-11 12:51:34,786 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:34,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:34,787 INFO L182 omatonBuilderFactory]: Interpolants [11296#(= (select |#valid| |main_#t~malloc13.base|) 1), 11297#(= (select |#valid| main_~nondetString1~0.base) 1), 11298#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= 0 |main_#t~malloc14.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|))), 11299#(and (= main_~nondetString2~0.offset 0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 11300#(and (= main_~nondetString2~0.offset 0) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (- 1))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 11301#(and (not (= |cstrncat_#in~s1.base| |cstrncat_#in~s2.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s2.base|) (+ (select |#length| |cstrncat_#in~s2.base|) (- 1))))), 11302#(and (= 0 (select (select |#memory_int| cstrncat_~s2.base) (+ (select |#length| cstrncat_~s2.base) (- 1)))) (not (= cstrncat_~s~0.base cstrncat_~s2.base))), 11303#(and (= |cstrncat_#t~post4.base| cstrncat_~s2.base) (= 0 (select (select |#memory_int| |cstrncat_#t~post4.base|) (+ (select |#length| cstrncat_~s2.base) (- 1)))) (not (= cstrncat_~s~0.base cstrncat_~s2.base))), 11304#(= 0 (select (select |#memory_int| cstrncat_~s2.base) (+ (select |#length| cstrncat_~s2.base) (- 1)))), 11305#(or (and (<= (+ |cstrncat_#t~post4.offset| 1) cstrncat_~s2.offset) (or (<= (select |#length| |cstrncat_#t~post4.base|) |cstrncat_#t~post4.offset|) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base)))) (= 0 (select (select |#memory_int| |cstrncat_#t~post4.base|) |cstrncat_#t~post4.offset|))), 11306#(or (and (<= 1 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base))) (= 0 |cstrncat_#t~mem5|)), 11307#(or (and (<= 1 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base))) (not |cstrncat_#t~short6|)), 11308#(and (<= 1 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base))), 11309#(and (<= 1 |cstrncat_#t~post4.offset|) (<= (+ |cstrncat_#t~post4.offset| 1) (select |#length| |cstrncat_#t~post4.base|))), 11294#true, 11295#false] [2018-04-11 12:51:34,787 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-04-11 12:51:34,787 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-11 12:51:34,788 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-11 12:51:34,788 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2018-04-11 12:51:34,788 INFO L87 Difference]: Start difference. First operand 174 states and 198 transitions. Second operand 16 states. [2018-04-11 12:51:35,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:35,241 INFO L93 Difference]: Finished difference Result 186 states and 206 transitions. [2018-04-11 12:51:35,241 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-04-11 12:51:35,241 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 46 [2018-04-11 12:51:35,241 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:35,242 INFO L225 Difference]: With dead ends: 186 [2018-04-11 12:51:35,242 INFO L226 Difference]: Without dead ends: 161 [2018-04-11 12:51:35,242 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 102 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=146, Invalid=724, Unknown=0, NotChecked=0, Total=870 [2018-04-11 12:51:35,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-04-11 12:51:35,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 123. [2018-04-11 12:51:35,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 123 states. [2018-04-11 12:51:35,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 136 transitions. [2018-04-11 12:51:35,244 INFO L78 Accepts]: Start accepts. Automaton has 123 states and 136 transitions. Word has length 46 [2018-04-11 12:51:35,244 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:35,244 INFO L459 AbstractCegarLoop]: Abstraction has 123 states and 136 transitions. [2018-04-11 12:51:35,244 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-11 12:51:35,244 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 136 transitions. [2018-04-11 12:51:35,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-04-11 12:51:35,245 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:35,245 INFO L355 BasicCegarLoop]: trace histogram [10, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:35,245 INFO L408 AbstractCegarLoop]: === Iteration 34 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:35,245 INFO L82 PathProgramCache]: Analyzing trace with hash -254018723, now seen corresponding path program 7 times [2018-04-11 12:51:35,246 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:35,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:35,254 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:35,872 WARN L151 SmtUtils]: Spent 172ms on a formula simplification. DAG size of input: 120 DAG size of output 84 [2018-04-11 12:51:36,084 WARN L151 SmtUtils]: Spent 194ms on a formula simplification. DAG size of input: 101 DAG size of output 68 [2018-04-11 12:51:36,298 WARN L151 SmtUtils]: Spent 196ms on a formula simplification. DAG size of input: 101 DAG size of output 68 [2018-04-11 12:51:36,528 WARN L151 SmtUtils]: Spent 207ms on a formula simplification. DAG size of input: 104 DAG size of output 71 [2018-04-11 12:51:36,751 WARN L151 SmtUtils]: Spent 196ms on a formula simplification. DAG size of input: 119 DAG size of output 75 [2018-04-11 12:51:36,979 WARN L151 SmtUtils]: Spent 201ms on a formula simplification. DAG size of input: 122 DAG size of output 78 [2018-04-11 12:51:37,133 WARN L151 SmtUtils]: Spent 131ms on a formula simplification. DAG size of input: 87 DAG size of output 65 [2018-04-11 12:51:37,300 WARN L151 SmtUtils]: Spent 142ms on a formula simplification. DAG size of input: 90 DAG size of output 68 [2018-04-11 12:51:37,863 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:37,863 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:37,863 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27] total 27 [2018-04-11 12:51:37,863 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:37,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:37,864 INFO L182 omatonBuilderFactory]: Interpolants [11648#false, 11649#(<= 1 main_~n~0), 11650#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 11651#(and (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 11652#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 11653#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 11654#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (<= 7 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 5 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (and (<= 8 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 6 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 10 (select |#length| main_~nondetString1~0.base))) (<= 9 (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (<= 4 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1)))) (+ main_~nondetString1~0.offset (- 1))))))))), 11655#(and (= 0 |cstrncat_#in~s1.offset|) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (<= 9 (select |#length| |cstrncat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1)) (- 1)))) (<= 10 (select |#length| |cstrncat_#in~s1.base|)))) (and (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1)) (- 1)))) (<= 6 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 8 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- 3)) (- 1))))) (and (<= 7 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1)) (- 1)))) (<= 5 (select |#length| |cstrncat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 11656#(and (= cstrncat_~s~0.offset 0) (or (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~s~0.base))) (<= 9 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1))))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))))), 11657#(and (= cstrncat_~s~0.offset 0) (or (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~s~0.base))) (<= 9 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1))))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))))), 11658#(and (or (and (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))) (= cstrncat_~s~0.offset 1)), 11659#(and (or (and (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))) (= cstrncat_~s~0.offset 1)), 11660#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 11661#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 11662#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 11663#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 11664#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 11665#(or (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 11666#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))), 11667#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 11668#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 11669#(or (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 11670#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 11671#(or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 11672#(<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)), 11673#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 11674#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 11647#true] [2018-04-11 12:51:37,864 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:37,864 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-04-11 12:51:37,864 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-04-11 12:51:37,864 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=126, Invalid=630, Unknown=0, NotChecked=0, Total=756 [2018-04-11 12:51:37,865 INFO L87 Difference]: Start difference. First operand 123 states and 136 transitions. Second operand 28 states. [2018-04-11 12:51:39,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:39,898 INFO L93 Difference]: Finished difference Result 194 states and 211 transitions. [2018-04-11 12:51:39,898 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-04-11 12:51:39,898 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 47 [2018-04-11 12:51:39,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:39,898 INFO L225 Difference]: With dead ends: 194 [2018-04-11 12:51:39,899 INFO L226 Difference]: Without dead ends: 180 [2018-04-11 12:51:39,899 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 602 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=437, Invalid=2113, Unknown=0, NotChecked=0, Total=2550 [2018-04-11 12:51:39,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-04-11 12:51:39,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 129. [2018-04-11 12:51:39,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-04-11 12:51:39,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 143 transitions. [2018-04-11 12:51:39,900 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 143 transitions. Word has length 47 [2018-04-11 12:51:39,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:39,901 INFO L459 AbstractCegarLoop]: Abstraction has 129 states and 143 transitions. [2018-04-11 12:51:39,901 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-04-11 12:51:39,901 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 143 transitions. [2018-04-11 12:51:39,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-04-11 12:51:39,901 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:39,901 INFO L355 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:39,901 INFO L408 AbstractCegarLoop]: === Iteration 35 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:39,901 INFO L82 PathProgramCache]: Analyzing trace with hash 782026389, now seen corresponding path program 3 times [2018-04-11 12:51:39,902 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:39,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:39,911 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:40,094 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-11 12:51:40,094 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:40,094 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-04-11 12:51:40,094 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:40,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:40,094 INFO L182 omatonBuilderFactory]: Interpolants [12044#true, 12045#false, 12046#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (= 0 |main_#t~malloc13.offset|)), 12047#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 12048#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 12049#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 12050#(and (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString1~0.offset (- 1)))))) (= main_~nondetString1~0.offset 0)), 12051#(= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ |cstrncat_#in~n| (- (select |#length| |cstrncat_#in~s1.base|)))) (- 1)))), 12052#(= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ cstrncat_~n (- (select |#length| cstrncat_~s~0.base)))) (- 1)))), 12053#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~n cstrncat_~s~0.offset))), 12054#(or (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~n cstrncat_~s~0.offset)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 12055#(or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (+ (select |#length| cstrncat_~s~0.base) 1) (+ cstrncat_~n cstrncat_~s~0.offset))), 12056#(and (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~n)) (<= 0 cstrncat_~s~0.offset)), 12057#(and (<= 1 cstrncat_~s~0.offset) (or (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))), 12058#(and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) |cstrncat_#t~short6|)), 12059#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))] [2018-04-11 12:51:40,095 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-11 12:51:40,095 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-11 12:51:40,095 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-11 12:51:40,095 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-04-11 12:51:40,095 INFO L87 Difference]: Start difference. First operand 129 states and 143 transitions. Second operand 16 states. [2018-04-11 12:51:40,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:40,526 INFO L93 Difference]: Finished difference Result 141 states and 154 transitions. [2018-04-11 12:51:40,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-04-11 12:51:40,527 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 49 [2018-04-11 12:51:40,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:40,527 INFO L225 Difference]: With dead ends: 141 [2018-04-11 12:51:40,527 INFO L226 Difference]: Without dead ends: 127 [2018-04-11 12:51:40,528 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 99 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=157, Invalid=713, Unknown=0, NotChecked=0, Total=870 [2018-04-11 12:51:40,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-04-11 12:51:40,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 113. [2018-04-11 12:51:40,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-04-11 12:51:40,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 122 transitions. [2018-04-11 12:51:40,530 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 122 transitions. Word has length 49 [2018-04-11 12:51:40,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:40,530 INFO L459 AbstractCegarLoop]: Abstraction has 113 states and 122 transitions. [2018-04-11 12:51:40,530 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-11 12:51:40,530 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 122 transitions. [2018-04-11 12:51:40,530 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-04-11 12:51:40,530 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:40,531 INFO L355 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:40,531 INFO L408 AbstractCegarLoop]: === Iteration 36 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:40,531 INFO L82 PathProgramCache]: Analyzing trace with hash 782017353, now seen corresponding path program 3 times [2018-04-11 12:51:40,531 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:40,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:40,541 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:40,874 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 5 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:40,874 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:40,874 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24] total 24 [2018-04-11 12:51:40,874 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:40,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:40,875 INFO L182 omatonBuilderFactory]: Interpolants [12352#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~s1.base|)) (<= 1 |cstrncat_#in~n|)), 12353#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base)) (select |#length| cstrncat_~s~0.base)) (= cstrncat_~s~0.offset 0)), 12354#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 1)) (= 0 cstrncat_~s2.offset)), 12355#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 2)) (= 0 cstrncat_~s2.offset)), 12356#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 3))), 12357#(and (<= 1 cstrncat_~n) (= |cstrncat_#t~post4.offset| 0) (<= (+ cstrncat_~n |cstrncat_#t~post4.offset| (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 2))), 12358#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 2))), 12359#(and (<= 0 cstrncat_~n) (or (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 2)) (<= cstrncat_~n 0))), 12360#(or (and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 2)) (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n)) (not |cstrncat_#t~short6|)), 12361#(and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 1)) (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n)), 12362#(and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 1)) (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= 0 cstrncat_~s~0.offset)), 12363#(and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 1)) (<= cstrncat_~n 0)) (<= 0 cstrncat_~n)), 12364#(or (not |cstrncat_#t~short6|) (and (<= 1 cstrncat_~s~0.offset) (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)))), 12365#(and (<= 1 cstrncat_~s~0.offset) (<= (+ (select |#length| |cstrncat_#t~post4.base|) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post4.offset|))), 12366#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 12342#true, 12343#false, 12344#(<= 1 main_~n~0), 12345#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 12346#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 12347#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 12348#(and (= 0 main_~nondetString1~0.offset) (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 12349#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 12350#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))), 12351#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0))] [2018-04-11 12:51:40,875 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 5 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:40,875 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-04-11 12:51:40,875 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-04-11 12:51:40,876 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=508, Unknown=0, NotChecked=0, Total=600 [2018-04-11 12:51:40,876 INFO L87 Difference]: Start difference. First operand 113 states and 122 transitions. Second operand 25 states. [2018-04-11 12:51:41,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:41,390 INFO L93 Difference]: Finished difference Result 134 states and 143 transitions. [2018-04-11 12:51:41,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-04-11 12:51:41,391 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 49 [2018-04-11 12:51:41,391 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:41,391 INFO L225 Difference]: With dead ends: 134 [2018-04-11 12:51:41,391 INFO L226 Difference]: Without dead ends: 113 [2018-04-11 12:51:41,392 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 440 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=286, Invalid=1436, Unknown=0, NotChecked=0, Total=1722 [2018-04-11 12:51:41,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-04-11 12:51:41,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-04-11 12:51:41,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-04-11 12:51:41,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 121 transitions. [2018-04-11 12:51:41,393 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 121 transitions. Word has length 49 [2018-04-11 12:51:41,393 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:41,393 INFO L459 AbstractCegarLoop]: Abstraction has 113 states and 121 transitions. [2018-04-11 12:51:41,393 INFO L460 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-04-11 12:51:41,393 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 121 transitions. [2018-04-11 12:51:41,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-04-11 12:51:41,393 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:41,393 INFO L355 BasicCegarLoop]: trace histogram [11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:41,393 INFO L408 AbstractCegarLoop]: === Iteration 37 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:41,394 INFO L82 PathProgramCache]: Analyzing trace with hash 260555674, now seen corresponding path program 8 times [2018-04-11 12:51:41,394 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:41,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:41,403 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:42,425 WARN L151 SmtUtils]: Spent 286ms on a formula simplification. DAG size of input: 142 DAG size of output 93 [2018-04-11 12:51:42,692 WARN L151 SmtUtils]: Spent 236ms on a formula simplification. DAG size of input: 122 DAG size of output 76 [2018-04-11 12:51:42,982 WARN L151 SmtUtils]: Spent 269ms on a formula simplification. DAG size of input: 122 DAG size of output 76 [2018-04-11 12:51:43,292 WARN L151 SmtUtils]: Spent 281ms on a formula simplification. DAG size of input: 125 DAG size of output 79 [2018-04-11 12:51:43,595 WARN L151 SmtUtils]: Spent 275ms on a formula simplification. DAG size of input: 141 DAG size of output 84 [2018-04-11 12:51:43,906 WARN L151 SmtUtils]: Spent 277ms on a formula simplification. DAG size of input: 144 DAG size of output 87 [2018-04-11 12:51:44,104 WARN L151 SmtUtils]: Spent 171ms on a formula simplification. DAG size of input: 107 DAG size of output 74 [2018-04-11 12:51:44,349 WARN L151 SmtUtils]: Spent 213ms on a formula simplification. DAG size of input: 110 DAG size of output 77 [2018-04-11 12:51:44,475 WARN L151 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 86 DAG size of output 64 [2018-04-11 12:51:44,614 WARN L151 SmtUtils]: Spent 113ms on a formula simplification. DAG size of input: 89 DAG size of output 67 [2018-04-11 12:51:45,205 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:45,205 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:45,206 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-04-11 12:51:45,206 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:45,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:45,207 INFO L182 omatonBuilderFactory]: Interpolants [12672#(or (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))))), 12673#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 12674#(and (or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (<= 0 cstrncat_~s~0.offset)), 12675#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base))), 12676#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)), 12648#true, 12649#false, 12650#(<= 1 main_~n~0), 12651#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 12652#(and (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 12653#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 12654#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 12655#(and (= 0 main_~nondetString1~0.offset) (or (and (<= 7 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 5 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 8 (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (and (<= 6 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 10 (select |#length| main_~nondetString1~0.base)) (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 11 (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (<= 4 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1)))) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (select |#length| main_~nondetString1~0.base)))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 12656#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (<= 10 (select |#length| |cstrncat_#in~s1.base|)) (or (<= 11 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1)) (- 1)))) (<= 8 (select |#length| |cstrncat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (<= 9 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- 3)) (- 1))))) (and (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1)) (- 1)))) (<= 6 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 7 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1)) (- 1)))) (<= 5 (select |#length| |cstrncat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 12657#(and (or (and (or (<= 11 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (<= 10 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base)))) (= cstrncat_~s~0.offset 0)), 12658#(and (or (and (or (<= 11 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (<= 10 (select |#length| cstrncat_~s~0.base))) (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (= cstrncat_~s~0.offset 0)), 12659#(and (or (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))) (= cstrncat_~s~0.offset 1)), 12660#(and (= cstrncat_~s~0.offset 1) (or (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))))), 12661#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 12662#(or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 12663#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 12664#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 12665#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 12666#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 12667#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 12668#(or (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 12669#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1))))))), 12670#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1))))))), 12671#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)))))] [2018-04-11 12:51:45,207 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:45,207 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-04-11 12:51:45,208 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-04-11 12:51:45,208 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=143, Invalid=669, Unknown=0, NotChecked=0, Total=812 [2018-04-11 12:51:45,208 INFO L87 Difference]: Start difference. First operand 113 states and 121 transitions. Second operand 29 states. [2018-04-11 12:51:45,949 WARN L151 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 145 DAG size of output 138 [2018-04-11 12:51:46,129 WARN L151 SmtUtils]: Spent 156ms on a formula simplification. DAG size of input: 150 DAG size of output 142 [2018-04-11 12:51:46,286 WARN L151 SmtUtils]: Spent 115ms on a formula simplification. DAG size of input: 137 DAG size of output 130 [2018-04-11 12:51:46,436 WARN L151 SmtUtils]: Spent 131ms on a formula simplification. DAG size of input: 142 DAG size of output 137 [2018-04-11 12:51:46,571 WARN L151 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 129 DAG size of output 122 [2018-04-11 12:51:46,702 WARN L151 SmtUtils]: Spent 107ms on a formula simplification. DAG size of input: 134 DAG size of output 126 [2018-04-11 12:51:47,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:47,809 INFO L93 Difference]: Finished difference Result 165 states and 175 transitions. [2018-04-11 12:51:47,809 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-04-11 12:51:47,809 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 50 [2018-04-11 12:51:47,809 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:47,810 INFO L225 Difference]: With dead ends: 165 [2018-04-11 12:51:47,810 INFO L226 Difference]: Without dead ends: 165 [2018-04-11 12:51:47,810 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 696 ImplicationChecksByTransitivity, 5.5s TimeCoverageRelationStatistics Valid=497, Invalid=2365, Unknown=0, NotChecked=0, Total=2862 [2018-04-11 12:51:47,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-04-11 12:51:47,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 119. [2018-04-11 12:51:47,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-04-11 12:51:47,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 128 transitions. [2018-04-11 12:51:47,812 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 128 transitions. Word has length 50 [2018-04-11 12:51:47,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:47,812 INFO L459 AbstractCegarLoop]: Abstraction has 119 states and 128 transitions. [2018-04-11 12:51:47,812 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-04-11 12:51:47,812 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 128 transitions. [2018-04-11 12:51:47,813 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-04-11 12:51:47,813 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:47,813 INFO L355 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:47,813 INFO L408 AbstractCegarLoop]: === Iteration 38 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:47,813 INFO L82 PathProgramCache]: Analyzing trace with hash 2012113674, now seen corresponding path program 4 times [2018-04-11 12:51:47,820 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:47,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:47,826 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:48,356 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 5 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:48,356 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:48,356 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-04-11 12:51:48,357 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:48,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:48,357 INFO L182 omatonBuilderFactory]: Interpolants [13011#true, 13012#false, 13013#(<= 1 main_~n~0), 13014#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 13015#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 13016#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 13017#(and (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 13018#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 13019#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (- main_~length2~0))) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 1) (select |#length| main_~nondetString1~0.base))) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 13020#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (- (select |#length| main_~nondetString2~0.base)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 13021#(and (or (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n| 1) (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- (select |#length| |cstrncat_#in~s2.base|))) (- 1))))) (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~s1.base|)) (<= 1 |cstrncat_#in~n|)), 13022#(and (<= 1 cstrncat_~n) (or (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) 1) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- (select |#length| cstrncat_~s2.base))) (- 1))))) (= 0 cstrncat_~s2.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base)) (select |#length| cstrncat_~s~0.base)) (= cstrncat_~s~0.offset 0)), 13023#(and (<= 1 cstrncat_~n) (or (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s2.base)) (+ (- cstrncat_~s~0.offset) 1))) (- 1))))) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 1)) (= 0 cstrncat_~s2.offset)), 13024#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 2)))), 13025#(or (and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 2))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 13026#(and (<= 1 cstrncat_~n) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 2)) (= 0 cstrncat_~s2.offset)), 13027#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s2.base) 2) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (= 0 cstrncat_~s2.offset)), 13028#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s2.base) 2) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (= 0 cstrncat_~s2.offset) (<= 0 cstrncat_~s~0.offset)), 13029#(and (<= 1 cstrncat_~n) (= |cstrncat_#t~post4.offset| 0) (or (<= (+ (select |#length| cstrncat_~s2.base) |cstrncat_#t~post4.offset|) (+ cstrncat_~s2.offset 1)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~s~0.offset)), 13030#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~s~0.offset)), 13031#(and (<= 1 cstrncat_~s~0.offset) (or (<= cstrncat_~n 0) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~n)), 13032#(or (not |cstrncat_#t~short6|) (and (<= 1 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n))), 13033#(and (<= 1 cstrncat_~s~0.offset) (not (= cstrncat_~n 0)) (or (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~n)), 13034#(and (or (<= cstrncat_~n 0) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~n) (<= 2 cstrncat_~s~0.offset)), 13035#(and (or (not |cstrncat_#t~short6|) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)) (<= 2 cstrncat_~s~0.offset)), 13036#(and (or (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| |cstrncat_#t~post4.base|) |cstrncat_#t~post4.offset|)) (<= 2 cstrncat_~s~0.offset)), 13037#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset))] [2018-04-11 12:51:48,357 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 5 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:48,357 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-04-11 12:51:48,357 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-04-11 12:51:48,357 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=618, Unknown=0, NotChecked=0, Total=702 [2018-04-11 12:51:48,358 INFO L87 Difference]: Start difference. First operand 119 states and 128 transitions. Second operand 27 states. [2018-04-11 12:51:48,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:48,975 INFO L93 Difference]: Finished difference Result 145 states and 154 transitions. [2018-04-11 12:51:48,976 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-04-11 12:51:48,976 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 52 [2018-04-11 12:51:48,976 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:48,976 INFO L225 Difference]: With dead ends: 145 [2018-04-11 12:51:48,976 INFO L226 Difference]: Without dead ends: 124 [2018-04-11 12:51:48,977 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 476 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=233, Invalid=1489, Unknown=0, NotChecked=0, Total=1722 [2018-04-11 12:51:48,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-04-11 12:51:48,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 119. [2018-04-11 12:51:48,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-04-11 12:51:48,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 127 transitions. [2018-04-11 12:51:48,978 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 127 transitions. Word has length 52 [2018-04-11 12:51:48,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:48,978 INFO L459 AbstractCegarLoop]: Abstraction has 119 states and 127 transitions. [2018-04-11 12:51:48,978 INFO L460 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-04-11 12:51:48,978 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 127 transitions. [2018-04-11 12:51:48,978 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-04-11 12:51:48,978 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:48,978 INFO L355 BasicCegarLoop]: trace histogram [12, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:48,978 INFO L408 AbstractCegarLoop]: === Iteration 39 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:48,979 INFO L82 PathProgramCache]: Analyzing trace with hash 1208137277, now seen corresponding path program 9 times [2018-04-11 12:51:48,979 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:48,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:48,986 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:50,685 WARN L151 SmtUtils]: Spent 432ms on a formula simplification. DAG size of input: 166 DAG size of output 102 [2018-04-11 12:51:51,095 WARN L151 SmtUtils]: Spent 384ms on a formula simplification. DAG size of input: 145 DAG size of output 84 [2018-04-11 12:51:51,451 WARN L151 SmtUtils]: Spent 330ms on a formula simplification. DAG size of input: 145 DAG size of output 84 [2018-04-11 12:51:51,862 WARN L151 SmtUtils]: Spent 382ms on a formula simplification. DAG size of input: 148 DAG size of output 87 [2018-04-11 12:51:52,277 WARN L151 SmtUtils]: Spent 379ms on a formula simplification. DAG size of input: 165 DAG size of output 93 [2018-04-11 12:51:52,686 WARN L151 SmtUtils]: Spent 372ms on a formula simplification. DAG size of input: 168 DAG size of output 96 [2018-04-11 12:51:52,987 WARN L151 SmtUtils]: Spent 269ms on a formula simplification. DAG size of input: 129 DAG size of output 83 [2018-04-11 12:51:53,283 WARN L151 SmtUtils]: Spent 260ms on a formula simplification. DAG size of input: 132 DAG size of output 86 [2018-04-11 12:51:53,509 WARN L151 SmtUtils]: Spent 195ms on a formula simplification. DAG size of input: 106 DAG size of output 73 [2018-04-11 12:51:53,749 WARN L151 SmtUtils]: Spent 207ms on a formula simplification. DAG size of input: 109 DAG size of output 76 [2018-04-11 12:51:53,882 WARN L151 SmtUtils]: Spent 107ms on a formula simplification. DAG size of input: 86 DAG size of output 64 [2018-04-11 12:51:54,034 WARN L151 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 89 DAG size of output 67 [2018-04-11 12:51:54,605 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:54,605 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:54,605 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-04-11 12:51:54,605 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:54,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:54,606 INFO L182 omatonBuilderFactory]: Interpolants [13332#true, 13333#false, 13334#(<= 1 main_~n~0), 13335#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 13336#(and (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 13337#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 13338#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 13339#(and (or (and (<= 7 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 10 (select |#length| main_~nondetString1~0.base))) (and (<= 5 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 11 (select |#length| main_~nondetString1~0.base)) (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 12 (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 8 (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (and (<= 6 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (<= 4 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1)))) (+ main_~nondetString1~0.offset (- 1)))))))) (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 13340#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1)) (- 1)))) (<= 8 (select |#length| |cstrncat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (<= 9 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1)) (- 1)))) (<= 6 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 7 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1)) (- 1))))) (and (<= 10 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- 3)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1)) (- 1)))) (<= 5 (select |#length| |cstrncat_#in~s1.base|))) (and (or (<= 12 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (<= 11 (select |#length| |cstrncat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 13341#(and (= cstrncat_~s~0.offset 0) (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 10 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (<= 11 (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 12 (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))))), 13342#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 10 (select |#length| cstrncat_~s~0.base))) (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (<= 11 (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 12 (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (= cstrncat_~s~0.offset 0)), 13343#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))) (= cstrncat_~s~0.offset 1)), 13344#(and (or (and (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))) (= cstrncat_~s~0.offset 1)), 13345#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 13346#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 13347#(or (and (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 13348#(or (and (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 13349#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 13350#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 13351#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 13352#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 13353#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))))), 13354#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 13355#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1))))))), 13356#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1))))))), 13357#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))))), 13358#(or (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))))), 13359#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 13360#(or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 13361#(<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)), 13362#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 13363#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))] [2018-04-11 12:51:54,606 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:54,606 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-11 12:51:54,606 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-11 12:51:54,607 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=181, Invalid=811, Unknown=0, NotChecked=0, Total=992 [2018-04-11 12:51:54,607 INFO L87 Difference]: Start difference. First operand 119 states and 127 transitions. Second operand 32 states. [2018-04-11 12:51:54,902 WARN L151 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 126 DAG size of output 125 [2018-04-11 12:51:55,386 WARN L151 SmtUtils]: Spent 133ms on a formula simplification. DAG size of input: 169 DAG size of output 168 [2018-04-11 12:51:55,549 WARN L151 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 161 DAG size of output 154 [2018-04-11 12:51:55,705 WARN L151 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 164 DAG size of output 161 [2018-04-11 12:51:55,883 WARN L151 SmtUtils]: Spent 133ms on a formula simplification. DAG size of input: 153 DAG size of output 146 [2018-04-11 12:51:56,009 WARN L151 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 156 DAG size of output 153 [2018-04-11 12:51:56,142 WARN L151 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 145 DAG size of output 138 [2018-04-11 12:51:56,280 WARN L151 SmtUtils]: Spent 115ms on a formula simplification. DAG size of input: 148 DAG size of output 145 [2018-04-11 12:51:56,543 WARN L151 SmtUtils]: Spent 107ms on a formula simplification. DAG size of input: 140 DAG size of output 137 [2018-04-11 12:51:56,940 WARN L151 SmtUtils]: Spent 100ms on a formula simplification. DAG size of input: 120 DAG size of output 117 [2018-04-11 12:51:57,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:57,765 INFO L93 Difference]: Finished difference Result 171 states and 181 transitions. [2018-04-11 12:51:57,765 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-04-11 12:51:57,766 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 53 [2018-04-11 12:51:57,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:57,766 INFO L225 Difference]: With dead ends: 171 [2018-04-11 12:51:57,766 INFO L226 Difference]: Without dead ends: 171 [2018-04-11 12:51:57,767 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 859 ImplicationChecksByTransitivity, 7.2s TimeCoverageRelationStatistics Valid=620, Invalid=2802, Unknown=0, NotChecked=0, Total=3422 [2018-04-11 12:51:57,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-04-11 12:51:57,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 125. [2018-04-11 12:51:57,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-04-11 12:51:57,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 134 transitions. [2018-04-11 12:51:57,769 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 134 transitions. Word has length 53 [2018-04-11 12:51:57,769 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:57,769 INFO L459 AbstractCegarLoop]: Abstraction has 125 states and 134 transitions. [2018-04-11 12:51:57,769 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-11 12:51:57,769 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 134 transitions. [2018-04-11 12:51:57,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-04-11 12:51:57,770 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:57,770 INFO L355 BasicCegarLoop]: trace histogram [6, 6, 5, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:57,770 INFO L408 AbstractCegarLoop]: === Iteration 40 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:57,770 INFO L82 PathProgramCache]: Analyzing trace with hash -1144324183, now seen corresponding path program 5 times [2018-04-11 12:51:57,770 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:57,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:57,781 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:51:58,539 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 5 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:58,539 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:51:58,540 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-04-11 12:51:58,540 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:51:58,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:58,540 INFO L182 omatonBuilderFactory]: Interpolants [13714#true, 13715#false, 13716#(<= 1 main_~n~0), 13717#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 13718#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 13719#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 13720#(and (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 13721#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 13722#(and (= 0 main_~nondetString2~0.offset) (or (and (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (- main_~length2~0))) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 2) (select |#length| main_~nondetString1~0.base))) (<= (+ main_~n~0 main_~length2~0 1) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base)))) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 13723#(and (= 0 main_~nondetString2~0.offset) (or (and (or (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 2) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (- (select |#length| main_~nondetString2~0.base)))) (+ main_~nondetString1~0.offset (- 1))))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base))) (and (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString1~0.offset (- 1)))))))) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 13724#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (or (and (or (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n| 2) (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- (select |#length| |cstrncat_#in~s2.base|))) (- 1))))) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n| 1) (select |#length| |cstrncat_#in~s1.base|))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ |cstrncat_#in~n| (- (select |#length| |cstrncat_#in~s1.base|)))) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~s1.base|)))) (<= 1 |cstrncat_#in~n|)), 13725#(and (<= 1 cstrncat_~n) (or (and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base)) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ cstrncat_~n (- (select |#length| cstrncat_~s~0.base)))) (- 1))))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) 1) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- (select |#length| cstrncat_~s2.base))) (- 1)))) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) 2) (select |#length| cstrncat_~s~0.base))))) (= 0 cstrncat_~s2.offset) (= cstrncat_~s~0.offset 0)), 13726#(and (<= 1 cstrncat_~n) (or (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (+ (- (select |#length| cstrncat_~s2.base)) 1))) (- 1)))) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ cstrncat_~n (- (select |#length| cstrncat_~s~0.base)))) (- 1)))))) (= 0 cstrncat_~s2.offset)), 13727#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ cstrncat_~n (- (select |#length| cstrncat_~s~0.base)))) (- 1))))))) (= 0 cstrncat_~s2.offset)), 13728#(and (= 0 cstrncat_~s2.offset) (or (<= (select |#length| cstrncat_~s2.base) 2) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ cstrncat_~n (- (select |#length| cstrncat_~s~0.base)))) (- 1)))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))))), 13729#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 cstrncat_~s2.offset) (or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| cstrncat_~s2.base) 2)))), 13730#(or (and (= 0 cstrncat_~s2.offset) (or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| cstrncat_~s2.base) 2))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 13731#(and (= 0 cstrncat_~s2.offset) (or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| cstrncat_~s2.base) 2))), 13732#(and (= 0 cstrncat_~s2.offset) (or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| cstrncat_~s2.base) 2))), 13733#(and (= |cstrncat_#t~post4.offset| 0) (or (<= (+ (select |#length| cstrncat_~s2.base) |cstrncat_#t~post4.offset|) (+ cstrncat_~s2.offset 1)) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))))), 13734#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1))), 13735#(or (and (or (<= cstrncat_~n 0) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~n)) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1))), 13736#(or (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (not |cstrncat_#t~short6|) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1))), 13737#(or (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)), 13738#(and (or (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)) (<= 0 cstrncat_~s~0.offset)), 13739#(and (<= 1 cstrncat_~s~0.offset) (or (and (or (<= cstrncat_~n 0) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~n)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset))), 13740#(and (<= 1 cstrncat_~s~0.offset) (or (not |cstrncat_#t~short6|) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset))), 13741#(and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| |cstrncat_#t~post4.base|) |cstrncat_#t~post4.offset|))), 13742#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))] [2018-04-11 12:51:58,540 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 5 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:51:58,540 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-04-11 12:51:58,540 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-04-11 12:51:58,541 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=702, Unknown=0, NotChecked=0, Total=812 [2018-04-11 12:51:58,541 INFO L87 Difference]: Start difference. First operand 125 states and 134 transitions. Second operand 29 states. [2018-04-11 12:51:59,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:51:59,493 INFO L93 Difference]: Finished difference Result 151 states and 160 transitions. [2018-04-11 12:51:59,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-04-11 12:51:59,493 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 55 [2018-04-11 12:51:59,494 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:51:59,494 INFO L225 Difference]: With dead ends: 151 [2018-04-11 12:51:59,494 INFO L226 Difference]: Without dead ends: 130 [2018-04-11 12:51:59,495 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 621 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=336, Invalid=1826, Unknown=0, NotChecked=0, Total=2162 [2018-04-11 12:51:59,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2018-04-11 12:51:59,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 125. [2018-04-11 12:51:59,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-04-11 12:51:59,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 133 transitions. [2018-04-11 12:51:59,496 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 133 transitions. Word has length 55 [2018-04-11 12:51:59,496 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:51:59,496 INFO L459 AbstractCegarLoop]: Abstraction has 125 states and 133 transitions. [2018-04-11 12:51:59,496 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-04-11 12:51:59,496 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 133 transitions. [2018-04-11 12:51:59,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-04-11 12:51:59,497 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:51:59,497 INFO L355 BasicCegarLoop]: trace histogram [13, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:51:59,497 INFO L408 AbstractCegarLoop]: === Iteration 41 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:51:59,497 INFO L82 PathProgramCache]: Analyzing trace with hash -208364358, now seen corresponding path program 10 times [2018-04-11 12:51:59,497 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:51:59,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:51:59,506 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:52:03,022 WARN L151 SmtUtils]: Spent 552ms on a formula simplification. DAG size of input: 192 DAG size of output 111 [2018-04-11 12:52:03,574 WARN L151 SmtUtils]: Spent 522ms on a formula simplification. DAG size of input: 170 DAG size of output 92 [2018-04-11 12:52:04,063 WARN L151 SmtUtils]: Spent 457ms on a formula simplification. DAG size of input: 170 DAG size of output 92 [2018-04-11 12:52:04,639 WARN L151 SmtUtils]: Spent 540ms on a formula simplification. DAG size of input: 173 DAG size of output 95 [2018-04-11 12:52:05,143 WARN L151 SmtUtils]: Spent 467ms on a formula simplification. DAG size of input: 191 DAG size of output 102 [2018-04-11 12:52:05,638 WARN L151 SmtUtils]: Spent 453ms on a formula simplification. DAG size of input: 194 DAG size of output 105 [2018-04-11 12:52:06,032 WARN L151 SmtUtils]: Spent 358ms on a formula simplification. DAG size of input: 153 DAG size of output 92 [2018-04-11 12:52:06,444 WARN L151 SmtUtils]: Spent 374ms on a formula simplification. DAG size of input: 156 DAG size of output 95 [2018-04-11 12:52:06,751 WARN L151 SmtUtils]: Spent 273ms on a formula simplification. DAG size of input: 128 DAG size of output 82 [2018-04-11 12:52:07,079 WARN L151 SmtUtils]: Spent 280ms on a formula simplification. DAG size of input: 131 DAG size of output 85 [2018-04-11 12:52:07,304 WARN L151 SmtUtils]: Spent 187ms on a formula simplification. DAG size of input: 106 DAG size of output 73 [2018-04-11 12:52:07,559 WARN L151 SmtUtils]: Spent 205ms on a formula simplification. DAG size of input: 109 DAG size of output 76 [2018-04-11 12:52:07,700 WARN L151 SmtUtils]: Spent 112ms on a formula simplification. DAG size of input: 86 DAG size of output 64 [2018-04-11 12:52:07,851 WARN L151 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 89 DAG size of output 67 [2018-04-11 12:52:08,423 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:52:08,423 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:52:08,423 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2018-04-11 12:52:08,423 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:52:08,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:52:08,424 INFO L182 omatonBuilderFactory]: Interpolants [14080#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))), 14081#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (<= 0 cstrncat_~s~0.offset)), 14082#(and (<= 1 cstrncat_~s~0.offset) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))))), 14083#(and (<= 1 cstrncat_~s~0.offset) (or (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))))), 14084#(or (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))), 14085#(or (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 14086#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 3 cstrncat_~s~0.offset)), 14087#(and (<= 4 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 14055#true, 14056#false, 14057#(<= 1 main_~n~0), 14058#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 14059#(and (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 14060#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 14061#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 14062#(and (= 0 main_~nondetString1~0.offset) (or (and (<= 7 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (select |#length| main_~nondetString1~0.base))) (and (<= 5 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 8 (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 11 (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (and (<= 6 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 10 (select |#length| main_~nondetString1~0.base))) (and (or (<= 13 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (<= 12 (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (<= 4 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1)))) (+ main_~nondetString1~0.offset (- 1)))))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 14063#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1)) (- 1)))) (<= 8 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 11 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- 3)) (- 1))))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (<= 9 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1)) (- 1)))) (<= 6 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 12 (select |#length| |cstrncat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 13 (select |#length| |cstrncat_#in~s1.base|)))) (and (<= 7 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1)) (- 1)))) (<= 5 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 10 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 14064#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 11 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 13 (select |#length| cstrncat_~s~0.base))) (<= 12 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base)))) (= cstrncat_~s~0.offset 0)), 14065#(and (or (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 11 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 13 (select |#length| cstrncat_~s~0.base))) (<= 12 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (= cstrncat_~s~0.offset 0)), 14066#(and (= cstrncat_~s~0.offset 1) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))))), 14067#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))) (= cstrncat_~s~0.offset 1)), 14068#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (or (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1))))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14069#(or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (or (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1))))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14070#(or (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14071#(or (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14072#(or (and (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14073#(or (and (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14074#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14075#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14076#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 14077#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 14078#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))))), 14079#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))))] [2018-04-11 12:52:08,424 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:52:08,424 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-04-11 12:52:08,424 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-04-11 12:52:08,424 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=156, Invalid=900, Unknown=0, NotChecked=0, Total=1056 [2018-04-11 12:52:08,425 INFO L87 Difference]: Start difference. First operand 125 states and 133 transitions. Second operand 33 states. [2018-04-11 12:52:08,709 WARN L151 SmtUtils]: Spent 111ms on a formula simplification. DAG size of input: 135 DAG size of output 134 [2018-04-11 12:52:09,390 WARN L151 SmtUtils]: Spent 163ms on a formula simplification. DAG size of input: 178 DAG size of output 166 [2018-04-11 12:52:09,603 WARN L151 SmtUtils]: Spent 183ms on a formula simplification. DAG size of input: 186 DAG size of output 169 [2018-04-11 12:52:09,779 WARN L151 SmtUtils]: Spent 130ms on a formula simplification. DAG size of input: 173 DAG size of output 158 [2018-04-11 12:52:09,970 WARN L151 SmtUtils]: Spent 163ms on a formula simplification. DAG size of input: 181 DAG size of output 167 [2018-04-11 12:52:10,166 WARN L151 SmtUtils]: Spent 149ms on a formula simplification. DAG size of input: 168 DAG size of output 149 [2018-04-11 12:52:10,358 WARN L151 SmtUtils]: Spent 158ms on a formula simplification. DAG size of input: 176 DAG size of output 156 [2018-04-11 12:52:10,541 WARN L151 SmtUtils]: Spent 137ms on a formula simplification. DAG size of input: 160 DAG size of output 141 [2018-04-11 12:52:10,713 WARN L151 SmtUtils]: Spent 146ms on a formula simplification. DAG size of input: 168 DAG size of output 151 [2018-04-11 12:52:10,875 WARN L151 SmtUtils]: Spent 125ms on a formula simplification. DAG size of input: 152 DAG size of output 138 [2018-04-11 12:52:11,035 WARN L151 SmtUtils]: Spent 134ms on a formula simplification. DAG size of input: 160 DAG size of output 140 [2018-04-11 12:52:11,172 WARN L151 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 144 DAG size of output 130 [2018-04-11 12:52:11,329 WARN L151 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 152 DAG size of output 137 [2018-04-11 12:52:11,487 WARN L151 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 136 DAG size of output 123 [2018-04-11 12:52:11,636 WARN L151 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 140 DAG size of output 126 [2018-04-11 12:52:12,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:52:12,398 INFO L93 Difference]: Finished difference Result 177 states and 187 transitions. [2018-04-11 12:52:12,398 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-04-11 12:52:12,399 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 56 [2018-04-11 12:52:12,399 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:52:12,399 INFO L225 Difference]: With dead ends: 177 [2018-04-11 12:52:12,399 INFO L226 Difference]: Without dead ends: 177 [2018-04-11 12:52:12,400 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 969 ImplicationChecksByTransitivity, 9.8s TimeCoverageRelationStatistics Valid=580, Invalid=3202, Unknown=0, NotChecked=0, Total=3782 [2018-04-11 12:52:12,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-04-11 12:52:12,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 131. [2018-04-11 12:52:12,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-04-11 12:52:12,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 140 transitions. [2018-04-11 12:52:12,401 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 140 transitions. Word has length 56 [2018-04-11 12:52:12,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:52:12,401 INFO L459 AbstractCegarLoop]: Abstraction has 131 states and 140 transitions. [2018-04-11 12:52:12,401 INFO L460 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-04-11 12:52:12,401 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 140 transitions. [2018-04-11 12:52:12,402 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-04-11 12:52:12,402 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:52:12,402 INFO L355 BasicCegarLoop]: trace histogram [7, 7, 6, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:52:12,402 INFO L408 AbstractCegarLoop]: === Iteration 42 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:52:12,402 INFO L82 PathProgramCache]: Analyzing trace with hash -570543446, now seen corresponding path program 6 times [2018-04-11 12:52:12,402 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:52:12,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:52:12,409 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:52:13,627 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 80 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:52:13,627 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:52:13,627 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-04-11 12:52:13,627 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:52:13,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:52:13,628 INFO L182 omatonBuilderFactory]: Interpolants [14464#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (= 0 |cstrncat_#in~s2.offset|) (<= (select |#length| |cstrncat_#in~s2.base|) 2)) (and (<= 7 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 3)) (- 1))))) (and (<= 8 (select |#length| |cstrncat_#in~s1.base|)) (or (<= 9 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 4)) (- 1)))))) (and (<= 6 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- 3)) (- 1))))) (and (<= |cstrncat_#in~n| 2) (<= 1 |cstrncat_#in~n|)))), 14465#(and (= cstrncat_~s~0.offset 0) (or (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 6 (select |#length| cstrncat_~s~0.base))) (and (<= 8 (select |#length| cstrncat_~s~0.base)) (or (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 4)) (- 1)))))) (and (<= 7 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))), 14466#(or (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (<= 1 cstrncat_~s~0.offset) (or (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 4)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))))), 14467#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 4)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (<= 2 cstrncat_~s~0.offset)) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2))), 14468#(or (and (or (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 4)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (<= 2 cstrncat_~s~0.offset)) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 14469#(or (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (<= 3 cstrncat_~s~0.offset))), 14470#(or (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (or (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (<= 3 cstrncat_~s~0.offset))), 14471#(or (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (<= 4 cstrncat_~s~0.offset) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))))), 14472#(or (and (<= 4 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2))), 14473#(or (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (<= 5 cstrncat_~s~0.offset))), 14474#(or (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (<= 6 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))))), 14475#(or (and (= |cstrncat_#t~post4.offset| 0) (<= (+ |cstrncat_#t~post4.offset| (select |#length| cstrncat_~s2.base)) (+ cstrncat_~s2.offset 1))) (and (<= 6 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))))), 14476#(or (and (<= 6 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1))), 14477#(or (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1)) (and (or (and (<= 0 cstrncat_~n) (<= cstrncat_~n 1)) (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base))) (<= 7 cstrncat_~s~0.offset))), 14478#(or (and (or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= cstrncat_~n 1)) (not |cstrncat_#t~short6|)) (<= 7 cstrncat_~s~0.offset)) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1))), 14479#(or (and (<= 7 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= cstrncat_~n 1)))) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)), 14480#(or (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset) (and (<= 8 cstrncat_~s~0.offset) (or (and (<= cstrncat_~n 0) (<= 0 cstrncat_~n)) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))))), 14481#(or (and (or (not |cstrncat_#t~short6|) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))) (<= 8 cstrncat_~s~0.offset)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)), 14482#(or (<= (select |#length| |cstrncat_#t~post4.base|) |cstrncat_#t~post4.offset|) (and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 8 cstrncat_~s~0.offset))), 14483#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 8 cstrncat_~s~0.offset)), 14454#true, 14455#false, 14456#(<= 1 main_~n~0), 14457#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 14458#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 14459#(and (or (<= (+ main_~n~0 3) (+ main_~nondetString1~0.offset main_~length1~0)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 14460#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (and (= 0 |main_#t~malloc14.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (<= (+ main_~n~0 3) (+ main_~nondetString1~0.offset main_~length1~0))) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 14461#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (and (= 0 main_~nondetString2~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (<= (+ main_~n~0 3) (+ main_~nondetString1~0.offset main_~length1~0))) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 14462#(and (or (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (select |#length| main_~nondetString1~0.base))) (and (<= 8 (select |#length| main_~nondetString1~0.base)) (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 4)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (select |#length| main_~nondetString1~0.base)))) (and (<= 1 main_~n~0) (<= main_~n~0 (+ main_~nondetString1~0.offset 2))) (and (<= 6 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 main_~nondetString2~0.offset) (<= (+ main_~nondetString1~0.offset main_~length2~0) 2) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 14463#(and (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (= 0 main_~nondetString2~0.offset) (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset) 2)) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (select |#length| main_~nondetString1~0.base))) (and (<= 8 (select |#length| main_~nondetString1~0.base)) (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 4)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (select |#length| main_~nondetString1~0.base)))) (and (<= 1 main_~n~0) (<= main_~n~0 (+ main_~nondetString1~0.offset 2))) (and (<= 6 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1)))))))) (= main_~nondetString1~0.offset 0))] [2018-04-11 12:52:13,628 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 80 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:52:13,628 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-04-11 12:52:13,628 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-04-11 12:52:13,628 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=797, Unknown=0, NotChecked=0, Total=870 [2018-04-11 12:52:13,628 INFO L87 Difference]: Start difference. First operand 131 states and 140 transitions. Second operand 30 states. [2018-04-11 12:52:14,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:52:14,931 INFO L93 Difference]: Finished difference Result 157 states and 166 transitions. [2018-04-11 12:52:14,931 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-04-11 12:52:14,932 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 58 [2018-04-11 12:52:14,932 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:52:14,932 INFO L225 Difference]: With dead ends: 157 [2018-04-11 12:52:14,932 INFO L226 Difference]: Without dead ends: 157 [2018-04-11 12:52:14,933 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 484 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=178, Invalid=2078, Unknown=0, NotChecked=0, Total=2256 [2018-04-11 12:52:14,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-04-11 12:52:14,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 138. [2018-04-11 12:52:14,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-04-11 12:52:14,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 147 transitions. [2018-04-11 12:52:14,934 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 147 transitions. Word has length 58 [2018-04-11 12:52:14,934 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:52:14,934 INFO L459 AbstractCegarLoop]: Abstraction has 138 states and 147 transitions. [2018-04-11 12:52:14,934 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-04-11 12:52:14,934 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 147 transitions. [2018-04-11 12:52:14,935 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-04-11 12:52:14,935 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:52:14,935 INFO L355 BasicCegarLoop]: trace histogram [14, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:52:14,935 INFO L408 AbstractCegarLoop]: === Iteration 43 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:52:14,935 INFO L82 PathProgramCache]: Analyzing trace with hash -1154889443, now seen corresponding path program 11 times [2018-04-11 12:52:14,935 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:52:14,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:52:14,948 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:52:21,577 WARN L151 SmtUtils]: Spent 706ms on a formula simplification. DAG size of input: 220 DAG size of output 120 [2018-04-11 12:52:22,244 WARN L151 SmtUtils]: Spent 634ms on a formula simplification. DAG size of input: 197 DAG size of output 100 [2018-04-11 12:52:22,881 WARN L151 SmtUtils]: Spent 598ms on a formula simplification. DAG size of input: 197 DAG size of output 100 [2018-04-11 12:52:23,553 WARN L151 SmtUtils]: Spent 629ms on a formula simplification. DAG size of input: 200 DAG size of output 103 [2018-04-11 12:52:24,244 WARN L151 SmtUtils]: Spent 645ms on a formula simplification. DAG size of input: 219 DAG size of output 111 [2018-04-11 12:52:24,969 WARN L151 SmtUtils]: Spent 675ms on a formula simplification. DAG size of input: 222 DAG size of output 114 [2018-04-11 12:52:25,477 WARN L151 SmtUtils]: Spent 464ms on a formula simplification. DAG size of input: 179 DAG size of output 101 [2018-04-11 12:52:25,965 WARN L151 SmtUtils]: Spent 441ms on a formula simplification. DAG size of input: 182 DAG size of output 104 [2018-04-11 12:52:26,314 WARN L151 SmtUtils]: Spent 313ms on a formula simplification. DAG size of input: 152 DAG size of output 91 [2018-04-11 12:52:26,717 WARN L151 SmtUtils]: Spent 362ms on a formula simplification. DAG size of input: 155 DAG size of output 94 [2018-04-11 12:52:26,995 WARN L151 SmtUtils]: Spent 241ms on a formula simplification. DAG size of input: 128 DAG size of output 82 [2018-04-11 12:52:27,267 WARN L151 SmtUtils]: Spent 234ms on a formula simplification. DAG size of input: 131 DAG size of output 85 [2018-04-11 12:52:27,461 WARN L151 SmtUtils]: Spent 160ms on a formula simplification. DAG size of input: 106 DAG size of output 73 [2018-04-11 12:52:27,667 WARN L151 SmtUtils]: Spent 169ms on a formula simplification. DAG size of input: 109 DAG size of output 76 [2018-04-11 12:52:27,808 WARN L151 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 87 DAG size of output 65 [2018-04-11 12:52:27,972 WARN L151 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 90 DAG size of output 68 [2018-04-11 12:52:28,593 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:52:28,593 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:52:28,593 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35] total 35 [2018-04-11 12:52:28,593 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:52:28,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:52:28,594 INFO L182 omatonBuilderFactory]: Interpolants [14848#(<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)), 14849#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 14850#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 14815#true, 14816#false, 14817#(<= 1 main_~n~0), 14818#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (<= 1 main_~n~0) (= 1 (select |#valid| |main_#t~malloc13.base|)) (= 0 |main_#t~malloc13.offset|)), 14819#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (= 1 (select |#valid| main_~nondetString1~0.base))), 14820#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (not (= |main_#t~malloc14.base| main_~nondetString1~0.base))), 14821#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 14822#(and (= 0 main_~nondetString1~0.offset) (or (and (<= 7 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (select |#length| main_~nondetString1~0.base))) (and (<= 5 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 8 (select |#length| main_~nondetString1~0.base))) (and (or (<= 14 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (<= 13 (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (and (<= 6 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 10 (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (<= 4 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1)))) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 12 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 11 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 14823#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1)) (- 1)))) (<= 8 (select |#length| |cstrncat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (<= 11 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= 9 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1)) (- 1)))) (<= 6 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 13 (select |#length| |cstrncat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 14 (select |#length| |cstrncat_#in~s1.base|)))) (and (<= 7 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1)) (- 1))))) (and (<= 12 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- 3)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1)) (- 1)))) (<= 5 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 10 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 14824#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 12 (select |#length| cstrncat_~s~0.base))) (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (<= 13 (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 14 (select |#length| cstrncat_~s~0.base))))) (= cstrncat_~s~0.offset 0)), 14825#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 12 (select |#length| cstrncat_~s~0.base))) (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (<= 13 (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 14 (select |#length| cstrncat_~s~0.base)))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (= cstrncat_~s~0.offset 0)), 14826#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (or (<= (+ cstrncat_~s~0.offset 13) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))) (= cstrncat_~s~0.offset 1)), 14827#(and (= cstrncat_~s~0.offset 1) (or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (or (<= (+ cstrncat_~s~0.offset 13) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))))), 14828#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base)))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14829#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base)))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14830#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14831#(or (and (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14832#(or (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14833#(or (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14834#(or (and (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14835#(or (and (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14836#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14837#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 14838#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 14839#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 14840#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 14841#(or (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 14842#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))), 14843#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 14844#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 14845#(or (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 14846#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 14847#(or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))))] [2018-04-11 12:52:28,594 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:52:28,594 INFO L442 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-04-11 12:52:28,595 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-04-11 12:52:28,595 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=248, Invalid=1012, Unknown=0, NotChecked=0, Total=1260 [2018-04-11 12:52:28,595 INFO L87 Difference]: Start difference. First operand 138 states and 147 transitions. Second operand 36 states. [2018-04-11 12:52:28,907 WARN L151 SmtUtils]: Spent 111ms on a formula simplification. DAG size of input: 144 DAG size of output 143 [2018-04-11 12:52:29,244 WARN L148 SmtUtils]: Spent 109ms on a formula simplification that was a NOOP. DAG size: 183 [2018-04-11 12:52:29,616 WARN L151 SmtUtils]: Spent 185ms on a formula simplification. DAG size of input: 201 DAG size of output 200 [2018-04-11 12:52:29,832 WARN L151 SmtUtils]: Spent 165ms on a formula simplification. DAG size of input: 193 DAG size of output 186 [2018-04-11 12:52:30,021 WARN L151 SmtUtils]: Spent 163ms on a formula simplification. DAG size of input: 196 DAG size of output 193 [2018-04-11 12:52:30,209 WARN L151 SmtUtils]: Spent 136ms on a formula simplification. DAG size of input: 185 DAG size of output 178 [2018-04-11 12:52:30,385 WARN L151 SmtUtils]: Spent 152ms on a formula simplification. DAG size of input: 188 DAG size of output 185 [2018-04-11 12:52:30,568 WARN L151 SmtUtils]: Spent 141ms on a formula simplification. DAG size of input: 177 DAG size of output 170 [2018-04-11 12:52:30,733 WARN L151 SmtUtils]: Spent 138ms on a formula simplification. DAG size of input: 180 DAG size of output 177 [2018-04-11 12:52:30,895 WARN L151 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 169 DAG size of output 162 [2018-04-11 12:52:31,074 WARN L151 SmtUtils]: Spent 150ms on a formula simplification. DAG size of input: 172 DAG size of output 169 [2018-04-11 12:52:31,251 WARN L151 SmtUtils]: Spent 126ms on a formula simplification. DAG size of input: 161 DAG size of output 154 [2018-04-11 12:52:31,422 WARN L151 SmtUtils]: Spent 137ms on a formula simplification. DAG size of input: 164 DAG size of output 161 [2018-04-11 12:52:31,572 WARN L151 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 153 DAG size of output 146 [2018-04-11 12:52:31,739 WARN L151 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 156 DAG size of output 153 [2018-04-11 12:52:31,885 WARN L151 SmtUtils]: Spent 107ms on a formula simplification. DAG size of input: 145 DAG size of output 138 [2018-04-11 12:52:32,056 WARN L151 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 148 DAG size of output 145 [2018-04-11 12:52:32,247 WARN L151 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 137 DAG size of output 131 [2018-04-11 12:52:32,687 WARN L151 SmtUtils]: Spent 105ms on a formula simplification. DAG size of input: 130 DAG size of output 127 [2018-04-11 12:52:33,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:52:33,226 INFO L93 Difference]: Finished difference Result 202 states and 213 transitions. [2018-04-11 12:52:33,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-04-11 12:52:33,227 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 59 [2018-04-11 12:52:33,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:52:33,227 INFO L225 Difference]: With dead ends: 202 [2018-04-11 12:52:33,227 INFO L226 Difference]: Without dead ends: 202 [2018-04-11 12:52:33,228 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1157 ImplicationChecksByTransitivity, 12.0s TimeCoverageRelationStatistics Valid=839, Invalid=3583, Unknown=0, NotChecked=0, Total=4422 [2018-04-11 12:52:33,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202 states. [2018-04-11 12:52:33,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202 to 144. [2018-04-11 12:52:33,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-04-11 12:52:33,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 154 transitions. [2018-04-11 12:52:33,229 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 154 transitions. Word has length 59 [2018-04-11 12:52:33,230 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:52:33,230 INFO L459 AbstractCegarLoop]: Abstraction has 144 states and 154 transitions. [2018-04-11 12:52:33,230 INFO L460 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-04-11 12:52:33,230 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 154 transitions. [2018-04-11 12:52:33,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-04-11 12:52:33,230 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:52:33,230 INFO L355 BasicCegarLoop]: trace histogram [8, 8, 7, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:52:33,230 INFO L408 AbstractCegarLoop]: === Iteration 44 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:52:33,230 INFO L82 PathProgramCache]: Analyzing trace with hash -1038445559, now seen corresponding path program 7 times [2018-04-11 12:52:33,230 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:52:33,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:52:33,238 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:52:33,620 WARN L151 SmtUtils]: Spent 145ms on a formula simplification. DAG size of input: 90 DAG size of output 76 [2018-04-11 12:52:33,757 WARN L151 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 88 DAG size of output 74 [2018-04-11 12:52:33,877 WARN L151 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 75 DAG size of output 62 [2018-04-11 12:52:33,994 WARN L151 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 75 DAG size of output 62 [2018-04-11 12:52:34,739 INFO L134 CoverageAnalysis]: Checked inductivity of 101 backedges. 0 proven. 101 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:52:34,739 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:52:34,740 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2018-04-11 12:52:34,740 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:52:34,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:52:34,740 INFO L182 omatonBuilderFactory]: Interpolants [15259#true, 15260#false, 15261#(<= 1 main_~n~0), 15262#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 15263#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 15264#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 15265#(and (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 15266#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 15267#(and (= 0 main_~nondetString2~0.offset) (or (and (<= (+ main_~nondetString1~0.offset main_~length2~0 6) (select |#length| main_~nondetString1~0.base)) (or (<= (+ main_~nondetString1~0.offset main_~length2~0 7) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3))) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~nondetString1~0.offset main_~length2~0 3) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3))) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~nondetString1~0.offset main_~length2~0 4) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (- main_~length2~0))) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~nondetString1~0.offset main_~length2~0 5) (select |#length| main_~nondetString1~0.base))) (and (<= 1 main_~n~0) (<= main_~n~0 (+ main_~nondetString1~0.offset 2)))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 15268#(and (= 0 main_~nondetString2~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (or (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset 7) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3))) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset 6) (select |#length| main_~nondetString1~0.base))) (and (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset 4) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3))) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 1 main_~n~0) (<= main_~n~0 (+ main_~nondetString1~0.offset 2))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset 3) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (- (select |#length| main_~nondetString2~0.base)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset 5) (select |#length| main_~nondetString1~0.base)))) (= main_~nondetString1~0.offset 0)), 15269#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (or (and (<= (+ (select |#length| |cstrncat_#in~s2.base|) 6) (select |#length| |cstrncat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 3) 1) 1)) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~s2.base|) 7) (select |#length| |cstrncat_#in~s1.base|)))) (and (<= (+ (select |#length| |cstrncat_#in~s2.base|) 5) (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- (select |#length| |cstrncat_#in~s2.base|))) (- 1))))) (and (<= (+ (select |#length| |cstrncat_#in~s2.base|) 3) (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 3)) (- 1))))) (and (<= |cstrncat_#in~n| 2) (<= 1 |cstrncat_#in~n|)) (and (<= (+ (select |#length| |cstrncat_#in~s2.base|) 4) (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 3) 1)) (- 1))))))), 15270#(and (or (and (<= (+ (select |#length| cstrncat_~s2.base) 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (<= (+ (select |#length| cstrncat_~s2.base) 6) (select |#length| cstrncat_~s~0.base)) (or (<= (+ (select |#length| cstrncat_~s2.base) 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1)) (- 1)))) (<= (+ (select |#length| cstrncat_~s2.base) 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- (select |#length| cstrncat_~s2.base))) (- 1)))) (<= (+ (select |#length| cstrncat_~s2.base) 5) (select |#length| cstrncat_~s~0.base))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (= 0 cstrncat_~s2.offset) (= cstrncat_~s~0.offset 0)), 15271#(and (or (and (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1) 1)) (- 1)))))) (and (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1)) (- 1)))) (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s2.base)) (+ (- cstrncat_~s~0.offset) 1))) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (= 0 cstrncat_~s2.offset)), 15272#(and (= 0 cstrncat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))), 15273#(and (= 0 cstrncat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (<= (select |#length| cstrncat_~s2.base) 2) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))), 15274#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (= 0 cstrncat_~s2.offset)), 15275#(and (= 0 cstrncat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| cstrncat_~s2.base) 2) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))), 15276#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1)))))) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (= 0 cstrncat_~s2.offset))), 15277#(or (and (or (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1)))))) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (= 0 cstrncat_~s2.offset)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 15278#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 cstrncat_~s2.offset) (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))))), 15279#(or (and (= 0 cstrncat_~s2.offset) (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 15280#(and (= 0 cstrncat_~s2.offset) (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))), 15281#(and (or (<= (select |#length| cstrncat_~s2.base) 2) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (= 0 cstrncat_~s2.offset)), 15282#(and (= |cstrncat_#t~post4.offset| 0) (or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (<= (+ |cstrncat_#t~post4.offset| (select |#length| cstrncat_~s2.base)) (+ cstrncat_~s2.offset 1)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))), 15283#(or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 15284#(or (and (<= 0 cstrncat_~n) (<= cstrncat_~n 1)) (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1))), 15285#(or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= cstrncat_~n 1)) (not |cstrncat_#t~short6|) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1))), 15286#(or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= cstrncat_~n 1)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)), 15287#(and (or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= cstrncat_~n 1)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)) (<= 0 cstrncat_~s~0.offset)), 15288#(and (<= 1 cstrncat_~s~0.offset) (or (and (<= cstrncat_~n 0) (<= 0 cstrncat_~n)) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset))), 15289#(and (<= 1 cstrncat_~s~0.offset) (or (not |cstrncat_#t~short6|) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset))), 15290#(and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| |cstrncat_#t~post4.base|) |cstrncat_#t~post4.offset|))), 15291#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))] [2018-04-11 12:52:34,740 INFO L134 CoverageAnalysis]: Checked inductivity of 101 backedges. 0 proven. 101 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:52:34,740 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-04-11 12:52:34,740 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-04-11 12:52:34,741 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=128, Invalid=928, Unknown=0, NotChecked=0, Total=1056 [2018-04-11 12:52:34,741 INFO L87 Difference]: Start difference. First operand 144 states and 154 transitions. Second operand 33 states. [2018-04-11 12:52:36,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:52:36,246 INFO L93 Difference]: Finished difference Result 182 states and 192 transitions. [2018-04-11 12:52:36,246 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-04-11 12:52:36,246 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 61 [2018-04-11 12:52:36,246 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:52:36,246 INFO L225 Difference]: With dead ends: 182 [2018-04-11 12:52:36,247 INFO L226 Difference]: Without dead ends: 182 [2018-04-11 12:52:36,247 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 744 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=360, Invalid=2396, Unknown=0, NotChecked=0, Total=2756 [2018-04-11 12:52:36,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-04-11 12:52:36,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 144. [2018-04-11 12:52:36,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-04-11 12:52:36,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 154 transitions. [2018-04-11 12:52:36,249 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 154 transitions. Word has length 61 [2018-04-11 12:52:36,249 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:52:36,249 INFO L459 AbstractCegarLoop]: Abstraction has 144 states and 154 transitions. [2018-04-11 12:52:36,249 INFO L460 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-04-11 12:52:36,249 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 154 transitions. [2018-04-11 12:52:36,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-04-11 12:52:36,250 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:52:36,250 INFO L355 BasicCegarLoop]: trace histogram [15, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:52:36,250 INFO L408 AbstractCegarLoop]: === Iteration 45 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:52:36,250 INFO L82 PathProgramCache]: Analyzing trace with hash 1671568858, now seen corresponding path program 12 times [2018-04-11 12:52:36,251 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:52:36,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:52:36,264 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:52:49,567 WARN L151 SmtUtils]: Spent 884ms on a formula simplification. DAG size of input: 255 DAG size of output 130 [2018-04-11 12:52:50,390 WARN L151 SmtUtils]: Spent 780ms on a formula simplification. DAG size of input: 226 DAG size of output 108 [2018-04-11 12:52:51,180 WARN L151 SmtUtils]: Spent 749ms on a formula simplification. DAG size of input: 226 DAG size of output 108 [2018-04-11 12:52:52,014 WARN L151 SmtUtils]: Spent 788ms on a formula simplification. DAG size of input: 229 DAG size of output 111 [2018-04-11 12:52:52,874 WARN L151 SmtUtils]: Spent 811ms on a formula simplification. DAG size of input: 249 DAG size of output 120 [2018-04-11 12:52:53,805 WARN L151 SmtUtils]: Spent 875ms on a formula simplification. DAG size of input: 252 DAG size of output 123 [2018-04-11 12:52:54,450 WARN L151 SmtUtils]: Spent 596ms on a formula simplification. DAG size of input: 207 DAG size of output 110 [2018-04-11 12:52:55,094 WARN L151 SmtUtils]: Spent 590ms on a formula simplification. DAG size of input: 210 DAG size of output 113 [2018-04-11 12:52:55,592 WARN L151 SmtUtils]: Spent 454ms on a formula simplification. DAG size of input: 178 DAG size of output 100 [2018-04-11 12:52:56,186 WARN L151 SmtUtils]: Spent 539ms on a formula simplification. DAG size of input: 181 DAG size of output 103 [2018-04-11 12:52:56,582 WARN L151 SmtUtils]: Spent 352ms on a formula simplification. DAG size of input: 152 DAG size of output 91 [2018-04-11 12:52:57,001 WARN L151 SmtUtils]: Spent 371ms on a formula simplification. DAG size of input: 155 DAG size of output 94 [2018-04-11 12:52:57,286 WARN L151 SmtUtils]: Spent 244ms on a formula simplification. DAG size of input: 128 DAG size of output 82 [2018-04-11 12:52:57,601 WARN L151 SmtUtils]: Spent 271ms on a formula simplification. DAG size of input: 131 DAG size of output 85 [2018-04-11 12:52:57,836 WARN L151 SmtUtils]: Spent 187ms on a formula simplification. DAG size of input: 107 DAG size of output 74 [2018-04-11 12:52:58,092 WARN L151 SmtUtils]: Spent 196ms on a formula simplification. DAG size of input: 110 DAG size of output 77 [2018-04-11 12:52:58,256 WARN L151 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 87 DAG size of output 65 [2018-04-11 12:52:58,419 WARN L151 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 90 DAG size of output 68 [2018-04-11 12:52:59,080 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:52:59,080 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:52:59,080 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36] total 36 [2018-04-11 12:52:59,080 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:52:59,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:52:59,081 INFO L182 omatonBuilderFactory]: Interpolants [15680#(or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 15681#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 15682#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 15683#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 15684#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 15685#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 15686#(or (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 15687#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))), 15688#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 15689#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 15690#(or (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 15691#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 15692#(or (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 15693#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base))), 15694#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)), 15658#true, 15659#false, 15660#(<= 1 main_~n~0), 15661#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (<= 1 main_~n~0) (= 1 (select |#valid| |main_#t~malloc13.base|)) (= 0 |main_#t~malloc13.offset|)), 15662#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (= 1 (select |#valid| main_~nondetString1~0.base))), 15663#(and (= 0 main_~nondetString1~0.offset) (not (= |main_#t~malloc14.base| main_~nondetString1~0.base)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 15664#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)))), 15665#(and (or (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 8 (select |#length| main_~nondetString1~0.base))) (and (<= 6 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 10 (select |#length| main_~nondetString1~0.base))) (and (<= 11 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 7 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (select |#length| main_~nondetString1~0.base))) (and (<= 5 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 4 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ main_~nondetString1~0.offset (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1)))) (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 13 (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 12 (select |#length| main_~nondetString1~0.base))) (and (<= 14 (select |#length| main_~nondetString1~0.base)) (or (<= 15 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))))) (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 15666#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1)) (- 1)))) (<= 8 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 9 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1)) (- 1)))) (<= 6 (select |#length| |cstrncat_#in~s1.base|))) (and (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 15 (select |#length| |cstrncat_#in~s1.base|))) (<= 14 (select |#length| |cstrncat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)) (and (<= 13 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- 3)) (- 1))))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (<= 12 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= 11 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= 7 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1)) (- 1)))) (<= 5 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 10 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1) 1)) (- 1))))))), 15667#(and (or (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 13 (select |#length| cstrncat_~s~0.base))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~s~0.base))) (and (<= 12 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 15 (select |#length| cstrncat_~s~0.base))) (<= 14 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base)))) (= cstrncat_~s~0.offset 0)), 15668#(and (= cstrncat_~s~0.offset 0) (or (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 13 (select |#length| cstrncat_~s~0.base))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~s~0.base))) (and (<= 12 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 15 (select |#length| cstrncat_~s~0.base))) (<= 14 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))))), 15669#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 13) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 14) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))) (= cstrncat_~s~0.offset 1)), 15670#(and (or (and (<= (+ cstrncat_~s~0.offset 13) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 14) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))) (= cstrncat_~s~0.offset 1)), 15671#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 13) (select |#length| cstrncat_~s~0.base))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 15672#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 13) (select |#length| cstrncat_~s~0.base))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 15673#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 15674#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 15675#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 15676#(or (and (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 15677#(or (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 15678#(or (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 15679#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))))] [2018-04-11 12:52:59,081 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:52:59,082 INFO L442 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-04-11 12:52:59,082 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-04-11 12:52:59,082 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=273, Invalid=1059, Unknown=0, NotChecked=0, Total=1332 [2018-04-11 12:52:59,082 INFO L87 Difference]: Start difference. First operand 144 states and 154 transitions. Second operand 37 states. [2018-04-11 12:52:59,418 WARN L151 SmtUtils]: Spent 129ms on a formula simplification. DAG size of input: 152 DAG size of output 151 [2018-04-11 12:53:00,220 WARN L151 SmtUtils]: Spent 176ms on a formula simplification. DAG size of input: 209 DAG size of output 202 [2018-04-11 12:53:00,436 WARN L151 SmtUtils]: Spent 192ms on a formula simplification. DAG size of input: 215 DAG size of output 206 [2018-04-11 12:53:00,646 WARN L151 SmtUtils]: Spent 160ms on a formula simplification. DAG size of input: 201 DAG size of output 194 [2018-04-11 12:53:00,863 WARN L151 SmtUtils]: Spent 187ms on a formula simplification. DAG size of input: 207 DAG size of output 198 [2018-04-11 12:53:01,065 WARN L151 SmtUtils]: Spent 160ms on a formula simplification. DAG size of input: 193 DAG size of output 186 [2018-04-11 12:53:01,261 WARN L151 SmtUtils]: Spent 166ms on a formula simplification. DAG size of input: 199 DAG size of output 190 [2018-04-11 12:53:01,469 WARN L151 SmtUtils]: Spent 167ms on a formula simplification. DAG size of input: 185 DAG size of output 178 [2018-04-11 12:53:01,802 WARN L151 SmtUtils]: Spent 253ms on a formula simplification. DAG size of input: 191 DAG size of output 185 [2018-04-11 12:53:01,996 WARN L151 SmtUtils]: Spent 146ms on a formula simplification. DAG size of input: 177 DAG size of output 170 [2018-04-11 12:53:02,196 WARN L151 SmtUtils]: Spent 163ms on a formula simplification. DAG size of input: 183 DAG size of output 174 [2018-04-11 12:53:02,384 WARN L151 SmtUtils]: Spent 133ms on a formula simplification. DAG size of input: 169 DAG size of output 162 [2018-04-11 12:53:02,590 WARN L151 SmtUtils]: Spent 141ms on a formula simplification. DAG size of input: 175 DAG size of output 166 [2018-04-11 12:53:02,753 WARN L151 SmtUtils]: Spent 117ms on a formula simplification. DAG size of input: 161 DAG size of output 154 [2018-04-11 12:53:02,940 WARN L151 SmtUtils]: Spent 129ms on a formula simplification. DAG size of input: 167 DAG size of output 158 [2018-04-11 12:53:03,133 WARN L151 SmtUtils]: Spent 112ms on a formula simplification. DAG size of input: 153 DAG size of output 146 [2018-04-11 12:53:03,312 WARN L151 SmtUtils]: Spent 120ms on a formula simplification. DAG size of input: 159 DAG size of output 150 [2018-04-11 12:53:03,460 WARN L151 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 145 DAG size of output 139 [2018-04-11 12:53:03,624 WARN L151 SmtUtils]: Spent 115ms on a formula simplification. DAG size of input: 151 DAG size of output 142 [2018-04-11 12:53:03,920 WARN L151 SmtUtils]: Spent 107ms on a formula simplification. DAG size of input: 141 DAG size of output 135 [2018-04-11 12:53:04,079 WARN L151 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 125 DAG size of output 122 [2018-04-11 12:53:04,232 WARN L151 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 130 DAG size of output 125 [2018-04-11 12:53:04,388 WARN L151 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 118 DAG size of output 115 [2018-04-11 12:53:04,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:53:04,527 INFO L93 Difference]: Finished difference Result 213 states and 225 transitions. [2018-04-11 12:53:04,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-04-11 12:53:04,528 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 62 [2018-04-11 12:53:04,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:53:04,528 INFO L225 Difference]: With dead ends: 213 [2018-04-11 12:53:04,528 INFO L226 Difference]: Without dead ends: 213 [2018-04-11 12:53:04,529 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1284 ImplicationChecksByTransitivity, 15.5s TimeCoverageRelationStatistics Valid=923, Invalid=3907, Unknown=0, NotChecked=0, Total=4830 [2018-04-11 12:53:04,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states. [2018-04-11 12:53:04,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 150. [2018-04-11 12:53:04,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-04-11 12:53:04,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 161 transitions. [2018-04-11 12:53:04,531 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 161 transitions. Word has length 62 [2018-04-11 12:53:04,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:53:04,531 INFO L459 AbstractCegarLoop]: Abstraction has 150 states and 161 transitions. [2018-04-11 12:53:04,531 INFO L460 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-04-11 12:53:04,531 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 161 transitions. [2018-04-11 12:53:04,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-04-11 12:53:04,532 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:53:04,532 INFO L355 BasicCegarLoop]: trace histogram [9, 9, 8, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:53:04,532 INFO L408 AbstractCegarLoop]: === Iteration 46 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:53:04,532 INFO L82 PathProgramCache]: Analyzing trace with hash 1153548874, now seen corresponding path program 8 times [2018-04-11 12:53:04,533 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:53:04,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:53:04,545 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:53:05,004 WARN L151 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 133 DAG size of output 91 [2018-04-11 12:53:05,150 WARN L151 SmtUtils]: Spent 129ms on a formula simplification. DAG size of input: 131 DAG size of output 89 [2018-04-11 12:53:05,365 WARN L151 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 109 DAG size of output 70 [2018-04-11 12:53:06,312 INFO L134 CoverageAnalysis]: Checked inductivity of 125 backedges. 0 proven. 125 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:53:06,312 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:53:06,313 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34] total 34 [2018-04-11 12:53:06,313 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:53:06,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:53:06,313 INFO L182 omatonBuilderFactory]: Interpolants [16128#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 16129#(and (or (<= (+ main_~n~0 3) (+ main_~nondetString1~0.offset main_~length1~0)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 16130#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (and (= 0 |main_#t~malloc14.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (<= (+ main_~n~0 3) (+ main_~nondetString1~0.offset main_~length1~0))) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 16131#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (and (= 0 main_~nondetString2~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (<= (+ main_~n~0 3) (+ main_~nondetString1~0.offset main_~length1~0))) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 16132#(and (or (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 5)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 4)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (select |#length| main_~nondetString1~0.base))) (and (<= 8 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 6 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3)))) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 1 main_~n~0) (<= main_~n~0 (+ main_~nondetString1~0.offset 2))) (and (= 0 main_~nondetString2~0.offset) (<= (+ main_~nondetString1~0.offset main_~length2~0) 2) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))) (and (or (<= 11 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 5))) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (<= 10 (select |#length| main_~nondetString1~0.base)))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 16133#(and (or (and (= 0 main_~nondetString2~0.offset) (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset) 2)) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 5)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 4)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (select |#length| main_~nondetString1~0.base))) (and (<= 8 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 6 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3)))) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 1 main_~n~0) (<= main_~n~0 (+ main_~nondetString1~0.offset 2))) (and (or (<= 11 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 5))) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (<= 10 (select |#length| main_~nondetString1~0.base)))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 16134#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (= 0 |cstrncat_#in~s2.offset|) (<= (select |#length| |cstrncat_#in~s2.base|) 2)) (and (<= 9 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 5)) (- 1))))) (and (<= 7 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 4)) (- 1))))) (and (<= 8 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- 3)) (- 1))))) (and (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 5) 1)) (- 1)))) (<= 11 (select |#length| |cstrncat_#in~s1.base|))) (<= 10 (select |#length| |cstrncat_#in~s1.base|))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 3)) (- 1)))) (<= 6 (select |#length| |cstrncat_#in~s1.base|))) (and (<= |cstrncat_#in~n| 2) (<= 1 |cstrncat_#in~n|)))), 16135#(and (or (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 5)) (- 1))))) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 5) 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~s~0.base))) (<= 10 (select |#length| cstrncat_~s~0.base))) (and (<= 7 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 4)) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (= cstrncat_~s~0.offset 0)), 16136#(or (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 5) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 4)) (- 1))))) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 5)) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16137#(or (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 4)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 5) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 5)) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16138#(or (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 4)) (- 1))))) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 5) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 5)) (- 1))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16139#(or (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 4)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16140#(or (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 4)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16141#(or (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 4)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16142#(or (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 4)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16143#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1)))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16144#(or (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1)))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16145#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16146#(or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16147#(or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16148#(or (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16149#(or (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16150#(or (and (<= (+ (select |#length| cstrncat_~s2.base) |cstrncat_#t~post4.offset|) (+ cstrncat_~s2.offset 1)) (= |cstrncat_#t~post4.offset| 0)) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16151#(or (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 16152#(or (and (<= 0 cstrncat_~n) (<= cstrncat_~n 1)) (and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1))), 16153#(or (and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base))) (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= cstrncat_~n 1)) (not |cstrncat_#t~short6|) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1))), 16154#(or (and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base))) (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= cstrncat_~n 1)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)), 16155#(or (and (<= cstrncat_~n 0) (<= 0 cstrncat_~n)) (and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)), 16156#(or (not |cstrncat_#t~short6|) (and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)), 16157#(or (<= (select |#length| |cstrncat_#t~post4.base|) |cstrncat_#t~post4.offset|) (and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset))), 16158#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)), 16124#true, 16125#false, 16126#(<= 1 main_~n~0), 16127#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))] [2018-04-11 12:53:06,313 INFO L134 CoverageAnalysis]: Checked inductivity of 125 backedges. 0 proven. 125 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:53:06,314 INFO L442 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-04-11 12:53:06,314 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-04-11 12:53:06,314 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=143, Invalid=1047, Unknown=0, NotChecked=0, Total=1190 [2018-04-11 12:53:06,314 INFO L87 Difference]: Start difference. First operand 150 states and 161 transitions. Second operand 35 states. [2018-04-11 12:53:06,904 WARN L151 SmtUtils]: Spent 115ms on a formula simplification. DAG size of input: 136 DAG size of output 133 [2018-04-11 12:53:07,184 WARN L151 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 134 DAG size of output 131 [2018-04-11 12:53:08,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:53:08,664 INFO L93 Difference]: Finished difference Result 191 states and 202 transitions. [2018-04-11 12:53:08,664 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-04-11 12:53:08,664 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 64 [2018-04-11 12:53:08,664 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:53:08,665 INFO L225 Difference]: With dead ends: 191 [2018-04-11 12:53:08,665 INFO L226 Difference]: Without dead ends: 191 [2018-04-11 12:53:08,665 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 892 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=434, Invalid=2758, Unknown=0, NotChecked=0, Total=3192 [2018-04-11 12:53:08,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191 states. [2018-04-11 12:53:08,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191 to 150. [2018-04-11 12:53:08,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-04-11 12:53:08,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 161 transitions. [2018-04-11 12:53:08,667 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 161 transitions. Word has length 64 [2018-04-11 12:53:08,668 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:53:08,668 INFO L459 AbstractCegarLoop]: Abstraction has 150 states and 161 transitions. [2018-04-11 12:53:08,668 INFO L460 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-04-11 12:53:08,668 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 161 transitions. [2018-04-11 12:53:08,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-04-11 12:53:08,668 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:53:08,668 INFO L355 BasicCegarLoop]: trace histogram [16, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:53:08,669 INFO L408 AbstractCegarLoop]: === Iteration 47 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:53:08,669 INFO L82 PathProgramCache]: Analyzing trace with hash 1856975869, now seen corresponding path program 13 times [2018-04-11 12:53:08,669 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:53:08,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:53:08,679 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:53:35,508 WARN L151 SmtUtils]: Spent 1178ms on a formula simplification. DAG size of input: 292 DAG size of output 138 [2018-04-11 12:53:36,565 WARN L151 SmtUtils]: Spent 1005ms on a formula simplification. DAG size of input: 257 DAG size of output 116 [2018-04-11 12:53:37,616 WARN L151 SmtUtils]: Spent 1006ms on a formula simplification. DAG size of input: 257 DAG size of output 116 [2018-04-11 12:53:38,666 WARN L151 SmtUtils]: Spent 999ms on a formula simplification. DAG size of input: 260 DAG size of output 119 [2018-04-11 12:53:39,754 WARN L151 SmtUtils]: Spent 998ms on a formula simplification. DAG size of input: 281 DAG size of output 129 [2018-04-11 12:53:40,863 WARN L151 SmtUtils]: Spent 1044ms on a formula simplification. DAG size of input: 284 DAG size of output 132 [2018-04-11 12:53:41,642 WARN L151 SmtUtils]: Spent 725ms on a formula simplification. DAG size of input: 237 DAG size of output 119 [2018-04-11 12:53:42,446 WARN L151 SmtUtils]: Spent 744ms on a formula simplification. DAG size of input: 240 DAG size of output 122 [2018-04-11 12:53:43,112 WARN L151 SmtUtils]: Spent 615ms on a formula simplification. DAG size of input: 206 DAG size of output 109 [2018-04-11 12:53:43,808 WARN L151 SmtUtils]: Spent 639ms on a formula simplification. DAG size of input: 209 DAG size of output 112 [2018-04-11 12:53:44,313 WARN L151 SmtUtils]: Spent 457ms on a formula simplification. DAG size of input: 178 DAG size of output 100 [2018-04-11 12:53:44,879 WARN L151 SmtUtils]: Spent 513ms on a formula simplification. DAG size of input: 181 DAG size of output 103 [2018-04-11 12:53:45,276 WARN L151 SmtUtils]: Spent 351ms on a formula simplification. DAG size of input: 152 DAG size of output 91 [2018-04-11 12:53:45,680 WARN L151 SmtUtils]: Spent 353ms on a formula simplification. DAG size of input: 155 DAG size of output 94 [2018-04-11 12:53:46,009 WARN L151 SmtUtils]: Spent 272ms on a formula simplification. DAG size of input: 129 DAG size of output 83 [2018-04-11 12:53:46,325 WARN L151 SmtUtils]: Spent 254ms on a formula simplification. DAG size of input: 132 DAG size of output 86 [2018-04-11 12:53:46,547 WARN L151 SmtUtils]: Spent 178ms on a formula simplification. DAG size of input: 107 DAG size of output 74 [2018-04-11 12:53:46,794 WARN L151 SmtUtils]: Spent 196ms on a formula simplification. DAG size of input: 110 DAG size of output 77 [2018-04-11 12:53:46,944 WARN L151 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 86 DAG size of output 64 [2018-04-11 12:53:47,093 WARN L151 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 89 DAG size of output 67 [2018-04-11 12:53:47,841 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:53:47,841 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:53:47,841 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39] total 39 [2018-04-11 12:53:47,841 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:53:47,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:53:47,842 INFO L182 omatonBuilderFactory]: Interpolants [16576#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 16577#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 16578#(or (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 16579#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 16580#(or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 16581#(<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)), 16582#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 16583#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 16544#true, 16545#false, 16546#(<= 1 main_~n~0), 16547#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (<= 1 main_~n~0) (= 1 (select |#valid| |main_#t~malloc13.base|)) (= 0 |main_#t~malloc13.offset|)), 16548#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (= 1 (select |#valid| main_~nondetString1~0.base))), 16549#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (not (= |main_#t~malloc14.base| main_~nondetString1~0.base))), 16550#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (= (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 16551#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 8 (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 13 (select |#length| main_~nondetString1~0.base))) (and (<= 6 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 10 (select |#length| main_~nondetString1~0.base))) (and (<= 15 (select |#length| main_~nondetString1~0.base)) (or (<= 16 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))))) (and (<= 11 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 7 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (select |#length| main_~nondetString1~0.base))) (and (<= 5 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 14 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ main_~nondetString1~0.offset (- 3)))) (+ main_~nondetString1~0.offset (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (<= 4 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1)))) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 1))) 1) 1) 1) 1) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 12 (select |#length| main_~nondetString1~0.base))))), 16552#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1)) (- 1)))) (<= 8 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 14 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- 3)) (- 1))))) (and (<= 9 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1)) (- 1)))) (<= 6 (select |#length| |cstrncat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (<= 12 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= 11 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (or (<= 16 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (<= 15 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 7 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 13 (select |#length| |cstrncat_#in~s1.base|))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1)) (- 1)))) (<= 5 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 10 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1) 1) 1) 1) 1) 1) 1)) (- 1))))))), 16553#(and (or (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (<= 13 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (or (<= 16 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (<= 15 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~s~0.base))) (and (<= 12 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 14 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base)))) (= cstrncat_~s~0.offset 0)), 16554#(and (or (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (<= 13 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (or (<= 16 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (<= 15 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~s~0.base))) (and (<= 12 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- 3)) (- 1)))) (<= 14 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (= cstrncat_~s~0.offset 0)), 16555#(and (or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 15) (select |#length| cstrncat_~s~0.base))) (<= (+ cstrncat_~s~0.offset 14) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 13) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))))) (= cstrncat_~s~0.offset 1)), 16556#(and (= cstrncat_~s~0.offset 1) (or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 15) (select |#length| cstrncat_~s~0.base))) (<= (+ cstrncat_~s~0.offset 14) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 13) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))))), 16557#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 13) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 14) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 16558#(or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 13) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 14) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 16559#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (or (<= (+ cstrncat_~s~0.offset 13) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 16560#(or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (or (<= (+ cstrncat_~s~0.offset 13) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 16561#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 16562#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 12) (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 16563#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 16564#(or (and (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 11) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1) 1)) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 16565#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 16566#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 16567#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 16568#(or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 16569#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 16570#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1) 1)) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1)))))), 16571#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 16572#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 16573#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 16574#(or (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 1) 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 16575#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))] [2018-04-11 12:53:47,842 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:53:47,843 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-04-11 12:53:47,843 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-04-11 12:53:47,843 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=327, Invalid=1233, Unknown=0, NotChecked=0, Total=1560 [2018-04-11 12:53:47,843 INFO L87 Difference]: Start difference. First operand 150 states and 161 transitions. Second operand 40 states. [2018-04-11 12:53:48,172 WARN L151 SmtUtils]: Spent 149ms on a formula simplification. DAG size of input: 162 DAG size of output 161 [2018-04-11 12:53:48,845 WARN L151 SmtUtils]: Spent 195ms on a formula simplification. DAG size of input: 233 DAG size of output 232 [2018-04-11 12:53:49,075 WARN L151 SmtUtils]: Spent 178ms on a formula simplification. DAG size of input: 225 DAG size of output 218 [2018-04-11 12:53:49,298 WARN L151 SmtUtils]: Spent 196ms on a formula simplification. DAG size of input: 228 DAG size of output 225 [2018-04-11 12:53:49,538 WARN L151 SmtUtils]: Spent 184ms on a formula simplification. DAG size of input: 217 DAG size of output 210 [2018-04-11 12:53:49,744 WARN L151 SmtUtils]: Spent 179ms on a formula simplification. DAG size of input: 220 DAG size of output 217 [2018-04-11 12:53:49,957 WARN L151 SmtUtils]: Spent 165ms on a formula simplification. DAG size of input: 209 DAG size of output 202 [2018-04-11 12:53:50,162 WARN L151 SmtUtils]: Spent 174ms on a formula simplification. DAG size of input: 212 DAG size of output 209 [2018-04-11 12:53:50,357 WARN L151 SmtUtils]: Spent 145ms on a formula simplification. DAG size of input: 201 DAG size of output 194 [2018-04-11 12:53:50,547 WARN L151 SmtUtils]: Spent 157ms on a formula simplification. DAG size of input: 204 DAG size of output 201 [2018-04-11 12:53:50,746 WARN L151 SmtUtils]: Spent 151ms on a formula simplification. DAG size of input: 193 DAG size of output 186 [2018-04-11 12:53:50,946 WARN L151 SmtUtils]: Spent 162ms on a formula simplification. DAG size of input: 196 DAG size of output 193 [2018-04-11 12:53:51,146 WARN L151 SmtUtils]: Spent 150ms on a formula simplification. DAG size of input: 185 DAG size of output 178 [2018-04-11 12:53:51,345 WARN L151 SmtUtils]: Spent 147ms on a formula simplification. DAG size of input: 188 DAG size of output 185 [2018-04-11 12:53:51,527 WARN L151 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 177 DAG size of output 170 [2018-04-11 12:53:51,741 WARN L151 SmtUtils]: Spent 144ms on a formula simplification. DAG size of input: 180 DAG size of output 177 [2018-04-11 12:53:51,948 WARN L151 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 169 DAG size of output 162 [2018-04-11 12:53:52,137 WARN L151 SmtUtils]: Spent 129ms on a formula simplification. DAG size of input: 172 DAG size of output 169 [2018-04-11 12:53:52,306 WARN L151 SmtUtils]: Spent 119ms on a formula simplification. DAG size of input: 161 DAG size of output 154 [2018-04-11 12:53:52,483 WARN L151 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 164 DAG size of output 161 [2018-04-11 12:53:52,657 WARN L151 SmtUtils]: Spent 114ms on a formula simplification. DAG size of input: 153 DAG size of output 147 [2018-04-11 12:53:52,828 WARN L151 SmtUtils]: Spent 117ms on a formula simplification. DAG size of input: 156 DAG size of output 153 [2018-04-11 12:53:53,002 WARN L151 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 143 DAG size of output 136 [2018-04-11 12:53:53,166 WARN L151 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 146 DAG size of output 143 [2018-04-11 12:53:53,482 WARN L151 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 136 DAG size of output 133 [2018-04-11 12:53:53,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:53:53,756 INFO L93 Difference]: Finished difference Result 224 states and 237 transitions. [2018-04-11 12:53:53,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-04-11 12:53:53,756 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 65 [2018-04-11 12:53:53,757 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:53:53,757 INFO L225 Difference]: With dead ends: 224 [2018-04-11 12:53:53,757 INFO L226 Difference]: Without dead ends: 224 [2018-04-11 12:53:53,757 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1496 ImplicationChecksByTransitivity, 19.1s TimeCoverageRelationStatistics Valid=1094, Invalid=4456, Unknown=0, NotChecked=0, Total=5550 [2018-04-11 12:53:53,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-04-11 12:53:53,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 156. [2018-04-11 12:53:53,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-04-11 12:53:53,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 168 transitions. [2018-04-11 12:53:53,759 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 168 transitions. Word has length 65 [2018-04-11 12:53:53,759 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:53:53,759 INFO L459 AbstractCegarLoop]: Abstraction has 156 states and 168 transitions. [2018-04-11 12:53:53,759 INFO L460 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-04-11 12:53:53,759 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 168 transitions. [2018-04-11 12:53:53,759 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-04-11 12:53:53,759 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:53:53,759 INFO L355 BasicCegarLoop]: trace histogram [7, 7, 6, 4, 4, 4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:53:53,759 INFO L408 AbstractCegarLoop]: === Iteration 48 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:53:53,760 INFO L82 PathProgramCache]: Analyzing trace with hash -1258986609, now seen corresponding path program 9 times [2018-04-11 12:53:53,760 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:53:53,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:53:53,768 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:53:54,529 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 5 proven. 94 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:53:54,529 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:53:54,529 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2018-04-11 12:53:54,529 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:53:54,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:53:54,529 INFO L182 omatonBuilderFactory]: Interpolants [17034#true, 17035#false, 17036#(<= 1 main_~n~0), 17037#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 17038#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 17039#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 17040#(and (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 17041#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 17042#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (or (and (<= (+ main_~n~0 main_~length2~0 1) (select |#length| main_~nondetString1~0.base)) (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- (select |#length| main_~nondetString1~0.base)) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 2) (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base)))) (= main_~nondetString1~0.offset 0)), 17043#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~n~0) (or (and (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base)) (or (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 2) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- (select |#length| main_~nondetString1~0.base)) 1)) (+ main_~nondetString1~0.offset (- 1)))))))) (and (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString1~0.offset (- 1)))))))) (= main_~nondetString1~0.offset 0)), 17044#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ |cstrncat_#in~n| (- (select |#length| |cstrncat_#in~s1.base|)))) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~s1.base|))) (and (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ |cstrncat_#in~n| (+ (- (select |#length| |cstrncat_#in~s1.base|)) 1))) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n| 2) (select |#length| |cstrncat_#in~s1.base|))) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n| 1) (select |#length| |cstrncat_#in~s1.base|)))) (<= 1 |cstrncat_#in~n|)), 17045#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (or (and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base)) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ cstrncat_~n (- (select |#length| cstrncat_~s~0.base)))) (- 1))))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) 1) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ cstrncat_~n (+ (- (select |#length| cstrncat_~s~0.base)) 1))) (- 1)))) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) 2) (select |#length| cstrncat_~s~0.base))))) (= cstrncat_~s~0.offset 0)), 17046#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (or (and (or (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ cstrncat_~n (+ (- (select |#length| cstrncat_~s~0.base)) 1))) (- 1))))) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ cstrncat_~n (- (select |#length| cstrncat_~s~0.base)))) (- 1))))))), 17047#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (or (and (or (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ cstrncat_~n (+ (- (select |#length| cstrncat_~s~0.base)) 1))) (- 1))))) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 1))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ cstrncat_~n (- (select |#length| cstrncat_~s~0.base)))) (- 1))))))), 17048#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (or (<= (select |#length| cstrncat_~s2.base) 3) (and (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~n cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))))))), 17049#(or (and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (or (<= (select |#length| cstrncat_~s2.base) 3) (and (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~n cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 17050#(or (and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 3))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))), 17051#(or (and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 3))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 17052#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s2.base) 3) (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))) (= 0 cstrncat_~s2.offset)), 17053#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (or (<= (select |#length| cstrncat_~s2.base) 3) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base)))), 17054#(and (<= 1 cstrncat_~n) (= |cstrncat_#t~post4.offset| 0) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base)) (<= (+ (select |#length| cstrncat_~s2.base) |cstrncat_#t~post4.offset|) (+ cstrncat_~s2.offset 2)))), 17055#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 2)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base)))), 17056#(and (or (<= cstrncat_~n 0) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 2)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~n)), 17057#(or (not |cstrncat_#t~short6|) (and (or (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 2)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n))), 17058#(and (or (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n)), 17059#(and (or (<= cstrncat_~n 0) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~n)), 17060#(or (and (or (and (not (= cstrncat_~n 0)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1))) (<= 0 cstrncat_~n)) (not |cstrncat_#t~short6|)), 17061#(and (<= 0 cstrncat_~n) (or (and (not (= cstrncat_~n 0)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset))), 17062#(and (<= 0 cstrncat_~n) (or (and (not (= cstrncat_~n 0)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)) (<= 0 cstrncat_~s~0.offset)), 17063#(and (<= 1 cstrncat_~s~0.offset) (or (and (or (<= cstrncat_~n 0) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~n)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset))), 17064#(or (and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset))) (not |cstrncat_#t~short6|)), 17065#(and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| |cstrncat_#t~post4.base|) |cstrncat_#t~post4.offset|))), 17066#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))] [2018-04-11 12:53:54,530 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 5 proven. 94 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:53:54,530 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-04-11 12:53:54,530 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-04-11 12:53:54,530 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=143, Invalid=913, Unknown=0, NotChecked=0, Total=1056 [2018-04-11 12:53:54,530 INFO L87 Difference]: Start difference. First operand 156 states and 168 transitions. Second operand 33 states. [2018-04-11 12:53:55,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:53:55,669 INFO L93 Difference]: Finished difference Result 194 states and 206 transitions. [2018-04-11 12:53:55,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-04-11 12:53:55,669 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 65 [2018-04-11 12:53:55,669 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:53:55,670 INFO L225 Difference]: With dead ends: 194 [2018-04-11 12:53:55,670 INFO L226 Difference]: Without dead ends: 166 [2018-04-11 12:53:55,670 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 873 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=480, Invalid=2600, Unknown=0, NotChecked=0, Total=3080 [2018-04-11 12:53:55,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states. [2018-04-11 12:53:55,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 156. [2018-04-11 12:53:55,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-04-11 12:53:55,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 167 transitions. [2018-04-11 12:53:55,671 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 167 transitions. Word has length 65 [2018-04-11 12:53:55,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:53:55,672 INFO L459 AbstractCegarLoop]: Abstraction has 156 states and 167 transitions. [2018-04-11 12:53:55,672 INFO L460 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-04-11 12:53:55,672 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 167 transitions. [2018-04-11 12:53:55,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-04-11 12:53:55,672 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:53:55,672 INFO L355 BasicCegarLoop]: trace histogram [10, 10, 9, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:53:55,672 INFO L408 AbstractCegarLoop]: === Iteration 49 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:53:55,672 INFO L82 PathProgramCache]: Analyzing trace with hash -2118033303, now seen corresponding path program 10 times [2018-04-11 12:53:55,673 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:53:55,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:53:55,683 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 12:53:56,407 WARN L151 SmtUtils]: Spent 273ms on a formula simplification. DAG size of input: 132 DAG size of output 98 [2018-04-11 12:53:56,676 WARN L151 SmtUtils]: Spent 251ms on a formula simplification. DAG size of input: 128 DAG size of output 94 [2018-04-11 12:53:56,920 WARN L151 SmtUtils]: Spent 227ms on a formula simplification. DAG size of input: 113 DAG size of output 80 [2018-04-11 12:53:57,140 WARN L151 SmtUtils]: Spent 202ms on a formula simplification. DAG size of input: 113 DAG size of output 80 [2018-04-11 12:53:57,388 WARN L151 SmtUtils]: Spent 204ms on a formula simplification. DAG size of input: 114 DAG size of output 81 [2018-04-11 12:53:57,535 WARN L151 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 100 DAG size of output 78 [2018-04-11 12:53:57,696 WARN L151 SmtUtils]: Spent 137ms on a formula simplification. DAG size of input: 103 DAG size of output 81 [2018-04-11 12:53:57,824 WARN L151 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 81 DAG size of output 68 [2018-04-11 12:53:57,965 WARN L151 SmtUtils]: Spent 119ms on a formula simplification. DAG size of input: 84 DAG size of output 71 [2018-04-11 12:53:58,649 INFO L134 CoverageAnalysis]: Checked inductivity of 152 backedges. 0 proven. 152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:53:58,649 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 12:53:58,649 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36] total 36 [2018-04-11 12:53:58,649 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-11 12:53:58,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:53:58,650 INFO L182 omatonBuilderFactory]: Interpolants [17472#(and (= 0 main_~nondetString2~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset 8) (select |#length| main_~nondetString1~0.base)) (or (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset 9) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3))) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))))) (and (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset 4) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3))) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset 5) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3))) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset 6) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3))) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 1 main_~n~0) (<= main_~n~0 (+ main_~nondetString1~0.offset 2))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset 3) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (- (select |#length| main_~nondetString2~0.base)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset 7) (select |#length| main_~nondetString1~0.base)))) (= main_~nondetString1~0.offset 0)), 17473#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 3) 1) 1)) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~s2.base|) 5) (select |#length| |cstrncat_#in~s1.base|))) (and (<= (+ (select |#length| |cstrncat_#in~s2.base|) 8) (select |#length| |cstrncat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 3) 1) 1) 1) 1)) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~s2.base|) 9) (select |#length| |cstrncat_#in~s1.base|)))) (and (<= (+ (select |#length| |cstrncat_#in~s2.base|) 6) (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 3) 1) 1) 1)) (- 1))))) (and (<= (+ (select |#length| |cstrncat_#in~s2.base|) 3) (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (- (select |#length| |cstrncat_#in~s1.base|)) 3)) (- 1))))) (and (<= |cstrncat_#in~n| 2) (<= 1 |cstrncat_#in~n|)) (and (<= (+ (select |#length| |cstrncat_#in~s2.base|) 7) (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (- (select |#length| |cstrncat_#in~s2.base|))) (- 1))))) (and (<= (+ (select |#length| |cstrncat_#in~s2.base|) 4) (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (- (+ (+ (- (select |#length| |cstrncat_#in~s1.base|)) 3) 1)) (- 1))))))), 17474#(and (= 0 cstrncat_~s2.offset) (= cstrncat_~s~0.offset 0) (or (and (<= (+ (select |#length| cstrncat_~s2.base) 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (<= (+ (select |#length| cstrncat_~s2.base) 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1) 1) 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1)) (- 1)))) (<= (+ (select |#length| cstrncat_~s2.base) 4) (select |#length| cstrncat_~s~0.base))) (and (<= (+ (select |#length| cstrncat_~s2.base) 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1) 1)) (- 1))))) (and (or (<= (+ (select |#length| cstrncat_~s2.base) 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1) 1) 1) 1)) (- 1))))) (<= (+ (select |#length| cstrncat_~s2.base) 8) (select |#length| cstrncat_~s~0.base))) (and (<= (+ (select |#length| cstrncat_~s2.base) 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (- (select |#length| cstrncat_~s2.base))) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))), 17475#(and (= 0 cstrncat_~s2.offset) (or (and (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1) 1) 1)) (- 1))))) (and (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1)) (- 1)))) (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1) 1)) (- 1))))) (and (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s2.base)) (+ (- cstrncat_~s~0.offset) 1))) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1) 1) 1) 1)) (- 1)))) (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base))))), 17476#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 cstrncat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1) 1)) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))))), 17477#(or (and (= 0 cstrncat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 3))) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1) 1)) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 17478#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 cstrncat_~s2.offset) (or (and (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))))), 17479#(or (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (= 0 cstrncat_~s2.offset) (or (and (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1) 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1))))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))))), 17480#(and (= 0 cstrncat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))), 17481#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (+ (- (select |#length| cstrncat_~s~0.base)) 3) 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)))) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (= 0 cstrncat_~s2.offset)), 17482#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (= 0 cstrncat_~s2.offset)), 17483#(and (= 0 cstrncat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- cstrncat_~s~0.offset) (- 2))) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| cstrncat_~s2.base) 2) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))), 17484#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1)))))) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (= 0 cstrncat_~s2.offset)), 17485#(and (= 0 cstrncat_~s2.offset) (or (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (- (+ (- (select |#length| cstrncat_~s~0.base)) 3)) (- 1)))))) (<= (select |#length| cstrncat_~s2.base) 2) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))), 17486#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (= 0 cstrncat_~s2.offset)), 17487#(and (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 2) (and (= |cstrncat_#t~mem2| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (= 0 cstrncat_~s2.offset)), 17488#(and (= 0 cstrncat_~s2.offset) (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 2) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))), 17489#(and (or (<= (select |#length| cstrncat_~s2.base) 2) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))) (= 0 cstrncat_~s2.offset)), 17490#(and (= |cstrncat_#t~post4.offset| 0) (or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (<= (+ |cstrncat_#t~post4.offset| (select |#length| cstrncat_~s2.base)) (+ cstrncat_~s2.offset 1)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2)))), 17491#(or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1)) (and (<= 1 cstrncat_~n) (<= cstrncat_~n 2))), 17492#(or (and (<= 0 cstrncat_~n) (<= cstrncat_~n 1)) (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1))), 17493#(or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= cstrncat_~n 1)) (not |cstrncat_#t~short6|) (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1))), 17494#(or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= cstrncat_~n 1)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)), 17495#(and (or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= cstrncat_~n 1)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)) (<= 0 cstrncat_~s~0.offset)), 17496#(and (<= 1 cstrncat_~s~0.offset) (or (and (<= cstrncat_~n 0) (<= 0 cstrncat_~n)) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset))), 17497#(and (<= 1 cstrncat_~s~0.offset) (or (not |cstrncat_#t~short6|) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset))), 17498#(and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| |cstrncat_#t~post4.base|) |cstrncat_#t~post4.offset|))), 17499#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 17463#true, 17464#false, 17465#(<= 1 main_~n~0), 17466#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 17467#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 17468#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 17469#(and (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 17470#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 17471#(and (= 0 main_~nondetString2~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (or (and (or (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3)))) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~nondetString1~0.offset main_~length2~0 3) (select |#length| main_~nondetString1~0.base))) (and (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3))) 1) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~nondetString1~0.offset main_~length2~0 9) (select |#length| main_~nondetString1~0.base))) (<= (+ main_~nondetString1~0.offset main_~length2~0 8) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (- main_~n~0) (- main_~length2~0))) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~nondetString1~0.offset main_~length2~0 7) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3))) 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~nondetString1~0.offset main_~length2~0 4) (select |#length| main_~nondetString1~0.base))) (and (<= (+ main_~nondetString1~0.offset main_~length2~0 5) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3))) 1) 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= (+ main_~nondetString1~0.offset main_~length2~0 6) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (- (+ (+ (+ (+ (- main_~n~0) (+ (- (select |#length| main_~nondetString1~0.base)) (+ main_~nondetString1~0.offset 3))) 1) 1) 1)) (+ main_~nondetString1~0.offset (- 1)))))))) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))) (and (<= 1 main_~n~0) (<= main_~n~0 (+ main_~nondetString1~0.offset 2)))))] [2018-04-11 12:53:58,650 INFO L134 CoverageAnalysis]: Checked inductivity of 152 backedges. 0 proven. 152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 12:53:58,650 INFO L442 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-04-11 12:53:58,651 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-04-11 12:53:58,651 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=149, Invalid=1183, Unknown=0, NotChecked=0, Total=1332 [2018-04-11 12:53:58,651 INFO L87 Difference]: Start difference. First operand 156 states and 167 transitions. Second operand 37 states. [2018-04-11 12:53:59,264 WARN L151 SmtUtils]: Spent 137ms on a formula simplification. DAG size of input: 158 DAG size of output 144 [2018-04-11 12:53:59,424 WARN L151 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 161 DAG size of output 156 [2018-04-11 12:53:59,621 WARN L151 SmtUtils]: Spent 160ms on a formula simplification. DAG size of input: 143 DAG size of output 135 [2018-04-11 12:53:59,788 WARN L151 SmtUtils]: Spent 129ms on a formula simplification. DAG size of input: 146 DAG size of output 138 [2018-04-11 12:54:00,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 12:54:00,974 INFO L93 Difference]: Finished difference Result 197 states and 208 transitions. [2018-04-11 12:54:00,974 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-04-11 12:54:00,974 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 67 [2018-04-11 12:54:00,975 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 12:54:00,975 INFO L225 Difference]: With dead ends: 197 [2018-04-11 12:54:00,975 INFO L226 Difference]: Without dead ends: 197 [2018-04-11 12:54:00,975 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1037 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=487, Invalid=3173, Unknown=0, NotChecked=0, Total=3660 [2018-04-11 12:54:00,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states. [2018-04-11 12:54:00,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 156. [2018-04-11 12:54:00,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-04-11 12:54:00,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 167 transitions. [2018-04-11 12:54:00,977 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 167 transitions. Word has length 67 [2018-04-11 12:54:00,977 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 12:54:00,977 INFO L459 AbstractCegarLoop]: Abstraction has 156 states and 167 transitions. [2018-04-11 12:54:00,977 INFO L460 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-04-11 12:54:00,977 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 167 transitions. [2018-04-11 12:54:00,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-04-11 12:54:00,978 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 12:54:00,978 INFO L355 BasicCegarLoop]: trace histogram [17, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 12:54:00,978 INFO L408 AbstractCegarLoop]: === Iteration 50 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr4EnsuresViolationMEMORY_LEAK, mainErr0RequiresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-04-11 12:54:00,978 INFO L82 PathProgramCache]: Analyzing trace with hash 1989297914, now seen corresponding path program 14 times [2018-04-11 12:54:00,978 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-11 12:54:00,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 12:54:00,989 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. Received shutdown request... [2018-04-11 12:54:19,846 FATAL L265 ToolchainWalker]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: Timeout exceeded at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.walkResolutionNode(Interpolator.java:235) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.access$0(Interpolator.java:233) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator$ProofTreeWalker.walk(Interpolator.java:130) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:122) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:113) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.interpolate(Interpolator.java:220) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.getInterpolants(Interpolator.java:201) at de.uni_freiburg.informatik.ultimate.smtinterpol.smtlib2.SMTInterpol.getInterpolants(SMTInterpol.java:918) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.managedscript.ManagedScript.getInterpolants(ManagedScript.java:192) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.NestedInterpolantsBuilder.computeCraigInterpolants(NestedInterpolantsBuilder.java:281) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.NestedInterpolantsBuilder.(NestedInterpolantsBuilder.java:164) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.InterpolatingTraceCheckCraig.computeInterpolantsTree(InterpolatingTraceCheckCraig.java:267) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.InterpolatingTraceCheckCraig.computeInterpolants(InterpolatingTraceCheckCraig.java:203) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.InterpolatingTraceCheckCraig.(InterpolatingTraceCheckCraig.java:106) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructCraig(TraceCheckConstructor.java:222) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.get(TraceCheckConstructor.java:179) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.FixedRefinementStrategy.getTraceCheck(FixedRefinementStrategy.java:131) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.checkFeasibility(BaseRefinementStrategy.java:231) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.executeStrategy(BaseRefinementStrategy.java:205) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:69) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:408) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:417) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:363) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:304) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:150) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:118) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:119) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:324) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.runToolchainDefault(DefaultToolchainJob.java:221) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.BasicToolchainJob.run(BasicToolchainJob.java:134) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) [2018-04-11 12:54:19,849 INFO L168 Benchmark]: Toolchain (without parser) took 189246.39 ms. Allocated memory was 404.2 MB in the beginning and 1.7 GB in the end (delta: 1.3 GB). Free memory was 336.4 MB in the beginning and 564.1 MB in the end (delta: -227.7 MB). Peak memory consumption was 1.5 GB. Max. memory is 5.3 GB. [2018-04-11 12:54:19,850 INFO L168 Benchmark]: CDTParser took 0.10 ms. Allocated memory is still 404.2 MB. Free memory is still 361.6 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-04-11 12:54:19,850 INFO L168 Benchmark]: CACSL2BoogieTranslator took 248.24 ms. Allocated memory is still 404.2 MB. Free memory was 335.1 MB in the beginning and 311.2 MB in the end (delta: 23.9 MB). Peak memory consumption was 23.9 MB. Max. memory is 5.3 GB. [2018-04-11 12:54:19,850 INFO L168 Benchmark]: Boogie Preprocessor took 31.54 ms. Allocated memory is still 404.2 MB. Free memory was 311.2 MB in the beginning and 308.6 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. [2018-04-11 12:54:19,850 INFO L168 Benchmark]: RCFGBuilder took 416.75 ms. Allocated memory was 404.2 MB in the beginning and 594.0 MB in the end (delta: 189.8 MB). Free memory was 308.6 MB in the beginning and 528.3 MB in the end (delta: -219.7 MB). Peak memory consumption was 23.9 MB. Max. memory is 5.3 GB. [2018-04-11 12:54:19,850 INFO L168 Benchmark]: TraceAbstraction took 188546.87 ms. Allocated memory was 594.0 MB in the beginning and 1.7 GB in the end (delta: 1.1 GB). Free memory was 526.9 MB in the beginning and 564.1 MB in the end (delta: -37.2 MB). Peak memory consumption was 1.5 GB. Max. memory is 5.3 GB. [2018-04-11 12:54:19,851 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10 ms. Allocated memory is still 404.2 MB. Free memory is still 361.6 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 248.24 ms. Allocated memory is still 404.2 MB. Free memory was 335.1 MB in the beginning and 311.2 MB in the end (delta: 23.9 MB). Peak memory consumption was 23.9 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 31.54 ms. Allocated memory is still 404.2 MB. Free memory was 311.2 MB in the beginning and 308.6 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 416.75 ms. Allocated memory was 404.2 MB in the beginning and 594.0 MB in the end (delta: 189.8 MB). Free memory was 308.6 MB in the beginning and 528.3 MB in the end (delta: -219.7 MB). Peak memory consumption was 23.9 MB. Max. memory is 5.3 GB. * TraceAbstraction took 188546.87 ms. Allocated memory was 594.0 MB in the beginning and 1.7 GB in the end (delta: 1.1 GB). Free memory was 526.9 MB in the beginning and 564.1 MB in the end (delta: -37.2 MB). Peak memory consumption was 1.5 GB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: Timeout exceeded de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: Timeout exceeded: de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.walkResolutionNode(Interpolator.java:235) RESULT: Ultimate could not prove your program: Toolchain returned no result. Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrncat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-Benchmark-0-2018-04-11_12-54-19-856.csv Completed graceful shutdown