java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv --cacsl2boogietranslator.bitprecise.bitfields false -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf -i ../../../trunk/examples/svcomp/array-memsafety/lis-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-666feb3-m [2018-04-11 15:12:20,407 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-04-11 15:12:20,409 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-04-11 15:12:20,417 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2018-04-11 15:12:20,433 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf [2018-04-11 15:12:20,449 INFO L110 SettingsManager]: Loading preferences was successful [2018-04-11 15:12:20,449 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-04-11 15:12:20,450 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-04-11 15:12:20,450 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-04-11 15:12:20,450 INFO L133 SettingsManager]: * Use SBE=true [2018-04-11 15:12:20,450 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-04-11 15:12:20,450 INFO L133 SettingsManager]: * sizeof long=4 [2018-04-11 15:12:20,451 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-04-11 15:12:20,451 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-04-11 15:12:20,451 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-04-11 15:12:20,451 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-04-11 15:12:20,451 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-04-11 15:12:20,451 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-04-11 15:12:20,451 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-04-11 15:12:20,451 INFO L133 SettingsManager]: * sizeof long double=12 [2018-04-11 15:12:20,452 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-04-11 15:12:20,452 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-04-11 15:12:20,452 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-04-11 15:12:20,452 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-04-11 15:12:20,452 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-11 15:12:20,452 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-04-11 15:12:20,452 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-04-11 15:12:20,452 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-04-11 15:12:20,453 INFO L133 SettingsManager]: * Trace refinement strategy=SMTINTERPOL Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Bitprecise bitfields -> false [2018-04-11 15:12:20,473 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-04-11 15:12:20,480 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully (re)initialized [2018-04-11 15:12:20,482 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-04-11 15:12:20,485 INFO L271 PluginConnector]: Initializing CDTParser... [2018-04-11 15:12:20,485 INFO L276 PluginConnector]: CDTParser initialized [2018-04-11 15:12:20,485 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,775 INFO L225 CDTParser]: Created temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGe1db26234 [2018-04-11 15:12:20,919 INFO L287 CDTParser]: IsIndexed: true [2018-04-11 15:12:20,919 INFO L288 CDTParser]: Found 1 translation units. [2018-04-11 15:12:20,920 INFO L168 CDTParser]: Scanning lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,929 INFO L210 ultiparseSymbolTable]: Include resolver: [2018-04-11 15:12:20,929 INFO L215 ultiparseSymbolTable]: [2018-04-11 15:12:20,929 INFO L218 ultiparseSymbolTable]: Function table: [2018-04-11 15:12:20,930 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_32 ('__bswap_32') in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,930 INFO L221 ultiparseSymbolTable]: Function definition of null ('main') in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,930 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_64 ('__bswap_64') in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,930 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis ('lis') in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,930 INFO L227 ultiparseSymbolTable]: Global variable table: [2018-04-11 15:12:20,930 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_char in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,930 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__ulong in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,930 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____u_long in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,930 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__blkcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,931 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____int16_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,931 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_rwlockattr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,931 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__daddr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,931 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_int32_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,931 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__clock_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,931 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____pthread_list_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,931 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_barrierattr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,931 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____ino64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,931 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_key_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,932 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__blksize_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,932 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_long in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,932 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____off_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,932 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____caddr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,932 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,932 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____uint32_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,932 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____ino_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,932 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__sigset_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,932 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____sigset_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,933 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____clockid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,933 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__clockid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,933 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_spinlock_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,933 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____suseconds_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,933 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____rlim_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,933 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__quad_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,933 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__fsblkcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,933 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_cond_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,933 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__div_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,934 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_int16_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,934 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____int32_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,934 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__fd_mask in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,934 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__key_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,934 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_int8_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,934 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__wchar_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,934 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lldiv_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,934 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__uid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,934 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__int16_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,935 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____u_char in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,935 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____gid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,935 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____off64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,935 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fd_mask in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,935 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____quad_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,935 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____timer_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,935 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____id_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,935 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_barrier_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,935 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____u_quad_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,935 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____syscall_ulong_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,936 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,936 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsblkcnt64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,936 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____pid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,936 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_int in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,936 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_mutexattr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,936 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__register_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,936 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____int8_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,936 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__off_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,936 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__ldiv_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,937 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__gid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,937 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsword_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,937 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____uint64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,937 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____blkcnt64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,937 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,937 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsfilcnt64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,937 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__int32_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,937 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_attr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,937 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__timer_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,937 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____ssize_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,937 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____sig_atomic_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,937 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____socklen_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,938 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____nlink_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,938 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____mode_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,938 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____uid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,938 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__size_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,938 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__nlink_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,938 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__fsfilcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,938 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____intptr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,938 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__id_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,938 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__ssize_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,938 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_once_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,939 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__uint in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,939 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_short in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,939 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__caddr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,939 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____clock_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,939 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____daddr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,939 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__mode_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,939 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__time_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,939 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____uint8_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,939 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__fsid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,939 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__dev_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,939 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____key_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,940 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____blkcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,940 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____useconds_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,940 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__suseconds_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,940 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____u_short in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,940 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____u_int in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,940 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____loff_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,940 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__fd_set in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,940 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_mutex_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,940 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_rwlock_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,940 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____syscall_slong_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,940 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____dev_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,940 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsblkcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,941 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____blksize_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,941 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____qaddr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,941 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__int8_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,941 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____time_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,941 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__ino_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,941 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__ushort in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,941 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____int64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,941 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_condattr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,941 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____rlim64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,941 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____WAIT_STATUS in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,941 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_quad_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,942 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__int64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,942 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__loff_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,942 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_int64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,942 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____uint16_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,942 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsfilcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:20,956 INFO L330 CDTParser]: Deleted temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGe1db26234 [2018-04-11 15:12:20,960 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-04-11 15:12:20,961 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-04-11 15:12:20,962 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-04-11 15:12:20,963 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-04-11 15:12:20,967 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-04-11 15:12:20,967 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 11.04 03:12:20" (1/1) ... [2018-04-11 15:12:20,969 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@709e8c38 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 03:12:20, skipping insertion in model container [2018-04-11 15:12:20,969 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 11.04 03:12:20" (1/1) ... [2018-04-11 15:12:20,984 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-11 15:12:21,006 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-11 15:12:21,130 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-11 15:12:21,165 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-11 15:12:21,171 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-11 15:12:21,207 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 03:12:21 WrapperNode [2018-04-11 15:12:21,207 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-04-11 15:12:21,208 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-04-11 15:12:21,208 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-04-11 15:12:21,208 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-04-11 15:12:21,220 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 03:12:21" (1/1) ... [2018-04-11 15:12:21,220 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 03:12:21" (1/1) ... [2018-04-11 15:12:21,232 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 03:12:21" (1/1) ... [2018-04-11 15:12:21,233 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 03:12:21" (1/1) ... [2018-04-11 15:12:21,241 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 03:12:21" (1/1) ... [2018-04-11 15:12:21,246 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 03:12:21" (1/1) ... [2018-04-11 15:12:21,249 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 03:12:21" (1/1) ... [2018-04-11 15:12:21,252 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-04-11 15:12:21,253 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-04-11 15:12:21,253 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-04-11 15:12:21,253 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-04-11 15:12:21,254 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 03:12:21" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-11 15:12:21,332 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-04-11 15:12:21,333 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-04-11 15:12:21,333 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-11 15:12:21,333 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-11 15:12:21,333 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis [2018-04-11 15:12:21,333 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-04-11 15:12:21,333 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-11 15:12:21,333 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-11 15:12:21,333 INFO L128 BoogieDeclarations]: Found specification of procedure __ctype_get_mb_cur_max [2018-04-11 15:12:21,333 INFO L128 BoogieDeclarations]: Found specification of procedure atof [2018-04-11 15:12:21,333 INFO L128 BoogieDeclarations]: Found specification of procedure atoi [2018-04-11 15:12:21,334 INFO L128 BoogieDeclarations]: Found specification of procedure atol [2018-04-11 15:12:21,334 INFO L128 BoogieDeclarations]: Found specification of procedure atoll [2018-04-11 15:12:21,334 INFO L128 BoogieDeclarations]: Found specification of procedure strtod [2018-04-11 15:12:21,334 INFO L128 BoogieDeclarations]: Found specification of procedure strtof [2018-04-11 15:12:21,334 INFO L128 BoogieDeclarations]: Found specification of procedure strtold [2018-04-11 15:12:21,334 INFO L128 BoogieDeclarations]: Found specification of procedure strtol [2018-04-11 15:12:21,334 INFO L128 BoogieDeclarations]: Found specification of procedure strtoul [2018-04-11 15:12:21,334 INFO L128 BoogieDeclarations]: Found specification of procedure strtoq [2018-04-11 15:12:21,334 INFO L128 BoogieDeclarations]: Found specification of procedure strtouq [2018-04-11 15:12:21,335 INFO L128 BoogieDeclarations]: Found specification of procedure strtoll [2018-04-11 15:12:21,335 INFO L128 BoogieDeclarations]: Found specification of procedure strtoull [2018-04-11 15:12:21,335 INFO L128 BoogieDeclarations]: Found specification of procedure l64a [2018-04-11 15:12:21,335 INFO L128 BoogieDeclarations]: Found specification of procedure a64l [2018-04-11 15:12:21,335 INFO L128 BoogieDeclarations]: Found specification of procedure select [2018-04-11 15:12:21,335 INFO L128 BoogieDeclarations]: Found specification of procedure pselect [2018-04-11 15:12:21,335 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_major [2018-04-11 15:12:21,335 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_minor [2018-04-11 15:12:21,335 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_makedev [2018-04-11 15:12:21,335 INFO L128 BoogieDeclarations]: Found specification of procedure random [2018-04-11 15:12:21,336 INFO L128 BoogieDeclarations]: Found specification of procedure srandom [2018-04-11 15:12:21,336 INFO L128 BoogieDeclarations]: Found specification of procedure initstate [2018-04-11 15:12:21,336 INFO L128 BoogieDeclarations]: Found specification of procedure setstate [2018-04-11 15:12:21,336 INFO L128 BoogieDeclarations]: Found specification of procedure random_r [2018-04-11 15:12:21,336 INFO L128 BoogieDeclarations]: Found specification of procedure srandom_r [2018-04-11 15:12:21,336 INFO L128 BoogieDeclarations]: Found specification of procedure initstate_r [2018-04-11 15:12:21,336 INFO L128 BoogieDeclarations]: Found specification of procedure setstate_r [2018-04-11 15:12:21,336 INFO L128 BoogieDeclarations]: Found specification of procedure rand [2018-04-11 15:12:21,336 INFO L128 BoogieDeclarations]: Found specification of procedure srand [2018-04-11 15:12:21,337 INFO L128 BoogieDeclarations]: Found specification of procedure rand_r [2018-04-11 15:12:21,337 INFO L128 BoogieDeclarations]: Found specification of procedure drand48 [2018-04-11 15:12:21,337 INFO L128 BoogieDeclarations]: Found specification of procedure erand48 [2018-04-11 15:12:21,337 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48 [2018-04-11 15:12:21,337 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48 [2018-04-11 15:12:21,337 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48 [2018-04-11 15:12:21,337 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48 [2018-04-11 15:12:21,337 INFO L128 BoogieDeclarations]: Found specification of procedure srand48 [2018-04-11 15:12:21,337 INFO L128 BoogieDeclarations]: Found specification of procedure seed48 [2018-04-11 15:12:21,337 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48 [2018-04-11 15:12:21,337 INFO L128 BoogieDeclarations]: Found specification of procedure drand48_r [2018-04-11 15:12:21,337 INFO L128 BoogieDeclarations]: Found specification of procedure erand48_r [2018-04-11 15:12:21,337 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48_r [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48_r [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48_r [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48_r [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure srand48_r [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure seed48_r [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48_r [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure realloc [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure cfree [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure alloca [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure valloc [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure posix_memalign [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure abort [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure atexit [2018-04-11 15:12:21,338 INFO L128 BoogieDeclarations]: Found specification of procedure on_exit [2018-04-11 15:12:21,339 INFO L128 BoogieDeclarations]: Found specification of procedure exit [2018-04-11 15:12:21,339 INFO L128 BoogieDeclarations]: Found specification of procedure _Exit [2018-04-11 15:12:21,339 INFO L128 BoogieDeclarations]: Found specification of procedure getenv [2018-04-11 15:12:21,339 INFO L128 BoogieDeclarations]: Found specification of procedure putenv [2018-04-11 15:12:21,339 INFO L128 BoogieDeclarations]: Found specification of procedure setenv [2018-04-11 15:12:21,339 INFO L128 BoogieDeclarations]: Found specification of procedure unsetenv [2018-04-11 15:12:21,339 INFO L128 BoogieDeclarations]: Found specification of procedure clearenv [2018-04-11 15:12:21,339 INFO L128 BoogieDeclarations]: Found specification of procedure mktemp [2018-04-11 15:12:21,339 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemp [2018-04-11 15:12:21,339 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemps [2018-04-11 15:12:21,340 INFO L128 BoogieDeclarations]: Found specification of procedure mkdtemp [2018-04-11 15:12:21,340 INFO L128 BoogieDeclarations]: Found specification of procedure system [2018-04-11 15:12:21,340 INFO L128 BoogieDeclarations]: Found specification of procedure realpath [2018-04-11 15:12:21,340 INFO L128 BoogieDeclarations]: Found specification of procedure bsearch [2018-04-11 15:12:21,340 INFO L128 BoogieDeclarations]: Found specification of procedure qsort [2018-04-11 15:12:21,340 INFO L128 BoogieDeclarations]: Found specification of procedure abs [2018-04-11 15:12:21,340 INFO L128 BoogieDeclarations]: Found specification of procedure labs [2018-04-11 15:12:21,340 INFO L128 BoogieDeclarations]: Found specification of procedure llabs [2018-04-11 15:12:21,340 INFO L128 BoogieDeclarations]: Found specification of procedure div [2018-04-11 15:12:21,340 INFO L128 BoogieDeclarations]: Found specification of procedure ldiv [2018-04-11 15:12:21,340 INFO L128 BoogieDeclarations]: Found specification of procedure lldiv [2018-04-11 15:12:21,341 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt [2018-04-11 15:12:21,341 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt [2018-04-11 15:12:21,341 INFO L128 BoogieDeclarations]: Found specification of procedure gcvt [2018-04-11 15:12:21,341 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt [2018-04-11 15:12:21,341 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt [2018-04-11 15:12:21,341 INFO L128 BoogieDeclarations]: Found specification of procedure qgcvt [2018-04-11 15:12:21,341 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt_r [2018-04-11 15:12:21,341 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt_r [2018-04-11 15:12:21,341 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt_r [2018-04-11 15:12:21,341 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt_r [2018-04-11 15:12:21,341 INFO L128 BoogieDeclarations]: Found specification of procedure mblen [2018-04-11 15:12:21,341 INFO L128 BoogieDeclarations]: Found specification of procedure mbtowc [2018-04-11 15:12:21,342 INFO L128 BoogieDeclarations]: Found specification of procedure wctomb [2018-04-11 15:12:21,342 INFO L128 BoogieDeclarations]: Found specification of procedure mbstowcs [2018-04-11 15:12:21,342 INFO L128 BoogieDeclarations]: Found specification of procedure wcstombs [2018-04-11 15:12:21,342 INFO L128 BoogieDeclarations]: Found specification of procedure rpmatch [2018-04-11 15:12:21,342 INFO L128 BoogieDeclarations]: Found specification of procedure getsubopt [2018-04-11 15:12:21,342 INFO L128 BoogieDeclarations]: Found specification of procedure getloadavg [2018-04-11 15:12:21,342 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-04-11 15:12:21,342 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis [2018-04-11 15:12:21,342 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-04-11 15:12:21,343 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-04-11 15:12:21,343 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-04-11 15:12:21,343 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-04-11 15:12:21,343 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-04-11 15:12:21,343 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-04-11 15:12:21,343 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-04-11 15:12:21,343 INFO L128 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-04-11 15:12:21,662 INFO L259 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-04-11 15:12:21,663 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.04 03:12:21 BoogieIcfgContainer [2018-04-11 15:12:21,663 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-04-11 15:12:21,663 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-04-11 15:12:21,663 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-04-11 15:12:21,665 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-04-11 15:12:21,665 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 11.04 03:12:20" (1/3) ... [2018-04-11 15:12:21,666 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d820281 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.04 03:12:21, skipping insertion in model container [2018-04-11 15:12:21,666 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 03:12:21" (2/3) ... [2018-04-11 15:12:21,666 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d820281 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.04 03:12:21, skipping insertion in model container [2018-04-11 15:12:21,666 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.04 03:12:21" (3/3) ... [2018-04-11 15:12:21,667 INFO L107 eAbstractionObserver]: Analyzing ICFG lis-alloca_true-valid-memsafety_true-termination.i [2018-04-11 15:12:21,674 INFO L131 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-04-11 15:12:21,680 INFO L143 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2018-04-11 15:12:21,706 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-04-11 15:12:21,707 INFO L369 AbstractCegarLoop]: Interprodecural is true [2018-04-11 15:12:21,707 INFO L370 AbstractCegarLoop]: Hoare is false [2018-04-11 15:12:21,707 INFO L371 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-04-11 15:12:21,707 INFO L372 AbstractCegarLoop]: Backedges is TWOTRACK [2018-04-11 15:12:21,707 INFO L373 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-04-11 15:12:21,707 INFO L374 AbstractCegarLoop]: Difference is false [2018-04-11 15:12:21,707 INFO L375 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-04-11 15:12:21,707 INFO L380 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-04-11 15:12:21,708 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-04-11 15:12:21,716 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states. [2018-04-11 15:12:21,722 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-04-11 15:12:21,722 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:21,722 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:21,722 INFO L408 AbstractCegarLoop]: === Iteration 1 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:21,725 INFO L82 PathProgramCache]: Analyzing trace with hash 903315809, now seen corresponding path program 1 times [2018-04-11 15:12:21,726 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:21,726 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:21,754 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:21,754 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:21,754 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:21,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:21,798 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:21,812 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 15:12:21,812 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 15:12:21,813 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 15:12:21,813 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:21,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:21,856 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 15:12:21,890 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 15:12:21,891 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:21,895 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 15:12:21,895 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-11 15:12:21,915 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 15:12:21,916 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 15:12:21,917 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-11 15:12:21,917 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:21,923 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-11 15:12:21,924 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-04-11 15:12:21,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 15:12:21,946 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 15:12:21,946 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-11 15:12:21,948 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-11 15:12:21,956 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-11 15:12:21,956 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-04-11 15:12:21,958 INFO L87 Difference]: Start difference. First operand 84 states. Second operand 5 states. [2018-04-11 15:12:22,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:22,063 INFO L93 Difference]: Finished difference Result 77 states and 84 transitions. [2018-04-11 15:12:22,063 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-11 15:12:22,064 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 18 [2018-04-11 15:12:22,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:22,072 INFO L225 Difference]: With dead ends: 77 [2018-04-11 15:12:22,072 INFO L226 Difference]: Without dead ends: 74 [2018-04-11 15:12:22,073 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-04-11 15:12:22,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-04-11 15:12:22,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 74. [2018-04-11 15:12:22,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-04-11 15:12:22,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 81 transitions. [2018-04-11 15:12:22,095 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 81 transitions. Word has length 18 [2018-04-11 15:12:22,095 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:22,095 INFO L459 AbstractCegarLoop]: Abstraction has 74 states and 81 transitions. [2018-04-11 15:12:22,096 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-11 15:12:22,096 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 81 transitions. [2018-04-11 15:12:22,096 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-04-11 15:12:22,096 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:22,096 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:22,096 INFO L408 AbstractCegarLoop]: === Iteration 2 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:22,096 INFO L82 PathProgramCache]: Analyzing trace with hash 903315810, now seen corresponding path program 1 times [2018-04-11 15:12:22,096 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:22,096 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:22,097 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:22,097 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:22,097 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:22,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:22,107 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:22,118 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 15:12:22,118 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 15:12:22,119 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 15:12:22,119 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:22,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:22,146 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 15:12:22,161 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-11 15:12:22,162 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:22,171 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 15:12:22,171 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:22,183 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 15:12:22,183 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-04-11 15:12:22,213 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 15:12:22,214 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 15:12:22,215 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-11 15:12:22,215 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:22,226 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-11 15:12:22,227 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:22,240 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-11 15:12:22,240 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:32, output treesize:25 [2018-04-11 15:12:22,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 15:12:22,288 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 15:12:22,288 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-04-11 15:12:22,289 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-11 15:12:22,289 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-11 15:12:22,290 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-04-11 15:12:22,290 INFO L87 Difference]: Start difference. First operand 74 states and 81 transitions. Second operand 9 states. [2018-04-11 15:12:22,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:22,663 INFO L93 Difference]: Finished difference Result 88 states and 96 transitions. [2018-04-11 15:12:22,664 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-11 15:12:22,664 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 18 [2018-04-11 15:12:22,664 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:22,665 INFO L225 Difference]: With dead ends: 88 [2018-04-11 15:12:22,665 INFO L226 Difference]: Without dead ends: 88 [2018-04-11 15:12:22,665 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 10 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2018-04-11 15:12:22,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-04-11 15:12:22,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 82. [2018-04-11 15:12:22,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-04-11 15:12:22,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 90 transitions. [2018-04-11 15:12:22,669 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 90 transitions. Word has length 18 [2018-04-11 15:12:22,669 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:22,670 INFO L459 AbstractCegarLoop]: Abstraction has 82 states and 90 transitions. [2018-04-11 15:12:22,670 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-11 15:12:22,670 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 90 transitions. [2018-04-11 15:12:22,670 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-04-11 15:12:22,670 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:22,670 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:22,670 INFO L408 AbstractCegarLoop]: === Iteration 3 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:22,670 INFO L82 PathProgramCache]: Analyzing trace with hash -2061980982, now seen corresponding path program 1 times [2018-04-11 15:12:22,670 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:22,670 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:22,671 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:22,671 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:22,671 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:22,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:22,682 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:22,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 15:12:22,708 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 15:12:22,708 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-11 15:12:22,708 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-11 15:12:22,709 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-11 15:12:22,709 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-11 15:12:22,709 INFO L87 Difference]: Start difference. First operand 82 states and 90 transitions. Second operand 4 states. [2018-04-11 15:12:22,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:22,749 INFO L93 Difference]: Finished difference Result 80 states and 88 transitions. [2018-04-11 15:12:22,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-11 15:12:22,749 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 19 [2018-04-11 15:12:22,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:22,750 INFO L225 Difference]: With dead ends: 80 [2018-04-11 15:12:22,750 INFO L226 Difference]: Without dead ends: 80 [2018-04-11 15:12:22,750 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-11 15:12:22,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-04-11 15:12:22,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 80. [2018-04-11 15:12:22,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-04-11 15:12:22,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 88 transitions. [2018-04-11 15:12:22,753 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 88 transitions. Word has length 19 [2018-04-11 15:12:22,753 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:22,753 INFO L459 AbstractCegarLoop]: Abstraction has 80 states and 88 transitions. [2018-04-11 15:12:22,753 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-11 15:12:22,753 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 88 transitions. [2018-04-11 15:12:22,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-04-11 15:12:22,754 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:22,754 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:22,754 INFO L408 AbstractCegarLoop]: === Iteration 4 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:22,754 INFO L82 PathProgramCache]: Analyzing trace with hash -2061980981, now seen corresponding path program 1 times [2018-04-11 15:12:22,754 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:22,754 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:22,755 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:22,755 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:22,755 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:22,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:22,766 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:22,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 15:12:22,828 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 15:12:22,828 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-04-11 15:12:22,829 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-11 15:12:22,829 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-11 15:12:22,829 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-04-11 15:12:22,829 INFO L87 Difference]: Start difference. First operand 80 states and 88 transitions. Second operand 8 states. [2018-04-11 15:12:22,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:22,978 INFO L93 Difference]: Finished difference Result 97 states and 108 transitions. [2018-04-11 15:12:22,978 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-11 15:12:22,978 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 19 [2018-04-11 15:12:22,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:22,979 INFO L225 Difference]: With dead ends: 97 [2018-04-11 15:12:22,979 INFO L226 Difference]: Without dead ends: 97 [2018-04-11 15:12:22,979 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=64, Invalid=118, Unknown=0, NotChecked=0, Total=182 [2018-04-11 15:12:22,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-04-11 15:12:22,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 78. [2018-04-11 15:12:22,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-04-11 15:12:22,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 86 transitions. [2018-04-11 15:12:22,982 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 86 transitions. Word has length 19 [2018-04-11 15:12:22,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:22,982 INFO L459 AbstractCegarLoop]: Abstraction has 78 states and 86 transitions. [2018-04-11 15:12:22,982 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-11 15:12:22,982 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 86 transitions. [2018-04-11 15:12:22,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-04-11 15:12:22,982 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:22,982 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:22,982 INFO L408 AbstractCegarLoop]: === Iteration 5 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:22,983 INFO L82 PathProgramCache]: Analyzing trace with hash -1613164609, now seen corresponding path program 1 times [2018-04-11 15:12:22,983 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:22,983 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:22,983 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:22,983 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:22,983 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:22,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:22,993 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:23,059 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 15:12:23,059 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 15:12:23,059 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 15:12:23,060 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:23,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:23,077 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 15:12:23,104 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 15:12:23,104 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-04-11 15:12:23,104 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [9] total 11 [2018-04-11 15:12:23,105 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-11 15:12:23,105 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-11 15:12:23,105 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-04-11 15:12:23,105 INFO L87 Difference]: Start difference. First operand 78 states and 86 transitions. Second operand 11 states. [2018-04-11 15:12:23,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:23,265 INFO L93 Difference]: Finished difference Result 118 states and 126 transitions. [2018-04-11 15:12:23,265 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-11 15:12:23,265 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 23 [2018-04-11 15:12:23,265 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:23,266 INFO L225 Difference]: With dead ends: 118 [2018-04-11 15:12:23,266 INFO L226 Difference]: Without dead ends: 118 [2018-04-11 15:12:23,266 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 21 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=79, Invalid=193, Unknown=0, NotChecked=0, Total=272 [2018-04-11 15:12:23,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-04-11 15:12:23,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 113. [2018-04-11 15:12:23,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-04-11 15:12:23,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 122 transitions. [2018-04-11 15:12:23,271 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 122 transitions. Word has length 23 [2018-04-11 15:12:23,271 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:23,271 INFO L459 AbstractCegarLoop]: Abstraction has 113 states and 122 transitions. [2018-04-11 15:12:23,271 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-11 15:12:23,271 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 122 transitions. [2018-04-11 15:12:23,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-04-11 15:12:23,272 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:23,272 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:23,272 INFO L408 AbstractCegarLoop]: === Iteration 6 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:23,272 INFO L82 PathProgramCache]: Analyzing trace with hash 1093454785, now seen corresponding path program 1 times [2018-04-11 15:12:23,272 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:23,273 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:23,273 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:23,273 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:23,274 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:23,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:23,284 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:23,286 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 15:12:23,286 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 15:12:23,287 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 15:12:23,287 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:23,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:23,312 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 15:12:23,319 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 15:12:23,319 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:23,324 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-11 15:12:23,324 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:23,327 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 15:12:23,327 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-04-11 15:12:23,339 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 15:12:23,339 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 15:12:23,340 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-11 15:12:23,340 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:23,346 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-11 15:12:23,347 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:23,352 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-11 15:12:23,352 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:29, output treesize:22 [2018-04-11 15:12:23,415 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 15:12:23,415 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 15:12:23,415 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-04-11 15:12:23,416 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-11 15:12:23,416 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-11 15:12:23,416 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-04-11 15:12:23,416 INFO L87 Difference]: Start difference. First operand 113 states and 122 transitions. Second operand 8 states. [2018-04-11 15:12:23,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:23,721 INFO L93 Difference]: Finished difference Result 158 states and 174 transitions. [2018-04-11 15:12:23,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-04-11 15:12:23,722 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 23 [2018-04-11 15:12:23,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:23,724 INFO L225 Difference]: With dead ends: 158 [2018-04-11 15:12:23,724 INFO L226 Difference]: Without dead ends: 158 [2018-04-11 15:12:23,725 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 16 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=56, Invalid=100, Unknown=0, NotChecked=0, Total=156 [2018-04-11 15:12:23,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2018-04-11 15:12:23,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 132. [2018-04-11 15:12:23,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-04-11 15:12:23,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 157 transitions. [2018-04-11 15:12:23,732 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 157 transitions. Word has length 23 [2018-04-11 15:12:23,732 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:23,732 INFO L459 AbstractCegarLoop]: Abstraction has 132 states and 157 transitions. [2018-04-11 15:12:23,733 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-11 15:12:23,733 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 157 transitions. [2018-04-11 15:12:23,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-04-11 15:12:23,733 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:23,733 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:23,733 INFO L408 AbstractCegarLoop]: === Iteration 7 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:23,734 INFO L82 PathProgramCache]: Analyzing trace with hash -200886193, now seen corresponding path program 1 times [2018-04-11 15:12:23,734 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:23,734 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:23,734 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:23,734 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:23,734 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:23,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:23,742 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:23,770 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 15:12:23,770 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 15:12:23,770 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 15:12:23,771 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:23,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:23,784 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 15:12:23,796 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 15:12:23,796 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 15:12:23,796 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 8 [2018-04-11 15:12:23,796 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-11 15:12:23,796 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-11 15:12:23,796 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-04-11 15:12:23,797 INFO L87 Difference]: Start difference. First operand 132 states and 157 transitions. Second operand 8 states. [2018-04-11 15:12:23,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:23,889 INFO L93 Difference]: Finished difference Result 215 states and 256 transitions. [2018-04-11 15:12:23,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-11 15:12:23,889 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 28 [2018-04-11 15:12:23,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:23,890 INFO L225 Difference]: With dead ends: 215 [2018-04-11 15:12:23,890 INFO L226 Difference]: Without dead ends: 215 [2018-04-11 15:12:23,890 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=74, Unknown=0, NotChecked=0, Total=110 [2018-04-11 15:12:23,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215 states. [2018-04-11 15:12:23,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215 to 152. [2018-04-11 15:12:23,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152 states. [2018-04-11 15:12:23,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 180 transitions. [2018-04-11 15:12:23,897 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 180 transitions. Word has length 28 [2018-04-11 15:12:23,897 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:23,898 INFO L459 AbstractCegarLoop]: Abstraction has 152 states and 180 transitions. [2018-04-11 15:12:23,898 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-11 15:12:23,898 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 180 transitions. [2018-04-11 15:12:23,898 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-04-11 15:12:23,898 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:23,899 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:23,899 INFO L408 AbstractCegarLoop]: === Iteration 8 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:23,899 INFO L82 PathProgramCache]: Analyzing trace with hash -392535376, now seen corresponding path program 2 times [2018-04-11 15:12:23,899 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:23,899 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:23,899 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:23,900 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:23,900 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:23,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:23,918 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:23,922 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 15:12:23,922 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 15:12:23,922 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 15:12:23,923 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 15:12:23,936 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-04-11 15:12:23,936 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 15:12:23,938 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 15:12:23,945 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 15:12:23,945 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:23,946 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 15:12:23,947 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-11 15:12:23,967 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 15:12:23,968 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 15:12:23,969 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-11 15:12:23,969 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:23,975 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-11 15:12:23,975 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-04-11 15:12:23,993 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 20 [2018-04-11 15:12:23,993 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:23,999 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-11 15:12:23,999 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:21, output treesize:20 [2018-04-11 15:12:24,026 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-11 15:12:24,026 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 15:12:24,026 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-04-11 15:12:24,027 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-04-11 15:12:24,027 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-04-11 15:12:24,027 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-04-11 15:12:24,027 INFO L87 Difference]: Start difference. First operand 152 states and 180 transitions. Second operand 7 states. [2018-04-11 15:12:24,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:24,081 INFO L93 Difference]: Finished difference Result 150 states and 174 transitions. [2018-04-11 15:12:24,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-11 15:12:24,081 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 33 [2018-04-11 15:12:24,081 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:24,082 INFO L225 Difference]: With dead ends: 150 [2018-04-11 15:12:24,082 INFO L226 Difference]: Without dead ends: 150 [2018-04-11 15:12:24,082 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 26 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=64, Unknown=0, NotChecked=0, Total=90 [2018-04-11 15:12:24,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-04-11 15:12:24,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 150. [2018-04-11 15:12:24,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-04-11 15:12:24,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 174 transitions. [2018-04-11 15:12:24,085 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 174 transitions. Word has length 33 [2018-04-11 15:12:24,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:24,086 INFO L459 AbstractCegarLoop]: Abstraction has 150 states and 174 transitions. [2018-04-11 15:12:24,086 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-04-11 15:12:24,086 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 174 transitions. [2018-04-11 15:12:24,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-04-11 15:12:24,086 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:24,086 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:24,086 INFO L408 AbstractCegarLoop]: === Iteration 9 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:24,086 INFO L82 PathProgramCache]: Analyzing trace with hash -392535375, now seen corresponding path program 1 times [2018-04-11 15:12:24,086 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:24,087 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:24,087 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:24,087 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 15:12:24,087 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:24,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:24,097 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:24,101 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 15:12:24,101 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 15:12:24,101 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 15:12:24,101 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:24,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:24,126 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 15:12:24,129 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 15:12:24,129 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:24,135 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-11 15:12:24,135 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:24,139 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 15:12:24,140 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-04-11 15:12:24,171 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 15:12:24,172 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-11 15:12:24,172 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:24,180 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 15:12:24,180 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 15:12:24,181 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-11 15:12:24,181 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:24,185 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-11 15:12:24,185 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:29, output treesize:22 [2018-04-11 15:12:24,204 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 26 [2018-04-11 15:12:24,205 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:24,213 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-11 15:12:24,213 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:30, output treesize:29 [2018-04-11 15:12:24,343 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 15:12:24,344 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 15:12:24,344 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11] total 11 [2018-04-11 15:12:24,344 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-04-11 15:12:24,344 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-04-11 15:12:24,344 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2018-04-11 15:12:24,345 INFO L87 Difference]: Start difference. First operand 150 states and 174 transitions. Second operand 12 states. [2018-04-11 15:12:24,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:24,805 INFO L93 Difference]: Finished difference Result 191 states and 220 transitions. [2018-04-11 15:12:24,805 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-04-11 15:12:24,805 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 33 [2018-04-11 15:12:24,805 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:24,806 INFO L225 Difference]: With dead ends: 191 [2018-04-11 15:12:24,806 INFO L226 Difference]: Without dead ends: 191 [2018-04-11 15:12:24,806 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 21 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=123, Invalid=339, Unknown=0, NotChecked=0, Total=462 [2018-04-11 15:12:24,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191 states. [2018-04-11 15:12:24,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191 to 149. [2018-04-11 15:12:24,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-04-11 15:12:24,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 170 transitions. [2018-04-11 15:12:24,809 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 170 transitions. Word has length 33 [2018-04-11 15:12:24,809 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:24,809 INFO L459 AbstractCegarLoop]: Abstraction has 149 states and 170 transitions. [2018-04-11 15:12:24,810 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-04-11 15:12:24,810 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 170 transitions. [2018-04-11 15:12:24,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-04-11 15:12:24,810 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:24,810 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:24,810 INFO L408 AbstractCegarLoop]: === Iteration 10 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:24,810 INFO L82 PathProgramCache]: Analyzing trace with hash 716305274, now seen corresponding path program 1 times [2018-04-11 15:12:24,811 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:24,811 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:24,812 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:24,812 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:24,812 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:24,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:24,823 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:24,879 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-11 15:12:24,879 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 15:12:24,879 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-04-11 15:12:24,880 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-11 15:12:24,880 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-11 15:12:24,880 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2018-04-11 15:12:24,880 INFO L87 Difference]: Start difference. First operand 149 states and 170 transitions. Second operand 9 states. [2018-04-11 15:12:25,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:25,019 INFO L93 Difference]: Finished difference Result 208 states and 242 transitions. [2018-04-11 15:12:25,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-11 15:12:25,019 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 34 [2018-04-11 15:12:25,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:25,020 INFO L225 Difference]: With dead ends: 208 [2018-04-11 15:12:25,021 INFO L226 Difference]: Without dead ends: 208 [2018-04-11 15:12:25,021 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=52, Invalid=130, Unknown=0, NotChecked=0, Total=182 [2018-04-11 15:12:25,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208 states. [2018-04-11 15:12:25,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 157. [2018-04-11 15:12:25,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-04-11 15:12:25,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 180 transitions. [2018-04-11 15:12:25,025 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 180 transitions. Word has length 34 [2018-04-11 15:12:25,025 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:25,025 INFO L459 AbstractCegarLoop]: Abstraction has 157 states and 180 transitions. [2018-04-11 15:12:25,026 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-11 15:12:25,026 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 180 transitions. [2018-04-11 15:12:25,027 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-04-11 15:12:25,027 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:25,027 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:25,027 INFO L408 AbstractCegarLoop]: === Iteration 11 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:25,027 INFO L82 PathProgramCache]: Analyzing trace with hash 2052905205, now seen corresponding path program 1 times [2018-04-11 15:12:25,027 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:25,027 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:25,028 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:25,028 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:25,028 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:25,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:25,037 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:25,157 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-04-11 15:12:25,157 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 15:12:25,157 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-04-11 15:12:25,158 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-04-11 15:12:25,158 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-04-11 15:12:25,158 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=119, Unknown=0, NotChecked=0, Total=156 [2018-04-11 15:12:25,158 INFO L87 Difference]: Start difference. First operand 157 states and 180 transitions. Second operand 13 states. [2018-04-11 15:12:25,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:25,401 INFO L93 Difference]: Finished difference Result 157 states and 180 transitions. [2018-04-11 15:12:25,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-04-11 15:12:25,406 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 37 [2018-04-11 15:12:25,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:25,407 INFO L225 Difference]: With dead ends: 157 [2018-04-11 15:12:25,407 INFO L226 Difference]: Without dead ends: 157 [2018-04-11 15:12:25,407 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 58 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=151, Invalid=401, Unknown=0, NotChecked=0, Total=552 [2018-04-11 15:12:25,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-04-11 15:12:25,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 125. [2018-04-11 15:12:25,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-04-11 15:12:25,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 136 transitions. [2018-04-11 15:12:25,411 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 136 transitions. Word has length 37 [2018-04-11 15:12:25,411 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:25,411 INFO L459 AbstractCegarLoop]: Abstraction has 125 states and 136 transitions. [2018-04-11 15:12:25,411 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-04-11 15:12:25,412 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 136 transitions. [2018-04-11 15:12:25,412 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-11 15:12:25,412 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:25,413 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:25,413 INFO L408 AbstractCegarLoop]: === Iteration 12 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:25,413 INFO L82 PathProgramCache]: Analyzing trace with hash -784439033, now seen corresponding path program 1 times [2018-04-11 15:12:25,413 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:25,413 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:25,414 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:25,414 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:25,414 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:25,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:25,425 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:25,445 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-11 15:12:25,445 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 15:12:25,445 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-11 15:12:25,446 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-11 15:12:25,446 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-11 15:12:25,446 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-11 15:12:25,446 INFO L87 Difference]: Start difference. First operand 125 states and 136 transitions. Second operand 3 states. [2018-04-11 15:12:25,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:25,452 INFO L93 Difference]: Finished difference Result 126 states and 137 transitions. [2018-04-11 15:12:25,452 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-11 15:12:25,452 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 38 [2018-04-11 15:12:25,452 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:25,453 INFO L225 Difference]: With dead ends: 126 [2018-04-11 15:12:25,453 INFO L226 Difference]: Without dead ends: 126 [2018-04-11 15:12:25,453 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-11 15:12:25,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-04-11 15:12:25,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 126. [2018-04-11 15:12:25,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-04-11 15:12:25,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 137 transitions. [2018-04-11 15:12:25,457 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 137 transitions. Word has length 38 [2018-04-11 15:12:25,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:25,457 INFO L459 AbstractCegarLoop]: Abstraction has 126 states and 137 transitions. [2018-04-11 15:12:25,457 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-11 15:12:25,457 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 137 transitions. [2018-04-11 15:12:25,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-11 15:12:25,458 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:25,458 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:25,458 INFO L408 AbstractCegarLoop]: === Iteration 13 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:25,458 INFO L82 PathProgramCache]: Analyzing trace with hash -784448064, now seen corresponding path program 1 times [2018-04-11 15:12:25,459 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:25,459 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:25,459 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:25,459 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:25,460 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:25,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:25,468 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:25,542 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-11 15:12:25,542 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 15:12:25,542 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-04-11 15:12:25,542 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-11 15:12:25,543 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-11 15:12:25,543 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-04-11 15:12:25,543 INFO L87 Difference]: Start difference. First operand 126 states and 137 transitions. Second operand 11 states. [2018-04-11 15:12:25,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:25,650 INFO L93 Difference]: Finished difference Result 125 states and 136 transitions. [2018-04-11 15:12:25,650 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-04-11 15:12:25,650 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2018-04-11 15:12:25,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:25,650 INFO L225 Difference]: With dead ends: 125 [2018-04-11 15:12:25,650 INFO L226 Difference]: Without dead ends: 125 [2018-04-11 15:12:25,651 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=91, Invalid=251, Unknown=0, NotChecked=0, Total=342 [2018-04-11 15:12:25,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2018-04-11 15:12:25,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 124. [2018-04-11 15:12:25,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-04-11 15:12:25,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 135 transitions. [2018-04-11 15:12:25,654 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 135 transitions. Word has length 38 [2018-04-11 15:12:25,654 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:25,654 INFO L459 AbstractCegarLoop]: Abstraction has 124 states and 135 transitions. [2018-04-11 15:12:25,654 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-11 15:12:25,654 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 135 transitions. [2018-04-11 15:12:25,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-04-11 15:12:25,655 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:25,655 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:25,655 INFO L408 AbstractCegarLoop]: === Iteration 14 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:25,655 INFO L82 PathProgramCache]: Analyzing trace with hash -545854832, now seen corresponding path program 1 times [2018-04-11 15:12:25,655 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:25,655 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:25,656 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:25,656 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:25,656 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:25,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:25,665 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:25,726 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-11 15:12:25,726 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 15:12:25,726 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-04-11 15:12:25,726 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-11 15:12:25,726 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-11 15:12:25,726 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-04-11 15:12:25,727 INFO L87 Difference]: Start difference. First operand 124 states and 135 transitions. Second operand 9 states. [2018-04-11 15:12:25,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:25,794 INFO L93 Difference]: Finished difference Result 143 states and 157 transitions. [2018-04-11 15:12:25,794 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-11 15:12:25,794 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 42 [2018-04-11 15:12:25,794 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:25,795 INFO L225 Difference]: With dead ends: 143 [2018-04-11 15:12:25,795 INFO L226 Difference]: Without dead ends: 143 [2018-04-11 15:12:25,795 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2018-04-11 15:12:25,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-04-11 15:12:25,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 142. [2018-04-11 15:12:25,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-04-11 15:12:25,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 156 transitions. [2018-04-11 15:12:25,797 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 156 transitions. Word has length 42 [2018-04-11 15:12:25,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:25,797 INFO L459 AbstractCegarLoop]: Abstraction has 142 states and 156 transitions. [2018-04-11 15:12:25,797 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-11 15:12:25,797 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 156 transitions. [2018-04-11 15:12:25,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-04-11 15:12:25,798 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:25,798 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:25,798 INFO L408 AbstractCegarLoop]: === Iteration 15 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:25,798 INFO L82 PathProgramCache]: Analyzing trace with hash -192166533, now seen corresponding path program 1 times [2018-04-11 15:12:25,798 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:25,798 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:25,798 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:25,798 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:25,799 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:25,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:25,811 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:25,819 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 15:12:25,819 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 15:12:25,819 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 15:12:25,819 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:25,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:25,844 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 15:12:25,867 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 15:12:25,867 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:25,871 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 15:12:25,872 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:13, output treesize:12 [2018-04-11 15:12:25,889 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 15:12:25,890 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 15:12:25,891 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-11 15:12:25,891 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:25,895 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 15:12:25,895 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:11 [2018-04-11 15:12:25,920 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-04-11 15:12:25,922 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-04-11 15:12:25,922 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:25,924 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 15:12:25,931 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 15:12:25,932 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:36, output treesize:32 [2018-04-11 15:12:25,956 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 28 [2018-04-11 15:12:25,958 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-04-11 15:12:25,958 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:25,961 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 15:12:25,967 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-11 15:12:25,967 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:47, output treesize:43 [2018-04-11 15:12:26,025 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 32 [2018-04-11 15:12:26,028 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 1 [2018-04-11 15:12:26,028 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:26,033 INFO L682 Elim1Store]: detected equality via solver [2018-04-11 15:12:26,034 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 15 [2018-04-11 15:12:26,034 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-11 15:12:26,036 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 15:12:26,043 INFO L267 ElimStorePlain]: Start of recursive call 1: 6 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 15:12:26,043 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 7 variables, input treesize:64, output treesize:7 [2018-04-11 15:12:26,057 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 15:12:26,057 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 15:12:26,057 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11] total 11 [2018-04-11 15:12:26,057 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-11 15:12:26,058 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-11 15:12:26,058 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=81, Unknown=0, NotChecked=0, Total=110 [2018-04-11 15:12:26,058 INFO L87 Difference]: Start difference. First operand 142 states and 156 transitions. Second operand 11 states. [2018-04-11 15:12:26,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:26,288 INFO L93 Difference]: Finished difference Result 158 states and 172 transitions. [2018-04-11 15:12:26,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-04-11 15:12:26,288 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 44 [2018-04-11 15:12:26,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:26,290 INFO L225 Difference]: With dead ends: 158 [2018-04-11 15:12:26,290 INFO L226 Difference]: Without dead ends: 158 [2018-04-11 15:12:26,290 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 34 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=110, Invalid=232, Unknown=0, NotChecked=0, Total=342 [2018-04-11 15:12:26,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2018-04-11 15:12:26,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 142. [2018-04-11 15:12:26,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-04-11 15:12:26,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 154 transitions. [2018-04-11 15:12:26,294 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 154 transitions. Word has length 44 [2018-04-11 15:12:26,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:26,294 INFO L459 AbstractCegarLoop]: Abstraction has 142 states and 154 transitions. [2018-04-11 15:12:26,294 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-11 15:12:26,294 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 154 transitions. [2018-04-11 15:12:26,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-04-11 15:12:26,295 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:26,295 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:26,295 INFO L408 AbstractCegarLoop]: === Iteration 16 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:26,295 INFO L82 PathProgramCache]: Analyzing trace with hash 2143854456, now seen corresponding path program 1 times [2018-04-11 15:12:26,295 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:26,295 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:26,296 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:26,296 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:26,296 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:26,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:26,306 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:26,309 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 15:12:26,309 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 15:12:26,309 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 15:12:26,309 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:26,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:26,328 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 15:12:26,360 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base| Int)) (let ((.cse0 (store |c_old(#valid)| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base| 1))) (and (= 0 (select |c_old(#valid)| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base|)) (= (store (store .cse0 |c___U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base| 1) |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base| 0) |c_#valid|) (= (select .cse0 |c___U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base|) 0)))) is different from true [2018-04-11 15:12:26,363 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base| Int) (|__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base| Int)) (let ((.cse0 (store |c_old(#valid)| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base| 1))) (and (= 0 (select |c_old(#valid)| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base|)) (= |c_#valid| (store (store (store .cse0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base| 1) |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base| 0) |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base| 0)) (= (select .cse0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base|) 0)))) is different from true [2018-04-11 15:12:26,379 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc17.base| Int) (|__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base| Int) (|__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base| Int)) (let ((.cse0 (store |c_old(#valid)| |main_#t~malloc17.base| 1))) (let ((.cse1 (store .cse0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base| 1))) (and (= 0 (select .cse0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base|)) (= (select .cse1 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base|) 0) (= |c_#valid| (store (store (store (store .cse1 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base| 1) |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base| 0) |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base| 0) |main_#t~malloc17.base| 0)) (= (select |c_old(#valid)| |main_#t~malloc17.base|) 0))))) is different from true [2018-04-11 15:12:26,384 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-11 15:12:26,385 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 15:12:26,385 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-04-11 15:12:26,385 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-11 15:12:26,385 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-11 15:12:26,385 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=33, Unknown=3, NotChecked=36, Total=90 [2018-04-11 15:12:26,385 INFO L87 Difference]: Start difference. First operand 142 states and 154 transitions. Second operand 10 states. [2018-04-11 15:12:26,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:26,456 INFO L93 Difference]: Finished difference Result 141 states and 153 transitions. [2018-04-11 15:12:26,456 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-11 15:12:26,456 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 46 [2018-04-11 15:12:26,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:26,457 INFO L225 Difference]: With dead ends: 141 [2018-04-11 15:12:26,457 INFO L226 Difference]: Without dead ends: 72 [2018-04-11 15:12:26,457 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=43, Unknown=4, NotChecked=42, Total=110 [2018-04-11 15:12:26,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-04-11 15:12:26,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 72. [2018-04-11 15:12:26,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-04-11 15:12:26,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 80 transitions. [2018-04-11 15:12:26,458 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 80 transitions. Word has length 46 [2018-04-11 15:12:26,458 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:26,459 INFO L459 AbstractCegarLoop]: Abstraction has 72 states and 80 transitions. [2018-04-11 15:12:26,459 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-11 15:12:26,459 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 80 transitions. [2018-04-11 15:12:26,459 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-04-11 15:12:26,459 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:26,459 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:26,459 INFO L408 AbstractCegarLoop]: === Iteration 17 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:26,459 INFO L82 PathProgramCache]: Analyzing trace with hash -1439353826, now seen corresponding path program 1 times [2018-04-11 15:12:26,459 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:26,459 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:26,460 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:26,460 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:26,460 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:26,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:26,465 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:26,525 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 6 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-11 15:12:26,525 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 15:12:26,525 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 15:12:26,526 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:26,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:26,533 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 15:12:26,550 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-04-11 15:12:26,551 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-04-11 15:12:26,551 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [11] total 13 [2018-04-11 15:12:26,551 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-04-11 15:12:26,551 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-04-11 15:12:26,551 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2018-04-11 15:12:26,551 INFO L87 Difference]: Start difference. First operand 72 states and 80 transitions. Second operand 13 states. [2018-04-11 15:12:26,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:26,709 INFO L93 Difference]: Finished difference Result 88 states and 96 transitions. [2018-04-11 15:12:26,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-04-11 15:12:26,709 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 47 [2018-04-11 15:12:26,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:26,709 INFO L225 Difference]: With dead ends: 88 [2018-04-11 15:12:26,709 INFO L226 Difference]: Without dead ends: 88 [2018-04-11 15:12:26,710 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 45 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=124, Invalid=428, Unknown=0, NotChecked=0, Total=552 [2018-04-11 15:12:26,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-04-11 15:12:26,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 72. [2018-04-11 15:12:26,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-04-11 15:12:26,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 78 transitions. [2018-04-11 15:12:26,711 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 78 transitions. Word has length 47 [2018-04-11 15:12:26,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:26,711 INFO L459 AbstractCegarLoop]: Abstraction has 72 states and 78 transitions. [2018-04-11 15:12:26,711 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-04-11 15:12:26,712 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 78 transitions. [2018-04-11 15:12:26,712 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-04-11 15:12:26,712 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 15:12:26,712 INFO L355 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 15:12:26,712 INFO L408 AbstractCegarLoop]: === Iteration 18 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-11 15:12:26,712 INFO L82 PathProgramCache]: Analyzing trace with hash 982053064, now seen corresponding path program 2 times [2018-04-11 15:12:26,713 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 15:12:26,713 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 15:12:26,713 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:26,713 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 15:12:26,713 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 15:12:26,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 15:12:26,732 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 15:12:26,814 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 4 proven. 25 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-11 15:12:26,815 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 15:12:26,815 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 15:12:26,815 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 15:12:26,835 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 15:12:26,835 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 15:12:26,837 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 15:12:26,908 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-04-11 15:12:26,908 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-04-11 15:12:26,908 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [12] total 20 [2018-04-11 15:12:26,909 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-04-11 15:12:26,909 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-04-11 15:12:26,909 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=314, Unknown=0, NotChecked=0, Total=380 [2018-04-11 15:12:26,909 INFO L87 Difference]: Start difference. First operand 72 states and 78 transitions. Second operand 20 states. [2018-04-11 15:12:27,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 15:12:27,392 INFO L93 Difference]: Finished difference Result 171 states and 189 transitions. [2018-04-11 15:12:27,392 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-04-11 15:12:27,392 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 55 [2018-04-11 15:12:27,393 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 15:12:27,393 INFO L225 Difference]: With dead ends: 171 [2018-04-11 15:12:27,393 INFO L226 Difference]: Without dead ends: 0 [2018-04-11 15:12:27,393 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 90 GetRequests, 48 SyntacticMatches, 1 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 357 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=393, Invalid=1413, Unknown=0, NotChecked=0, Total=1806 [2018-04-11 15:12:27,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2018-04-11 15:12:27,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2018-04-11 15:12:27,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 0 states. [2018-04-11 15:12:27,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2018-04-11 15:12:27,394 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 55 [2018-04-11 15:12:27,394 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 15:12:27,394 INFO L459 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2018-04-11 15:12:27,394 INFO L460 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-04-11 15:12:27,394 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2018-04-11 15:12:27,394 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-04-11 15:12:27,396 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 11.04 03:12:27 BoogieIcfgContainer [2018-04-11 15:12:27,397 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-04-11 15:12:27,397 INFO L168 Benchmark]: Toolchain (without parser) took 6436.36 ms. Allocated memory was 404.2 MB in the beginning and 684.7 MB in the end (delta: 280.5 MB). Free memory was 338.5 MB in the beginning and 452.3 MB in the end (delta: -113.8 MB). Peak memory consumption was 166.7 MB. Max. memory is 5.3 GB. [2018-04-11 15:12:27,398 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 404.2 MB. Free memory is still 364.2 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-04-11 15:12:27,398 INFO L168 Benchmark]: CACSL2BoogieTranslator took 245.13 ms. Allocated memory is still 404.2 MB. Free memory was 337.2 MB in the beginning and 312.8 MB in the end (delta: 24.3 MB). Peak memory consumption was 24.3 MB. Max. memory is 5.3 GB. [2018-04-11 15:12:27,398 INFO L168 Benchmark]: Boogie Preprocessor took 44.46 ms. Allocated memory is still 404.2 MB. Free memory was 312.8 MB in the beginning and 310.2 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. [2018-04-11 15:12:27,398 INFO L168 Benchmark]: RCFGBuilder took 410.27 ms. Allocated memory was 404.2 MB in the beginning and 593.5 MB in the end (delta: 189.3 MB). Free memory was 310.2 MB in the beginning and 522.4 MB in the end (delta: -212.2 MB). Peak memory consumption was 24.6 MB. Max. memory is 5.3 GB. [2018-04-11 15:12:27,398 INFO L168 Benchmark]: TraceAbstraction took 5733.20 ms. Allocated memory was 593.5 MB in the beginning and 684.7 MB in the end (delta: 91.2 MB). Free memory was 522.4 MB in the beginning and 452.3 MB in the end (delta: 70.1 MB). Peak memory consumption was 161.4 MB. Max. memory is 5.3 GB. [2018-04-11 15:12:27,399 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 404.2 MB. Free memory is still 364.2 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 245.13 ms. Allocated memory is still 404.2 MB. Free memory was 337.2 MB in the beginning and 312.8 MB in the end (delta: 24.3 MB). Peak memory consumption was 24.3 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 44.46 ms. Allocated memory is still 404.2 MB. Free memory was 312.8 MB in the beginning and 310.2 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 410.27 ms. Allocated memory was 404.2 MB in the beginning and 593.5 MB in the end (delta: 189.3 MB). Free memory was 310.2 MB in the beginning and 522.4 MB in the end (delta: -212.2 MB). Peak memory consumption was 24.6 MB. Max. memory is 5.3 GB. * TraceAbstraction took 5733.20 ms. Allocated memory was 593.5 MB in the beginning and 684.7 MB in the end (delta: 91.2 MB). Free memory was 522.4 MB in the beginning and 452.3 MB in the end (delta: 70.1 MB). Peak memory consumption was 161.4 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - PositiveResult [Line: 556]: all allocated memory was freed For all program executions holds that all allocated memory was freed at this location - PositiveResult [Line: 546]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 553]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 546]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 552]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 546]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 546]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 552]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 553]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - AllSpecificationsHoldResult: All specifications hold 23 specifications checked. All of them hold - StatisticsResult: Ultimate Automizer benchmark data CFG has 6 procedures, 90 locations, 23 error locations. SAFE Result, 5.6s OverallTime, 18 OverallIterations, 4 TraceHistogramMax, 3.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 958 SDtfs, 3570 SDslu, 3027 SDs, 0 SdLazy, 2552 SolverSat, 297 SolverUnsat, 1 SolverUnknown, 0 SolverNotchecked, 1.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 564 GetRequests, 308 SyntacticMatches, 7 SemanticMatches, 249 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 652 ImplicationChecksByTransitivity, 2.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=157occurred in iteration=10, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 18 MinimizatonAttempts, 278 StatesRemovedByMinimization, 12 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.7s InterpolantComputationTime, 963 NumberOfCodeBlocks, 953 NumberOfCodeBlocksAsserted, 30 NumberOfCheckSat, 726 ConstructedInterpolants, 79 QuantifiedInterpolants, 198636 SizeOfPredicates, 52 NumberOfNonLiveVariables, 1361 ConjunctsInSsa, 144 ConjunctsInUnsatCore, 22 InterpolantComputations, 14 PerfectInterpolantSequences, 145/192 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be correct! Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/lis-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf_AutomizerC.xml/Csv-Benchmark-0-2018-04-11_15-12-27-406.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/lis-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-04-11_15-12-27-406.csv Received shutdown request...