java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv --cacsl2boogietranslator.bitprecise.bitfields false -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf -i ../../../trunk/examples/svcomp/list-ext-properties/960521-1_1_true-valid-memsafety.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-408c70d-m [2018-04-12 14:24:42,899 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-04-12 14:24:42,901 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-04-12 14:24:42,912 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-04-12 14:24:42,912 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-04-12 14:24:42,913 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-04-12 14:24:42,914 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-04-12 14:24:42,915 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-04-12 14:24:42,917 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-04-12 14:24:42,918 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-04-12 14:24:42,918 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-04-12 14:24:42,919 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-04-12 14:24:42,919 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-04-12 14:24:42,920 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-04-12 14:24:42,921 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-04-12 14:24:42,923 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-04-12 14:24:42,924 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-04-12 14:24:42,926 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-04-12 14:24:42,927 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-04-12 14:24:42,927 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-04-12 14:24:42,929 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-04-12 14:24:42,929 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-04-12 14:24:42,929 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-04-12 14:24:42,930 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-04-12 14:24:42,931 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-04-12 14:24:42,932 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-04-12 14:24:42,932 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-04-12 14:24:42,932 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-04-12 14:24:42,933 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-04-12 14:24:42,933 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-04-12 14:24:42,934 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-04-12 14:24:42,934 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf [2018-04-12 14:24:42,943 INFO L110 SettingsManager]: Loading preferences was successful [2018-04-12 14:24:42,943 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-04-12 14:24:42,944 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-04-12 14:24:42,944 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-04-12 14:24:42,944 INFO L133 SettingsManager]: * Use SBE=true [2018-04-12 14:24:42,944 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-04-12 14:24:42,945 INFO L133 SettingsManager]: * sizeof long=4 [2018-04-12 14:24:42,945 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-04-12 14:24:42,945 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-04-12 14:24:42,945 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-04-12 14:24:42,945 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-04-12 14:24:42,945 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-04-12 14:24:42,945 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-04-12 14:24:42,945 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-04-12 14:24:42,946 INFO L133 SettingsManager]: * sizeof long double=12 [2018-04-12 14:24:42,946 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-04-12 14:24:42,946 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-04-12 14:24:42,946 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-04-12 14:24:42,946 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-04-12 14:24:42,946 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-12 14:24:42,946 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-04-12 14:24:42,947 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-04-12 14:24:42,947 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-04-12 14:24:42,947 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Bitprecise bitfields -> false [2018-04-12 14:24:42,974 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-04-12 14:24:42,984 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully (re)initialized [2018-04-12 14:24:42,987 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-04-12 14:24:42,988 INFO L271 PluginConnector]: Initializing CDTParser... [2018-04-12 14:24:42,988 INFO L276 PluginConnector]: CDTParser initialized [2018-04-12 14:24:42,989 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/list-ext-properties/960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,342 INFO L225 CDTParser]: Created temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAG4b8cc7334 [2018-04-12 14:24:43,468 INFO L287 CDTParser]: IsIndexed: true [2018-04-12 14:24:43,468 INFO L288 CDTParser]: Found 1 translation units. [2018-04-12 14:24:43,468 INFO L168 CDTParser]: Scanning 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,477 INFO L210 ultiparseSymbolTable]: Include resolver: [2018-04-12 14:24:43,478 INFO L215 ultiparseSymbolTable]: [2018-04-12 14:24:43,478 INFO L218 ultiparseSymbolTable]: Function table: [2018-04-12 14:24:43,478 INFO L221 ultiparseSymbolTable]: Function definition of null ('main') in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,478 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_f___________true_valid_memsafety_i__foo ('foo') in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,478 INFO L227 ultiparseSymbolTable]: Global variable table: [2018-04-12 14:24:43,478 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____uint8_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,478 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____daddr_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,478 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____key_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,479 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_int8_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,479 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____u_int in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,479 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__loff_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,479 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__quad_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,479 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____clockid_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,479 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__clockid_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,479 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____blkcnt_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,479 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____fd_mask in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,479 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__fsid_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,479 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__int64_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,480 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,480 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_int16_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,480 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_cond_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,480 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_spinlock_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,480 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__id_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,480 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____clock_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,480 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____WAIT_STATUS in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,480 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__dev_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,480 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_condattr_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,481 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_attr_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,481 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____u_quad_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,481 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____pid_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,481 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__ushort in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,481 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____quad_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,481 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____fsblkcnt64_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,481 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__wchar_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,481 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__register_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,481 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____int64_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,481 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____useconds_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,482 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____swblk_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,482 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_barrier_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,482 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____nlink_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,482 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__timer_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,482 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_int32_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,482 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__sigset_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,482 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____gid_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,482 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____sig_atomic_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,482 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____uid_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,482 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__key_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,482 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____ssize_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,482 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____ino64_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,482 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__int32_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,483 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__nlink_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,483 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__uint in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,483 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____uint64_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,483 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__ssize_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,483 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_rwlockattr_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,483 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____off_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,483 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____blkcnt64_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,483 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__fd_mask in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,483 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__fsfilcnt_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,483 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____suseconds_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,483 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__time_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,483 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____rlim64_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,484 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__caddr_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,484 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____id_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,484 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_rwlock_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,484 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____qaddr_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,484 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_int in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,484 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____blksize_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,484 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__blksize_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,484 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____int32_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,484 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__div_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,484 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____uint32_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,484 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__fsblkcnt_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,484 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____timer_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,485 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____off64_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,485 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____time_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,485 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____intptr_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,485 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_mutexattr_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,485 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_quad_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,485 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__size_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,485 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____fsfilcnt_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,485 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__n in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,485 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____u_char in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,485 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__int16_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,485 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____fsblkcnt_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,486 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__int8_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,486 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_key_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,486 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__lldiv_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,486 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____rlim_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,486 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____socklen_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,486 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__uid_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,486 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____pthread_list_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,486 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_barrierattr_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,486 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__b in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,486 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__a in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,486 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__ldiv_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,486 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____fsfilcnt64_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_mutex_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__ino_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_short in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__off_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__gid_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____int8_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_char in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__blkcnt_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_int64_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____uint16_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__daddr_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____mode_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_once_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____u_long in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____int16_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____caddr_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,487 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____ino_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,488 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____dev_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,488 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____loff_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,488 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____sigset_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,488 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__fd_set in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,488 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____u_short in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,488 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____fsid_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,488 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__clock_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,488 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__suseconds_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,488 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__mode_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,488 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__ulong in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,488 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_long in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,488 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pid_t in 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:43,536 INFO L330 CDTParser]: Deleted temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAG4b8cc7334 [2018-04-12 14:24:43,539 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-04-12 14:24:43,540 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-04-12 14:24:43,540 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-04-12 14:24:43,540 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-04-12 14:24:43,544 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-04-12 14:24:43,544 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.04 02:24:43" (1/1) ... [2018-04-12 14:24:43,546 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@67cf35de and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 02:24:43, skipping insertion in model container [2018-04-12 14:24:43,546 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.04 02:24:43" (1/1) ... [2018-04-12 14:24:43,557 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-12 14:24:43,578 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-12 14:24:43,695 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-12 14:24:43,725 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-12 14:24:43,731 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-12 14:24:43,756 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 02:24:43 WrapperNode [2018-04-12 14:24:43,756 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-04-12 14:24:43,757 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-04-12 14:24:43,757 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-04-12 14:24:43,757 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-04-12 14:24:43,764 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 02:24:43" (1/1) ... [2018-04-12 14:24:43,764 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 02:24:43" (1/1) ... [2018-04-12 14:24:43,774 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 02:24:43" (1/1) ... [2018-04-12 14:24:43,774 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 02:24:43" (1/1) ... [2018-04-12 14:24:43,782 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 02:24:43" (1/1) ... [2018-04-12 14:24:43,786 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 02:24:43" (1/1) ... [2018-04-12 14:24:43,788 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 02:24:43" (1/1) ... [2018-04-12 14:24:43,791 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-04-12 14:24:43,792 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-04-12 14:24:43,792 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-04-12 14:24:43,792 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-04-12 14:24:43,793 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 02:24:43" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-12 14:24:43,873 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-04-12 14:24:43,873 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-04-12 14:24:43,873 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f___________true_valid_memsafety_i__foo [2018-04-12 14:24:43,873 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-04-12 14:24:43,873 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure __ctype_get_mb_cur_max [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure atof [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure atoi [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure atol [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure atoll [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure strtod [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure strtof [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure strtold [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure strtol [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure strtoul [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure strtoq [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure strtouq [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure strtoll [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure strtoull [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure l64a [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure a64l [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure select [2018-04-12 14:24:43,875 INFO L128 BoogieDeclarations]: Found specification of procedure pselect [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_major [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_minor [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_makedev [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure random [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure srandom [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure initstate [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure setstate [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure random_r [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure srandom_r [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure initstate_r [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure setstate_r [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure rand [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure srand [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure rand_r [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure drand48 [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure erand48 [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48 [2018-04-12 14:24:43,876 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48 [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48 [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48 [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure srand48 [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure seed48 [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48 [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure drand48_r [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure erand48_r [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48_r [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48_r [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48_r [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48_r [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure srand48_r [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure seed48_r [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48_r [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure realloc [2018-04-12 14:24:43,877 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure cfree [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure alloca [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure valloc [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure posix_memalign [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure abort [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure atexit [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure on_exit [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure exit [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure _Exit [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure getenv [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure __secure_getenv [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure putenv [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure setenv [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure unsetenv [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure clearenv [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure mktemp [2018-04-12 14:24:43,878 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemp [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemps [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure mkdtemp [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure system [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure realpath [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure bsearch [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure qsort [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure abs [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure labs [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure llabs [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure div [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure ldiv [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure lldiv [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure gcvt [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt [2018-04-12 14:24:43,879 INFO L128 BoogieDeclarations]: Found specification of procedure qgcvt [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt_r [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt_r [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt_r [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt_r [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure mblen [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure mbtowc [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure wctomb [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure mbstowcs [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure wcstombs [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure rpmatch [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure getsubopt [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure getloadavg [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_f___________true_valid_memsafety_i__foo [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-04-12 14:24:43,880 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-04-12 14:24:43,881 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-04-12 14:24:43,881 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-04-12 14:24:43,881 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-04-12 14:24:43,881 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-04-12 14:24:43,881 INFO L128 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-04-12 14:24:44,161 INFO L259 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-04-12 14:24:44,162 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.04 02:24:44 BoogieIcfgContainer [2018-04-12 14:24:44,162 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-04-12 14:24:44,162 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-04-12 14:24:44,162 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-04-12 14:24:44,164 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-04-12 14:24:44,164 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 12.04 02:24:43" (1/3) ... [2018-04-12 14:24:44,164 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6a3baeb6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.04 02:24:44, skipping insertion in model container [2018-04-12 14:24:44,164 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 02:24:43" (2/3) ... [2018-04-12 14:24:44,165 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6a3baeb6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.04 02:24:44, skipping insertion in model container [2018-04-12 14:24:44,165 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.04 02:24:44" (3/3) ... [2018-04-12 14:24:44,165 INFO L107 eAbstractionObserver]: Analyzing ICFG 960521-1_1_true-valid-memsafety.i [2018-04-12 14:24:44,170 INFO L131 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-04-12 14:24:44,174 INFO L143 ceAbstractionStarter]: Appying trace abstraction to program that has 19 error locations. [2018-04-12 14:24:44,200 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-04-12 14:24:44,201 INFO L369 AbstractCegarLoop]: Interprodecural is true [2018-04-12 14:24:44,201 INFO L370 AbstractCegarLoop]: Hoare is false [2018-04-12 14:24:44,201 INFO L371 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-04-12 14:24:44,201 INFO L372 AbstractCegarLoop]: Backedges is TWOTRACK [2018-04-12 14:24:44,201 INFO L373 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-04-12 14:24:44,201 INFO L374 AbstractCegarLoop]: Difference is false [2018-04-12 14:24:44,201 INFO L375 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-04-12 14:24:44,201 INFO L380 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-04-12 14:24:44,202 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-04-12 14:24:44,210 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states. [2018-04-12 14:24:44,215 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-04-12 14:24:44,215 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:44,216 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:44,216 INFO L408 AbstractCegarLoop]: === Iteration 1 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:44,218 INFO L82 PathProgramCache]: Analyzing trace with hash 284919364, now seen corresponding path program 1 times [2018-04-12 14:24:44,219 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:44,219 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:44,252 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:44,252 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:44,252 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:44,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:44,286 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:44,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:44,308 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 14:24:44,308 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-04-12 14:24:44,309 INFO L442 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-04-12 14:24:44,316 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-04-12 14:24:44,317 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-04-12 14:24:44,318 INFO L87 Difference]: Start difference. First operand 67 states. Second operand 2 states. [2018-04-12 14:24:44,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:44,329 INFO L93 Difference]: Finished difference Result 67 states and 70 transitions. [2018-04-12 14:24:44,329 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-04-12 14:24:44,330 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 12 [2018-04-12 14:24:44,331 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:44,338 INFO L225 Difference]: With dead ends: 67 [2018-04-12 14:24:44,338 INFO L226 Difference]: Without dead ends: 64 [2018-04-12 14:24:44,339 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-04-12 14:24:44,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-04-12 14:24:44,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 64. [2018-04-12 14:24:44,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-04-12 14:24:44,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 67 transitions. [2018-04-12 14:24:44,365 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 67 transitions. Word has length 12 [2018-04-12 14:24:44,365 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:44,365 INFO L459 AbstractCegarLoop]: Abstraction has 64 states and 67 transitions. [2018-04-12 14:24:44,365 INFO L460 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-04-12 14:24:44,365 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 67 transitions. [2018-04-12 14:24:44,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-04-12 14:24:44,365 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:44,365 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:44,365 INFO L408 AbstractCegarLoop]: === Iteration 2 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:44,366 INFO L82 PathProgramCache]: Analyzing trace with hash 824267754, now seen corresponding path program 1 times [2018-04-12 14:24:44,366 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:44,366 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:44,366 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:44,366 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:44,366 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:44,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:44,382 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:44,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:44,415 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 14:24:44,415 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-12 14:24:44,415 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-12 14:24:44,416 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-12 14:24:44,416 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-12 14:24:44,416 INFO L87 Difference]: Start difference. First operand 64 states and 67 transitions. Second operand 4 states. [2018-04-12 14:24:44,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:44,493 INFO L93 Difference]: Finished difference Result 63 states and 66 transitions. [2018-04-12 14:24:44,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-12 14:24:44,494 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 14 [2018-04-12 14:24:44,494 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:44,494 INFO L225 Difference]: With dead ends: 63 [2018-04-12 14:24:44,494 INFO L226 Difference]: Without dead ends: 63 [2018-04-12 14:24:44,495 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-12 14:24:44,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-04-12 14:24:44,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2018-04-12 14:24:44,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-04-12 14:24:44,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 66 transitions. [2018-04-12 14:24:44,498 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 66 transitions. Word has length 14 [2018-04-12 14:24:44,498 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:44,498 INFO L459 AbstractCegarLoop]: Abstraction has 63 states and 66 transitions. [2018-04-12 14:24:44,498 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-12 14:24:44,498 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 66 transitions. [2018-04-12 14:24:44,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-04-12 14:24:44,498 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:44,498 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:44,498 INFO L408 AbstractCegarLoop]: === Iteration 3 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:44,499 INFO L82 PathProgramCache]: Analyzing trace with hash 824267755, now seen corresponding path program 1 times [2018-04-12 14:24:44,499 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:44,499 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:44,499 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:44,499 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:44,499 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:44,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:44,511 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:44,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:44,557 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 14:24:44,557 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-12 14:24:44,557 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-12 14:24:44,557 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-12 14:24:44,557 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-04-12 14:24:44,557 INFO L87 Difference]: Start difference. First operand 63 states and 66 transitions. Second operand 5 states. [2018-04-12 14:24:44,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:44,608 INFO L93 Difference]: Finished difference Result 62 states and 65 transitions. [2018-04-12 14:24:44,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-12 14:24:44,609 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 14 [2018-04-12 14:24:44,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:44,609 INFO L225 Difference]: With dead ends: 62 [2018-04-12 14:24:44,609 INFO L226 Difference]: Without dead ends: 62 [2018-04-12 14:24:44,610 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-04-12 14:24:44,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-04-12 14:24:44,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 62. [2018-04-12 14:24:44,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2018-04-12 14:24:44,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 65 transitions. [2018-04-12 14:24:44,615 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 65 transitions. Word has length 14 [2018-04-12 14:24:44,615 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:44,615 INFO L459 AbstractCegarLoop]: Abstraction has 62 states and 65 transitions. [2018-04-12 14:24:44,616 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-12 14:24:44,616 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 65 transitions. [2018-04-12 14:24:44,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-04-12 14:24:44,616 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:44,616 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:44,616 INFO L408 AbstractCegarLoop]: === Iteration 4 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:44,617 INFO L82 PathProgramCache]: Analyzing trace with hash 1288303895, now seen corresponding path program 1 times [2018-04-12 14:24:44,617 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:44,617 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:44,617 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:44,617 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:44,618 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:44,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:44,631 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:44,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:44,679 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 14:24:44,679 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-12 14:24:44,680 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-12 14:24:44,680 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-12 14:24:44,680 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-04-12 14:24:44,681 INFO L87 Difference]: Start difference. First operand 62 states and 65 transitions. Second operand 6 states. [2018-04-12 14:24:44,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:44,742 INFO L93 Difference]: Finished difference Result 59 states and 62 transitions. [2018-04-12 14:24:44,742 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-12 14:24:44,742 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 20 [2018-04-12 14:24:44,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:44,743 INFO L225 Difference]: With dead ends: 59 [2018-04-12 14:24:44,743 INFO L226 Difference]: Without dead ends: 59 [2018-04-12 14:24:44,743 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-04-12 14:24:44,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-04-12 14:24:44,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2018-04-12 14:24:44,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states. [2018-04-12 14:24:44,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 62 transitions. [2018-04-12 14:24:44,747 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 62 transitions. Word has length 20 [2018-04-12 14:24:44,747 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:44,747 INFO L459 AbstractCegarLoop]: Abstraction has 59 states and 62 transitions. [2018-04-12 14:24:44,747 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-12 14:24:44,747 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 62 transitions. [2018-04-12 14:24:44,748 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-04-12 14:24:44,748 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:44,748 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:44,748 INFO L408 AbstractCegarLoop]: === Iteration 5 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:44,748 INFO L82 PathProgramCache]: Analyzing trace with hash 1288303896, now seen corresponding path program 1 times [2018-04-12 14:24:44,748 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:44,749 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:44,749 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:44,749 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:44,749 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:44,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:44,761 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:44,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:44,828 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 14:24:44,828 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-04-12 14:24:44,828 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-04-12 14:24:44,828 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-04-12 14:24:44,828 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-04-12 14:24:44,828 INFO L87 Difference]: Start difference. First operand 59 states and 62 transitions. Second operand 7 states. [2018-04-12 14:24:44,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:44,913 INFO L93 Difference]: Finished difference Result 69 states and 73 transitions. [2018-04-12 14:24:44,913 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-12 14:24:44,913 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 20 [2018-04-12 14:24:44,914 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:44,915 INFO L225 Difference]: With dead ends: 69 [2018-04-12 14:24:44,915 INFO L226 Difference]: Without dead ends: 69 [2018-04-12 14:24:44,915 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-04-12 14:24:44,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2018-04-12 14:24:44,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 60. [2018-04-12 14:24:44,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-04-12 14:24:44,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 63 transitions. [2018-04-12 14:24:44,918 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 63 transitions. Word has length 20 [2018-04-12 14:24:44,918 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:44,918 INFO L459 AbstractCegarLoop]: Abstraction has 60 states and 63 transitions. [2018-04-12 14:24:44,918 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-04-12 14:24:44,918 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 63 transitions. [2018-04-12 14:24:44,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-04-12 14:24:44,918 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:44,918 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:44,919 INFO L408 AbstractCegarLoop]: === Iteration 6 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:44,919 INFO L82 PathProgramCache]: Analyzing trace with hash 1040443247, now seen corresponding path program 1 times [2018-04-12 14:24:44,919 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:44,919 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:44,919 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:44,919 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:44,919 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:44,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:44,929 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:44,974 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:44,974 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:24:44,974 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:24:44,984 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:45,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:45,013 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:24:45,063 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:45,081 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-04-12 14:24:45,081 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 9 [2018-04-12 14:24:45,081 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-12 14:24:45,081 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-12 14:24:45,081 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-04-12 14:24:45,082 INFO L87 Difference]: Start difference. First operand 60 states and 63 transitions. Second operand 9 states. [2018-04-12 14:24:45,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:45,209 INFO L93 Difference]: Finished difference Result 108 states and 112 transitions. [2018-04-12 14:24:45,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-12 14:24:45,210 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 24 [2018-04-12 14:24:45,210 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:45,210 INFO L225 Difference]: With dead ends: 108 [2018-04-12 14:24:45,211 INFO L226 Difference]: Without dead ends: 108 [2018-04-12 14:24:45,211 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 22 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=91, Unknown=0, NotChecked=0, Total=132 [2018-04-12 14:24:45,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states. [2018-04-12 14:24:45,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 82. [2018-04-12 14:24:45,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-04-12 14:24:45,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 86 transitions. [2018-04-12 14:24:45,218 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 86 transitions. Word has length 24 [2018-04-12 14:24:45,218 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:45,218 INFO L459 AbstractCegarLoop]: Abstraction has 82 states and 86 transitions. [2018-04-12 14:24:45,218 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-12 14:24:45,219 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 86 transitions. [2018-04-12 14:24:45,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-04-12 14:24:45,219 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:45,219 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:45,219 INFO L408 AbstractCegarLoop]: === Iteration 7 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:45,220 INFO L82 PathProgramCache]: Analyzing trace with hash 1635534113, now seen corresponding path program 1 times [2018-04-12 14:24:45,220 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:45,220 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:45,220 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:45,221 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:45,221 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:45,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:45,232 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:45,344 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:45,345 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:24:45,345 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:24:45,350 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:45,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:45,365 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:24:45,382 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 14:24:45,383 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:45,387 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:45,388 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:15, output treesize:14 [2018-04-12 14:24:45,398 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 15 [2018-04-12 14:24:45,398 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:45,403 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-12 14:24:45,403 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:22, output treesize:21 [2018-04-12 14:24:45,478 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:45,494 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:24:45,495 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 9] total 12 [2018-04-12 14:24:45,495 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-04-12 14:24:45,495 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-04-12 14:24:45,495 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=113, Unknown=0, NotChecked=0, Total=156 [2018-04-12 14:24:45,495 INFO L87 Difference]: Start difference. First operand 82 states and 86 transitions. Second operand 13 states. [2018-04-12 14:24:45,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:45,825 INFO L93 Difference]: Finished difference Result 127 states and 132 transitions. [2018-04-12 14:24:45,826 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-12 14:24:45,826 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 27 [2018-04-12 14:24:45,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:45,827 INFO L225 Difference]: With dead ends: 127 [2018-04-12 14:24:45,827 INFO L226 Difference]: Without dead ends: 127 [2018-04-12 14:24:45,827 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 22 SyntacticMatches, 3 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=68, Invalid=172, Unknown=0, NotChecked=0, Total=240 [2018-04-12 14:24:45,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-04-12 14:24:45,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 88. [2018-04-12 14:24:45,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-04-12 14:24:45,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 92 transitions. [2018-04-12 14:24:45,833 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 92 transitions. Word has length 27 [2018-04-12 14:24:45,833 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:45,834 INFO L459 AbstractCegarLoop]: Abstraction has 88 states and 92 transitions. [2018-04-12 14:24:45,834 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-04-12 14:24:45,834 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 92 transitions. [2018-04-12 14:24:45,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-04-12 14:24:45,834 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:45,835 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:45,835 INFO L408 AbstractCegarLoop]: === Iteration 8 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:45,835 INFO L82 PathProgramCache]: Analyzing trace with hash -1703872188, now seen corresponding path program 1 times [2018-04-12 14:24:45,835 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:45,835 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:45,836 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:45,836 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:45,836 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:45,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:45,843 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:45,858 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 14:24:45,858 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 14:24:45,858 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-12 14:24:45,859 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-12 14:24:45,859 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-12 14:24:45,859 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-12 14:24:45,859 INFO L87 Difference]: Start difference. First operand 88 states and 92 transitions. Second operand 4 states. [2018-04-12 14:24:45,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:45,895 INFO L93 Difference]: Finished difference Result 85 states and 89 transitions. [2018-04-12 14:24:45,896 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-12 14:24:45,896 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 29 [2018-04-12 14:24:45,896 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:45,896 INFO L225 Difference]: With dead ends: 85 [2018-04-12 14:24:45,896 INFO L226 Difference]: Without dead ends: 85 [2018-04-12 14:24:45,897 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-12 14:24:45,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-04-12 14:24:45,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-04-12 14:24:45,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-04-12 14:24:45,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 89 transitions. [2018-04-12 14:24:45,899 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 89 transitions. Word has length 29 [2018-04-12 14:24:45,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:45,900 INFO L459 AbstractCegarLoop]: Abstraction has 85 states and 89 transitions. [2018-04-12 14:24:45,900 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-12 14:24:45,900 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 89 transitions. [2018-04-12 14:24:45,900 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-04-12 14:24:45,900 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:45,900 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:45,900 INFO L408 AbstractCegarLoop]: === Iteration 9 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:45,901 INFO L82 PathProgramCache]: Analyzing trace with hash -1703872187, now seen corresponding path program 1 times [2018-04-12 14:24:45,901 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:45,901 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:45,901 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:45,901 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:45,901 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:45,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:45,909 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:45,947 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 14:24:45,947 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 14:24:45,947 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-04-12 14:24:45,947 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-04-12 14:24:45,947 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-04-12 14:24:45,947 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-04-12 14:24:45,947 INFO L87 Difference]: Start difference. First operand 85 states and 89 transitions. Second operand 7 states. [2018-04-12 14:24:46,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:46,019 INFO L93 Difference]: Finished difference Result 81 states and 84 transitions. [2018-04-12 14:24:46,020 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-12 14:24:46,020 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 29 [2018-04-12 14:24:46,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:46,020 INFO L225 Difference]: With dead ends: 81 [2018-04-12 14:24:46,020 INFO L226 Difference]: Without dead ends: 81 [2018-04-12 14:24:46,020 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=41, Unknown=0, NotChecked=0, Total=72 [2018-04-12 14:24:46,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2018-04-12 14:24:46,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2018-04-12 14:24:46,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-04-12 14:24:46,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 84 transitions. [2018-04-12 14:24:46,023 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 84 transitions. Word has length 29 [2018-04-12 14:24:46,023 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:46,023 INFO L459 AbstractCegarLoop]: Abstraction has 81 states and 84 transitions. [2018-04-12 14:24:46,023 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-04-12 14:24:46,023 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 84 transitions. [2018-04-12 14:24:46,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-04-12 14:24:46,024 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:46,024 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:46,024 INFO L408 AbstractCegarLoop]: === Iteration 10 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:46,024 INFO L82 PathProgramCache]: Analyzing trace with hash -1280430239, now seen corresponding path program 1 times [2018-04-12 14:24:46,024 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:46,024 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:46,025 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:46,025 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:46,025 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:46,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:46,031 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:46,062 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 14:24:46,063 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 14:24:46,063 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-12 14:24:46,063 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-12 14:24:46,063 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-12 14:24:46,063 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-12 14:24:46,063 INFO L87 Difference]: Start difference. First operand 81 states and 84 transitions. Second operand 4 states. [2018-04-12 14:24:46,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:46,134 INFO L93 Difference]: Finished difference Result 100 states and 102 transitions. [2018-04-12 14:24:46,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-12 14:24:46,134 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 30 [2018-04-12 14:24:46,135 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:46,135 INFO L225 Difference]: With dead ends: 100 [2018-04-12 14:24:46,135 INFO L226 Difference]: Without dead ends: 100 [2018-04-12 14:24:46,136 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-12 14:24:46,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-04-12 14:24:46,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 83. [2018-04-12 14:24:46,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2018-04-12 14:24:46,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 86 transitions. [2018-04-12 14:24:46,139 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 86 transitions. Word has length 30 [2018-04-12 14:24:46,139 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:46,139 INFO L459 AbstractCegarLoop]: Abstraction has 83 states and 86 transitions. [2018-04-12 14:24:46,139 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-12 14:24:46,139 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 86 transitions. [2018-04-12 14:24:46,140 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-04-12 14:24:46,140 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:46,140 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:46,140 INFO L408 AbstractCegarLoop]: === Iteration 11 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:46,140 INFO L82 PathProgramCache]: Analyzing trace with hash 294456056, now seen corresponding path program 2 times [2018-04-12 14:24:46,140 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:46,140 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:46,141 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:46,141 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:46,141 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:46,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:46,148 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:46,206 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 5 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:46,206 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:24:46,207 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:24:46,215 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 14:24:46,234 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 14:24:46,235 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:24:46,236 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:24:46,262 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 10 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:46,280 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:24:46,280 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 7] total 12 [2018-04-12 14:24:46,280 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-04-12 14:24:46,280 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-04-12 14:24:46,280 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2018-04-12 14:24:46,280 INFO L87 Difference]: Start difference. First operand 83 states and 86 transitions. Second operand 12 states. [2018-04-12 14:24:46,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:46,429 INFO L93 Difference]: Finished difference Result 151 states and 153 transitions. [2018-04-12 14:24:46,429 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-12 14:24:46,429 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 31 [2018-04-12 14:24:46,430 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:46,430 INFO L225 Difference]: With dead ends: 151 [2018-04-12 14:24:46,430 INFO L226 Difference]: Without dead ends: 151 [2018-04-12 14:24:46,430 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 29 SyntacticMatches, 1 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 56 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=102, Invalid=278, Unknown=0, NotChecked=0, Total=380 [2018-04-12 14:24:46,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-04-12 14:24:46,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 113. [2018-04-12 14:24:46,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-04-12 14:24:46,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 118 transitions. [2018-04-12 14:24:46,433 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 118 transitions. Word has length 31 [2018-04-12 14:24:46,433 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:46,433 INFO L459 AbstractCegarLoop]: Abstraction has 113 states and 118 transitions. [2018-04-12 14:24:46,433 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-04-12 14:24:46,433 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 118 transitions. [2018-04-12 14:24:46,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-04-12 14:24:46,433 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:46,433 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:46,434 INFO L408 AbstractCegarLoop]: === Iteration 12 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:46,434 INFO L82 PathProgramCache]: Analyzing trace with hash 1815499577, now seen corresponding path program 1 times [2018-04-12 14:24:46,434 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:46,434 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:46,434 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:46,434 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:24:46,434 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:46,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:46,440 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:46,497 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-12 14:24:46,497 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 14:24:46,497 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-04-12 14:24:46,497 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-12 14:24:46,498 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-12 14:24:46,498 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-04-12 14:24:46,498 INFO L87 Difference]: Start difference. First operand 113 states and 118 transitions. Second operand 9 states. [2018-04-12 14:24:46,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:46,665 INFO L93 Difference]: Finished difference Result 132 states and 135 transitions. [2018-04-12 14:24:46,665 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-04-12 14:24:46,665 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 34 [2018-04-12 14:24:46,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:46,666 INFO L225 Difference]: With dead ends: 132 [2018-04-12 14:24:46,666 INFO L226 Difference]: Without dead ends: 132 [2018-04-12 14:24:46,666 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2018-04-12 14:24:46,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-04-12 14:24:46,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 114. [2018-04-12 14:24:46,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-04-12 14:24:46,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 118 transitions. [2018-04-12 14:24:46,669 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 118 transitions. Word has length 34 [2018-04-12 14:24:46,669 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:46,669 INFO L459 AbstractCegarLoop]: Abstraction has 114 states and 118 transitions. [2018-04-12 14:24:46,669 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-12 14:24:46,670 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 118 transitions. [2018-04-12 14:24:46,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-04-12 14:24:46,671 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:46,671 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:46,671 INFO L408 AbstractCegarLoop]: === Iteration 13 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:46,671 INFO L82 PathProgramCache]: Analyzing trace with hash -1628225274, now seen corresponding path program 3 times [2018-04-12 14:24:46,671 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:46,671 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:46,672 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:46,672 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:46,672 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:46,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:46,681 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:46,745 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-04-12 14:24:46,745 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:24:46,745 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:24:46,750 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 14:24:46,766 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-04-12 14:24:46,766 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:24:46,768 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:24:46,774 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 14:24:46,774 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:46,780 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 14:24:46,780 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:46,787 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:46,787 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-04-12 14:24:46,816 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:46,817 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-12 14:24:46,818 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:46,829 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:46,830 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:46,831 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-12 14:24:46,831 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:46,837 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:46,837 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:29, output treesize:22 [2018-04-12 14:24:46,953 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-04-12 14:24:46,970 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:24:46,970 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 8] total 13 [2018-04-12 14:24:46,970 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-04-12 14:24:46,970 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-04-12 14:24:46,970 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=150, Unknown=0, NotChecked=0, Total=182 [2018-04-12 14:24:46,970 INFO L87 Difference]: Start difference. First operand 114 states and 118 transitions. Second operand 14 states. [2018-04-12 14:24:47,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:47,278 INFO L93 Difference]: Finished difference Result 114 states and 118 transitions. [2018-04-12 14:24:47,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-12 14:24:47,278 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 34 [2018-04-12 14:24:47,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:47,279 INFO L225 Difference]: With dead ends: 114 [2018-04-12 14:24:47,279 INFO L226 Difference]: Without dead ends: 114 [2018-04-12 14:24:47,279 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=99, Invalid=363, Unknown=0, NotChecked=0, Total=462 [2018-04-12 14:24:47,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-04-12 14:24:47,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 112. [2018-04-12 14:24:47,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-04-12 14:24:47,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 116 transitions. [2018-04-12 14:24:47,281 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 116 transitions. Word has length 34 [2018-04-12 14:24:47,281 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:47,281 INFO L459 AbstractCegarLoop]: Abstraction has 112 states and 116 transitions. [2018-04-12 14:24:47,281 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-04-12 14:24:47,281 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 116 transitions. [2018-04-12 14:24:47,281 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-04-12 14:24:47,282 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:47,282 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:47,282 INFO L408 AbstractCegarLoop]: === Iteration 14 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:47,282 INFO L82 PathProgramCache]: Analyzing trace with hash 1135421431, now seen corresponding path program 1 times [2018-04-12 14:24:47,282 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:47,282 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:47,282 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:47,282 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:24:47,282 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:47,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:47,289 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:47,319 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 14:24:47,319 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 14:24:47,319 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-12 14:24:47,319 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-12 14:24:47,319 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-12 14:24:47,319 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-04-12 14:24:47,319 INFO L87 Difference]: Start difference. First operand 112 states and 116 transitions. Second operand 6 states. [2018-04-12 14:24:47,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:47,366 INFO L93 Difference]: Finished difference Result 111 states and 115 transitions. [2018-04-12 14:24:47,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-12 14:24:47,366 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35 [2018-04-12 14:24:47,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:47,366 INFO L225 Difference]: With dead ends: 111 [2018-04-12 14:24:47,366 INFO L226 Difference]: Without dead ends: 111 [2018-04-12 14:24:47,367 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=43, Unknown=0, NotChecked=0, Total=72 [2018-04-12 14:24:47,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-04-12 14:24:47,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2018-04-12 14:24:47,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-04-12 14:24:47,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 115 transitions. [2018-04-12 14:24:47,369 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 115 transitions. Word has length 35 [2018-04-12 14:24:47,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:47,369 INFO L459 AbstractCegarLoop]: Abstraction has 111 states and 115 transitions. [2018-04-12 14:24:47,369 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-12 14:24:47,369 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 115 transitions. [2018-04-12 14:24:47,369 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-04-12 14:24:47,369 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:47,370 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:47,370 INFO L408 AbstractCegarLoop]: === Iteration 15 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:47,370 INFO L82 PathProgramCache]: Analyzing trace with hash 1123969771, now seen corresponding path program 1 times [2018-04-12 14:24:47,370 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:47,370 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:47,371 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:47,371 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:47,371 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:47,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:47,379 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:47,552 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:47,552 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:24:47,552 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:24:47,558 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:47,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:47,573 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:24:47,591 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 15 [2018-04-12 14:24:47,593 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 3 [2018-04-12 14:24:47,593 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:47,595 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:47,595 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:47,595 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:19, output treesize:3 [2018-04-12 14:24:47,603 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 14:24:47,621 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-04-12 14:24:47,621 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [14] total 16 [2018-04-12 14:24:47,621 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-12 14:24:47,621 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-12 14:24:47,621 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=196, Unknown=0, NotChecked=0, Total=240 [2018-04-12 14:24:47,622 INFO L87 Difference]: Start difference. First operand 111 states and 115 transitions. Second operand 16 states. [2018-04-12 14:24:47,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:47,913 INFO L93 Difference]: Finished difference Result 122 states and 125 transitions. [2018-04-12 14:24:47,913 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-04-12 14:24:47,913 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 35 [2018-04-12 14:24:47,913 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:47,914 INFO L225 Difference]: With dead ends: 122 [2018-04-12 14:24:47,914 INFO L226 Difference]: Without dead ends: 122 [2018-04-12 14:24:47,914 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 33 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 105 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=165, Invalid=591, Unknown=0, NotChecked=0, Total=756 [2018-04-12 14:24:47,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states. [2018-04-12 14:24:47,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 112. [2018-04-12 14:24:47,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-04-12 14:24:47,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 116 transitions. [2018-04-12 14:24:47,917 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 116 transitions. Word has length 35 [2018-04-12 14:24:47,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:47,917 INFO L459 AbstractCegarLoop]: Abstraction has 112 states and 116 transitions. [2018-04-12 14:24:47,917 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-12 14:24:47,917 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 116 transitions. [2018-04-12 14:24:47,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-04-12 14:24:47,918 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:47,918 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:47,918 INFO L408 AbstractCegarLoop]: === Iteration 16 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:47,918 INFO L82 PathProgramCache]: Analyzing trace with hash 838326115, now seen corresponding path program 1 times [2018-04-12 14:24:47,918 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:47,918 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:47,919 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:47,919 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:47,919 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:47,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:47,925 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:47,963 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 14:24:47,963 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 14:24:47,964 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-04-12 14:24:47,964 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-04-12 14:24:47,964 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-04-12 14:24:47,964 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-04-12 14:24:47,964 INFO L87 Difference]: Start difference. First operand 112 states and 116 transitions. Second operand 7 states. [2018-04-12 14:24:48,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:48,029 INFO L93 Difference]: Finished difference Result 111 states and 115 transitions. [2018-04-12 14:24:48,029 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-12 14:24:48,029 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 36 [2018-04-12 14:24:48,029 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:48,029 INFO L225 Difference]: With dead ends: 111 [2018-04-12 14:24:48,030 INFO L226 Difference]: Without dead ends: 111 [2018-04-12 14:24:48,030 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=43, Invalid=89, Unknown=0, NotChecked=0, Total=132 [2018-04-12 14:24:48,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-04-12 14:24:48,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2018-04-12 14:24:48,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-04-12 14:24:48,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 115 transitions. [2018-04-12 14:24:48,032 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 115 transitions. Word has length 36 [2018-04-12 14:24:48,032 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:48,032 INFO L459 AbstractCegarLoop]: Abstraction has 111 states and 115 transitions. [2018-04-12 14:24:48,032 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-04-12 14:24:48,032 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 115 transitions. [2018-04-12 14:24:48,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-04-12 14:24:48,032 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:48,032 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:48,032 INFO L408 AbstractCegarLoop]: === Iteration 17 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:48,032 INFO L82 PathProgramCache]: Analyzing trace with hash -661412069, now seen corresponding path program 1 times [2018-04-12 14:24:48,032 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:48,033 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:48,033 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:48,033 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:48,033 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:48,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:48,039 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:48,170 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 14:24:48,170 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 14:24:48,170 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-04-12 14:24:48,170 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-12 14:24:48,170 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-12 14:24:48,170 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-04-12 14:24:48,171 INFO L87 Difference]: Start difference. First operand 111 states and 115 transitions. Second operand 10 states. [2018-04-12 14:24:48,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:48,389 INFO L93 Difference]: Finished difference Result 110 states and 114 transitions. [2018-04-12 14:24:48,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-12 14:24:48,389 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 39 [2018-04-12 14:24:48,389 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:48,390 INFO L225 Difference]: With dead ends: 110 [2018-04-12 14:24:48,390 INFO L226 Difference]: Without dead ends: 80 [2018-04-12 14:24:48,390 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=58, Invalid=182, Unknown=0, NotChecked=0, Total=240 [2018-04-12 14:24:48,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-04-12 14:24:48,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 80. [2018-04-12 14:24:48,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-04-12 14:24:48,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 83 transitions. [2018-04-12 14:24:48,392 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 83 transitions. Word has length 39 [2018-04-12 14:24:48,392 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:48,392 INFO L459 AbstractCegarLoop]: Abstraction has 80 states and 83 transitions. [2018-04-12 14:24:48,392 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-12 14:24:48,393 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 83 transitions. [2018-04-12 14:24:48,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-04-12 14:24:48,393 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:48,393 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:48,393 INFO L408 AbstractCegarLoop]: === Iteration 18 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:48,393 INFO L82 PathProgramCache]: Analyzing trace with hash -1581570445, now seen corresponding path program 1 times [2018-04-12 14:24:48,393 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:48,394 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:48,394 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:48,394 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:48,394 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:48,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:48,402 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:48,438 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-12 14:24:48,438 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 14:24:48,438 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-04-12 14:24:48,439 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-12 14:24:48,439 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-12 14:24:48,439 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-04-12 14:24:48,439 INFO L87 Difference]: Start difference. First operand 80 states and 83 transitions. Second operand 9 states. [2018-04-12 14:24:48,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:48,492 INFO L93 Difference]: Finished difference Result 79 states and 82 transitions. [2018-04-12 14:24:48,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-04-12 14:24:48,493 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 41 [2018-04-12 14:24:48,493 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:48,493 INFO L225 Difference]: With dead ends: 79 [2018-04-12 14:24:48,493 INFO L226 Difference]: Without dead ends: 79 [2018-04-12 14:24:48,494 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=48, Invalid=108, Unknown=0, NotChecked=0, Total=156 [2018-04-12 14:24:48,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2018-04-12 14:24:48,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 79. [2018-04-12 14:24:48,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-04-12 14:24:48,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 82 transitions. [2018-04-12 14:24:48,496 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 82 transitions. Word has length 41 [2018-04-12 14:24:48,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:48,497 INFO L459 AbstractCegarLoop]: Abstraction has 79 states and 82 transitions. [2018-04-12 14:24:48,497 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-12 14:24:48,497 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 82 transitions. [2018-04-12 14:24:48,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-04-12 14:24:48,497 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:48,497 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:48,498 INFO L408 AbstractCegarLoop]: === Iteration 19 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:48,498 INFO L82 PathProgramCache]: Analyzing trace with hash -678674494, now seen corresponding path program 1 times [2018-04-12 14:24:48,498 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:48,498 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:48,498 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:48,499 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:48,499 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:48,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:48,506 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:48,545 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 9 proven. 8 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-04-12 14:24:48,546 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:24:48,546 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:24:48,554 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:48,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:48,571 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:24:48,600 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 9 proven. 8 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-04-12 14:24:48,623 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:24:48,623 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 11 [2018-04-12 14:24:48,624 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-12 14:24:48,624 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-12 14:24:48,624 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=62, Unknown=0, NotChecked=0, Total=110 [2018-04-12 14:24:48,624 INFO L87 Difference]: Start difference. First operand 79 states and 82 transitions. Second operand 11 states. [2018-04-12 14:24:48,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:48,722 INFO L93 Difference]: Finished difference Result 106 states and 109 transitions. [2018-04-12 14:24:48,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-04-12 14:24:48,722 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 41 [2018-04-12 14:24:48,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:48,723 INFO L225 Difference]: With dead ends: 106 [2018-04-12 14:24:48,723 INFO L226 Difference]: Without dead ends: 106 [2018-04-12 14:24:48,723 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=106, Invalid=134, Unknown=0, NotChecked=0, Total=240 [2018-04-12 14:24:48,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-04-12 14:24:48,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 86. [2018-04-12 14:24:48,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-04-12 14:24:48,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 89 transitions. [2018-04-12 14:24:48,725 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 89 transitions. Word has length 41 [2018-04-12 14:24:48,725 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:48,726 INFO L459 AbstractCegarLoop]: Abstraction has 86 states and 89 transitions. [2018-04-12 14:24:48,726 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-12 14:24:48,726 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 89 transitions. [2018-04-12 14:24:48,726 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-04-12 14:24:48,726 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:48,726 INFO L355 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:48,726 INFO L408 AbstractCegarLoop]: === Iteration 20 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:48,726 INFO L82 PathProgramCache]: Analyzing trace with hash -507390837, now seen corresponding path program 2 times [2018-04-12 14:24:48,726 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:48,726 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:48,727 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:48,727 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:48,727 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:48,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:48,732 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:48,788 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-04-12 14:24:48,788 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:24:48,788 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:24:48,793 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 14:24:48,806 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 14:24:48,807 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:24:48,808 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:24:48,823 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 14:24:48,823 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:48,826 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:48,826 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-12 14:24:48,864 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-04-12 14:24:48,882 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:24:48,882 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6] total 11 [2018-04-12 14:24:48,882 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-04-12 14:24:48,882 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-04-12 14:24:48,882 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2018-04-12 14:24:48,883 INFO L87 Difference]: Start difference. First operand 86 states and 89 transitions. Second operand 12 states. [2018-04-12 14:24:48,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:48,976 INFO L93 Difference]: Finished difference Result 85 states and 88 transitions. [2018-04-12 14:24:48,976 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-12 14:24:48,976 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 45 [2018-04-12 14:24:48,976 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:48,977 INFO L225 Difference]: With dead ends: 85 [2018-04-12 14:24:48,977 INFO L226 Difference]: Without dead ends: 85 [2018-04-12 14:24:48,977 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 40 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=67, Invalid=173, Unknown=0, NotChecked=0, Total=240 [2018-04-12 14:24:48,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-04-12 14:24:48,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-04-12 14:24:48,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-04-12 14:24:48,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 88 transitions. [2018-04-12 14:24:48,979 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 88 transitions. Word has length 45 [2018-04-12 14:24:48,979 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:48,979 INFO L459 AbstractCegarLoop]: Abstraction has 85 states and 88 transitions. [2018-04-12 14:24:48,979 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-04-12 14:24:48,979 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 88 transitions. [2018-04-12 14:24:48,979 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-04-12 14:24:48,980 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:48,980 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:48,980 INFO L408 AbstractCegarLoop]: === Iteration 21 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:48,980 INFO L82 PathProgramCache]: Analyzing trace with hash -668266727, now seen corresponding path program 1 times [2018-04-12 14:24:48,980 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:48,980 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:48,981 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:48,981 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:24:48,981 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:48,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:48,992 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:49,460 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:49,460 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:24:49,460 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:24:49,466 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:49,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:49,482 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:24:49,499 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 14:24:49,500 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,502 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,503 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:13, output treesize:12 [2018-04-12 14:24:49,535 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:49,536 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:49,536 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-12 14:24:49,536 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,538 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,538 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:11 [2018-04-12 14:24:49,579 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-04-12 14:24:49,580 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-04-12 14:24:49,580 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,581 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,584 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,585 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:24, output treesize:20 [2018-04-12 14:24:49,607 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2018-04-12 14:24:49,609 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 1 [2018-04-12 14:24:49,609 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,609 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,612 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,612 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:23, output treesize:14 [2018-04-12 14:24:49,826 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 44 [2018-04-12 14:24:49,828 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 22 [2018-04-12 14:24:49,830 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 32 [2018-04-12 14:24:49,831 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,835 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,844 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 42 [2018-04-12 14:24:49,846 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:49,846 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 23 [2018-04-12 14:24:49,847 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,852 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,857 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,864 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-2 vars, End of recursive call: 4 dim-0 vars, and 1 xjuncts. [2018-04-12 14:24:49,864 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 5 variables, input treesize:69, output treesize:49 [2018-04-12 14:24:49,947 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 93 treesize of output 75 [2018-04-12 14:24:49,949 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:49,949 INFO L682 Elim1Store]: detected equality via solver [2018-04-12 14:24:49,950 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 72 [2018-04-12 14:24:49,950 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,958 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 10 [2018-04-12 14:24:49,958 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,960 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,963 INFO L267 ElimStorePlain]: Start of recursive call 1: 6 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:49,963 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 7 variables, input treesize:97, output treesize:10 [2018-04-12 14:24:49,985 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 10 refuted. 3 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:50,012 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:24:50,012 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 17] total 34 [2018-04-12 14:24:50,012 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-04-12 14:24:50,012 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-04-12 14:24:50,012 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=999, Unknown=26, NotChecked=0, Total=1122 [2018-04-12 14:24:50,013 INFO L87 Difference]: Start difference. First operand 85 states and 88 transitions. Second operand 34 states. [2018-04-12 14:24:51,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:51,562 INFO L93 Difference]: Finished difference Result 94 states and 97 transitions. [2018-04-12 14:24:51,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-04-12 14:24:51,562 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 46 [2018-04-12 14:24:51,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:51,562 INFO L225 Difference]: With dead ends: 94 [2018-04-12 14:24:51,562 INFO L226 Difference]: Without dead ends: 64 [2018-04-12 14:24:51,563 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 92 GetRequests, 33 SyntacticMatches, 3 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 599 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=388, Invalid=2851, Unknown=67, NotChecked=0, Total=3306 [2018-04-12 14:24:51,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-04-12 14:24:51,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 58. [2018-04-12 14:24:51,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-04-12 14:24:51,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 60 transitions. [2018-04-12 14:24:51,564 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 60 transitions. Word has length 46 [2018-04-12 14:24:51,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:51,564 INFO L459 AbstractCegarLoop]: Abstraction has 58 states and 60 transitions. [2018-04-12 14:24:51,564 INFO L460 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-04-12 14:24:51,564 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 60 transitions. [2018-04-12 14:24:51,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-04-12 14:24:51,565 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:51,565 INFO L355 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:51,565 INFO L408 AbstractCegarLoop]: === Iteration 22 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:51,565 INFO L82 PathProgramCache]: Analyzing trace with hash -1049287317, now seen corresponding path program 2 times [2018-04-12 14:24:51,565 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:51,565 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:51,565 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:51,565 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:24:51,565 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:51,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:51,574 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:52,223 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:52,223 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:24:52,223 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:24:52,228 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 14:24:52,243 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 14:24:52,243 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:24:52,245 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:24:52,250 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 14:24:52,251 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,257 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,258 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:13, output treesize:12 [2018-04-12 14:24:52,298 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:52,298 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:52,299 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-12 14:24:52,299 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,302 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,302 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:20, output treesize:14 [2018-04-12 14:24:52,351 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-04-12 14:24:52,352 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 14:24:52,352 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,353 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,357 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,357 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:25, output treesize:21 [2018-04-12 14:24:52,384 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 5 [2018-04-12 14:24:52,388 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-04-12 14:24:52,388 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,391 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,402 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,403 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:24, output treesize:17 [2018-04-12 14:24:52,856 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 54 [2018-04-12 14:24:52,858 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 29 [2018-04-12 14:24:52,861 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 38 [2018-04-12 14:24:52,869 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 41 [2018-04-12 14:24:52,869 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,875 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,878 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,892 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 56 [2018-04-12 14:24:52,895 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:52,895 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 25 [2018-04-12 14:24:52,898 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:52,898 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:52,899 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 40 [2018-04-12 14:24:52,899 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,904 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,910 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,916 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:52,926 INFO L267 ElimStorePlain]: Start of recursive call 1: 5 dim-0 vars, 1 dim-2 vars, End of recursive call: 5 dim-0 vars, and 1 xjuncts. [2018-04-12 14:24:52,926 INFO L202 ElimStorePlain]: Needed 8 recursive calls to eliminate 6 variables, input treesize:89, output treesize:70 [2018-04-12 14:24:53,044 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 109 treesize of output 83 [2018-04-12 14:24:53,047 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:53,048 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:53,049 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:53,049 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:53,050 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:53,051 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:53,051 INFO L682 Elim1Store]: detected equality via solver [2018-04-12 14:24:53,051 INFO L682 Elim1Store]: detected equality via solver [2018-04-12 14:24:53,052 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 3 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 144 [2018-04-12 14:24:53,052 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:53,067 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 14 [2018-04-12 14:24:53,067 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:53,069 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:53,071 INFO L267 ElimStorePlain]: Start of recursive call 1: 6 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:53,072 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 7 variables, input treesize:116, output treesize:17 [2018-04-12 14:24:53,104 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 0 proven. 25 refuted. 10 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:24:53,121 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:24:53,121 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 21] total 42 [2018-04-12 14:24:53,121 INFO L442 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-04-12 14:24:53,121 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-04-12 14:24:53,122 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=129, Invalid=1544, Unknown=49, NotChecked=0, Total=1722 [2018-04-12 14:24:53,122 INFO L87 Difference]: Start difference. First operand 58 states and 60 transitions. Second operand 42 states. [2018-04-12 14:24:55,349 WARN L151 SmtUtils]: Spent 105ms on a formula simplification. DAG size of input: 106 DAG size of output 66 [2018-04-12 14:24:56,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:56,974 INFO L93 Difference]: Finished difference Result 151 states and 158 transitions. [2018-04-12 14:24:56,976 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-04-12 14:24:56,976 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 57 [2018-04-12 14:24:56,976 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:56,976 INFO L225 Difference]: With dead ends: 151 [2018-04-12 14:24:56,976 INFO L226 Difference]: Without dead ends: 123 [2018-04-12 14:24:56,977 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 127 GetRequests, 42 SyntacticMatches, 3 SemanticMatches, 82 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1512 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=719, Invalid=6077, Unknown=176, NotChecked=0, Total=6972 [2018-04-12 14:24:56,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states. [2018-04-12 14:24:56,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 104. [2018-04-12 14:24:56,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104 states. [2018-04-12 14:24:56,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 109 transitions. [2018-04-12 14:24:56,979 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 109 transitions. Word has length 57 [2018-04-12 14:24:56,979 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:56,979 INFO L459 AbstractCegarLoop]: Abstraction has 104 states and 109 transitions. [2018-04-12 14:24:56,979 INFO L460 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-04-12 14:24:56,979 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 109 transitions. [2018-04-12 14:24:56,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-04-12 14:24:56,980 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:56,980 INFO L355 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:56,980 INFO L408 AbstractCegarLoop]: === Iteration 23 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:56,980 INFO L82 PathProgramCache]: Analyzing trace with hash -145570311, now seen corresponding path program 3 times [2018-04-12 14:24:56,980 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:56,980 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:56,980 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:56,981 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:24:56,981 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:56,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:56,986 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:57,043 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 18 proven. 18 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-12 14:24:57,043 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:24:57,043 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:24:57,053 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 14:24:57,079 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-04-12 14:24:57,080 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:24:57,081 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:24:57,146 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 18 proven. 8 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-12 14:24:57,174 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:24:57,174 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 9] total 14 [2018-04-12 14:24:57,175 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-04-12 14:24:57,175 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-04-12 14:24:57,175 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=122, Unknown=0, NotChecked=0, Total=182 [2018-04-12 14:24:57,175 INFO L87 Difference]: Start difference. First operand 104 states and 109 transitions. Second operand 14 states. [2018-04-12 14:24:57,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:24:57,323 INFO L93 Difference]: Finished difference Result 140 states and 146 transitions. [2018-04-12 14:24:57,323 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-04-12 14:24:57,323 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 60 [2018-04-12 14:24:57,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:24:57,324 INFO L225 Difference]: With dead ends: 140 [2018-04-12 14:24:57,324 INFO L226 Difference]: Without dead ends: 140 [2018-04-12 14:24:57,324 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 57 SyntacticMatches, 1 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 77 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=137, Invalid=283, Unknown=0, NotChecked=0, Total=420 [2018-04-12 14:24:57,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-04-12 14:24:57,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 66. [2018-04-12 14:24:57,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-04-12 14:24:57,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 68 transitions. [2018-04-12 14:24:57,326 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 68 transitions. Word has length 60 [2018-04-12 14:24:57,326 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:24:57,326 INFO L459 AbstractCegarLoop]: Abstraction has 66 states and 68 transitions. [2018-04-12 14:24:57,326 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-04-12 14:24:57,326 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 68 transitions. [2018-04-12 14:24:57,327 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-04-12 14:24:57,327 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:24:57,327 INFO L355 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:24:57,327 INFO L408 AbstractCegarLoop]: === Iteration 24 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:24:57,327 INFO L82 PathProgramCache]: Analyzing trace with hash 1841342091, now seen corresponding path program 4 times [2018-04-12 14:24:57,327 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:24:57,327 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:24:57,327 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:57,328 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:24:57,328 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:24:57,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:24:57,335 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:24:57,415 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 21 proven. 20 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-12 14:24:57,415 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:24:57,416 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:24:57,428 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-12 14:24:57,467 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-12 14:24:57,468 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:24:57,470 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:24:57,471 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 14:24:57,472 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:57,472 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:57,472 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-12 14:24:57,484 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:57,484 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:57,485 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-12 14:24:57,485 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:57,486 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:57,486 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:11, output treesize:4 [2018-04-12 14:24:57,501 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-04-12 14:24:57,502 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-04-12 14:24:57,502 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:57,503 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:57,505 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:57,506 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:18, output treesize:14 [2018-04-12 14:24:57,515 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2018-04-12 14:24:57,516 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 1 [2018-04-12 14:24:57,516 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:57,517 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:57,518 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:57,519 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:17, output treesize:8 [2018-04-12 14:24:58,170 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 58 [2018-04-12 14:24:58,172 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 26 [2018-04-12 14:24:58,174 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,174 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2018-04-12 14:24:58,176 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,177 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,177 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,178 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 50 [2018-04-12 14:24:58,180 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,181 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,181 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,182 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,182 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,183 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,184 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 77 [2018-04-12 14:24:58,184 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:58,195 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:58,201 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:58,207 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:58,221 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 64 [2018-04-12 14:24:58,223 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,224 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2018-04-12 14:24:58,226 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,226 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,227 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,228 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 50 [2018-04-12 14:24:58,230 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,230 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,231 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,231 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,232 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,232 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,233 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 77 [2018-04-12 14:24:58,233 INFO L267 ElimStorePlain]: Start of recursive call 10: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:58,241 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:58,246 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:58,256 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:58,265 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:58,278 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-12 14:24:58,278 INFO L202 ElimStorePlain]: Needed 10 recursive calls to eliminate 3 variables, input treesize:87, output treesize:79 [2018-04-12 14:24:58,418 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 147 treesize of output 113 [2018-04-12 14:24:58,420 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,420 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,421 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,421 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,422 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,422 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,423 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 43 [2018-04-12 14:24:58,423 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:58,438 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,439 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,439 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,440 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,440 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,441 INFO L682 Elim1Store]: detected equality via solver [2018-04-12 14:24:58,441 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,441 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:24:58,442 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 6 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 67 treesize of output 71 [2018-04-12 14:24:58,442 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-12 14:24:58,450 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:58,454 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:24:58,454 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 5 variables, input treesize:151, output treesize:10 [2018-04-12 14:24:58,505 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 14:24:58,524 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:24:58,524 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 28] total 38 [2018-04-12 14:24:58,524 INFO L442 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-04-12 14:24:58,525 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-04-12 14:24:58,525 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=1316, Unknown=0, NotChecked=0, Total=1406 [2018-04-12 14:24:58,525 INFO L87 Difference]: Start difference. First operand 66 states and 68 transitions. Second operand 38 states. [2018-04-12 14:25:01,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:25:01,133 INFO L93 Difference]: Finished difference Result 123 states and 127 transitions. [2018-04-12 14:25:01,133 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-04-12 14:25:01,133 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 65 [2018-04-12 14:25:01,133 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:25:01,133 INFO L225 Difference]: With dead ends: 123 [2018-04-12 14:25:01,133 INFO L226 Difference]: Without dead ends: 74 [2018-04-12 14:25:01,135 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 48 SyntacticMatches, 1 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1674 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=574, Invalid=6736, Unknown=0, NotChecked=0, Total=7310 [2018-04-12 14:25:01,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-04-12 14:25:01,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 73. [2018-04-12 14:25:01,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-04-12 14:25:01,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 75 transitions. [2018-04-12 14:25:01,136 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 75 transitions. Word has length 65 [2018-04-12 14:25:01,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:25:01,136 INFO L459 AbstractCegarLoop]: Abstraction has 73 states and 75 transitions. [2018-04-12 14:25:01,136 INFO L460 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-04-12 14:25:01,136 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 75 transitions. [2018-04-12 14:25:01,136 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-04-12 14:25:01,136 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:25:01,136 INFO L355 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:25:01,136 INFO L408 AbstractCegarLoop]: === Iteration 25 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:25:01,136 INFO L82 PathProgramCache]: Analyzing trace with hash -1568543774, now seen corresponding path program 5 times [2018-04-12 14:25:01,137 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:25:01,137 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:25:01,137 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:25:01,137 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:25:01,137 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:25:01,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:25:01,147 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:25:01,214 INFO L134 CoverageAnalysis]: Checked inductivity of 86 backedges. 35 proven. 33 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-12 14:25:01,215 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:25:01,215 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:25:01,220 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-12 14:25:01,246 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-04-12 14:25:01,246 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:25:01,247 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:25:01,295 INFO L134 CoverageAnalysis]: Checked inductivity of 86 backedges. 50 proven. 18 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-12 14:25:01,330 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:25:01,330 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 11] total 19 [2018-04-12 14:25:01,330 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-04-12 14:25:01,330 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-04-12 14:25:01,331 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=274, Unknown=0, NotChecked=0, Total=342 [2018-04-12 14:25:01,331 INFO L87 Difference]: Start difference. First operand 73 states and 75 transitions. Second operand 19 states. [2018-04-12 14:25:01,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:25:01,521 INFO L93 Difference]: Finished difference Result 102 states and 104 transitions. [2018-04-12 14:25:01,521 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-04-12 14:25:01,521 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 72 [2018-04-12 14:25:01,522 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:25:01,522 INFO L225 Difference]: With dead ends: 102 [2018-04-12 14:25:01,522 INFO L226 Difference]: Without dead ends: 76 [2018-04-12 14:25:01,522 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 74 SyntacticMatches, 2 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 161 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=162, Invalid=650, Unknown=0, NotChecked=0, Total=812 [2018-04-12 14:25:01,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-04-12 14:25:01,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 76. [2018-04-12 14:25:01,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-04-12 14:25:01,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 78 transitions. [2018-04-12 14:25:01,523 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 78 transitions. Word has length 72 [2018-04-12 14:25:01,523 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:25:01,524 INFO L459 AbstractCegarLoop]: Abstraction has 76 states and 78 transitions. [2018-04-12 14:25:01,524 INFO L460 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-04-12 14:25:01,524 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 78 transitions. [2018-04-12 14:25:01,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2018-04-12 14:25:01,524 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:25:01,524 INFO L355 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:25:01,524 INFO L408 AbstractCegarLoop]: === Iteration 26 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:25:01,524 INFO L82 PathProgramCache]: Analyzing trace with hash -1600561772, now seen corresponding path program 6 times [2018-04-12 14:25:01,524 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:25:01,524 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:25:01,525 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:25:01,525 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:25:01,525 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:25:01,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:25:01,531 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:25:01,569 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 30 proven. 18 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-04-12 14:25:01,569 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:25:01,569 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:25:01,581 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-12 14:25:01,671 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2018-04-12 14:25:01,671 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:25:01,674 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:25:01,945 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 30 proven. 18 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-04-12 14:25:01,978 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:25:01,978 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11] total 16 [2018-04-12 14:25:01,978 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-12 14:25:01,978 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-12 14:25:01,979 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=160, Unknown=0, NotChecked=0, Total=240 [2018-04-12 14:25:01,979 INFO L87 Difference]: Start difference. First operand 76 states and 78 transitions. Second operand 16 states. [2018-04-12 14:25:02,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:25:02,076 INFO L93 Difference]: Finished difference Result 82 states and 84 transitions. [2018-04-12 14:25:02,076 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-04-12 14:25:02,076 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 75 [2018-04-12 14:25:02,077 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:25:02,077 INFO L225 Difference]: With dead ends: 82 [2018-04-12 14:25:02,077 INFO L226 Difference]: Without dead ends: 82 [2018-04-12 14:25:02,077 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 89 GetRequests, 72 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=99, Invalid=207, Unknown=0, NotChecked=0, Total=306 [2018-04-12 14:25:02,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-04-12 14:25:02,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 80. [2018-04-12 14:25:02,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-04-12 14:25:02,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 82 transitions. [2018-04-12 14:25:02,078 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 82 transitions. Word has length 75 [2018-04-12 14:25:02,078 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:25:02,078 INFO L459 AbstractCegarLoop]: Abstraction has 80 states and 82 transitions. [2018-04-12 14:25:02,078 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-12 14:25:02,078 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 82 transitions. [2018-04-12 14:25:02,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-04-12 14:25:02,079 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:25:02,079 INFO L355 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:25:02,079 INFO L408 AbstractCegarLoop]: === Iteration 27 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:25:02,079 INFO L82 PathProgramCache]: Analyzing trace with hash 42879979, now seen corresponding path program 7 times [2018-04-12 14:25:02,079 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:25:02,079 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:25:02,080 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:25:02,080 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:25:02,080 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:25:02,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:25:02,094 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:25:03,465 WARN L151 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 84 DAG size of output 69 [2018-04-12 14:25:03,691 WARN L151 SmtUtils]: Spent 134ms on a formula simplification. DAG size of input: 101 DAG size of output 73 [2018-04-12 14:25:04,049 WARN L151 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 97 DAG size of output 67 [2018-04-12 14:25:04,249 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 28 proven. 84 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:25:04,249 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:25:04,249 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:25:04,254 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:25:04,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:25:04,271 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:25:04,275 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 14:25:04,275 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:04,280 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:04,280 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:13, output treesize:12 [2018-04-12 14:25:04,345 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:04,346 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:04,346 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-12 14:25:04,346 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:04,348 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:04,348 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:11 [2018-04-12 14:25:04,417 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-04-12 14:25:04,418 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-04-12 14:25:04,418 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:04,419 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:04,422 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:04,422 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:24, output treesize:20 [2018-04-12 14:25:04,457 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2018-04-12 14:25:04,458 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 1 [2018-04-12 14:25:04,458 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:04,459 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:04,461 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:04,462 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:23, output treesize:14 [2018-04-12 14:25:06,140 WARN L151 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 61 DAG size of output 52 [2018-04-12 14:25:06,155 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 80 [2018-04-12 14:25:06,157 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 43 [2018-04-12 14:25:06,163 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 54 [2018-04-12 14:25:06,174 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 56 [2018-04-12 14:25:06,189 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 58 [2018-04-12 14:25:06,211 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 65 [2018-04-12 14:25:06,211 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:06,222 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:06,233 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:06,244 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:06,255 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:06,285 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 90 [2018-04-12 14:25:06,292 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,292 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 39 [2018-04-12 14:25:06,296 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,297 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,299 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,299 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 55 [2018-04-12 14:25:06,303 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,304 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,304 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,306 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,306 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,308 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,308 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 79 [2018-04-12 14:25:06,312 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,313 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,314 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,315 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,316 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,316 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,317 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,318 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,319 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,320 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,320 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 116 [2018-04-12 14:25:06,321 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:06,336 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:06,345 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:06,351 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:06,364 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:06,375 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:06,391 INFO L267 ElimStorePlain]: Start of recursive call 1: 7 dim-0 vars, 1 dim-2 vars, End of recursive call: 7 dim-0 vars, and 1 xjuncts. [2018-04-12 14:25:06,391 INFO L202 ElimStorePlain]: Needed 12 recursive calls to eliminate 8 variables, input treesize:126, output treesize:109 [2018-04-12 14:25:06,587 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 189 treesize of output 147 [2018-04-12 14:25:06,589 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,589 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,590 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,590 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,591 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,591 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,592 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,592 INFO L682 Elim1Store]: detected equality via solver [2018-04-12 14:25:06,593 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,593 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,594 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,594 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:06,595 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 10 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 143 treesize of output 227 [2018-04-12 14:25:06,595 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:06,627 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 95 treesize of output 14 [2018-04-12 14:25:06,627 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:06,638 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:06,640 INFO L267 ElimStorePlain]: Start of recursive call 1: 9 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-12 14:25:06,640 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 10 variables, input treesize:193, output treesize:14 [2018-04-12 14:25:06,715 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 76 refuted. 36 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:25:06,732 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:25:06,732 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 29] total 54 [2018-04-12 14:25:06,732 INFO L442 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-04-12 14:25:06,732 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-04-12 14:25:06,733 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=197, Invalid=2534, Unknown=131, NotChecked=0, Total=2862 [2018-04-12 14:25:06,733 INFO L87 Difference]: Start difference. First operand 80 states and 82 transitions. Second operand 54 states. [2018-04-12 14:25:11,520 WARN L151 SmtUtils]: Spent 129ms on a formula simplification. DAG size of input: 95 DAG size of output 68 [2018-04-12 14:25:12,221 WARN L151 SmtUtils]: Spent 150ms on a formula simplification. DAG size of input: 103 DAG size of output 68 [2018-04-12 14:25:13,271 WARN L151 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 106 DAG size of output 71 [2018-04-12 14:25:13,689 WARN L151 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 88 DAG size of output 64 [2018-04-12 14:25:14,036 WARN L151 SmtUtils]: Spent 134ms on a formula simplification. DAG size of input: 74 DAG size of output 71 [2018-04-12 14:25:14,287 WARN L151 SmtUtils]: Spent 111ms on a formula simplification. DAG size of input: 108 DAG size of output 68 [2018-04-12 14:25:14,653 WARN L151 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 84 DAG size of output 67 [2018-04-12 14:25:16,518 WARN L151 SmtUtils]: Spent 1223ms on a formula simplification. DAG size of input: 147 DAG size of output 99 [2018-04-12 14:25:16,817 WARN L151 SmtUtils]: Spent 114ms on a formula simplification. DAG size of input: 103 DAG size of output 70 [2018-04-12 14:25:17,040 WARN L151 SmtUtils]: Spent 114ms on a formula simplification. DAG size of input: 97 DAG size of output 77 [2018-04-12 14:25:20,951 WARN L151 SmtUtils]: Spent 1122ms on a formula simplification. DAG size of input: 153 DAG size of output 102 [2018-04-12 14:25:21,261 WARN L151 SmtUtils]: Spent 137ms on a formula simplification. DAG size of input: 116 DAG size of output 75 [2018-04-12 14:25:23,692 WARN L151 SmtUtils]: Spent 307ms on a formula simplification. DAG size of input: 156 DAG size of output 126 [2018-04-12 14:25:23,973 WARN L151 SmtUtils]: Spent 133ms on a formula simplification. DAG size of input: 89 DAG size of output 77 [2018-04-12 14:25:24,913 WARN L151 SmtUtils]: Spent 225ms on a formula simplification. DAG size of input: 132 DAG size of output 108 [2018-04-12 14:25:25,347 WARN L151 SmtUtils]: Spent 178ms on a formula simplification. DAG size of input: 94 DAG size of output 82 [2018-04-12 14:25:25,893 WARN L151 SmtUtils]: Spent 227ms on a formula simplification. DAG size of input: 92 DAG size of output 87 [2018-04-12 14:25:26,418 WARN L151 SmtUtils]: Spent 212ms on a formula simplification. DAG size of input: 115 DAG size of output 92 [2018-04-12 14:25:29,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:25:29,295 INFO L93 Difference]: Finished difference Result 199 states and 207 transitions. [2018-04-12 14:25:29,336 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2018-04-12 14:25:29,336 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 79 [2018-04-12 14:25:29,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:25:29,337 INFO L225 Difference]: With dead ends: 199 [2018-04-12 14:25:29,337 INFO L226 Difference]: Without dead ends: 163 [2018-04-12 14:25:29,339 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 186 GetRequests, 62 SyntacticMatches, 6 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3748 ImplicationChecksByTransitivity, 18.8s TimeCoverageRelationStatistics Valid=1350, Invalid=12501, Unknown=429, NotChecked=0, Total=14280 [2018-04-12 14:25:29,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-04-12 14:25:29,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 142. [2018-04-12 14:25:29,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-04-12 14:25:29,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 147 transitions. [2018-04-12 14:25:29,341 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 147 transitions. Word has length 79 [2018-04-12 14:25:29,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:25:29,341 INFO L459 AbstractCegarLoop]: Abstraction has 142 states and 147 transitions. [2018-04-12 14:25:29,341 INFO L460 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-04-12 14:25:29,341 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 147 transitions. [2018-04-12 14:25:29,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-04-12 14:25:29,341 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:25:29,341 INFO L355 BasicCegarLoop]: trace histogram [6, 6, 6, 5, 5, 5, 5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:25:29,341 INFO L408 AbstractCegarLoop]: === Iteration 28 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:25:29,341 INFO L82 PathProgramCache]: Analyzing trace with hash -336138759, now seen corresponding path program 8 times [2018-04-12 14:25:29,342 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:25:29,342 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:25:29,342 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:25:29,342 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:25:29,342 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:25:29,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:25:29,350 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:25:29,430 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 45 proven. 50 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-04-12 14:25:29,431 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:25:29,431 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:25:29,439 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 14:25:29,471 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 14:25:29,471 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:25:29,474 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:25:29,565 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 45 proven. 50 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-04-12 14:25:29,582 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:25:29,582 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14] total 21 [2018-04-12 14:25:29,583 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-04-12 14:25:29,583 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-04-12 14:25:29,583 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=280, Unknown=0, NotChecked=0, Total=420 [2018-04-12 14:25:29,583 INFO L87 Difference]: Start difference. First operand 142 states and 147 transitions. Second operand 21 states. [2018-04-12 14:25:29,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:25:29,768 INFO L93 Difference]: Finished difference Result 178 states and 184 transitions. [2018-04-12 14:25:29,769 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-04-12 14:25:29,769 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 82 [2018-04-12 14:25:29,769 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:25:29,770 INFO L225 Difference]: With dead ends: 178 [2018-04-12 14:25:29,770 INFO L226 Difference]: Without dead ends: 178 [2018-04-12 14:25:29,770 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 76 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 176 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=268, Invalid=544, Unknown=0, NotChecked=0, Total=812 [2018-04-12 14:25:29,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states. [2018-04-12 14:25:29,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 88. [2018-04-12 14:25:29,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-04-12 14:25:29,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 90 transitions. [2018-04-12 14:25:29,773 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 90 transitions. Word has length 82 [2018-04-12 14:25:29,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:25:29,773 INFO L459 AbstractCegarLoop]: Abstraction has 88 states and 90 transitions. [2018-04-12 14:25:29,773 INFO L460 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-04-12 14:25:29,773 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 90 transitions. [2018-04-12 14:25:29,774 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-04-12 14:25:29,774 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:25:29,774 INFO L355 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 5, 5, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:25:29,774 INFO L408 AbstractCegarLoop]: === Iteration 29 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:25:29,774 INFO L82 PathProgramCache]: Analyzing trace with hash -1527891189, now seen corresponding path program 9 times [2018-04-12 14:25:29,774 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:25:29,774 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:25:29,775 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:25:29,775 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:25:29,775 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:25:29,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:25:29,784 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:25:29,885 INFO L134 CoverageAnalysis]: Checked inductivity of 152 backedges. 53 proven. 49 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-04-12 14:25:29,885 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:25:29,885 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:25:29,890 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 14:25:29,926 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-04-12 14:25:29,927 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:25:29,928 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:25:29,982 INFO L134 CoverageAnalysis]: Checked inductivity of 152 backedges. 50 proven. 30 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-04-12 14:25:30,000 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:25:30,000 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 12] total 21 [2018-04-12 14:25:30,001 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-04-12 14:25:30,001 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-04-12 14:25:30,001 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=339, Unknown=0, NotChecked=0, Total=420 [2018-04-12 14:25:30,001 INFO L87 Difference]: Start difference. First operand 88 states and 90 transitions. Second operand 21 states. [2018-04-12 14:25:30,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:25:30,231 INFO L93 Difference]: Finished difference Result 121 states and 123 transitions. [2018-04-12 14:25:30,231 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-04-12 14:25:30,231 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 87 [2018-04-12 14:25:30,231 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:25:30,232 INFO L225 Difference]: With dead ends: 121 [2018-04-12 14:25:30,232 INFO L226 Difference]: Without dead ends: 91 [2018-04-12 14:25:30,232 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 90 SyntacticMatches, 2 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 219 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=207, Invalid=849, Unknown=0, NotChecked=0, Total=1056 [2018-04-12 14:25:30,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-04-12 14:25:30,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 91. [2018-04-12 14:25:30,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2018-04-12 14:25:30,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 93 transitions. [2018-04-12 14:25:30,234 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 93 transitions. Word has length 87 [2018-04-12 14:25:30,234 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:25:30,234 INFO L459 AbstractCegarLoop]: Abstraction has 91 states and 93 transitions. [2018-04-12 14:25:30,235 INFO L460 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-04-12 14:25:30,235 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 93 transitions. [2018-04-12 14:25:30,235 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-04-12 14:25:30,235 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:25:30,235 INFO L355 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:25:30,235 INFO L408 AbstractCegarLoop]: === Iteration 30 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:25:30,235 INFO L82 PathProgramCache]: Analyzing trace with hash 273870617, now seen corresponding path program 10 times [2018-04-12 14:25:30,235 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:25:30,235 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:25:30,236 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:25:30,236 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:25:30,236 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:25:30,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:25:30,252 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:25:32,794 WARN L151 SmtUtils]: Spent 133ms on a formula simplification. DAG size of input: 93 DAG size of output 67 [2018-04-12 14:25:33,183 WARN L151 SmtUtils]: Spent 161ms on a formula simplification. DAG size of input: 115 DAG size of output 72 [2018-04-12 14:25:33,788 WARN L151 SmtUtils]: Spent 165ms on a formula simplification. DAG size of input: 113 DAG size of output 65 [2018-04-12 14:25:34,206 INFO L134 CoverageAnalysis]: Checked inductivity of 167 backedges. 0 proven. 167 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:25:34,206 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:25:34,206 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:25:34,211 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-12 14:25:34,229 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-12 14:25:34,229 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:25:34,231 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:25:34,235 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 14:25:34,236 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:34,237 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:34,237 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-12 14:25:34,329 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:34,329 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:34,361 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-12 14:25:34,361 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:34,361 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:34,361 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:11, output treesize:4 [2018-04-12 14:25:34,445 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-04-12 14:25:34,446 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-04-12 14:25:34,446 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:34,447 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:34,449 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:34,449 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:18, output treesize:14 [2018-04-12 14:25:34,498 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2018-04-12 14:25:34,499 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 1 [2018-04-12 14:25:34,499 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:34,500 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:34,502 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:34,502 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:17, output treesize:8 [2018-04-12 14:25:37,981 WARN L151 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 58 DAG size of output 48 [2018-04-12 14:25:37,994 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 78 [2018-04-12 14:25:37,998 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 36 [2018-04-12 14:25:38,001 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,002 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 44 [2018-04-12 14:25:38,005 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,006 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,007 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,008 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 60 [2018-04-12 14:25:38,012 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,014 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,015 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,016 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,019 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,020 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,021 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 84 [2018-04-12 14:25:38,025 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,026 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,028 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,029 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,030 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,031 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,032 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,033 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,034 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,036 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,036 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 42 treesize of output 116 [2018-04-12 14:25:38,040 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,041 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,043 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,044 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,045 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,046 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,047 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,048 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,049 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,050 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,051 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,052 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,053 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,054 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,056 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,056 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 163 [2018-04-12 14:25:38,057 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,091 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,114 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,133 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,149 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,164 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,194 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 93 treesize of output 92 [2018-04-12 14:25:38,198 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,199 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 44 [2018-04-12 14:25:38,202 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,203 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,204 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,204 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 60 [2018-04-12 14:25:38,207 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,208 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,209 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,210 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,210 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,211 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,211 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 84 [2018-04-12 14:25:38,214 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,215 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,215 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,216 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,217 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,217 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,218 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,218 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,219 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,220 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,220 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 42 treesize of output 116 [2018-04-12 14:25:38,223 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,223 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,224 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,225 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,225 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,226 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,226 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,227 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,227 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,228 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,228 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,229 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,229 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,230 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,230 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,231 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 163 [2018-04-12 14:25:38,232 INFO L267 ElimStorePlain]: Start of recursive call 14: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,248 INFO L267 ElimStorePlain]: Start of recursive call 13: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,258 INFO L267 ElimStorePlain]: Start of recursive call 12: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,266 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,272 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,286 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,298 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,313 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-12 14:25:38,313 INFO L202 ElimStorePlain]: Needed 14 recursive calls to eliminate 3 variables, input treesize:117, output treesize:115 [2018-04-12 14:25:38,560 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 207 treesize of output 157 [2018-04-12 14:25:38,563 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,563 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,564 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,564 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,565 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,565 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,566 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,575 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,575 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,576 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,576 INFO L682 Elim1Store]: detected equality via solver [2018-04-12 14:25:38,577 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,578 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,578 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,579 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,579 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,580 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,580 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 7 select indices, 7 select index equivalence classes, 15 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 153 treesize of output 247 [2018-04-12 14:25:38,581 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,617 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,618 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,618 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,619 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,619 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,620 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,620 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,620 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,621 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,621 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,622 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,622 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,623 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,623 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,623 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:25:38,624 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 15 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 82 treesize of output 124 [2018-04-12 14:25:38,624 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,634 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:25:38,637 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-12 14:25:38,637 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 5 variables, input treesize:211, output treesize:14 [2018-04-12 14:25:38,729 INFO L134 CoverageAnalysis]: Checked inductivity of 167 backedges. 0 proven. 122 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-04-12 14:25:38,746 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:25:38,746 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 36] total 71 [2018-04-12 14:25:38,746 INFO L442 AbstractCegarLoop]: Interpolant automaton has 71 states [2018-04-12 14:25:38,746 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2018-04-12 14:25:38,747 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=376, Invalid=4594, Unknown=0, NotChecked=0, Total=4970 [2018-04-12 14:25:38,747 INFO L87 Difference]: Start difference. First operand 91 states and 93 transitions. Second operand 71 states. [2018-04-12 14:25:49,360 WARN L151 SmtUtils]: Spent 154ms on a formula simplification. DAG size of input: 87 DAG size of output 63 [2018-04-12 14:25:50,586 WARN L151 SmtUtils]: Spent 167ms on a formula simplification. DAG size of input: 94 DAG size of output 62 [2018-04-12 14:25:51,842 WARN L151 SmtUtils]: Spent 186ms on a formula simplification. DAG size of input: 97 DAG size of output 65 [2018-04-12 14:25:53,389 WARN L151 SmtUtils]: Spent 817ms on a formula simplification. DAG size of input: 147 DAG size of output 92 [2018-04-12 14:25:55,554 WARN L151 SmtUtils]: Spent 745ms on a formula simplification. DAG size of input: 152 DAG size of output 94 [2018-04-12 14:25:55,979 WARN L151 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 110 DAG size of output 68 [2018-04-12 14:25:58,154 WARN L151 SmtUtils]: Spent 757ms on a formula simplification. DAG size of input: 133 DAG size of output 89 [2018-04-12 14:26:00,573 WARN L151 SmtUtils]: Spent 165ms on a formula simplification. DAG size of input: 85 DAG size of output 72 [2018-04-12 14:26:04,723 WARN L151 SmtUtils]: Spent 605ms on a formula simplification. DAG size of input: 138 DAG size of output 91 [2018-04-12 14:26:05,347 WARN L151 SmtUtils]: Spent 174ms on a formula simplification. DAG size of input: 102 DAG size of output 79 [2018-04-12 14:26:06,292 WARN L151 SmtUtils]: Spent 163ms on a formula simplification. DAG size of input: 90 DAG size of output 76 [2018-04-12 14:26:07,211 WARN L151 SmtUtils]: Spent 254ms on a formula simplification. DAG size of input: 113 DAG size of output 90 [2018-04-12 14:26:08,789 WARN L151 SmtUtils]: Spent 141ms on a formula simplification. DAG size of input: 77 DAG size of output 76 [2018-04-12 14:26:10,350 WARN L151 SmtUtils]: Spent 172ms on a formula simplification. DAG size of input: 82 DAG size of output 81 [2018-04-12 14:26:11,444 WARN L151 SmtUtils]: Spent 279ms on a formula simplification. DAG size of input: 102 DAG size of output 100 [2018-04-12 14:26:12,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:26:12,068 INFO L93 Difference]: Finished difference Result 263 states and 273 transitions. [2018-04-12 14:26:12,068 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 120 states. [2018-04-12 14:26:12,068 INFO L78 Accepts]: Start accepts. Automaton has 71 states. Word has length 90 [2018-04-12 14:26:12,068 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:26:12,069 INFO L225 Difference]: With dead ends: 263 [2018-04-12 14:26:12,069 INFO L226 Difference]: Without dead ends: 188 [2018-04-12 14:26:12,072 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 255 GetRequests, 64 SyntacticMatches, 6 SemanticMatches, 185 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10498 ImplicationChecksByTransitivity, 33.0s TimeCoverageRelationStatistics Valid=2652, Invalid=32129, Unknown=1, NotChecked=0, Total=34782 [2018-04-12 14:26:12,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-04-12 14:26:12,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 165. [2018-04-12 14:26:12,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-04-12 14:26:12,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 170 transitions. [2018-04-12 14:26:12,075 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 170 transitions. Word has length 90 [2018-04-12 14:26:12,075 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:26:12,076 INFO L459 AbstractCegarLoop]: Abstraction has 165 states and 170 transitions. [2018-04-12 14:26:12,076 INFO L460 AbstractCegarLoop]: Interpolant automaton has 71 states. [2018-04-12 14:26:12,076 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 170 transitions. [2018-04-12 14:26:12,076 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-04-12 14:26:12,076 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:26:12,076 INFO L355 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:26:12,076 INFO L408 AbstractCegarLoop]: === Iteration 31 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:26:12,077 INFO L82 PathProgramCache]: Analyzing trace with hash -1178456044, now seen corresponding path program 11 times [2018-04-12 14:26:12,077 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:26:12,077 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:26:12,077 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:26:12,077 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:26:12,077 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:26:12,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:26:12,084 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:26:12,254 INFO L134 CoverageAnalysis]: Checked inductivity of 211 backedges. 75 proven. 73 refuted. 0 times theorem prover too weak. 63 trivial. 0 not checked. [2018-04-12 14:26:12,254 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:26:12,254 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:26:12,259 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-12 14:26:12,335 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2018-04-12 14:26:12,336 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:26:12,338 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:26:12,498 INFO L134 CoverageAnalysis]: Checked inductivity of 211 backedges. 63 proven. 50 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-04-12 14:26:12,515 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:26:12,516 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 15] total 32 [2018-04-12 14:26:12,516 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-12 14:26:12,516 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-12 14:26:12,516 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=176, Invalid=816, Unknown=0, NotChecked=0, Total=992 [2018-04-12 14:26:12,516 INFO L87 Difference]: Start difference. First operand 165 states and 170 transitions. Second operand 32 states. [2018-04-12 14:26:13,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:26:13,092 INFO L93 Difference]: Finished difference Result 173 states and 178 transitions. [2018-04-12 14:26:13,092 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-04-12 14:26:13,092 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 97 [2018-04-12 14:26:13,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:26:13,093 INFO L225 Difference]: With dead ends: 173 [2018-04-12 14:26:13,093 INFO L226 Difference]: Without dead ends: 173 [2018-04-12 14:26:13,094 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 98 SyntacticMatches, 2 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 537 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=671, Invalid=2409, Unknown=0, NotChecked=0, Total=3080 [2018-04-12 14:26:13,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states. [2018-04-12 14:26:13,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 99. [2018-04-12 14:26:13,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-04-12 14:26:13,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 101 transitions. [2018-04-12 14:26:13,095 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 101 transitions. Word has length 97 [2018-04-12 14:26:13,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:26:13,096 INFO L459 AbstractCegarLoop]: Abstraction has 99 states and 101 transitions. [2018-04-12 14:26:13,096 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-12 14:26:13,096 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 101 transitions. [2018-04-12 14:26:13,096 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-04-12 14:26:13,096 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:26:13,096 INFO L355 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:26:13,096 INFO L408 AbstractCegarLoop]: === Iteration 32 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:26:13,096 INFO L82 PathProgramCache]: Analyzing trace with hash 1005586233, now seen corresponding path program 12 times [2018-04-12 14:26:13,096 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:26:13,096 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:26:13,097 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:26:13,097 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:26:13,097 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:26:13,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:26:13,104 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:26:13,229 INFO L134 CoverageAnalysis]: Checked inductivity of 215 backedges. 75 proven. 68 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-04-12 14:26:13,230 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:26:13,230 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:26:13,235 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-12 14:26:13,377 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-04-12 14:26:13,377 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:26:13,379 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:26:13,452 INFO L134 CoverageAnalysis]: Checked inductivity of 215 backedges. 72 proven. 45 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-04-12 14:26:13,470 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:26:13,470 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 14] total 24 [2018-04-12 14:26:13,470 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-04-12 14:26:13,470 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-04-12 14:26:13,470 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=104, Invalid=448, Unknown=0, NotChecked=0, Total=552 [2018-04-12 14:26:13,470 INFO L87 Difference]: Start difference. First operand 99 states and 101 transitions. Second operand 24 states. [2018-04-12 14:26:13,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:26:13,710 INFO L93 Difference]: Finished difference Result 136 states and 138 transitions. [2018-04-12 14:26:13,711 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-04-12 14:26:13,711 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 98 [2018-04-12 14:26:13,711 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:26:13,711 INFO L225 Difference]: With dead ends: 136 [2018-04-12 14:26:13,711 INFO L226 Difference]: Without dead ends: 102 [2018-04-12 14:26:13,711 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 139 GetRequests, 101 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 307 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=268, Invalid=1138, Unknown=0, NotChecked=0, Total=1406 [2018-04-12 14:26:13,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-04-12 14:26:13,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 102. [2018-04-12 14:26:13,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-04-12 14:26:13,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 104 transitions. [2018-04-12 14:26:13,713 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 104 transitions. Word has length 98 [2018-04-12 14:26:13,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:26:13,713 INFO L459 AbstractCegarLoop]: Abstraction has 102 states and 104 transitions. [2018-04-12 14:26:13,713 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-04-12 14:26:13,713 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 104 transitions. [2018-04-12 14:26:13,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-04-12 14:26:13,714 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:26:13,714 INFO L355 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:26:13,714 INFO L408 AbstractCegarLoop]: === Iteration 33 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:26:13,714 INFO L82 PathProgramCache]: Analyzing trace with hash -569778581, now seen corresponding path program 13 times [2018-04-12 14:26:13,714 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:26:13,715 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:26:13,715 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:26:13,715 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:26:13,715 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:26:13,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:26:13,731 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:26:17,195 WARN L151 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 102 DAG size of output 59 [2018-04-12 14:26:17,563 WARN L151 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 116 DAG size of output 51 [2018-04-12 14:26:18,551 WARN L151 SmtUtils]: Spent 288ms on a formula simplification. DAG size of input: 138 DAG size of output 95 [2018-04-12 14:26:19,176 WARN L151 SmtUtils]: Spent 310ms on a formula simplification. DAG size of input: 148 DAG size of output 84 [2018-04-12 14:26:20,099 WARN L151 SmtUtils]: Spent 297ms on a formula simplification. DAG size of input: 144 DAG size of output 79 [2018-04-12 14:26:20,765 INFO L134 CoverageAnalysis]: Checked inductivity of 233 backedges. 86 proven. 92 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-04-12 14:26:20,765 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:26:20,765 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:26:20,771 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:26:20,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:26:20,793 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:26:21,292 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 14:26:21,293 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:26:21,294 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:21,294 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 14:26:21,436 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:21,437 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:21,437 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-12 14:26:21,437 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:26:21,439 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:21,439 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:14, output treesize:8 [2018-04-12 14:26:21,547 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-04-12 14:26:21,548 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-04-12 14:26:21,548 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:26:21,548 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:21,551 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:21,551 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:21, output treesize:17 [2018-04-12 14:26:21,608 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2018-04-12 14:26:21,609 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 1 [2018-04-12 14:26:21,609 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:26:21,609 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:21,611 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:21,612 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:20, output treesize:11 [2018-04-12 14:26:28,821 WARN L148 SmtUtils]: Spent 112ms on a formula simplification that was a NOOP. DAG size: 58 [2018-04-12 14:26:29,371 WARN L148 SmtUtils]: Spent 119ms on a formula simplification that was a NOOP. DAG size: 61 [2018-04-12 14:26:30,249 WARN L148 SmtUtils]: Spent 132ms on a formula simplification that was a NOOP. DAG size: 62 [2018-04-12 14:26:32,018 WARN L151 SmtUtils]: Spent 372ms on a formula simplification. DAG size of input: 76 DAG size of output 65 [2018-04-12 14:26:32,152 INFO L303 Elim1Store]: Index analysis took 132 ms [2018-04-12 14:26:32,152 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 100 treesize of output 104 [2018-04-12 14:26:32,156 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 57 [2018-04-12 14:26:32,162 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 68 [2018-04-12 14:26:32,181 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 70 [2018-04-12 14:26:32,250 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 61 treesize of output 72 [2018-04-12 14:26:32,311 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 74 [2018-04-12 14:26:32,361 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 76 [2018-04-12 14:26:32,425 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 67 treesize of output 87 [2018-04-12 14:26:32,425 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-04-12 14:26:32,457 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:32,488 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:32,521 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:32,552 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:32,581 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:32,615 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:32,685 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 123 treesize of output 122 [2018-04-12 14:26:32,689 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,690 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 49 [2018-04-12 14:26:32,695 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,697 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,699 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,699 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 65 [2018-04-12 14:26:32,704 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,705 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,707 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,709 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,710 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,712 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,712 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 89 [2018-04-12 14:26:32,716 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,717 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,718 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,719 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,721 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,722 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,723 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,724 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,725 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,726 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,727 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 121 [2018-04-12 14:26:32,731 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,731 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,733 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,733 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,734 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,735 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,736 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,737 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,738 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,739 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,740 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,741 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,742 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,743 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,744 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,745 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 161 [2018-04-12 14:26:32,748 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,749 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,750 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,751 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,752 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,753 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,753 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,754 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,755 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,755 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,756 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,757 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,757 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,758 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,759 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,760 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,760 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,761 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,762 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,763 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,764 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:32,764 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 21 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 218 [2018-04-12 14:26:32,765 INFO L267 ElimStorePlain]: Start of recursive call 16: End of recursive call: and 1 xjuncts. [2018-04-12 14:26:32,796 INFO L267 ElimStorePlain]: Start of recursive call 15: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:32,814 INFO L267 ElimStorePlain]: Start of recursive call 14: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:32,837 INFO L267 ElimStorePlain]: Start of recursive call 13: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:32,849 INFO L267 ElimStorePlain]: Start of recursive call 12: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:32,859 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:32,881 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:32,903 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:32,929 INFO L267 ElimStorePlain]: Start of recursive call 1: 9 dim-0 vars, 1 dim-2 vars, End of recursive call: 9 dim-0 vars, and 1 xjuncts. [2018-04-12 14:26:32,929 INFO L202 ElimStorePlain]: Needed 16 recursive calls to eliminate 10 variables, input treesize:161, output treesize:146 [2018-04-12 14:26:33,398 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 244 treesize of output 188 [2018-04-12 14:26:33,419 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 7 select indices, 7 select index equivalence classes, 0 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 1 [2018-04-12 14:26:33,419 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:26:33,431 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,431 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,432 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,432 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,433 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,433 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,434 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,434 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,435 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,435 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,435 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,436 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,436 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,437 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,438 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,438 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,439 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,439 INFO L682 Elim1Store]: detected equality via solver [2018-04-12 14:26:33,439 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,440 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,440 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,441 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,441 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,442 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:26:33,442 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 21 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 93 treesize of output 193 [2018-04-12 14:26:33,443 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-12 14:26:33,460 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:33,471 INFO L267 ElimStorePlain]: Start of recursive call 1: 11 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:26:33,471 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 12 variables, input treesize:248, output treesize:7 [2018-04-12 14:26:33,678 INFO L134 CoverageAnalysis]: Checked inductivity of 233 backedges. 0 proven. 155 refuted. 78 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:26:33,695 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:26:33,695 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 37] total 69 [2018-04-12 14:26:33,695 INFO L442 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-04-12 14:26:33,695 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-04-12 14:26:33,696 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=706, Invalid=3871, Unknown=115, NotChecked=0, Total=4692 [2018-04-12 14:26:33,696 INFO L87 Difference]: Start difference. First operand 102 states and 104 transitions. Second operand 69 states. [2018-04-12 14:26:42,085 WARN L151 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 75 DAG size of output 66 [2018-04-12 14:26:42,438 WARN L151 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 73 DAG size of output 64 [2018-04-12 14:26:43,581 WARN L151 SmtUtils]: Spent 128ms on a formula simplification. DAG size of input: 76 DAG size of output 67 [2018-04-12 14:26:44,479 WARN L151 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 76 DAG size of output 67 [2018-04-12 14:26:45,600 WARN L151 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 79 DAG size of output 70 [2018-04-12 14:26:45,967 WARN L151 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 120 DAG size of output 52 [2018-04-12 14:26:46,732 WARN L151 SmtUtils]: Spent 151ms on a formula simplification. DAG size of input: 79 DAG size of output 70 [2018-04-12 14:26:47,497 WARN L151 SmtUtils]: Spent 124ms on a formula simplification. DAG size of input: 118 DAG size of output 68 [2018-04-12 14:26:48,081 WARN L151 SmtUtils]: Spent 159ms on a formula simplification. DAG size of input: 82 DAG size of output 73 [2018-04-12 14:26:48,435 WARN L151 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 124 DAG size of output 67 [2018-04-12 14:26:48,801 WARN L151 SmtUtils]: Spent 125ms on a formula simplification. DAG size of input: 110 DAG size of output 65 [2018-04-12 14:26:49,432 WARN L151 SmtUtils]: Spent 267ms on a formula simplification. DAG size of input: 81 DAG size of output 72 [2018-04-12 14:26:49,874 WARN L151 SmtUtils]: Spent 138ms on a formula simplification. DAG size of input: 116 DAG size of output 64 [2018-04-12 14:26:50,521 WARN L151 SmtUtils]: Spent 200ms on a formula simplification. DAG size of input: 121 DAG size of output 78 [2018-04-12 14:26:51,285 WARN L151 SmtUtils]: Spent 235ms on a formula simplification. DAG size of input: 84 DAG size of output 75 [2018-04-12 14:26:51,795 WARN L151 SmtUtils]: Spent 187ms on a formula simplification. DAG size of input: 127 DAG size of output 77 [2018-04-12 14:26:52,388 WARN L151 SmtUtils]: Spent 186ms on a formula simplification. DAG size of input: 113 DAG size of output 72 [2018-04-12 14:26:53,017 WARN L151 SmtUtils]: Spent 164ms on a formula simplification. DAG size of input: 85 DAG size of output 76 [2018-04-12 14:26:53,566 WARN L151 SmtUtils]: Spent 153ms on a formula simplification. DAG size of input: 119 DAG size of output 71 [2018-04-12 14:26:54,333 WARN L151 SmtUtils]: Spent 241ms on a formula simplification. DAG size of input: 124 DAG size of output 88 [2018-04-12 14:26:59,626 WARN L151 SmtUtils]: Spent 3469ms on a formula simplification. DAG size of input: 193 DAG size of output 135 [2018-04-12 14:27:00,246 WARN L151 SmtUtils]: Spent 266ms on a formula simplification. DAG size of input: 130 DAG size of output 87 [2018-04-12 14:27:00,964 WARN L151 SmtUtils]: Spent 213ms on a formula simplification. DAG size of input: 116 DAG size of output 79 [2018-04-12 14:27:08,716 WARN L151 SmtUtils]: Spent 4161ms on a formula simplification. DAG size of input: 183 DAG size of output 122 [2018-04-12 14:27:09,549 WARN L151 SmtUtils]: Spent 267ms on a formula simplification. DAG size of input: 122 DAG size of output 78 [2018-04-12 14:27:11,560 WARN L151 SmtUtils]: Spent 317ms on a formula simplification. DAG size of input: 109 DAG size of output 98 [2018-04-12 14:27:13,902 WARN L151 SmtUtils]: Spent 261ms on a formula simplification. DAG size of input: 115 DAG size of output 97 [2018-04-12 14:27:14,869 WARN L151 SmtUtils]: Spent 288ms on a formula simplification. DAG size of input: 98 DAG size of output 86 [2018-04-12 14:27:18,793 WARN L151 SmtUtils]: Spent 2579ms on a formula simplification. DAG size of input: 120 DAG size of output 76 [2018-04-12 14:27:19,890 WARN L151 SmtUtils]: Spent 282ms on a formula simplification. DAG size of input: 104 DAG size of output 85 [2018-04-12 14:27:22,152 WARN L151 SmtUtils]: Spent 131ms on a formula simplification. DAG size of input: 118 DAG size of output 99 [2018-04-12 14:27:23,050 WARN L151 SmtUtils]: Spent 424ms on a formula simplification. DAG size of input: 121 DAG size of output 102 [2018-04-12 14:27:24,368 WARN L151 SmtUtils]: Spent 418ms on a formula simplification. DAG size of input: 127 DAG size of output 102 [2018-04-12 14:27:26,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:27:26,094 INFO L93 Difference]: Finished difference Result 243 states and 249 transitions. [2018-04-12 14:27:26,094 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 105 states. [2018-04-12 14:27:26,094 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 101 [2018-04-12 14:27:26,094 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:27:26,095 INFO L225 Difference]: With dead ends: 243 [2018-04-12 14:27:26,095 INFO L226 Difference]: Without dead ends: 195 [2018-04-12 14:27:26,097 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 252 GetRequests, 74 SyntacticMatches, 9 SemanticMatches, 169 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8787 ImplicationChecksByTransitivity, 57.5s TimeCoverageRelationStatistics Valid=3782, Invalid=24802, Unknown=486, NotChecked=0, Total=29070 [2018-04-12 14:27:26,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states. [2018-04-12 14:27:26,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 184. [2018-04-12 14:27:26,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 184 states. [2018-04-12 14:27:26,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184 states to 184 states and 189 transitions. [2018-04-12 14:27:26,099 INFO L78 Accepts]: Start accepts. Automaton has 184 states and 189 transitions. Word has length 101 [2018-04-12 14:27:26,099 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:27:26,099 INFO L459 AbstractCegarLoop]: Abstraction has 184 states and 189 transitions. [2018-04-12 14:27:26,099 INFO L460 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-04-12 14:27:26,100 INFO L276 IsEmpty]: Start isEmpty. Operand 184 states and 189 transitions. [2018-04-12 14:27:26,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-04-12 14:27:26,100 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:27:26,100 INFO L355 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:27:26,100 INFO L408 AbstractCegarLoop]: === Iteration 34 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:27:26,100 INFO L82 PathProgramCache]: Analyzing trace with hash 101029328, now seen corresponding path program 14 times [2018-04-12 14:27:26,100 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:27:26,100 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:27:26,101 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:27:26,101 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 14:27:26,101 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:27:26,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:27:26,108 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:27:26,234 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 84 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-04-12 14:27:26,235 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:27:26,235 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:27:26,242 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 14:27:26,266 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 14:27:26,266 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:27:26,268 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:27:26,343 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 84 proven. 98 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-04-12 14:27:26,361 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:27:26,361 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 18] total 27 [2018-04-12 14:27:26,361 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-04-12 14:27:26,361 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-04-12 14:27:26,361 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=234, Invalid=468, Unknown=0, NotChecked=0, Total=702 [2018-04-12 14:27:26,362 INFO L87 Difference]: Start difference. First operand 184 states and 189 transitions. Second operand 27 states. [2018-04-12 14:27:26,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:27:26,618 INFO L93 Difference]: Finished difference Result 216 states and 222 transitions. [2018-04-12 14:27:26,618 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-04-12 14:27:26,618 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 108 [2018-04-12 14:27:26,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:27:26,619 INFO L225 Difference]: With dead ends: 216 [2018-04-12 14:27:26,619 INFO L226 Difference]: Without dead ends: 216 [2018-04-12 14:27:26,619 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 100 SyntacticMatches, 1 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 309 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=443, Invalid=889, Unknown=0, NotChecked=0, Total=1332 [2018-04-12 14:27:26,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-04-12 14:27:26,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 110. [2018-04-12 14:27:26,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-04-12 14:27:26,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 112 transitions. [2018-04-12 14:27:26,621 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 112 transitions. Word has length 108 [2018-04-12 14:27:26,621 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:27:26,621 INFO L459 AbstractCegarLoop]: Abstraction has 110 states and 112 transitions. [2018-04-12 14:27:26,621 INFO L460 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-04-12 14:27:26,621 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 112 transitions. [2018-04-12 14:27:26,621 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-04-12 14:27:26,621 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:27:26,622 INFO L355 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 7, 7, 7, 7, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:27:26,622 INFO L408 AbstractCegarLoop]: === Iteration 35 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:27:26,622 INFO L82 PathProgramCache]: Analyzing trace with hash -259769461, now seen corresponding path program 15 times [2018-04-12 14:27:26,622 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:27:26,622 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:27:26,622 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:27:26,622 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:27:26,622 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:27:26,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:27:26,629 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:27:26,766 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 101 proven. 90 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-04-12 14:27:26,766 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:27:26,766 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:27:26,771 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 14:27:26,828 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-04-12 14:27:26,828 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:27:26,830 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:27:26,914 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 98 proven. 63 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-04-12 14:27:26,933 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:27:26,933 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 16] total 27 [2018-04-12 14:27:26,934 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-04-12 14:27:26,934 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-04-12 14:27:26,934 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=572, Unknown=0, NotChecked=0, Total=702 [2018-04-12 14:27:26,934 INFO L87 Difference]: Start difference. First operand 110 states and 112 transitions. Second operand 27 states. [2018-04-12 14:27:27,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:27:27,217 INFO L93 Difference]: Finished difference Result 151 states and 153 transitions. [2018-04-12 14:27:27,217 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-04-12 14:27:27,217 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 109 [2018-04-12 14:27:27,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:27:27,217 INFO L225 Difference]: With dead ends: 151 [2018-04-12 14:27:27,217 INFO L226 Difference]: Without dead ends: 113 [2018-04-12 14:27:27,217 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 155 GetRequests, 112 SyntacticMatches, 2 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 410 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=337, Invalid=1469, Unknown=0, NotChecked=0, Total=1806 [2018-04-12 14:27:27,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-04-12 14:27:27,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-04-12 14:27:27,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-04-12 14:27:27,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 115 transitions. [2018-04-12 14:27:27,219 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 115 transitions. Word has length 109 [2018-04-12 14:27:27,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:27:27,219 INFO L459 AbstractCegarLoop]: Abstraction has 113 states and 115 transitions. [2018-04-12 14:27:27,219 INFO L460 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-04-12 14:27:27,219 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 115 transitions. [2018-04-12 14:27:27,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-04-12 14:27:27,219 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:27:27,219 INFO L355 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:27:27,219 INFO L408 AbstractCegarLoop]: === Iteration 36 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:27:27,219 INFO L82 PathProgramCache]: Analyzing trace with hash -413118183, now seen corresponding path program 16 times [2018-04-12 14:27:27,219 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:27:27,220 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:27:27,220 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:27:27,220 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:27:27,220 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:27:27,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:27:27,230 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:27:41,523 WARN L151 SmtUtils]: Spent 111ms on a formula simplification. DAG size of input: 72 DAG size of output 63 [2018-04-12 14:27:41,805 WARN L151 SmtUtils]: Spent 139ms on a formula simplification. DAG size of input: 79 DAG size of output 62 [2018-04-12 14:27:42,221 WARN L151 SmtUtils]: Spent 197ms on a formula simplification. DAG size of input: 91 DAG size of output 74 [2018-04-12 14:27:42,665 WARN L151 SmtUtils]: Spent 207ms on a formula simplification. DAG size of input: 99 DAG size of output 69 [2018-04-12 14:27:44,001 WARN L151 SmtUtils]: Spent 302ms on a formula simplification. DAG size of input: 114 DAG size of output 84 [2018-04-12 14:27:44,722 WARN L151 SmtUtils]: Spent 323ms on a formula simplification. DAG size of input: 123 DAG size of output 76 [2018-04-12 14:27:46,755 WARN L151 SmtUtils]: Spent 504ms on a formula simplification. DAG size of input: 141 DAG size of output 94 [2018-04-12 14:27:47,838 WARN L151 SmtUtils]: Spent 392ms on a formula simplification. DAG size of input: 150 DAG size of output 88 [2018-04-12 14:27:49,996 WARN L151 SmtUtils]: Spent 687ms on a formula simplification. DAG size of input: 168 DAG size of output 114 [2018-04-12 14:27:51,606 WARN L151 SmtUtils]: Spent 738ms on a formula simplification. DAG size of input: 178 DAG size of output 101 [2018-04-12 14:27:53,896 WARN L151 SmtUtils]: Spent 700ms on a formula simplification. DAG size of input: 173 DAG size of output 95 [2018-04-12 14:27:55,237 INFO L134 CoverageAnalysis]: Checked inductivity of 310 backedges. 91 proven. 219 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 14:27:55,237 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:27:55,237 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:27:55,242 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-12 14:27:55,263 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-12 14:27:55,263 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:27:55,265 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:27:55,267 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 14:27:55,267 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:27:55,268 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:27:55,268 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-12 14:27:55,516 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:27:55,516 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:27:55,516 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-12 14:27:55,517 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:27:55,517 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:27:55,518 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:11, output treesize:4 [2018-04-12 14:27:55,766 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-04-12 14:27:55,766 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-04-12 14:27:55,767 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:27:55,767 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:27:55,769 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:27:55,769 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:18, output treesize:14 [2018-04-12 14:27:55,900 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2018-04-12 14:27:55,901 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 1 [2018-04-12 14:27:55,902 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:27:55,902 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:27:55,905 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:27:55,905 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:17, output treesize:8 [2018-04-12 14:28:11,568 WARN L151 SmtUtils]: Spent 206ms on a formula simplification. DAG size of input: 69 DAG size of output 57 [2018-04-12 14:28:11,593 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 94 treesize of output 98 [2018-04-12 14:28:11,598 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 46 [2018-04-12 14:28:11,603 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,603 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 54 [2018-04-12 14:28:11,609 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,611 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,614 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,614 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 70 [2018-04-12 14:28:11,620 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,623 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,625 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,627 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,630 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,631 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,632 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 94 [2018-04-12 14:28:11,637 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,640 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,642 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,643 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,646 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,649 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,651 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,653 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,656 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,658 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,659 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 126 [2018-04-12 14:28:11,665 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,668 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,669 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,673 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,675 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,677 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,679 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,682 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,685 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,687 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,690 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,692 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,695 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,697 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,699 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,700 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 166 [2018-04-12 14:28:11,707 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,710 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,712 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,714 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,716 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,718 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,720 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,723 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,724 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,727 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,729 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,730 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,733 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,735 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,737 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,740 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,742 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,745 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,748 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,750 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,752 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,753 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 21 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 214 [2018-04-12 14:28:11,759 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,760 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,762 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,764 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,767 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,769 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,771 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,773 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,776 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,778 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,780 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,784 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,785 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,787 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,790 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,792 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,794 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,796 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,798 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,801 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,804 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,805 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,807 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,810 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,812 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,815 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,816 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,818 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:11,819 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 28 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 281 [2018-04-12 14:28:11,819 INFO L267 ElimStorePlain]: Start of recursive call 10: End of recursive call: and 1 xjuncts. [2018-04-12 14:28:11,939 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,026 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,096 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,156 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,205 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,258 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,299 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,371 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 121 treesize of output 120 [2018-04-12 14:28:12,374 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,374 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 54 [2018-04-12 14:28:12,376 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,377 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,377 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,378 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 70 [2018-04-12 14:28:12,384 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,385 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,386 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,387 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,390 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,393 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,393 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 94 [2018-04-12 14:28:12,398 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,399 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,400 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,402 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,404 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,405 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,407 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,408 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,409 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,410 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,410 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 126 [2018-04-12 14:28:12,415 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,417 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,418 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,419 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,420 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,421 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,422 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,423 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,424 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,425 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,427 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,427 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,428 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,429 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,430 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,431 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 166 [2018-04-12 14:28:12,435 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,436 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,437 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,447 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,448 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,449 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,450 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,451 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,452 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,453 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,454 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,454 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,455 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,456 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,457 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,457 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,458 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,459 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,460 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,460 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,461 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,462 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 21 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 214 [2018-04-12 14:28:12,466 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,466 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,467 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,468 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,468 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,469 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,469 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,470 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,471 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,471 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,472 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,472 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,474 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,475 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,475 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,476 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,477 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,478 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,478 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,479 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,480 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,480 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,481 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,482 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,482 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,483 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,484 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,484 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:12,485 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 28 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 281 [2018-04-12 14:28:12,485 INFO L267 ElimStorePlain]: Start of recursive call 18: End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,528 INFO L267 ElimStorePlain]: Start of recursive call 17: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,551 INFO L267 ElimStorePlain]: Start of recursive call 16: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,569 INFO L267 ElimStorePlain]: Start of recursive call 15: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,584 INFO L267 ElimStorePlain]: Start of recursive call 14: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,596 INFO L267 ElimStorePlain]: Start of recursive call 13: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,606 INFO L267 ElimStorePlain]: Start of recursive call 12: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,628 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,648 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:12,671 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-12 14:28:12,672 INFO L202 ElimStorePlain]: Needed 18 recursive calls to eliminate 3 variables, input treesize:147, output treesize:151 [2018-04-12 14:28:13,384 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 267 treesize of output 201 [2018-04-12 14:28:13,387 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,387 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,388 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,388 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,389 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,389 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,390 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,390 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,391 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,391 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,391 INFO L682 Elim1Store]: detected equality via solver [2018-04-12 14:28:13,392 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,392 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,393 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,394 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,394 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,395 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,395 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,395 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,396 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,396 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,397 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,397 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,398 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,398 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,398 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,399 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,399 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,400 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,400 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,401 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 9 select indices, 9 select index equivalence classes, 28 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 197 treesize of output 341 [2018-04-12 14:28:13,401 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:28:13,447 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,447 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,448 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,448 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,449 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,449 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,449 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,450 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,450 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,451 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,451 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,451 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,452 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,452 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,453 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,453 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,454 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,454 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,455 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,455 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,455 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,456 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,456 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,457 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,457 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,457 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,458 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,458 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:28:13,459 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 28 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 104 treesize of output 224 [2018-04-12 14:28:13,459 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-12 14:28:13,479 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:28:13,482 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-12 14:28:13,482 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 5 variables, input treesize:271, output treesize:14 [2018-04-12 14:28:13,705 INFO L134 CoverageAnalysis]: Checked inductivity of 310 backedges. 0 proven. 226 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-04-12 14:28:13,722 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:28:13,722 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44] total 86 [2018-04-12 14:28:13,723 INFO L442 AbstractCegarLoop]: Interpolant automaton has 86 states [2018-04-12 14:28:13,723 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2018-04-12 14:28:13,723 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=303, Invalid=7007, Unknown=0, NotChecked=0, Total=7310 [2018-04-12 14:28:13,723 INFO L87 Difference]: Start difference. First operand 113 states and 115 transitions. Second operand 86 states. [2018-04-12 14:28:14,560 WARN L151 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 212 DAG size of output 42 [2018-04-12 14:28:28,063 WARN L151 SmtUtils]: Spent 105ms on a formula simplification. DAG size of input: 152 DAG size of output 45 [2018-04-12 14:28:32,194 WARN L151 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 158 DAG size of output 52 [2018-04-12 14:28:33,825 WARN L151 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 147 DAG size of output 55 [2018-04-12 14:28:39,644 WARN L151 SmtUtils]: Spent 126ms on a formula simplification. DAG size of input: 161 DAG size of output 54 [2018-04-12 14:28:41,064 WARN L151 SmtUtils]: Spent 222ms on a formula simplification. DAG size of input: 173 DAG size of output 59 [2018-04-12 14:28:42,597 WARN L151 SmtUtils]: Spent 252ms on a formula simplification. DAG size of input: 160 DAG size of output 64 [2018-04-12 14:28:44,055 WARN L151 SmtUtils]: Spent 281ms on a formula simplification. DAG size of input: 169 DAG size of output 62 [2018-04-12 14:28:45,938 WARN L151 SmtUtils]: Spent 210ms on a formula simplification. DAG size of input: 168 DAG size of output 61 [2018-04-12 14:28:48,586 WARN L151 SmtUtils]: Spent 652ms on a formula simplification. DAG size of input: 297 DAG size of output 62 [2018-04-12 14:28:50,548 WARN L151 SmtUtils]: Spent 297ms on a formula simplification. DAG size of input: 164 DAG size of output 64 [2018-04-12 14:28:51,328 WARN L151 SmtUtils]: Spent 161ms on a formula simplification. DAG size of input: 129 DAG size of output 55 [2018-04-12 14:28:53,683 WARN L151 SmtUtils]: Spent 703ms on a formula simplification. DAG size of input: 298 DAG size of output 65 [2018-04-12 14:28:57,048 WARN L151 SmtUtils]: Spent 913ms on a formula simplification. DAG size of input: 292 DAG size of output 64 [2018-04-12 14:28:57,927 WARN L151 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 119 DAG size of output 60 [2018-04-12 14:29:00,818 WARN L151 SmtUtils]: Spent 658ms on a formula simplification. DAG size of input: 284 DAG size of output 63 [2018-04-12 14:29:05,472 WARN L151 SmtUtils]: Spent 1379ms on a formula simplification. DAG size of input: 293 DAG size of output 67 [2018-04-12 14:29:06,766 WARN L151 SmtUtils]: Spent 174ms on a formula simplification. DAG size of input: 133 DAG size of output 67 [2018-04-12 14:29:10,352 WARN L151 SmtUtils]: Spent 1208ms on a formula simplification. DAG size of input: 285 DAG size of output 66 [2018-04-12 14:29:14,910 WARN L151 SmtUtils]: Spent 1150ms on a formula simplification. DAG size of input: 279 DAG size of output 66 [2018-04-12 14:29:16,989 WARN L151 SmtUtils]: Spent 787ms on a formula simplification. DAG size of input: 232 DAG size of output 151 [2018-04-12 14:29:20,017 WARN L151 SmtUtils]: Spent 799ms on a formula simplification. DAG size of input: 268 DAG size of output 65 [2018-04-12 14:29:23,658 WARN L151 SmtUtils]: Spent 1040ms on a formula simplification. DAG size of input: 280 DAG size of output 69 [2018-04-12 14:29:26,424 WARN L151 SmtUtils]: Spent 1435ms on a formula simplification. DAG size of input: 264 DAG size of output 160 [2018-04-12 14:29:29,379 WARN L151 SmtUtils]: Spent 1042ms on a formula simplification. DAG size of input: 269 DAG size of output 68 [2018-04-12 14:29:32,833 WARN L151 SmtUtils]: Spent 678ms on a formula simplification. DAG size of input: 263 DAG size of output 67 [2018-04-12 14:29:34,961 WARN L151 SmtUtils]: Spent 871ms on a formula simplification. DAG size of input: 218 DAG size of output 157 [2018-04-12 14:29:38,978 WARN L151 SmtUtils]: Spent 981ms on a formula simplification. DAG size of input: 248 DAG size of output 68 [2018-04-12 14:29:43,310 WARN L151 SmtUtils]: Spent 1201ms on a formula simplification. DAG size of input: 264 DAG size of output 70 [2018-04-12 14:29:47,704 WARN L151 SmtUtils]: Spent 1953ms on a formula simplification. DAG size of input: 250 DAG size of output 167 [2018-04-12 14:29:51,519 WARN L151 SmtUtils]: Spent 795ms on a formula simplification. DAG size of input: 249 DAG size of output 71 [2018-04-12 14:29:56,167 WARN L151 SmtUtils]: Spent 980ms on a formula simplification. DAG size of input: 243 DAG size of output 70 [2018-04-12 14:29:58,193 WARN L151 SmtUtils]: Spent 851ms on a formula simplification. DAG size of input: 198 DAG size of output 155 [2018-04-12 14:29:59,614 WARN L151 SmtUtils]: Spent 205ms on a formula simplification. DAG size of input: 156 DAG size of output 70 [2018-04-12 14:30:05,930 WARN L151 SmtUtils]: Spent 1602ms on a formula simplification. DAG size of input: 244 DAG size of output 73 [2018-04-12 14:30:10,256 WARN L151 SmtUtils]: Spent 2109ms on a formula simplification. DAG size of input: 230 DAG size of output 166 [2018-04-12 14:30:15,308 WARN L151 SmtUtils]: Spent 2072ms on a formula simplification. DAG size of input: 208 DAG size of output 153 [2018-04-12 14:30:18,378 WARN L151 SmtUtils]: Spent 957ms on a formula simplification. DAG size of input: 151 DAG size of output 81 [2018-04-12 14:30:23,119 WARN L151 SmtUtils]: Spent 2960ms on a formula simplification. DAG size of input: 175 DAG size of output 147 [2018-04-12 14:30:28,911 WARN L151 SmtUtils]: Spent 1992ms on a formula simplification. DAG size of input: 194 DAG size of output 131 [2018-04-12 14:30:34,596 WARN L151 SmtUtils]: Spent 2282ms on a formula simplification. DAG size of input: 229 DAG size of output 138 [2018-04-12 14:30:49,363 WARN L151 SmtUtils]: Spent 9944ms on a formula simplification. DAG size of input: 198 DAG size of output 160 [2018-04-12 14:30:53,573 WARN L151 SmtUtils]: Spent 1948ms on a formula simplification. DAG size of input: 207 DAG size of output 137 [2018-04-12 14:31:07,475 WARN L151 SmtUtils]: Spent 5850ms on a formula simplification. DAG size of input: 151 DAG size of output 139 [2018-04-12 14:31:10,556 WARN L151 SmtUtils]: Spent 1107ms on a formula simplification. DAG size of input: 147 DAG size of output 145 [2018-04-12 14:31:24,192 WARN L151 SmtUtils]: Spent 5448ms on a formula simplification. DAG size of input: 184 DAG size of output 139 [2018-04-12 14:31:29,773 WARN L151 SmtUtils]: Spent 695ms on a formula simplification. DAG size of input: 124 DAG size of output 123 [2018-04-12 14:31:37,487 WARN L151 SmtUtils]: Spent 805ms on a formula simplification. DAG size of input: 110 DAG size of output 109 [2018-04-12 14:31:43,925 WARN L151 SmtUtils]: Spent 1448ms on a formula simplification. DAG size of input: 140 DAG size of output 134 [2018-04-12 14:31:45,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:31:45,585 INFO L93 Difference]: Finished difference Result 264 states and 271 transitions. [2018-04-12 14:31:45,585 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 128 states. [2018-04-12 14:31:45,585 INFO L78 Accepts]: Start accepts. Automaton has 86 states. Word has length 112 [2018-04-12 14:31:45,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:31:45,586 INFO L225 Difference]: With dead ends: 264 [2018-04-12 14:31:45,586 INFO L226 Difference]: Without dead ends: 179 [2018-04-12 14:31:45,587 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 299 GetRequests, 80 SyntacticMatches, 10 SemanticMatches, 209 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12286 ImplicationChecksByTransitivity, 222.3s TimeCoverageRelationStatistics Valid=2997, Invalid=41312, Unknown=1, NotChecked=0, Total=44310 [2018-04-12 14:31:45,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-04-12 14:31:45,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 125. [2018-04-12 14:31:45,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-04-12 14:31:45,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 128 transitions. [2018-04-12 14:31:45,588 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 128 transitions. Word has length 112 [2018-04-12 14:31:45,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:31:45,588 INFO L459 AbstractCegarLoop]: Abstraction has 125 states and 128 transitions. [2018-04-12 14:31:45,588 INFO L460 AbstractCegarLoop]: Interpolant automaton has 86 states. [2018-04-12 14:31:45,588 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 128 transitions. [2018-04-12 14:31:45,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-04-12 14:31:45,589 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:31:45,589 INFO L355 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:31:45,589 INFO L408 AbstractCegarLoop]: === Iteration 37 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:31:45,589 INFO L82 PathProgramCache]: Analyzing trace with hash -818994270, now seen corresponding path program 17 times [2018-04-12 14:31:45,589 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:31:45,589 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:31:45,590 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:31:45,590 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:31:45,590 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:31:45,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:31:45,599 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:31:45,732 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 108 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-04-12 14:31:45,732 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:31:45,733 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:31:45,738 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-12 14:31:46,114 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2018-04-12 14:31:46,114 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:31:46,117 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:31:46,259 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 108 proven. 128 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2018-04-12 14:31:46,277 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:31:46,278 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 20] total 30 [2018-04-12 14:31:46,278 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-04-12 14:31:46,278 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-04-12 14:31:46,278 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=290, Invalid=580, Unknown=0, NotChecked=0, Total=870 [2018-04-12 14:31:46,278 INFO L87 Difference]: Start difference. First operand 125 states and 128 transitions. Second operand 30 states. [2018-04-12 14:31:46,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 14:31:46,452 INFO L93 Difference]: Finished difference Result 134 states and 137 transitions. [2018-04-12 14:31:46,452 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-04-12 14:31:46,452 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 119 [2018-04-12 14:31:46,453 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 14:31:46,453 INFO L225 Difference]: With dead ends: 134 [2018-04-12 14:31:46,453 INFO L226 Difference]: Without dead ends: 134 [2018-04-12 14:31:46,453 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 141 GetRequests, 110 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 247 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=323, Invalid=669, Unknown=0, NotChecked=0, Total=992 [2018-04-12 14:31:46,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-04-12 14:31:46,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 124. [2018-04-12 14:31:46,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-04-12 14:31:46,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 126 transitions. [2018-04-12 14:31:46,455 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 126 transitions. Word has length 119 [2018-04-12 14:31:46,455 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 14:31:46,455 INFO L459 AbstractCegarLoop]: Abstraction has 124 states and 126 transitions. [2018-04-12 14:31:46,455 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-04-12 14:31:46,455 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 126 transitions. [2018-04-12 14:31:46,456 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-04-12 14:31:46,456 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 14:31:46,456 INFO L355 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 14:31:46,456 INFO L408 AbstractCegarLoop]: === Iteration 38 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-12 14:31:46,456 INFO L82 PathProgramCache]: Analyzing trace with hash 1218960619, now seen corresponding path program 18 times [2018-04-12 14:31:46,456 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 14:31:46,456 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 14:31:46,456 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:31:46,456 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 14:31:46,457 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 14:31:46,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 14:31:46,470 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 14:35:08,419 WARN L151 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 89 DAG size of output 46 [2018-04-12 14:35:08,774 WARN L151 SmtUtils]: Spent 138ms on a formula simplification. DAG size of input: 111 DAG size of output 51 [2018-04-12 14:35:09,785 WARN L151 SmtUtils]: Spent 202ms on a formula simplification. DAG size of input: 113 DAG size of output 53 [2018-04-12 14:35:10,429 WARN L151 SmtUtils]: Spent 225ms on a formula simplification. DAG size of input: 139 DAG size of output 58 [2018-04-12 14:35:12,377 WARN L151 SmtUtils]: Spent 349ms on a formula simplification. DAG size of input: 141 DAG size of output 60 [2018-04-12 14:35:13,813 WARN L151 SmtUtils]: Spent 396ms on a formula simplification. DAG size of input: 176 DAG size of output 65 [2018-04-12 14:35:17,382 WARN L151 SmtUtils]: Spent 722ms on a formula simplification. DAG size of input: 182 DAG size of output 93 [2018-04-12 14:35:20,574 WARN L151 SmtUtils]: Spent 621ms on a formula simplification. DAG size of input: 216 DAG size of output 98 [2018-04-12 14:35:23,214 WARN L151 SmtUtils]: Spent 611ms on a formula simplification. DAG size of input: 212 DAG size of output 93 [2018-04-12 14:35:24,069 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 139 proven. 154 refuted. 0 times theorem prover too weak. 105 trivial. 0 not checked. [2018-04-12 14:35:24,070 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 14:35:24,070 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 14:35:24,075 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-12 14:35:24,213 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2018-04-12 14:35:24,213 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 14:35:24,217 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 14:35:24,219 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 14:35:24,219 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:35:24,220 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:35:24,220 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-12 14:35:24,406 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:35:24,407 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:35:24,407 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-12 14:35:24,407 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 14:35:24,409 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:35:24,409 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:14, output treesize:8 [2018-04-12 14:35:24,594 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-04-12 14:35:24,595 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 14:35:24,595 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:35:24,596 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:35:24,599 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:35:24,599 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:19, output treesize:15 [2018-04-12 14:35:24,700 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 5 [2018-04-12 14:35:24,701 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-04-12 14:35:24,701 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:35:24,702 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:35:24,704 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:35:24,704 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:18, output treesize:11 [2018-04-12 14:35:41,569 WARN L148 SmtUtils]: Spent 111ms on a formula simplification that was a NOOP. DAG size: 90 [2018-04-12 14:35:44,201 WARN L148 SmtUtils]: Spent 314ms on a formula simplification that was a NOOP. DAG size: 94 [2018-04-12 14:35:47,072 WARN L148 SmtUtils]: Spent 163ms on a formula simplification that was a NOOP. DAG size: 95 [2018-04-12 14:35:50,444 WARN L148 SmtUtils]: Spent 195ms on a formula simplification that was a NOOP. DAG size: 97 [2018-04-12 14:35:54,004 WARN L148 SmtUtils]: Spent 200ms on a formula simplification that was a NOOP. DAG size: 98 [2018-04-12 14:35:57,279 WARN L148 SmtUtils]: Spent 315ms on a formula simplification that was a NOOP. DAG size: 100 [2018-04-12 14:36:01,745 WARN L148 SmtUtils]: Spent 435ms on a formula simplification that was a NOOP. DAG size: 102 [2018-04-12 14:36:06,692 WARN L148 SmtUtils]: Spent 185ms on a formula simplification that was a NOOP. DAG size: 104 [2018-04-12 14:36:14,605 WARN L148 SmtUtils]: Spent 283ms on a formula simplification that was a NOOP. DAG size: 105 [2018-04-12 14:36:18,123 WARN L151 SmtUtils]: Spent 3511ms on a formula simplification. DAG size of input: 118 DAG size of output 104 [2018-04-12 14:36:18,569 INFO L303 Elim1Store]: Index analysis took 445 ms [2018-04-12 14:36:18,570 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 138 treesize of output 142 [2018-04-12 14:36:18,580 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 71 [2018-04-12 14:36:18,588 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,588 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 85 [2018-04-12 14:36:18,611 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,620 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,625 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,626 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 73 treesize of output 111 [2018-04-12 14:36:18,646 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,654 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,670 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,679 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,688 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,697 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,697 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 75 treesize of output 149 [2018-04-12 14:36:18,711 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,715 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,718 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,731 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,734 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,746 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,762 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 77 treesize of output 158 [2018-04-12 14:36:18,772 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,783 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,787 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,804 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,808 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,844 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,858 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 6 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 160 [2018-04-12 14:36:18,891 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,898 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:18,928 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,031 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,065 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,105 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,161 INFO L303 Elim1Store]: Index analysis took 300 ms [2018-04-12 14:36:19,161 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 6 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 81 treesize of output 162 [2018-04-12 14:36:19,221 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,229 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,238 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,256 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,268 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,312 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,337 INFO L303 Elim1Store]: Index analysis took 174 ms [2018-04-12 14:36:19,337 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 6 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 164 [2018-04-12 14:36:19,500 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,506 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,510 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,577 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,581 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,608 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:19,657 INFO L303 Elim1Store]: Index analysis took 318 ms [2018-04-12 14:36:19,658 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 6 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 85 treesize of output 179 [2018-04-12 14:36:19,658 INFO L267 ElimStorePlain]: Start of recursive call 11: End of recursive call: and 1 xjuncts. [2018-04-12 14:36:19,765 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:19,867 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:19,974 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:20,068 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:20,174 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:20,262 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:20,345 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:20,422 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:20,583 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 169 treesize of output 168 [2018-04-12 14:36:20,594 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,595 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 71 [2018-04-12 14:36:20,606 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,609 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,610 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 67 treesize of output 89 [2018-04-12 14:36:20,620 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,624 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,627 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,629 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,634 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,635 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 7 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 119 [2018-04-12 14:36:20,639 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,640 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,641 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,641 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,642 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,643 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,644 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,645 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,645 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,646 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 12 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 161 [2018-04-12 14:36:20,655 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,658 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,662 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,666 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,669 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,672 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,674 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,677 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,679 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,681 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,684 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,685 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,687 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,689 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,689 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 18 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 73 treesize of output 215 [2018-04-12 14:36:20,699 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,701 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,704 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,707 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,716 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,718 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,722 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,725 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,732 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,734 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,736 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,742 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,745 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,751 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,759 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,759 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 20 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 75 treesize of output 237 [2018-04-12 14:36:20,768 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,769 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,771 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,772 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,775 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,788 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,791 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,793 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,795 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,797 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,799 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,802 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,804 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,806 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,809 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,810 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,814 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,818 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,819 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 24 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 77 treesize of output 271 [2018-04-12 14:36:20,830 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,831 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,832 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,834 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,835 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,836 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,840 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,846 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,847 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,851 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,852 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,853 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,855 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,863 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,864 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,865 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,866 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,868 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,871 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,872 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,876 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,880 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:20,880 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 29 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 328 [2018-04-12 14:36:20,881 INFO L267 ElimStorePlain]: Start of recursive call 20: End of recursive call: and 1 xjuncts. [2018-04-12 14:36:20,926 INFO L267 ElimStorePlain]: Start of recursive call 19: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:20,960 INFO L267 ElimStorePlain]: Start of recursive call 18: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:20,992 INFO L267 ElimStorePlain]: Start of recursive call 17: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:21,017 INFO L267 ElimStorePlain]: Start of recursive call 16: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:21,037 INFO L267 ElimStorePlain]: Start of recursive call 15: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:21,054 INFO L267 ElimStorePlain]: Start of recursive call 14: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:21,070 INFO L267 ElimStorePlain]: Start of recursive call 13: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:21,102 INFO L267 ElimStorePlain]: Start of recursive call 12: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:21,132 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:21,189 INFO L267 ElimStorePlain]: Start of recursive call 1: 16 dim-0 vars, 1 dim-2 vars, End of recursive call: 16 dim-0 vars, and 1 xjuncts. [2018-04-12 14:36:21,190 INFO L202 ElimStorePlain]: Needed 20 recursive calls to eliminate 17 variables, input treesize:265, output treesize:249 [2018-04-12 14:36:26,126 WARN L148 SmtUtils]: Spent 2023ms on a formula simplification that was a NOOP. DAG size: 123 [2018-04-12 14:36:28,772 WARN L148 SmtUtils]: Spent 2025ms on a formula simplification that was a NOOP. DAG size: 127 [2018-04-12 14:36:28,780 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 304 treesize of output 228 [2018-04-12 14:36:28,786 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,787 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,788 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,789 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,789 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,790 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,791 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,792 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,792 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,794 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,795 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,797 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,799 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,801 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,804 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,805 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,806 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,808 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,809 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,809 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,811 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,813 INFO L682 Elim1Store]: detected equality via solver [2018-04-12 14:36:28,815 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,817 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,820 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,820 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,821 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,823 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,824 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,825 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,826 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,826 INFO L682 Elim1Store]: detected equality via solver [2018-04-12 14:36:28,828 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,830 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 11 select indices, 11 select index equivalence classes, 23 disjoint index pairs (out of 55 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 224 treesize of output 513 [2018-04-12 14:36:28,830 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 14:36:28,931 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,932 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,932 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,937 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,938 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,939 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 14:36:28,942 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 9 select indices, 9 select index equivalence classes, 6 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 170 treesize of output 89 [2018-04-12 14:36:28,942 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-12 14:36:28,952 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:28,966 INFO L267 ElimStorePlain]: Start of recursive call 1: 17 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 14:36:28,967 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 18 variables, input treesize:347, output treesize:10 [2018-04-12 14:36:29,555 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 144 refuted. 146 times theorem prover too weak. 108 trivial. 0 not checked. [2018-04-12 14:36:29,573 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 14:36:29,573 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 44] total 82 [2018-04-12 14:36:29,573 INFO L442 AbstractCegarLoop]: Interpolant automaton has 82 states [2018-04-12 14:36:29,573 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2018-04-12 14:36:29,574 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=805, Invalid=5406, Unknown=431, NotChecked=0, Total=6642 [2018-04-12 14:36:29,574 INFO L87 Difference]: Start difference. First operand 124 states and 126 transitions. Second operand 82 states. [2018-04-12 14:36:29,954 WARN L151 SmtUtils]: Spent 124ms on a formula simplification. DAG size of input: 186 DAG size of output 30 [2018-04-12 14:36:59,929 WARN L151 SmtUtils]: Spent 514ms on a formula simplification. DAG size of input: 218 DAG size of output 98 [2018-04-12 14:37:06,395 WARN L151 SmtUtils]: Spent 1121ms on a formula simplification. DAG size of input: 219 DAG size of output 100 [2018-04-12 14:37:13,944 WARN L151 SmtUtils]: Spent 1259ms on a formula simplification. DAG size of input: 170 DAG size of output 112 [2018-04-12 14:37:23,824 WARN L151 SmtUtils]: Spent 2294ms on a formula simplification. DAG size of input: 229 DAG size of output 115 [2018-04-12 14:37:24,275 WARN L151 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 161 DAG size of output 50 [2018-04-12 14:37:31,122 WARN L151 SmtUtils]: Spent 2579ms on a formula simplification. DAG size of input: 179 DAG size of output 125 [2018-04-12 14:37:41,967 WARN L151 SmtUtils]: Spent 2853ms on a formula simplification. DAG size of input: 180 DAG size of output 127 [2018-04-12 14:37:56,799 WARN L151 SmtUtils]: Spent 4260ms on a formula simplification. DAG size of input: 239 DAG size of output 130 [2018-04-12 14:37:58,060 WARN L151 SmtUtils]: Spent 198ms on a formula simplification. DAG size of input: 165 DAG size of output 58 [2018-04-12 14:38:16,623 WARN L151 SmtUtils]: Spent 5683ms on a formula simplification. DAG size of input: 188 DAG size of output 138 [2018-04-12 14:38:17,239 WARN L151 SmtUtils]: Spent 139ms on a formula simplification. DAG size of input: 110 DAG size of output 63 Received shutdown request... [2018-04-12 14:38:21,324 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-04-12 14:38:21,324 WARN L519 AbstractCegarLoop]: Verification canceled [2018-04-12 14:38:21,328 WARN L197 ceAbstractionStarter]: Timeout [2018-04-12 14:38:21,328 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 12.04 02:38:21 BoogieIcfgContainer [2018-04-12 14:38:21,328 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-04-12 14:38:21,329 INFO L168 Benchmark]: Toolchain (without parser) took 817789.73 ms. Allocated memory was 391.6 MB in the beginning and 2.6 GB in the end (delta: 2.3 GB). Free memory was 328.8 MB in the beginning and 1.3 GB in the end (delta: -951.2 MB). Peak memory consumption was 1.3 GB. Max. memory is 5.3 GB. [2018-04-12 14:38:21,330 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 391.6 MB. Free memory is still 354.9 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-04-12 14:38:21,331 INFO L168 Benchmark]: CACSL2BoogieTranslator took 216.19 ms. Allocated memory is still 391.6 MB. Free memory was 328.8 MB in the beginning and 303.7 MB in the end (delta: 25.1 MB). Peak memory consumption was 25.1 MB. Max. memory is 5.3 GB. [2018-04-12 14:38:21,331 INFO L168 Benchmark]: Boogie Preprocessor took 34.72 ms. Allocated memory is still 391.6 MB. Free memory was 303.7 MB in the beginning and 301.1 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. [2018-04-12 14:38:21,331 INFO L168 Benchmark]: RCFGBuilder took 370.06 ms. Allocated memory was 391.6 MB in the beginning and 588.8 MB in the end (delta: 197.1 MB). Free memory was 301.1 MB in the beginning and 521.6 MB in the end (delta: -220.5 MB). Peak memory consumption was 22.8 MB. Max. memory is 5.3 GB. [2018-04-12 14:38:21,331 INFO L168 Benchmark]: TraceAbstraction took 817166.40 ms. Allocated memory was 588.8 MB in the beginning and 2.6 GB in the end (delta: 2.1 GB). Free memory was 521.6 MB in the beginning and 1.3 GB in the end (delta: -758.5 MB). Peak memory consumption was 1.3 GB. Max. memory is 5.3 GB. [2018-04-12 14:38:21,332 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 391.6 MB. Free memory is still 354.9 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 216.19 ms. Allocated memory is still 391.6 MB. Free memory was 328.8 MB in the beginning and 303.7 MB in the end (delta: 25.1 MB). Peak memory consumption was 25.1 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 34.72 ms. Allocated memory is still 391.6 MB. Free memory was 303.7 MB in the beginning and 301.1 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 370.06 ms. Allocated memory was 391.6 MB in the beginning and 588.8 MB in the end (delta: 197.1 MB). Free memory was 301.1 MB in the beginning and 521.6 MB in the end (delta: -220.5 MB). Peak memory consumption was 22.8 MB. Max. memory is 5.3 GB. * TraceAbstraction took 817166.40 ms. Allocated memory was 588.8 MB in the beginning and 2.6 GB in the end (delta: 2.1 GB). Free memory was 521.6 MB in the beginning and 1.3 GB in the end (delta: -758.5 MB). Peak memory consumption was 1.3 GB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 640]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 640). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 638]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 638). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 641]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 641). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 643]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 643). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 643]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 643). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 643]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 643). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 638]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 638). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 630]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 630). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 640]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 640). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 641]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 641). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 641]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 641). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 640]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 640). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 640]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 640). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 641]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 641). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 643]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 643). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 626]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 626). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 628]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 628). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 628]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 628). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 626]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 626). Cancelled while BasicCegarLoop was constructing difference of abstraction (124states) and interpolant automaton (currently 67 states, 82 states before enhancement), while ReachableStatesComputation was computing reachable states (117 states constructedinput type IntersectNwa). - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 67 locations, 19 error locations. TIMEOUT Result, 817.1s OverallTime, 38 OverallIterations, 10 TraceHistogramMax, 444.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1519 SDtfs, 8127 SDslu, 13657 SDs, 0 SdLazy, 24774 SolverSat, 3418 SolverUnsat, 1961 SolverUnknown, 0 SolverNotchecked, 98.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 3260 GetRequests, 1631 SyntacticMatches, 73 SemanticMatches, 1556 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47887 ImplicationChecksByTransitivity, 481.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=184occurred in iteration=33, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 37 MinimizatonAttempts, 670 StatesRemovedByMinimization, 22 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 1.4s SatisfiabilityAnalysisTime, 369.4s InterpolantComputationTime, 3987 NumberOfCodeBlocks, 3938 NumberOfCodeBlocksAsserted, 125 NumberOfCheckSat, 3924 ConstructedInterpolants, 251 QuantifiedInterpolants, 158370078 SizeOfPredicates, 152 NumberOfNonLiveVariables, 5896 ConjunctsInSsa, 599 ConjunctsInUnsatCore, 63 InterpolantComputations, 15 PerfectInterpolantSequences, 3567/6608 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_1_true-valid-memsafety.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf_AutomizerC.xml/Csv-Benchmark-0-2018-04-12_14-38-21-338.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/960521-1_1_true-valid-memsafety.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-04-12_14-38-21-338.csv Completed graceful shutdown