java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv --cacsl2boogietranslator.bitprecise.bitfields false -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c -------------------------------------------------------------------------------- This is Ultimate 0.1.23-408c70d-m [2018-04-12 15:06:41,802 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-04-12 15:06:41,804 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-04-12 15:06:41,815 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-04-12 15:06:41,815 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-04-12 15:06:41,816 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-04-12 15:06:41,817 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-04-12 15:06:41,818 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-04-12 15:06:41,819 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-04-12 15:06:41,820 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-04-12 15:06:41,821 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-04-12 15:06:41,821 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-04-12 15:06:41,822 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-04-12 15:06:41,823 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-04-12 15:06:41,824 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-04-12 15:06:41,825 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-04-12 15:06:41,827 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-04-12 15:06:41,829 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-04-12 15:06:41,830 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-04-12 15:06:41,831 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-04-12 15:06:41,833 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-04-12 15:06:41,833 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-04-12 15:06:41,833 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-04-12 15:06:41,834 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-04-12 15:06:41,835 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-04-12 15:06:41,836 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-04-12 15:06:41,836 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-04-12 15:06:41,837 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-04-12 15:06:41,837 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-04-12 15:06:41,837 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-04-12 15:06:41,838 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-04-12 15:06:41,838 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf [2018-04-12 15:06:41,849 INFO L110 SettingsManager]: Loading preferences was successful [2018-04-12 15:06:41,849 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-04-12 15:06:41,850 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-04-12 15:06:41,850 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-04-12 15:06:41,850 INFO L133 SettingsManager]: * Use SBE=true [2018-04-12 15:06:41,850 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-04-12 15:06:41,851 INFO L133 SettingsManager]: * sizeof long=4 [2018-04-12 15:06:41,851 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-04-12 15:06:41,851 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-04-12 15:06:41,851 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-04-12 15:06:41,851 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-04-12 15:06:41,851 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-04-12 15:06:41,851 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-04-12 15:06:41,852 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-04-12 15:06:41,852 INFO L133 SettingsManager]: * sizeof long double=12 [2018-04-12 15:06:41,852 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-04-12 15:06:41,852 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-04-12 15:06:41,852 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-04-12 15:06:41,852 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-04-12 15:06:41,852 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-12 15:06:41,853 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-04-12 15:06:41,853 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-04-12 15:06:41,853 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-04-12 15:06:41,853 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Bitprecise bitfields -> false [2018-04-12 15:06:41,884 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-04-12 15:06:41,895 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully (re)initialized [2018-04-12 15:06:41,898 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-04-12 15:06:41,900 INFO L271 PluginConnector]: Initializing CDTParser... [2018-04-12 15:06:41,900 INFO L276 PluginConnector]: CDTParser initialized [2018-04-12 15:06:41,901 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-04-12 15:06:42,268 INFO L225 CDTParser]: Created temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGf57f51afe [2018-04-12 15:06:42,357 INFO L287 CDTParser]: IsIndexed: true [2018-04-12 15:06:42,357 INFO L288 CDTParser]: Found 1 translation units. [2018-04-12 15:06:42,358 INFO L168 CDTParser]: Scanning ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-04-12 15:06:42,359 INFO L210 ultiparseSymbolTable]: Include resolver: [2018-04-12 15:06:42,359 INFO L215 ultiparseSymbolTable]: [2018-04-12 15:06:42,359 INFO L218 ultiparseSymbolTable]: Function table: [2018-04-12 15:06:42,359 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__foo ('foo') in ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-04-12 15:06:42,359 INFO L221 ultiparseSymbolTable]: Function definition of null ('main') in ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-04-12 15:06:42,359 INFO L227 ultiparseSymbolTable]: Global variable table: [2018-04-12 15:06:42,360 INFO L233 ultiparseSymbolTable]: [2018-04-12 15:06:42,371 INFO L330 CDTParser]: Deleted temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGf57f51afe [2018-04-12 15:06:42,375 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-04-12 15:06:42,376 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-04-12 15:06:42,377 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-04-12 15:06:42,377 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-04-12 15:06:42,381 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-04-12 15:06:42,381 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.04 03:06:42" (1/1) ... [2018-04-12 15:06:42,383 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@78201a53 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 03:06:42, skipping insertion in model container [2018-04-12 15:06:42,383 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.04 03:06:42" (1/1) ... [2018-04-12 15:06:42,395 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-12 15:06:42,404 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-12 15:06:42,500 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-12 15:06:42,522 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-12 15:06:42,526 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 9 non ball SCCs. Number of states in SCCs 9. [2018-04-12 15:06:42,533 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 03:06:42 WrapperNode [2018-04-12 15:06:42,533 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-04-12 15:06:42,533 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-04-12 15:06:42,533 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-04-12 15:06:42,533 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-04-12 15:06:42,541 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 03:06:42" (1/1) ... [2018-04-12 15:06:42,541 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 03:06:42" (1/1) ... [2018-04-12 15:06:42,547 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 03:06:42" (1/1) ... [2018-04-12 15:06:42,548 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 03:06:42" (1/1) ... [2018-04-12 15:06:42,551 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 03:06:42" (1/1) ... [2018-04-12 15:06:42,556 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 03:06:42" (1/1) ... [2018-04-12 15:06:42,557 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 03:06:42" (1/1) ... [2018-04-12 15:06:42,558 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-04-12 15:06:42,559 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-04-12 15:06:42,559 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-04-12 15:06:42,559 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-04-12 15:06:42,560 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 03:06:42" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-12 15:06:42,593 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-04-12 15:06:42,594 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-04-12 15:06:42,594 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__foo [2018-04-12 15:06:42,594 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-04-12 15:06:42,594 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__foo [2018-04-12 15:06:42,594 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-04-12 15:06:42,594 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-04-12 15:06:42,594 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-04-12 15:06:42,594 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-04-12 15:06:42,594 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-04-12 15:06:42,594 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-04-12 15:06:42,595 INFO L128 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-04-12 15:06:42,595 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-04-12 15:06:42,796 INFO L259 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-04-12 15:06:42,796 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.04 03:06:42 BoogieIcfgContainer [2018-04-12 15:06:42,797 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-04-12 15:06:42,797 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-04-12 15:06:42,797 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-04-12 15:06:42,799 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-04-12 15:06:42,799 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 12.04 03:06:42" (1/3) ... [2018-04-12 15:06:42,800 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d43d35d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.04 03:06:42, skipping insertion in model container [2018-04-12 15:06:42,800 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 03:06:42" (2/3) ... [2018-04-12 15:06:42,800 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d43d35d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.04 03:06:42, skipping insertion in model container [2018-04-12 15:06:42,800 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.04 03:06:42" (3/3) ... [2018-04-12 15:06:42,801 INFO L107 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-04-12 15:06:42,808 INFO L131 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-04-12 15:06:42,812 INFO L143 ceAbstractionStarter]: Appying trace abstraction to program that has 6 error locations. [2018-04-12 15:06:42,837 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-04-12 15:06:42,838 INFO L369 AbstractCegarLoop]: Interprodecural is true [2018-04-12 15:06:42,838 INFO L370 AbstractCegarLoop]: Hoare is false [2018-04-12 15:06:42,838 INFO L371 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-04-12 15:06:42,838 INFO L372 AbstractCegarLoop]: Backedges is TWOTRACK [2018-04-12 15:06:42,838 INFO L373 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-04-12 15:06:42,838 INFO L374 AbstractCegarLoop]: Difference is false [2018-04-12 15:06:42,839 INFO L375 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-04-12 15:06:42,839 INFO L380 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-04-12 15:06:42,839 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-04-12 15:06:42,847 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states. [2018-04-12 15:06:42,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-04-12 15:06:42,853 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:42,854 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:42,854 INFO L408 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:42,857 INFO L82 PathProgramCache]: Analyzing trace with hash -215054890, now seen corresponding path program 1 times [2018-04-12 15:06:42,858 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:42,859 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:42,888 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:42,888 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:42,888 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:42,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:42,927 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:42,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 15:06:42,973 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 15:06:42,973 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-04-12 15:06:42,974 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-12 15:06:42,983 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-12 15:06:42,984 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-12 15:06:42,986 INFO L87 Difference]: Start difference. First operand 46 states. Second operand 3 states. [2018-04-12 15:06:43,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:43,039 INFO L93 Difference]: Finished difference Result 63 states and 68 transitions. [2018-04-12 15:06:43,039 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-12 15:06:43,040 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-04-12 15:06:43,040 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:43,046 INFO L225 Difference]: With dead ends: 63 [2018-04-12 15:06:43,046 INFO L226 Difference]: Without dead ends: 59 [2018-04-12 15:06:43,047 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-12 15:06:43,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-04-12 15:06:43,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 49. [2018-04-12 15:06:43,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-04-12 15:06:43,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 52 transitions. [2018-04-12 15:06:43,073 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 52 transitions. Word has length 11 [2018-04-12 15:06:43,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:43,074 INFO L459 AbstractCegarLoop]: Abstraction has 49 states and 52 transitions. [2018-04-12 15:06:43,074 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-12 15:06:43,074 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 52 transitions. [2018-04-12 15:06:43,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-04-12 15:06:43,074 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:43,075 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:43,075 INFO L408 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:43,075 INFO L82 PathProgramCache]: Analyzing trace with hash 1100032001, now seen corresponding path program 1 times [2018-04-12 15:06:43,075 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:43,075 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:43,076 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:43,076 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:43,076 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:43,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:43,086 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:43,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 15:06:43,102 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 15:06:43,102 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-04-12 15:06:43,103 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-12 15:06:43,103 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-12 15:06:43,103 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-12 15:06:43,104 INFO L87 Difference]: Start difference. First operand 49 states and 52 transitions. Second operand 3 states. [2018-04-12 15:06:43,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:43,141 INFO L93 Difference]: Finished difference Result 60 states and 64 transitions. [2018-04-12 15:06:43,141 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-12 15:06:43,141 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 16 [2018-04-12 15:06:43,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:43,144 INFO L225 Difference]: With dead ends: 60 [2018-04-12 15:06:43,144 INFO L226 Difference]: Without dead ends: 60 [2018-04-12 15:06:43,145 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-12 15:06:43,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-04-12 15:06:43,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 52. [2018-04-12 15:06:43,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-04-12 15:06:43,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 56 transitions. [2018-04-12 15:06:43,150 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 56 transitions. Word has length 16 [2018-04-12 15:06:43,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:43,151 INFO L459 AbstractCegarLoop]: Abstraction has 52 states and 56 transitions. [2018-04-12 15:06:43,151 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-12 15:06:43,151 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 56 transitions. [2018-04-12 15:06:43,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-04-12 15:06:43,151 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:43,151 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:43,151 INFO L408 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:43,152 INFO L82 PathProgramCache]: Analyzing trace with hash -258746290, now seen corresponding path program 1 times [2018-04-12 15:06:43,152 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:43,152 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:43,153 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:43,153 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:43,153 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:43,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:43,165 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:43,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 15:06:43,288 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 15:06:43,289 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-04-12 15:06:43,289 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-12 15:06:43,289 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-12 15:06:43,289 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-04-12 15:06:43,290 INFO L87 Difference]: Start difference. First operand 52 states and 56 transitions. Second operand 8 states. [2018-04-12 15:06:43,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:43,461 INFO L93 Difference]: Finished difference Result 75 states and 81 transitions. [2018-04-12 15:06:43,461 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-12 15:06:43,461 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 17 [2018-04-12 15:06:43,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:43,462 INFO L225 Difference]: With dead ends: 75 [2018-04-12 15:06:43,463 INFO L226 Difference]: Without dead ends: 75 [2018-04-12 15:06:43,463 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2018-04-12 15:06:43,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2018-04-12 15:06:43,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 66. [2018-04-12 15:06:43,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-04-12 15:06:43,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 73 transitions. [2018-04-12 15:06:43,469 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 73 transitions. Word has length 17 [2018-04-12 15:06:43,469 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:43,469 INFO L459 AbstractCegarLoop]: Abstraction has 66 states and 73 transitions. [2018-04-12 15:06:43,470 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-12 15:06:43,470 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 73 transitions. [2018-04-12 15:06:43,470 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-04-12 15:06:43,470 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:43,470 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:43,470 INFO L408 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:43,470 INFO L82 PathProgramCache]: Analyzing trace with hash -258746291, now seen corresponding path program 1 times [2018-04-12 15:06:43,471 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:43,471 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:43,472 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:43,472 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:43,472 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:43,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:43,479 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:43,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 15:06:43,497 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 15:06:43,497 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-12 15:06:43,498 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-12 15:06:43,498 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-12 15:06:43,498 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-04-12 15:06:43,498 INFO L87 Difference]: Start difference. First operand 66 states and 73 transitions. Second operand 5 states. [2018-04-12 15:06:43,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:43,520 INFO L93 Difference]: Finished difference Result 65 states and 71 transitions. [2018-04-12 15:06:43,521 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-12 15:06:43,521 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-04-12 15:06:43,521 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:43,522 INFO L225 Difference]: With dead ends: 65 [2018-04-12 15:06:43,522 INFO L226 Difference]: Without dead ends: 65 [2018-04-12 15:06:43,522 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-04-12 15:06:43,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2018-04-12 15:06:43,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 65. [2018-04-12 15:06:43,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65 states. [2018-04-12 15:06:43,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 71 transitions. [2018-04-12 15:06:43,525 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 71 transitions. Word has length 17 [2018-04-12 15:06:43,525 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:43,525 INFO L459 AbstractCegarLoop]: Abstraction has 65 states and 71 transitions. [2018-04-12 15:06:43,525 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-12 15:06:43,525 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 71 transitions. [2018-04-12 15:06:43,526 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-04-12 15:06:43,526 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:43,526 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:43,526 INFO L408 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:43,526 INFO L82 PathProgramCache]: Analyzing trace with hash -1933852231, now seen corresponding path program 1 times [2018-04-12 15:06:43,526 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:43,526 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:43,527 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:43,527 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:43,527 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:43,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:43,534 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:43,596 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 15:06:43,597 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:43,597 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:43,603 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:43,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:43,621 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:43,644 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 15:06:43,673 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:43,673 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 3] total 9 [2018-04-12 15:06:43,674 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-12 15:06:43,674 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-12 15:06:43,674 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-04-12 15:06:43,675 INFO L87 Difference]: Start difference. First operand 65 states and 71 transitions. Second operand 10 states. [2018-04-12 15:06:43,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:43,799 INFO L93 Difference]: Finished difference Result 105 states and 114 transitions. [2018-04-12 15:06:43,799 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-12 15:06:43,799 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 22 [2018-04-12 15:06:43,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:43,800 INFO L225 Difference]: With dead ends: 105 [2018-04-12 15:06:43,801 INFO L226 Difference]: Without dead ends: 105 [2018-04-12 15:06:43,801 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 20 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=52, Invalid=130, Unknown=0, NotChecked=0, Total=182 [2018-04-12 15:06:43,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-04-12 15:06:43,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 76. [2018-04-12 15:06:43,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-04-12 15:06:43,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 83 transitions. [2018-04-12 15:06:43,807 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 83 transitions. Word has length 22 [2018-04-12 15:06:43,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:43,807 INFO L459 AbstractCegarLoop]: Abstraction has 76 states and 83 transitions. [2018-04-12 15:06:43,807 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-12 15:06:43,807 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 83 transitions. [2018-04-12 15:06:43,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-04-12 15:06:43,808 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:43,808 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:43,808 INFO L408 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:43,808 INFO L82 PathProgramCache]: Analyzing trace with hash 1693854175, now seen corresponding path program 1 times [2018-04-12 15:06:43,809 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:43,809 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:43,810 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:43,810 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:43,810 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:43,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:43,819 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:43,861 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 15:06:43,861 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 15:06:43,862 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-12 15:06:43,862 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-12 15:06:43,862 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-12 15:06:43,862 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-04-12 15:06:43,862 INFO L87 Difference]: Start difference. First operand 76 states and 83 transitions. Second operand 5 states. [2018-04-12 15:06:43,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:43,888 INFO L93 Difference]: Finished difference Result 85 states and 91 transitions. [2018-04-12 15:06:43,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-12 15:06:43,888 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 29 [2018-04-12 15:06:43,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:43,889 INFO L225 Difference]: With dead ends: 85 [2018-04-12 15:06:43,890 INFO L226 Difference]: Without dead ends: 85 [2018-04-12 15:06:43,890 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-04-12 15:06:43,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-04-12 15:06:43,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 73. [2018-04-12 15:06:43,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-04-12 15:06:43,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 80 transitions. [2018-04-12 15:06:43,893 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 80 transitions. Word has length 29 [2018-04-12 15:06:43,894 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:43,894 INFO L459 AbstractCegarLoop]: Abstraction has 73 states and 80 transitions. [2018-04-12 15:06:43,894 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-12 15:06:43,894 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 80 transitions. [2018-04-12 15:06:43,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-04-12 15:06:43,894 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:43,894 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:43,895 INFO L408 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:43,895 INFO L82 PathProgramCache]: Analyzing trace with hash 1643098334, now seen corresponding path program 1 times [2018-04-12 15:06:43,895 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:43,895 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:43,895 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:43,896 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:43,896 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:43,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:43,903 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:43,921 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 15:06:43,922 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:43,922 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:43,937 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:43,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:43,957 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:44,009 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 15:06:44,028 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:44,028 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6] total 8 [2018-04-12 15:06:44,028 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-12 15:06:44,028 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-12 15:06:44,029 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-04-12 15:06:44,029 INFO L87 Difference]: Start difference. First operand 73 states and 80 transitions. Second operand 8 states. [2018-04-12 15:06:44,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:44,160 INFO L93 Difference]: Finished difference Result 118 states and 124 transitions. [2018-04-12 15:06:44,161 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-04-12 15:06:44,161 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 37 [2018-04-12 15:06:44,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:44,162 INFO L225 Difference]: With dead ends: 118 [2018-04-12 15:06:44,162 INFO L226 Difference]: Without dead ends: 109 [2018-04-12 15:06:44,163 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 34 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=79, Unknown=0, NotChecked=0, Total=110 [2018-04-12 15:06:44,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-04-12 15:06:44,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 88. [2018-04-12 15:06:44,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-04-12 15:06:44,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 94 transitions. [2018-04-12 15:06:44,168 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 94 transitions. Word has length 37 [2018-04-12 15:06:44,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:44,168 INFO L459 AbstractCegarLoop]: Abstraction has 88 states and 94 transitions. [2018-04-12 15:06:44,168 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-12 15:06:44,168 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 94 transitions. [2018-04-12 15:06:44,169 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-04-12 15:06:44,169 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:44,169 INFO L355 BasicCegarLoop]: trace histogram [7, 6, 6, 5, 5, 5, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:44,169 INFO L408 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:44,169 INFO L82 PathProgramCache]: Analyzing trace with hash 98230391, now seen corresponding path program 1 times [2018-04-12 15:06:44,169 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:44,169 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:44,170 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:44,170 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:44,170 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:44,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:44,199 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:44,361 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 53 proven. 30 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-04-12 15:06:44,361 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:44,362 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:44,367 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:44,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:44,389 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:44,462 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 83 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-04-12 15:06:44,479 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:44,480 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 9] total 16 [2018-04-12 15:06:44,480 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-12 15:06:44,480 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-12 15:06:44,480 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=196, Unknown=0, NotChecked=0, Total=240 [2018-04-12 15:06:44,481 INFO L87 Difference]: Start difference. First operand 88 states and 94 transitions. Second operand 16 states. [2018-04-12 15:06:44,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:44,895 INFO L93 Difference]: Finished difference Result 155 states and 162 transitions. [2018-04-12 15:06:44,895 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-04-12 15:06:44,895 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 59 [2018-04-12 15:06:44,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:44,896 INFO L225 Difference]: With dead ends: 155 [2018-04-12 15:06:44,896 INFO L226 Difference]: Without dead ends: 155 [2018-04-12 15:06:44,897 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 52 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 146 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=168, Invalid=644, Unknown=0, NotChecked=0, Total=812 [2018-04-12 15:06:44,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states. [2018-04-12 15:06:44,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 126. [2018-04-12 15:06:44,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-04-12 15:06:44,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 134 transitions. [2018-04-12 15:06:44,904 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 134 transitions. Word has length 59 [2018-04-12 15:06:44,905 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:44,905 INFO L459 AbstractCegarLoop]: Abstraction has 126 states and 134 transitions. [2018-04-12 15:06:44,905 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-12 15:06:44,905 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 134 transitions. [2018-04-12 15:06:44,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-04-12 15:06:44,907 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:44,907 INFO L355 BasicCegarLoop]: trace histogram [6, 4, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:44,907 INFO L408 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:44,907 INFO L82 PathProgramCache]: Analyzing trace with hash -81663113, now seen corresponding path program 2 times [2018-04-12 15:06:44,908 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:44,908 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:44,908 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:44,908 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:44,909 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:44,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:44,923 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:45,058 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 37 proven. 16 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-04-12 15:06:45,058 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:45,058 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:45,064 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 15:06:45,073 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-04-12 15:06:45,073 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:06:45,075 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:45,117 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 15:06:45,122 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 5 [2018-04-12 15:06:45,123 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:06:45,125 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-12 15:06:45,126 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:12, output treesize:5 [2018-04-12 15:06:45,175 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 15:06:45,176 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 5 [2018-04-12 15:06:45,176 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:06:45,178 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-12 15:06:45,178 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:12, output treesize:5 [2018-04-12 15:06:45,218 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_~#mask~0.base| Int)) (and (= (store |c_old(#valid)| |main_~#mask~0.base| 0) |c_#valid|) (= (select |c_old(#valid)| |main_~#mask~0.base|) 0))) is different from true [2018-04-12 15:06:45,231 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 68 trivial. 0 not checked. [2018-04-12 15:06:45,262 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-04-12 15:06:45,263 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [10] total 14 [2018-04-12 15:06:45,263 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-04-12 15:06:45,263 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-04-12 15:06:45,264 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=130, Unknown=1, NotChecked=22, Total=182 [2018-04-12 15:06:45,264 INFO L87 Difference]: Start difference. First operand 126 states and 134 transitions. Second operand 14 states. [2018-04-12 15:06:45,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:45,538 INFO L93 Difference]: Finished difference Result 105 states and 110 transitions. [2018-04-12 15:06:45,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-04-12 15:06:45,538 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 67 [2018-04-12 15:06:45,539 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:45,539 INFO L225 Difference]: With dead ends: 105 [2018-04-12 15:06:45,539 INFO L226 Difference]: Without dead ends: 105 [2018-04-12 15:06:45,540 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 62 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 60 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=103, Invalid=362, Unknown=1, NotChecked=40, Total=506 [2018-04-12 15:06:45,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-04-12 15:06:45,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 105. [2018-04-12 15:06:45,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-04-12 15:06:45,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 110 transitions. [2018-04-12 15:06:45,544 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 110 transitions. Word has length 67 [2018-04-12 15:06:45,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:45,545 INFO L459 AbstractCegarLoop]: Abstraction has 105 states and 110 transitions. [2018-04-12 15:06:45,545 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-04-12 15:06:45,545 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 110 transitions. [2018-04-12 15:06:45,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-04-12 15:06:45,546 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:45,546 INFO L355 BasicCegarLoop]: trace histogram [11, 9, 9, 8, 8, 8, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:45,546 INFO L408 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:45,546 INFO L82 PathProgramCache]: Analyzing trace with hash 1376831888, now seen corresponding path program 2 times [2018-04-12 15:06:45,546 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:45,546 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:45,547 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:45,547 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:06:45,547 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:45,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:45,565 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:45,635 INFO L134 CoverageAnalysis]: Checked inductivity of 258 backedges. 185 proven. 10 refuted. 0 times theorem prover too weak. 63 trivial. 0 not checked. [2018-04-12 15:06:45,635 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:45,635 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:45,645 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 15:06:45,674 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 15:06:45,675 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:06:45,678 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:45,733 INFO L134 CoverageAnalysis]: Checked inductivity of 258 backedges. 185 proven. 10 refuted. 0 times theorem prover too weak. 63 trivial. 0 not checked. [2018-04-12 15:06:45,763 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:45,763 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 11 [2018-04-12 15:06:45,763 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-12 15:06:45,763 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-12 15:06:45,764 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=76, Unknown=0, NotChecked=0, Total=110 [2018-04-12 15:06:45,764 INFO L87 Difference]: Start difference. First operand 105 states and 110 transitions. Second operand 11 states. [2018-04-12 15:06:45,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:45,834 INFO L93 Difference]: Finished difference Result 114 states and 117 transitions. [2018-04-12 15:06:45,834 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-12 15:06:45,834 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 89 [2018-04-12 15:06:45,835 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:45,835 INFO L225 Difference]: With dead ends: 114 [2018-04-12 15:06:45,836 INFO L226 Difference]: Without dead ends: 108 [2018-04-12 15:06:45,836 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=93, Unknown=0, NotChecked=0, Total=132 [2018-04-12 15:06:45,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states. [2018-04-12 15:06:45,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 105. [2018-04-12 15:06:45,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-04-12 15:06:45,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 108 transitions. [2018-04-12 15:06:45,840 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 108 transitions. Word has length 89 [2018-04-12 15:06:45,841 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:45,841 INFO L459 AbstractCegarLoop]: Abstraction has 105 states and 108 transitions. [2018-04-12 15:06:45,841 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-12 15:06:45,841 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 108 transitions. [2018-04-12 15:06:45,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-04-12 15:06:45,842 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:45,842 INFO L355 BasicCegarLoop]: trace histogram [12, 10, 10, 9, 9, 9, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:45,842 INFO L408 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:45,843 INFO L82 PathProgramCache]: Analyzing trace with hash -30161384, now seen corresponding path program 3 times [2018-04-12 15:06:45,843 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:45,843 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:45,844 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:45,844 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:06:45,844 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:45,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:45,863 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:45,949 INFO L134 CoverageAnalysis]: Checked inductivity of 314 backedges. 203 proven. 25 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-04-12 15:06:45,950 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:45,950 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:45,959 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 15:06:45,978 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-04-12 15:06:45,979 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:06:45,982 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:45,986 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:06:45,986 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:06:45,989 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:06:45,989 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:06:46,194 INFO L134 CoverageAnalysis]: Checked inductivity of 314 backedges. 162 proven. 22 refuted. 0 times theorem prover too weak. 130 trivial. 0 not checked. [2018-04-12 15:06:46,227 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:46,227 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 10] total 21 [2018-04-12 15:06:46,228 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-04-12 15:06:46,228 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-04-12 15:06:46,228 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=346, Unknown=0, NotChecked=0, Total=420 [2018-04-12 15:06:46,228 INFO L87 Difference]: Start difference. First operand 105 states and 108 transitions. Second operand 21 states. [2018-04-12 15:06:46,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:46,623 INFO L93 Difference]: Finished difference Result 143 states and 147 transitions. [2018-04-12 15:06:46,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-04-12 15:06:46,624 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 95 [2018-04-12 15:06:46,624 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:46,625 INFO L225 Difference]: With dead ends: 143 [2018-04-12 15:06:46,625 INFO L226 Difference]: Without dead ends: 143 [2018-04-12 15:06:46,626 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 84 SyntacticMatches, 3 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 243 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=247, Invalid=875, Unknown=0, NotChecked=0, Total=1122 [2018-04-12 15:06:46,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-04-12 15:06:46,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 141. [2018-04-12 15:06:46,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-04-12 15:06:46,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 145 transitions. [2018-04-12 15:06:46,631 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 145 transitions. Word has length 95 [2018-04-12 15:06:46,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:46,631 INFO L459 AbstractCegarLoop]: Abstraction has 141 states and 145 transitions. [2018-04-12 15:06:46,631 INFO L460 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-04-12 15:06:46,631 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 145 transitions. [2018-04-12 15:06:46,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2018-04-12 15:06:46,633 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:46,633 INFO L355 BasicCegarLoop]: trace histogram [16, 13, 13, 12, 12, 12, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:46,633 INFO L408 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:46,633 INFO L82 PathProgramCache]: Analyzing trace with hash -2114920591, now seen corresponding path program 4 times [2018-04-12 15:06:46,633 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:46,633 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:46,634 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:46,634 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:06:46,634 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:46,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:46,659 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:46,850 INFO L134 CoverageAnalysis]: Checked inductivity of 573 backedges. 257 proven. 52 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-04-12 15:06:46,850 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:46,850 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:46,859 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-12 15:06:46,892 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-12 15:06:46,892 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:06:46,896 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:46,982 INFO L134 CoverageAnalysis]: Checked inductivity of 573 backedges. 409 proven. 24 refuted. 0 times theorem prover too weak. 140 trivial. 0 not checked. [2018-04-12 15:06:47,000 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:47,000 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 10] total 18 [2018-04-12 15:06:47,001 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-04-12 15:06:47,001 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-04-12 15:06:47,001 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=252, Unknown=0, NotChecked=0, Total=306 [2018-04-12 15:06:47,002 INFO L87 Difference]: Start difference. First operand 141 states and 145 transitions. Second operand 18 states. [2018-04-12 15:06:47,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:47,292 INFO L93 Difference]: Finished difference Result 161 states and 164 transitions. [2018-04-12 15:06:47,292 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-12 15:06:47,292 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 125 [2018-04-12 15:06:47,292 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:47,293 INFO L225 Difference]: With dead ends: 161 [2018-04-12 15:06:47,293 INFO L226 Difference]: Without dead ends: 155 [2018-04-12 15:06:47,294 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 144 GetRequests, 117 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 125 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=151, Invalid=605, Unknown=0, NotChecked=0, Total=756 [2018-04-12 15:06:47,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states. [2018-04-12 15:06:47,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 147. [2018-04-12 15:06:47,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-04-12 15:06:47,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 150 transitions. [2018-04-12 15:06:47,297 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 150 transitions. Word has length 125 [2018-04-12 15:06:47,298 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:47,298 INFO L459 AbstractCegarLoop]: Abstraction has 147 states and 150 transitions. [2018-04-12 15:06:47,298 INFO L460 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-04-12 15:06:47,298 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 150 transitions. [2018-04-12 15:06:47,299 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-04-12 15:06:47,300 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:47,300 INFO L355 BasicCegarLoop]: trace histogram [18, 15, 15, 14, 14, 14, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:47,300 INFO L408 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:47,300 INFO L82 PathProgramCache]: Analyzing trace with hash -936202175, now seen corresponding path program 5 times [2018-04-12 15:06:47,300 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:47,300 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:47,301 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:47,301 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:06:47,301 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:47,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:47,317 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:47,520 INFO L134 CoverageAnalysis]: Checked inductivity of 743 backedges. 345 proven. 80 refuted. 0 times theorem prover too weak. 318 trivial. 0 not checked. [2018-04-12 15:06:47,521 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:47,521 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:47,528 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-12 15:06:47,565 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-04-12 15:06:47,566 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:06:47,568 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:47,704 INFO L134 CoverageAnalysis]: Checked inductivity of 743 backedges. 425 proven. 30 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-04-12 15:06:47,723 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:47,723 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 14] total 23 [2018-04-12 15:06:47,723 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-04-12 15:06:47,723 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-04-12 15:06:47,724 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=419, Unknown=0, NotChecked=0, Total=506 [2018-04-12 15:06:47,724 INFO L87 Difference]: Start difference. First operand 147 states and 150 transitions. Second operand 23 states. [2018-04-12 15:06:48,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:48,159 INFO L93 Difference]: Finished difference Result 211 states and 216 transitions. [2018-04-12 15:06:48,159 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-04-12 15:06:48,159 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 137 [2018-04-12 15:06:48,159 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:48,160 INFO L225 Difference]: With dead ends: 211 [2018-04-12 15:06:48,160 INFO L226 Difference]: Without dead ends: 211 [2018-04-12 15:06:48,161 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 166 GetRequests, 125 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 365 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=314, Invalid=1408, Unknown=0, NotChecked=0, Total=1722 [2018-04-12 15:06:48,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states. [2018-04-12 15:06:48,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 195. [2018-04-12 15:06:48,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 195 states. [2018-04-12 15:06:48,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 200 transitions. [2018-04-12 15:06:48,164 INFO L78 Accepts]: Start accepts. Automaton has 195 states and 200 transitions. Word has length 137 [2018-04-12 15:06:48,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:48,165 INFO L459 AbstractCegarLoop]: Abstraction has 195 states and 200 transitions. [2018-04-12 15:06:48,165 INFO L460 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-04-12 15:06:48,165 INFO L276 IsEmpty]: Start isEmpty. Operand 195 states and 200 transitions. [2018-04-12 15:06:48,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2018-04-12 15:06:48,167 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:48,167 INFO L355 BasicCegarLoop]: trace histogram [24, 20, 20, 19, 19, 19, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:48,167 INFO L408 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:48,167 INFO L82 PathProgramCache]: Analyzing trace with hash -1943695766, now seen corresponding path program 6 times [2018-04-12 15:06:48,167 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:48,167 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:48,168 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:48,168 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:06:48,168 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:48,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:48,181 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:48,243 INFO L134 CoverageAnalysis]: Checked inductivity of 1354 backedges. 905 proven. 44 refuted. 0 times theorem prover too weak. 405 trivial. 0 not checked. [2018-04-12 15:06:48,244 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:48,244 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:48,249 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-12 15:06:48,291 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-04-12 15:06:48,291 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:06:48,294 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:48,446 INFO L134 CoverageAnalysis]: Checked inductivity of 1354 backedges. 716 proven. 333 refuted. 0 times theorem prover too weak. 305 trivial. 0 not checked. [2018-04-12 15:06:48,464 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:48,465 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 19] total 28 [2018-04-12 15:06:48,465 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-04-12 15:06:48,465 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-04-12 15:06:48,465 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=633, Unknown=0, NotChecked=0, Total=756 [2018-04-12 15:06:48,466 INFO L87 Difference]: Start difference. First operand 195 states and 200 transitions. Second operand 28 states. [2018-04-12 15:06:48,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:48,868 INFO L93 Difference]: Finished difference Result 260 states and 264 transitions. [2018-04-12 15:06:48,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-04-12 15:06:48,868 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 179 [2018-04-12 15:06:48,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:48,869 INFO L225 Difference]: With dead ends: 260 [2018-04-12 15:06:48,869 INFO L226 Difference]: Without dead ends: 251 [2018-04-12 15:06:48,869 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 210 GetRequests, 164 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 647 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=343, Invalid=1913, Unknown=0, NotChecked=0, Total=2256 [2018-04-12 15:06:48,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 251 states. [2018-04-12 15:06:48,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 251 to 243. [2018-04-12 15:06:48,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 243 states. [2018-04-12 15:06:48,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 243 states to 243 states and 247 transitions. [2018-04-12 15:06:48,873 INFO L78 Accepts]: Start accepts. Automaton has 243 states and 247 transitions. Word has length 179 [2018-04-12 15:06:48,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:48,873 INFO L459 AbstractCegarLoop]: Abstraction has 243 states and 247 transitions. [2018-04-12 15:06:48,874 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-04-12 15:06:48,874 INFO L276 IsEmpty]: Start isEmpty. Operand 243 states and 247 transitions. [2018-04-12 15:06:48,875 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 228 [2018-04-12 15:06:48,875 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:48,875 INFO L355 BasicCegarLoop]: trace histogram [31, 26, 26, 25, 25, 25, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:48,875 INFO L408 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:48,875 INFO L82 PathProgramCache]: Analyzing trace with hash -431804325, now seen corresponding path program 7 times [2018-04-12 15:06:48,876 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:48,876 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:48,876 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:48,876 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:06:48,876 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:48,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:48,892 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:48,989 INFO L134 CoverageAnalysis]: Checked inductivity of 2305 backedges. 1423 proven. 70 refuted. 0 times theorem prover too weak. 812 trivial. 0 not checked. [2018-04-12 15:06:48,989 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:48,989 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:48,994 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:49,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:49,040 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:49,114 INFO L134 CoverageAnalysis]: Checked inductivity of 2305 backedges. 1423 proven. 70 refuted. 0 times theorem prover too weak. 812 trivial. 0 not checked. [2018-04-12 15:06:49,131 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:49,131 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 20 [2018-04-12 15:06:49,131 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-04-12 15:06:49,131 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-04-12 15:06:49,132 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=277, Unknown=0, NotChecked=0, Total=380 [2018-04-12 15:06:49,132 INFO L87 Difference]: Start difference. First operand 243 states and 247 transitions. Second operand 20 states. [2018-04-12 15:06:49,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:49,243 INFO L93 Difference]: Finished difference Result 254 states and 256 transitions. [2018-04-12 15:06:49,243 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-04-12 15:06:49,243 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 227 [2018-04-12 15:06:49,244 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:49,245 INFO L225 Difference]: With dead ends: 254 [2018-04-12 15:06:49,245 INFO L226 Difference]: Without dead ends: 248 [2018-04-12 15:06:49,245 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 244 GetRequests, 222 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 145 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=141, Invalid=411, Unknown=0, NotChecked=0, Total=552 [2018-04-12 15:06:49,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 248 states. [2018-04-12 15:06:49,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 248 to 243. [2018-04-12 15:06:49,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 243 states. [2018-04-12 15:06:49,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 243 states to 243 states and 245 transitions. [2018-04-12 15:06:49,250 INFO L78 Accepts]: Start accepts. Automaton has 243 states and 245 transitions. Word has length 227 [2018-04-12 15:06:49,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:49,251 INFO L459 AbstractCegarLoop]: Abstraction has 243 states and 245 transitions. [2018-04-12 15:06:49,251 INFO L460 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-04-12 15:06:49,251 INFO L276 IsEmpty]: Start isEmpty. Operand 243 states and 245 transitions. [2018-04-12 15:06:49,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 234 [2018-04-12 15:06:49,253 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:49,253 INFO L355 BasicCegarLoop]: trace histogram [32, 27, 27, 26, 26, 26, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:49,253 INFO L408 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:49,254 INFO L82 PathProgramCache]: Analyzing trace with hash 944998563, now seen corresponding path program 8 times [2018-04-12 15:06:49,254 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:49,254 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:49,255 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:49,255 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:49,255 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:49,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:49,278 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:49,507 INFO L134 CoverageAnalysis]: Checked inductivity of 2469 backedges. 875 proven. 114 refuted. 0 times theorem prover too weak. 1480 trivial. 0 not checked. [2018-04-12 15:06:49,507 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:49,507 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:49,512 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 15:06:49,548 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 15:06:49,548 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:06:49,551 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:49,554 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:06:49,554 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:06:49,556 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:06:49,556 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:06:49,878 INFO L134 CoverageAnalysis]: Checked inductivity of 2469 backedges. 875 proven. 92 refuted. 0 times theorem prover too weak. 1502 trivial. 0 not checked. [2018-04-12 15:06:49,896 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:49,896 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 13] total 20 [2018-04-12 15:06:49,923 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-04-12 15:06:49,923 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-04-12 15:06:49,923 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=318, Unknown=0, NotChecked=0, Total=420 [2018-04-12 15:06:49,924 INFO L87 Difference]: Start difference. First operand 243 states and 245 transitions. Second operand 21 states. [2018-04-12 15:06:50,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:50,324 INFO L93 Difference]: Finished difference Result 317 states and 322 transitions. [2018-04-12 15:06:50,325 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-04-12 15:06:50,325 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 233 [2018-04-12 15:06:50,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:50,326 INFO L225 Difference]: With dead ends: 317 [2018-04-12 15:06:50,326 INFO L226 Difference]: Without dead ends: 317 [2018-04-12 15:06:50,326 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 261 GetRequests, 213 SyntacticMatches, 12 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 442 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=355, Invalid=1051, Unknown=0, NotChecked=0, Total=1406 [2018-04-12 15:06:50,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 317 states. [2018-04-12 15:06:50,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 317 to 297. [2018-04-12 15:06:50,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 297 states. [2018-04-12 15:06:50,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 297 states to 297 states and 301 transitions. [2018-04-12 15:06:50,330 INFO L78 Accepts]: Start accepts. Automaton has 297 states and 301 transitions. Word has length 233 [2018-04-12 15:06:50,330 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:50,330 INFO L459 AbstractCegarLoop]: Abstraction has 297 states and 301 transitions. [2018-04-12 15:06:50,330 INFO L460 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-04-12 15:06:50,330 INFO L276 IsEmpty]: Start isEmpty. Operand 297 states and 301 transitions. [2018-04-12 15:06:50,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 288 [2018-04-12 15:06:50,331 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:50,331 INFO L355 BasicCegarLoop]: trace histogram [40, 34, 34, 33, 33, 33, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:50,331 INFO L408 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:50,331 INFO L82 PathProgramCache]: Analyzing trace with hash 733219996, now seen corresponding path program 9 times [2018-04-12 15:06:50,331 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:50,331 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:50,332 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:50,332 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:06:50,332 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:50,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:50,349 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:50,498 INFO L134 CoverageAnalysis]: Checked inductivity of 3918 backedges. 2257 proven. 102 refuted. 0 times theorem prover too weak. 1559 trivial. 0 not checked. [2018-04-12 15:06:50,498 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:50,498 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:50,504 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 15:06:50,570 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-04-12 15:06:50,570 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:06:50,574 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:50,782 INFO L134 CoverageAnalysis]: Checked inductivity of 3918 backedges. 2051 proven. 382 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-04-12 15:06:50,800 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:50,800 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 21] total 34 [2018-04-12 15:06:50,800 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-04-12 15:06:50,801 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-04-12 15:06:50,801 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=186, Invalid=936, Unknown=0, NotChecked=0, Total=1122 [2018-04-12 15:06:50,801 INFO L87 Difference]: Start difference. First operand 297 states and 301 transitions. Second operand 34 states. [2018-04-12 15:06:51,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:51,339 INFO L93 Difference]: Finished difference Result 316 states and 318 transitions. [2018-04-12 15:06:51,340 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-04-12 15:06:51,340 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 287 [2018-04-12 15:06:51,340 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:51,341 INFO L225 Difference]: With dead ends: 316 [2018-04-12 15:06:51,341 INFO L226 Difference]: Without dead ends: 310 [2018-04-12 15:06:51,341 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 328 GetRequests, 270 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1078 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=534, Invalid=3006, Unknown=0, NotChecked=0, Total=3540 [2018-04-12 15:06:51,342 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 310 states. [2018-04-12 15:06:51,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 310 to 303. [2018-04-12 15:06:51,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 303 states. [2018-04-12 15:06:51,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 305 transitions. [2018-04-12 15:06:51,345 INFO L78 Accepts]: Start accepts. Automaton has 303 states and 305 transitions. Word has length 287 [2018-04-12 15:06:51,345 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:51,345 INFO L459 AbstractCegarLoop]: Abstraction has 303 states and 305 transitions. [2018-04-12 15:06:51,345 INFO L460 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-04-12 15:06:51,345 INFO L276 IsEmpty]: Start isEmpty. Operand 303 states and 305 transitions. [2018-04-12 15:06:51,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 294 [2018-04-12 15:06:51,346 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:51,346 INFO L355 BasicCegarLoop]: trace histogram [41, 35, 35, 34, 34, 34, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:51,346 INFO L408 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:51,346 INFO L82 PathProgramCache]: Analyzing trace with hash 1751572516, now seen corresponding path program 10 times [2018-04-12 15:06:51,346 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:51,346 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:51,347 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:51,347 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:06:51,347 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:51,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:51,365 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:51,685 INFO L134 CoverageAnalysis]: Checked inductivity of 4132 backedges. 1344 proven. 154 refuted. 0 times theorem prover too weak. 2634 trivial. 0 not checked. [2018-04-12 15:06:51,686 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:51,686 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:51,694 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-12 15:06:51,760 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-12 15:06:51,761 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:06:51,764 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:51,766 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:06:51,767 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:06:51,769 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:06:51,769 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:06:52,068 INFO L134 CoverageAnalysis]: Checked inductivity of 4132 backedges. 1260 proven. 663 refuted. 0 times theorem prover too weak. 2209 trivial. 0 not checked. [2018-04-12 15:06:52,087 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:52,087 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 15] total 23 [2018-04-12 15:06:52,088 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-04-12 15:06:52,088 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-04-12 15:06:52,088 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=133, Invalid=419, Unknown=0, NotChecked=0, Total=552 [2018-04-12 15:06:52,088 INFO L87 Difference]: Start difference. First operand 303 states and 305 transitions. Second operand 24 states. [2018-04-12 15:06:52,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:52,361 INFO L93 Difference]: Finished difference Result 317 states and 320 transitions. [2018-04-12 15:06:52,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-04-12 15:06:52,361 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 293 [2018-04-12 15:06:52,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:52,362 INFO L225 Difference]: With dead ends: 317 [2018-04-12 15:06:52,362 INFO L226 Difference]: Without dead ends: 317 [2018-04-12 15:06:52,362 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 313 GetRequests, 270 SyntacticMatches, 13 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 258 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=225, Invalid=767, Unknown=0, NotChecked=0, Total=992 [2018-04-12 15:06:52,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 317 states. [2018-04-12 15:06:52,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 317 to 309. [2018-04-12 15:06:52,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 309 states. [2018-04-12 15:06:52,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 309 states to 309 states and 312 transitions. [2018-04-12 15:06:52,366 INFO L78 Accepts]: Start accepts. Automaton has 309 states and 312 transitions. Word has length 293 [2018-04-12 15:06:52,366 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:52,366 INFO L459 AbstractCegarLoop]: Abstraction has 309 states and 312 transitions. [2018-04-12 15:06:52,366 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-04-12 15:06:52,366 INFO L276 IsEmpty]: Start isEmpty. Operand 309 states and 312 transitions. [2018-04-12 15:06:52,367 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 300 [2018-04-12 15:06:52,367 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:52,367 INFO L355 BasicCegarLoop]: trace histogram [42, 36, 36, 35, 35, 35, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:52,367 INFO L408 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:52,368 INFO L82 PathProgramCache]: Analyzing trace with hash -1671183124, now seen corresponding path program 11 times [2018-04-12 15:06:52,368 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:52,368 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:52,368 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:52,368 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:06:52,368 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:52,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:52,385 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:52,574 INFO L134 CoverageAnalysis]: Checked inductivity of 4352 backedges. 1695 proven. 137 refuted. 0 times theorem prover too weak. 2520 trivial. 0 not checked. [2018-04-12 15:06:52,574 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:52,574 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:52,581 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-12 15:06:52,668 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2018-04-12 15:06:52,669 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:06:52,673 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:52,877 INFO L134 CoverageAnalysis]: Checked inductivity of 4352 backedges. 1624 proven. 613 refuted. 0 times theorem prover too weak. 2115 trivial. 0 not checked. [2018-04-12 15:06:52,897 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:52,897 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 24] total 34 [2018-04-12 15:06:52,897 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-04-12 15:06:52,897 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-04-12 15:06:52,898 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=223, Invalid=899, Unknown=0, NotChecked=0, Total=1122 [2018-04-12 15:06:52,898 INFO L87 Difference]: Start difference. First operand 309 states and 312 transitions. Second operand 34 states. [2018-04-12 15:06:53,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:53,384 INFO L93 Difference]: Finished difference Result 368 states and 371 transitions. [2018-04-12 15:06:53,384 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-04-12 15:06:53,384 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 299 [2018-04-12 15:06:53,385 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:53,385 INFO L225 Difference]: With dead ends: 368 [2018-04-12 15:06:53,385 INFO L226 Difference]: Without dead ends: 368 [2018-04-12 15:06:53,386 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 335 GetRequests, 286 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 473 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=549, Invalid=2001, Unknown=0, NotChecked=0, Total=2550 [2018-04-12 15:06:53,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states. [2018-04-12 15:06:53,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 363. [2018-04-12 15:06:53,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 363 states. [2018-04-12 15:06:53,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 363 states to 363 states and 366 transitions. [2018-04-12 15:06:53,391 INFO L78 Accepts]: Start accepts. Automaton has 363 states and 366 transitions. Word has length 299 [2018-04-12 15:06:53,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:53,391 INFO L459 AbstractCegarLoop]: Abstraction has 363 states and 366 transitions. [2018-04-12 15:06:53,391 INFO L460 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-04-12 15:06:53,391 INFO L276 IsEmpty]: Start isEmpty. Operand 363 states and 366 transitions. [2018-04-12 15:06:53,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 354 [2018-04-12 15:06:53,392 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:53,393 INFO L355 BasicCegarLoop]: trace histogram [50, 43, 43, 42, 42, 42, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:53,393 INFO L408 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:53,393 INFO L82 PathProgramCache]: Analyzing trace with hash 1483763557, now seen corresponding path program 12 times [2018-04-12 15:06:53,393 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:53,393 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:53,393 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:53,393 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:06:53,394 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:53,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:53,411 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:53,648 INFO L134 CoverageAnalysis]: Checked inductivity of 6223 backedges. 3357 proven. 140 refuted. 0 times theorem prover too weak. 2726 trivial. 0 not checked. [2018-04-12 15:06:53,648 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:53,648 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:53,653 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-12 15:06:53,723 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-04-12 15:06:53,724 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:06:53,728 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:53,730 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:06:53,730 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:06:53,732 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:06:53,733 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:06:54,346 INFO L134 CoverageAnalysis]: Checked inductivity of 6223 backedges. 1901 proven. 170 refuted. 0 times theorem prover too weak. 4152 trivial. 0 not checked. [2018-04-12 15:06:54,375 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:54,375 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 15] total 32 [2018-04-12 15:06:54,375 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-12 15:06:54,375 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-12 15:06:54,376 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=160, Invalid=832, Unknown=0, NotChecked=0, Total=992 [2018-04-12 15:06:54,376 INFO L87 Difference]: Start difference. First operand 363 states and 366 transitions. Second operand 32 states. [2018-04-12 15:06:56,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:56,049 INFO L93 Difference]: Finished difference Result 440 states and 442 transitions. [2018-04-12 15:06:56,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-04-12 15:06:56,049 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 353 [2018-04-12 15:06:56,050 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:56,051 INFO L225 Difference]: With dead ends: 440 [2018-04-12 15:06:56,051 INFO L226 Difference]: Without dead ends: 431 [2018-04-12 15:06:56,052 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 439 GetRequests, 336 SyntacticMatches, 13 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3306 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1497, Invalid=6875, Unknown=0, NotChecked=0, Total=8372 [2018-04-12 15:06:56,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 431 states. [2018-04-12 15:06:56,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 431 to 423. [2018-04-12 15:06:56,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 423 states. [2018-04-12 15:06:56,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 423 states to 423 states and 425 transitions. [2018-04-12 15:06:56,058 INFO L78 Accepts]: Start accepts. Automaton has 423 states and 425 transitions. Word has length 353 [2018-04-12 15:06:56,059 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:56,059 INFO L459 AbstractCegarLoop]: Abstraction has 423 states and 425 transitions. [2018-04-12 15:06:56,059 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-12 15:06:56,059 INFO L276 IsEmpty]: Start isEmpty. Operand 423 states and 425 transitions. [2018-04-12 15:06:56,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 420 [2018-04-12 15:06:56,061 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:56,062 INFO L355 BasicCegarLoop]: trace histogram [60, 52, 52, 51, 51, 51, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:56,062 INFO L408 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:56,062 INFO L82 PathProgramCache]: Analyzing trace with hash -983766034, now seen corresponding path program 13 times [2018-04-12 15:06:56,062 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:56,062 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:56,063 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:56,063 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:06:56,063 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:56,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:56,096 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:56,387 INFO L134 CoverageAnalysis]: Checked inductivity of 9062 backedges. 4485 proven. 184 refuted. 0 times theorem prover too weak. 4393 trivial. 0 not checked. [2018-04-12 15:06:56,388 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:56,388 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:56,397 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:56,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:56,514 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:56,773 INFO L134 CoverageAnalysis]: Checked inductivity of 9062 backedges. 4485 proven. 184 refuted. 0 times theorem prover too weak. 4393 trivial. 0 not checked. [2018-04-12 15:06:56,792 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:56,792 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 29 [2018-04-12 15:06:56,793 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-04-12 15:06:56,793 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-04-12 15:06:56,794 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=208, Invalid=604, Unknown=0, NotChecked=0, Total=812 [2018-04-12 15:06:56,794 INFO L87 Difference]: Start difference. First operand 423 states and 425 transitions. Second operand 29 states. [2018-04-12 15:06:57,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:57,251 INFO L93 Difference]: Finished difference Result 448 states and 450 transitions. [2018-04-12 15:06:57,251 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-04-12 15:06:57,251 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 419 [2018-04-12 15:06:57,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:57,253 INFO L225 Difference]: With dead ends: 448 [2018-04-12 15:06:57,253 INFO L226 Difference]: Without dead ends: 442 [2018-04-12 15:06:57,254 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 445 GetRequests, 411 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 379 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=306, Invalid=954, Unknown=0, NotChecked=0, Total=1260 [2018-04-12 15:06:57,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 442 states. [2018-04-12 15:06:57,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 442 to 433. [2018-04-12 15:06:57,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 433 states. [2018-04-12 15:06:57,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 435 transitions. [2018-04-12 15:06:57,264 INFO L78 Accepts]: Start accepts. Automaton has 433 states and 435 transitions. Word has length 419 [2018-04-12 15:06:57,264 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:57,265 INFO L459 AbstractCegarLoop]: Abstraction has 433 states and 435 transitions. [2018-04-12 15:06:57,265 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-04-12 15:06:57,265 INFO L276 IsEmpty]: Start isEmpty. Operand 433 states and 435 transitions. [2018-04-12 15:06:57,267 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 426 [2018-04-12 15:06:57,267 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:57,267 INFO L355 BasicCegarLoop]: trace histogram [61, 53, 53, 52, 52, 52, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:57,267 INFO L408 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:57,268 INFO L82 PathProgramCache]: Analyzing trace with hash 1494870518, now seen corresponding path program 14 times [2018-04-12 15:06:57,268 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:57,268 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:57,269 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:57,270 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:06:57,270 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:57,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:57,304 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:57,707 INFO L134 CoverageAnalysis]: Checked inductivity of 9388 backedges. 2440 proven. 200 refuted. 0 times theorem prover too weak. 6748 trivial. 0 not checked. [2018-04-12 15:06:57,707 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:57,708 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:57,717 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 15:06:57,822 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 15:06:57,823 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:06:57,829 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:57,833 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:06:57,833 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:06:57,836 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:06:57,837 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:06:58,277 INFO L134 CoverageAnalysis]: Checked inductivity of 9388 backedges. 2440 proven. 200 refuted. 0 times theorem prover too weak. 6748 trivial. 0 not checked. [2018-04-12 15:06:58,297 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:58,297 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14] total 15 [2018-04-12 15:06:58,297 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-12 15:06:58,297 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-12 15:06:58,298 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=89, Invalid=151, Unknown=0, NotChecked=0, Total=240 [2018-04-12 15:06:58,298 INFO L87 Difference]: Start difference. First operand 433 states and 435 transitions. Second operand 16 states. [2018-04-12 15:06:58,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:58,529 INFO L93 Difference]: Finished difference Result 441 states and 443 transitions. [2018-04-12 15:06:58,530 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-04-12 15:06:58,530 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 425 [2018-04-12 15:06:58,531 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:58,532 INFO L225 Difference]: With dead ends: 441 [2018-04-12 15:06:58,532 INFO L226 Difference]: Without dead ends: 441 [2018-04-12 15:06:58,533 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 447 GetRequests, 406 SyntacticMatches, 18 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 100 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=216, Invalid=384, Unknown=0, NotChecked=0, Total=600 [2018-04-12 15:06:58,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 441 states. [2018-04-12 15:06:58,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 441 to 435. [2018-04-12 15:06:58,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 435 states. [2018-04-12 15:06:58,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 437 transitions. [2018-04-12 15:06:58,539 INFO L78 Accepts]: Start accepts. Automaton has 435 states and 437 transitions. Word has length 425 [2018-04-12 15:06:58,540 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:58,540 INFO L459 AbstractCegarLoop]: Abstraction has 435 states and 437 transitions. [2018-04-12 15:06:58,540 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-12 15:06:58,540 INFO L276 IsEmpty]: Start isEmpty. Operand 435 states and 437 transitions. [2018-04-12 15:06:58,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 432 [2018-04-12 15:06:58,542 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:58,543 INFO L355 BasicCegarLoop]: trace histogram [62, 54, 54, 53, 53, 53, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:58,543 INFO L408 AbstractCegarLoop]: === Iteration 23 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:58,543 INFO L82 PathProgramCache]: Analyzing trace with hash 2009639230, now seen corresponding path program 15 times [2018-04-12 15:06:58,543 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:58,543 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:58,544 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:58,544 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:06:58,544 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:58,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:58,578 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:06:59,025 INFO L134 CoverageAnalysis]: Checked inductivity of 9720 backedges. 2720 proven. 252 refuted. 0 times theorem prover too weak. 6748 trivial. 0 not checked. [2018-04-12 15:06:59,025 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:06:59,025 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:06:59,033 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 15:06:59,195 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-04-12 15:06:59,196 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:06:59,204 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:06:59,218 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:06:59,218 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:06:59,221 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:06:59,221 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:06:59,714 INFO L134 CoverageAnalysis]: Checked inductivity of 9720 backedges. 2720 proven. 252 refuted. 0 times theorem prover too weak. 6748 trivial. 0 not checked. [2018-04-12 15:06:59,733 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:06:59,733 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15] total 16 [2018-04-12 15:06:59,733 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-04-12 15:06:59,733 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-04-12 15:06:59,734 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=170, Unknown=0, NotChecked=0, Total=272 [2018-04-12 15:06:59,734 INFO L87 Difference]: Start difference. First operand 435 states and 437 transitions. Second operand 17 states. [2018-04-12 15:06:59,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:06:59,956 INFO L93 Difference]: Finished difference Result 459 states and 463 transitions. [2018-04-12 15:06:59,963 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-12 15:06:59,963 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 431 [2018-04-12 15:06:59,963 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:06:59,964 INFO L225 Difference]: With dead ends: 459 [2018-04-12 15:06:59,964 INFO L226 Difference]: Without dead ends: 459 [2018-04-12 15:06:59,964 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 455 GetRequests, 412 SyntacticMatches, 18 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 114 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=253, Invalid=449, Unknown=0, NotChecked=0, Total=702 [2018-04-12 15:06:59,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 459 states. [2018-04-12 15:06:59,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 459 to 441. [2018-04-12 15:06:59,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 441 states. [2018-04-12 15:06:59,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 441 states to 441 states and 444 transitions. [2018-04-12 15:06:59,968 INFO L78 Accepts]: Start accepts. Automaton has 441 states and 444 transitions. Word has length 431 [2018-04-12 15:06:59,968 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:06:59,968 INFO L459 AbstractCegarLoop]: Abstraction has 441 states and 444 transitions. [2018-04-12 15:06:59,968 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-04-12 15:06:59,969 INFO L276 IsEmpty]: Start isEmpty. Operand 441 states and 444 transitions. [2018-04-12 15:06:59,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 438 [2018-04-12 15:06:59,970 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:06:59,970 INFO L355 BasicCegarLoop]: trace histogram [63, 55, 55, 54, 54, 54, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:06:59,970 INFO L408 AbstractCegarLoop]: === Iteration 24 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:06:59,970 INFO L82 PathProgramCache]: Analyzing trace with hash 49074822, now seen corresponding path program 16 times [2018-04-12 15:06:59,970 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:06:59,970 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:06:59,971 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:59,971 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:06:59,971 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:06:59,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:06:59,992 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:00,257 INFO L134 CoverageAnalysis]: Checked inductivity of 10058 backedges. 3281 proven. 229 refuted. 0 times theorem prover too weak. 6548 trivial. 0 not checked. [2018-04-12 15:07:00,257 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:00,257 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:00,266 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-12 15:07:00,371 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-12 15:07:00,371 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:00,377 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:00,742 INFO L134 CoverageAnalysis]: Checked inductivity of 10058 backedges. 3310 proven. 200 refuted. 0 times theorem prover too weak. 6548 trivial. 0 not checked. [2018-04-12 15:07:00,772 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:00,772 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 23] total 36 [2018-04-12 15:07:00,773 INFO L442 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-04-12 15:07:00,773 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-04-12 15:07:00,773 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=301, Invalid=959, Unknown=0, NotChecked=0, Total=1260 [2018-04-12 15:07:00,774 INFO L87 Difference]: Start difference. First operand 441 states and 444 transitions. Second operand 36 states. [2018-04-12 15:07:01,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:01,310 INFO L93 Difference]: Finished difference Result 527 states and 531 transitions. [2018-04-12 15:07:01,310 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-04-12 15:07:01,310 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 437 [2018-04-12 15:07:01,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:01,312 INFO L225 Difference]: With dead ends: 527 [2018-04-12 15:07:01,312 INFO L226 Difference]: Without dead ends: 527 [2018-04-12 15:07:01,312 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 479 GetRequests, 426 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 458 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=792, Invalid=2178, Unknown=0, NotChecked=0, Total=2970 [2018-04-12 15:07:01,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states. [2018-04-12 15:07:01,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 519. [2018-04-12 15:07:01,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 519 states. [2018-04-12 15:07:01,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 519 states to 519 states and 523 transitions. [2018-04-12 15:07:01,317 INFO L78 Accepts]: Start accepts. Automaton has 519 states and 523 transitions. Word has length 437 [2018-04-12 15:07:01,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:01,317 INFO L459 AbstractCegarLoop]: Abstraction has 519 states and 523 transitions. [2018-04-12 15:07:01,318 INFO L460 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-04-12 15:07:01,318 INFO L276 IsEmpty]: Start isEmpty. Operand 519 states and 523 transitions. [2018-04-12 15:07:01,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 504 [2018-04-12 15:07:01,319 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:01,319 INFO L355 BasicCegarLoop]: trace histogram [73, 64, 64, 63, 63, 63, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:01,319 INFO L408 AbstractCegarLoop]: === Iteration 25 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:01,320 INFO L82 PathProgramCache]: Analyzing trace with hash 1416226959, now seen corresponding path program 17 times [2018-04-12 15:07:01,320 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:01,320 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:01,320 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:01,320 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:01,320 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:01,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:01,345 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:01,850 INFO L134 CoverageAnalysis]: Checked inductivity of 13599 backedges. 3599 proven. 310 refuted. 0 times theorem prover too weak. 9690 trivial. 0 not checked. [2018-04-12 15:07:01,850 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:01,851 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:01,859 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-12 15:07:02,046 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2018-04-12 15:07:02,046 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:02,055 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:02,542 INFO L134 CoverageAnalysis]: Checked inductivity of 13599 backedges. 6365 proven. 1285 refuted. 0 times theorem prover too weak. 5949 trivial. 0 not checked. [2018-04-12 15:07:02,575 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:02,575 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 26] total 40 [2018-04-12 15:07:02,575 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-04-12 15:07:02,575 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-04-12 15:07:02,576 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=213, Invalid=1347, Unknown=0, NotChecked=0, Total=1560 [2018-04-12 15:07:02,576 INFO L87 Difference]: Start difference. First operand 519 states and 523 transitions. Second operand 40 states. [2018-04-12 15:07:03,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:03,775 INFO L93 Difference]: Finished difference Result 539 states and 542 transitions. [2018-04-12 15:07:03,775 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-04-12 15:07:03,775 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 503 [2018-04-12 15:07:03,775 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:03,776 INFO L225 Difference]: With dead ends: 539 [2018-04-12 15:07:03,777 INFO L226 Difference]: Without dead ends: 533 [2018-04-12 15:07:03,778 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 551 GetRequests, 480 SyntacticMatches, 1 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1148 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=898, Invalid=4214, Unknown=0, NotChecked=0, Total=5112 [2018-04-12 15:07:03,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 533 states. [2018-04-12 15:07:03,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 533 to 525. [2018-04-12 15:07:03,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 525 states. [2018-04-12 15:07:03,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 525 states to 525 states and 528 transitions. [2018-04-12 15:07:03,785 INFO L78 Accepts]: Start accepts. Automaton has 525 states and 528 transitions. Word has length 503 [2018-04-12 15:07:03,786 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:03,786 INFO L459 AbstractCegarLoop]: Abstraction has 525 states and 528 transitions. [2018-04-12 15:07:03,786 INFO L460 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-04-12 15:07:03,786 INFO L276 IsEmpty]: Start isEmpty. Operand 525 states and 528 transitions. [2018-04-12 15:07:03,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 516 [2018-04-12 15:07:03,789 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:03,789 INFO L355 BasicCegarLoop]: trace histogram [75, 66, 66, 65, 65, 65, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:03,789 INFO L408 AbstractCegarLoop]: === Iteration 26 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:03,789 INFO L82 PathProgramCache]: Analyzing trace with hash 874224735, now seen corresponding path program 18 times [2018-04-12 15:07:03,790 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:03,790 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:03,790 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:03,790 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:03,790 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:03,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:03,828 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:04,299 INFO L134 CoverageAnalysis]: Checked inductivity of 14405 backedges. 4005 proven. 374 refuted. 0 times theorem prover too weak. 10026 trivial. 0 not checked. [2018-04-12 15:07:04,299 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:04,299 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:04,304 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-12 15:07:04,468 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2018-04-12 15:07:04,468 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:04,474 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:04,496 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:07:04,496 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:07:04,499 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:07:04,500 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:07:05,365 INFO L134 CoverageAnalysis]: Checked inductivity of 14405 backedges. 4005 proven. 274 refuted. 0 times theorem prover too weak. 10126 trivial. 0 not checked. [2018-04-12 15:07:05,383 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:05,383 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 17] total 30 [2018-04-12 15:07:05,384 INFO L442 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-04-12 15:07:05,384 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-04-12 15:07:05,384 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=215, Invalid=715, Unknown=0, NotChecked=0, Total=930 [2018-04-12 15:07:05,384 INFO L87 Difference]: Start difference. First operand 525 states and 528 transitions. Second operand 31 states. [2018-04-12 15:07:06,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:06,110 INFO L93 Difference]: Finished difference Result 627 states and 633 transitions. [2018-04-12 15:07:06,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-04-12 15:07:06,110 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 515 [2018-04-12 15:07:06,110 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:06,112 INFO L225 Difference]: With dead ends: 627 [2018-04-12 15:07:06,112 INFO L226 Difference]: Without dead ends: 627 [2018-04-12 15:07:06,112 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 557 GetRequests, 482 SyntacticMatches, 20 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1103 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=790, Invalid=2402, Unknown=0, NotChecked=0, Total=3192 [2018-04-12 15:07:06,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 627 states. [2018-04-12 15:07:06,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 627 to 603. [2018-04-12 15:07:06,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 603 states. [2018-04-12 15:07:06,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 603 states to 603 states and 608 transitions. [2018-04-12 15:07:06,117 INFO L78 Accepts]: Start accepts. Automaton has 603 states and 608 transitions. Word has length 515 [2018-04-12 15:07:06,117 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:06,117 INFO L459 AbstractCegarLoop]: Abstraction has 603 states and 608 transitions. [2018-04-12 15:07:06,117 INFO L460 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-04-12 15:07:06,117 INFO L276 IsEmpty]: Start isEmpty. Operand 603 states and 608 transitions. [2018-04-12 15:07:06,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 594 [2018-04-12 15:07:06,119 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:06,120 INFO L355 BasicCegarLoop]: trace histogram [87, 77, 77, 76, 76, 76, 11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:06,120 INFO L408 AbstractCegarLoop]: === Iteration 27 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:06,120 INFO L82 PathProgramCache]: Analyzing trace with hash 1350141368, now seen corresponding path program 19 times [2018-04-12 15:07:06,120 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:06,120 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:06,120 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:06,121 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:06,121 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:06,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:06,148 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:06,454 INFO L134 CoverageAnalysis]: Checked inductivity of 19534 backedges. 9017 proven. 290 refuted. 0 times theorem prover too weak. 10227 trivial. 0 not checked. [2018-04-12 15:07:06,454 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:06,454 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:06,459 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:07:06,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:06,557 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:06,908 INFO L134 CoverageAnalysis]: Checked inductivity of 19534 backedges. 9017 proven. 290 refuted. 0 times theorem prover too weak. 10227 trivial. 0 not checked. [2018-04-12 15:07:06,926 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:06,926 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 35 [2018-04-12 15:07:06,927 INFO L442 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-04-12 15:07:06,927 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-04-12 15:07:06,927 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=298, Invalid=892, Unknown=0, NotChecked=0, Total=1190 [2018-04-12 15:07:06,928 INFO L87 Difference]: Start difference. First operand 603 states and 608 transitions. Second operand 35 states. [2018-04-12 15:07:07,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:07,149 INFO L93 Difference]: Finished difference Result 622 states and 626 transitions. [2018-04-12 15:07:07,150 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-04-12 15:07:07,150 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 593 [2018-04-12 15:07:07,150 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:07,152 INFO L225 Difference]: With dead ends: 622 [2018-04-12 15:07:07,152 INFO L226 Difference]: Without dead ends: 616 [2018-04-12 15:07:07,153 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 625 GetRequests, 583 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 595 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=451, Invalid=1441, Unknown=0, NotChecked=0, Total=1892 [2018-04-12 15:07:07,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 616 states. [2018-04-12 15:07:07,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 616 to 609. [2018-04-12 15:07:07,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 609 states. [2018-04-12 15:07:07,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 609 states and 613 transitions. [2018-04-12 15:07:07,163 INFO L78 Accepts]: Start accepts. Automaton has 609 states and 613 transitions. Word has length 593 [2018-04-12 15:07:07,163 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:07,163 INFO L459 AbstractCegarLoop]: Abstraction has 609 states and 613 transitions. [2018-04-12 15:07:07,163 INFO L460 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-04-12 15:07:07,163 INFO L276 IsEmpty]: Start isEmpty. Operand 609 states and 613 transitions. [2018-04-12 15:07:07,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 600 [2018-04-12 15:07:07,166 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:07,166 INFO L355 BasicCegarLoop]: trace histogram [88, 78, 78, 77, 77, 77, 11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:07,166 INFO L408 AbstractCegarLoop]: === Iteration 28 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:07,166 INFO L82 PathProgramCache]: Analyzing trace with hash -46382016, now seen corresponding path program 20 times [2018-04-12 15:07:07,166 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:07,166 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:07,167 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:07,167 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:07:07,167 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:07,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:07,193 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:07,644 INFO L134 CoverageAnalysis]: Checked inductivity of 20014 backedges. 5619 proven. 345 refuted. 0 times theorem prover too weak. 14050 trivial. 0 not checked. [2018-04-12 15:07:07,644 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:07,644 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:07,652 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 15:07:07,751 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 15:07:07,751 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:07,756 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:08,385 INFO L134 CoverageAnalysis]: Checked inductivity of 20014 backedges. 5584 proven. 380 refuted. 0 times theorem prover too weak. 14050 trivial. 0 not checked. [2018-04-12 15:07:08,415 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:08,416 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 29] total 56 [2018-04-12 15:07:08,416 INFO L442 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-04-12 15:07:08,416 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-04-12 15:07:08,417 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=532, Invalid=2548, Unknown=0, NotChecked=0, Total=3080 [2018-04-12 15:07:08,417 INFO L87 Difference]: Start difference. First operand 609 states and 613 transitions. Second operand 56 states. [2018-04-12 15:07:09,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:09,288 INFO L93 Difference]: Finished difference Result 710 states and 715 transitions. [2018-04-12 15:07:09,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-04-12 15:07:09,288 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 599 [2018-04-12 15:07:09,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:09,290 INFO L225 Difference]: With dead ends: 710 [2018-04-12 15:07:09,290 INFO L226 Difference]: Without dead ends: 710 [2018-04-12 15:07:09,291 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 651 GetRequests, 572 SyntacticMatches, 0 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1747 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1310, Invalid=5170, Unknown=0, NotChecked=0, Total=6480 [2018-04-12 15:07:09,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 710 states. [2018-04-12 15:07:09,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 710 to 699. [2018-04-12 15:07:09,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 699 states. [2018-04-12 15:07:09,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 699 states to 699 states and 704 transitions. [2018-04-12 15:07:09,300 INFO L78 Accepts]: Start accepts. Automaton has 699 states and 704 transitions. Word has length 599 [2018-04-12 15:07:09,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:09,301 INFO L459 AbstractCegarLoop]: Abstraction has 699 states and 704 transitions. [2018-04-12 15:07:09,301 INFO L460 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-04-12 15:07:09,301 INFO L276 IsEmpty]: Start isEmpty. Operand 699 states and 704 transitions. [2018-04-12 15:07:09,305 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 678 [2018-04-12 15:07:09,305 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:09,306 INFO L355 BasicCegarLoop]: trace histogram [100, 89, 89, 88, 88, 88, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:09,306 INFO L408 AbstractCegarLoop]: === Iteration 29 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:09,306 INFO L82 PathProgramCache]: Analyzing trace with hash -1742682151, now seen corresponding path program 21 times [2018-04-12 15:07:09,306 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:09,306 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:09,307 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:09,307 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:09,307 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:09,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:09,351 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:09,819 INFO L134 CoverageAnalysis]: Checked inductivity of 25993 backedges. 14286 proven. 1218 refuted. 0 times theorem prover too weak. 10489 trivial. 0 not checked. [2018-04-12 15:07:09,820 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:09,820 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:09,825 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 15:07:09,966 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-04-12 15:07:09,966 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:09,971 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:10,515 INFO L134 CoverageAnalysis]: Checked inductivity of 25993 backedges. 10431 proven. 1192 refuted. 0 times theorem prover too weak. 14370 trivial. 0 not checked. [2018-04-12 15:07:10,533 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:10,533 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 31] total 58 [2018-04-12 15:07:10,534 INFO L442 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-04-12 15:07:10,534 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-04-12 15:07:10,534 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=470, Invalid=2836, Unknown=0, NotChecked=0, Total=3306 [2018-04-12 15:07:10,534 INFO L87 Difference]: Start difference. First operand 699 states and 704 transitions. Second operand 58 states. [2018-04-12 15:07:12,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:12,091 INFO L93 Difference]: Finished difference Result 799 states and 803 transitions. [2018-04-12 15:07:12,091 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-04-12 15:07:12,091 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 677 [2018-04-12 15:07:12,092 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:12,093 INFO L225 Difference]: With dead ends: 799 [2018-04-12 15:07:12,093 INFO L226 Difference]: Without dead ends: 793 [2018-04-12 15:07:12,094 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 760 GetRequests, 651 SyntacticMatches, 0 SemanticMatches, 109 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3673 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1946, Invalid=10264, Unknown=0, NotChecked=0, Total=12210 [2018-04-12 15:07:12,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 793 states. [2018-04-12 15:07:12,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 793 to 699. [2018-04-12 15:07:12,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 699 states. [2018-04-12 15:07:12,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 699 states to 699 states and 702 transitions. [2018-04-12 15:07:12,101 INFO L78 Accepts]: Start accepts. Automaton has 699 states and 702 transitions. Word has length 677 [2018-04-12 15:07:12,102 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:12,102 INFO L459 AbstractCegarLoop]: Abstraction has 699 states and 702 transitions. [2018-04-12 15:07:12,102 INFO L460 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-04-12 15:07:12,102 INFO L276 IsEmpty]: Start isEmpty. Operand 699 states and 702 transitions. [2018-04-12 15:07:12,106 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 684 [2018-04-12 15:07:12,106 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:12,107 INFO L355 BasicCegarLoop]: trace histogram [101, 90, 90, 89, 89, 89, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:12,107 INFO L408 AbstractCegarLoop]: === Iteration 30 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:12,107 INFO L82 PathProgramCache]: Analyzing trace with hash -661149279, now seen corresponding path program 22 times [2018-04-12 15:07:12,107 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:12,107 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:12,108 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:12,108 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:12,108 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:12,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:12,156 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:12,808 INFO L134 CoverageAnalysis]: Checked inductivity of 26547 backedges. 6149 proven. 444 refuted. 0 times theorem prover too weak. 19954 trivial. 0 not checked. [2018-04-12 15:07:12,809 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:12,809 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:12,814 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-12 15:07:12,948 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-12 15:07:12,948 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:12,956 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:12,958 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:07:12,958 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:07:12,960 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:07:12,960 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:07:13,821 INFO L134 CoverageAnalysis]: Checked inductivity of 26547 backedges. 6015 proven. 1768 refuted. 0 times theorem prover too weak. 18764 trivial. 0 not checked. [2018-04-12 15:07:13,851 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:13,851 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 20] total 33 [2018-04-12 15:07:13,852 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-04-12 15:07:13,852 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-04-12 15:07:13,852 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=268, Invalid=854, Unknown=0, NotChecked=0, Total=1122 [2018-04-12 15:07:13,852 INFO L87 Difference]: Start difference. First operand 699 states and 702 transitions. Second operand 34 states. [2018-04-12 15:07:14,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:14,417 INFO L93 Difference]: Finished difference Result 716 states and 720 transitions. [2018-04-12 15:07:14,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-04-12 15:07:14,417 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 683 [2018-04-12 15:07:14,417 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:14,418 INFO L225 Difference]: With dead ends: 716 [2018-04-12 15:07:14,418 INFO L226 Difference]: Without dead ends: 716 [2018-04-12 15:07:14,419 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 713 GetRequests, 645 SyntacticMatches, 23 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 618 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=450, Invalid=1712, Unknown=0, NotChecked=0, Total=2162 [2018-04-12 15:07:14,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 716 states. [2018-04-12 15:07:14,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 716 to 705. [2018-04-12 15:07:14,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 705 states. [2018-04-12 15:07:14,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 705 states to 705 states and 709 transitions. [2018-04-12 15:07:14,423 INFO L78 Accepts]: Start accepts. Automaton has 705 states and 709 transitions. Word has length 683 [2018-04-12 15:07:14,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:14,424 INFO L459 AbstractCegarLoop]: Abstraction has 705 states and 709 transitions. [2018-04-12 15:07:14,424 INFO L460 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-04-12 15:07:14,424 INFO L276 IsEmpty]: Start isEmpty. Operand 705 states and 709 transitions. [2018-04-12 15:07:14,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 690 [2018-04-12 15:07:14,427 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:14,427 INFO L355 BasicCegarLoop]: trace histogram [102, 91, 91, 90, 90, 90, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:14,427 INFO L408 AbstractCegarLoop]: === Iteration 31 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:14,427 INFO L82 PathProgramCache]: Analyzing trace with hash -1048265559, now seen corresponding path program 23 times [2018-04-12 15:07:14,427 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:14,427 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:14,428 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:14,428 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:14,428 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:14,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:14,457 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:14,941 INFO L134 CoverageAnalysis]: Checked inductivity of 27107 backedges. 7115 proven. 412 refuted. 0 times theorem prover too weak. 19580 trivial. 0 not checked. [2018-04-12 15:07:14,941 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:14,941 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:14,946 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-12 15:07:15,210 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 27 check-sat command(s) [2018-04-12 15:07:15,210 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:15,217 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:15,598 INFO L134 CoverageAnalysis]: Checked inductivity of 27107 backedges. 7153 proven. 374 refuted. 0 times theorem prover too weak. 19580 trivial. 0 not checked. [2018-04-12 15:07:15,618 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:15,618 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 45 [2018-04-12 15:07:15,619 INFO L442 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-04-12 15:07:15,620 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-04-12 15:07:15,620 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=466, Invalid=1514, Unknown=0, NotChecked=0, Total=1980 [2018-04-12 15:07:15,620 INFO L87 Difference]: Start difference. First operand 705 states and 709 transitions. Second operand 45 states. [2018-04-12 15:07:16,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:16,391 INFO L93 Difference]: Finished difference Result 806 states and 811 transitions. [2018-04-12 15:07:16,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-04-12 15:07:16,391 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 689 [2018-04-12 15:07:16,392 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:16,393 INFO L225 Difference]: With dead ends: 806 [2018-04-12 15:07:16,393 INFO L226 Difference]: Without dead ends: 806 [2018-04-12 15:07:16,393 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 743 GetRequests, 675 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 773 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1263, Invalid=3567, Unknown=0, NotChecked=0, Total=4830 [2018-04-12 15:07:16,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 806 states. [2018-04-12 15:07:16,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 806 to 795. [2018-04-12 15:07:16,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 795 states. [2018-04-12 15:07:16,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 795 states to 795 states and 800 transitions. [2018-04-12 15:07:16,402 INFO L78 Accepts]: Start accepts. Automaton has 795 states and 800 transitions. Word has length 689 [2018-04-12 15:07:16,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:16,402 INFO L459 AbstractCegarLoop]: Abstraction has 795 states and 800 transitions. [2018-04-12 15:07:16,403 INFO L460 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-04-12 15:07:16,403 INFO L276 IsEmpty]: Start isEmpty. Operand 795 states and 800 transitions. [2018-04-12 15:07:16,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 774 [2018-04-12 15:07:16,408 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:16,408 INFO L355 BasicCegarLoop]: trace histogram [115, 103, 103, 102, 102, 102, 13, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:16,408 INFO L408 AbstractCegarLoop]: === Iteration 32 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:16,409 INFO L82 PathProgramCache]: Analyzing trace with hash 1462874826, now seen corresponding path program 24 times [2018-04-12 15:07:16,409 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:16,409 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:16,410 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:16,410 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:16,410 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:16,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:16,461 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:16,994 INFO L134 CoverageAnalysis]: Checked inductivity of 34638 backedges. 17188 proven. 2197 refuted. 0 times theorem prover too weak. 15253 trivial. 0 not checked. [2018-04-12 15:07:16,994 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:16,994 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:17,000 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-12 15:07:17,258 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2018-04-12 15:07:17,258 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:17,265 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:17,267 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:07:17,267 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:07:17,269 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:07:17,269 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:07:18,706 INFO L134 CoverageAnalysis]: Checked inductivity of 34638 backedges. 7646 proven. 470 refuted. 0 times theorem prover too weak. 26522 trivial. 0 not checked. [2018-04-12 15:07:18,725 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:18,725 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 20] total 51 [2018-04-12 15:07:18,726 INFO L442 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-04-12 15:07:18,726 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-04-12 15:07:18,726 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=345, Invalid=2205, Unknown=0, NotChecked=0, Total=2550 [2018-04-12 15:07:18,726 INFO L87 Difference]: Start difference. First operand 795 states and 800 transitions. Second operand 51 states. [2018-04-12 15:07:20,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:20,998 INFO L93 Difference]: Finished difference Result 914 states and 919 transitions. [2018-04-12 15:07:20,999 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-04-12 15:07:20,999 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 773 [2018-04-12 15:07:20,999 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:21,000 INFO L225 Difference]: With dead ends: 914 [2018-04-12 15:07:21,000 INFO L226 Difference]: Without dead ends: 905 [2018-04-12 15:07:21,001 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 869 GetRequests, 733 SyntacticMatches, 23 SemanticMatches, 113 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4692 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1823, Invalid=11287, Unknown=0, NotChecked=0, Total=13110 [2018-04-12 15:07:21,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 905 states. [2018-04-12 15:07:21,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 905 to 885. [2018-04-12 15:07:21,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 885 states. [2018-04-12 15:07:21,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 885 states to 885 states and 889 transitions. [2018-04-12 15:07:21,006 INFO L78 Accepts]: Start accepts. Automaton has 885 states and 889 transitions. Word has length 773 [2018-04-12 15:07:21,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:21,007 INFO L459 AbstractCegarLoop]: Abstraction has 885 states and 889 transitions. [2018-04-12 15:07:21,007 INFO L460 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-04-12 15:07:21,007 INFO L276 IsEmpty]: Start isEmpty. Operand 885 states and 889 transitions. [2018-04-12 15:07:21,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 870 [2018-04-12 15:07:21,011 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:21,011 INFO L355 BasicCegarLoop]: trace histogram [130, 117, 117, 116, 116, 116, 14, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:21,011 INFO L408 AbstractCegarLoop]: === Iteration 33 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:21,011 INFO L82 PathProgramCache]: Analyzing trace with hash 593559995, now seen corresponding path program 25 times [2018-04-12 15:07:21,011 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:21,011 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:21,012 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:21,012 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:21,012 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:21,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:21,046 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:21,580 INFO L134 CoverageAnalysis]: Checked inductivity of 44527 backedges. 19928 proven. 3250 refuted. 0 times theorem prover too weak. 21349 trivial. 0 not checked. [2018-04-12 15:07:21,581 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:21,581 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:21,587 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:07:21,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:21,713 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:22,261 INFO L134 CoverageAnalysis]: Checked inductivity of 44527 backedges. 16915 proven. 494 refuted. 0 times theorem prover too weak. 27118 trivial. 0 not checked. [2018-04-12 15:07:22,280 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:22,296 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 30] total 57 [2018-04-12 15:07:22,297 INFO L442 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-04-12 15:07:22,297 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-04-12 15:07:22,297 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=544, Invalid=2648, Unknown=0, NotChecked=0, Total=3192 [2018-04-12 15:07:22,297 INFO L87 Difference]: Start difference. First operand 885 states and 889 transitions. Second operand 57 states. [2018-04-12 15:07:23,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:23,678 INFO L93 Difference]: Finished difference Result 916 states and 920 transitions. [2018-04-12 15:07:23,679 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-04-12 15:07:23,679 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 869 [2018-04-12 15:07:23,679 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:23,680 INFO L225 Difference]: With dead ends: 916 [2018-04-12 15:07:23,680 INFO L226 Difference]: Without dead ends: 910 [2018-04-12 15:07:23,681 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 942 GetRequests, 849 SyntacticMatches, 0 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2757 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1566, Invalid=7364, Unknown=0, NotChecked=0, Total=8930 [2018-04-12 15:07:23,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 910 states. [2018-04-12 15:07:23,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 910 to 895. [2018-04-12 15:07:23,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 895 states. [2018-04-12 15:07:23,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 895 states to 895 states and 899 transitions. [2018-04-12 15:07:23,687 INFO L78 Accepts]: Start accepts. Automaton has 895 states and 899 transitions. Word has length 869 [2018-04-12 15:07:23,687 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:23,688 INFO L459 AbstractCegarLoop]: Abstraction has 895 states and 899 transitions. [2018-04-12 15:07:23,688 INFO L460 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-04-12 15:07:23,688 INFO L276 IsEmpty]: Start isEmpty. Operand 895 states and 899 transitions. [2018-04-12 15:07:23,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 876 [2018-04-12 15:07:23,692 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:23,692 INFO L355 BasicCegarLoop]: trace histogram [131, 118, 118, 117, 117, 117, 14, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:23,692 INFO L408 AbstractCegarLoop]: === Iteration 34 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:23,692 INFO L82 PathProgramCache]: Analyzing trace with hash -753671677, now seen corresponding path program 26 times [2018-04-12 15:07:23,692 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:23,692 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:23,693 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:23,693 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:07:23,693 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:23,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:23,730 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:24,459 INFO L134 CoverageAnalysis]: Checked inductivity of 45253 backedges. 8905 proven. 520 refuted. 0 times theorem prover too weak. 35828 trivial. 0 not checked. [2018-04-12 15:07:24,459 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:24,459 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:24,464 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 15:07:24,598 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 15:07:24,598 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:24,606 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:24,607 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:07:24,608 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:07:24,609 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:07:24,609 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:07:25,605 INFO L134 CoverageAnalysis]: Checked inductivity of 45253 backedges. 8905 proven. 520 refuted. 0 times theorem prover too weak. 35828 trivial. 0 not checked. [2018-04-12 15:07:25,623 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:25,623 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19] total 20 [2018-04-12 15:07:25,624 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-04-12 15:07:25,624 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-04-12 15:07:25,624 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=164, Invalid=256, Unknown=0, NotChecked=0, Total=420 [2018-04-12 15:07:25,624 INFO L87 Difference]: Start difference. First operand 895 states and 899 transitions. Second operand 21 states. [2018-04-12 15:07:25,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:25,921 INFO L93 Difference]: Finished difference Result 909 states and 913 transitions. [2018-04-12 15:07:25,921 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-04-12 15:07:25,921 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 875 [2018-04-12 15:07:25,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:25,923 INFO L225 Difference]: With dead ends: 909 [2018-04-12 15:07:25,923 INFO L226 Difference]: Without dead ends: 909 [2018-04-12 15:07:25,923 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 907 GetRequests, 846 SyntacticMatches, 28 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 195 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=431, Invalid=759, Unknown=0, NotChecked=0, Total=1190 [2018-04-12 15:07:25,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 909 states. [2018-04-12 15:07:25,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 909 to 897. [2018-04-12 15:07:25,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 897 states. [2018-04-12 15:07:25,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 897 states to 897 states and 901 transitions. [2018-04-12 15:07:25,928 INFO L78 Accepts]: Start accepts. Automaton has 897 states and 901 transitions. Word has length 875 [2018-04-12 15:07:25,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:25,929 INFO L459 AbstractCegarLoop]: Abstraction has 897 states and 901 transitions. [2018-04-12 15:07:25,929 INFO L460 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-04-12 15:07:25,929 INFO L276 IsEmpty]: Start isEmpty. Operand 897 states and 901 transitions. [2018-04-12 15:07:25,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 882 [2018-04-12 15:07:25,932 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:25,933 INFO L355 BasicCegarLoop]: trace histogram [132, 119, 119, 118, 118, 118, 14, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:25,933 INFO L408 AbstractCegarLoop]: === Iteration 35 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:25,933 INFO L82 PathProgramCache]: Analyzing trace with hash -1944476789, now seen corresponding path program 27 times [2018-04-12 15:07:25,933 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:25,933 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:25,933 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:25,934 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:25,934 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:25,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:25,969 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:26,645 INFO L134 CoverageAnalysis]: Checked inductivity of 45985 backedges. 9555 proven. 602 refuted. 0 times theorem prover too weak. 35828 trivial. 0 not checked. [2018-04-12 15:07:26,646 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:26,646 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:26,651 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 15:07:26,861 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-04-12 15:07:26,861 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:26,867 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:26,868 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:07:26,869 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:07:26,881 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:07:26,882 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:07:27,775 INFO L134 CoverageAnalysis]: Checked inductivity of 45985 backedges. 9555 proven. 602 refuted. 0 times theorem prover too weak. 35828 trivial. 0 not checked. [2018-04-12 15:07:27,794 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:27,794 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20] total 21 [2018-04-12 15:07:27,795 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-04-12 15:07:27,795 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-04-12 15:07:27,795 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=182, Invalid=280, Unknown=0, NotChecked=0, Total=462 [2018-04-12 15:07:27,795 INFO L87 Difference]: Start difference. First operand 897 states and 901 transitions. Second operand 22 states. [2018-04-12 15:07:28,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:28,135 INFO L93 Difference]: Finished difference Result 927 states and 933 transitions. [2018-04-12 15:07:28,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-04-12 15:07:28,135 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 881 [2018-04-12 15:07:28,136 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:28,137 INFO L225 Difference]: With dead ends: 927 [2018-04-12 15:07:28,137 INFO L226 Difference]: Without dead ends: 927 [2018-04-12 15:07:28,137 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 915 GetRequests, 852 SyntacticMatches, 28 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 214 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=483, Invalid=849, Unknown=0, NotChecked=0, Total=1332 [2018-04-12 15:07:28,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 927 states. [2018-04-12 15:07:28,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 927 to 903. [2018-04-12 15:07:28,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 903 states. [2018-04-12 15:07:28,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 903 states to 903 states and 908 transitions. [2018-04-12 15:07:28,141 INFO L78 Accepts]: Start accepts. Automaton has 903 states and 908 transitions. Word has length 881 [2018-04-12 15:07:28,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:28,141 INFO L459 AbstractCegarLoop]: Abstraction has 903 states and 908 transitions. [2018-04-12 15:07:28,141 INFO L460 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-04-12 15:07:28,141 INFO L276 IsEmpty]: Start isEmpty. Operand 903 states and 908 transitions. [2018-04-12 15:07:28,145 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 888 [2018-04-12 15:07:28,145 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:28,145 INFO L355 BasicCegarLoop]: trace histogram [133, 120, 120, 119, 119, 119, 14, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:28,145 INFO L408 AbstractCegarLoop]: === Iteration 36 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:28,146 INFO L82 PathProgramCache]: Analyzing trace with hash 1515855635, now seen corresponding path program 28 times [2018-04-12 15:07:28,146 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:28,146 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:28,146 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:28,146 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:28,146 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:28,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:28,201 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:28,845 INFO L134 CoverageAnalysis]: Checked inductivity of 46723 backedges. 10851 proven. 564 refuted. 0 times theorem prover too weak. 35308 trivial. 0 not checked. [2018-04-12 15:07:28,846 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:28,846 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:28,851 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-12 15:07:28,957 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-12 15:07:28,957 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:28,963 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:29,490 INFO L134 CoverageAnalysis]: Checked inductivity of 46723 backedges. 10895 proven. 520 refuted. 0 times theorem prover too weak. 35308 trivial. 0 not checked. [2018-04-12 15:07:29,509 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:29,509 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 33] total 51 [2018-04-12 15:07:29,510 INFO L442 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-04-12 15:07:29,510 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-04-12 15:07:29,510 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=596, Invalid=1954, Unknown=0, NotChecked=0, Total=2550 [2018-04-12 15:07:29,510 INFO L87 Difference]: Start difference. First operand 903 states and 908 transitions. Second operand 51 states. [2018-04-12 15:07:30,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:30,419 INFO L93 Difference]: Finished difference Result 1025 states and 1031 transitions. [2018-04-12 15:07:30,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-04-12 15:07:30,420 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 887 [2018-04-12 15:07:30,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:30,422 INFO L225 Difference]: With dead ends: 1025 [2018-04-12 15:07:30,422 INFO L226 Difference]: Without dead ends: 1025 [2018-04-12 15:07:30,422 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 949 GetRequests, 871 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1028 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1637, Invalid=4683, Unknown=0, NotChecked=0, Total=6320 [2018-04-12 15:07:30,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1025 states. [2018-04-12 15:07:30,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1025 to 1011. [2018-04-12 15:07:30,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1011 states. [2018-04-12 15:07:30,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1011 states to 1011 states and 1017 transitions. [2018-04-12 15:07:30,429 INFO L78 Accepts]: Start accepts. Automaton has 1011 states and 1017 transitions. Word has length 887 [2018-04-12 15:07:30,429 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:30,429 INFO L459 AbstractCegarLoop]: Abstraction has 1011 states and 1017 transitions. [2018-04-12 15:07:30,429 INFO L460 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-04-12 15:07:30,429 INFO L276 IsEmpty]: Start isEmpty. Operand 1011 states and 1017 transitions. [2018-04-12 15:07:30,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 984 [2018-04-12 15:07:30,434 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:30,434 INFO L355 BasicCegarLoop]: trace histogram [148, 134, 134, 133, 133, 133, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:30,434 INFO L408 AbstractCegarLoop]: === Iteration 37 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:30,435 INFO L82 PathProgramCache]: Analyzing trace with hash 951248836, now seen corresponding path program 29 times [2018-04-12 15:07:30,435 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:30,435 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:30,435 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:30,435 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:30,435 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:30,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:30,473 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:31,189 INFO L134 CoverageAnalysis]: Checked inductivity of 58114 backedges. 24474 proven. 4377 refuted. 0 times theorem prover too weak. 29263 trivial. 0 not checked. [2018-04-12 15:07:31,189 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:31,189 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:31,195 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-12 15:07:31,736 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2018-04-12 15:07:31,736 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:31,746 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:32,425 INFO L134 CoverageAnalysis]: Checked inductivity of 58114 backedges. 21295 proven. 2980 refuted. 0 times theorem prover too weak. 33839 trivial. 0 not checked. [2018-04-12 15:07:32,446 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:32,447 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 63 [2018-04-12 15:07:32,447 INFO L442 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-04-12 15:07:32,447 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-04-12 15:07:32,447 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=613, Invalid=3293, Unknown=0, NotChecked=0, Total=3906 [2018-04-12 15:07:32,448 INFO L87 Difference]: Start difference. First operand 1011 states and 1017 transitions. Second operand 63 states. [2018-04-12 15:07:33,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:33,858 INFO L93 Difference]: Finished difference Result 1028 states and 1032 transitions. [2018-04-12 15:07:33,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-04-12 15:07:33,858 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 983 [2018-04-12 15:07:33,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:33,860 INFO L225 Difference]: With dead ends: 1028 [2018-04-12 15:07:33,860 INFO L226 Difference]: Without dead ends: 1022 [2018-04-12 15:07:33,861 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1062 GetRequests, 958 SyntacticMatches, 0 SemanticMatches, 104 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3379 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=2021, Invalid=9109, Unknown=0, NotChecked=0, Total=11130 [2018-04-12 15:07:33,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1022 states. [2018-04-12 15:07:33,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1022 to 1011. [2018-04-12 15:07:33,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1011 states. [2018-04-12 15:07:33,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1011 states to 1011 states and 1015 transitions. [2018-04-12 15:07:33,867 INFO L78 Accepts]: Start accepts. Automaton has 1011 states and 1015 transitions. Word has length 983 [2018-04-12 15:07:33,868 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:33,868 INFO L459 AbstractCegarLoop]: Abstraction has 1011 states and 1015 transitions. [2018-04-12 15:07:33,868 INFO L460 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-04-12 15:07:33,868 INFO L276 IsEmpty]: Start isEmpty. Operand 1011 states and 1015 transitions. [2018-04-12 15:07:33,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 990 [2018-04-12 15:07:33,872 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:33,873 INFO L355 BasicCegarLoop]: trace histogram [149, 135, 135, 134, 134, 134, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:33,873 INFO L408 AbstractCegarLoop]: === Iteration 38 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:33,873 INFO L82 PathProgramCache]: Analyzing trace with hash 1557282124, now seen corresponding path program 30 times [2018-04-12 15:07:33,873 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:33,873 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:33,873 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:33,874 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:33,874 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:33,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:33,918 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:34,643 INFO L134 CoverageAnalysis]: Checked inductivity of 58944 backedges. 11648 proven. 690 refuted. 0 times theorem prover too weak. 46606 trivial. 0 not checked. [2018-04-12 15:07:34,643 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:34,643 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:34,648 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-12 15:07:35,109 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 24 check-sat command(s) [2018-04-12 15:07:35,109 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:35,118 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:35,123 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:07:35,123 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:07:35,125 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:07:35,125 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:07:36,706 INFO L134 CoverageAnalysis]: Checked inductivity of 58944 backedges. 11648 proven. 632 refuted. 0 times theorem prover too weak. 46664 trivial. 0 not checked. [2018-04-12 15:07:36,725 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:36,725 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 22] total 38 [2018-04-12 15:07:36,726 INFO L442 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-04-12 15:07:36,726 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-04-12 15:07:36,726 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=354, Invalid=1128, Unknown=0, NotChecked=0, Total=1482 [2018-04-12 15:07:36,726 INFO L87 Difference]: Start difference. First operand 1011 states and 1015 transitions. Second operand 39 states. [2018-04-12 15:07:37,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:37,757 INFO L93 Difference]: Finished difference Result 1145 states and 1152 transitions. [2018-04-12 15:07:37,757 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-04-12 15:07:37,757 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 989 [2018-04-12 15:07:37,757 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:37,759 INFO L225 Difference]: With dead ends: 1145 [2018-04-12 15:07:37,759 INFO L226 Difference]: Without dead ends: 1145 [2018-04-12 15:07:37,759 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1044 GetRequests, 942 SyntacticMatches, 30 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2035 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1264, Invalid=4138, Unknown=0, NotChecked=0, Total=5402 [2018-04-12 15:07:37,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1145 states. [2018-04-12 15:07:37,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1145 to 1119. [2018-04-12 15:07:37,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1119 states. [2018-04-12 15:07:37,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1119 states to 1119 states and 1125 transitions. [2018-04-12 15:07:37,765 INFO L78 Accepts]: Start accepts. Automaton has 1119 states and 1125 transitions. Word has length 989 [2018-04-12 15:07:37,766 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:37,766 INFO L459 AbstractCegarLoop]: Abstraction has 1119 states and 1125 transitions. [2018-04-12 15:07:37,766 INFO L460 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-04-12 15:07:37,766 INFO L276 IsEmpty]: Start isEmpty. Operand 1119 states and 1125 transitions. [2018-04-12 15:07:37,771 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1098 [2018-04-12 15:07:37,771 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:37,771 INFO L355 BasicCegarLoop]: trace histogram [166, 151, 151, 150, 150, 150, 16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:37,771 INFO L408 AbstractCegarLoop]: === Iteration 39 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:37,772 INFO L82 PathProgramCache]: Analyzing trace with hash 890947789, now seen corresponding path program 31 times [2018-04-12 15:07:37,772 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:37,772 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:37,772 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:37,772 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:37,772 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:37,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:37,814 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:38,605 INFO L134 CoverageAnalysis]: Checked inductivity of 73515 backedges. 28930 proven. 5578 refuted. 0 times theorem prover too weak. 39007 trivial. 0 not checked. [2018-04-12 15:07:38,605 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:38,605 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:38,611 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:07:38,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:38,771 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:39,528 INFO L134 CoverageAnalysis]: Checked inductivity of 73515 backedges. 26053 proven. 660 refuted. 0 times theorem prover too weak. 46802 trivial. 0 not checked. [2018-04-12 15:07:39,547 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:39,547 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 34] total 63 [2018-04-12 15:07:39,548 INFO L442 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-04-12 15:07:39,548 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-04-12 15:07:39,548 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=674, Invalid=3232, Unknown=0, NotChecked=0, Total=3906 [2018-04-12 15:07:39,549 INFO L87 Difference]: Start difference. First operand 1119 states and 1125 transitions. Second operand 63 states. [2018-04-12 15:07:40,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:40,996 INFO L93 Difference]: Finished difference Result 1146 states and 1151 transitions. [2018-04-12 15:07:40,996 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-04-12 15:07:40,997 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 1097 [2018-04-12 15:07:40,997 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:40,999 INFO L225 Difference]: With dead ends: 1146 [2018-04-12 15:07:40,999 INFO L226 Difference]: Without dead ends: 1140 [2018-04-12 15:07:40,999 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1177 GetRequests, 1074 SyntacticMatches, 0 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3452 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1947, Invalid=8973, Unknown=0, NotChecked=0, Total=10920 [2018-04-12 15:07:41,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1140 states. [2018-04-12 15:07:41,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1140 to 1125. [2018-04-12 15:07:41,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1125 states. [2018-04-12 15:07:41,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1125 states to 1125 states and 1130 transitions. [2018-04-12 15:07:41,005 INFO L78 Accepts]: Start accepts. Automaton has 1125 states and 1130 transitions. Word has length 1097 [2018-04-12 15:07:41,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:41,006 INFO L459 AbstractCegarLoop]: Abstraction has 1125 states and 1130 transitions. [2018-04-12 15:07:41,006 INFO L460 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-04-12 15:07:41,006 INFO L276 IsEmpty]: Start isEmpty. Operand 1125 states and 1130 transitions. [2018-04-12 15:07:41,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1104 [2018-04-12 15:07:41,011 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:41,011 INFO L355 BasicCegarLoop]: trace histogram [167, 152, 152, 151, 151, 151, 16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:41,012 INFO L408 AbstractCegarLoop]: === Iteration 40 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:41,012 INFO L82 PathProgramCache]: Analyzing trace with hash -80485483, now seen corresponding path program 32 times [2018-04-12 15:07:41,012 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:41,012 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:41,012 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:41,012 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:07:41,013 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:41,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:41,066 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:41,949 INFO L134 CoverageAnalysis]: Checked inductivity of 74449 backedges. 14025 proven. 784 refuted. 0 times theorem prover too weak. 59640 trivial. 0 not checked. [2018-04-12 15:07:41,949 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:41,949 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:41,954 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 15:07:42,116 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 15:07:42,116 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:42,126 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:42,128 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:07:42,128 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:07:42,130 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:07:42,130 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:07:44,193 INFO L134 CoverageAnalysis]: Checked inductivity of 74449 backedges. 14025 proven. 722 refuted. 0 times theorem prover too weak. 59702 trivial. 0 not checked. [2018-04-12 15:07:44,212 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:44,212 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 23] total 40 [2018-04-12 15:07:44,213 INFO L442 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-04-12 15:07:44,213 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-04-12 15:07:44,213 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=392, Invalid=1248, Unknown=0, NotChecked=0, Total=1640 [2018-04-12 15:07:44,213 INFO L87 Difference]: Start difference. First operand 1125 states and 1130 transitions. Second operand 41 states. [2018-04-12 15:07:45,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:45,349 INFO L93 Difference]: Finished difference Result 1275 states and 1284 transitions. [2018-04-12 15:07:45,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-04-12 15:07:45,349 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 1103 [2018-04-12 15:07:45,349 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:45,351 INFO L225 Difference]: With dead ends: 1275 [2018-04-12 15:07:45,351 INFO L226 Difference]: Without dead ends: 1275 [2018-04-12 15:07:45,352 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1161 GetRequests, 1053 SyntacticMatches, 32 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2282 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1400, Invalid=4606, Unknown=0, NotChecked=0, Total=6006 [2018-04-12 15:07:45,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1275 states. [2018-04-12 15:07:45,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1275 to 1239. [2018-04-12 15:07:45,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1239 states. [2018-04-12 15:07:45,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1239 states to 1239 states and 1246 transitions. [2018-04-12 15:07:45,361 INFO L78 Accepts]: Start accepts. Automaton has 1239 states and 1246 transitions. Word has length 1103 [2018-04-12 15:07:45,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:45,362 INFO L459 AbstractCegarLoop]: Abstraction has 1239 states and 1246 transitions. [2018-04-12 15:07:45,362 INFO L460 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-04-12 15:07:45,362 INFO L276 IsEmpty]: Start isEmpty. Operand 1239 states and 1246 transitions. [2018-04-12 15:07:45,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1218 [2018-04-12 15:07:45,368 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:45,368 INFO L355 BasicCegarLoop]: trace histogram [185, 169, 169, 168, 168, 168, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:45,368 INFO L408 AbstractCegarLoop]: === Iteration 41 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:45,368 INFO L82 PathProgramCache]: Analyzing trace with hash -230054690, now seen corresponding path program 33 times [2018-04-12 15:07:45,368 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:45,369 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:45,369 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:45,369 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:45,369 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:45,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:45,411 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:46,370 INFO L134 CoverageAnalysis]: Checked inductivity of 91768 backedges. 33976 proven. 6853 refuted. 0 times theorem prover too weak. 50939 trivial. 0 not checked. [2018-04-12 15:07:46,370 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:46,370 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:46,376 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 15:07:46,653 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2018-04-12 15:07:46,653 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:46,662 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:47,791 INFO L134 CoverageAnalysis]: Checked inductivity of 91768 backedges. 29661 proven. 2452 refuted. 0 times theorem prover too weak. 59655 trivial. 0 not checked. [2018-04-12 15:07:47,810 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:47,810 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 41] total 78 [2018-04-12 15:07:47,811 INFO L442 AbstractCegarLoop]: Interpolant automaton has 78 states [2018-04-12 15:07:47,811 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2018-04-12 15:07:47,811 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=825, Invalid=5181, Unknown=0, NotChecked=0, Total=6006 [2018-04-12 15:07:47,812 INFO L87 Difference]: Start difference. First operand 1239 states and 1246 transitions. Second operand 78 states. [2018-04-12 15:07:50,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:50,063 INFO L93 Difference]: Finished difference Result 1394 states and 1400 transitions. [2018-04-12 15:07:50,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2018-04-12 15:07:50,064 INFO L78 Accepts]: Start accepts. Automaton has 78 states. Word has length 1217 [2018-04-12 15:07:50,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:50,066 INFO L225 Difference]: With dead ends: 1394 [2018-04-12 15:07:50,067 INFO L226 Difference]: Without dead ends: 1385 [2018-04-12 15:07:50,068 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1335 GetRequests, 1181 SyntacticMatches, 0 SemanticMatches, 154 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7932 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3510, Invalid=20670, Unknown=0, NotChecked=0, Total=24180 [2018-04-12 15:07:50,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1385 states. [2018-04-12 15:07:50,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1385 to 1368. [2018-04-12 15:07:50,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1368 states. [2018-04-12 15:07:50,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1368 states to 1368 states and 1374 transitions. [2018-04-12 15:07:50,076 INFO L78 Accepts]: Start accepts. Automaton has 1368 states and 1374 transitions. Word has length 1217 [2018-04-12 15:07:50,076 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:50,076 INFO L459 AbstractCegarLoop]: Abstraction has 1368 states and 1374 transitions. [2018-04-12 15:07:50,076 INFO L460 AbstractCegarLoop]: Interpolant automaton has 78 states. [2018-04-12 15:07:50,076 INFO L276 IsEmpty]: Start isEmpty. Operand 1368 states and 1374 transitions. [2018-04-12 15:07:50,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1224 [2018-04-12 15:07:50,083 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:50,083 INFO L355 BasicCegarLoop]: trace histogram [186, 170, 170, 169, 169, 169, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:50,083 INFO L408 AbstractCegarLoop]: === Iteration 42 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:50,083 INFO L82 PathProgramCache]: Analyzing trace with hash -929947930, now seen corresponding path program 34 times [2018-04-12 15:07:50,083 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:50,083 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:50,084 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:50,084 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:50,084 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:50,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:50,134 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:51,108 INFO L134 CoverageAnalysis]: Checked inductivity of 92812 backedges. 16704 proven. 884 refuted. 0 times theorem prover too weak. 75224 trivial. 0 not checked. [2018-04-12 15:07:51,108 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:51,109 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:51,114 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-12 15:07:51,392 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-12 15:07:51,392 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:51,405 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:51,407 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:07:51,407 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:07:51,409 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:07:51,409 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:07:53,395 INFO L134 CoverageAnalysis]: Checked inductivity of 92812 backedges. 16520 proven. 3373 refuted. 0 times theorem prover too weak. 72919 trivial. 0 not checked. [2018-04-12 15:07:53,415 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:53,416 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 25] total 43 [2018-04-12 15:07:53,416 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-04-12 15:07:53,417 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-04-12 15:07:53,417 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=453, Invalid=1439, Unknown=0, NotChecked=0, Total=1892 [2018-04-12 15:07:53,417 INFO L87 Difference]: Start difference. First operand 1368 states and 1374 transitions. Second operand 44 states. [2018-04-12 15:07:54,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:54,462 INFO L93 Difference]: Finished difference Result 1401 states and 1409 transitions. [2018-04-12 15:07:54,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-04-12 15:07:54,462 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 1223 [2018-04-12 15:07:54,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:54,465 INFO L225 Difference]: With dead ends: 1401 [2018-04-12 15:07:54,465 INFO L226 Difference]: Without dead ends: 1401 [2018-04-12 15:07:54,465 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1263 GetRequests, 1170 SyntacticMatches, 33 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1128 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=750, Invalid=3032, Unknown=0, NotChecked=0, Total=3782 [2018-04-12 15:07:54,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1401 states. [2018-04-12 15:07:54,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1401 to 1374. [2018-04-12 15:07:54,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1374 states. [2018-04-12 15:07:54,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1374 states to 1374 states and 1381 transitions. [2018-04-12 15:07:54,473 INFO L78 Accepts]: Start accepts. Automaton has 1374 states and 1381 transitions. Word has length 1223 [2018-04-12 15:07:54,473 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:54,473 INFO L459 AbstractCegarLoop]: Abstraction has 1374 states and 1381 transitions. [2018-04-12 15:07:54,473 INFO L460 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-04-12 15:07:54,473 INFO L276 IsEmpty]: Start isEmpty. Operand 1374 states and 1381 transitions. [2018-04-12 15:07:54,479 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1230 [2018-04-12 15:07:54,480 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:54,480 INFO L355 BasicCegarLoop]: trace histogram [187, 171, 171, 170, 170, 170, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:54,480 INFO L408 AbstractCegarLoop]: === Iteration 43 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:54,480 INFO L82 PathProgramCache]: Analyzing trace with hash -920557010, now seen corresponding path program 35 times [2018-04-12 15:07:54,480 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:54,480 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:54,481 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:54,481 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:54,481 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:54,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:54,533 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:55,274 INFO L134 CoverageAnalysis]: Checked inductivity of 93862 backedges. 18585 proven. 837 refuted. 0 times theorem prover too weak. 74440 trivial. 0 not checked. [2018-04-12 15:07:55,274 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:55,275 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:55,280 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-12 15:07:56,160 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 33 check-sat command(s) [2018-04-12 15:07:56,161 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:07:56,173 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:07:57,091 INFO L134 CoverageAnalysis]: Checked inductivity of 93862 backedges. 18471 proven. 4116 refuted. 0 times theorem prover too weak. 71275 trivial. 0 not checked. [2018-04-12 15:07:57,112 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:07:57,112 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 44] total 64 [2018-04-12 15:07:57,113 INFO L442 AbstractCegarLoop]: Interpolant automaton has 64 states [2018-04-12 15:07:57,113 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2018-04-12 15:07:57,113 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=819, Invalid=3213, Unknown=0, NotChecked=0, Total=4032 [2018-04-12 15:07:57,114 INFO L87 Difference]: Start difference. First operand 1374 states and 1381 transitions. Second operand 64 states. [2018-04-12 15:07:58,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:07:58,209 INFO L93 Difference]: Finished difference Result 1517 states and 1525 transitions. [2018-04-12 15:07:58,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2018-04-12 15:07:58,209 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 1229 [2018-04-12 15:07:58,210 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:07:58,212 INFO L225 Difference]: With dead ends: 1517 [2018-04-12 15:07:58,212 INFO L226 Difference]: Without dead ends: 1517 [2018-04-12 15:07:58,213 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1306 GetRequests, 1206 SyntacticMatches, 0 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1925 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=2228, Invalid=8074, Unknown=0, NotChecked=0, Total=10302 [2018-04-12 15:07:58,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1517 states. [2018-04-12 15:07:58,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1517 to 1500. [2018-04-12 15:07:58,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1500 states. [2018-04-12 15:07:58,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1500 states to 1500 states and 1508 transitions. [2018-04-12 15:07:58,223 INFO L78 Accepts]: Start accepts. Automaton has 1500 states and 1508 transitions. Word has length 1229 [2018-04-12 15:07:58,224 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:07:58,224 INFO L459 AbstractCegarLoop]: Abstraction has 1500 states and 1508 transitions. [2018-04-12 15:07:58,224 INFO L460 AbstractCegarLoop]: Interpolant automaton has 64 states. [2018-04-12 15:07:58,224 INFO L276 IsEmpty]: Start isEmpty. Operand 1500 states and 1508 transitions. [2018-04-12 15:07:58,232 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1344 [2018-04-12 15:07:58,232 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:07:58,232 INFO L355 BasicCegarLoop]: trace histogram [205, 188, 188, 187, 187, 187, 18, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:07:58,232 INFO L408 AbstractCegarLoop]: === Iteration 44 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:07:58,232 INFO L82 PathProgramCache]: Analyzing trace with hash -710434185, now seen corresponding path program 36 times [2018-04-12 15:07:58,233 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:07:58,233 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:07:58,233 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:58,233 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:07:58,233 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:07:58,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:07:58,286 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:07:59,276 INFO L134 CoverageAnalysis]: Checked inductivity of 113203 backedges. 39648 proven. 8202 refuted. 0 times theorem prover too weak. 65353 trivial. 0 not checked. [2018-04-12 15:07:59,277 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:07:59,277 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:07:59,282 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-12 15:08:00,414 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 36 check-sat command(s) [2018-04-12 15:08:00,415 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:08:00,430 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:08:00,432 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:08:00,432 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:08:00,434 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:08:00,434 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:08:03,445 INFO L134 CoverageAnalysis]: Checked inductivity of 113203 backedges. 19591 proven. 920 refuted. 0 times theorem prover too weak. 92692 trivial. 0 not checked. [2018-04-12 15:08:03,469 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:08:03,469 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 25] total 66 [2018-04-12 15:08:03,471 INFO L442 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-04-12 15:08:03,471 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-04-12 15:08:03,471 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=560, Invalid=3730, Unknown=0, NotChecked=0, Total=4290 [2018-04-12 15:08:03,471 INFO L87 Difference]: Start difference. First operand 1500 states and 1508 transitions. Second operand 66 states. [2018-04-12 15:08:06,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:08:06,713 INFO L93 Difference]: Finished difference Result 1652 states and 1660 transitions. [2018-04-12 15:08:06,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 97 states. [2018-04-12 15:08:06,713 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 1343 [2018-04-12 15:08:06,714 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:08:06,716 INFO L225 Difference]: With dead ends: 1652 [2018-04-12 15:08:06,716 INFO L226 Difference]: Without dead ends: 1643 [2018-04-12 15:08:06,717 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1469 GetRequests, 1288 SyntacticMatches, 33 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8552 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=2963, Invalid=19387, Unknown=0, NotChecked=0, Total=22350 [2018-04-12 15:08:06,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1643 states. [2018-04-12 15:08:06,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1643 to 1620. [2018-04-12 15:08:06,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1620 states. [2018-04-12 15:08:06,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1620 states to 1620 states and 1627 transitions. [2018-04-12 15:08:06,725 INFO L78 Accepts]: Start accepts. Automaton has 1620 states and 1627 transitions. Word has length 1343 [2018-04-12 15:08:06,726 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:08:06,726 INFO L459 AbstractCegarLoop]: Abstraction has 1620 states and 1627 transitions. [2018-04-12 15:08:06,726 INFO L460 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-04-12 15:08:06,726 INFO L276 IsEmpty]: Start isEmpty. Operand 1620 states and 1627 transitions. [2018-04-12 15:08:06,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1470 [2018-04-12 15:08:06,737 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:08:06,737 INFO L355 BasicCegarLoop]: trace histogram [225, 207, 207, 206, 206, 206, 19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:08:06,737 INFO L408 AbstractCegarLoop]: === Iteration 45 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:08:06,738 INFO L82 PathProgramCache]: Analyzing trace with hash 1705644624, now seen corresponding path program 37 times [2018-04-12 15:08:06,738 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:08:06,738 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:08:06,738 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:06,738 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:08:06,738 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:06,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:08:06,791 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:08:07,883 INFO L134 CoverageAnalysis]: Checked inductivity of 136892 backedges. 44818 proven. 9625 refuted. 0 times theorem prover too weak. 82449 trivial. 0 not checked. [2018-04-12 15:08:07,883 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:08:07,883 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:08:07,888 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:08:08,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:08:08,110 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:08:09,130 INFO L134 CoverageAnalysis]: Checked inductivity of 136892 backedges. 42145 proven. 954 refuted. 0 times theorem prover too weak. 93793 trivial. 0 not checked. [2018-04-12 15:08:09,148 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:08:09,148 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 40] total 72 [2018-04-12 15:08:09,149 INFO L442 AbstractCegarLoop]: Interpolant automaton has 72 states [2018-04-12 15:08:09,149 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2018-04-12 15:08:09,150 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=899, Invalid=4213, Unknown=0, NotChecked=0, Total=5112 [2018-04-12 15:08:09,150 INFO L87 Difference]: Start difference. First operand 1620 states and 1627 transitions. Second operand 72 states. [2018-04-12 15:08:10,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:08:10,827 INFO L93 Difference]: Finished difference Result 1657 states and 1664 transitions. [2018-04-12 15:08:10,827 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-04-12 15:08:10,827 INFO L78 Accepts]: Start accepts. Automaton has 72 states. Word has length 1469 [2018-04-12 15:08:10,828 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:08:10,830 INFO L225 Difference]: With dead ends: 1657 [2018-04-12 15:08:10,830 INFO L226 Difference]: Without dead ends: 1651 [2018-04-12 15:08:10,831 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1562 GetRequests, 1444 SyntacticMatches, 0 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4637 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=2601, Invalid=11679, Unknown=0, NotChecked=0, Total=14280 [2018-04-12 15:08:10,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1651 states. [2018-04-12 15:08:10,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1651 to 1630. [2018-04-12 15:08:10,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1630 states. [2018-04-12 15:08:10,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1630 states to 1630 states and 1637 transitions. [2018-04-12 15:08:10,838 INFO L78 Accepts]: Start accepts. Automaton has 1630 states and 1637 transitions. Word has length 1469 [2018-04-12 15:08:10,839 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:08:10,839 INFO L459 AbstractCegarLoop]: Abstraction has 1630 states and 1637 transitions. [2018-04-12 15:08:10,839 INFO L460 AbstractCegarLoop]: Interpolant automaton has 72 states. [2018-04-12 15:08:10,839 INFO L276 IsEmpty]: Start isEmpty. Operand 1630 states and 1637 transitions. [2018-04-12 15:08:10,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1476 [2018-04-12 15:08:10,848 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:08:10,848 INFO L355 BasicCegarLoop]: trace histogram [226, 208, 208, 207, 207, 207, 19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:08:10,848 INFO L408 AbstractCegarLoop]: === Iteration 46 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:08:10,848 INFO L82 PathProgramCache]: Analyzing trace with hash -1936089384, now seen corresponding path program 38 times [2018-04-12 15:08:10,848 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:08:10,848 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:08:10,849 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:10,849 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:08:10,849 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:10,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:08:10,909 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:08:12,105 INFO L134 CoverageAnalysis]: Checked inductivity of 138168 backedges. 21870 proven. 990 refuted. 0 times theorem prover too weak. 115308 trivial. 0 not checked. [2018-04-12 15:08:12,105 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:08:12,105 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:08:12,111 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 15:08:12,339 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 15:08:12,339 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:08:12,351 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:08:12,353 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:08:12,353 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:08:12,355 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:08:12,355 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:08:14,764 INFO L134 CoverageAnalysis]: Checked inductivity of 138168 backedges. 21870 proven. 990 refuted. 0 times theorem prover too weak. 115308 trivial. 0 not checked. [2018-04-12 15:08:14,782 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:08:14,782 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24] total 25 [2018-04-12 15:08:14,783 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-04-12 15:08:14,783 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-04-12 15:08:14,783 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=264, Invalid=386, Unknown=0, NotChecked=0, Total=650 [2018-04-12 15:08:14,783 INFO L87 Difference]: Start difference. First operand 1630 states and 1637 transitions. Second operand 26 states. [2018-04-12 15:08:15,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:08:15,222 INFO L93 Difference]: Finished difference Result 1650 states and 1657 transitions. [2018-04-12 15:08:15,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-04-12 15:08:15,223 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 1475 [2018-04-12 15:08:15,223 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:08:15,225 INFO L225 Difference]: With dead ends: 1650 [2018-04-12 15:08:15,225 INFO L226 Difference]: Without dead ends: 1650 [2018-04-12 15:08:15,226 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1517 GetRequests, 1436 SyntacticMatches, 38 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 315 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=721, Invalid=1259, Unknown=0, NotChecked=0, Total=1980 [2018-04-12 15:08:15,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1650 states. [2018-04-12 15:08:15,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1650 to 1632. [2018-04-12 15:08:15,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1632 states. [2018-04-12 15:08:15,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1632 states to 1632 states and 1639 transitions. [2018-04-12 15:08:15,235 INFO L78 Accepts]: Start accepts. Automaton has 1632 states and 1639 transitions. Word has length 1475 [2018-04-12 15:08:15,236 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:08:15,236 INFO L459 AbstractCegarLoop]: Abstraction has 1632 states and 1639 transitions. [2018-04-12 15:08:15,236 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-04-12 15:08:15,236 INFO L276 IsEmpty]: Start isEmpty. Operand 1632 states and 1639 transitions. [2018-04-12 15:08:15,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1482 [2018-04-12 15:08:15,245 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:08:15,245 INFO L355 BasicCegarLoop]: trace histogram [227, 209, 209, 208, 208, 208, 19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:08:15,245 INFO L408 AbstractCegarLoop]: === Iteration 47 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:08:15,246 INFO L82 PathProgramCache]: Analyzing trace with hash 1693559968, now seen corresponding path program 39 times [2018-04-12 15:08:15,246 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:08:15,246 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:08:15,246 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:15,246 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:08:15,246 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:15,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:08:15,311 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:08:16,565 INFO L134 CoverageAnalysis]: Checked inductivity of 139450 backedges. 23040 proven. 1102 refuted. 0 times theorem prover too weak. 115308 trivial. 0 not checked. [2018-04-12 15:08:16,566 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:08:16,566 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:08:16,571 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 15:08:16,936 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 20 check-sat command(s) [2018-04-12 15:08:16,936 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:08:16,947 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:08:16,949 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:08:16,949 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:08:16,951 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:08:16,951 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:08:19,324 INFO L134 CoverageAnalysis]: Checked inductivity of 139450 backedges. 23040 proven. 1102 refuted. 0 times theorem prover too weak. 115308 trivial. 0 not checked. [2018-04-12 15:08:19,343 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:08:19,343 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 25] total 26 [2018-04-12 15:08:19,344 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-04-12 15:08:19,344 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-04-12 15:08:19,344 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=287, Invalid=415, Unknown=0, NotChecked=0, Total=702 [2018-04-12 15:08:19,344 INFO L87 Difference]: Start difference. First operand 1632 states and 1639 transitions. Second operand 27 states. [2018-04-12 15:08:19,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:08:19,803 INFO L93 Difference]: Finished difference Result 1668 states and 1677 transitions. [2018-04-12 15:08:19,803 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-04-12 15:08:19,803 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 1481 [2018-04-12 15:08:19,804 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:08:19,807 INFO L225 Difference]: With dead ends: 1668 [2018-04-12 15:08:19,807 INFO L226 Difference]: Without dead ends: 1668 [2018-04-12 15:08:19,807 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1525 GetRequests, 1442 SyntacticMatches, 38 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 339 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=788, Invalid=1374, Unknown=0, NotChecked=0, Total=2162 [2018-04-12 15:08:19,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1668 states. [2018-04-12 15:08:19,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1668 to 1638. [2018-04-12 15:08:19,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1638 states. [2018-04-12 15:08:19,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1638 states to 1638 states and 1646 transitions. [2018-04-12 15:08:19,817 INFO L78 Accepts]: Start accepts. Automaton has 1638 states and 1646 transitions. Word has length 1481 [2018-04-12 15:08:19,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:08:19,818 INFO L459 AbstractCegarLoop]: Abstraction has 1638 states and 1646 transitions. [2018-04-12 15:08:19,818 INFO L460 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-04-12 15:08:19,818 INFO L276 IsEmpty]: Start isEmpty. Operand 1638 states and 1646 transitions. [2018-04-12 15:08:19,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1488 [2018-04-12 15:08:19,827 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:08:19,828 INFO L355 BasicCegarLoop]: trace histogram [228, 210, 210, 209, 209, 209, 19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:08:19,828 INFO L408 AbstractCegarLoop]: === Iteration 48 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:08:19,828 INFO L82 PathProgramCache]: Analyzing trace with hash -1607842712, now seen corresponding path program 40 times [2018-04-12 15:08:19,828 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:08:19,828 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:08:19,829 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:19,829 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:08:19,829 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:19,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:08:19,898 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:08:20,930 INFO L134 CoverageAnalysis]: Checked inductivity of 140738 backedges. 25371 proven. 1049 refuted. 0 times theorem prover too weak. 114318 trivial. 0 not checked. [2018-04-12 15:08:20,930 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:08:20,930 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:08:20,935 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-12 15:08:21,110 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-12 15:08:21,110 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:08:21,120 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:08:22,187 INFO L134 CoverageAnalysis]: Checked inductivity of 140738 backedges. 25430 proven. 990 refuted. 0 times theorem prover too weak. 114318 trivial. 0 not checked. [2018-04-12 15:08:22,207 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:08:22,207 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 43] total 66 [2018-04-12 15:08:22,208 INFO L442 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-04-12 15:08:22,208 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-04-12 15:08:22,208 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=991, Invalid=3299, Unknown=0, NotChecked=0, Total=4290 [2018-04-12 15:08:22,208 INFO L87 Difference]: Start difference. First operand 1638 states and 1646 transitions. Second operand 66 states. [2018-04-12 15:08:23,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:08:23,337 INFO L93 Difference]: Finished difference Result 1796 states and 1805 transitions. [2018-04-12 15:08:23,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-04-12 15:08:23,337 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 1487 [2018-04-12 15:08:23,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:08:23,340 INFO L225 Difference]: With dead ends: 1796 [2018-04-12 15:08:23,341 INFO L226 Difference]: Without dead ends: 1796 [2018-04-12 15:08:23,341 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1569 GetRequests, 1466 SyntacticMatches, 0 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1823 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=2782, Invalid=8138, Unknown=0, NotChecked=0, Total=10920 [2018-04-12 15:08:23,342 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1796 states. [2018-04-12 15:08:23,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1796 to 1776. [2018-04-12 15:08:23,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1776 states. [2018-04-12 15:08:23,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1776 states to 1776 states and 1785 transitions. [2018-04-12 15:08:23,352 INFO L78 Accepts]: Start accepts. Automaton has 1776 states and 1785 transitions. Word has length 1487 [2018-04-12 15:08:23,352 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:08:23,352 INFO L459 AbstractCegarLoop]: Abstraction has 1776 states and 1785 transitions. [2018-04-12 15:08:23,352 INFO L460 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-04-12 15:08:23,352 INFO L276 IsEmpty]: Start isEmpty. Operand 1776 states and 1785 transitions. [2018-04-12 15:08:23,362 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1614 [2018-04-12 15:08:23,362 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:08:23,362 INFO L355 BasicCegarLoop]: trace histogram [248, 229, 229, 228, 228, 228, 20, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:08:23,363 INFO L408 AbstractCegarLoop]: === Iteration 49 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:08:23,363 INFO L82 PathProgramCache]: Analyzing trace with hash 158683713, now seen corresponding path program 41 times [2018-04-12 15:08:23,363 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:08:23,363 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:08:23,363 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:23,363 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:08:23,364 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:23,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:08:23,422 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:08:24,736 INFO L134 CoverageAnalysis]: Checked inductivity of 167029 backedges. 68630 proven. 3474 refuted. 0 times theorem prover too weak. 94925 trivial. 0 not checked. [2018-04-12 15:08:24,736 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:08:24,736 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:08:24,745 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-12 15:08:26,181 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 48 check-sat command(s) [2018-04-12 15:08:26,182 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:08:26,198 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:08:27,639 INFO L134 CoverageAnalysis]: Checked inductivity of 167029 backedges. 50068 proven. 6466 refuted. 0 times theorem prover too weak. 110495 trivial. 0 not checked. [2018-04-12 15:08:27,661 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:08:27,661 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 45] total 86 [2018-04-12 15:08:27,662 INFO L442 AbstractCegarLoop]: Interpolant automaton has 86 states [2018-04-12 15:08:27,662 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2018-04-12 15:08:27,662 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1106, Invalid=6204, Unknown=0, NotChecked=0, Total=7310 [2018-04-12 15:08:27,662 INFO L87 Difference]: Start difference. First operand 1776 states and 1785 transitions. Second operand 86 states. [2018-04-12 15:08:30,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:08:30,169 INFO L93 Difference]: Finished difference Result 1799 states and 1806 transitions. [2018-04-12 15:08:30,169 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-04-12 15:08:30,169 INFO L78 Accepts]: Start accepts. Automaton has 86 states. Word has length 1613 [2018-04-12 15:08:30,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:08:30,172 INFO L225 Difference]: With dead ends: 1799 [2018-04-12 15:08:30,173 INFO L226 Difference]: Without dead ends: 1793 [2018-04-12 15:08:30,174 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1721 GetRequests, 1575 SyntacticMatches, 0 SemanticMatches, 146 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6971 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=3628, Invalid=18128, Unknown=0, NotChecked=0, Total=21756 [2018-04-12 15:08:30,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1793 states. [2018-04-12 15:08:30,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1793 to 1776. [2018-04-12 15:08:30,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1776 states. [2018-04-12 15:08:30,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1776 states to 1776 states and 1783 transitions. [2018-04-12 15:08:30,184 INFO L78 Accepts]: Start accepts. Automaton has 1776 states and 1783 transitions. Word has length 1613 [2018-04-12 15:08:30,184 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:08:30,184 INFO L459 AbstractCegarLoop]: Abstraction has 1776 states and 1783 transitions. [2018-04-12 15:08:30,184 INFO L460 AbstractCegarLoop]: Interpolant automaton has 86 states. [2018-04-12 15:08:30,184 INFO L276 IsEmpty]: Start isEmpty. Operand 1776 states and 1783 transitions. [2018-04-12 15:08:30,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1620 [2018-04-12 15:08:30,195 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:08:30,195 INFO L355 BasicCegarLoop]: trace histogram [249, 230, 230, 229, 229, 229, 20, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:08:30,195 INFO L408 AbstractCegarLoop]: === Iteration 50 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:08:30,195 INFO L82 PathProgramCache]: Analyzing trace with hash -2037889527, now seen corresponding path program 42 times [2018-04-12 15:08:30,195 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:08:30,196 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:08:30,196 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:30,196 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:08:30,196 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:30,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:08:30,295 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:08:31,760 INFO L134 CoverageAnalysis]: Checked inductivity of 168439 backedges. 26733 proven. 1220 refuted. 0 times theorem prover too weak. 140486 trivial. 0 not checked. [2018-04-12 15:08:31,760 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:08:31,760 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:08:31,766 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-12 15:08:32,730 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 41 check-sat command(s) [2018-04-12 15:08:32,730 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:08:32,745 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:08:32,747 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:08:32,747 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:08:32,748 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:08:32,749 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:08:35,526 INFO L134 CoverageAnalysis]: Checked inductivity of 168439 backedges. 26733 proven. 1220 refuted. 0 times theorem prover too weak. 140486 trivial. 0 not checked. [2018-04-12 15:08:35,546 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:08:35,547 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26] total 27 [2018-04-12 15:08:35,548 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-04-12 15:08:35,548 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-04-12 15:08:35,548 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=311, Invalid=445, Unknown=0, NotChecked=0, Total=756 [2018-04-12 15:08:35,548 INFO L87 Difference]: Start difference. First operand 1776 states and 1783 transitions. Second operand 28 states. [2018-04-12 15:08:36,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:08:36,052 INFO L93 Difference]: Finished difference Result 1802 states and 1810 transitions. [2018-04-12 15:08:36,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-04-12 15:08:36,052 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 1619 [2018-04-12 15:08:36,053 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:08:36,055 INFO L225 Difference]: With dead ends: 1802 [2018-04-12 15:08:36,055 INFO L226 Difference]: Without dead ends: 1802 [2018-04-12 15:08:36,055 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1665 GetRequests, 1578 SyntacticMatches, 40 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 367 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=858, Invalid=1494, Unknown=0, NotChecked=0, Total=2352 [2018-04-12 15:08:36,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1802 states. [2018-04-12 15:08:36,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1802 to 1782. [2018-04-12 15:08:36,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1782 states. [2018-04-12 15:08:36,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1782 states to 1782 states and 1790 transitions. [2018-04-12 15:08:36,064 INFO L78 Accepts]: Start accepts. Automaton has 1782 states and 1790 transitions. Word has length 1619 [2018-04-12 15:08:36,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:08:36,065 INFO L459 AbstractCegarLoop]: Abstraction has 1782 states and 1790 transitions. [2018-04-12 15:08:36,065 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-04-12 15:08:36,065 INFO L276 IsEmpty]: Start isEmpty. Operand 1782 states and 1790 transitions. [2018-04-12 15:08:36,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1626 [2018-04-12 15:08:36,075 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:08:36,076 INFO L355 BasicCegarLoop]: trace histogram [250, 231, 231, 230, 230, 230, 20, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:08:36,076 INFO L408 AbstractCegarLoop]: === Iteration 51 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:08:36,076 INFO L82 PathProgramCache]: Analyzing trace with hash 85486353, now seen corresponding path program 43 times [2018-04-12 15:08:36,076 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:08:36,076 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:08:36,076 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:36,076 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:08:36,076 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:36,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:08:36,149 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:08:37,307 INFO L134 CoverageAnalysis]: Checked inductivity of 169855 backedges. 29307 proven. 1164 refuted. 0 times theorem prover too weak. 139384 trivial. 0 not checked. [2018-04-12 15:08:37,307 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:08:37,307 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:08:37,312 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:08:37,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:08:37,539 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:08:38,792 INFO L134 CoverageAnalysis]: Checked inductivity of 169855 backedges. 29369 proven. 1102 refuted. 0 times theorem prover too weak. 139384 trivial. 0 not checked. [2018-04-12 15:08:38,811 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:08:38,811 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 45] total 69 [2018-04-12 15:08:38,812 INFO L442 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-04-12 15:08:38,812 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-04-12 15:08:38,812 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1082, Invalid=3610, Unknown=0, NotChecked=0, Total=4692 [2018-04-12 15:08:38,812 INFO L87 Difference]: Start difference. First operand 1782 states and 1790 transitions. Second operand 69 states. [2018-04-12 15:08:40,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:08:40,018 INFO L93 Difference]: Finished difference Result 1940 states and 1949 transitions. [2018-04-12 15:08:40,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-04-12 15:08:40,019 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 1625 [2018-04-12 15:08:40,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:08:40,022 INFO L225 Difference]: With dead ends: 1940 [2018-04-12 15:08:40,022 INFO L226 Difference]: Without dead ends: 1940 [2018-04-12 15:08:40,022 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1711 GetRequests, 1603 SyntacticMatches, 0 SemanticMatches, 108 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2009 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=3047, Invalid=8943, Unknown=0, NotChecked=0, Total=11990 [2018-04-12 15:08:40,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1940 states. [2018-04-12 15:08:40,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1940 to 1920. [2018-04-12 15:08:40,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1920 states. [2018-04-12 15:08:40,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1920 states to 1920 states and 1929 transitions. [2018-04-12 15:08:40,031 INFO L78 Accepts]: Start accepts. Automaton has 1920 states and 1929 transitions. Word has length 1625 [2018-04-12 15:08:40,032 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:08:40,032 INFO L459 AbstractCegarLoop]: Abstraction has 1920 states and 1929 transitions. [2018-04-12 15:08:40,032 INFO L460 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-04-12 15:08:40,032 INFO L276 IsEmpty]: Start isEmpty. Operand 1920 states and 1929 transitions. [2018-04-12 15:08:40,044 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1758 [2018-04-12 15:08:40,044 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:08:40,044 INFO L355 BasicCegarLoop]: trace histogram [271, 251, 251, 250, 250, 250, 21, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:08:40,044 INFO L408 AbstractCegarLoop]: === Iteration 52 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:08:40,044 INFO L82 PathProgramCache]: Analyzing trace with hash 1662420850, now seen corresponding path program 44 times [2018-04-12 15:08:40,044 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:08:40,045 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:08:40,045 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:40,045 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:08:40,045 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:40,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:08:40,116 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:08:41,630 INFO L134 CoverageAnalysis]: Checked inductivity of 200170 backedges. 76348 proven. 6069 refuted. 0 times theorem prover too weak. 117753 trivial. 0 not checked. [2018-04-12 15:08:41,630 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:08:41,630 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:08:41,635 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 15:08:41,903 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 15:08:41,904 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:08:41,918 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:08:43,415 INFO L134 CoverageAnalysis]: Checked inductivity of 200170 backedges. 58243 proven. 1180 refuted. 0 times theorem prover too weak. 140747 trivial. 0 not checked. [2018-04-12 15:08:43,434 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:08:43,434 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 44] total 86 [2018-04-12 15:08:43,435 INFO L442 AbstractCegarLoop]: Interpolant automaton has 86 states [2018-04-12 15:08:43,435 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2018-04-12 15:08:43,435 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1201, Invalid=6109, Unknown=0, NotChecked=0, Total=7310 [2018-04-12 15:08:43,435 INFO L87 Difference]: Start difference. First operand 1920 states and 1929 transitions. Second operand 86 states. [2018-04-12 15:08:45,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:08:45,874 INFO L93 Difference]: Finished difference Result 1943 states and 1950 transitions. [2018-04-12 15:08:45,874 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-04-12 15:08:45,874 INFO L78 Accepts]: Start accepts. Automaton has 86 states. Word has length 1757 [2018-04-12 15:08:45,875 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:08:45,878 INFO L225 Difference]: With dead ends: 1943 [2018-04-12 15:08:45,878 INFO L226 Difference]: Without dead ends: 1937 [2018-04-12 15:08:45,879 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1865 GetRequests, 1721 SyntacticMatches, 0 SemanticMatches, 144 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7026 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=3432, Invalid=17738, Unknown=0, NotChecked=0, Total=21170 [2018-04-12 15:08:45,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1937 states. [2018-04-12 15:08:45,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1937 to 1920. [2018-04-12 15:08:45,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1920 states. [2018-04-12 15:08:45,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1920 states to 1920 states and 1927 transitions. [2018-04-12 15:08:45,894 INFO L78 Accepts]: Start accepts. Automaton has 1920 states and 1927 transitions. Word has length 1757 [2018-04-12 15:08:45,895 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:08:45,895 INFO L459 AbstractCegarLoop]: Abstraction has 1920 states and 1927 transitions. [2018-04-12 15:08:45,895 INFO L460 AbstractCegarLoop]: Interpolant automaton has 86 states. [2018-04-12 15:08:45,895 INFO L276 IsEmpty]: Start isEmpty. Operand 1920 states and 1927 transitions. [2018-04-12 15:08:45,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1764 [2018-04-12 15:08:45,916 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:08:45,916 INFO L355 BasicCegarLoop]: trace histogram [272, 252, 252, 251, 251, 251, 21, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:08:45,916 INFO L408 AbstractCegarLoop]: === Iteration 53 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:08:45,917 INFO L82 PathProgramCache]: Analyzing trace with hash -840334726, now seen corresponding path program 45 times [2018-04-12 15:08:45,917 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:08:45,917 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:08:45,918 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:45,918 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:08:45,918 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:46,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:08:46,027 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:08:47,657 INFO L134 CoverageAnalysis]: Checked inductivity of 201714 backedges. 30800 proven. 1344 refuted. 0 times theorem prover too weak. 169570 trivial. 0 not checked. [2018-04-12 15:08:47,657 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:08:47,657 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:08:47,662 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 15:08:48,108 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-04-12 15:08:48,108 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:08:48,120 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:08:48,122 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:08:48,122 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:08:48,131 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:08:48,131 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:08:51,395 INFO L134 CoverageAnalysis]: Checked inductivity of 201714 backedges. 30800 proven. 1344 refuted. 0 times theorem prover too weak. 169570 trivial. 0 not checked. [2018-04-12 15:08:51,413 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:08:51,413 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 27] total 28 [2018-04-12 15:08:51,414 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-04-12 15:08:51,414 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-04-12 15:08:51,414 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=336, Invalid=476, Unknown=0, NotChecked=0, Total=812 [2018-04-12 15:08:51,414 INFO L87 Difference]: Start difference. First operand 1920 states and 1927 transitions. Second operand 29 states. [2018-04-12 15:08:51,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:08:51,987 INFO L93 Difference]: Finished difference Result 1946 states and 1954 transitions. [2018-04-12 15:08:51,987 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-04-12 15:08:51,987 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 1763 [2018-04-12 15:08:51,988 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:08:51,991 INFO L225 Difference]: With dead ends: 1946 [2018-04-12 15:08:51,991 INFO L226 Difference]: Without dead ends: 1946 [2018-04-12 15:08:51,991 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1811 GetRequests, 1720 SyntacticMatches, 42 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 396 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=931, Invalid=1619, Unknown=0, NotChecked=0, Total=2550 [2018-04-12 15:08:51,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1946 states. [2018-04-12 15:08:51,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1946 to 1926. [2018-04-12 15:08:51,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1926 states. [2018-04-12 15:08:52,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1926 states to 1926 states and 1934 transitions. [2018-04-12 15:08:52,000 INFO L78 Accepts]: Start accepts. Automaton has 1926 states and 1934 transitions. Word has length 1763 [2018-04-12 15:08:52,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:08:52,001 INFO L459 AbstractCegarLoop]: Abstraction has 1926 states and 1934 transitions. [2018-04-12 15:08:52,001 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-04-12 15:08:52,001 INFO L276 IsEmpty]: Start isEmpty. Operand 1926 states and 1934 transitions. [2018-04-12 15:08:52,013 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1770 [2018-04-12 15:08:52,013 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:08:52,013 INFO L355 BasicCegarLoop]: trace histogram [273, 253, 253, 252, 252, 252, 21, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:08:52,013 INFO L408 AbstractCegarLoop]: === Iteration 54 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:08:52,014 INFO L82 PathProgramCache]: Analyzing trace with hash -818098494, now seen corresponding path program 46 times [2018-04-12 15:08:52,014 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:08:52,014 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:08:52,014 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:52,014 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:08:52,014 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:52,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:08:52,094 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:08:53,462 INFO L134 CoverageAnalysis]: Checked inductivity of 203264 backedges. 33629 proven. 1285 refuted. 0 times theorem prover too weak. 168350 trivial. 0 not checked. [2018-04-12 15:08:53,462 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:08:53,462 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:08:53,467 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-12 15:08:53,687 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-12 15:08:53,687 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:08:53,701 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:08:55,081 INFO L134 CoverageAnalysis]: Checked inductivity of 203264 backedges. 33694 proven. 1220 refuted. 0 times theorem prover too weak. 168350 trivial. 0 not checked. [2018-04-12 15:08:55,100 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:08:55,100 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 47] total 72 [2018-04-12 15:08:55,101 INFO L442 AbstractCegarLoop]: Interpolant automaton has 72 states [2018-04-12 15:08:55,101 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2018-04-12 15:08:55,101 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1177, Invalid=3935, Unknown=0, NotChecked=0, Total=5112 [2018-04-12 15:08:55,101 INFO L87 Difference]: Start difference. First operand 1926 states and 1934 transitions. Second operand 72 states. [2018-04-12 15:08:56,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:08:56,481 INFO L93 Difference]: Finished difference Result 2090 states and 2099 transitions. [2018-04-12 15:08:56,481 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-04-12 15:08:56,481 INFO L78 Accepts]: Start accepts. Automaton has 72 states. Word has length 1769 [2018-04-12 15:08:56,482 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:08:56,484 INFO L225 Difference]: With dead ends: 2090 [2018-04-12 15:08:56,484 INFO L226 Difference]: Without dead ends: 2090 [2018-04-12 15:08:56,485 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1859 GetRequests, 1746 SyntacticMatches, 0 SemanticMatches, 113 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2204 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=3324, Invalid=9786, Unknown=0, NotChecked=0, Total=13110 [2018-04-12 15:08:56,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2090 states. [2018-04-12 15:08:56,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2090 to 2070. [2018-04-12 15:08:56,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2070 states. [2018-04-12 15:08:56,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2070 states to 2070 states and 2079 transitions. [2018-04-12 15:08:56,495 INFO L78 Accepts]: Start accepts. Automaton has 2070 states and 2079 transitions. Word has length 1769 [2018-04-12 15:08:56,496 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:08:56,496 INFO L459 AbstractCegarLoop]: Abstraction has 2070 states and 2079 transitions. [2018-04-12 15:08:56,496 INFO L460 AbstractCegarLoop]: Interpolant automaton has 72 states. [2018-04-12 15:08:56,496 INFO L276 IsEmpty]: Start isEmpty. Operand 2070 states and 2079 transitions. [2018-04-12 15:08:56,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1908 [2018-04-12 15:08:56,510 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:08:56,510 INFO L355 BasicCegarLoop]: trace histogram [295, 274, 274, 273, 273, 273, 22, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:08:56,510 INFO L408 AbstractCegarLoop]: === Iteration 55 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:08:56,511 INFO L82 PathProgramCache]: Analyzing trace with hash 1085039659, now seen corresponding path program 47 times [2018-04-12 15:08:56,511 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:08:56,511 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:08:56,511 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:56,511 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:08:56,511 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:08:56,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:08:56,640 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:08:58,341 INFO L134 CoverageAnalysis]: Checked inductivity of 237993 backedges. 84836 proven. 8786 refuted. 0 times theorem prover too weak. 144371 trivial. 0 not checked. [2018-04-12 15:08:58,342 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:08:58,342 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:08:58,347 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-12 15:09:00,496 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 55 check-sat command(s) [2018-04-12 15:09:00,496 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:09:00,517 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:09:02,392 INFO L134 CoverageAnalysis]: Checked inductivity of 237993 backedges. 66454 proven. 7848 refuted. 0 times theorem prover too weak. 163691 trivial. 0 not checked. [2018-04-12 15:09:02,416 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:09:02,416 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 92 [2018-04-12 15:09:02,417 INFO L442 AbstractCegarLoop]: Interpolant automaton has 92 states [2018-04-12 15:09:02,417 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2018-04-12 15:09:02,417 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1280, Invalid=7092, Unknown=0, NotChecked=0, Total=8372 [2018-04-12 15:09:02,418 INFO L87 Difference]: Start difference. First operand 2070 states and 2079 transitions. Second operand 92 states. [2018-04-12 15:09:04,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:09:04,620 INFO L93 Difference]: Finished difference Result 2093 states and 2100 transitions. [2018-04-12 15:09:04,620 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-04-12 15:09:04,621 INFO L78 Accepts]: Start accepts. Automaton has 92 states. Word has length 1907 [2018-04-12 15:09:04,621 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:09:04,624 INFO L225 Difference]: With dead ends: 2093 [2018-04-12 15:09:04,624 INFO L226 Difference]: Without dead ends: 2087 [2018-04-12 15:09:04,626 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2023 GetRequests, 1867 SyntacticMatches, 0 SemanticMatches, 156 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8048 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=4189, Invalid=20617, Unknown=0, NotChecked=0, Total=24806 [2018-04-12 15:09:04,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2087 states. [2018-04-12 15:09:04,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2087 to 2070. [2018-04-12 15:09:04,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2070 states. [2018-04-12 15:09:04,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2070 states to 2070 states and 2077 transitions. [2018-04-12 15:09:04,641 INFO L78 Accepts]: Start accepts. Automaton has 2070 states and 2077 transitions. Word has length 1907 [2018-04-12 15:09:04,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:09:04,642 INFO L459 AbstractCegarLoop]: Abstraction has 2070 states and 2077 transitions. [2018-04-12 15:09:04,642 INFO L460 AbstractCegarLoop]: Interpolant automaton has 92 states. [2018-04-12 15:09:04,643 INFO L276 IsEmpty]: Start isEmpty. Operand 2070 states and 2077 transitions. [2018-04-12 15:09:04,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1914 [2018-04-12 15:09:04,666 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:09:04,666 INFO L355 BasicCegarLoop]: trace histogram [296, 275, 275, 274, 274, 274, 22, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:09:04,667 INFO L408 AbstractCegarLoop]: === Iteration 56 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:09:04,667 INFO L82 PathProgramCache]: Analyzing trace with hash -1885233037, now seen corresponding path program 48 times [2018-04-12 15:09:04,667 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:09:04,667 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:09:04,668 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:09:04,668 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:09:04,668 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:09:04,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:09:04,808 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:09:06,685 INFO L134 CoverageAnalysis]: Checked inductivity of 239677 backedges. 35259 proven. 1474 refuted. 0 times theorem prover too weak. 202944 trivial. 0 not checked. [2018-04-12 15:09:06,685 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:09:06,685 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:09:06,690 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-12 15:09:07,675 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 45 check-sat command(s) [2018-04-12 15:09:07,675 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:09:07,692 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:09:07,694 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:09:07,695 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:09:07,696 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:09:07,697 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:09:11,545 INFO L134 CoverageAnalysis]: Checked inductivity of 239677 backedges. 35259 proven. 1474 refuted. 0 times theorem prover too weak. 202944 trivial. 0 not checked. [2018-04-12 15:09:11,567 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:09:11,568 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 28] total 29 [2018-04-12 15:09:11,568 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-04-12 15:09:11,568 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-04-12 15:09:11,568 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=362, Invalid=508, Unknown=0, NotChecked=0, Total=870 [2018-04-12 15:09:11,569 INFO L87 Difference]: Start difference. First operand 2070 states and 2077 transitions. Second operand 30 states. [2018-04-12 15:09:12,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:09:12,116 INFO L93 Difference]: Finished difference Result 2096 states and 2104 transitions. [2018-04-12 15:09:12,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-04-12 15:09:12,117 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 1913 [2018-04-12 15:09:12,117 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:09:12,119 INFO L225 Difference]: With dead ends: 2096 [2018-04-12 15:09:12,119 INFO L226 Difference]: Without dead ends: 2096 [2018-04-12 15:09:12,119 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1963 GetRequests, 1868 SyntacticMatches, 44 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 426 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1007, Invalid=1749, Unknown=0, NotChecked=0, Total=2756 [2018-04-12 15:09:12,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2096 states. [2018-04-12 15:09:12,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2096 to 2076. [2018-04-12 15:09:12,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2076 states. [2018-04-12 15:09:12,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2076 states to 2076 states and 2084 transitions. [2018-04-12 15:09:12,133 INFO L78 Accepts]: Start accepts. Automaton has 2076 states and 2084 transitions. Word has length 1913 [2018-04-12 15:09:12,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:09:12,134 INFO L459 AbstractCegarLoop]: Abstraction has 2076 states and 2084 transitions. [2018-04-12 15:09:12,134 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-04-12 15:09:12,134 INFO L276 IsEmpty]: Start isEmpty. Operand 2076 states and 2084 transitions. [2018-04-12 15:09:12,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1920 [2018-04-12 15:09:12,156 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:09:12,157 INFO L355 BasicCegarLoop]: trace histogram [297, 276, 276, 275, 275, 275, 22, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:09:12,157 INFO L408 AbstractCegarLoop]: === Iteration 57 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:09:12,157 INFO L82 PathProgramCache]: Analyzing trace with hash -275067397, now seen corresponding path program 49 times [2018-04-12 15:09:12,157 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:09:12,158 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:09:12,158 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:09:12,158 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:09:12,158 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:09:12,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:09:12,297 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:09:13,852 INFO L134 CoverageAnalysis]: Checked inductivity of 241367 backedges. 38355 proven. 1412 refuted. 0 times theorem prover too weak. 201600 trivial. 0 not checked. [2018-04-12 15:09:13,852 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:09:13,852 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:09:13,857 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:09:14,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:09:14,127 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:09:15,733 INFO L134 CoverageAnalysis]: Checked inductivity of 241367 backedges. 38423 proven. 1344 refuted. 0 times theorem prover too weak. 201600 trivial. 0 not checked. [2018-04-12 15:09:15,753 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:09:15,753 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 49] total 75 [2018-04-12 15:09:15,754 INFO L442 AbstractCegarLoop]: Interpolant automaton has 75 states [2018-04-12 15:09:15,754 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 75 interpolants. [2018-04-12 15:09:15,754 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1276, Invalid=4274, Unknown=0, NotChecked=0, Total=5550 [2018-04-12 15:09:15,754 INFO L87 Difference]: Start difference. First operand 2076 states and 2084 transitions. Second operand 75 states. [2018-04-12 15:09:17,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:09:17,192 INFO L93 Difference]: Finished difference Result 2246 states and 2255 transitions. [2018-04-12 15:09:17,193 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-04-12 15:09:17,193 INFO L78 Accepts]: Start accepts. Automaton has 75 states. Word has length 1919 [2018-04-12 15:09:17,193 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:09:17,195 INFO L225 Difference]: With dead ends: 2246 [2018-04-12 15:09:17,195 INFO L226 Difference]: Without dead ends: 2246 [2018-04-12 15:09:17,196 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2013 GetRequests, 1895 SyntacticMatches, 0 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2408 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=3613, Invalid=10667, Unknown=0, NotChecked=0, Total=14280 [2018-04-12 15:09:17,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2246 states. [2018-04-12 15:09:17,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2246 to 2226. [2018-04-12 15:09:17,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2226 states. [2018-04-12 15:09:17,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2226 states to 2226 states and 2235 transitions. [2018-04-12 15:09:17,205 INFO L78 Accepts]: Start accepts. Automaton has 2226 states and 2235 transitions. Word has length 1919 [2018-04-12 15:09:17,205 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:09:17,205 INFO L459 AbstractCegarLoop]: Abstraction has 2226 states and 2235 transitions. [2018-04-12 15:09:17,205 INFO L460 AbstractCegarLoop]: Interpolant automaton has 75 states. [2018-04-12 15:09:17,205 INFO L276 IsEmpty]: Start isEmpty. Operand 2226 states and 2235 transitions. [2018-04-12 15:09:17,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2064 [2018-04-12 15:09:17,221 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:09:17,221 INFO L355 BasicCegarLoop]: trace histogram [320, 298, 298, 297, 297, 297, 23, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:09:17,221 INFO L408 AbstractCegarLoop]: === Iteration 58 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:09:17,222 INFO L82 PathProgramCache]: Analyzing trace with hash 1741145324, now seen corresponding path program 50 times [2018-04-12 15:09:17,222 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:09:17,222 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:09:17,222 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:09:17,222 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:09:17,222 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:09:17,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:09:17,311 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:09:19,371 INFO L134 CoverageAnalysis]: Checked inductivity of 280918 backedges. 39986 proven. 1610 refuted. 0 times theorem prover too weak. 239322 trivial. 0 not checked. [2018-04-12 15:09:19,372 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:09:19,372 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:09:19,378 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 15:09:19,674 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 15:09:19,674 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:09:19,690 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:09:21,650 INFO L134 CoverageAnalysis]: Checked inductivity of 280918 backedges. 76257 proven. 1430 refuted. 0 times theorem prover too weak. 203231 trivial. 0 not checked. [2018-04-12 15:09:21,669 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:09:21,669 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 48] total 75 [2018-04-12 15:09:21,670 INFO L442 AbstractCegarLoop]: Interpolant automaton has 75 states [2018-04-12 15:09:21,670 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 75 interpolants. [2018-04-12 15:09:21,670 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=909, Invalid=4641, Unknown=0, NotChecked=0, Total=5550 [2018-04-12 15:09:21,670 INFO L87 Difference]: Start difference. First operand 2226 states and 2235 transitions. Second operand 75 states. [2018-04-12 15:09:24,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:09:24,152 INFO L93 Difference]: Finished difference Result 2258 states and 2266 transitions. [2018-04-12 15:09:24,152 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-04-12 15:09:24,152 INFO L78 Accepts]: Start accepts. Automaton has 75 states. Word has length 2063 [2018-04-12 15:09:24,153 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:09:24,155 INFO L225 Difference]: With dead ends: 2258 [2018-04-12 15:09:24,156 INFO L226 Difference]: Without dead ends: 2252 [2018-04-12 15:09:24,157 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2158 GetRequests, 2017 SyntacticMatches, 1 SemanticMatches, 140 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5065 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=3457, Invalid=16565, Unknown=0, NotChecked=0, Total=20022 [2018-04-12 15:09:24,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2252 states. [2018-04-12 15:09:24,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2252 to 2232. [2018-04-12 15:09:24,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2232 states. [2018-04-12 15:09:24,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2232 states to 2232 states and 2240 transitions. [2018-04-12 15:09:24,167 INFO L78 Accepts]: Start accepts. Automaton has 2232 states and 2240 transitions. Word has length 2063 [2018-04-12 15:09:24,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:09:24,168 INFO L459 AbstractCegarLoop]: Abstraction has 2232 states and 2240 transitions. [2018-04-12 15:09:24,168 INFO L460 AbstractCegarLoop]: Interpolant automaton has 75 states. [2018-04-12 15:09:24,168 INFO L276 IsEmpty]: Start isEmpty. Operand 2232 states and 2240 transitions. [2018-04-12 15:09:24,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2076 [2018-04-12 15:09:24,185 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:09:24,185 INFO L355 BasicCegarLoop]: trace histogram [322, 300, 300, 299, 299, 299, 23, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:09:24,185 INFO L408 AbstractCegarLoop]: === Iteration 59 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:09:24,185 INFO L82 PathProgramCache]: Analyzing trace with hash 1843168572, now seen corresponding path program 51 times [2018-04-12 15:09:24,186 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:09:24,186 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:09:24,186 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:09:24,186 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:09:24,186 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:09:24,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:09:24,278 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:09:26,425 INFO L134 CoverageAnalysis]: Checked inductivity of 284584 backedges. 41822 proven. 1752 refuted. 0 times theorem prover too weak. 241010 trivial. 0 not checked. [2018-04-12 15:09:26,425 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:09:26,425 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:09:26,431 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 15:09:27,108 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 25 check-sat command(s) [2018-04-12 15:09:27,108 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:09:27,123 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:09:29,535 INFO L134 CoverageAnalysis]: Checked inductivity of 284584 backedges. 76647 proven. 4972 refuted. 0 times theorem prover too weak. 202965 trivial. 0 not checked. [2018-04-12 15:09:29,554 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:09:29,554 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 55] total 83 [2018-04-12 15:09:29,555 INFO L442 AbstractCegarLoop]: Interpolant automaton has 83 states [2018-04-12 15:09:29,555 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2018-04-12 15:09:29,555 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1043, Invalid=5763, Unknown=0, NotChecked=0, Total=6806 [2018-04-12 15:09:29,555 INFO L87 Difference]: Start difference. First operand 2232 states and 2240 transitions. Second operand 83 states. [2018-04-12 15:09:32,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:09:32,900 INFO L93 Difference]: Finished difference Result 2422 states and 2432 transitions. [2018-04-12 15:09:32,900 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-04-12 15:09:32,900 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 2075 [2018-04-12 15:09:32,901 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:09:32,903 INFO L225 Difference]: With dead ends: 2422 [2018-04-12 15:09:32,903 INFO L226 Difference]: Without dead ends: 2422 [2018-04-12 15:09:32,904 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2184 GetRequests, 2022 SyntacticMatches, 1 SemanticMatches, 161 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6781 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=5072, Invalid=21334, Unknown=0, NotChecked=0, Total=26406 [2018-04-12 15:09:32,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2422 states. [2018-04-12 15:09:32,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2422 to 2400. [2018-04-12 15:09:32,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2400 states. [2018-04-12 15:09:32,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2400 states to 2400 states and 2410 transitions. [2018-04-12 15:09:32,914 INFO L78 Accepts]: Start accepts. Automaton has 2400 states and 2410 transitions. Word has length 2075 [2018-04-12 15:09:32,915 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:09:32,915 INFO L459 AbstractCegarLoop]: Abstraction has 2400 states and 2410 transitions. [2018-04-12 15:09:32,915 INFO L460 AbstractCegarLoop]: Interpolant automaton has 83 states. [2018-04-12 15:09:32,915 INFO L276 IsEmpty]: Start isEmpty. Operand 2400 states and 2410 transitions. [2018-04-12 15:09:32,950 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2238 [2018-04-12 15:09:32,950 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:09:32,950 INFO L355 BasicCegarLoop]: trace histogram [348, 325, 325, 324, 324, 324, 24, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:09:32,950 INFO L408 AbstractCegarLoop]: === Iteration 60 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:09:32,951 INFO L82 PathProgramCache]: Analyzing trace with hash -1102393595, now seen corresponding path program 52 times [2018-04-12 15:09:32,951 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:09:32,951 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:09:32,951 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:09:32,951 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:09:32,952 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:09:33,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:09:33,057 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:09:35,044 INFO L134 CoverageAnalysis]: Checked inductivity of 333353 backedges. 49091 proven. 1684 refuted. 0 times theorem prover too weak. 282578 trivial. 0 not checked. [2018-04-12 15:09:35,044 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:09:35,044 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:09:35,049 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-12 15:09:35,308 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-12 15:09:35,308 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:09:35,324 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:09:37,308 INFO L134 CoverageAnalysis]: Checked inductivity of 333353 backedges. 49165 proven. 1610 refuted. 0 times theorem prover too weak. 282578 trivial. 0 not checked. [2018-04-12 15:09:37,327 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:09:37,328 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 53] total 81 [2018-04-12 15:09:37,328 INFO L442 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-04-12 15:09:37,328 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-04-12 15:09:37,329 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1486, Invalid=4994, Unknown=0, NotChecked=0, Total=6480 [2018-04-12 15:09:37,329 INFO L87 Difference]: Start difference. First operand 2400 states and 2410 transitions. Second operand 81 states. [2018-04-12 15:09:38,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:09:38,776 INFO L93 Difference]: Finished difference Result 2752 states and 2767 transitions. [2018-04-12 15:09:38,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-04-12 15:09:38,777 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 2237 [2018-04-12 15:09:38,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:09:38,783 INFO L225 Difference]: With dead ends: 2752 [2018-04-12 15:09:38,783 INFO L226 Difference]: Without dead ends: 2752 [2018-04-12 15:09:38,784 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2339 GetRequests, 2211 SyntacticMatches, 0 SemanticMatches, 128 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2843 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=4227, Invalid=12543, Unknown=0, NotChecked=0, Total=16770 [2018-04-12 15:09:38,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2752 states. [2018-04-12 15:09:38,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2752 to 2730. [2018-04-12 15:09:38,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2730 states. [2018-04-12 15:09:38,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2730 states to 2730 states and 2745 transitions. [2018-04-12 15:09:38,799 INFO L78 Accepts]: Start accepts. Automaton has 2730 states and 2745 transitions. Word has length 2237 [2018-04-12 15:09:38,800 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:09:38,800 INFO L459 AbstractCegarLoop]: Abstraction has 2730 states and 2745 transitions. [2018-04-12 15:09:38,800 INFO L460 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-04-12 15:09:38,800 INFO L276 IsEmpty]: Start isEmpty. Operand 2730 states and 2745 transitions. [2018-04-12 15:09:38,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2388 [2018-04-12 15:09:38,823 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:09:38,824 INFO L355 BasicCegarLoop]: trace histogram [372, 348, 348, 347, 347, 347, 25, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:09:38,824 INFO L408 AbstractCegarLoop]: === Iteration 61 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:09:38,824 INFO L82 PathProgramCache]: Analyzing trace with hash -623771714, now seen corresponding path program 53 times [2018-04-12 15:09:38,824 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:09:38,824 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:09:38,825 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:09:38,825 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:09:38,825 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:09:38,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:09:38,931 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:09:41,298 INFO L134 CoverageAnalysis]: Checked inductivity of 381710 backedges. 109985 proven. 20824 refuted. 0 times theorem prover too weak. 250901 trivial. 0 not checked. [2018-04-12 15:09:41,299 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:09:41,299 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:09:41,304 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-12 15:09:45,089 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 58 check-sat command(s) [2018-04-12 15:09:45,089 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:09:45,119 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:09:47,501 INFO L134 CoverageAnalysis]: Checked inductivity of 381710 backedges. 132784 proven. 9358 refuted. 0 times theorem prover too weak. 239568 trivial. 0 not checked. [2018-04-12 15:09:47,529 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:09:47,530 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54] total 98 [2018-04-12 15:09:47,530 INFO L442 AbstractCegarLoop]: Interpolant automaton has 98 states [2018-04-12 15:09:47,530 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2018-04-12 15:09:47,531 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1470, Invalid=8036, Unknown=0, NotChecked=0, Total=9506 [2018-04-12 15:09:47,531 INFO L87 Difference]: Start difference. First operand 2730 states and 2745 transitions. Second operand 98 states. [2018-04-12 15:09:50,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:09:50,100 INFO L93 Difference]: Finished difference Result 2580 states and 2589 transitions. [2018-04-12 15:09:50,100 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2018-04-12 15:09:50,100 INFO L78 Accepts]: Start accepts. Automaton has 98 states. Word has length 2387 [2018-04-12 15:09:50,101 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:09:50,105 INFO L225 Difference]: With dead ends: 2580 [2018-04-12 15:09:50,105 INFO L226 Difference]: Without dead ends: 2571 [2018-04-12 15:09:50,106 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2511 GetRequests, 2345 SyntacticMatches, 0 SemanticMatches, 166 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9201 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=4794, Invalid=23262, Unknown=0, NotChecked=0, Total=28056 [2018-04-12 15:09:50,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2571 states. [2018-04-12 15:09:50,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2571 to 2556. [2018-04-12 15:09:50,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2556 states. [2018-04-12 15:09:50,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2556 states to 2556 states and 2565 transitions. [2018-04-12 15:09:50,117 INFO L78 Accepts]: Start accepts. Automaton has 2556 states and 2565 transitions. Word has length 2387 [2018-04-12 15:09:50,118 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:09:50,118 INFO L459 AbstractCegarLoop]: Abstraction has 2556 states and 2565 transitions. [2018-04-12 15:09:50,118 INFO L460 AbstractCegarLoop]: Interpolant automaton has 98 states. [2018-04-12 15:09:50,118 INFO L276 IsEmpty]: Start isEmpty. Operand 2556 states and 2565 transitions. [2018-04-12 15:09:50,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2394 [2018-04-12 15:09:50,139 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:09:50,139 INFO L355 BasicCegarLoop]: trace histogram [373, 349, 349, 348, 348, 348, 25, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:09:50,140 INFO L408 AbstractCegarLoop]: === Iteration 62 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:09:50,140 INFO L82 PathProgramCache]: Analyzing trace with hash -808142202, now seen corresponding path program 54 times [2018-04-12 15:09:50,140 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:09:50,140 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:09:50,140 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:09:50,140 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:09:50,140 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:09:50,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:09:50,239 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:09:52,679 INFO L134 CoverageAnalysis]: Checked inductivity of 383844 backedges. 115280 proven. 17669 refuted. 0 times theorem prover too weak. 250895 trivial. 0 not checked. [2018-04-12 15:09:52,679 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:09:52,679 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:09:52,685 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-12 15:09:55,033 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 51 check-sat command(s) [2018-04-12 15:09:55,034 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:09:55,056 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:09:57,903 INFO L134 CoverageAnalysis]: Checked inductivity of 383844 backedges. 94229 proven. 5404 refuted. 0 times theorem prover too weak. 284211 trivial. 0 not checked. [2018-04-12 15:09:57,927 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:09:57,927 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 57] total 110 [2018-04-12 15:09:57,928 INFO L442 AbstractCegarLoop]: Interpolant automaton has 110 states [2018-04-12 15:09:57,928 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 110 interpolants. [2018-04-12 15:09:57,929 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1685, Invalid=10305, Unknown=0, NotChecked=0, Total=11990 [2018-04-12 15:09:57,929 INFO L87 Difference]: Start difference. First operand 2556 states and 2565 transitions. Second operand 110 states. [2018-04-12 15:10:01,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:10:01,799 INFO L93 Difference]: Finished difference Result 2581 states and 2588 transitions. [2018-04-12 15:10:01,799 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 118 states. [2018-04-12 15:10:01,799 INFO L78 Accepts]: Start accepts. Automaton has 110 states. Word has length 2393 [2018-04-12 15:10:01,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:10:01,804 INFO L225 Difference]: With dead ends: 2581 [2018-04-12 15:10:01,804 INFO L226 Difference]: Without dead ends: 2575 [2018-04-12 15:10:01,808 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2559 GetRequests, 2341 SyntacticMatches, 0 SemanticMatches, 218 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16160 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=7070, Invalid=41110, Unknown=0, NotChecked=0, Total=48180 [2018-04-12 15:10:01,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2575 states. [2018-04-12 15:10:01,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2575 to 2556. [2018-04-12 15:10:01,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2556 states. [2018-04-12 15:10:01,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2556 states to 2556 states and 2563 transitions. [2018-04-12 15:10:01,825 INFO L78 Accepts]: Start accepts. Automaton has 2556 states and 2563 transitions. Word has length 2393 [2018-04-12 15:10:01,826 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:10:01,826 INFO L459 AbstractCegarLoop]: Abstraction has 2556 states and 2563 transitions. [2018-04-12 15:10:01,826 INFO L460 AbstractCegarLoop]: Interpolant automaton has 110 states. [2018-04-12 15:10:01,826 INFO L276 IsEmpty]: Start isEmpty. Operand 2556 states and 2563 transitions. [2018-04-12 15:10:01,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2400 [2018-04-12 15:10:01,861 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:10:01,862 INFO L355 BasicCegarLoop]: trace histogram [374, 350, 350, 349, 349, 349, 25, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:10:01,862 INFO L408 AbstractCegarLoop]: === Iteration 63 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:10:01,862 INFO L82 PathProgramCache]: Analyzing trace with hash -489433458, now seen corresponding path program 55 times [2018-04-12 15:10:01,862 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:10:01,863 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:10:01,863 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:10:01,863 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:10:01,864 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:10:01,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:10:01,995 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:10:04,697 INFO L134 CoverageAnalysis]: Checked inductivity of 385984 backedges. 51168 proven. 1900 refuted. 0 times theorem prover too weak. 332916 trivial. 0 not checked. [2018-04-12 15:10:04,697 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:10:04,698 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:10:04,704 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:10:05,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:10:05,055 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:10:05,057 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:10:05,057 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:10:05,059 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:10:05,059 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:10:11,275 INFO L134 CoverageAnalysis]: Checked inductivity of 385984 backedges. 51168 proven. 1900 refuted. 0 times theorem prover too weak. 332916 trivial. 0 not checked. [2018-04-12 15:10:11,296 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:10:11,296 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 56 [2018-04-12 15:10:11,297 INFO L442 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-04-12 15:10:11,297 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-04-12 15:10:11,297 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=842, Invalid=2350, Unknown=0, NotChecked=0, Total=3192 [2018-04-12 15:10:11,297 INFO L87 Difference]: Start difference. First operand 2556 states and 2563 transitions. Second operand 57 states. [2018-04-12 15:10:13,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:10:13,209 INFO L93 Difference]: Finished difference Result 2582 states and 2590 transitions. [2018-04-12 15:10:13,210 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-04-12 15:10:13,210 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 2399 [2018-04-12 15:10:13,211 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:10:13,213 INFO L225 Difference]: With dead ends: 2582 [2018-04-12 15:10:13,213 INFO L226 Difference]: Without dead ends: 2582 [2018-04-12 15:10:13,213 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2455 GetRequests, 2324 SyntacticMatches, 50 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2049 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1348, Invalid=5458, Unknown=0, NotChecked=0, Total=6806 [2018-04-12 15:10:13,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2582 states. [2018-04-12 15:10:13,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2582 to 2562. [2018-04-12 15:10:13,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2562 states. [2018-04-12 15:10:13,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2562 states to 2562 states and 2570 transitions. [2018-04-12 15:10:13,226 INFO L78 Accepts]: Start accepts. Automaton has 2562 states and 2570 transitions. Word has length 2399 [2018-04-12 15:10:13,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:10:13,227 INFO L459 AbstractCegarLoop]: Abstraction has 2562 states and 2570 transitions. [2018-04-12 15:10:13,227 INFO L460 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-04-12 15:10:13,227 INFO L276 IsEmpty]: Start isEmpty. Operand 2562 states and 2570 transitions. [2018-04-12 15:10:13,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2406 [2018-04-12 15:10:13,263 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:10:13,264 INFO L355 BasicCegarLoop]: trace histogram [375, 351, 351, 350, 350, 350, 25, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:10:13,264 INFO L408 AbstractCegarLoop]: === Iteration 64 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:10:13,264 INFO L82 PathProgramCache]: Analyzing trace with hash -1173044266, now seen corresponding path program 56 times [2018-04-12 15:10:13,264 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:10:13,265 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:10:13,265 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:10:13,265 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:10:13,266 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:10:13,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:10:13,402 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:10:15,613 INFO L134 CoverageAnalysis]: Checked inductivity of 388130 backedges. 55137 proven. 1829 refuted. 0 times theorem prover too weak. 331164 trivial. 0 not checked. [2018-04-12 15:10:15,613 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:10:15,613 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:10:15,618 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 15:10:15,972 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 15:10:15,972 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:10:15,994 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:10:19,167 INFO L134 CoverageAnalysis]: Checked inductivity of 388130 backedges. 55060 proven. 1906 refuted. 0 times theorem prover too weak. 331164 trivial. 0 not checked. [2018-04-12 15:10:19,187 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:10:19,187 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 57] total 112 [2018-04-12 15:10:19,188 INFO L442 AbstractCegarLoop]: Interpolant automaton has 112 states [2018-04-12 15:10:19,188 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 112 interpolants. [2018-04-12 15:10:19,189 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2226, Invalid=10206, Unknown=0, NotChecked=0, Total=12432 [2018-04-12 15:10:19,189 INFO L87 Difference]: Start difference. First operand 2562 states and 2570 transitions. Second operand 112 states. [2018-04-12 15:10:21,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:10:21,573 INFO L93 Difference]: Finished difference Result 2750 states and 2759 transitions. [2018-04-12 15:10:21,574 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 82 states. [2018-04-12 15:10:21,574 INFO L78 Accepts]: Start accepts. Automaton has 112 states. Word has length 2405 [2018-04-12 15:10:21,575 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:10:21,577 INFO L225 Difference]: With dead ends: 2750 [2018-04-12 15:10:21,577 INFO L226 Difference]: Without dead ends: 2750 [2018-04-12 15:10:21,578 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2513 GetRequests, 2350 SyntacticMatches, 0 SemanticMatches, 163 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7984 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=5370, Invalid=21690, Unknown=0, NotChecked=0, Total=27060 [2018-04-12 15:10:21,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2750 states. [2018-04-12 15:10:21,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2750 to 2730. [2018-04-12 15:10:21,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2730 states. [2018-04-12 15:10:21,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2730 states to 2730 states and 2739 transitions. [2018-04-12 15:10:21,589 INFO L78 Accepts]: Start accepts. Automaton has 2730 states and 2739 transitions. Word has length 2405 [2018-04-12 15:10:21,590 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:10:21,590 INFO L459 AbstractCegarLoop]: Abstraction has 2730 states and 2739 transitions. [2018-04-12 15:10:21,590 INFO L460 AbstractCegarLoop]: Interpolant automaton has 112 states. [2018-04-12 15:10:21,590 INFO L276 IsEmpty]: Start isEmpty. Operand 2730 states and 2739 transitions. [2018-04-12 15:10:21,614 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2568 [2018-04-12 15:10:21,614 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:10:21,615 INFO L355 BasicCegarLoop]: trace histogram [401, 376, 376, 375, 375, 375, 26, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:10:21,615 INFO L408 AbstractCegarLoop]: === Iteration 65 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:10:21,616 INFO L82 PathProgramCache]: Analyzing trace with hash 185613919, now seen corresponding path program 57 times [2018-04-12 15:10:21,616 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:10:21,616 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:10:21,616 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:10:21,616 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:10:21,616 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:10:21,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:10:21,753 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:10:24,539 INFO L134 CoverageAnalysis]: Checked inductivity of 444775 backedges. 127208 proven. 20874 refuted. 0 times theorem prover too weak. 296693 trivial. 0 not checked. [2018-04-12 15:10:24,540 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:10:24,540 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:10:24,546 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 15:10:25,260 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2018-04-12 15:10:25,260 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:10:25,279 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:10:28,458 INFO L134 CoverageAnalysis]: Checked inductivity of 444775 backedges. 105981 proven. 5854 refuted. 0 times theorem prover too weak. 332940 trivial. 0 not checked. [2018-04-12 15:10:28,482 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:10:28,495 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 59] total 114 [2018-04-12 15:10:28,495 INFO L442 AbstractCegarLoop]: Interpolant automaton has 114 states [2018-04-12 15:10:28,496 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 114 interpolants. [2018-04-12 15:10:28,496 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1803, Invalid=11079, Unknown=0, NotChecked=0, Total=12882 [2018-04-12 15:10:28,496 INFO L87 Difference]: Start difference. First operand 2730 states and 2739 transitions. Second operand 114 states. [2018-04-12 15:10:32,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:10:32,522 INFO L93 Difference]: Finished difference Result 2755 states and 2762 transitions. [2018-04-12 15:10:32,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 123 states. [2018-04-12 15:10:32,522 INFO L78 Accepts]: Start accepts. Automaton has 114 states. Word has length 2567 [2018-04-12 15:10:32,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:10:32,526 INFO L225 Difference]: With dead ends: 2755 [2018-04-12 15:10:32,526 INFO L226 Difference]: Without dead ends: 2749 [2018-04-12 15:10:32,528 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2740 GetRequests, 2513 SyntacticMatches, 0 SemanticMatches, 227 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17642 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=7576, Invalid=44636, Unknown=0, NotChecked=0, Total=52212 [2018-04-12 15:10:32,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2749 states. [2018-04-12 15:10:32,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2749 to 2730. [2018-04-12 15:10:32,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2730 states. [2018-04-12 15:10:32,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2730 states to 2730 states and 2737 transitions. [2018-04-12 15:10:32,542 INFO L78 Accepts]: Start accepts. Automaton has 2730 states and 2737 transitions. Word has length 2567 [2018-04-12 15:10:32,543 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:10:32,543 INFO L459 AbstractCegarLoop]: Abstraction has 2730 states and 2737 transitions. [2018-04-12 15:10:32,543 INFO L460 AbstractCegarLoop]: Interpolant automaton has 114 states. [2018-04-12 15:10:32,543 INFO L276 IsEmpty]: Start isEmpty. Operand 2730 states and 2737 transitions. [2018-04-12 15:10:32,566 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2574 [2018-04-12 15:10:32,566 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:10:32,567 INFO L355 BasicCegarLoop]: trace histogram [402, 377, 377, 376, 376, 376, 26, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:10:32,567 INFO L408 AbstractCegarLoop]: === Iteration 66 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:10:32,567 INFO L82 PathProgramCache]: Analyzing trace with hash 2140128167, now seen corresponding path program 58 times [2018-04-12 15:10:32,567 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:10:32,567 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:10:32,568 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:10:32,568 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:10:32,568 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:10:32,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:10:32,697 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:10:35,674 INFO L134 CoverageAnalysis]: Checked inductivity of 447079 backedges. 57375 proven. 2054 refuted. 0 times theorem prover too weak. 387650 trivial. 0 not checked. [2018-04-12 15:10:35,674 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:10:35,674 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:10:35,680 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-12 15:10:36,527 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-12 15:10:36,527 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:10:36,558 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:10:36,560 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:10:36,560 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:10:36,563 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:10:36,563 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:10:43,734 INFO L134 CoverageAnalysis]: Checked inductivity of 447079 backedges. 57101 proven. 7522 refuted. 0 times theorem prover too weak. 382456 trivial. 0 not checked. [2018-04-12 15:10:43,763 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:10:43,764 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 34] total 61 [2018-04-12 15:10:43,764 INFO L442 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-04-12 15:10:43,764 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-04-12 15:10:43,764 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=912, Invalid=2870, Unknown=0, NotChecked=0, Total=3782 [2018-04-12 15:10:43,765 INFO L87 Difference]: Start difference. First operand 2730 states and 2737 transitions. Second operand 62 states. [2018-04-12 15:10:45,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:10:45,662 INFO L93 Difference]: Finished difference Result 2756 states and 2764 transitions. [2018-04-12 15:10:45,662 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-04-12 15:10:45,662 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 2573 [2018-04-12 15:10:45,663 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:10:45,665 INFO L225 Difference]: With dead ends: 2756 [2018-04-12 15:10:45,665 INFO L226 Difference]: Without dead ends: 2756 [2018-04-12 15:10:45,665 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2631 GetRequests, 2493 SyntacticMatches, 51 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2424 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1479, Invalid=6353, Unknown=0, NotChecked=0, Total=7832 [2018-04-12 15:10:45,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2756 states. [2018-04-12 15:10:45,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2756 to 2736. [2018-04-12 15:10:45,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2736 states. [2018-04-12 15:10:45,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2736 states to 2736 states and 2744 transitions. [2018-04-12 15:10:45,675 INFO L78 Accepts]: Start accepts. Automaton has 2736 states and 2744 transitions. Word has length 2573 [2018-04-12 15:10:45,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:10:45,675 INFO L459 AbstractCegarLoop]: Abstraction has 2736 states and 2744 transitions. [2018-04-12 15:10:45,675 INFO L460 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-04-12 15:10:45,675 INFO L276 IsEmpty]: Start isEmpty. Operand 2736 states and 2744 transitions. [2018-04-12 15:10:45,698 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2580 [2018-04-12 15:10:45,698 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:10:45,699 INFO L355 BasicCegarLoop]: trace histogram [403, 378, 378, 377, 377, 377, 26, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:10:45,699 INFO L408 AbstractCegarLoop]: === Iteration 67 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:10:45,699 INFO L82 PathProgramCache]: Analyzing trace with hash -303646161, now seen corresponding path program 59 times [2018-04-12 15:10:45,699 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:10:45,699 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:10:45,699 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:10:45,700 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:10:45,700 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:10:45,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:10:45,820 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:10:48,366 INFO L134 CoverageAnalysis]: Checked inductivity of 449389 backedges. 61659 proven. 1980 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-04-12 15:10:48,366 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:10:48,366 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:10:48,371 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-12 15:10:53,852 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 61 check-sat command(s) [2018-04-12 15:10:53,852 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:10:53,885 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:10:56,559 INFO L134 CoverageAnalysis]: Checked inductivity of 449389 backedges. 61551 proven. 11426 refuted. 0 times theorem prover too weak. 376412 trivial. 0 not checked. [2018-04-12 15:10:56,593 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:10:56,594 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 62] total 92 [2018-04-12 15:10:56,594 INFO L442 AbstractCegarLoop]: Interpolant automaton has 92 states [2018-04-12 15:10:56,594 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2018-04-12 15:10:56,595 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1707, Invalid=6665, Unknown=0, NotChecked=0, Total=8372 [2018-04-12 15:10:56,595 INFO L87 Difference]: Start difference. First operand 2736 states and 2744 transitions. Second operand 92 states. [2018-04-12 15:10:58,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:10:58,771 INFO L93 Difference]: Finished difference Result 2930 states and 2939 transitions. [2018-04-12 15:10:58,771 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2018-04-12 15:10:58,772 INFO L78 Accepts]: Start accepts. Automaton has 92 states. Word has length 2579 [2018-04-12 15:10:58,772 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:10:58,774 INFO L225 Difference]: With dead ends: 2930 [2018-04-12 15:10:58,774 INFO L226 Difference]: Without dead ends: 2930 [2018-04-12 15:10:58,775 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2693 GetRequests, 2546 SyntacticMatches, 0 SemanticMatches, 147 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4227 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=4744, Invalid=17308, Unknown=0, NotChecked=0, Total=22052 [2018-04-12 15:10:58,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2930 states. [2018-04-12 15:10:58,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2930 to 2910. [2018-04-12 15:10:58,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2910 states. [2018-04-12 15:10:58,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2910 states to 2910 states and 2919 transitions. [2018-04-12 15:10:58,785 INFO L78 Accepts]: Start accepts. Automaton has 2910 states and 2919 transitions. Word has length 2579 [2018-04-12 15:10:58,785 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:10:58,785 INFO L459 AbstractCegarLoop]: Abstraction has 2910 states and 2919 transitions. [2018-04-12 15:10:58,785 INFO L460 AbstractCegarLoop]: Interpolant automaton has 92 states. [2018-04-12 15:10:58,785 INFO L276 IsEmpty]: Start isEmpty. Operand 2910 states and 2919 transitions. [2018-04-12 15:10:58,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2748 [2018-04-12 15:10:58,811 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:10:58,811 INFO L355 BasicCegarLoop]: trace histogram [430, 404, 404, 403, 403, 403, 27, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:10:58,811 INFO L408 AbstractCegarLoop]: === Iteration 68 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:10:58,812 INFO L82 PathProgramCache]: Analyzing trace with hash -2000509888, now seen corresponding path program 60 times [2018-04-12 15:10:58,812 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:10:58,812 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:10:58,812 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:10:58,812 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:10:58,812 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:10:58,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:10:58,930 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:11:02,069 INFO L134 CoverageAnalysis]: Checked inductivity of 512668 backedges. 140086 proven. 24201 refuted. 0 times theorem prover too weak. 348381 trivial. 0 not checked. [2018-04-12 15:11:02,070 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:11:02,070 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:11:02,077 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-12 15:11:05,568 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 55 check-sat command(s) [2018-04-12 15:11:05,568 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:11:05,595 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:11:09,061 INFO L134 CoverageAnalysis]: Checked inductivity of 512668 backedges. 118671 proven. 6322 refuted. 0 times theorem prover too weak. 387675 trivial. 0 not checked. [2018-04-12 15:11:09,086 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:11:09,087 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 61] total 118 [2018-04-12 15:11:09,087 INFO L442 AbstractCegarLoop]: Interpolant automaton has 118 states [2018-04-12 15:11:09,087 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 118 interpolants. [2018-04-12 15:11:09,088 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1926, Invalid=11880, Unknown=0, NotChecked=0, Total=13806 [2018-04-12 15:11:09,088 INFO L87 Difference]: Start difference. First operand 2910 states and 2919 transitions. Second operand 118 states. [2018-04-12 15:11:12,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:11:12,935 INFO L93 Difference]: Finished difference Result 2935 states and 2942 transitions. [2018-04-12 15:11:12,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 128 states. [2018-04-12 15:11:12,935 INFO L78 Accepts]: Start accepts. Automaton has 118 states. Word has length 2747 [2018-04-12 15:11:12,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:11:12,939 INFO L225 Difference]: With dead ends: 2935 [2018-04-12 15:11:12,939 INFO L226 Difference]: Without dead ends: 2929 [2018-04-12 15:11:12,941 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2927 GetRequests, 2691 SyntacticMatches, 0 SemanticMatches, 236 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19186 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=8103, Invalid=48303, Unknown=0, NotChecked=0, Total=56406 [2018-04-12 15:11:12,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2929 states. [2018-04-12 15:11:12,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2929 to 2910. [2018-04-12 15:11:12,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2910 states. [2018-04-12 15:11:12,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2910 states to 2910 states and 2917 transitions. [2018-04-12 15:11:12,953 INFO L78 Accepts]: Start accepts. Automaton has 2910 states and 2917 transitions. Word has length 2747 [2018-04-12 15:11:12,953 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:11:12,953 INFO L459 AbstractCegarLoop]: Abstraction has 2910 states and 2917 transitions. [2018-04-12 15:11:12,953 INFO L460 AbstractCegarLoop]: Interpolant automaton has 118 states. [2018-04-12 15:11:12,954 INFO L276 IsEmpty]: Start isEmpty. Operand 2910 states and 2917 transitions. [2018-04-12 15:11:12,979 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2754 [2018-04-12 15:11:12,979 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:11:12,979 INFO L355 BasicCegarLoop]: trace histogram [431, 405, 405, 404, 404, 404, 27, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:11:12,979 INFO L408 AbstractCegarLoop]: === Iteration 69 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:11:12,979 INFO L82 PathProgramCache]: Analyzing trace with hash -2094076728, now seen corresponding path program 61 times [2018-04-12 15:11:12,979 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:11:12,979 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:11:12,980 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:11:12,980 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:11:12,980 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:11:13,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:11:13,108 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:11:16,479 INFO L134 CoverageAnalysis]: Checked inductivity of 515142 backedges. 64064 proven. 2214 refuted. 0 times theorem prover too weak. 448864 trivial. 0 not checked. [2018-04-12 15:11:16,479 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:11:16,479 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:11:16,485 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:11:16,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:11:16,911 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:11:16,913 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:11:16,913 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:11:16,916 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:11:16,916 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:11:24,842 INFO L134 CoverageAnalysis]: Checked inductivity of 515142 backedges. 64064 proven. 2214 refuted. 0 times theorem prover too weak. 448864 trivial. 0 not checked. [2018-04-12 15:11:24,862 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:11:24,862 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 60 [2018-04-12 15:11:24,863 INFO L442 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-04-12 15:11:24,863 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-04-12 15:11:24,863 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=962, Invalid=2698, Unknown=0, NotChecked=0, Total=3660 [2018-04-12 15:11:24,863 INFO L87 Difference]: Start difference. First operand 2910 states and 2917 transitions. Second operand 61 states. [2018-04-12 15:11:27,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:11:27,191 INFO L93 Difference]: Finished difference Result 2936 states and 2944 transitions. [2018-04-12 15:11:27,191 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-04-12 15:11:27,191 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 2753 [2018-04-12 15:11:27,192 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:11:27,195 INFO L225 Difference]: With dead ends: 2936 [2018-04-12 15:11:27,195 INFO L226 Difference]: Without dead ends: 2936 [2018-04-12 15:11:27,195 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2813 GetRequests, 2672 SyntacticMatches, 54 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2375 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1535, Invalid=6297, Unknown=0, NotChecked=0, Total=7832 [2018-04-12 15:11:27,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2936 states. [2018-04-12 15:11:27,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2936 to 2916. [2018-04-12 15:11:27,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2916 states. [2018-04-12 15:11:27,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2916 states to 2916 states and 2924 transitions. [2018-04-12 15:11:27,209 INFO L78 Accepts]: Start accepts. Automaton has 2916 states and 2924 transitions. Word has length 2753 [2018-04-12 15:11:27,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:11:27,210 INFO L459 AbstractCegarLoop]: Abstraction has 2916 states and 2924 transitions. [2018-04-12 15:11:27,210 INFO L460 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-04-12 15:11:27,210 INFO L276 IsEmpty]: Start isEmpty. Operand 2916 states and 2924 transitions. [2018-04-12 15:11:27,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2760 [2018-04-12 15:11:27,237 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:11:27,237 INFO L355 BasicCegarLoop]: trace histogram [432, 406, 406, 405, 405, 405, 27, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:11:27,237 INFO L408 AbstractCegarLoop]: === Iteration 70 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:11:27,237 INFO L82 PathProgramCache]: Analyzing trace with hash 795920016, now seen corresponding path program 62 times [2018-04-12 15:11:27,237 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:11:27,238 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:11:27,238 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:11:27,238 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:11:27,238 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:11:27,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:11:27,382 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:11:30,199 INFO L134 CoverageAnalysis]: Checked inductivity of 517622 backedges. 68675 proven. 2137 refuted. 0 times theorem prover too weak. 446810 trivial. 0 not checked. [2018-04-12 15:11:30,199 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:11:30,199 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:11:30,205 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 15:11:30,637 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 15:11:30,637 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:11:30,659 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:11:34,513 INFO L134 CoverageAnalysis]: Checked inductivity of 517622 backedges. 68592 proven. 2220 refuted. 0 times theorem prover too weak. 446810 trivial. 0 not checked. [2018-04-12 15:11:34,536 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:11:34,537 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 61] total 120 [2018-04-12 15:11:34,537 INFO L442 AbstractCegarLoop]: Interpolant automaton has 120 states [2018-04-12 15:11:34,538 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 120 interpolants. [2018-04-12 15:11:34,538 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2564, Invalid=11716, Unknown=0, NotChecked=0, Total=14280 [2018-04-12 15:11:34,538 INFO L87 Difference]: Start difference. First operand 2916 states and 2924 transitions. Second operand 120 states. [2018-04-12 15:11:36,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:11:36,653 INFO L93 Difference]: Finished difference Result 3116 states and 3125 transitions. [2018-04-12 15:11:36,653 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2018-04-12 15:11:36,653 INFO L78 Accepts]: Start accepts. Automaton has 120 states. Word has length 2759 [2018-04-12 15:11:36,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:11:36,657 INFO L225 Difference]: With dead ends: 3116 [2018-04-12 15:11:36,657 INFO L226 Difference]: Without dead ends: 3116 [2018-04-12 15:11:36,658 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2875 GetRequests, 2700 SyntacticMatches, 0 SemanticMatches, 175 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9243 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=6174, Invalid=24978, Unknown=0, NotChecked=0, Total=31152 [2018-04-12 15:11:36,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3116 states. [2018-04-12 15:11:36,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3116 to 3096. [2018-04-12 15:11:36,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3096 states. [2018-04-12 15:11:36,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3096 states to 3096 states and 3105 transitions. [2018-04-12 15:11:36,672 INFO L78 Accepts]: Start accepts. Automaton has 3096 states and 3105 transitions. Word has length 2759 [2018-04-12 15:11:36,673 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:11:36,673 INFO L459 AbstractCegarLoop]: Abstraction has 3096 states and 3105 transitions. [2018-04-12 15:11:36,673 INFO L460 AbstractCegarLoop]: Interpolant automaton has 120 states. [2018-04-12 15:11:36,673 INFO L276 IsEmpty]: Start isEmpty. Operand 3096 states and 3105 transitions. [2018-04-12 15:11:36,704 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2934 [2018-04-12 15:11:36,704 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:11:36,704 INFO L355 BasicCegarLoop]: trace histogram [460, 433, 433, 432, 432, 432, 28, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:11:36,704 INFO L408 AbstractCegarLoop]: === Iteration 71 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:11:36,705 INFO L82 PathProgramCache]: Analyzing trace with hash -1868726615, now seen corresponding path program 63 times [2018-04-12 15:11:36,705 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:11:36,705 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:11:36,705 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:11:36,705 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:11:36,705 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:11:36,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:11:36,849 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:11:40,408 INFO L134 CoverageAnalysis]: Checked inductivity of 588033 backedges. 191070 proven. 6882 refuted. 0 times theorem prover too weak. 390081 trivial. 0 not checked. [2018-04-12 15:11:40,409 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:11:40,409 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:11:40,414 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 15:11:41,556 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 29 check-sat command(s) [2018-04-12 15:11:41,556 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:11:41,573 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:11:45,545 INFO L134 CoverageAnalysis]: Checked inductivity of 588033 backedges. 132335 proven. 6808 refuted. 0 times theorem prover too weak. 448890 trivial. 0 not checked. [2018-04-12 15:11:45,565 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:11:45,566 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 63] total 122 [2018-04-12 15:11:45,566 INFO L442 AbstractCegarLoop]: Interpolant automaton has 122 states [2018-04-12 15:11:45,566 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 122 interpolants. [2018-04-12 15:11:45,567 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2190, Invalid=12572, Unknown=0, NotChecked=0, Total=14762 [2018-04-12 15:11:45,567 INFO L87 Difference]: Start difference. First operand 3096 states and 3105 transitions. Second operand 122 states. [2018-04-12 15:11:49,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:11:49,812 INFO L93 Difference]: Finished difference Result 3121 states and 3128 transitions. [2018-04-12 15:11:49,812 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 124 states. [2018-04-12 15:11:49,812 INFO L78 Accepts]: Start accepts. Automaton has 122 states. Word has length 2933 [2018-04-12 15:11:49,813 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:11:49,815 INFO L225 Difference]: With dead ends: 3121 [2018-04-12 15:11:49,816 INFO L226 Difference]: Without dead ends: 3115 [2018-04-12 15:11:49,818 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3111 GetRequests, 2875 SyntacticMatches, 0 SemanticMatches, 236 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18442 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=8948, Invalid=47458, Unknown=0, NotChecked=0, Total=56406 [2018-04-12 15:11:49,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3115 states. [2018-04-12 15:11:49,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3115 to 3096. [2018-04-12 15:11:49,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3096 states. [2018-04-12 15:11:49,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3096 states to 3096 states and 3103 transitions. [2018-04-12 15:11:49,832 INFO L78 Accepts]: Start accepts. Automaton has 3096 states and 3103 transitions. Word has length 2933 [2018-04-12 15:11:49,833 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:11:49,833 INFO L459 AbstractCegarLoop]: Abstraction has 3096 states and 3103 transitions. [2018-04-12 15:11:49,833 INFO L460 AbstractCegarLoop]: Interpolant automaton has 122 states. [2018-04-12 15:11:49,833 INFO L276 IsEmpty]: Start isEmpty. Operand 3096 states and 3103 transitions. [2018-04-12 15:11:49,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2940 [2018-04-12 15:11:49,862 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:11:49,862 INFO L355 BasicCegarLoop]: trace histogram [461, 434, 434, 433, 433, 433, 28, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:11:49,862 INFO L408 AbstractCegarLoop]: === Iteration 72 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:11:49,862 INFO L82 PathProgramCache]: Analyzing trace with hash -326433679, now seen corresponding path program 64 times [2018-04-12 15:11:49,862 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:11:49,862 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:11:49,863 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:11:49,863 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:11:49,863 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:11:50,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:11:50,014 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:11:53,802 INFO L134 CoverageAnalysis]: Checked inductivity of 590683 backedges. 71253 proven. 2380 refuted. 0 times theorem prover too weak. 517050 trivial. 0 not checked. [2018-04-12 15:11:53,802 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:11:53,802 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:11:53,807 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-12 15:11:54,837 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-12 15:11:54,837 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:11:54,872 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:11:54,874 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:11:54,874 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:11:54,876 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:11:54,876 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:12:03,940 INFO L134 CoverageAnalysis]: Checked inductivity of 590683 backedges. 70959 proven. 8664 refuted. 0 times theorem prover too weak. 511060 trivial. 0 not checked. [2018-04-12 15:12:03,965 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:12:03,965 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 36] total 65 [2018-04-12 15:12:03,966 INFO L442 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-04-12 15:12:03,966 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-04-12 15:12:03,967 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1036, Invalid=3254, Unknown=0, NotChecked=0, Total=4290 [2018-04-12 15:12:03,967 INFO L87 Difference]: Start difference. First operand 3096 states and 3103 transitions. Second operand 66 states. [2018-04-12 15:12:05,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:12:05,731 INFO L93 Difference]: Finished difference Result 3122 states and 3130 transitions. [2018-04-12 15:12:05,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-04-12 15:12:05,731 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 2939 [2018-04-12 15:12:05,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:12:05,735 INFO L225 Difference]: With dead ends: 3122 [2018-04-12 15:12:05,735 INFO L226 Difference]: Without dead ends: 3122 [2018-04-12 15:12:05,735 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3001 GetRequests, 2853 SyntacticMatches, 55 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2778 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1674, Invalid=7256, Unknown=0, NotChecked=0, Total=8930 [2018-04-12 15:12:05,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3122 states. [2018-04-12 15:12:05,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3122 to 3102. [2018-04-12 15:12:05,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3102 states. [2018-04-12 15:12:05,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3102 states to 3102 states and 3110 transitions. [2018-04-12 15:12:05,750 INFO L78 Accepts]: Start accepts. Automaton has 3102 states and 3110 transitions. Word has length 2939 [2018-04-12 15:12:05,751 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:12:05,751 INFO L459 AbstractCegarLoop]: Abstraction has 3102 states and 3110 transitions. [2018-04-12 15:12:05,751 INFO L460 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-04-12 15:12:05,751 INFO L276 IsEmpty]: Start isEmpty. Operand 3102 states and 3110 transitions. [2018-04-12 15:12:05,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2946 [2018-04-12 15:12:05,781 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:12:05,781 INFO L355 BasicCegarLoop]: trace histogram [462, 435, 435, 434, 434, 434, 28, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:12:05,781 INFO L408 AbstractCegarLoop]: === Iteration 73 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:12:05,781 INFO L82 PathProgramCache]: Analyzing trace with hash -1088636039, now seen corresponding path program 65 times [2018-04-12 15:12:05,782 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:12:05,782 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:12:05,782 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:12:05,782 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:12:05,782 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:12:05,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:12:05,941 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:12:09,079 INFO L134 CoverageAnalysis]: Checked inductivity of 593339 backedges. 76203 proven. 2300 refuted. 0 times theorem prover too weak. 514836 trivial. 0 not checked. [2018-04-12 15:12:09,080 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:12:09,080 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:12:09,085 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-12 15:12:16,184 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 63 check-sat command(s) [2018-04-12 15:12:16,184 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:12:16,217 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:12:19,550 INFO L134 CoverageAnalysis]: Checked inductivity of 593339 backedges. 76081 proven. 13216 refuted. 0 times theorem prover too weak. 504042 trivial. 0 not checked. [2018-04-12 15:12:19,581 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:12:19,582 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 66] total 98 [2018-04-12 15:12:19,582 INFO L442 AbstractCegarLoop]: Interpolant automaton has 98 states [2018-04-12 15:12:19,583 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2018-04-12 15:12:19,583 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1947, Invalid=7559, Unknown=0, NotChecked=0, Total=9506 [2018-04-12 15:12:19,583 INFO L87 Difference]: Start difference. First operand 3102 states and 3110 transitions. Second operand 98 states. [2018-04-12 15:12:21,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:12:21,739 INFO L93 Difference]: Finished difference Result 3308 states and 3317 transitions. [2018-04-12 15:12:21,739 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-04-12 15:12:21,740 INFO L78 Accepts]: Start accepts. Automaton has 98 states. Word has length 2945 [2018-04-12 15:12:21,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:12:21,743 INFO L225 Difference]: With dead ends: 3308 [2018-04-12 15:12:21,743 INFO L226 Difference]: Without dead ends: 3308 [2018-04-12 15:12:21,745 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3067 GetRequests, 2910 SyntacticMatches, 0 SemanticMatches, 157 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4804 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=5434, Invalid=19688, Unknown=0, NotChecked=0, Total=25122 [2018-04-12 15:12:21,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3308 states. [2018-04-12 15:12:21,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3308 to 3288. [2018-04-12 15:12:21,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3288 states. [2018-04-12 15:12:21,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3288 states to 3288 states and 3297 transitions. [2018-04-12 15:12:21,757 INFO L78 Accepts]: Start accepts. Automaton has 3288 states and 3297 transitions. Word has length 2945 [2018-04-12 15:12:21,758 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:12:21,758 INFO L459 AbstractCegarLoop]: Abstraction has 3288 states and 3297 transitions. [2018-04-12 15:12:21,758 INFO L460 AbstractCegarLoop]: Interpolant automaton has 98 states. [2018-04-12 15:12:21,758 INFO L276 IsEmpty]: Start isEmpty. Operand 3288 states and 3297 transitions. [2018-04-12 15:12:21,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3126 [2018-04-12 15:12:21,791 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:12:21,791 INFO L355 BasicCegarLoop]: trace histogram [491, 463, 463, 462, 462, 462, 29, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:12:21,792 INFO L408 AbstractCegarLoop]: === Iteration 74 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:12:21,792 INFO L82 PathProgramCache]: Analyzing trace with hash 54435354, now seen corresponding path program 66 times [2018-04-12 15:12:21,792 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:12:21,792 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:12:21,792 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:12:21,792 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:12:21,792 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:12:21,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:12:21,940 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:12:25,864 INFO L134 CoverageAnalysis]: Checked inductivity of 671398 backedges. 205908 proven. 11861 refuted. 0 times theorem prover too weak. 453629 trivial. 0 not checked. [2018-04-12 15:12:25,865 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:12:25,865 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:12:25,870 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-12 15:12:32,140 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 59 check-sat command(s) [2018-04-12 15:12:32,140 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:12:32,175 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:12:36,019 INFO L134 CoverageAnalysis]: Checked inductivity of 671398 backedges. 151659 proven. 2324 refuted. 0 times theorem prover too weak. 517415 trivial. 0 not checked. [2018-04-12 15:12:36,048 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:12:36,048 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 60] total 118 [2018-04-12 15:12:36,049 INFO L442 AbstractCegarLoop]: Interpolant automaton has 118 states [2018-04-12 15:12:36,049 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 118 interpolants. [2018-04-12 15:12:36,049 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2237, Invalid=11569, Unknown=0, NotChecked=0, Total=13806 [2018-04-12 15:12:36,049 INFO L87 Difference]: Start difference. First operand 3288 states and 3297 transitions. Second operand 118 states. [2018-04-12 15:12:38,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:12:38,925 INFO L93 Difference]: Finished difference Result 3311 states and 3318 transitions. [2018-04-12 15:12:38,925 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 115 states. [2018-04-12 15:12:38,925 INFO L78 Accepts]: Start accepts. Automaton has 118 states. Word has length 3125 [2018-04-12 15:12:38,926 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:12:38,928 INFO L225 Difference]: With dead ends: 3311 [2018-04-12 15:12:38,928 INFO L226 Difference]: Without dead ends: 3305 [2018-04-12 15:12:38,930 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3273 GetRequests, 3073 SyntacticMatches, 0 SemanticMatches, 200 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13982 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=6368, Invalid=34234, Unknown=0, NotChecked=0, Total=40602 [2018-04-12 15:12:38,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3305 states. [2018-04-12 15:12:38,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3305 to 3288. [2018-04-12 15:12:38,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3288 states. [2018-04-12 15:12:38,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3288 states to 3288 states and 3295 transitions. [2018-04-12 15:12:38,941 INFO L78 Accepts]: Start accepts. Automaton has 3288 states and 3295 transitions. Word has length 3125 [2018-04-12 15:12:38,942 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:12:38,942 INFO L459 AbstractCegarLoop]: Abstraction has 3288 states and 3295 transitions. [2018-04-12 15:12:38,942 INFO L460 AbstractCegarLoop]: Interpolant automaton has 118 states. [2018-04-12 15:12:38,942 INFO L276 IsEmpty]: Start isEmpty. Operand 3288 states and 3295 transitions. [2018-04-12 15:12:38,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3132 [2018-04-12 15:12:38,975 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:12:38,975 INFO L355 BasicCegarLoop]: trace histogram [492, 464, 464, 463, 463, 463, 29, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:12:38,975 INFO L408 AbstractCegarLoop]: === Iteration 75 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:12:38,976 INFO L82 PathProgramCache]: Analyzing trace with hash 1958968098, now seen corresponding path program 67 times [2018-04-12 15:12:38,976 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:12:38,976 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:12:38,976 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:12:38,976 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:12:38,976 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:12:39,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:12:39,149 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:12:43,321 INFO L134 CoverageAnalysis]: Checked inductivity of 674230 backedges. 78960 proven. 2552 refuted. 0 times theorem prover too weak. 592718 trivial. 0 not checked. [2018-04-12 15:12:43,321 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:12:43,321 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:12:43,327 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:12:43,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:12:43,822 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:12:43,825 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:12:43,825 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:12:43,827 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:12:43,827 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:12:53,705 INFO L134 CoverageAnalysis]: Checked inductivity of 674230 backedges. 78960 proven. 2552 refuted. 0 times theorem prover too weak. 592718 trivial. 0 not checked. [2018-04-12 15:12:53,727 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:12:53,727 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 64 [2018-04-12 15:12:53,728 INFO L442 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-04-12 15:12:53,728 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-04-12 15:12:53,728 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1090, Invalid=3070, Unknown=0, NotChecked=0, Total=4160 [2018-04-12 15:12:53,728 INFO L87 Difference]: Start difference. First operand 3288 states and 3295 transitions. Second operand 65 states. [2018-04-12 15:12:56,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:12:56,214 INFO L93 Difference]: Finished difference Result 3314 states and 3322 transitions. [2018-04-12 15:12:56,214 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-04-12 15:12:56,214 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 3131 [2018-04-12 15:12:56,215 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:12:56,217 INFO L225 Difference]: With dead ends: 3314 [2018-04-12 15:12:56,217 INFO L226 Difference]: Without dead ends: 3314 [2018-04-12 15:12:56,218 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3195 GetRequests, 3044 SyntacticMatches, 58 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2725 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1734, Invalid=7196, Unknown=0, NotChecked=0, Total=8930 [2018-04-12 15:12:56,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3314 states. [2018-04-12 15:12:56,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3314 to 3294. [2018-04-12 15:12:56,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3294 states. [2018-04-12 15:12:56,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3294 states to 3294 states and 3302 transitions. [2018-04-12 15:12:56,231 INFO L78 Accepts]: Start accepts. Automaton has 3294 states and 3302 transitions. Word has length 3131 [2018-04-12 15:12:56,232 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:12:56,232 INFO L459 AbstractCegarLoop]: Abstraction has 3294 states and 3302 transitions. [2018-04-12 15:12:56,232 INFO L460 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-04-12 15:12:56,232 INFO L276 IsEmpty]: Start isEmpty. Operand 3294 states and 3302 transitions. [2018-04-12 15:12:56,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3138 [2018-04-12 15:12:56,266 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:12:56,267 INFO L355 BasicCegarLoop]: trace histogram [493, 465, 465, 464, 464, 464, 29, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:12:56,267 INFO L408 AbstractCegarLoop]: === Iteration 76 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:12:56,267 INFO L82 PathProgramCache]: Analyzing trace with hash -271341206, now seen corresponding path program 68 times [2018-04-12 15:12:56,267 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:12:56,267 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:12:56,268 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:12:56,268 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:12:56,268 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:12:56,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:12:56,461 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:12:59,902 INFO L134 CoverageAnalysis]: Checked inductivity of 677068 backedges. 84261 proven. 2469 refuted. 0 times theorem prover too weak. 590338 trivial. 0 not checked. [2018-04-12 15:12:59,902 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:12:59,902 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:12:59,908 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 15:13:00,411 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 15:13:00,411 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:13:00,436 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:13:05,379 INFO L134 CoverageAnalysis]: Checked inductivity of 677068 backedges. 84172 proven. 2558 refuted. 0 times theorem prover too weak. 590338 trivial. 0 not checked. [2018-04-12 15:13:05,401 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:13:05,402 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 65] total 128 [2018-04-12 15:13:05,403 INFO L442 AbstractCegarLoop]: Interpolant automaton has 128 states [2018-04-12 15:13:05,403 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 128 interpolants. [2018-04-12 15:13:05,404 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2926, Invalid=13330, Unknown=0, NotChecked=0, Total=16256 [2018-04-12 15:13:05,404 INFO L87 Difference]: Start difference. First operand 3294 states and 3302 transitions. Second operand 128 states. [2018-04-12 15:13:08,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:13:08,151 INFO L93 Difference]: Finished difference Result 3506 states and 3515 transitions. [2018-04-12 15:13:08,151 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2018-04-12 15:13:08,151 INFO L78 Accepts]: Start accepts. Automaton has 128 states. Word has length 3137 [2018-04-12 15:13:08,152 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:13:08,155 INFO L225 Difference]: With dead ends: 3506 [2018-04-12 15:13:08,155 INFO L226 Difference]: Without dead ends: 3506 [2018-04-12 15:13:08,156 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3261 GetRequests, 3074 SyntacticMatches, 0 SemanticMatches, 187 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10594 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=7034, Invalid=28498, Unknown=0, NotChecked=0, Total=35532 [2018-04-12 15:13:08,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3506 states. [2018-04-12 15:13:08,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3506 to 3486. [2018-04-12 15:13:08,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3486 states. [2018-04-12 15:13:08,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3486 states to 3486 states and 3495 transitions. [2018-04-12 15:13:08,169 INFO L78 Accepts]: Start accepts. Automaton has 3486 states and 3495 transitions. Word has length 3137 [2018-04-12 15:13:08,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:13:08,170 INFO L459 AbstractCegarLoop]: Abstraction has 3486 states and 3495 transitions. [2018-04-12 15:13:08,170 INFO L460 AbstractCegarLoop]: Interpolant automaton has 128 states. [2018-04-12 15:13:08,170 INFO L276 IsEmpty]: Start isEmpty. Operand 3486 states and 3495 transitions. [2018-04-12 15:13:08,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3324 [2018-04-12 15:13:08,208 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:13:08,208 INFO L355 BasicCegarLoop]: trace histogram [523, 494, 494, 493, 493, 493, 30, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:13:08,208 INFO L408 AbstractCegarLoop]: === Iteration 77 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:13:08,208 INFO L82 PathProgramCache]: Analyzing trace with hash -167440109, now seen corresponding path program 69 times [2018-04-12 15:13:08,208 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:13:08,209 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:13:08,209 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:13:08,209 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:13:08,209 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:13:08,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:13:08,432 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:13:13,056 INFO L134 CoverageAnalysis]: Checked inductivity of 763309 backedges. 221804 proven. 17010 refuted. 0 times theorem prover too weak. 524495 trivial. 0 not checked. [2018-04-12 15:13:13,056 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:13:13,056 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:13:13,061 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 15:13:14,847 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 31 check-sat command(s) [2018-04-12 15:13:14,847 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:13:14,878 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:13:19,599 INFO L134 CoverageAnalysis]: Checked inductivity of 763309 backedges. 162729 proven. 7834 refuted. 0 times theorem prover too weak. 592746 trivial. 0 not checked. [2018-04-12 15:13:19,622 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:13:19,623 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 67] total 130 [2018-04-12 15:13:19,624 INFO L442 AbstractCegarLoop]: Interpolant automaton has 130 states [2018-04-12 15:13:19,624 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 130 interpolants. [2018-04-12 15:13:19,624 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2445, Invalid=14325, Unknown=0, NotChecked=0, Total=16770 [2018-04-12 15:13:19,625 INFO L87 Difference]: Start difference. First operand 3486 states and 3495 transitions. Second operand 130 states. [2018-04-12 15:13:24,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:13:24,145 INFO L93 Difference]: Finished difference Result 3511 states and 3518 transitions. [2018-04-12 15:13:24,145 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 135 states. [2018-04-12 15:13:24,145 INFO L78 Accepts]: Start accepts. Automaton has 130 states. Word has length 3323 [2018-04-12 15:13:24,146 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:13:24,149 INFO L225 Difference]: With dead ends: 3511 [2018-04-12 15:13:24,149 INFO L226 Difference]: Without dead ends: 3505 [2018-04-12 15:13:24,153 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3516 GetRequests, 3261 SyntacticMatches, 0 SemanticMatches, 255 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21871 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=10110, Invalid=55682, Unknown=0, NotChecked=0, Total=65792 [2018-04-12 15:13:24,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3505 states. [2018-04-12 15:13:24,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3505 to 3486. [2018-04-12 15:13:24,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3486 states. [2018-04-12 15:13:24,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3486 states to 3486 states and 3493 transitions. [2018-04-12 15:13:24,168 INFO L78 Accepts]: Start accepts. Automaton has 3486 states and 3493 transitions. Word has length 3323 [2018-04-12 15:13:24,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:13:24,169 INFO L459 AbstractCegarLoop]: Abstraction has 3486 states and 3493 transitions. [2018-04-12 15:13:24,169 INFO L460 AbstractCegarLoop]: Interpolant automaton has 130 states. [2018-04-12 15:13:24,169 INFO L276 IsEmpty]: Start isEmpty. Operand 3486 states and 3493 transitions. [2018-04-12 15:13:24,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3330 [2018-04-12 15:13:24,206 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:13:24,206 INFO L355 BasicCegarLoop]: trace histogram [524, 495, 495, 494, 494, 494, 30, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:13:24,206 INFO L408 AbstractCegarLoop]: === Iteration 78 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:13:24,207 INFO L82 PathProgramCache]: Analyzing trace with hash 928153435, now seen corresponding path program 70 times [2018-04-12 15:13:24,207 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:13:24,207 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:13:24,207 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:13:24,207 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:13:24,207 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:13:24,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:13:24,395 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:13:28,993 INFO L134 CoverageAnalysis]: Checked inductivity of 766329 backedges. 87203 proven. 2730 refuted. 0 times theorem prover too weak. 676396 trivial. 0 not checked. [2018-04-12 15:13:28,993 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:13:28,993 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:13:28,999 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-12 15:13:30,244 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-12 15:13:30,245 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:13:30,276 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:13:30,283 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:13:30,283 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:13:30,285 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:13:30,285 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:13:41,480 INFO L134 CoverageAnalysis]: Checked inductivity of 766329 backedges. 86889 proven. 9886 refuted. 0 times theorem prover too weak. 669554 trivial. 0 not checked. [2018-04-12 15:13:41,509 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:13:41,509 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 38] total 69 [2018-04-12 15:13:41,510 INFO L442 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-04-12 15:13:41,510 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-04-12 15:13:41,510 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1168, Invalid=3662, Unknown=0, NotChecked=0, Total=4830 [2018-04-12 15:13:41,510 INFO L87 Difference]: Start difference. First operand 3486 states and 3493 transitions. Second operand 70 states. [2018-04-12 15:13:43,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:13:43,845 INFO L93 Difference]: Finished difference Result 3512 states and 3520 transitions. [2018-04-12 15:13:43,846 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-04-12 15:13:43,846 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 3329 [2018-04-12 15:13:43,847 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:13:43,849 INFO L225 Difference]: With dead ends: 3512 [2018-04-12 15:13:43,849 INFO L226 Difference]: Without dead ends: 3512 [2018-04-12 15:13:43,849 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3395 GetRequests, 3237 SyntacticMatches, 59 SemanticMatches, 99 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3156 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1881, Invalid=8219, Unknown=0, NotChecked=0, Total=10100 [2018-04-12 15:13:43,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3512 states. [2018-04-12 15:13:43,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3512 to 3492. [2018-04-12 15:13:43,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3492 states. [2018-04-12 15:13:43,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3492 states to 3492 states and 3500 transitions. [2018-04-12 15:13:43,863 INFO L78 Accepts]: Start accepts. Automaton has 3492 states and 3500 transitions. Word has length 3329 [2018-04-12 15:13:43,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:13:43,864 INFO L459 AbstractCegarLoop]: Abstraction has 3492 states and 3500 transitions. [2018-04-12 15:13:43,864 INFO L460 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-04-12 15:13:43,864 INFO L276 IsEmpty]: Start isEmpty. Operand 3492 states and 3500 transitions. [2018-04-12 15:13:43,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3336 [2018-04-12 15:13:43,909 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:13:43,909 INFO L355 BasicCegarLoop]: trace histogram [525, 496, 496, 495, 495, 495, 30, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:13:43,909 INFO L408 AbstractCegarLoop]: === Iteration 79 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:13:43,909 INFO L82 PathProgramCache]: Analyzing trace with hash -1420632349, now seen corresponding path program 71 times [2018-04-12 15:13:43,910 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:13:43,910 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:13:43,910 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:13:43,910 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:13:43,911 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:13:44,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:13:44,106 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:13:47,982 INFO L134 CoverageAnalysis]: Checked inductivity of 769355 backedges. 92867 proven. 2644 refuted. 0 times theorem prover too weak. 673844 trivial. 0 not checked. [2018-04-12 15:13:47,983 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:13:47,983 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:13:47,988 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-12 15:13:58,831 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 75 check-sat command(s) [2018-04-12 15:13:58,832 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:13:58,880 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:14:03,536 INFO L134 CoverageAnalysis]: Checked inductivity of 769355 backedges. 92731 proven. 15134 refuted. 0 times theorem prover too weak. 661490 trivial. 0 not checked. [2018-04-12 15:14:03,573 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:14:03,574 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 70] total 104 [2018-04-12 15:14:03,574 INFO L442 AbstractCegarLoop]: Interpolant automaton has 104 states [2018-04-12 15:14:03,575 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 104 interpolants. [2018-04-12 15:14:03,575 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2203, Invalid=8509, Unknown=0, NotChecked=0, Total=10712 [2018-04-12 15:14:03,575 INFO L87 Difference]: Start difference. First operand 3492 states and 3500 transitions. Second operand 104 states. [2018-04-12 15:14:06,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:14:06,514 INFO L93 Difference]: Finished difference Result 3710 states and 3719 transitions. [2018-04-12 15:14:06,515 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 105 states. [2018-04-12 15:14:06,515 INFO L78 Accepts]: Start accepts. Automaton has 104 states. Word has length 3335 [2018-04-12 15:14:06,516 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:14:06,519 INFO L225 Difference]: With dead ends: 3710 [2018-04-12 15:14:06,519 INFO L226 Difference]: Without dead ends: 3710 [2018-04-12 15:14:06,520 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3465 GetRequests, 3298 SyntacticMatches, 0 SemanticMatches, 167 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5417 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=6172, Invalid=22220, Unknown=0, NotChecked=0, Total=28392 [2018-04-12 15:14:06,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3710 states. [2018-04-12 15:14:06,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3710 to 3690. [2018-04-12 15:14:06,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3690 states. [2018-04-12 15:14:06,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3690 states to 3690 states and 3699 transitions. [2018-04-12 15:14:06,535 INFO L78 Accepts]: Start accepts. Automaton has 3690 states and 3699 transitions. Word has length 3335 [2018-04-12 15:14:06,536 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:14:06,536 INFO L459 AbstractCegarLoop]: Abstraction has 3690 states and 3699 transitions. [2018-04-12 15:14:06,536 INFO L460 AbstractCegarLoop]: Interpolant automaton has 104 states. [2018-04-12 15:14:06,537 INFO L276 IsEmpty]: Start isEmpty. Operand 3690 states and 3699 transitions. [2018-04-12 15:14:06,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3528 [2018-04-12 15:14:06,579 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:14:06,579 INFO L355 BasicCegarLoop]: trace histogram [556, 526, 526, 525, 525, 525, 31, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:14:06,579 INFO L408 AbstractCegarLoop]: === Iteration 80 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:14:06,580 INFO L82 PathProgramCache]: Analyzing trace with hash 970302484, now seen corresponding path program 72 times [2018-04-12 15:14:06,580 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:14:06,580 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:14:06,580 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:14:06,580 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:14:06,580 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:14:06,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:14:06,772 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:14:11,454 INFO L134 CoverageAnalysis]: Checked inductivity of 864330 backedges. 238794 proven. 22329 refuted. 0 times theorem prover too weak. 603207 trivial. 0 not checked. [2018-04-12 15:14:11,454 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:14:11,454 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:14:11,459 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-12 15:14:17,734 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 63 check-sat command(s) [2018-04-12 15:14:17,734 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:14:17,764 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:14:23,009 INFO L134 CoverageAnalysis]: Checked inductivity of 864330 backedges. 179531 proven. 8374 refuted. 0 times theorem prover too weak. 676425 trivial. 0 not checked. [2018-04-12 15:14:23,035 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:14:23,035 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 69] total 134 [2018-04-12 15:14:23,036 INFO L442 AbstractCegarLoop]: Interpolant automaton has 134 states [2018-04-12 15:14:23,036 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 134 interpolants. [2018-04-12 15:14:23,037 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2580, Invalid=15242, Unknown=0, NotChecked=0, Total=17822 [2018-04-12 15:14:23,037 INFO L87 Difference]: Start difference. First operand 3690 states and 3699 transitions. Second operand 134 states. [2018-04-12 15:14:27,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:14:27,807 INFO L93 Difference]: Finished difference Result 3715 states and 3722 transitions. [2018-04-12 15:14:27,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 140 states. [2018-04-12 15:14:27,807 INFO L78 Accepts]: Start accepts. Automaton has 134 states. Word has length 3527 [2018-04-12 15:14:27,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:14:27,811 INFO L225 Difference]: With dead ends: 3715 [2018-04-12 15:14:27,811 INFO L226 Difference]: Without dead ends: 3709 [2018-04-12 15:14:27,814 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3727 GetRequests, 3463 SyntacticMatches, 0 SemanticMatches, 264 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23607 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=10689, Invalid=59801, Unknown=0, NotChecked=0, Total=70490 [2018-04-12 15:14:27,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3709 states. [2018-04-12 15:14:27,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3709 to 3690. [2018-04-12 15:14:27,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3690 states. [2018-04-12 15:14:27,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3690 states to 3690 states and 3697 transitions. [2018-04-12 15:14:27,829 INFO L78 Accepts]: Start accepts. Automaton has 3690 states and 3697 transitions. Word has length 3527 [2018-04-12 15:14:27,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:14:27,830 INFO L459 AbstractCegarLoop]: Abstraction has 3690 states and 3697 transitions. [2018-04-12 15:14:27,830 INFO L460 AbstractCegarLoop]: Interpolant automaton has 134 states. [2018-04-12 15:14:27,830 INFO L276 IsEmpty]: Start isEmpty. Operand 3690 states and 3697 transitions. [2018-04-12 15:14:27,870 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3534 [2018-04-12 15:14:27,871 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:14:27,871 INFO L355 BasicCegarLoop]: trace histogram [557, 527, 527, 526, 526, 526, 31, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:14:27,871 INFO L408 AbstractCegarLoop]: === Iteration 81 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:14:27,871 INFO L82 PathProgramCache]: Analyzing trace with hash 863075740, now seen corresponding path program 73 times [2018-04-12 15:14:27,871 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:14:27,872 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:14:27,872 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:14:27,872 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:14:27,872 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:14:28,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:14:28,108 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:14:33,069 INFO L134 CoverageAnalysis]: Checked inductivity of 867544 backedges. 96000 proven. 2914 refuted. 0 times theorem prover too weak. 768630 trivial. 0 not checked. [2018-04-12 15:14:33,069 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:14:33,069 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:14:33,074 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:14:33,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:14:33,607 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:14:33,609 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 15:14:33,609 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 15:14:33,612 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 15:14:33,612 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 15:14:46,079 INFO L134 CoverageAnalysis]: Checked inductivity of 867544 backedges. 96000 proven. 2914 refuted. 0 times theorem prover too weak. 768630 trivial. 0 not checked. [2018-04-12 15:14:46,102 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:14:46,103 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 68 [2018-04-12 15:14:46,103 INFO L442 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-04-12 15:14:46,103 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-04-12 15:14:46,104 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1226, Invalid=3466, Unknown=0, NotChecked=0, Total=4692 [2018-04-12 15:14:46,104 INFO L87 Difference]: Start difference. First operand 3690 states and 3697 transitions. Second operand 69 states. [2018-04-12 15:14:48,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:14:48,961 INFO L93 Difference]: Finished difference Result 3716 states and 3724 transitions. [2018-04-12 15:14:48,961 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-04-12 15:14:48,962 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 3533 [2018-04-12 15:14:48,963 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:14:48,965 INFO L225 Difference]: With dead ends: 3716 [2018-04-12 15:14:48,965 INFO L226 Difference]: Without dead ends: 3716 [2018-04-12 15:14:48,966 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3601 GetRequests, 3440 SyntacticMatches, 62 SemanticMatches, 99 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3099 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1945, Invalid=8155, Unknown=0, NotChecked=0, Total=10100 [2018-04-12 15:14:48,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3716 states. [2018-04-12 15:14:48,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3716 to 3696. [2018-04-12 15:14:48,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3696 states. [2018-04-12 15:14:48,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3696 states to 3696 states and 3704 transitions. [2018-04-12 15:14:48,981 INFO L78 Accepts]: Start accepts. Automaton has 3696 states and 3704 transitions. Word has length 3533 [2018-04-12 15:14:48,981 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:14:48,981 INFO L459 AbstractCegarLoop]: Abstraction has 3696 states and 3704 transitions. [2018-04-12 15:14:48,981 INFO L460 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-04-12 15:14:48,982 INFO L276 IsEmpty]: Start isEmpty. Operand 3696 states and 3704 transitions. [2018-04-12 15:14:49,022 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3540 [2018-04-12 15:14:49,022 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:14:49,022 INFO L355 BasicCegarLoop]: trace histogram [558, 528, 528, 527, 527, 527, 31, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:14:49,022 INFO L408 AbstractCegarLoop]: === Iteration 82 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:14:49,022 INFO L82 PathProgramCache]: Analyzing trace with hash 1982883940, now seen corresponding path program 74 times [2018-04-12 15:14:49,022 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:14:49,022 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:14:49,023 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:14:49,023 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 15:14:49,023 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:14:49,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:14:49,221 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:14:53,425 INFO L134 CoverageAnalysis]: Checked inductivity of 870764 backedges. 102039 proven. 2825 refuted. 0 times theorem prover too weak. 765900 trivial. 0 not checked. [2018-04-12 15:14:53,425 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:14:53,425 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:14:53,430 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 15:14:53,962 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-12 15:14:53,962 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:14:53,992 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:14:59,546 INFO L134 CoverageAnalysis]: Checked inductivity of 870764 backedges. 101944 proven. 2920 refuted. 0 times theorem prover too weak. 765900 trivial. 0 not checked. [2018-04-12 15:14:59,568 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:14:59,569 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 69] total 136 [2018-04-12 15:14:59,570 INFO L442 AbstractCegarLoop]: Interpolant automaton has 136 states [2018-04-12 15:14:59,570 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 136 interpolants. [2018-04-12 15:14:59,571 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3312, Invalid=15048, Unknown=0, NotChecked=0, Total=18360 [2018-04-12 15:14:59,571 INFO L87 Difference]: Start difference. First operand 3696 states and 3704 transitions. Second operand 136 states. [2018-04-12 15:15:03,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:15:03,403 INFO L93 Difference]: Finished difference Result 3920 states and 3929 transitions. [2018-04-12 15:15:03,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 100 states. [2018-04-12 15:15:03,403 INFO L78 Accepts]: Start accepts. Automaton has 136 states. Word has length 3539 [2018-04-12 15:15:03,404 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:15:03,407 INFO L225 Difference]: With dead ends: 3920 [2018-04-12 15:15:03,408 INFO L226 Difference]: Without dead ends: 3920 [2018-04-12 15:15:03,409 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3671 GetRequests, 3472 SyntacticMatches, 0 SemanticMatches, 199 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12037 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=7950, Invalid=32250, Unknown=0, NotChecked=0, Total=40200 [2018-04-12 15:15:03,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3920 states. [2018-04-12 15:15:03,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3920 to 3900. [2018-04-12 15:15:03,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3900 states. [2018-04-12 15:15:03,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3900 states to 3900 states and 3909 transitions. [2018-04-12 15:15:03,426 INFO L78 Accepts]: Start accepts. Automaton has 3900 states and 3909 transitions. Word has length 3539 [2018-04-12 15:15:03,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:15:03,428 INFO L459 AbstractCegarLoop]: Abstraction has 3900 states and 3909 transitions. [2018-04-12 15:15:03,428 INFO L460 AbstractCegarLoop]: Interpolant automaton has 136 states. [2018-04-12 15:15:03,428 INFO L276 IsEmpty]: Start isEmpty. Operand 3900 states and 3909 transitions. [2018-04-12 15:15:03,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3738 [2018-04-12 15:15:03,474 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:15:03,474 INFO L355 BasicCegarLoop]: trace histogram [590, 559, 559, 558, 558, 558, 32, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:15:03,474 INFO L408 AbstractCegarLoop]: === Iteration 83 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:15:03,474 INFO L82 PathProgramCache]: Analyzing trace with hash -1802575459, now seen corresponding path program 75 times [2018-04-12 15:15:03,474 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:15:03,474 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:15:03,475 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:15:03,475 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:15:03,475 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:15:03,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 15:15:03,693 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 15:15:08,791 INFO L134 CoverageAnalysis]: Checked inductivity of 975043 backedges. 256914 proven. 27818 refuted. 0 times theorem prover too weak. 690311 trivial. 0 not checked. [2018-04-12 15:15:08,791 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 15:15:08,791 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 15:15:08,796 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-12 15:15:10,662 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2018-04-12 15:15:10,662 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 15:15:10,684 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 15:15:16,147 INFO L134 CoverageAnalysis]: Checked inductivity of 975043 backedges. 197451 proven. 8932 refuted. 0 times theorem prover too weak. 768660 trivial. 0 not checked. [2018-04-12 15:15:16,171 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 15:15:16,172 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 71] total 138 [2018-04-12 15:15:16,172 INFO L442 AbstractCegarLoop]: Interpolant automaton has 138 states [2018-04-12 15:15:16,173 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 138 interpolants. [2018-04-12 15:15:16,173 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2720, Invalid=16186, Unknown=0, NotChecked=0, Total=18906 [2018-04-12 15:15:16,173 INFO L87 Difference]: Start difference. First operand 3900 states and 3909 transitions. Second operand 138 states. [2018-04-12 15:15:21,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 15:15:21,254 INFO L93 Difference]: Finished difference Result 3925 states and 3932 transitions. [2018-04-12 15:15:21,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 145 states. [2018-04-12 15:15:21,254 INFO L78 Accepts]: Start accepts. Automaton has 138 states. Word has length 3737 [2018-04-12 15:15:21,255 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 15:15:21,258 INFO L225 Difference]: With dead ends: 3925 [2018-04-12 15:15:21,258 INFO L226 Difference]: Without dead ends: 3919 [2018-04-12 15:15:21,262 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3944 GetRequests, 3671 SyntacticMatches, 0 SemanticMatches, 273 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25405 ImplicationChecksByTransitivity, 4.8s TimeCoverageRelationStatistics Valid=11289, Invalid=64061, Unknown=0, NotChecked=0, Total=75350 [2018-04-12 15:15:21,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3919 states. [2018-04-12 15:15:21,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3919 to 3900. [2018-04-12 15:15:21,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3900 states. [2018-04-12 15:15:21,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3900 states to 3900 states and 3907 transitions. [2018-04-12 15:15:21,281 INFO L78 Accepts]: Start accepts. Automaton has 3900 states and 3907 transitions. Word has length 3737 [2018-04-12 15:15:21,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 15:15:21,282 INFO L459 AbstractCegarLoop]: Abstraction has 3900 states and 3907 transitions. [2018-04-12 15:15:21,282 INFO L460 AbstractCegarLoop]: Interpolant automaton has 138 states. [2018-04-12 15:15:21,282 INFO L276 IsEmpty]: Start isEmpty. Operand 3900 states and 3907 transitions. [2018-04-12 15:15:21,327 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3744 [2018-04-12 15:15:21,327 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 15:15:21,328 INFO L355 BasicCegarLoop]: trace histogram [591, 560, 560, 559, 559, 559, 32, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 15:15:21,328 INFO L408 AbstractCegarLoop]: === Iteration 84 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-12 15:15:21,328 INFO L82 PathProgramCache]: Analyzing trace with hash -1634918299, now seen corresponding path program 76 times [2018-04-12 15:15:21,328 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 15:15:21,328 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 15:15:21,328 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:15:21,328 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 15:15:21,329 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 15:15:22,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-04-12 15:15:22,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-04-12 15:15:23,596 INFO L421 BasicCegarLoop]: Counterexample might be feasible [2018-04-12 15:15:24,094 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 12.04 03:15:24 BoogieIcfgContainer [2018-04-12 15:15:24,094 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-04-12 15:15:24,095 INFO L168 Benchmark]: Toolchain (without parser) took 521719.70 ms. Allocated memory was 400.0 MB in the beginning and 2.6 GB in the end (delta: 2.2 GB). Free memory was 341.6 MB in the beginning and 1.9 GB in the end (delta: -1.6 GB). Peak memory consumption was 2.2 GB. Max. memory is 5.3 GB. [2018-04-12 15:15:24,096 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 400.0 MB. Free memory is still 361.9 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-04-12 15:15:24,096 INFO L168 Benchmark]: CACSL2BoogieTranslator took 156.51 ms. Allocated memory is still 400.0 MB. Free memory was 341.6 MB in the beginning and 331.1 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. [2018-04-12 15:15:24,097 INFO L168 Benchmark]: Boogie Preprocessor took 25.15 ms. Allocated memory is still 400.0 MB. Free memory was 331.1 MB in the beginning and 329.7 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. [2018-04-12 15:15:24,097 INFO L168 Benchmark]: RCFGBuilder took 237.99 ms. Allocated memory was 400.0 MB in the beginning and 607.6 MB in the end (delta: 207.6 MB). Free memory was 329.7 MB in the beginning and 568.5 MB in the end (delta: -238.7 MB). Peak memory consumption was 24.8 MB. Max. memory is 5.3 GB. [2018-04-12 15:15:24,097 INFO L168 Benchmark]: TraceAbstraction took 521297.26 ms. Allocated memory was 607.6 MB in the beginning and 2.6 GB in the end (delta: 2.0 GB). Free memory was 568.5 MB in the beginning and 1.9 GB in the end (delta: -1.3 GB). Peak memory consumption was 2.3 GB. Max. memory is 5.3 GB. [2018-04-12 15:15:24,098 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 400.0 MB. Free memory is still 361.9 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 156.51 ms. Allocated memory is still 400.0 MB. Free memory was 341.6 MB in the beginning and 331.1 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 25.15 ms. Allocated memory is still 400.0 MB. Free memory was 331.1 MB in the beginning and 329.7 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. * RCFGBuilder took 237.99 ms. Allocated memory was 400.0 MB in the beginning and 607.6 MB in the end (delta: 207.6 MB). Free memory was 329.7 MB in the beginning and 568.5 MB in the end (delta: -238.7 MB). Peak memory consumption was 24.8 MB. Max. memory is 5.3 GB. * TraceAbstraction took 521297.26 ms. Allocated memory was 607.6 MB in the beginning and 2.6 GB in the end (delta: 2.0 GB). Free memory was 568.5 MB in the beginning and 1.9 GB in the end (delta: -1.3 GB). Peak memory consumption was 2.3 GB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: pointer dereference may fail pointer dereference may fail We found a FailurePath: [L24] int i, b[32]; [L25] FCALL char mask[32]; VAL [mask={64:0}] [L26] i = 0 VAL [i=0, mask={64:0}] [L26] COND TRUE i < sizeof(mask) VAL [i=0, mask={64:0}] [L27] EXPR b[i] VAL [i=0, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=0, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=0, b={64:0}, b={64:0}, i=0, size=0] [L17] COND TRUE i <= size + 1 VAL [\old(size)=0, b={64:0}, b={64:0}, i=0, size=0] [L18] EXPR a[i] VAL [\old(size)=0, b={64:0}, b={64:0}, i=0, size=0] [L18] EXPR, FCALL b[i] VAL [\old(size)=0, b={64:0}, b={64:0}, b[i]=34, i=0, size=0] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=0, b={64:0}, b={64:0}, i=1, size=0] [L18] EXPR a[i] VAL [\old(size)=0, b={64:0}, b={64:0}, i=1, size=0] [L18] EXPR, FCALL b[i] VAL [\old(size)=0, b={64:0}, b={64:0}, b[i]=67, i=1, size=0] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=0, b={64:0}, b={64:0}, i=2, size=0] [L20] RET return i; VAL [\old(size)=0, \result=2, b={64:0}, b={64:0}, i=2, size=0] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=2, i=0, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=1, mask={64:0}] [L27] EXPR b[i] VAL [i=1, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=1, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={64:0}, b={64:0}, i=0, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={64:0}, b={64:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={64:0}, b={64:0}, i=0, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={64:0}, b={64:0}, b[i]=34, i=0, size=1] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={64:0}, b={64:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={64:0}, b={64:0}, i=1, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={64:0}, b={64:0}, b[i]=67, i=1, size=1] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={64:0}, b={64:0}, i=2, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={64:0}, b={64:0}, i=2, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={64:0}, b={64:0}, b[i]=33, i=2, size=1] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=1, b={64:0}, b={64:0}, i=3, size=1] [L20] RET return i; VAL [\old(size)=1, \result=3, b={64:0}, b={64:0}, i=3, size=1] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=3, i=1, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=2, mask={64:0}] [L27] EXPR b[i] VAL [i=2, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=2, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={64:0}, b={64:0}, i=0, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={64:0}, b={64:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={64:0}, b={64:0}, i=0, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={64:0}, b={64:0}, b[i]=34, i=0, size=2] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={64:0}, b={64:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={64:0}, b={64:0}, i=1, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={64:0}, b={64:0}, b[i]=67, i=1, size=2] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={64:0}, b={64:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={64:0}, b={64:0}, i=2, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={64:0}, b={64:0}, b[i]=33, i=2, size=2] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={64:0}, b={64:0}, i=3, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={64:0}, b={64:0}, i=3, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={64:0}, b={64:0}, b[i]=43, i=3, size=2] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=2, b={64:0}, b={64:0}, i=4, size=2] [L20] RET return i; VAL [\old(size)=2, \result=4, b={64:0}, b={64:0}, i=4, size=2] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=4, i=2, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=3, mask={64:0}] [L27] EXPR b[i] VAL [i=3, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=3, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={64:0}, b={64:0}, i=0, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={64:0}, b={64:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={64:0}, b={64:0}, i=0, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={64:0}, b={64:0}, b[i]=34, i=0, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={64:0}, b={64:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={64:0}, b={64:0}, i=1, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={64:0}, b={64:0}, b[i]=67, i=1, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={64:0}, b={64:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={64:0}, b={64:0}, i=2, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={64:0}, b={64:0}, b[i]=33, i=2, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={64:0}, b={64:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={64:0}, b={64:0}, i=3, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={64:0}, b={64:0}, b[i]=43, i=3, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={64:0}, b={64:0}, i=4, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={64:0}, b={64:0}, i=4, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={64:0}, b={64:0}, b[i]=55, i=4, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=3, b={64:0}, b={64:0}, i=5, size=3] [L20] RET return i; VAL [\old(size)=3, \result=5, b={64:0}, b={64:0}, i=5, size=3] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=5, i=3, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=4, mask={64:0}] [L27] EXPR b[i] VAL [i=4, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=4, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={64:0}, b={64:0}, i=0, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={64:0}, b={64:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={64:0}, b={64:0}, i=0, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={64:0}, b={64:0}, b[i]=34, i=0, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={64:0}, b={64:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={64:0}, b={64:0}, i=1, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={64:0}, b={64:0}, b[i]=67, i=1, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={64:0}, b={64:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={64:0}, b={64:0}, i=2, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={64:0}, b={64:0}, b[i]=33, i=2, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={64:0}, b={64:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={64:0}, b={64:0}, i=3, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={64:0}, b={64:0}, b[i]=43, i=3, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={64:0}, b={64:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={64:0}, b={64:0}, i=4, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={64:0}, b={64:0}, b[i]=55, i=4, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={64:0}, b={64:0}, i=5, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={64:0}, b={64:0}, i=5, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={64:0}, b={64:0}, b[i]=46, i=5, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=4, b={64:0}, b={64:0}, i=6, size=4] [L20] RET return i; VAL [\old(size)=4, \result=6, b={64:0}, b={64:0}, i=6, size=4] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=6, i=4, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=5, mask={64:0}] [L27] EXPR b[i] VAL [i=5, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=5, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={64:0}, b={64:0}, i=0, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={64:0}, b={64:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={64:0}, b={64:0}, i=0, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={64:0}, b={64:0}, b[i]=34, i=0, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={64:0}, b={64:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={64:0}, b={64:0}, i=1, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={64:0}, b={64:0}, b[i]=67, i=1, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={64:0}, b={64:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={64:0}, b={64:0}, i=2, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={64:0}, b={64:0}, b[i]=33, i=2, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={64:0}, b={64:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={64:0}, b={64:0}, i=3, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={64:0}, b={64:0}, b[i]=43, i=3, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={64:0}, b={64:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={64:0}, b={64:0}, i=4, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={64:0}, b={64:0}, b[i]=55, i=4, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={64:0}, b={64:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={64:0}, b={64:0}, i=5, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={64:0}, b={64:0}, b[i]=46, i=5, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={64:0}, b={64:0}, i=6, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={64:0}, b={64:0}, i=6, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={64:0}, b={64:0}, b[i]=41, i=6, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=5, b={64:0}, b={64:0}, i=7, size=5] [L20] RET return i; VAL [\old(size)=5, \result=7, b={64:0}, b={64:0}, i=7, size=5] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=7, i=5, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=6, mask={64:0}] [L27] EXPR b[i] VAL [i=6, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=6, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={64:0}, b={64:0}, i=0, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=0, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=34, i=0, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=1, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=67, i=1, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=2, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=33, i=2, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=3, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=43, i=3, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=4, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=55, i=4, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=5, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=46, i=5, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=6, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=41, i=6, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=7, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=7, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=60, i=7, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=6, b={64:0}, b={64:0}, i=8, size=6] [L20] RET return i; VAL [\old(size)=6, \result=8, b={64:0}, b={64:0}, i=8, size=6] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=8, i=6, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=7, mask={64:0}] [L27] EXPR b[i] VAL [i=7, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=7, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={64:0}, b={64:0}, i=0, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=0, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=34, i=0, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=1, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=67, i=1, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=2, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=33, i=2, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=3, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=43, i=3, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=4, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=55, i=4, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=5, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=46, i=5, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=6, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=41, i=6, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=7, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=60, i=7, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=8, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=8, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=47, i=8, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=7, b={64:0}, b={64:0}, i=9, size=7] [L20] RET return i; VAL [\old(size)=7, \result=9, b={64:0}, b={64:0}, i=9, size=7] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=9, i=7, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=8, mask={64:0}] [L27] EXPR b[i] VAL [i=8, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=8, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={64:0}, b={64:0}, i=0, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=0, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=34, i=0, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=1, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=67, i=1, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=2, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=33, i=2, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=3, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=43, i=3, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=4, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=55, i=4, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=5, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=46, i=5, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=6, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=41, i=6, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=7, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=60, i=7, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=8, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=47, i=8, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=9, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=9, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=49, i=9, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=8, b={64:0}, b={64:0}, i=10, size=8] [L20] RET return i; VAL [\old(size)=8, \result=10, b={64:0}, b={64:0}, i=10, size=8] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=10, i=8, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=9, mask={64:0}] [L27] EXPR b[i] VAL [i=9, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=9, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={64:0}, b={64:0}, i=0, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=0, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=34, i=0, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=1, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=67, i=1, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=2, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=33, i=2, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=3, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=43, i=3, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=4, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=55, i=4, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=5, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=46, i=5, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=6, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=41, i=6, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=7, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=60, i=7, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=8, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=47, i=8, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=9, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=49, i=9, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=10, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=10, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=44, i=10, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=9, b={64:0}, b={64:0}, i=11, size=9] [L20] RET return i; VAL [\old(size)=9, \result=11, b={64:0}, b={64:0}, i=11, size=9] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=11, i=9, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=10, mask={64:0}] [L27] EXPR b[i] VAL [i=10, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=10, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={64:0}, b={64:0}, i=0, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=0, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=34, i=0, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=1, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=67, i=1, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=2, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=33, i=2, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=3, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=43, i=3, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=4, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=55, i=4, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=5, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=46, i=5, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=6, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=41, i=6, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=7, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=60, i=7, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=8, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=47, i=8, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=9, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=49, i=9, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=10, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=44, i=10, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=11, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=11, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=65, i=11, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=10, b={64:0}, b={64:0}, i=12, size=10] [L20] RET return i; VAL [\old(size)=10, \result=12, b={64:0}, b={64:0}, i=12, size=10] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=12, i=10, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=11, mask={64:0}] [L27] EXPR b[i] VAL [i=11, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=11, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={64:0}, b={64:0}, i=0, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=0, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=34, i=0, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=1, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=67, i=1, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=2, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=33, i=2, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=3, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=43, i=3, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=4, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=55, i=4, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=5, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=46, i=5, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=6, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=41, i=6, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=7, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=60, i=7, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=8, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=47, i=8, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=9, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=49, i=9, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=10, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=44, i=10, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=11, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=65, i=11, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=12, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=12, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=62, i=12, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=11, b={64:0}, b={64:0}, i=13, size=11] [L20] RET return i; VAL [\old(size)=11, \result=13, b={64:0}, b={64:0}, i=13, size=11] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=13, i=11, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=12, mask={64:0}] [L27] EXPR b[i] VAL [i=12, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=12, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={64:0}, b={64:0}, i=0, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=0, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=34, i=0, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=1, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=67, i=1, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=2, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=33, i=2, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=3, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=43, i=3, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=4, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=55, i=4, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=5, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=46, i=5, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=6, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=41, i=6, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=7, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=60, i=7, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=8, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=47, i=8, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=9, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=49, i=9, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=10, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=44, i=10, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=11, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=65, i=11, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=12, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=62, i=12, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=13, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=13, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=66, i=13, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=12, b={64:0}, b={64:0}, i=14, size=12] [L20] RET return i; VAL [\old(size)=12, \result=14, b={64:0}, b={64:0}, i=14, size=12] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=14, i=12, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=13, mask={64:0}] [L27] EXPR b[i] VAL [i=13, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=13, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={64:0}, b={64:0}, i=0, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=0, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=34, i=0, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=1, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=67, i=1, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=2, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=33, i=2, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=3, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=43, i=3, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=4, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=55, i=4, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=5, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=46, i=5, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=6, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=41, i=6, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=7, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=60, i=7, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=8, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=47, i=8, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=9, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=49, i=9, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=10, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=44, i=10, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=11, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=65, i=11, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=12, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=62, i=12, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=13, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=66, i=13, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=14, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=14, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=45, i=14, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=13, b={64:0}, b={64:0}, i=15, size=13] [L20] RET return i; VAL [\old(size)=13, \result=15, b={64:0}, b={64:0}, i=15, size=13] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=15, i=13, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=14, mask={64:0}] [L27] EXPR b[i] VAL [i=14, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=14, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={64:0}, b={64:0}, i=0, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=0, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=34, i=0, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=1, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=67, i=1, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=2, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=33, i=2, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=3, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=43, i=3, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=4, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=55, i=4, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=5, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=46, i=5, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=6, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=41, i=6, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=7, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=60, i=7, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=8, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=47, i=8, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=9, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=49, i=9, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=10, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=44, i=10, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=11, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=65, i=11, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=12, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=62, i=12, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=13, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=66, i=13, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=14, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=45, i=14, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=15, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=15, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=48, i=15, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=14, b={64:0}, b={64:0}, i=16, size=14] [L20] RET return i; VAL [\old(size)=14, \result=16, b={64:0}, b={64:0}, i=16, size=14] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=16, i=14, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=15, mask={64:0}] [L27] EXPR b[i] VAL [i=15, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=15, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={64:0}, b={64:0}, i=0, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=0, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=34, i=0, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=1, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=67, i=1, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=2, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=33, i=2, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=3, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=43, i=3, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=4, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=55, i=4, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=5, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=46, i=5, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=6, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=41, i=6, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=7, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=60, i=7, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=8, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=47, i=8, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=9, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=49, i=9, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=10, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=44, i=10, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=11, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=65, i=11, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=12, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=62, i=12, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=13, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=66, i=13, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=14, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=45, i=14, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=15, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=48, i=15, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=16, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=16, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=57, i=16, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=15, b={64:0}, b={64:0}, i=17, size=15] [L20] RET return i; VAL [\old(size)=15, \result=17, b={64:0}, b={64:0}, i=17, size=15] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=17, i=15, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=16, mask={64:0}] [L27] EXPR b[i] VAL [i=16, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=16, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={64:0}, b={64:0}, i=0, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=0, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=34, i=0, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=1, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=67, i=1, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=2, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=33, i=2, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=3, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=43, i=3, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=4, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=55, i=4, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=5, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=46, i=5, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=6, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=41, i=6, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=7, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=60, i=7, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=8, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=47, i=8, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=9, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=49, i=9, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=10, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=44, i=10, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=11, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=65, i=11, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=12, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=62, i=12, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=13, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=66, i=13, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=14, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=45, i=14, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=15, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=48, i=15, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=16, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=57, i=16, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=17, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=17, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=36, i=17, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=16, b={64:0}, b={64:0}, i=18, size=16] [L20] RET return i; VAL [\old(size)=16, \result=18, b={64:0}, b={64:0}, i=18, size=16] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=18, i=16, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=17, mask={64:0}] [L27] EXPR b[i] VAL [i=17, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=17, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={64:0}, b={64:0}, i=0, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=0, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=34, i=0, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=1, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=67, i=1, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=2, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=33, i=2, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=3, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=43, i=3, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=4, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=55, i=4, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=5, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=46, i=5, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=6, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=41, i=6, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=7, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=60, i=7, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=8, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=47, i=8, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=9, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=49, i=9, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=10, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=44, i=10, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=11, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=65, i=11, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=12, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=62, i=12, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=13, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=66, i=13, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=14, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=45, i=14, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=15, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=48, i=15, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=16, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=57, i=16, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=17, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=36, i=17, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=18, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=18, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=56, i=18, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=17, b={64:0}, b={64:0}, i=19, size=17] [L20] RET return i; VAL [\old(size)=17, \result=19, b={64:0}, b={64:0}, i=19, size=17] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=19, i=17, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=18, mask={64:0}] [L27] EXPR b[i] VAL [i=18, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=18, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={64:0}, b={64:0}, i=0, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=0, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=34, i=0, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=1, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=67, i=1, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=2, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=33, i=2, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=3, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=43, i=3, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=4, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=55, i=4, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=5, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=46, i=5, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=6, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=41, i=6, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=7, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=60, i=7, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=8, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=47, i=8, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=9, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=49, i=9, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=10, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=44, i=10, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=11, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=65, i=11, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=12, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=62, i=12, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=13, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=66, i=13, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=14, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=45, i=14, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=15, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=48, i=15, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=16, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=57, i=16, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=17, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=36, i=17, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=18, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=56, i=18, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=19, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=19, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=58, i=19, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=18, b={64:0}, b={64:0}, i=20, size=18] [L20] RET return i; VAL [\old(size)=18, \result=20, b={64:0}, b={64:0}, i=20, size=18] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=20, i=18, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=19, mask={64:0}] [L27] EXPR b[i] VAL [i=19, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=19, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={64:0}, b={64:0}, i=0, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=0, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=34, i=0, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=1, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=67, i=1, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=2, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=33, i=2, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=3, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=43, i=3, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=4, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=55, i=4, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=5, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=46, i=5, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=6, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=41, i=6, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=7, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=60, i=7, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=8, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=47, i=8, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=9, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=49, i=9, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=10, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=44, i=10, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=11, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=65, i=11, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=12, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=62, i=12, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=13, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=66, i=13, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=14, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=45, i=14, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=15, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=48, i=15, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=16, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=57, i=16, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=17, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=36, i=17, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=18, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=56, i=18, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=19, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=58, i=19, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=20, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=20, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=51, i=20, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=19, b={64:0}, b={64:0}, i=21, size=19] [L20] RET return i; VAL [\old(size)=19, \result=21, b={64:0}, b={64:0}, i=21, size=19] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=21, i=19, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=20, mask={64:0}] [L27] EXPR b[i] VAL [i=20, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=20, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={64:0}, b={64:0}, i=0, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=0, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=34, i=0, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=1, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=67, i=1, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=2, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=33, i=2, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=3, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=43, i=3, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=4, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=55, i=4, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=5, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=46, i=5, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=6, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=41, i=6, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=7, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=60, i=7, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=8, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=47, i=8, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=9, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=49, i=9, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=10, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=44, i=10, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=11, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=65, i=11, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=12, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=62, i=12, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=13, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=66, i=13, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=14, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=45, i=14, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=15, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=48, i=15, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=16, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=57, i=16, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=17, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=36, i=17, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=18, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=56, i=18, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=19, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=58, i=19, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=20, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=51, i=20, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=21, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=21, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=35, i=21, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=20, b={64:0}, b={64:0}, i=22, size=20] [L20] RET return i; VAL [\old(size)=20, \result=22, b={64:0}, b={64:0}, i=22, size=20] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=22, i=20, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=21, mask={64:0}] [L27] EXPR b[i] VAL [i=21, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=21, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={64:0}, b={64:0}, i=0, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=0, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=34, i=0, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=1, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=67, i=1, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=2, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=33, i=2, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=3, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=43, i=3, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=4, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=55, i=4, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=5, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=46, i=5, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=6, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=41, i=6, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=7, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=60, i=7, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=8, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=47, i=8, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=9, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=49, i=9, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=10, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=44, i=10, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=11, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=65, i=11, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=12, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=62, i=12, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=13, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=66, i=13, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=14, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=45, i=14, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=15, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=48, i=15, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=16, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=57, i=16, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=17, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=36, i=17, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=18, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=56, i=18, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=19, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=58, i=19, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=20, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=51, i=20, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=21, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=35, i=21, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=22, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=22, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=42, i=22, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=21, b={64:0}, b={64:0}, i=23, size=21] [L20] RET return i; VAL [\old(size)=21, \result=23, b={64:0}, b={64:0}, i=23, size=21] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=23, i=21, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=22, mask={64:0}] [L27] EXPR b[i] VAL [i=22, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=22, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={64:0}, b={64:0}, i=0, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=0, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=34, i=0, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=1, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=67, i=1, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=2, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=33, i=2, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=3, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=43, i=3, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=4, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=55, i=4, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=5, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=46, i=5, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=6, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=41, i=6, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=7, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=60, i=7, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=8, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=47, i=8, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=9, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=49, i=9, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=10, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=44, i=10, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=11, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=65, i=11, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=12, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=62, i=12, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=13, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=66, i=13, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=14, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=45, i=14, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=15, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=48, i=15, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=16, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=57, i=16, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=17, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=36, i=17, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=18, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=56, i=18, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=19, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=58, i=19, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=20, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=51, i=20, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=21, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=35, i=21, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=22, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=42, i=22, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=23, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=23, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=54, i=23, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=22, b={64:0}, b={64:0}, i=24, size=22] [L20] RET return i; VAL [\old(size)=22, \result=24, b={64:0}, b={64:0}, i=24, size=22] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=24, i=22, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=23, mask={64:0}] [L27] EXPR b[i] VAL [i=23, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=23, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={64:0}, b={64:0}, i=0, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=0, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=34, i=0, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=1, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=67, i=1, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=2, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=33, i=2, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=3, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=43, i=3, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=4, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=55, i=4, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=5, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=46, i=5, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=6, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=41, i=6, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=7, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=60, i=7, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=8, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=47, i=8, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=9, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=49, i=9, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=10, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=44, i=10, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=11, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=65, i=11, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=12, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=62, i=12, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=13, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=66, i=13, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=14, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=45, i=14, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=15, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=48, i=15, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=16, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=57, i=16, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=17, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=36, i=17, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=18, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=56, i=18, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=19, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=58, i=19, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=20, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=51, i=20, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=21, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=35, i=21, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=22, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=42, i=22, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=23, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=54, i=23, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=24, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=24, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=63, i=24, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=23, b={64:0}, b={64:0}, i=25, size=23] [L20] RET return i; VAL [\old(size)=23, \result=25, b={64:0}, b={64:0}, i=25, size=23] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=25, i=23, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=24, mask={64:0}] [L27] EXPR b[i] VAL [i=24, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=24, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={64:0}, b={64:0}, i=0, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=0, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=34, i=0, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=1, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=67, i=1, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=2, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=33, i=2, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=3, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=43, i=3, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=4, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=55, i=4, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=5, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=46, i=5, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=6, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=41, i=6, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=7, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=60, i=7, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=8, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=47, i=8, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=9, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=49, i=9, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=10, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=44, i=10, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=11, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=65, i=11, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=12, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=62, i=12, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=13, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=66, i=13, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=14, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=45, i=14, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=15, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=48, i=15, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=16, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=57, i=16, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=17, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=36, i=17, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=18, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=56, i=18, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=19, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=58, i=19, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=20, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=51, i=20, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=21, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=35, i=21, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=22, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=42, i=22, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=23, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=54, i=23, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=24, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=63, i=24, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=25, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=25, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=61, i=25, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=24, b={64:0}, b={64:0}, i=26, size=24] [L20] RET return i; VAL [\old(size)=24, \result=26, b={64:0}, b={64:0}, i=26, size=24] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=26, i=24, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=25, mask={64:0}] [L27] EXPR b[i] VAL [i=25, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=25, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={64:0}, b={64:0}, i=0, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=0, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=34, i=0, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=1, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=67, i=1, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=2, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=33, i=2, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=3, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=43, i=3, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=4, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=55, i=4, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=5, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=46, i=5, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=6, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=41, i=6, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=7, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=60, i=7, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=8, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=47, i=8, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=9, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=49, i=9, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=10, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=44, i=10, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=11, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=65, i=11, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=12, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=62, i=12, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=13, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=66, i=13, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=14, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=45, i=14, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=15, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=48, i=15, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=16, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=57, i=16, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=17, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=36, i=17, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=18, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=56, i=18, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=19, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=58, i=19, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=20, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=51, i=20, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=21, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=35, i=21, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=22, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=42, i=22, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=23, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=54, i=23, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=24, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=63, i=24, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=25, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=61, i=25, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=26, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=26, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=52, i=26, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=25, b={64:0}, b={64:0}, i=27, size=25] [L20] RET return i; VAL [\old(size)=25, \result=27, b={64:0}, b={64:0}, i=27, size=25] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=27, i=25, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=26, mask={64:0}] [L27] EXPR b[i] VAL [i=26, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=26, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={64:0}, b={64:0}, i=0, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=0, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=34, i=0, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=1, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=67, i=1, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=2, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=33, i=2, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=3, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=43, i=3, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=4, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=55, i=4, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=5, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=46, i=5, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=6, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=41, i=6, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=7, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=60, i=7, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=8, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=47, i=8, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=9, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=49, i=9, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=10, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=44, i=10, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=11, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=65, i=11, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=12, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=62, i=12, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=13, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=66, i=13, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=14, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=45, i=14, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=15, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=48, i=15, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=16, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=57, i=16, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=17, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=36, i=17, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=18, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=56, i=18, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=19, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=58, i=19, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=20, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=51, i=20, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=21, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=35, i=21, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=22, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=42, i=22, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=23, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=54, i=23, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=24, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=63, i=24, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=25, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=61, i=25, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=26, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=52, i=26, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=27, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=27, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=38, i=27, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=26, b={64:0}, b={64:0}, i=28, size=26] [L20] RET return i; VAL [\old(size)=26, \result=28, b={64:0}, b={64:0}, i=28, size=26] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=28, i=26, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=27, mask={64:0}] [L27] EXPR b[i] VAL [i=27, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=27, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={64:0}, b={64:0}, i=0, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=0, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=34, i=0, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=1, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=67, i=1, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=2, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=33, i=2, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=3, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=43, i=3, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=4, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=55, i=4, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=5, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=46, i=5, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=6, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=41, i=6, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=7, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=60, i=7, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=8, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=47, i=8, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=9, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=49, i=9, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=10, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=44, i=10, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=11, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=65, i=11, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=12, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=62, i=12, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=13, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=66, i=13, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=14, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=45, i=14, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=15, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=48, i=15, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=16, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=57, i=16, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=17, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=36, i=17, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=18, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=56, i=18, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=19, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=58, i=19, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=20, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=51, i=20, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=21, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=35, i=21, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=22, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=42, i=22, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=23, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=54, i=23, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=24, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=63, i=24, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=25, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=61, i=25, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=26, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=52, i=26, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=27, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=38, i=27, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=28, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=28, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=39, i=28, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=27, b={64:0}, b={64:0}, i=29, size=27] [L20] RET return i; VAL [\old(size)=27, \result=29, b={64:0}, b={64:0}, i=29, size=27] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=29, i=27, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=28, mask={64:0}] [L27] EXPR b[i] VAL [i=28, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=28, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={64:0}, b={64:0}, i=0, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=0, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=34, i=0, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=1, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=67, i=1, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=2, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=33, i=2, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=3, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=43, i=3, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=4, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=55, i=4, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=5, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=46, i=5, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=6, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=41, i=6, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=7, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=60, i=7, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=8, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=47, i=8, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=9, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=49, i=9, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=10, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=44, i=10, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=11, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=65, i=11, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=12, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=62, i=12, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=13, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=66, i=13, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=14, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=45, i=14, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=15, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=48, i=15, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=16, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=57, i=16, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=17, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=36, i=17, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=18, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=56, i=18, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=19, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=58, i=19, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=20, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=51, i=20, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=21, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=35, i=21, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=22, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=42, i=22, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=23, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=54, i=23, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=24, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=63, i=24, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=25, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=61, i=25, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=26, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=52, i=26, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=27, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=38, i=27, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=28, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=39, i=28, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=29, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=29, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=40, i=29, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=28, b={64:0}, b={64:0}, i=30, size=28] [L20] RET return i; VAL [\old(size)=28, \result=30, b={64:0}, b={64:0}, i=30, size=28] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=30, i=28, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=29, mask={64:0}] [L27] EXPR b[i] VAL [i=29, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=29, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={64:0}, b={64:0}, i=0, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=0, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=34, i=0, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=1, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=67, i=1, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=2, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=33, i=2, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=3, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=43, i=3, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=4, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=55, i=4, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=5, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=46, i=5, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=6, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=41, i=6, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=7, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=60, i=7, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=8, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=47, i=8, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=9, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=49, i=9, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=10, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=44, i=10, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=11, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=65, i=11, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=12, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=62, i=12, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=13, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=66, i=13, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=14, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=45, i=14, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=15, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=48, i=15, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=16, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=57, i=16, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=17, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=36, i=17, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=18, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=56, i=18, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=19, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=58, i=19, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=20, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=51, i=20, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=21, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=35, i=21, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=22, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=42, i=22, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=23, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=54, i=23, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=24, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=63, i=24, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=25, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=61, i=25, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=26, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=52, i=26, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=27, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=38, i=27, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=28, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=39, i=28, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=29, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=40, i=29, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=30, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=30, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=37, i=30, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=29, b={64:0}, b={64:0}, i=31, size=29] [L20] RET return i; VAL [\old(size)=29, \result=31, b={64:0}, b={64:0}, i=31, size=29] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=31, i=29, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=30, mask={64:0}] [L27] EXPR b[i] VAL [i=30, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=30, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={64:0}, b={64:0}, i=0, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=0, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=34, i=0, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=1, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=67, i=1, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=2, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=33, i=2, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=3, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=43, i=3, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=4, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=55, i=4, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=5, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=46, i=5, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=6, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=41, i=6, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=7, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=60, i=7, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=8, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=47, i=8, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=9, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=49, i=9, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=10, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=44, i=10, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=11, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=65, i=11, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=12, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=62, i=12, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=13, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=66, i=13, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=14, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=45, i=14, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=15, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=48, i=15, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=16, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=57, i=16, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=17, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=36, i=17, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=18, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=56, i=18, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=19, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=58, i=19, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=20, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=51, i=20, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=21, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=35, i=21, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=22, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=42, i=22, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=23, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=54, i=23, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=24, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=63, i=24, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=25, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=61, i=25, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=26, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=52, i=26, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=27, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=38, i=27, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=28, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=39, i=28, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=29, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=40, i=29, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=30, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=37, i=30, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=31, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=31, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=53, i=31, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=30, b={64:0}, b={64:0}, i=32, size=30] [L20] RET return i; VAL [\old(size)=30, \result=32, b={64:0}, b={64:0}, i=32, size=30] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=32, i=30, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=31, mask={64:0}] [L27] b[i] VAL [i=31, mask={64:0}] [L27] CALL foo(mask, i) VAL [\old(size)=31, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={64:0}, b={64:0}, i=0, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=0, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=34, i=0, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=1, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=67, i=1, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=2, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=33, i=2, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=3, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=43, i=3, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=4, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=55, i=4, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=5, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=46, i=5, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=6, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=41, i=6, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=7, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=60, i=7, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=8, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=47, i=8, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=9, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=49, i=9, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=10, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=44, i=10, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=11, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=65, i=11, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=12, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=62, i=12, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=13, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=66, i=13, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=14, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=45, i=14, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=15, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=48, i=15, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=16, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=57, i=16, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=17, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=36, i=17, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=18, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=56, i=18, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=19, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=58, i=19, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=20, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=51, i=20, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=21, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=35, i=21, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=22, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=42, i=22, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=23, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=54, i=23, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=24, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=63, i=24, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=25, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=61, i=25, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=26, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=52, i=26, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=27, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=38, i=27, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=28, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=39, i=28, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=29, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=40, i=29, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=30, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=37, i=30, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=31, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=53, i=31, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=32, size=31] [L18] a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=32, size=31] [L18] FCALL b[i] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 46 locations, 6 error locations. UNSAFE Result, 521.2s OverallTime, 84 OverallIterations, 591 TraceHistogramMax, 125.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4255 SDtfs, 52416 SDslu, 62114 SDs, 0 SdLazy, 226244 SolverSat, 6414 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 56.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 124175 GetRequests, 115370 SyntacticMatches, 928 SemanticMatches, 7877 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 347684 ImplicationChecksByTransitivity, 131.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3900occurred in iteration=82, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.7s AutomataMinimizationTime, 83 MinimizatonAttempts, 1441 StatesRemovedByMinimization, 81 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 3.8s SsaConstructionTime, 76.8s SatisfiabilityAnalysisTime, 228.7s InterpolantComputationTime, 240251 NumberOfCodeBlocks, 223719 NumberOfCodeBlocksAsserted, 1325 NumberOfCheckSat, 236347 ConstructedInterpolants, 33254 QuantifiedInterpolants, 1357010274 SizeOfPredicates, 292 NumberOfNonLiveVariables, 229001 ConjunctsInSsa, 3264 ConjunctsInUnsatCore, 161 InterpolantComputations, 6 PerfectInterpolantSequences, 36439052/36934829 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf_AutomizerC.xml/Csv-Benchmark-0-2018-04-12_15-15-24-109.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-04-12_15-15-24-109.csv Received shutdown request...