java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv --cacsl2boogietranslator.bitprecise.bitfields false -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf -i ../../../trunk/examples/svcomp/array-memsafety/lis-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-408c70d-m [2018-04-12 19:59:57,116 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-04-12 19:59:57,117 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-04-12 19:59:57,129 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2018-04-12 19:59:57,152 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf [2018-04-12 19:59:57,162 INFO L110 SettingsManager]: Loading preferences was successful [2018-04-12 19:59:57,162 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-04-12 19:59:57,163 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-04-12 19:59:57,164 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-04-12 19:59:57,164 INFO L133 SettingsManager]: * Use SBE=true [2018-04-12 19:59:57,164 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-04-12 19:59:57,164 INFO L133 SettingsManager]: * sizeof long=4 [2018-04-12 19:59:57,164 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-04-12 19:59:57,164 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-04-12 19:59:57,165 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-04-12 19:59:57,165 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-04-12 19:59:57,165 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-04-12 19:59:57,165 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-04-12 19:59:57,165 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-04-12 19:59:57,165 INFO L133 SettingsManager]: * sizeof long double=12 [2018-04-12 19:59:57,165 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-04-12 19:59:57,166 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-04-12 19:59:57,166 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-04-12 19:59:57,166 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-04-12 19:59:57,166 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-12 19:59:57,166 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-04-12 19:59:57,166 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_TreeInterpolation Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Bitprecise bitfields -> false [2018-04-12 19:59:57,196 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-04-12 19:59:57,206 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully (re)initialized [2018-04-12 19:59:57,209 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-04-12 19:59:57,211 INFO L271 PluginConnector]: Initializing CDTParser... [2018-04-12 19:59:57,211 INFO L276 PluginConnector]: CDTParser initialized [2018-04-12 19:59:57,212 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,485 INFO L225 CDTParser]: Created temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAG8bba06d72 [2018-04-12 19:59:57,615 INFO L287 CDTParser]: IsIndexed: true [2018-04-12 19:59:57,615 INFO L288 CDTParser]: Found 1 translation units. [2018-04-12 19:59:57,616 INFO L168 CDTParser]: Scanning lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,624 INFO L210 ultiparseSymbolTable]: Include resolver: [2018-04-12 19:59:57,624 INFO L215 ultiparseSymbolTable]: [2018-04-12 19:59:57,624 INFO L218 ultiparseSymbolTable]: Function table: [2018-04-12 19:59:57,624 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_32 ('__bswap_32') in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,624 INFO L221 ultiparseSymbolTable]: Function definition of null ('main') in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,624 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_64 ('__bswap_64') in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,624 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis ('lis') in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,624 INFO L227 ultiparseSymbolTable]: Global variable table: [2018-04-12 19:59:57,625 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_char in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,625 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__ulong in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,625 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____u_long in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,625 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__blkcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,625 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____int16_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,625 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_rwlockattr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,625 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__daddr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,625 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_int32_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,625 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__clock_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,626 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____pthread_list_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,626 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_barrierattr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,626 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____ino64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,626 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_key_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,626 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__blksize_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,626 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_long in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,626 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____off_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,626 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____caddr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,626 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____uint32_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____ino_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__sigset_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____sigset_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____clockid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__clockid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_spinlock_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____suseconds_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____rlim_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__quad_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__fsblkcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_cond_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__div_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_int16_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____int32_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__fd_mask in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__key_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_int8_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__wchar_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lldiv_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__uid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__int16_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____u_char in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____gid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____off64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fd_mask in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____quad_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____timer_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____id_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_barrier_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____u_quad_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____syscall_ulong_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsblkcnt64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____pid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_int in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_mutexattr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__register_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____int8_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__off_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__ldiv_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__gid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsword_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____uint64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____blkcnt64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsfilcnt64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__int32_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_attr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__timer_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____ssize_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____sig_atomic_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____socklen_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____nlink_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____mode_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____uid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__size_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__nlink_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__fsfilcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____intptr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__id_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__ssize_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_once_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__uint in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_short in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__caddr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____clock_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____daddr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__mode_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__time_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____uint8_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__fsid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__dev_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____key_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____blkcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____useconds_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__suseconds_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____u_short in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____u_int in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____loff_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__fd_set in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_mutex_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_rwlock_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____syscall_slong_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____dev_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsblkcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____blksize_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____qaddr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__int8_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____time_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__ino_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__ushort in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____int64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_condattr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____rlim64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____WAIT_STATUS in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_quad_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__int64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__loff_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_int64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____uint16_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsfilcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:57,648 INFO L330 CDTParser]: Deleted temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAG8bba06d72 [2018-04-12 19:59:57,650 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-04-12 19:59:57,652 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-04-12 19:59:57,652 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-04-12 19:59:57,653 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-04-12 19:59:57,658 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-04-12 19:59:57,659 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.04 07:59:57" (1/1) ... [2018-04-12 19:59:57,661 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@430cde96 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 07:59:57, skipping insertion in model container [2018-04-12 19:59:57,661 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.04 07:59:57" (1/1) ... [2018-04-12 19:59:57,674 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-12 19:59:57,696 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-12 19:59:57,839 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-12 19:59:57,879 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-12 19:59:57,885 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-12 19:59:57,922 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 07:59:57 WrapperNode [2018-04-12 19:59:57,922 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-04-12 19:59:57,923 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-04-12 19:59:57,923 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-04-12 19:59:57,923 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-04-12 19:59:57,934 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 07:59:57" (1/1) ... [2018-04-12 19:59:57,934 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 07:59:57" (1/1) ... [2018-04-12 19:59:57,946 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 07:59:57" (1/1) ... [2018-04-12 19:59:57,946 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 07:59:57" (1/1) ... [2018-04-12 19:59:57,953 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 07:59:57" (1/1) ... [2018-04-12 19:59:57,958 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 07:59:57" (1/1) ... [2018-04-12 19:59:57,960 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 07:59:57" (1/1) ... [2018-04-12 19:59:57,963 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-04-12 19:59:57,964 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-04-12 19:59:57,964 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-04-12 19:59:57,964 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-04-12 19:59:57,965 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 07:59:57" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-12 19:59:58,074 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-04-12 19:59:58,074 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-04-12 19:59:58,074 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-12 19:59:58,074 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-12 19:59:58,074 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis [2018-04-12 19:59:58,074 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-04-12 19:59:58,074 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-12 19:59:58,074 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-12 19:59:58,074 INFO L128 BoogieDeclarations]: Found specification of procedure __ctype_get_mb_cur_max [2018-04-12 19:59:58,074 INFO L128 BoogieDeclarations]: Found specification of procedure atof [2018-04-12 19:59:58,075 INFO L128 BoogieDeclarations]: Found specification of procedure atoi [2018-04-12 19:59:58,075 INFO L128 BoogieDeclarations]: Found specification of procedure atol [2018-04-12 19:59:58,075 INFO L128 BoogieDeclarations]: Found specification of procedure atoll [2018-04-12 19:59:58,075 INFO L128 BoogieDeclarations]: Found specification of procedure strtod [2018-04-12 19:59:58,075 INFO L128 BoogieDeclarations]: Found specification of procedure strtof [2018-04-12 19:59:58,075 INFO L128 BoogieDeclarations]: Found specification of procedure strtold [2018-04-12 19:59:58,075 INFO L128 BoogieDeclarations]: Found specification of procedure strtol [2018-04-12 19:59:58,075 INFO L128 BoogieDeclarations]: Found specification of procedure strtoul [2018-04-12 19:59:58,075 INFO L128 BoogieDeclarations]: Found specification of procedure strtoq [2018-04-12 19:59:58,075 INFO L128 BoogieDeclarations]: Found specification of procedure strtouq [2018-04-12 19:59:58,075 INFO L128 BoogieDeclarations]: Found specification of procedure strtoll [2018-04-12 19:59:58,075 INFO L128 BoogieDeclarations]: Found specification of procedure strtoull [2018-04-12 19:59:58,075 INFO L128 BoogieDeclarations]: Found specification of procedure l64a [2018-04-12 19:59:58,075 INFO L128 BoogieDeclarations]: Found specification of procedure a64l [2018-04-12 19:59:58,075 INFO L128 BoogieDeclarations]: Found specification of procedure select [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure pselect [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_major [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_minor [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_makedev [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure random [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure srandom [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure initstate [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure setstate [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure random_r [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure srandom_r [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure initstate_r [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure setstate_r [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure rand [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure srand [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure rand_r [2018-04-12 19:59:58,076 INFO L128 BoogieDeclarations]: Found specification of procedure drand48 [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure erand48 [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48 [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48 [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48 [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48 [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure srand48 [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure seed48 [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48 [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure drand48_r [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure erand48_r [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48_r [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48_r [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48_r [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48_r [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure srand48_r [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure seed48_r [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48_r [2018-04-12 19:59:58,077 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure realloc [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure cfree [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure alloca [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure valloc [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure posix_memalign [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure abort [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure atexit [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure on_exit [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure exit [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure _Exit [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure getenv [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure putenv [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure setenv [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure unsetenv [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure clearenv [2018-04-12 19:59:58,078 INFO L128 BoogieDeclarations]: Found specification of procedure mktemp [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemp [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemps [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure mkdtemp [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure system [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure realpath [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure bsearch [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure qsort [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure abs [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure labs [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure llabs [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure div [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure ldiv [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure lldiv [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure gcvt [2018-04-12 19:59:58,079 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure qgcvt [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt_r [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt_r [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt_r [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt_r [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure mblen [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure mbtowc [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure wctomb [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure mbstowcs [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure wcstombs [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure rpmatch [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure getsubopt [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure getloadavg [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-04-12 19:59:58,080 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-04-12 19:59:58,081 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-04-12 19:59:58,081 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-04-12 19:59:58,081 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-04-12 19:59:58,081 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-04-12 19:59:58,081 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-04-12 19:59:58,081 INFO L128 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-04-12 19:59:58,412 INFO L259 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-04-12 19:59:58,413 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.04 07:59:58 BoogieIcfgContainer [2018-04-12 19:59:58,413 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-04-12 19:59:58,413 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-04-12 19:59:58,413 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-04-12 19:59:58,415 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-04-12 19:59:58,415 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 12.04 07:59:57" (1/3) ... [2018-04-12 19:59:58,416 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@43fdeaa3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.04 07:59:58, skipping insertion in model container [2018-04-12 19:59:58,416 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 07:59:57" (2/3) ... [2018-04-12 19:59:58,416 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@43fdeaa3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.04 07:59:58, skipping insertion in model container [2018-04-12 19:59:58,416 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.04 07:59:58" (3/3) ... [2018-04-12 19:59:58,417 INFO L107 eAbstractionObserver]: Analyzing ICFG lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 19:59:58,423 INFO L131 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_TreeInterpolation Determinization: PREDICATE_ABSTRACTION [2018-04-12 19:59:58,427 INFO L143 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2018-04-12 19:59:58,451 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-04-12 19:59:58,451 INFO L369 AbstractCegarLoop]: Interprodecural is true [2018-04-12 19:59:58,451 INFO L370 AbstractCegarLoop]: Hoare is false [2018-04-12 19:59:58,451 INFO L371 AbstractCegarLoop]: Compute interpolants for Craig_TreeInterpolation [2018-04-12 19:59:58,451 INFO L372 AbstractCegarLoop]: Backedges is CANONICAL [2018-04-12 19:59:58,452 INFO L373 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-04-12 19:59:58,452 INFO L374 AbstractCegarLoop]: Difference is false [2018-04-12 19:59:58,452 INFO L375 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-04-12 19:59:58,452 INFO L380 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-04-12 19:59:58,452 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-04-12 19:59:58,462 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states. [2018-04-12 19:59:58,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-04-12 19:59:58,468 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 19:59:58,469 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 19:59:58,469 INFO L408 AbstractCegarLoop]: === Iteration 1 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 19:59:58,472 INFO L82 PathProgramCache]: Analyzing trace with hash 903315809, now seen corresponding path program 1 times [2018-04-12 19:59:58,503 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 19:59:58,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 19:59:58,545 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 19:59:58,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:58,613 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 19:59:58,613 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-12 19:59:58,613 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 19:59:58,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:58,614 INFO L182 omatonBuilderFactory]: Interpolants [87#true, 88#false, 89#(= 1 (select |#valid| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base|)), 90#(= 1 (select |#valid| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base))] [2018-04-12 19:59:58,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:58,615 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-12 19:59:58,624 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-12 19:59:58,625 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-12 19:59:58,626 INFO L87 Difference]: Start difference. First operand 84 states. Second operand 4 states. [2018-04-12 19:59:58,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 19:59:58,722 INFO L93 Difference]: Finished difference Result 77 states and 84 transitions. [2018-04-12 19:59:58,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-12 19:59:58,723 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 18 [2018-04-12 19:59:58,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 19:59:58,729 INFO L225 Difference]: With dead ends: 77 [2018-04-12 19:59:58,730 INFO L226 Difference]: Without dead ends: 74 [2018-04-12 19:59:58,731 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-12 19:59:58,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-04-12 19:59:58,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 74. [2018-04-12 19:59:58,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-04-12 19:59:58,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 81 transitions. [2018-04-12 19:59:58,754 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 81 transitions. Word has length 18 [2018-04-12 19:59:58,754 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 19:59:58,754 INFO L459 AbstractCegarLoop]: Abstraction has 74 states and 81 transitions. [2018-04-12 19:59:58,754 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-12 19:59:58,754 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 81 transitions. [2018-04-12 19:59:58,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-04-12 19:59:58,755 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 19:59:58,755 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 19:59:58,755 INFO L408 AbstractCegarLoop]: === Iteration 2 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 19:59:58,755 INFO L82 PathProgramCache]: Analyzing trace with hash 903315810, now seen corresponding path program 1 times [2018-04-12 19:59:58,756 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 19:59:58,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 19:59:58,773 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 19:59:58,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:58,826 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 19:59:58,826 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-12 19:59:58,826 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 19:59:58,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:58,827 INFO L182 omatonBuilderFactory]: Interpolants [244#true, 245#false, 246#(and (= 0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.offset|) (= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base|))), 247#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base))), 248#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base))), 249#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) 4) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base)))] [2018-04-12 19:59:58,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:58,828 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-12 19:59:58,829 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-12 19:59:58,829 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-04-12 19:59:58,829 INFO L87 Difference]: Start difference. First operand 74 states and 81 transitions. Second operand 6 states. [2018-04-12 19:59:59,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 19:59:59,030 INFO L93 Difference]: Finished difference Result 96 states and 106 transitions. [2018-04-12 19:59:59,030 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-12 19:59:59,030 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 18 [2018-04-12 19:59:59,031 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 19:59:59,034 INFO L225 Difference]: With dead ends: 96 [2018-04-12 19:59:59,034 INFO L226 Difference]: Without dead ends: 96 [2018-04-12 19:59:59,034 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-04-12 19:59:59,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-04-12 19:59:59,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 82. [2018-04-12 19:59:59,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-04-12 19:59:59,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 92 transitions. [2018-04-12 19:59:59,041 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 92 transitions. Word has length 18 [2018-04-12 19:59:59,041 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 19:59:59,041 INFO L459 AbstractCegarLoop]: Abstraction has 82 states and 92 transitions. [2018-04-12 19:59:59,041 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-12 19:59:59,041 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 92 transitions. [2018-04-12 19:59:59,042 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-04-12 19:59:59,042 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 19:59:59,042 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 19:59:59,042 INFO L408 AbstractCegarLoop]: === Iteration 3 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 19:59:59,042 INFO L82 PathProgramCache]: Analyzing trace with hash -2061980982, now seen corresponding path program 1 times [2018-04-12 19:59:59,043 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 19:59:59,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 19:59:59,053 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 19:59:59,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,081 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 19:59:59,082 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-12 19:59:59,082 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 19:59:59,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,082 INFO L182 omatonBuilderFactory]: Interpolants [434#true, 435#false, 436#(= 1 (select |#valid| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base|)), 437#(= 1 (select |#valid| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~prev~0.base))] [2018-04-12 19:59:59,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,083 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-12 19:59:59,083 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-12 19:59:59,083 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-12 19:59:59,083 INFO L87 Difference]: Start difference. First operand 82 states and 92 transitions. Second operand 4 states. [2018-04-12 19:59:59,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 19:59:59,135 INFO L93 Difference]: Finished difference Result 80 states and 90 transitions. [2018-04-12 19:59:59,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-12 19:59:59,135 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 19 [2018-04-12 19:59:59,136 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 19:59:59,136 INFO L225 Difference]: With dead ends: 80 [2018-04-12 19:59:59,136 INFO L226 Difference]: Without dead ends: 80 [2018-04-12 19:59:59,137 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-12 19:59:59,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-04-12 19:59:59,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 80. [2018-04-12 19:59:59,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-04-12 19:59:59,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 90 transitions. [2018-04-12 19:59:59,141 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 90 transitions. Word has length 19 [2018-04-12 19:59:59,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 19:59:59,141 INFO L459 AbstractCegarLoop]: Abstraction has 80 states and 90 transitions. [2018-04-12 19:59:59,141 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-12 19:59:59,141 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 90 transitions. [2018-04-12 19:59:59,142 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-04-12 19:59:59,142 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 19:59:59,142 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 19:59:59,142 INFO L408 AbstractCegarLoop]: === Iteration 4 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 19:59:59,142 INFO L82 PathProgramCache]: Analyzing trace with hash -2061980981, now seen corresponding path program 1 times [2018-04-12 19:59:59,143 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 19:59:59,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 19:59:59,153 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 19:59:59,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,212 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 19:59:59,212 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-04-12 19:59:59,212 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 19:59:59,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,212 INFO L182 omatonBuilderFactory]: Interpolants [600#true, 601#false, 602#(= 0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.offset|), 603#(= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0), 604#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base|)) (= 0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.offset|)), 605#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~prev~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~prev~0.base))), 606#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~prev~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) 4) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~prev~0.base))), 607#(and (<= 0 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~prev~0.offset 0) (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) 4) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~prev~0.base)))] [2018-04-12 19:59:59,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,213 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-12 19:59:59,213 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-12 19:59:59,213 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-04-12 19:59:59,213 INFO L87 Difference]: Start difference. First operand 80 states and 90 transitions. Second operand 8 states. [2018-04-12 19:59:59,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 19:59:59,370 INFO L93 Difference]: Finished difference Result 97 states and 110 transitions. [2018-04-12 19:59:59,371 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-12 19:59:59,371 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 19 [2018-04-12 19:59:59,371 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 19:59:59,371 INFO L225 Difference]: With dead ends: 97 [2018-04-12 19:59:59,371 INFO L226 Difference]: Without dead ends: 97 [2018-04-12 19:59:59,372 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=64, Invalid=118, Unknown=0, NotChecked=0, Total=182 [2018-04-12 19:59:59,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-04-12 19:59:59,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 78. [2018-04-12 19:59:59,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-04-12 19:59:59,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 88 transitions. [2018-04-12 19:59:59,375 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 88 transitions. Word has length 19 [2018-04-12 19:59:59,375 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 19:59:59,375 INFO L459 AbstractCegarLoop]: Abstraction has 78 states and 88 transitions. [2018-04-12 19:59:59,376 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-12 19:59:59,376 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 88 transitions. [2018-04-12 19:59:59,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-04-12 19:59:59,376 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 19:59:59,376 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 19:59:59,376 INFO L408 AbstractCegarLoop]: === Iteration 5 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 19:59:59,376 INFO L82 PathProgramCache]: Analyzing trace with hash 1233215310, now seen corresponding path program 1 times [2018-04-12 19:59:59,377 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 19:59:59,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 19:59:59,385 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 19:59:59,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,415 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 19:59:59,415 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-04-12 19:59:59,415 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 19:59:59,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,416 INFO L182 omatonBuilderFactory]: Interpolants [800#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0 0) (<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 0)), 795#true, 796#false, 797#(<= main_~array_size~0 1), 798#(<= |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N| 1), 799#(<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N 1)] [2018-04-12 19:59:59,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,416 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-12 19:59:59,416 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-12 19:59:59,417 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-04-12 19:59:59,417 INFO L87 Difference]: Start difference. First operand 78 states and 88 transitions. Second operand 6 states. [2018-04-12 19:59:59,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 19:59:59,525 INFO L93 Difference]: Finished difference Result 128 states and 144 transitions. [2018-04-12 19:59:59,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-12 19:59:59,525 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 23 [2018-04-12 19:59:59,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 19:59:59,526 INFO L225 Difference]: With dead ends: 128 [2018-04-12 19:59:59,526 INFO L226 Difference]: Without dead ends: 128 [2018-04-12 19:59:59,527 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-04-12 19:59:59,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-04-12 19:59:59,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 120. [2018-04-12 19:59:59,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-04-12 19:59:59,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 140 transitions. [2018-04-12 19:59:59,533 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 140 transitions. Word has length 23 [2018-04-12 19:59:59,533 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 19:59:59,533 INFO L459 AbstractCegarLoop]: Abstraction has 120 states and 140 transitions. [2018-04-12 19:59:59,533 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-12 19:59:59,533 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 140 transitions. [2018-04-12 19:59:59,534 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-04-12 19:59:59,534 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 19:59:59,534 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 19:59:59,534 INFO L408 AbstractCegarLoop]: === Iteration 6 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 19:59:59,534 INFO L82 PathProgramCache]: Analyzing trace with hash -1613164609, now seen corresponding path program 1 times [2018-04-12 19:59:59,535 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 19:59:59,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 19:59:59,544 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 19:59:59,615 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,615 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-12 19:59:59,616 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-04-12 19:59:59,616 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 19:59:59,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,616 INFO L182 omatonBuilderFactory]: Interpolants [1056#(<= |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N| 1), 1057#(<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N 1), 1058#(and (<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N 1) (= 0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.offset|)), 1059#(and (<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N 1) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0)), 1060#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (<= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 4))), 1061#(and (<= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0)), 1053#true, 1054#false, 1055#(<= main_~array_size~0 1)] [2018-04-12 19:59:59,616 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,617 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-12 19:59:59,617 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-12 19:59:59,617 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-04-12 19:59:59,617 INFO L87 Difference]: Start difference. First operand 120 states and 140 transitions. Second operand 9 states. [2018-04-12 19:59:59,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 19:59:59,757 INFO L93 Difference]: Finished difference Result 118 states and 130 transitions. [2018-04-12 19:59:59,757 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-12 19:59:59,757 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 23 [2018-04-12 19:59:59,758 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 19:59:59,758 INFO L225 Difference]: With dead ends: 118 [2018-04-12 19:59:59,758 INFO L226 Difference]: Without dead ends: 118 [2018-04-12 19:59:59,758 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=67, Invalid=143, Unknown=0, NotChecked=0, Total=210 [2018-04-12 19:59:59,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-04-12 19:59:59,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 113. [2018-04-12 19:59:59,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-04-12 19:59:59,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 126 transitions. [2018-04-12 19:59:59,765 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 126 transitions. Word has length 23 [2018-04-12 19:59:59,765 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 19:59:59,765 INFO L459 AbstractCegarLoop]: Abstraction has 113 states and 126 transitions. [2018-04-12 19:59:59,765 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-12 19:59:59,765 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 126 transitions. [2018-04-12 19:59:59,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-04-12 19:59:59,765 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 19:59:59,765 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 19:59:59,766 INFO L408 AbstractCegarLoop]: === Iteration 7 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 19:59:59,766 INFO L82 PathProgramCache]: Analyzing trace with hash -355132592, now seen corresponding path program 1 times [2018-04-12 19:59:59,766 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 19:59:59,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 19:59:59,773 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 19:59:59,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,797 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 19:59:59,797 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-04-12 19:59:59,797 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 19:59:59,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,797 INFO L182 omatonBuilderFactory]: Interpolants [1305#true, 1306#false, 1307#(<= 1 main_~array_size~0), 1308#(<= 1 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N|), 1309#(<= 1 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N), 1310#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 0) (<= 1 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N))] [2018-04-12 19:59:59,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,798 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-12 19:59:59,798 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-12 19:59:59,798 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-04-12 19:59:59,798 INFO L87 Difference]: Start difference. First operand 113 states and 126 transitions. Second operand 6 states. [2018-04-12 19:59:59,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 19:59:59,861 INFO L93 Difference]: Finished difference Result 117 states and 126 transitions. [2018-04-12 19:59:59,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-12 19:59:59,861 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 23 [2018-04-12 19:59:59,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 19:59:59,861 INFO L225 Difference]: With dead ends: 117 [2018-04-12 19:59:59,862 INFO L226 Difference]: Without dead ends: 117 [2018-04-12 19:59:59,862 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-04-12 19:59:59,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-04-12 19:59:59,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 113. [2018-04-12 19:59:59,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-04-12 19:59:59,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 122 transitions. [2018-04-12 19:59:59,865 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 122 transitions. Word has length 23 [2018-04-12 19:59:59,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 19:59:59,865 INFO L459 AbstractCegarLoop]: Abstraction has 113 states and 122 transitions. [2018-04-12 19:59:59,865 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-12 19:59:59,865 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 122 transitions. [2018-04-12 19:59:59,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-04-12 19:59:59,865 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 19:59:59,865 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 19:59:59,866 INFO L408 AbstractCegarLoop]: === Iteration 8 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 19:59:59,866 INFO L82 PathProgramCache]: Analyzing trace with hash 1093454785, now seen corresponding path program 1 times [2018-04-12 19:59:59,866 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 19:59:59,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 19:59:59,876 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 19:59:59,965 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,965 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-12 19:59:59,966 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-04-12 19:59:59,966 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 19:59:59,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,966 INFO L182 omatonBuilderFactory]: Interpolants [1545#true, 1546#false, 1547#(and (= 0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.offset|) (= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base|))), 1548#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base))), 1549#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (<= 0 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset)) (= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base))), 1550#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (<= 4 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset)) (= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base))), 1551#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (<= 4 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset)) (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) 4) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base)))] [2018-04-12 19:59:59,966 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 19:59:59,966 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-04-12 19:59:59,967 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-04-12 19:59:59,967 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-04-12 19:59:59,967 INFO L87 Difference]: Start difference. First operand 113 states and 122 transitions. Second operand 7 states. [2018-04-12 20:00:00,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 20:00:00,096 INFO L93 Difference]: Finished difference Result 112 states and 121 transitions. [2018-04-12 20:00:00,096 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-12 20:00:00,096 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 23 [2018-04-12 20:00:00,096 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 20:00:00,097 INFO L225 Difference]: With dead ends: 112 [2018-04-12 20:00:00,097 INFO L226 Difference]: Without dead ends: 112 [2018-04-12 20:00:00,098 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=42, Invalid=68, Unknown=0, NotChecked=0, Total=110 [2018-04-12 20:00:00,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-04-12 20:00:00,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 104. [2018-04-12 20:00:00,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104 states. [2018-04-12 20:00:00,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 112 transitions. [2018-04-12 20:00:00,101 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 112 transitions. Word has length 23 [2018-04-12 20:00:00,101 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 20:00:00,101 INFO L459 AbstractCegarLoop]: Abstraction has 104 states and 112 transitions. [2018-04-12 20:00:00,101 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-04-12 20:00:00,101 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 112 transitions. [2018-04-12 20:00:00,101 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-04-12 20:00:00,101 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 20:00:00,102 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 20:00:00,102 INFO L408 AbstractCegarLoop]: === Iteration 9 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 20:00:00,102 INFO L82 PathProgramCache]: Analyzing trace with hash -200886193, now seen corresponding path program 1 times [2018-04-12 20:00:00,102 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 20:00:00,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 20:00:00,111 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 20:00:00,131 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:00,131 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-12 20:00:00,131 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-04-12 20:00:00,131 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 20:00:00,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:00,132 INFO L182 omatonBuilderFactory]: Interpolants [1776#true, 1777#false, 1778#(= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 0), 1779#(<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1), 1780#(<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N 1), 1781#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0 0) (<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 0))] [2018-04-12 20:00:00,132 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:00,132 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-12 20:00:00,132 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-12 20:00:00,132 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-04-12 20:00:00,132 INFO L87 Difference]: Start difference. First operand 104 states and 112 transitions. Second operand 6 states. [2018-04-12 20:00:00,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 20:00:00,201 INFO L93 Difference]: Finished difference Result 185 states and 206 transitions. [2018-04-12 20:00:00,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-12 20:00:00,201 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2018-04-12 20:00:00,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 20:00:00,203 INFO L225 Difference]: With dead ends: 185 [2018-04-12 20:00:00,203 INFO L226 Difference]: Without dead ends: 185 [2018-04-12 20:00:00,203 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-04-12 20:00:00,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 185 states. [2018-04-12 20:00:00,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 185 to 115. [2018-04-12 20:00:00,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-04-12 20:00:00,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 125 transitions. [2018-04-12 20:00:00,208 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 125 transitions. Word has length 28 [2018-04-12 20:00:00,208 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 20:00:00,208 INFO L459 AbstractCegarLoop]: Abstraction has 115 states and 125 transitions. [2018-04-12 20:00:00,208 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-12 20:00:00,208 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 125 transitions. [2018-04-12 20:00:00,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-04-12 20:00:00,209 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 20:00:00,209 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 20:00:00,209 INFO L408 AbstractCegarLoop]: === Iteration 10 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 20:00:00,210 INFO L82 PathProgramCache]: Analyzing trace with hash -392535376, now seen corresponding path program 2 times [2018-04-12 20:00:00,210 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 20:00:00,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 20:00:00,221 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 20:00:00,323 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-04-12 20:00:00,323 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 20:00:00,323 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-04-12 20:00:00,324 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 20:00:00,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:00,324 INFO L182 omatonBuilderFactory]: Interpolants [2096#(or (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base) (= 1 (select |#valid| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base|)), 2097#(or (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base) (= 1 (select |#valid| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~prev~0.base __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)), 2098#(or (= 1 (select |#valid| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~prev~0.base __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)), 2088#true, 2089#false, 2090#(= 1 (select |#valid| |main_#t~malloc17.base|)), 2091#(= 1 (select |#valid| main_~numbers~0.base)), 2092#(= 1 (select |#valid| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~a.base|)), 2093#(= 1 (select |#valid| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)), 2094#(or (= 1 (select |#valid| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base|)), 2095#(or (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base) (= 1 (select |#valid| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)))] [2018-04-12 20:00:00,324 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-04-12 20:00:00,324 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-12 20:00:00,324 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-12 20:00:00,324 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2018-04-12 20:00:00,324 INFO L87 Difference]: Start difference. First operand 115 states and 125 transitions. Second operand 11 states. [2018-04-12 20:00:00,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 20:00:00,391 INFO L93 Difference]: Finished difference Result 113 states and 123 transitions. [2018-04-12 20:00:00,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-12 20:00:00,392 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 33 [2018-04-12 20:00:00,392 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 20:00:00,392 INFO L225 Difference]: With dead ends: 113 [2018-04-12 20:00:00,392 INFO L226 Difference]: Without dead ends: 113 [2018-04-12 20:00:00,392 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-04-12 20:00:00,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-04-12 20:00:00,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-04-12 20:00:00,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-04-12 20:00:00,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 123 transitions. [2018-04-12 20:00:00,394 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 123 transitions. Word has length 33 [2018-04-12 20:00:00,395 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 20:00:00,395 INFO L459 AbstractCegarLoop]: Abstraction has 113 states and 123 transitions. [2018-04-12 20:00:00,395 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-12 20:00:00,395 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 123 transitions. [2018-04-12 20:00:00,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-04-12 20:00:00,395 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 20:00:00,395 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 20:00:00,396 INFO L408 AbstractCegarLoop]: === Iteration 11 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 20:00:00,396 INFO L82 PathProgramCache]: Analyzing trace with hash -392535375, now seen corresponding path program 1 times [2018-04-12 20:00:00,396 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 20:00:00,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 20:00:00,404 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 20:00:00,597 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:00,597 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-12 20:00:00,597 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-04-12 20:00:00,597 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 20:00:00,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:00,598 INFO L182 omatonBuilderFactory]: Interpolants [2336#(and (<= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 2337#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (<= 0 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0) (<= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)))), 2338#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) 4) (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base))) (<= 4 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 2339#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (<= 8 (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N))) (<= 8 (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base))) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 2340#(and (<= 2 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (<= 8 (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 2341#(and (<= 2 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (<= 8 (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 2342#(and (<= 8 (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 2329#true, 2330#false, 2331#(and (= (* 4 main_~array_size~0) (select |#length| |main_#t~malloc17.base|)) (= 0 |main_#t~malloc17.offset|)), 2332#(and (= 0 main_~numbers~0.offset) (= (* 4 main_~array_size~0) (select |#length| main_~numbers~0.base))), 2333#(and (<= (* 4 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N|) (select |#length| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~a.base|)) (= 0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~a.offset|)), 2334#(and (<= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 2335#(and (= 0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.offset|) (<= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0))] [2018-04-12 20:00:00,598 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:00,598 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-04-12 20:00:00,598 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-04-12 20:00:00,598 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2018-04-12 20:00:00,598 INFO L87 Difference]: Start difference. First operand 113 states and 123 transitions. Second operand 14 states. [2018-04-12 20:00:00,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 20:00:00,952 INFO L93 Difference]: Finished difference Result 158 states and 175 transitions. [2018-04-12 20:00:00,952 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-04-12 20:00:00,952 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 33 [2018-04-12 20:00:00,953 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 20:00:00,953 INFO L225 Difference]: With dead ends: 158 [2018-04-12 20:00:00,953 INFO L226 Difference]: Without dead ends: 158 [2018-04-12 20:00:00,954 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 66 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=119, Invalid=433, Unknown=0, NotChecked=0, Total=552 [2018-04-12 20:00:00,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2018-04-12 20:00:00,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 130. [2018-04-12 20:00:00,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-04-12 20:00:00,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 146 transitions. [2018-04-12 20:00:00,956 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 146 transitions. Word has length 33 [2018-04-12 20:00:00,956 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 20:00:00,956 INFO L459 AbstractCegarLoop]: Abstraction has 130 states and 146 transitions. [2018-04-12 20:00:00,956 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-04-12 20:00:00,956 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 146 transitions. [2018-04-12 20:00:00,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-04-12 20:00:00,959 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 20:00:00,959 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 20:00:00,959 INFO L408 AbstractCegarLoop]: === Iteration 12 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 20:00:00,959 INFO L82 PathProgramCache]: Analyzing trace with hash 716305274, now seen corresponding path program 1 times [2018-04-12 20:00:00,960 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 20:00:00,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 20:00:00,966 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 20:00:01,019 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 20:00:01,019 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 20:00:01,019 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-04-12 20:00:01,019 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 20:00:01,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:01,020 INFO L182 omatonBuilderFactory]: Interpolants [2656#(= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0), 2657#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 2658#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0 0) (<= (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0 1) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 2659#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0 0) (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 8) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 2651#true, 2652#false, 2653#(= 0 |main_#t~malloc17.offset|), 2654#(= 0 main_~numbers~0.offset), 2655#(= 0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~a.offset|)] [2018-04-12 20:00:01,020 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 20:00:01,020 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-12 20:00:01,020 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-12 20:00:01,020 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2018-04-12 20:00:01,020 INFO L87 Difference]: Start difference. First operand 130 states and 146 transitions. Second operand 9 states. [2018-04-12 20:00:01,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 20:00:01,115 INFO L93 Difference]: Finished difference Result 185 states and 213 transitions. [2018-04-12 20:00:01,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-12 20:00:01,116 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 34 [2018-04-12 20:00:01,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 20:00:01,117 INFO L225 Difference]: With dead ends: 185 [2018-04-12 20:00:01,117 INFO L226 Difference]: Without dead ends: 185 [2018-04-12 20:00:01,117 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=52, Invalid=130, Unknown=0, NotChecked=0, Total=182 [2018-04-12 20:00:01,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 185 states. [2018-04-12 20:00:01,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 185 to 138. [2018-04-12 20:00:01,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-04-12 20:00:01,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 157 transitions. [2018-04-12 20:00:01,121 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 157 transitions. Word has length 34 [2018-04-12 20:00:01,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 20:00:01,121 INFO L459 AbstractCegarLoop]: Abstraction has 138 states and 157 transitions. [2018-04-12 20:00:01,121 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-12 20:00:01,121 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 157 transitions. [2018-04-12 20:00:01,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-12 20:00:01,122 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 20:00:01,122 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 20:00:01,122 INFO L408 AbstractCegarLoop]: === Iteration 13 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 20:00:01,123 INFO L82 PathProgramCache]: Analyzing trace with hash -1431404189, now seen corresponding path program 1 times [2018-04-12 20:00:01,123 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 20:00:01,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 20:00:01,133 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 20:00:01,167 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 20:00:01,167 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 20:00:01,167 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-12 20:00:01,167 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 20:00:01,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:01,168 INFO L182 omatonBuilderFactory]: Interpolants [2993#true, 2994#false, 2995#(= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1), 2996#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1))] [2018-04-12 20:00:01,168 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 20:00:01,168 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-12 20:00:01,168 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-12 20:00:01,168 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-04-12 20:00:01,168 INFO L87 Difference]: Start difference. First operand 138 states and 157 transitions. Second operand 4 states. [2018-04-12 20:00:01,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 20:00:01,222 INFO L93 Difference]: Finished difference Result 155 states and 171 transitions. [2018-04-12 20:00:01,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-12 20:00:01,222 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 38 [2018-04-12 20:00:01,222 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 20:00:01,223 INFO L225 Difference]: With dead ends: 155 [2018-04-12 20:00:01,223 INFO L226 Difference]: Without dead ends: 153 [2018-04-12 20:00:01,224 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-04-12 20:00:01,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2018-04-12 20:00:01,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 135. [2018-04-12 20:00:01,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-04-12 20:00:01,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 152 transitions. [2018-04-12 20:00:01,227 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 152 transitions. Word has length 38 [2018-04-12 20:00:01,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 20:00:01,228 INFO L459 AbstractCegarLoop]: Abstraction has 135 states and 152 transitions. [2018-04-12 20:00:01,228 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-12 20:00:01,228 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 152 transitions. [2018-04-12 20:00:01,228 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-12 20:00:01,228 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 20:00:01,228 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 20:00:01,229 INFO L408 AbstractCegarLoop]: === Iteration 14 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 20:00:01,229 INFO L82 PathProgramCache]: Analyzing trace with hash -784439033, now seen corresponding path program 1 times [2018-04-12 20:00:01,229 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 20:00:01,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 20:00:01,237 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 20:00:01,251 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 20:00:01,251 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 20:00:01,251 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-12 20:00:01,251 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 20:00:01,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:01,252 INFO L182 omatonBuilderFactory]: Interpolants [3287#true, 3288#false, 3289#(not |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~short11|)] [2018-04-12 20:00:01,252 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 20:00:01,252 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-12 20:00:01,252 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-12 20:00:01,252 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-12 20:00:01,252 INFO L87 Difference]: Start difference. First operand 135 states and 152 transitions. Second operand 3 states. [2018-04-12 20:00:01,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 20:00:01,259 INFO L93 Difference]: Finished difference Result 137 states and 154 transitions. [2018-04-12 20:00:01,259 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-12 20:00:01,259 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 38 [2018-04-12 20:00:01,259 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 20:00:01,260 INFO L225 Difference]: With dead ends: 137 [2018-04-12 20:00:01,260 INFO L226 Difference]: Without dead ends: 137 [2018-04-12 20:00:01,260 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-12 20:00:01,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2018-04-12 20:00:01,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 137. [2018-04-12 20:00:01,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-04-12 20:00:01,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 154 transitions. [2018-04-12 20:00:01,264 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 154 transitions. Word has length 38 [2018-04-12 20:00:01,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 20:00:01,265 INFO L459 AbstractCegarLoop]: Abstraction has 137 states and 154 transitions. [2018-04-12 20:00:01,265 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-12 20:00:01,265 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 154 transitions. [2018-04-12 20:00:01,265 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-12 20:00:01,265 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 20:00:01,265 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 20:00:01,265 INFO L408 AbstractCegarLoop]: === Iteration 15 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 20:00:01,266 INFO L82 PathProgramCache]: Analyzing trace with hash -784448064, now seen corresponding path program 1 times [2018-04-12 20:00:01,266 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 20:00:01,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 20:00:01,275 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 20:00:01,371 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 20:00:01,371 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 20:00:01,371 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-04-12 20:00:01,371 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 20:00:01,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:01,371 INFO L182 omatonBuilderFactory]: Interpolants [3568#(= 0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~a.offset|), 3569#(= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0), 3570#(and (= 0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.offset|) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 3571#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 3572#(and (<= (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0 1) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 3573#(and (<= 0 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0) (<= (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0 1) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0)), 3574#(and (<= 0 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 8) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base))), 3564#true, 3565#false, 3566#(= 0 |main_#t~malloc17.offset|), 3567#(= 0 main_~numbers~0.offset)] [2018-04-12 20:00:01,372 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 20:00:01,372 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-12 20:00:01,372 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-12 20:00:01,372 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-04-12 20:00:01,372 INFO L87 Difference]: Start difference. First operand 137 states and 154 transitions. Second operand 11 states. [2018-04-12 20:00:01,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 20:00:01,481 INFO L93 Difference]: Finished difference Result 137 states and 152 transitions. [2018-04-12 20:00:01,481 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-04-12 20:00:01,481 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2018-04-12 20:00:01,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 20:00:01,482 INFO L225 Difference]: With dead ends: 137 [2018-04-12 20:00:01,482 INFO L226 Difference]: Without dead ends: 137 [2018-04-12 20:00:01,482 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=91, Invalid=251, Unknown=0, NotChecked=0, Total=342 [2018-04-12 20:00:01,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2018-04-12 20:00:01,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 135. [2018-04-12 20:00:01,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-04-12 20:00:01,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 150 transitions. [2018-04-12 20:00:01,484 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 150 transitions. Word has length 38 [2018-04-12 20:00:01,485 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 20:00:01,485 INFO L459 AbstractCegarLoop]: Abstraction has 135 states and 150 transitions. [2018-04-12 20:00:01,485 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-12 20:00:01,485 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 150 transitions. [2018-04-12 20:00:01,485 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-04-12 20:00:01,485 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 20:00:01,486 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 20:00:01,486 INFO L408 AbstractCegarLoop]: === Iteration 16 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 20:00:01,486 INFO L82 PathProgramCache]: Analyzing trace with hash -545854832, now seen corresponding path program 1 times [2018-04-12 20:00:01,486 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 20:00:01,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 20:00:01,494 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 20:00:01,645 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 20:00:01,645 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 20:00:01,645 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-04-12 20:00:01,645 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 20:00:01,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:01,646 INFO L182 omatonBuilderFactory]: Interpolants [3863#true, 3864#false, 3865#(= 0 |main_#t~malloc17.offset|), 3866#(= 0 main_~numbers~0.offset), 3867#(= 0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~a.offset|), 3868#(= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0), 3869#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 3870#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1) (<= 0 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 3871#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0) (<= 4 (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0))))] [2018-04-12 20:00:01,646 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 20:00:01,646 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-12 20:00:01,646 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-12 20:00:01,647 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-04-12 20:00:01,647 INFO L87 Difference]: Start difference. First operand 135 states and 150 transitions. Second operand 9 states. [2018-04-12 20:00:01,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 20:00:01,828 INFO L93 Difference]: Finished difference Result 135 states and 148 transitions. [2018-04-12 20:00:01,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-12 20:00:01,829 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 42 [2018-04-12 20:00:01,829 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 20:00:01,829 INFO L225 Difference]: With dead ends: 135 [2018-04-12 20:00:01,830 INFO L226 Difference]: Without dead ends: 135 [2018-04-12 20:00:01,830 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2018-04-12 20:00:01,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-04-12 20:00:01,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 133. [2018-04-12 20:00:01,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 133 states. [2018-04-12 20:00:01,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 146 transitions. [2018-04-12 20:00:01,833 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 146 transitions. Word has length 42 [2018-04-12 20:00:01,834 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 20:00:01,834 INFO L459 AbstractCegarLoop]: Abstraction has 133 states and 146 transitions. [2018-04-12 20:00:01,834 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-12 20:00:01,834 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 146 transitions. [2018-04-12 20:00:01,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-04-12 20:00:01,835 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 20:00:01,835 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 20:00:01,835 INFO L408 AbstractCegarLoop]: === Iteration 17 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 20:00:01,835 INFO L82 PathProgramCache]: Analyzing trace with hash -192166533, now seen corresponding path program 1 times [2018-04-12 20:00:01,836 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 20:00:01,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 20:00:01,848 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 20:00:02,161 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:02,162 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-12 20:00:02,162 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-04-12 20:00:02,162 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 20:00:02,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:02,162 INFO L182 omatonBuilderFactory]: Interpolants [4160#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (or (not (= 0 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset))) (= 1 (select (select |#memory_int| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base) (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset)))) (or (= 0 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset)) (and (<= (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1) |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N|) (<= 0 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset))))), 4161#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (or (<= 5 (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset (* 4 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N|))) (= 1 (select (select |#memory_int| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base) 0)))), 4162#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (or (<= 5 (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset (* 4 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N|))) (= 1 (select (select |#memory_int| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base) 0)))), 4163#(and (or (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (not (= |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~mem14| 1))) (or (= |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~mem14| 1) (<= 2 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N|))), 4164#(<= 2 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N|), 4150#true, 4151#false, 4152#(<= main_~array_size~0 1), 4153#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N|)), 4154#(and (= (select |#valid| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base|) 1) (= 0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.offset|) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N|)), 4155#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N|) (= (select |#valid| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base) 1)), 4156#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (not (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base|)) (<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N|)), 4157#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (or (<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N|) (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset) 0)) (not (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~prev~0.base))), 4158#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (or (<= (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1) |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N|) (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset) 0)) (not (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~prev~0.base))), 4159#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (or (not (= 0 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset))) (= 1 (select (select |#memory_int| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base) (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset)))) (or (= 0 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset)) (and (<= (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1) |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N|) (<= 0 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset)))) (not (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~prev~0.base)))] [2018-04-12 20:00:02,163 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:02,163 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-04-12 20:00:02,163 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-04-12 20:00:02,163 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=175, Unknown=0, NotChecked=0, Total=210 [2018-04-12 20:00:02,163 INFO L87 Difference]: Start difference. First operand 133 states and 146 transitions. Second operand 15 states. [2018-04-12 20:00:02,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 20:00:02,888 INFO L93 Difference]: Finished difference Result 238 states and 264 transitions. [2018-04-12 20:00:02,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-04-12 20:00:02,888 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 44 [2018-04-12 20:00:02,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 20:00:02,890 INFO L225 Difference]: With dead ends: 238 [2018-04-12 20:00:02,890 INFO L226 Difference]: Without dead ends: 228 [2018-04-12 20:00:02,891 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 211 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=308, Invalid=814, Unknown=0, NotChecked=0, Total=1122 [2018-04-12 20:00:02,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states. [2018-04-12 20:00:02,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 133. [2018-04-12 20:00:02,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 133 states. [2018-04-12 20:00:02,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 145 transitions. [2018-04-12 20:00:02,894 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 145 transitions. Word has length 44 [2018-04-12 20:00:02,894 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 20:00:02,894 INFO L459 AbstractCegarLoop]: Abstraction has 133 states and 145 transitions. [2018-04-12 20:00:02,894 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-04-12 20:00:02,894 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 145 transitions. [2018-04-12 20:00:02,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-04-12 20:00:02,894 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 20:00:02,894 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 20:00:02,901 INFO L408 AbstractCegarLoop]: === Iteration 18 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 20:00:02,902 INFO L82 PathProgramCache]: Analyzing trace with hash -1221525831, now seen corresponding path program 1 times [2018-04-12 20:00:02,902 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 20:00:02,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 20:00:02,913 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 20:00:03,129 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:03,129 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-12 20:00:03,129 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-04-12 20:00:03,129 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 20:00:03,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:03,130 INFO L182 omatonBuilderFactory]: Interpolants [4576#(= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0), 4577#(and (= (select |#valid| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base|) 1) (= 0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.offset|) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0)), 4578#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (= (select |#valid| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base) 1)), 4579#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (not (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base|))), 4580#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (or (not (= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset) 0)) (and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (not (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~prev~0.base))))), 4581#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (or (not (= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset) 0)) (and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (not (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~prev~0.base)))) (or (<= (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset) 0))), 4582#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (or (<= (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset) 0)) (or (not (= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset) 0)) (and (= 1 (select (select |#memory_int| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base) (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset))) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (not (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~prev~0.base)))) (<= 0 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset))), 4583#(and (or (and (= 1 (select (select |#memory_int| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base) (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset))) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0)) (not (= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset) 0))) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (or (<= (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset) 0)) (<= 0 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset))), 4584#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (or (and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (= 1 (select (select |#memory_int| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base) 0))) (<= 5 (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N))))), 4585#(and (or (and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1) (<= 5 (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N)))) (and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (= 1 (select (select |#memory_int| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base) 0)))) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0)), 4586#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (= 1 (select (select |#memory_int| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base) 0))), 4587#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.offset 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0) (= 1 (select (select |#memory_int| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~best~0.base) 0))), 4588#(and (= |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~mem14| 1) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~max~0 0)), 4574#true, 4575#false] [2018-04-12 20:00:03,130 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:03,130 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-04-12 20:00:03,130 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-04-12 20:00:03,130 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=164, Unknown=0, NotChecked=0, Total=210 [2018-04-12 20:00:03,130 INFO L87 Difference]: Start difference. First operand 133 states and 145 transitions. Second operand 15 states. [2018-04-12 20:00:03,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 20:00:03,653 INFO L93 Difference]: Finished difference Result 245 states and 276 transitions. [2018-04-12 20:00:03,653 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-04-12 20:00:03,653 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 44 [2018-04-12 20:00:03,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 20:00:03,654 INFO L225 Difference]: With dead ends: 245 [2018-04-12 20:00:03,654 INFO L226 Difference]: Without dead ends: 245 [2018-04-12 20:00:03,654 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 171 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=247, Invalid=623, Unknown=0, NotChecked=0, Total=870 [2018-04-12 20:00:03,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245 states. [2018-04-12 20:00:03,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245 to 138. [2018-04-12 20:00:03,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-04-12 20:00:03,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 150 transitions. [2018-04-12 20:00:03,656 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 150 transitions. Word has length 44 [2018-04-12 20:00:03,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 20:00:03,657 INFO L459 AbstractCegarLoop]: Abstraction has 138 states and 150 transitions. [2018-04-12 20:00:03,657 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-04-12 20:00:03,657 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 150 transitions. [2018-04-12 20:00:03,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-04-12 20:00:03,657 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 20:00:03,657 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 20:00:03,657 INFO L408 AbstractCegarLoop]: === Iteration 19 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 20:00:03,657 INFO L82 PathProgramCache]: Analyzing trace with hash 2143854456, now seen corresponding path program 1 times [2018-04-12 20:00:03,658 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 20:00:03,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 20:00:03,664 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 20:00:03,774 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-12 20:00:03,774 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 20:00:03,774 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-04-12 20:00:03,774 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 20:00:03,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:03,775 INFO L182 omatonBuilderFactory]: Interpolants [5008#(and (= (store |#valid| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base| (select |old(#valid)| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base|)) |old(#valid)|) (= 0 (select |old(#valid)| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base|))), 5009#(= (store |#valid| |main_#t~malloc17.base| 0) |old(#valid)|), 5002#true, 5003#false, 5004#(= |#valid| |old(#valid)|), 5005#(and (= (store |#valid| |main_#t~malloc17.base| 0) |old(#valid)|) (= (select |#valid| |main_#t~malloc17.base|) 1)), 5006#(and (= (select |#valid| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base|) 1) (= 0 (select |old(#valid)| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base|)) (= (store |#valid| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base| (select |old(#valid)| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base|)) |old(#valid)|)), 5007#(and (= 0 (select |old(#valid)| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base|)) (= 0 (select |old(#valid)| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base|)) (not (= |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base|)) (= (store (store |#valid| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base| (select |old(#valid)| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc2.base|)) |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base| (select |old(#valid)| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#t~malloc3.base|)) |old(#valid)|))] [2018-04-12 20:00:03,775 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-12 20:00:03,775 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-12 20:00:03,775 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-12 20:00:03,775 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-04-12 20:00:03,775 INFO L87 Difference]: Start difference. First operand 138 states and 150 transitions. Second operand 8 states. [2018-04-12 20:00:03,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 20:00:03,868 INFO L93 Difference]: Finished difference Result 137 states and 149 transitions. [2018-04-12 20:00:03,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-12 20:00:03,868 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 46 [2018-04-12 20:00:03,869 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 20:00:03,869 INFO L225 Difference]: With dead ends: 137 [2018-04-12 20:00:03,869 INFO L226 Difference]: Without dead ends: 73 [2018-04-12 20:00:03,869 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=26, Invalid=84, Unknown=0, NotChecked=0, Total=110 [2018-04-12 20:00:03,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-04-12 20:00:03,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73. [2018-04-12 20:00:03,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-04-12 20:00:03,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 81 transitions. [2018-04-12 20:00:03,871 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 81 transitions. Word has length 46 [2018-04-12 20:00:03,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 20:00:03,871 INFO L459 AbstractCegarLoop]: Abstraction has 73 states and 81 transitions. [2018-04-12 20:00:03,871 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-12 20:00:03,871 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 81 transitions. [2018-04-12 20:00:03,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-04-12 20:00:03,871 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 20:00:03,871 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 20:00:03,871 INFO L408 AbstractCegarLoop]: === Iteration 20 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 20:00:03,871 INFO L82 PathProgramCache]: Analyzing trace with hash -145359495, now seen corresponding path program 1 times [2018-04-12 20:00:03,872 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 20:00:03,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 20:00:03,877 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 20:00:03,959 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 5 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:03,960 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-12 20:00:03,960 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-04-12 20:00:03,960 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 20:00:03,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:03,960 INFO L182 omatonBuilderFactory]: Interpolants [5226#true, 5227#false, 5228#(= 0 |main_#t~malloc17.offset|), 5229#(= 0 main_~numbers~0.offset), 5230#(= 0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~a.offset|), 5231#(= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0), 5232#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 5233#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0) (<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1)), 5234#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0) (<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 2)), 5235#(and (<= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N 2) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 5236#(and (<= (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0 1)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 5237#(and (<= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 4)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 5238#(and (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0) (<= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset)))] [2018-04-12 20:00:03,960 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 5 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:03,960 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-04-12 20:00:03,960 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-04-12 20:00:03,960 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=122, Unknown=0, NotChecked=0, Total=156 [2018-04-12 20:00:03,961 INFO L87 Difference]: Start difference. First operand 73 states and 81 transitions. Second operand 13 states. [2018-04-12 20:00:04,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 20:00:04,108 INFO L93 Difference]: Finished difference Result 131 states and 146 transitions. [2018-04-12 20:00:04,108 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-04-12 20:00:04,108 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 46 [2018-04-12 20:00:04,108 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 20:00:04,108 INFO L225 Difference]: With dead ends: 131 [2018-04-12 20:00:04,108 INFO L226 Difference]: Without dead ends: 107 [2018-04-12 20:00:04,109 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=108, Invalid=354, Unknown=0, NotChecked=0, Total=462 [2018-04-12 20:00:04,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-04-12 20:00:04,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 78. [2018-04-12 20:00:04,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-04-12 20:00:04,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 86 transitions. [2018-04-12 20:00:04,110 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 86 transitions. Word has length 46 [2018-04-12 20:00:04,110 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 20:00:04,110 INFO L459 AbstractCegarLoop]: Abstraction has 78 states and 86 transitions. [2018-04-12 20:00:04,110 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-04-12 20:00:04,110 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 86 transitions. [2018-04-12 20:00:04,110 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-04-12 20:00:04,110 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 20:00:04,111 INFO L355 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 20:00:04,111 INFO L408 AbstractCegarLoop]: === Iteration 21 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 20:00:04,111 INFO L82 PathProgramCache]: Analyzing trace with hash 530723226, now seen corresponding path program 2 times [2018-04-12 20:00:04,111 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 20:00:04,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 20:00:04,119 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 20:00:04,265 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 4 proven. 5 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-04-12 20:00:04,265 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-12 20:00:04,265 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-04-12 20:00:04,265 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 20:00:04,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:04,266 INFO L182 omatonBuilderFactory]: Interpolants [5472#(and (<= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (<= (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0 1) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 5473#(and (<= 4 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset)) (<= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 5474#(and (<= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (<= 8 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 5475#(and (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) 4) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (<= 8 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0)), 5466#true, 5467#false, 5468#(and (= (* 4 main_~array_size~0) (select |#length| |main_#t~malloc17.base|)) (= 0 |main_#t~malloc17.offset|)), 5469#(and (= 0 main_~numbers~0.offset) (= (* 4 main_~array_size~0) (select |#length| main_~numbers~0.base))), 5470#(and (<= (* 4 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~N|) (select |#length| |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~a.base|)) (= 0 |__U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_#in~a.offset|)), 5471#(and (<= (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~N) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (= __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 0))] [2018-04-12 20:00:04,266 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 4 proven. 5 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-04-12 20:00:04,266 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-12 20:00:04,266 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-12 20:00:04,266 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-04-12 20:00:04,266 INFO L87 Difference]: Start difference. First operand 78 states and 86 transitions. Second operand 10 states. [2018-04-12 20:00:04,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 20:00:04,390 INFO L93 Difference]: Finished difference Result 78 states and 84 transitions. [2018-04-12 20:00:04,390 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-04-12 20:00:04,390 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 51 [2018-04-12 20:00:04,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 20:00:04,390 INFO L225 Difference]: With dead ends: 78 [2018-04-12 20:00:04,390 INFO L226 Difference]: Without dead ends: 78 [2018-04-12 20:00:04,390 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 6 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=161, Unknown=0, NotChecked=0, Total=210 [2018-04-12 20:00:04,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2018-04-12 20:00:04,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 77. [2018-04-12 20:00:04,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-04-12 20:00:04,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 83 transitions. [2018-04-12 20:00:04,392 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 83 transitions. Word has length 51 [2018-04-12 20:00:04,392 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 20:00:04,392 INFO L459 AbstractCegarLoop]: Abstraction has 77 states and 83 transitions. [2018-04-12 20:00:04,392 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-12 20:00:04,392 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 83 transitions. [2018-04-12 20:00:04,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-04-12 20:00:04,392 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 20:00:04,392 INFO L355 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 20:00:04,392 INFO L408 AbstractCegarLoop]: === Iteration 22 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 20:00:04,392 INFO L82 PathProgramCache]: Analyzing trace with hash 271503815, now seen corresponding path program 1 times [2018-04-12 20:00:04,393 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-12 20:00:04,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 20:00:04,398 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 20:00:04,425 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 14 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-04-12 20:00:04,425 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-12 20:00:04,425 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-04-12 20:00:04,425 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-04-12 20:00:04,425 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 20:00:04,425 INFO L182 omatonBuilderFactory]: Interpolants [5641#true, 5642#false, 5643#(<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 4) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)), 5644#(and (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 4) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (<= 0 (+ __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0)))), 5645#(and (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~i~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 4) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)) (<= 4 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset))), 5646#(and (<= 4 (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset)) (<= (+ (* 4 __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~j~0) __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.offset 8) (select |#length| __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis_~a.base)))] [2018-04-12 20:00:04,425 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 14 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-04-12 20:00:04,425 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-12 20:00:04,426 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-12 20:00:04,426 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-04-12 20:00:04,426 INFO L87 Difference]: Start difference. First operand 77 states and 83 transitions. Second operand 6 states. [2018-04-12 20:00:04,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 20:00:04,490 INFO L93 Difference]: Finished difference Result 88 states and 96 transitions. [2018-04-12 20:00:04,492 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-12 20:00:04,492 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 60 [2018-04-12 20:00:04,492 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 20:00:04,492 INFO L225 Difference]: With dead ends: 88 [2018-04-12 20:00:04,492 INFO L226 Difference]: Without dead ends: 0 [2018-04-12 20:00:04,492 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-04-12 20:00:04,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2018-04-12 20:00:04,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2018-04-12 20:00:04,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 0 states. [2018-04-12 20:00:04,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2018-04-12 20:00:04,493 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 60 [2018-04-12 20:00:04,493 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 20:00:04,493 INFO L459 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2018-04-12 20:00:04,493 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-12 20:00:04,493 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2018-04-12 20:00:04,493 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-04-12 20:00:04,496 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 12.04 08:00:04 BoogieIcfgContainer [2018-04-12 20:00:04,496 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-04-12 20:00:04,496 INFO L168 Benchmark]: Toolchain (without parser) took 6845.65 ms. Allocated memory was 402.7 MB in the beginning and 764.9 MB in the end (delta: 362.3 MB). Free memory was 340.5 MB in the beginning and 586.7 MB in the end (delta: -246.2 MB). Peak memory consumption was 116.1 MB. Max. memory is 5.3 GB. [2018-04-12 20:00:04,498 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 402.7 MB. Free memory is still 364.7 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-04-12 20:00:04,498 INFO L168 Benchmark]: CACSL2BoogieTranslator took 270.43 ms. Allocated memory is still 402.7 MB. Free memory was 339.2 MB in the beginning and 315.3 MB in the end (delta: 23.9 MB). Peak memory consumption was 23.9 MB. Max. memory is 5.3 GB. [2018-04-12 20:00:04,498 INFO L168 Benchmark]: Boogie Preprocessor took 40.54 ms. Allocated memory is still 402.7 MB. Free memory was 315.3 MB in the beginning and 312.7 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. [2018-04-12 20:00:04,498 INFO L168 Benchmark]: RCFGBuilder took 448.86 ms. Allocated memory was 402.7 MB in the beginning and 618.1 MB in the end (delta: 215.5 MB). Free memory was 312.7 MB in the beginning and 545.7 MB in the end (delta: -233.0 MB). Peak memory consumption was 22.7 MB. Max. memory is 5.3 GB. [2018-04-12 20:00:04,499 INFO L168 Benchmark]: TraceAbstraction took 6082.83 ms. Allocated memory was 618.1 MB in the beginning and 764.9 MB in the end (delta: 146.8 MB). Free memory was 545.7 MB in the beginning and 586.7 MB in the end (delta: -41.1 MB). Peak memory consumption was 105.7 MB. Max. memory is 5.3 GB. [2018-04-12 20:00:04,501 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 402.7 MB. Free memory is still 364.7 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 270.43 ms. Allocated memory is still 402.7 MB. Free memory was 339.2 MB in the beginning and 315.3 MB in the end (delta: 23.9 MB). Peak memory consumption was 23.9 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 40.54 ms. Allocated memory is still 402.7 MB. Free memory was 315.3 MB in the beginning and 312.7 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 448.86 ms. Allocated memory was 402.7 MB in the beginning and 618.1 MB in the end (delta: 215.5 MB). Free memory was 312.7 MB in the beginning and 545.7 MB in the end (delta: -233.0 MB). Peak memory consumption was 22.7 MB. Max. memory is 5.3 GB. * TraceAbstraction took 6082.83 ms. Allocated memory was 618.1 MB in the beginning and 764.9 MB in the end (delta: 146.8 MB). Free memory was 545.7 MB in the beginning and 586.7 MB in the end (delta: -41.1 MB). Peak memory consumption was 105.7 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - PositiveResult [Line: 556]: all allocated memory was freed For all program executions holds that all allocated memory was freed at this location - PositiveResult [Line: 546]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 553]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 546]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 552]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 546]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 546]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 552]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 553]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - AllSpecificationsHoldResult: All specifications hold 23 specifications checked. All of them hold - StatisticsResult: Ultimate Automizer benchmark data CFG has 6 procedures, 90 locations, 23 error locations. SAFE Result, 6.0s OverallTime, 22 OverallIterations, 4 TraceHistogramMax, 3.6s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1159 SDtfs, 4252 SDslu, 3418 SDs, 0 SdLazy, 2819 SolverSat, 363 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 307 GetRequests, 39 SyntacticMatches, 18 SemanticMatches, 250 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 599 ImplicationChecksByTransitivity, 3.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=138occurred in iteration=12, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 145/184 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 22 MinimizatonAttempts, 457 StatesRemovedByMinimization, 16 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.1s SatisfiabilityAnalysisTime, 1.9s InterpolantComputationTime, 741 NumberOfCodeBlocks, 741 NumberOfCodeBlocksAsserted, 22 NumberOfCheckSat, 719 ConstructedInterpolants, 0 QuantifiedInterpolants, 185979 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 22 InterpolantComputations, 13 PerfectInterpolantSequences, 145/184 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be correct! Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/lis-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-Benchmark-0-2018-04-12_20-00-04-517.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/lis-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-04-12_20-00-04-517.csv Received shutdown request...