java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv --cacsl2boogietranslator.bitprecise.bitfields false -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c -------------------------------------------------------------------------------- This is Ultimate 0.1.23-408c70d-m [2018-04-13 08:22:37,179 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-04-13 08:22:37,181 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-04-13 08:22:37,193 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-04-13 08:22:37,194 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-04-13 08:22:37,194 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-04-13 08:22:37,195 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-04-13 08:22:37,196 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-04-13 08:22:37,198 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-04-13 08:22:37,198 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-04-13 08:22:37,199 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-04-13 08:22:37,199 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-04-13 08:22:37,200 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-04-13 08:22:37,201 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-04-13 08:22:37,202 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-04-13 08:22:37,203 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-04-13 08:22:37,205 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-04-13 08:22:37,206 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-04-13 08:22:37,207 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-04-13 08:22:37,208 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-04-13 08:22:37,209 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-04-13 08:22:37,210 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-04-13 08:22:37,210 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-04-13 08:22:37,211 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-04-13 08:22:37,211 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-04-13 08:22:37,212 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-04-13 08:22:37,212 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-04-13 08:22:37,213 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-04-13 08:22:37,213 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-04-13 08:22:37,214 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-04-13 08:22:37,214 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-04-13 08:22:37,215 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf [2018-04-13 08:22:37,224 INFO L110 SettingsManager]: Loading preferences was successful [2018-04-13 08:22:37,224 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-04-13 08:22:37,225 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-04-13 08:22:37,225 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-04-13 08:22:37,225 INFO L133 SettingsManager]: * Use SBE=true [2018-04-13 08:22:37,226 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-04-13 08:22:37,226 INFO L133 SettingsManager]: * sizeof long=4 [2018-04-13 08:22:37,226 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-04-13 08:22:37,226 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-04-13 08:22:37,226 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-04-13 08:22:37,226 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-04-13 08:22:37,226 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-04-13 08:22:37,226 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-04-13 08:22:37,226 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-04-13 08:22:37,226 INFO L133 SettingsManager]: * sizeof long double=12 [2018-04-13 08:22:37,227 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-04-13 08:22:37,227 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-04-13 08:22:37,227 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-04-13 08:22:37,227 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-04-13 08:22:37,227 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-13 08:22:37,227 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-04-13 08:22:37,227 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-04-13 08:22:37,227 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-04-13 08:22:37,227 INFO L133 SettingsManager]: * Trace refinement strategy=SMTINTERPOL Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Bitprecise bitfields -> false [2018-04-13 08:22:37,258 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-04-13 08:22:37,268 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully (re)initialized [2018-04-13 08:22:37,272 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-04-13 08:22:37,273 INFO L271 PluginConnector]: Initializing CDTParser... [2018-04-13 08:22:37,273 INFO L276 PluginConnector]: CDTParser initialized [2018-04-13 08:22:37,274 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-04-13 08:22:37,571 INFO L225 CDTParser]: Created temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGad0f48dd8 [2018-04-13 08:22:37,668 INFO L287 CDTParser]: IsIndexed: true [2018-04-13 08:22:37,668 INFO L288 CDTParser]: Found 1 translation units. [2018-04-13 08:22:37,669 INFO L168 CDTParser]: Scanning ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-04-13 08:22:37,669 INFO L210 ultiparseSymbolTable]: Include resolver: [2018-04-13 08:22:37,669 INFO L215 ultiparseSymbolTable]: [2018-04-13 08:22:37,669 INFO L218 ultiparseSymbolTable]: Function table: [2018-04-13 08:22:37,669 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__foo ('foo') in ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-04-13 08:22:37,669 INFO L221 ultiparseSymbolTable]: Function definition of null ('main') in ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-04-13 08:22:37,670 INFO L227 ultiparseSymbolTable]: Global variable table: [2018-04-13 08:22:37,670 INFO L233 ultiparseSymbolTable]: [2018-04-13 08:22:37,681 INFO L330 CDTParser]: Deleted temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGad0f48dd8 [2018-04-13 08:22:37,684 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-04-13 08:22:37,685 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-04-13 08:22:37,686 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-04-13 08:22:37,686 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-04-13 08:22:37,689 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-04-13 08:22:37,690 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.04 08:22:37" (1/1) ... [2018-04-13 08:22:37,692 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3baeb232 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:22:37, skipping insertion in model container [2018-04-13 08:22:37,692 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.04 08:22:37" (1/1) ... [2018-04-13 08:22:37,702 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-13 08:22:37,710 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-13 08:22:37,802 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-13 08:22:37,822 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-13 08:22:37,827 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 9 non ball SCCs. Number of states in SCCs 9. [2018-04-13 08:22:37,833 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:22:37 WrapperNode [2018-04-13 08:22:37,833 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-04-13 08:22:37,834 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-04-13 08:22:37,834 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-04-13 08:22:37,834 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-04-13 08:22:37,842 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:22:37" (1/1) ... [2018-04-13 08:22:37,842 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:22:37" (1/1) ... [2018-04-13 08:22:37,848 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:22:37" (1/1) ... [2018-04-13 08:22:37,849 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:22:37" (1/1) ... [2018-04-13 08:22:37,852 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:22:37" (1/1) ... [2018-04-13 08:22:37,856 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:22:37" (1/1) ... [2018-04-13 08:22:37,857 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:22:37" (1/1) ... [2018-04-13 08:22:37,858 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-04-13 08:22:37,859 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-04-13 08:22:37,859 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-04-13 08:22:37,859 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-04-13 08:22:37,860 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:22:37" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-13 08:22:37,894 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-04-13 08:22:37,895 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-04-13 08:22:37,895 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__foo [2018-04-13 08:22:37,895 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-04-13 08:22:37,895 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__foo [2018-04-13 08:22:37,895 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-04-13 08:22:37,895 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-04-13 08:22:37,895 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-04-13 08:22:37,895 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-04-13 08:22:37,895 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-04-13 08:22:37,895 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-04-13 08:22:37,896 INFO L128 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-04-13 08:22:37,896 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-04-13 08:22:38,078 INFO L259 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-04-13 08:22:38,078 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.04 08:22:38 BoogieIcfgContainer [2018-04-13 08:22:38,079 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-04-13 08:22:38,079 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-04-13 08:22:38,079 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-04-13 08:22:38,081 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-04-13 08:22:38,081 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 13.04 08:22:37" (1/3) ... [2018-04-13 08:22:38,082 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@24cd5d41 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 13.04 08:22:38, skipping insertion in model container [2018-04-13 08:22:38,082 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:22:37" (2/3) ... [2018-04-13 08:22:38,082 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@24cd5d41 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 13.04 08:22:38, skipping insertion in model container [2018-04-13 08:22:38,082 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.04 08:22:38" (3/3) ... [2018-04-13 08:22:38,083 INFO L107 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_false-valid-deref-read.c [2018-04-13 08:22:38,089 INFO L131 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-04-13 08:22:38,093 INFO L143 ceAbstractionStarter]: Appying trace abstraction to program that has 6 error locations. [2018-04-13 08:22:38,120 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-04-13 08:22:38,122 INFO L369 AbstractCegarLoop]: Interprodecural is true [2018-04-13 08:22:38,122 INFO L370 AbstractCegarLoop]: Hoare is false [2018-04-13 08:22:38,122 INFO L371 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-04-13 08:22:38,122 INFO L372 AbstractCegarLoop]: Backedges is TWOTRACK [2018-04-13 08:22:38,122 INFO L373 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-04-13 08:22:38,123 INFO L374 AbstractCegarLoop]: Difference is false [2018-04-13 08:22:38,123 INFO L375 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-04-13 08:22:38,123 INFO L380 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-04-13 08:22:38,124 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-04-13 08:22:38,134 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states. [2018-04-13 08:22:38,140 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-04-13 08:22:38,140 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:38,141 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:38,141 INFO L408 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:38,144 INFO L82 PathProgramCache]: Analyzing trace with hash -215054890, now seen corresponding path program 1 times [2018-04-13 08:22:38,145 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:38,145 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:38,181 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:38,181 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:38,182 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:38,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:38,213 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:38,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:22:38,254 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-13 08:22:38,254 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-04-13 08:22:38,256 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-13 08:22:38,268 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-13 08:22:38,268 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-13 08:22:38,270 INFO L87 Difference]: Start difference. First operand 46 states. Second operand 3 states. [2018-04-13 08:22:38,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:38,324 INFO L93 Difference]: Finished difference Result 63 states and 68 transitions. [2018-04-13 08:22:38,324 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-13 08:22:38,325 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-04-13 08:22:38,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:38,331 INFO L225 Difference]: With dead ends: 63 [2018-04-13 08:22:38,331 INFO L226 Difference]: Without dead ends: 59 [2018-04-13 08:22:38,332 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-13 08:22:38,342 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-04-13 08:22:38,354 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 49. [2018-04-13 08:22:38,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-04-13 08:22:38,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 52 transitions. [2018-04-13 08:22:38,356 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 52 transitions. Word has length 11 [2018-04-13 08:22:38,357 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:38,357 INFO L459 AbstractCegarLoop]: Abstraction has 49 states and 52 transitions. [2018-04-13 08:22:38,357 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-13 08:22:38,357 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 52 transitions. [2018-04-13 08:22:38,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-04-13 08:22:38,357 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:38,358 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:38,358 INFO L408 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:38,358 INFO L82 PathProgramCache]: Analyzing trace with hash 1100032001, now seen corresponding path program 1 times [2018-04-13 08:22:38,358 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:38,358 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:38,359 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:38,359 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:38,359 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:38,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:38,374 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:38,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:22:38,392 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-13 08:22:38,393 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-04-13 08:22:38,394 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-13 08:22:38,394 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-13 08:22:38,395 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-13 08:22:38,395 INFO L87 Difference]: Start difference. First operand 49 states and 52 transitions. Second operand 3 states. [2018-04-13 08:22:38,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:38,425 INFO L93 Difference]: Finished difference Result 60 states and 64 transitions. [2018-04-13 08:22:38,425 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-13 08:22:38,425 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 16 [2018-04-13 08:22:38,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:38,427 INFO L225 Difference]: With dead ends: 60 [2018-04-13 08:22:38,427 INFO L226 Difference]: Without dead ends: 60 [2018-04-13 08:22:38,428 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-13 08:22:38,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-04-13 08:22:38,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 52. [2018-04-13 08:22:38,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-04-13 08:22:38,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 56 transitions. [2018-04-13 08:22:38,433 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 56 transitions. Word has length 16 [2018-04-13 08:22:38,433 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:38,434 INFO L459 AbstractCegarLoop]: Abstraction has 52 states and 56 transitions. [2018-04-13 08:22:38,434 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-13 08:22:38,434 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 56 transitions. [2018-04-13 08:22:38,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-04-13 08:22:38,434 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:38,434 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:38,435 INFO L408 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:38,435 INFO L82 PathProgramCache]: Analyzing trace with hash -258746290, now seen corresponding path program 1 times [2018-04-13 08:22:38,435 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:38,435 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:38,436 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:38,436 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:38,436 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:38,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:38,448 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:38,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:22:38,546 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-13 08:22:38,546 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-04-13 08:22:38,546 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-13 08:22:38,546 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-13 08:22:38,546 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-04-13 08:22:38,547 INFO L87 Difference]: Start difference. First operand 52 states and 56 transitions. Second operand 8 states. [2018-04-13 08:22:38,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:38,732 INFO L93 Difference]: Finished difference Result 75 states and 81 transitions. [2018-04-13 08:22:38,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-13 08:22:38,733 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 17 [2018-04-13 08:22:38,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:38,734 INFO L225 Difference]: With dead ends: 75 [2018-04-13 08:22:38,734 INFO L226 Difference]: Without dead ends: 75 [2018-04-13 08:22:38,734 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2018-04-13 08:22:38,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2018-04-13 08:22:38,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 66. [2018-04-13 08:22:38,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-04-13 08:22:38,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 73 transitions. [2018-04-13 08:22:38,743 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 73 transitions. Word has length 17 [2018-04-13 08:22:38,743 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:38,743 INFO L459 AbstractCegarLoop]: Abstraction has 66 states and 73 transitions. [2018-04-13 08:22:38,743 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-13 08:22:38,743 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 73 transitions. [2018-04-13 08:22:38,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-04-13 08:22:38,744 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:38,744 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:38,744 INFO L408 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:38,744 INFO L82 PathProgramCache]: Analyzing trace with hash -258746291, now seen corresponding path program 1 times [2018-04-13 08:22:38,744 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:38,744 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:38,745 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:38,746 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:38,746 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:38,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:38,751 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:38,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:22:38,779 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-13 08:22:38,780 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-13 08:22:38,780 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-13 08:22:38,780 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-13 08:22:38,781 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-04-13 08:22:38,781 INFO L87 Difference]: Start difference. First operand 66 states and 73 transitions. Second operand 5 states. [2018-04-13 08:22:38,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:38,806 INFO L93 Difference]: Finished difference Result 65 states and 71 transitions. [2018-04-13 08:22:38,806 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-13 08:22:38,807 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-04-13 08:22:38,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:38,807 INFO L225 Difference]: With dead ends: 65 [2018-04-13 08:22:38,808 INFO L226 Difference]: Without dead ends: 65 [2018-04-13 08:22:38,808 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-04-13 08:22:38,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2018-04-13 08:22:38,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 65. [2018-04-13 08:22:38,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65 states. [2018-04-13 08:22:38,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 71 transitions. [2018-04-13 08:22:38,813 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 71 transitions. Word has length 17 [2018-04-13 08:22:38,813 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:38,813 INFO L459 AbstractCegarLoop]: Abstraction has 65 states and 71 transitions. [2018-04-13 08:22:38,813 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-13 08:22:38,813 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 71 transitions. [2018-04-13 08:22:38,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-04-13 08:22:38,814 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:38,814 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:38,814 INFO L408 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:38,814 INFO L82 PathProgramCache]: Analyzing trace with hash -1933852231, now seen corresponding path program 1 times [2018-04-13 08:22:38,814 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:38,814 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:38,815 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:38,815 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:38,815 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:38,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:38,824 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:38,885 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:22:38,886 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:38,886 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:38,887 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:38,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:38,907 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:38,929 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:22:38,929 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:38,929 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 3] total 9 [2018-04-13 08:22:38,929 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-13 08:22:38,929 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-13 08:22:38,930 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-04-13 08:22:38,930 INFO L87 Difference]: Start difference. First operand 65 states and 71 transitions. Second operand 10 states. [2018-04-13 08:22:39,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:39,090 INFO L93 Difference]: Finished difference Result 105 states and 114 transitions. [2018-04-13 08:22:39,091 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-13 08:22:39,091 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 22 [2018-04-13 08:22:39,091 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:39,092 INFO L225 Difference]: With dead ends: 105 [2018-04-13 08:22:39,092 INFO L226 Difference]: Without dead ends: 105 [2018-04-13 08:22:39,093 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 20 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=52, Invalid=130, Unknown=0, NotChecked=0, Total=182 [2018-04-13 08:22:39,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-04-13 08:22:39,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 76. [2018-04-13 08:22:39,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-04-13 08:22:39,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 83 transitions. [2018-04-13 08:22:39,098 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 83 transitions. Word has length 22 [2018-04-13 08:22:39,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:39,098 INFO L459 AbstractCegarLoop]: Abstraction has 76 states and 83 transitions. [2018-04-13 08:22:39,099 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-13 08:22:39,099 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 83 transitions. [2018-04-13 08:22:39,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-04-13 08:22:39,099 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:39,099 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:39,100 INFO L408 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:39,100 INFO L82 PathProgramCache]: Analyzing trace with hash 1693854175, now seen corresponding path program 1 times [2018-04-13 08:22:39,100 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:39,100 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:39,101 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:39,101 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:39,101 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:39,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:39,108 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:39,133 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-13 08:22:39,133 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-13 08:22:39,133 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-13 08:22:39,133 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-13 08:22:39,134 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-13 08:22:39,134 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-04-13 08:22:39,134 INFO L87 Difference]: Start difference. First operand 76 states and 83 transitions. Second operand 5 states. [2018-04-13 08:22:39,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:39,167 INFO L93 Difference]: Finished difference Result 85 states and 91 transitions. [2018-04-13 08:22:39,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-13 08:22:39,167 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 29 [2018-04-13 08:22:39,168 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:39,169 INFO L225 Difference]: With dead ends: 85 [2018-04-13 08:22:39,169 INFO L226 Difference]: Without dead ends: 85 [2018-04-13 08:22:39,170 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-04-13 08:22:39,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-04-13 08:22:39,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 73. [2018-04-13 08:22:39,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-04-13 08:22:39,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 80 transitions. [2018-04-13 08:22:39,175 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 80 transitions. Word has length 29 [2018-04-13 08:22:39,175 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:39,175 INFO L459 AbstractCegarLoop]: Abstraction has 73 states and 80 transitions. [2018-04-13 08:22:39,175 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-13 08:22:39,175 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 80 transitions. [2018-04-13 08:22:39,176 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-04-13 08:22:39,176 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:39,176 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:39,176 INFO L408 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:39,177 INFO L82 PathProgramCache]: Analyzing trace with hash 1643098334, now seen corresponding path program 1 times [2018-04-13 08:22:39,177 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:39,177 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:39,177 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:39,177 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:39,178 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:39,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:39,187 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:39,205 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-13 08:22:39,206 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:39,206 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:39,206 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:39,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:39,220 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:39,230 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-13 08:22:39,230 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:39,230 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2018-04-13 08:22:39,230 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-13 08:22:39,231 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-13 08:22:39,231 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-04-13 08:22:39,231 INFO L87 Difference]: Start difference. First operand 73 states and 80 transitions. Second operand 5 states. [2018-04-13 08:22:39,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:39,258 INFO L93 Difference]: Finished difference Result 99 states and 107 transitions. [2018-04-13 08:22:39,258 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-13 08:22:39,258 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 37 [2018-04-13 08:22:39,259 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:39,259 INFO L225 Difference]: With dead ends: 99 [2018-04-13 08:22:39,260 INFO L226 Difference]: Without dead ends: 99 [2018-04-13 08:22:39,260 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-04-13 08:22:39,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-04-13 08:22:39,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 82. [2018-04-13 08:22:39,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-04-13 08:22:39,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 90 transitions. [2018-04-13 08:22:39,264 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 90 transitions. Word has length 37 [2018-04-13 08:22:39,264 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:39,265 INFO L459 AbstractCegarLoop]: Abstraction has 82 states and 90 transitions. [2018-04-13 08:22:39,265 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-13 08:22:39,265 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 90 transitions. [2018-04-13 08:22:39,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-04-13 08:22:39,266 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:39,266 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:39,266 INFO L408 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:39,266 INFO L82 PathProgramCache]: Analyzing trace with hash -1898563809, now seen corresponding path program 2 times [2018-04-13 08:22:39,266 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:39,267 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:39,267 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:39,267 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:39,267 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:39,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:39,280 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:39,334 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-04-13 08:22:39,334 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:39,334 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:39,335 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:22:39,342 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-04-13 08:22:39,342 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:22:39,345 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:39,373 INFO L700 Elim1Store]: detected not equals via solver [2018-04-13 08:22:39,377 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 5 [2018-04-13 08:22:39,377 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:22:39,379 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-13 08:22:39,379 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:12, output treesize:5 [2018-04-13 08:22:39,407 INFO L700 Elim1Store]: detected not equals via solver [2018-04-13 08:22:39,408 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 5 [2018-04-13 08:22:39,408 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:22:39,409 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-13 08:22:39,409 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:12, output treesize:5 [2018-04-13 08:22:39,428 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_~#mask~0.base| Int)) (and (= (store |c_old(#valid)| |main_~#mask~0.base| 0) |c_#valid|) (= (select |c_old(#valid)| |main_~#mask~0.base|) 0))) is different from true [2018-04-13 08:22:39,437 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-04-13 08:22:39,438 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-04-13 08:22:39,438 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [6] total 10 [2018-04-13 08:22:39,438 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-13 08:22:39,440 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-13 08:22:39,440 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=56, Unknown=1, NotChecked=14, Total=90 [2018-04-13 08:22:39,440 INFO L87 Difference]: Start difference. First operand 82 states and 90 transitions. Second operand 10 states. [2018-04-13 08:22:39,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:39,662 INFO L93 Difference]: Finished difference Result 105 states and 111 transitions. [2018-04-13 08:22:39,662 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-04-13 08:22:39,662 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 49 [2018-04-13 08:22:39,662 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:39,663 INFO L225 Difference]: With dead ends: 105 [2018-04-13 08:22:39,663 INFO L226 Difference]: Without dead ends: 77 [2018-04-13 08:22:39,663 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 46 SyntacticMatches, 3 SemanticMatches, 16 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=69, Invalid=206, Unknown=1, NotChecked=30, Total=306 [2018-04-13 08:22:39,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2018-04-13 08:22:39,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 63. [2018-04-13 08:22:39,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-04-13 08:22:39,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 68 transitions. [2018-04-13 08:22:39,667 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 68 transitions. Word has length 49 [2018-04-13 08:22:39,668 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:39,668 INFO L459 AbstractCegarLoop]: Abstraction has 63 states and 68 transitions. [2018-04-13 08:22:39,668 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-13 08:22:39,668 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 68 transitions. [2018-04-13 08:22:39,669 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-04-13 08:22:39,669 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:39,669 INFO L355 BasicCegarLoop]: trace histogram [7, 6, 6, 5, 5, 5, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:39,669 INFO L408 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:39,669 INFO L82 PathProgramCache]: Analyzing trace with hash 98230391, now seen corresponding path program 1 times [2018-04-13 08:22:39,669 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:39,670 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:39,670 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:39,670 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:22:39,670 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:39,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:39,685 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:39,825 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 53 proven. 30 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-04-13 08:22:39,825 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:39,825 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:39,826 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:39,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:39,843 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:39,897 INFO L134 CoverageAnalysis]: Checked inductivity of 97 backedges. 83 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-04-13 08:22:39,897 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:39,897 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 9] total 16 [2018-04-13 08:22:39,898 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-13 08:22:39,898 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-13 08:22:39,898 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=196, Unknown=0, NotChecked=0, Total=240 [2018-04-13 08:22:39,898 INFO L87 Difference]: Start difference. First operand 63 states and 68 transitions. Second operand 16 states. [2018-04-13 08:22:40,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:40,304 INFO L93 Difference]: Finished difference Result 133 states and 142 transitions. [2018-04-13 08:22:40,305 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-04-13 08:22:40,305 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 59 [2018-04-13 08:22:40,305 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:40,306 INFO L225 Difference]: With dead ends: 133 [2018-04-13 08:22:40,306 INFO L226 Difference]: Without dead ends: 133 [2018-04-13 08:22:40,306 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 52 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 180 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=200, Invalid=730, Unknown=0, NotChecked=0, Total=930 [2018-04-13 08:22:40,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2018-04-13 08:22:40,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 105. [2018-04-13 08:22:40,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-04-13 08:22:40,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 114 transitions. [2018-04-13 08:22:40,310 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 114 transitions. Word has length 59 [2018-04-13 08:22:40,310 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:40,310 INFO L459 AbstractCegarLoop]: Abstraction has 105 states and 114 transitions. [2018-04-13 08:22:40,310 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-13 08:22:40,310 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 114 transitions. [2018-04-13 08:22:40,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-04-13 08:22:40,311 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:40,312 INFO L355 BasicCegarLoop]: trace histogram [9, 7, 7, 6, 6, 6, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:40,313 INFO L408 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:40,313 INFO L82 PathProgramCache]: Analyzing trace with hash -480231808, now seen corresponding path program 2 times [2018-04-13 08:22:40,314 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:40,314 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:40,315 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:40,315 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:40,315 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:40,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:40,327 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:40,366 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 101 proven. 0 refuted. 0 times theorem prover too weak. 63 trivial. 0 not checked. [2018-04-13 08:22:40,367 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-13 08:22:40,368 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-04-13 08:22:40,368 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-04-13 08:22:40,368 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-04-13 08:22:40,368 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-04-13 08:22:40,369 INFO L87 Difference]: Start difference. First operand 105 states and 114 transitions. Second operand 7 states. [2018-04-13 08:22:40,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:40,419 INFO L93 Difference]: Finished difference Result 111 states and 118 transitions. [2018-04-13 08:22:40,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-13 08:22:40,420 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 77 [2018-04-13 08:22:40,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:40,421 INFO L225 Difference]: With dead ends: 111 [2018-04-13 08:22:40,421 INFO L226 Difference]: Without dead ends: 105 [2018-04-13 08:22:40,422 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-04-13 08:22:40,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-04-13 08:22:40,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 105. [2018-04-13 08:22:40,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-04-13 08:22:40,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 112 transitions. [2018-04-13 08:22:40,426 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 112 transitions. Word has length 77 [2018-04-13 08:22:40,426 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:40,426 INFO L459 AbstractCegarLoop]: Abstraction has 105 states and 112 transitions. [2018-04-13 08:22:40,426 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-04-13 08:22:40,426 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 112 transitions. [2018-04-13 08:22:40,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-04-13 08:22:40,427 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:40,428 INFO L355 BasicCegarLoop]: trace histogram [10, 8, 8, 7, 7, 7, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:40,428 INFO L408 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:40,428 INFO L82 PathProgramCache]: Analyzing trace with hash 49530632, now seen corresponding path program 3 times [2018-04-13 08:22:40,428 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:40,428 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:40,429 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:40,429 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:22:40,429 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:40,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:40,440 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:40,486 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 143 proven. 2 refuted. 0 times theorem prover too weak. 63 trivial. 0 not checked. [2018-04-13 08:22:40,487 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:40,487 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:40,487 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:22:40,505 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-04-13 08:22:40,505 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:22:40,509 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:40,592 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 143 proven. 38 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-04-13 08:22:40,592 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:40,592 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12] total 16 [2018-04-13 08:22:40,593 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-13 08:22:40,593 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-13 08:22:40,593 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=196, Unknown=0, NotChecked=0, Total=240 [2018-04-13 08:22:40,594 INFO L87 Difference]: Start difference. First operand 105 states and 112 transitions. Second operand 16 states. [2018-04-13 08:22:40,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:40,774 INFO L93 Difference]: Finished difference Result 105 states and 109 transitions. [2018-04-13 08:22:40,774 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-13 08:22:40,775 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 83 [2018-04-13 08:22:40,775 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:40,776 INFO L225 Difference]: With dead ends: 105 [2018-04-13 08:22:40,776 INFO L226 Difference]: Without dead ends: 99 [2018-04-13 08:22:40,776 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 75 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 81 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=79, Invalid=341, Unknown=0, NotChecked=0, Total=420 [2018-04-13 08:22:40,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-04-13 08:22:40,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2018-04-13 08:22:40,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-04-13 08:22:40,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 103 transitions. [2018-04-13 08:22:40,784 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 103 transitions. Word has length 83 [2018-04-13 08:22:40,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:40,785 INFO L459 AbstractCegarLoop]: Abstraction has 99 states and 103 transitions. [2018-04-13 08:22:40,785 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-13 08:22:40,785 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 103 transitions. [2018-04-13 08:22:40,786 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-04-13 08:22:40,786 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:40,786 INFO L355 BasicCegarLoop]: trace histogram [11, 9, 9, 8, 8, 8, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:40,786 INFO L408 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:40,786 INFO L82 PathProgramCache]: Analyzing trace with hash 1376831888, now seen corresponding path program 4 times [2018-04-13 08:22:40,786 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:40,786 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:40,793 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:40,793 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:22:40,793 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:40,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:40,806 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:40,866 INFO L134 CoverageAnalysis]: Checked inductivity of 258 backedges. 185 proven. 10 refuted. 0 times theorem prover too weak. 63 trivial. 0 not checked. [2018-04-13 08:22:40,866 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:40,866 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:40,866 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:22:40,881 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:22:40,882 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:22:40,885 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:40,996 INFO L134 CoverageAnalysis]: Checked inductivity of 258 backedges. 186 proven. 14 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-04-13 08:22:40,996 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:40,997 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 11] total 17 [2018-04-13 08:22:40,997 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-04-13 08:22:40,997 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-04-13 08:22:40,998 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=223, Unknown=0, NotChecked=0, Total=272 [2018-04-13 08:22:40,998 INFO L87 Difference]: Start difference. First operand 99 states and 103 transitions. Second operand 17 states. [2018-04-13 08:22:41,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:41,267 INFO L93 Difference]: Finished difference Result 149 states and 152 transitions. [2018-04-13 08:22:41,267 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-04-13 08:22:41,268 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 89 [2018-04-13 08:22:41,268 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:41,269 INFO L225 Difference]: With dead ends: 149 [2018-04-13 08:22:41,269 INFO L226 Difference]: Without dead ends: 140 [2018-04-13 08:22:41,269 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 84 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 152 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=139, Invalid=673, Unknown=0, NotChecked=0, Total=812 [2018-04-13 08:22:41,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-04-13 08:22:41,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 135. [2018-04-13 08:22:41,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-04-13 08:22:41,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 138 transitions. [2018-04-13 08:22:41,273 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 138 transitions. Word has length 89 [2018-04-13 08:22:41,274 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:41,274 INFO L459 AbstractCegarLoop]: Abstraction has 135 states and 138 transitions. [2018-04-13 08:22:41,274 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-04-13 08:22:41,274 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 138 transitions. [2018-04-13 08:22:41,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2018-04-13 08:22:41,275 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:41,275 INFO L355 BasicCegarLoop]: trace histogram [16, 13, 13, 12, 12, 12, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:41,275 INFO L408 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:41,276 INFO L82 PathProgramCache]: Analyzing trace with hash -2114920591, now seen corresponding path program 5 times [2018-04-13 08:22:41,276 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:41,276 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:41,276 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:41,277 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:22:41,277 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:41,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:41,291 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:41,445 INFO L134 CoverageAnalysis]: Checked inductivity of 573 backedges. 257 proven. 52 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-04-13 08:22:41,445 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:41,445 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:41,446 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:22:41,474 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2018-04-13 08:22:41,474 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:22:41,480 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:41,588 INFO L134 CoverageAnalysis]: Checked inductivity of 573 backedges. 409 proven. 24 refuted. 0 times theorem prover too weak. 140 trivial. 0 not checked. [2018-04-13 08:22:41,589 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:41,589 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 10] total 18 [2018-04-13 08:22:41,589 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-04-13 08:22:41,590 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-04-13 08:22:41,590 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=252, Unknown=0, NotChecked=0, Total=306 [2018-04-13 08:22:41,590 INFO L87 Difference]: Start difference. First operand 135 states and 138 transitions. Second operand 18 states. [2018-04-13 08:22:41,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:41,907 INFO L93 Difference]: Finished difference Result 152 states and 154 transitions. [2018-04-13 08:22:41,907 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-13 08:22:41,907 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 125 [2018-04-13 08:22:41,908 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:41,908 INFO L225 Difference]: With dead ends: 152 [2018-04-13 08:22:41,908 INFO L226 Difference]: Without dead ends: 146 [2018-04-13 08:22:41,909 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 120 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 125 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=151, Invalid=605, Unknown=0, NotChecked=0, Total=756 [2018-04-13 08:22:41,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-04-13 08:22:41,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 141. [2018-04-13 08:22:41,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-04-13 08:22:41,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 143 transitions. [2018-04-13 08:22:41,911 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 143 transitions. Word has length 125 [2018-04-13 08:22:41,911 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:41,911 INFO L459 AbstractCegarLoop]: Abstraction has 141 states and 143 transitions. [2018-04-13 08:22:41,911 INFO L460 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-04-13 08:22:41,912 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 143 transitions. [2018-04-13 08:22:41,913 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-04-13 08:22:41,913 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:41,913 INFO L355 BasicCegarLoop]: trace histogram [18, 15, 15, 14, 14, 14, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:41,913 INFO L408 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:41,913 INFO L82 PathProgramCache]: Analyzing trace with hash -936202175, now seen corresponding path program 6 times [2018-04-13 08:22:41,913 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:41,913 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:41,914 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:41,914 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:22:41,914 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:41,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:41,925 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:42,097 INFO L134 CoverageAnalysis]: Checked inductivity of 743 backedges. 345 proven. 80 refuted. 0 times theorem prover too weak. 318 trivial. 0 not checked. [2018-04-13 08:22:42,097 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:42,097 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:42,098 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:22:42,120 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2018-04-13 08:22:42,120 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:22:42,125 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:42,334 INFO L134 CoverageAnalysis]: Checked inductivity of 743 backedges. 388 proven. 229 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-04-13 08:22:42,335 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:42,335 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 17] total 26 [2018-04-13 08:22:42,335 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-04-13 08:22:42,335 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-04-13 08:22:42,335 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=559, Unknown=0, NotChecked=0, Total=650 [2018-04-13 08:22:42,335 INFO L87 Difference]: Start difference. First operand 141 states and 143 transitions. Second operand 26 states. [2018-04-13 08:22:43,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:43,006 INFO L93 Difference]: Finished difference Result 202 states and 206 transitions. [2018-04-13 08:22:43,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-04-13 08:22:43,006 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 137 [2018-04-13 08:22:43,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:43,007 INFO L225 Difference]: With dead ends: 202 [2018-04-13 08:22:43,007 INFO L226 Difference]: Without dead ends: 202 [2018-04-13 08:22:43,008 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 170 GetRequests, 122 SyntacticMatches, 1 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 499 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=426, Invalid=1926, Unknown=0, NotChecked=0, Total=2352 [2018-04-13 08:22:43,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202 states. [2018-04-13 08:22:43,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202 to 189. [2018-04-13 08:22:43,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 189 states. [2018-04-13 08:22:43,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 193 transitions. [2018-04-13 08:22:43,011 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 193 transitions. Word has length 137 [2018-04-13 08:22:43,011 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:43,011 INFO L459 AbstractCegarLoop]: Abstraction has 189 states and 193 transitions. [2018-04-13 08:22:43,011 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-04-13 08:22:43,011 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 193 transitions. [2018-04-13 08:22:43,012 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2018-04-13 08:22:43,012 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:43,012 INFO L355 BasicCegarLoop]: trace histogram [24, 20, 20, 19, 19, 19, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:43,012 INFO L408 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:43,013 INFO L82 PathProgramCache]: Analyzing trace with hash -1943695766, now seen corresponding path program 7 times [2018-04-13 08:22:43,013 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:43,013 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:43,013 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:43,013 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:22:43,013 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:43,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:43,025 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:43,100 INFO L134 CoverageAnalysis]: Checked inductivity of 1354 backedges. 905 proven. 44 refuted. 0 times theorem prover too weak. 405 trivial. 0 not checked. [2018-04-13 08:22:43,100 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:43,101 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:43,101 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:43,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:43,128 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:43,369 INFO L134 CoverageAnalysis]: Checked inductivity of 1354 backedges. 694 proven. 52 refuted. 0 times theorem prover too weak. 608 trivial. 0 not checked. [2018-04-13 08:22:43,369 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:43,369 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 15] total 25 [2018-04-13 08:22:43,370 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-04-13 08:22:43,370 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-04-13 08:22:43,370 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=95, Invalid=505, Unknown=0, NotChecked=0, Total=600 [2018-04-13 08:22:43,370 INFO L87 Difference]: Start difference. First operand 189 states and 193 transitions. Second operand 25 states. [2018-04-13 08:22:43,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:43,834 INFO L93 Difference]: Finished difference Result 251 states and 254 transitions. [2018-04-13 08:22:43,834 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-04-13 08:22:43,834 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 179 [2018-04-13 08:22:43,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:43,835 INFO L225 Difference]: With dead ends: 251 [2018-04-13 08:22:43,835 INFO L226 Difference]: Without dead ends: 242 [2018-04-13 08:22:43,836 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 213 GetRequests, 172 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 412 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=265, Invalid=1541, Unknown=0, NotChecked=0, Total=1806 [2018-04-13 08:22:43,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states. [2018-04-13 08:22:43,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 237. [2018-04-13 08:22:43,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 237 states. [2018-04-13 08:22:43,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 237 states to 237 states and 240 transitions. [2018-04-13 08:22:43,840 INFO L78 Accepts]: Start accepts. Automaton has 237 states and 240 transitions. Word has length 179 [2018-04-13 08:22:43,840 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:43,840 INFO L459 AbstractCegarLoop]: Abstraction has 237 states and 240 transitions. [2018-04-13 08:22:43,840 INFO L460 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-04-13 08:22:43,840 INFO L276 IsEmpty]: Start isEmpty. Operand 237 states and 240 transitions. [2018-04-13 08:22:43,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 228 [2018-04-13 08:22:43,841 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:43,841 INFO L355 BasicCegarLoop]: trace histogram [31, 26, 26, 25, 25, 25, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:43,841 INFO L408 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:43,842 INFO L82 PathProgramCache]: Analyzing trace with hash -431804325, now seen corresponding path program 8 times [2018-04-13 08:22:43,842 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:43,842 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:43,842 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:43,842 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:43,842 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:43,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:43,856 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:44,002 INFO L134 CoverageAnalysis]: Checked inductivity of 2305 backedges. 1423 proven. 70 refuted. 0 times theorem prover too weak. 812 trivial. 0 not checked. [2018-04-13 08:22:44,003 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:44,003 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:44,003 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:22:44,053 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:22:44,053 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:22:44,064 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:44,072 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:22:44,072 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:22:44,075 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:22:44,076 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:22:44,430 INFO L134 CoverageAnalysis]: Checked inductivity of 2305 backedges. 835 proven. 92 refuted. 0 times theorem prover too weak. 1378 trivial. 0 not checked. [2018-04-13 08:22:44,430 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:44,430 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13] total 26 [2018-04-13 08:22:44,430 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-04-13 08:22:44,431 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-04-13 08:22:44,431 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=543, Unknown=0, NotChecked=0, Total=650 [2018-04-13 08:22:44,431 INFO L87 Difference]: Start difference. First operand 237 states and 240 transitions. Second operand 26 states. [2018-04-13 08:22:45,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:45,281 INFO L93 Difference]: Finished difference Result 302 states and 304 transitions. [2018-04-13 08:22:45,281 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-04-13 08:22:45,281 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 227 [2018-04-13 08:22:45,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:45,282 INFO L225 Difference]: With dead ends: 302 [2018-04-13 08:22:45,282 INFO L226 Difference]: Without dead ends: 293 [2018-04-13 08:22:45,284 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 291 GetRequests, 214 SyntacticMatches, 9 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1754 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=892, Invalid=3938, Unknown=0, NotChecked=0, Total=4830 [2018-04-13 08:22:45,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 293 states. [2018-04-13 08:22:45,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 293 to 285. [2018-04-13 08:22:45,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 285 states. [2018-04-13 08:22:45,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 285 states to 285 states and 287 transitions. [2018-04-13 08:22:45,289 INFO L78 Accepts]: Start accepts. Automaton has 285 states and 287 transitions. Word has length 227 [2018-04-13 08:22:45,290 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:45,290 INFO L459 AbstractCegarLoop]: Abstraction has 285 states and 287 transitions. [2018-04-13 08:22:45,290 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-04-13 08:22:45,290 INFO L276 IsEmpty]: Start isEmpty. Operand 285 states and 287 transitions. [2018-04-13 08:22:45,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 282 [2018-04-13 08:22:45,295 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:45,295 INFO L355 BasicCegarLoop]: trace histogram [39, 33, 33, 32, 32, 32, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:45,295 INFO L408 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:45,295 INFO L82 PathProgramCache]: Analyzing trace with hash -1397576748, now seen corresponding path program 9 times [2018-04-13 08:22:45,295 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:45,295 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:45,296 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:45,296 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:22:45,296 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:45,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:45,324 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:45,470 INFO L134 CoverageAnalysis]: Checked inductivity of 3710 backedges. 2089 proven. 102 refuted. 0 times theorem prover too weak. 1519 trivial. 0 not checked. [2018-04-13 08:22:45,470 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:45,470 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:45,470 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:22:45,510 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-04-13 08:22:45,510 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:22:45,524 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:45,526 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:22:45,526 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:22:45,532 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:22:45,532 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:22:46,057 INFO L134 CoverageAnalysis]: Checked inductivity of 3710 backedges. 1130 proven. 114 refuted. 0 times theorem prover too weak. 2466 trivial. 0 not checked. [2018-04-13 08:22:46,057 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:46,057 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 12] total 27 [2018-04-13 08:22:46,057 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-04-13 08:22:46,058 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-04-13 08:22:46,058 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=119, Invalid=583, Unknown=0, NotChecked=0, Total=702 [2018-04-13 08:22:46,058 INFO L87 Difference]: Start difference. First operand 285 states and 287 transitions. Second operand 27 states. [2018-04-13 08:22:46,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:46,588 INFO L93 Difference]: Finished difference Result 309 states and 311 transitions. [2018-04-13 08:22:46,588 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-04-13 08:22:46,588 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 281 [2018-04-13 08:22:46,589 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:46,589 INFO L225 Difference]: With dead ends: 309 [2018-04-13 08:22:46,589 INFO L226 Difference]: Without dead ends: 303 [2018-04-13 08:22:46,590 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 320 GetRequests, 266 SyntacticMatches, 11 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 528 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=376, Invalid=1604, Unknown=0, NotChecked=0, Total=1980 [2018-04-13 08:22:46,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states. [2018-04-13 08:22:46,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 297. [2018-04-13 08:22:46,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 297 states. [2018-04-13 08:22:46,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 297 states to 297 states and 299 transitions. [2018-04-13 08:22:46,594 INFO L78 Accepts]: Start accepts. Automaton has 297 states and 299 transitions. Word has length 281 [2018-04-13 08:22:46,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:46,595 INFO L459 AbstractCegarLoop]: Abstraction has 297 states and 299 transitions. [2018-04-13 08:22:46,595 INFO L460 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-04-13 08:22:46,595 INFO L276 IsEmpty]: Start isEmpty. Operand 297 states and 299 transitions. [2018-04-13 08:22:46,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 294 [2018-04-13 08:22:46,596 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:46,597 INFO L355 BasicCegarLoop]: trace histogram [41, 35, 35, 34, 34, 34, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:46,597 INFO L408 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:46,597 INFO L82 PathProgramCache]: Analyzing trace with hash 1751572516, now seen corresponding path program 10 times [2018-04-13 08:22:46,597 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:46,597 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:46,598 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:46,598 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:22:46,598 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:46,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:46,625 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:46,863 INFO L134 CoverageAnalysis]: Checked inductivity of 4132 backedges. 1344 proven. 154 refuted. 0 times theorem prover too weak. 2634 trivial. 0 not checked. [2018-04-13 08:22:46,864 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:46,864 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:46,864 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:22:46,942 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:22:46,942 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:22:46,948 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:46,950 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:22:46,951 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:22:46,953 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:22:46,953 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:22:47,422 INFO L134 CoverageAnalysis]: Checked inductivity of 4132 backedges. 1344 proven. 154 refuted. 0 times theorem prover too weak. 2634 trivial. 0 not checked. [2018-04-13 08:22:47,423 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:47,455 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13] total 24 [2018-04-13 08:22:47,455 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-04-13 08:22:47,455 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-04-13 08:22:47,456 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=152, Invalid=448, Unknown=0, NotChecked=0, Total=600 [2018-04-13 08:22:47,456 INFO L87 Difference]: Start difference. First operand 297 states and 299 transitions. Second operand 25 states. [2018-04-13 08:22:47,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:47,673 INFO L93 Difference]: Finished difference Result 321 states and 325 transitions. [2018-04-13 08:22:47,673 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-04-13 08:22:47,673 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 293 [2018-04-13 08:22:47,674 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:47,675 INFO L225 Difference]: With dead ends: 321 [2018-04-13 08:22:47,675 INFO L226 Difference]: Without dead ends: 321 [2018-04-13 08:22:47,675 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 313 GetRequests, 270 SyntacticMatches, 12 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 219 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=299, Invalid=757, Unknown=0, NotChecked=0, Total=1056 [2018-04-13 08:22:47,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2018-04-13 08:22:47,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 303. [2018-04-13 08:22:47,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 303 states. [2018-04-13 08:22:47,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 306 transitions. [2018-04-13 08:22:47,679 INFO L78 Accepts]: Start accepts. Automaton has 303 states and 306 transitions. Word has length 293 [2018-04-13 08:22:47,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:47,680 INFO L459 AbstractCegarLoop]: Abstraction has 303 states and 306 transitions. [2018-04-13 08:22:47,680 INFO L460 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-04-13 08:22:47,680 INFO L276 IsEmpty]: Start isEmpty. Operand 303 states and 306 transitions. [2018-04-13 08:22:47,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 300 [2018-04-13 08:22:47,680 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:47,681 INFO L355 BasicCegarLoop]: trace histogram [42, 36, 36, 35, 35, 35, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:47,681 INFO L408 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:47,681 INFO L82 PathProgramCache]: Analyzing trace with hash -1671183124, now seen corresponding path program 11 times [2018-04-13 08:22:47,681 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:47,681 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:47,681 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:47,682 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:22:47,682 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:47,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:47,698 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:47,922 INFO L134 CoverageAnalysis]: Checked inductivity of 4352 backedges. 1695 proven. 137 refuted. 0 times theorem prover too weak. 2520 trivial. 0 not checked. [2018-04-13 08:22:47,922 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:47,922 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:47,923 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:22:48,156 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 11 check-sat command(s) [2018-04-13 08:22:48,156 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:22:48,189 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:48,471 INFO L134 CoverageAnalysis]: Checked inductivity of 4352 backedges. 1651 proven. 736 refuted. 0 times theorem prover too weak. 1965 trivial. 0 not checked. [2018-04-13 08:22:48,471 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:48,471 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 24] total 34 [2018-04-13 08:22:48,472 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-04-13 08:22:48,472 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-04-13 08:22:48,473 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=219, Invalid=903, Unknown=0, NotChecked=0, Total=1122 [2018-04-13 08:22:48,473 INFO L87 Difference]: Start difference. First operand 303 states and 306 transitions. Second operand 34 states. [2018-04-13 08:22:48,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:48,971 INFO L93 Difference]: Finished difference Result 377 states and 381 transitions. [2018-04-13 08:22:48,971 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-04-13 08:22:48,971 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 299 [2018-04-13 08:22:48,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:48,973 INFO L225 Difference]: With dead ends: 377 [2018-04-13 08:22:48,973 INFO L226 Difference]: Without dead ends: 377 [2018-04-13 08:22:48,974 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 336 GetRequests, 286 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 480 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=558, Invalid=2094, Unknown=0, NotChecked=0, Total=2652 [2018-04-13 08:22:48,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 377 states. [2018-04-13 08:22:48,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 377 to 369. [2018-04-13 08:22:48,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 369 states. [2018-04-13 08:22:48,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 369 states to 369 states and 373 transitions. [2018-04-13 08:22:48,981 INFO L78 Accepts]: Start accepts. Automaton has 369 states and 373 transitions. Word has length 299 [2018-04-13 08:22:48,981 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:48,981 INFO L459 AbstractCegarLoop]: Abstraction has 369 states and 373 transitions. [2018-04-13 08:22:48,981 INFO L460 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-04-13 08:22:48,982 INFO L276 IsEmpty]: Start isEmpty. Operand 369 states and 373 transitions. [2018-04-13 08:22:48,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 354 [2018-04-13 08:22:48,983 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:48,983 INFO L355 BasicCegarLoop]: trace histogram [50, 43, 43, 42, 42, 42, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:48,983 INFO L408 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:48,984 INFO L82 PathProgramCache]: Analyzing trace with hash 1483763557, now seen corresponding path program 12 times [2018-04-13 08:22:48,984 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:48,984 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:48,984 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:48,984 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:22:48,985 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:49,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:49,012 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:49,351 INFO L134 CoverageAnalysis]: Checked inductivity of 6223 backedges. 3357 proven. 140 refuted. 0 times theorem prover too weak. 2726 trivial. 0 not checked. [2018-04-13 08:22:49,352 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:49,352 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:49,352 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:22:49,399 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-04-13 08:22:49,399 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:22:49,408 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:49,410 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:22:49,410 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:22:49,413 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:22:49,413 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:22:49,969 INFO L134 CoverageAnalysis]: Checked inductivity of 6223 backedges. 1901 proven. 170 refuted. 0 times theorem prover too weak. 4152 trivial. 0 not checked. [2018-04-13 08:22:49,969 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:49,969 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 15] total 32 [2018-04-13 08:22:49,970 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-13 08:22:49,970 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-13 08:22:49,970 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=160, Invalid=832, Unknown=0, NotChecked=0, Total=992 [2018-04-13 08:22:49,970 INFO L87 Difference]: Start difference. First operand 369 states and 373 transitions. Second operand 32 states. [2018-04-13 08:22:51,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:51,418 INFO L93 Difference]: Finished difference Result 446 states and 449 transitions. [2018-04-13 08:22:51,418 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-04-13 08:22:51,418 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 353 [2018-04-13 08:22:51,418 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:51,420 INFO L225 Difference]: With dead ends: 446 [2018-04-13 08:22:51,420 INFO L226 Difference]: Without dead ends: 437 [2018-04-13 08:22:51,422 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 439 GetRequests, 336 SyntacticMatches, 13 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3306 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1497, Invalid=6875, Unknown=0, NotChecked=0, Total=8372 [2018-04-13 08:22:51,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 437 states. [2018-04-13 08:22:51,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 437 to 429. [2018-04-13 08:22:51,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 429 states. [2018-04-13 08:22:51,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 429 states to 429 states and 432 transitions. [2018-04-13 08:22:51,429 INFO L78 Accepts]: Start accepts. Automaton has 429 states and 432 transitions. Word has length 353 [2018-04-13 08:22:51,429 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:51,429 INFO L459 AbstractCegarLoop]: Abstraction has 429 states and 432 transitions. [2018-04-13 08:22:51,429 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-13 08:22:51,429 INFO L276 IsEmpty]: Start isEmpty. Operand 429 states and 432 transitions. [2018-04-13 08:22:51,431 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 420 [2018-04-13 08:22:51,432 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:51,432 INFO L355 BasicCegarLoop]: trace histogram [60, 52, 52, 51, 51, 51, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:51,432 INFO L408 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:51,432 INFO L82 PathProgramCache]: Analyzing trace with hash -983766034, now seen corresponding path program 13 times [2018-04-13 08:22:51,432 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:51,432 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:51,433 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:51,433 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:22:51,433 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:51,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:51,465 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:51,827 INFO L134 CoverageAnalysis]: Checked inductivity of 9062 backedges. 4485 proven. 184 refuted. 0 times theorem prover too weak. 4393 trivial. 0 not checked. [2018-04-13 08:22:51,828 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:51,828 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:51,828 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:51,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:51,899 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:52,202 INFO L134 CoverageAnalysis]: Checked inductivity of 9062 backedges. 4485 proven. 184 refuted. 0 times theorem prover too weak. 4393 trivial. 0 not checked. [2018-04-13 08:22:52,202 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:52,202 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 29 [2018-04-13 08:22:52,203 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-04-13 08:22:52,203 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-04-13 08:22:52,203 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=208, Invalid=604, Unknown=0, NotChecked=0, Total=812 [2018-04-13 08:22:52,203 INFO L87 Difference]: Start difference. First operand 429 states and 432 transitions. Second operand 29 states. [2018-04-13 08:22:52,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:52,536 INFO L93 Difference]: Finished difference Result 457 states and 460 transitions. [2018-04-13 08:22:52,536 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-04-13 08:22:52,537 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 419 [2018-04-13 08:22:52,537 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:52,538 INFO L225 Difference]: With dead ends: 457 [2018-04-13 08:22:52,538 INFO L226 Difference]: Without dead ends: 451 [2018-04-13 08:22:52,538 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 445 GetRequests, 411 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 379 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=306, Invalid=954, Unknown=0, NotChecked=0, Total=1260 [2018-04-13 08:22:52,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451 states. [2018-04-13 08:22:52,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451 to 439. [2018-04-13 08:22:52,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 439 states. [2018-04-13 08:22:52,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 439 states to 439 states and 442 transitions. [2018-04-13 08:22:52,543 INFO L78 Accepts]: Start accepts. Automaton has 439 states and 442 transitions. Word has length 419 [2018-04-13 08:22:52,543 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:52,543 INFO L459 AbstractCegarLoop]: Abstraction has 439 states and 442 transitions. [2018-04-13 08:22:52,543 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-04-13 08:22:52,543 INFO L276 IsEmpty]: Start isEmpty. Operand 439 states and 442 transitions. [2018-04-13 08:22:52,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 426 [2018-04-13 08:22:52,545 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:52,545 INFO L355 BasicCegarLoop]: trace histogram [61, 53, 53, 52, 52, 52, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:52,545 INFO L408 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:52,545 INFO L82 PathProgramCache]: Analyzing trace with hash 1494870518, now seen corresponding path program 14 times [2018-04-13 08:22:52,545 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:52,545 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:52,546 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:52,546 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:22:52,546 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:52,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:52,568 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:52,928 INFO L134 CoverageAnalysis]: Checked inductivity of 9388 backedges. 2440 proven. 200 refuted. 0 times theorem prover too weak. 6748 trivial. 0 not checked. [2018-04-13 08:22:52,928 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:52,928 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:52,929 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:22:52,960 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:22:52,960 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:22:52,967 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:52,968 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:22:52,969 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:22:52,971 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:22:52,971 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:22:53,562 INFO L134 CoverageAnalysis]: Checked inductivity of 9388 backedges. 2440 proven. 216 refuted. 0 times theorem prover too weak. 6732 trivial. 0 not checked. [2018-04-13 08:22:53,562 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:53,562 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 16] total 27 [2018-04-13 08:22:53,563 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-04-13 08:22:53,563 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-04-13 08:22:53,563 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=175, Invalid=581, Unknown=0, NotChecked=0, Total=756 [2018-04-13 08:22:53,563 INFO L87 Difference]: Start difference. First operand 439 states and 442 transitions. Second operand 28 states. [2018-04-13 08:22:54,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:54,257 INFO L93 Difference]: Finished difference Result 543 states and 550 transitions. [2018-04-13 08:22:54,257 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-04-13 08:22:54,257 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 425 [2018-04-13 08:22:54,258 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:54,260 INFO L225 Difference]: With dead ends: 543 [2018-04-13 08:22:54,260 INFO L226 Difference]: Without dead ends: 543 [2018-04-13 08:22:54,261 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 461 GetRequests, 395 SyntacticMatches, 17 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 868 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=620, Invalid=1930, Unknown=0, NotChecked=0, Total=2550 [2018-04-13 08:22:54,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 543 states. [2018-04-13 08:22:54,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 543 to 513. [2018-04-13 08:22:54,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 513 states. [2018-04-13 08:22:54,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 513 states to 513 states and 518 transitions. [2018-04-13 08:22:54,269 INFO L78 Accepts]: Start accepts. Automaton has 513 states and 518 transitions. Word has length 425 [2018-04-13 08:22:54,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:54,269 INFO L459 AbstractCegarLoop]: Abstraction has 513 states and 518 transitions. [2018-04-13 08:22:54,269 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-04-13 08:22:54,269 INFO L276 IsEmpty]: Start isEmpty. Operand 513 states and 518 transitions. [2018-04-13 08:22:54,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 504 [2018-04-13 08:22:54,272 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:54,272 INFO L355 BasicCegarLoop]: trace histogram [73, 64, 64, 63, 63, 63, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:54,273 INFO L408 AbstractCegarLoop]: === Iteration 23 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:54,273 INFO L82 PathProgramCache]: Analyzing trace with hash 1416226959, now seen corresponding path program 15 times [2018-04-13 08:22:54,273 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:54,273 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:54,274 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:54,274 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:22:54,274 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:54,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:54,310 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:54,809 INFO L134 CoverageAnalysis]: Checked inductivity of 13599 backedges. 3599 proven. 310 refuted. 0 times theorem prover too weak. 9690 trivial. 0 not checked. [2018-04-13 08:22:54,809 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:54,809 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:54,810 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:22:54,874 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-04-13 08:22:54,874 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:22:54,888 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:55,360 INFO L134 CoverageAnalysis]: Checked inductivity of 13599 backedges. 6029 proven. 814 refuted. 0 times theorem prover too weak. 6756 trivial. 0 not checked. [2018-04-13 08:22:55,360 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:55,361 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 28] total 42 [2018-04-13 08:22:55,361 INFO L442 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-04-13 08:22:55,361 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-04-13 08:22:55,361 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=242, Invalid=1480, Unknown=0, NotChecked=0, Total=1722 [2018-04-13 08:22:55,362 INFO L87 Difference]: Start difference. First operand 513 states and 518 transitions. Second operand 42 states. [2018-04-13 08:22:56,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:56,640 INFO L93 Difference]: Finished difference Result 713 states and 723 transitions. [2018-04-13 08:22:56,641 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-04-13 08:22:56,641 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 503 [2018-04-13 08:22:56,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:56,643 INFO L225 Difference]: With dead ends: 713 [2018-04-13 08:22:56,643 INFO L226 Difference]: Without dead ends: 713 [2018-04-13 08:22:56,645 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 556 GetRequests, 477 SyntacticMatches, 1 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1569 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1186, Invalid=5134, Unknown=0, NotChecked=0, Total=6320 [2018-04-13 08:22:56,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 713 states. [2018-04-13 08:22:56,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 713 to 615. [2018-04-13 08:22:56,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 615 states. [2018-04-13 08:22:56,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 615 states to 615 states and 623 transitions. [2018-04-13 08:22:56,655 INFO L78 Accepts]: Start accepts. Automaton has 615 states and 623 transitions. Word has length 503 [2018-04-13 08:22:56,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:56,656 INFO L459 AbstractCegarLoop]: Abstraction has 615 states and 623 transitions. [2018-04-13 08:22:56,656 INFO L460 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-04-13 08:22:56,656 INFO L276 IsEmpty]: Start isEmpty. Operand 615 states and 623 transitions. [2018-04-13 08:22:56,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 516 [2018-04-13 08:22:56,659 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:56,659 INFO L355 BasicCegarLoop]: trace histogram [75, 66, 66, 65, 65, 65, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:56,659 INFO L408 AbstractCegarLoop]: === Iteration 24 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:56,659 INFO L82 PathProgramCache]: Analyzing trace with hash 874224735, now seen corresponding path program 16 times [2018-04-13 08:22:56,660 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:56,660 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:56,660 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:56,660 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:22:56,660 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:56,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:56,699 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:57,383 INFO L134 CoverageAnalysis]: Checked inductivity of 14405 backedges. 4005 proven. 374 refuted. 0 times theorem prover too weak. 10026 trivial. 0 not checked. [2018-04-13 08:22:57,383 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:57,383 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:57,383 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:22:57,423 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:22:57,423 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:22:57,433 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:22:57,850 INFO L134 CoverageAnalysis]: Checked inductivity of 14405 backedges. 5956 proven. 1459 refuted. 0 times theorem prover too weak. 6990 trivial. 0 not checked. [2018-04-13 08:22:57,850 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:22:57,879 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 29] total 44 [2018-04-13 08:22:57,880 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-04-13 08:22:57,880 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-04-13 08:22:57,881 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=268, Invalid=1624, Unknown=0, NotChecked=0, Total=1892 [2018-04-13 08:22:57,881 INFO L87 Difference]: Start difference. First operand 615 states and 623 transitions. Second operand 44 states. [2018-04-13 08:22:59,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:22:59,310 INFO L93 Difference]: Finished difference Result 727 states and 738 transitions. [2018-04-13 08:22:59,310 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-04-13 08:22:59,310 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 515 [2018-04-13 08:22:59,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:22:59,312 INFO L225 Difference]: With dead ends: 727 [2018-04-13 08:22:59,312 INFO L226 Difference]: Without dead ends: 727 [2018-04-13 08:22:59,314 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 573 GetRequests, 488 SyntacticMatches, 1 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1774 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1342, Invalid=5968, Unknown=0, NotChecked=0, Total=7310 [2018-04-13 08:22:59,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 727 states. [2018-04-13 08:22:59,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 727 to 552. [2018-04-13 08:22:59,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 552 states. [2018-04-13 08:22:59,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 560 transitions. [2018-04-13 08:22:59,322 INFO L78 Accepts]: Start accepts. Automaton has 552 states and 560 transitions. Word has length 515 [2018-04-13 08:22:59,323 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:22:59,323 INFO L459 AbstractCegarLoop]: Abstraction has 552 states and 560 transitions. [2018-04-13 08:22:59,323 INFO L460 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-04-13 08:22:59,323 INFO L276 IsEmpty]: Start isEmpty. Operand 552 states and 560 transitions. [2018-04-13 08:22:59,326 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 528 [2018-04-13 08:22:59,326 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:22:59,326 INFO L355 BasicCegarLoop]: trace histogram [77, 68, 68, 67, 67, 67, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:22:59,326 INFO L408 AbstractCegarLoop]: === Iteration 25 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:22:59,327 INFO L82 PathProgramCache]: Analyzing trace with hash -637722385, now seen corresponding path program 17 times [2018-04-13 08:22:59,327 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:22:59,327 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:22:59,327 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:59,327 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:22:59,328 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:22:59,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:22:59,365 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:22:59,698 INFO L134 CoverageAnalysis]: Checked inductivity of 15235 backedges. 4423 proven. 276 refuted. 0 times theorem prover too weak. 10536 trivial. 0 not checked. [2018-04-13 08:22:59,698 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:22:59,698 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:22:59,699 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:23:00,285 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 23 check-sat command(s) [2018-04-13 08:23:00,285 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:23:00,348 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:00,685 INFO L134 CoverageAnalysis]: Checked inductivity of 15235 backedges. 9268 proven. 1161 refuted. 0 times theorem prover too weak. 4806 trivial. 0 not checked. [2018-04-13 08:23:00,686 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:00,686 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 26] total 41 [2018-04-13 08:23:00,686 INFO L442 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-04-13 08:23:00,686 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-04-13 08:23:00,687 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=248, Invalid=1392, Unknown=0, NotChecked=0, Total=1640 [2018-04-13 08:23:00,687 INFO L87 Difference]: Start difference. First operand 552 states and 560 transitions. Second operand 41 states. [2018-04-13 08:23:01,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:01,814 INFO L93 Difference]: Finished difference Result 729 states and 743 transitions. [2018-04-13 08:23:01,815 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-04-13 08:23:01,815 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 527 [2018-04-13 08:23:01,815 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:01,817 INFO L225 Difference]: With dead ends: 729 [2018-04-13 08:23:01,817 INFO L226 Difference]: Without dead ends: 729 [2018-04-13 08:23:01,817 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 571 GetRequests, 504 SyntacticMatches, 1 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1407 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=645, Invalid=3911, Unknown=0, NotChecked=0, Total=4556 [2018-04-13 08:23:01,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 729 states. [2018-04-13 08:23:01,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 729 to 639. [2018-04-13 08:23:01,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 639 states. [2018-04-13 08:23:01,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 639 states to 639 states and 651 transitions. [2018-04-13 08:23:01,832 INFO L78 Accepts]: Start accepts. Automaton has 639 states and 651 transitions. Word has length 527 [2018-04-13 08:23:01,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:01,832 INFO L459 AbstractCegarLoop]: Abstraction has 639 states and 651 transitions. [2018-04-13 08:23:01,832 INFO L460 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-04-13 08:23:01,833 INFO L276 IsEmpty]: Start isEmpty. Operand 639 states and 651 transitions. [2018-04-13 08:23:01,837 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 594 [2018-04-13 08:23:01,838 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:01,838 INFO L355 BasicCegarLoop]: trace histogram [87, 77, 77, 76, 76, 76, 11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:01,838 INFO L408 AbstractCegarLoop]: === Iteration 26 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:01,838 INFO L82 PathProgramCache]: Analyzing trace with hash 1350141368, now seen corresponding path program 18 times [2018-04-13 08:23:01,838 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:01,839 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:01,839 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:01,839 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:23:01,839 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:01,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:01,885 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:02,448 INFO L134 CoverageAnalysis]: Checked inductivity of 19534 backedges. 9017 proven. 290 refuted. 0 times theorem prover too weak. 10227 trivial. 0 not checked. [2018-04-13 08:23:02,448 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:02,448 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:02,449 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:23:02,582 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2018-04-13 08:23:02,582 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:23:02,603 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:02,605 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:23:02,606 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:23:02,609 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:23:02,609 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:23:03,866 INFO L134 CoverageAnalysis]: Checked inductivity of 19534 backedges. 5134 proven. 334 refuted. 0 times theorem prover too weak. 14066 trivial. 0 not checked. [2018-04-13 08:23:03,866 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:03,866 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 18] total 41 [2018-04-13 08:23:03,867 INFO L442 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-04-13 08:23:03,867 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-04-13 08:23:03,867 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=262, Invalid=1378, Unknown=0, NotChecked=0, Total=1640 [2018-04-13 08:23:03,867 INFO L87 Difference]: Start difference. First operand 639 states and 651 transitions. Second operand 41 states. [2018-04-13 08:23:05,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:05,756 INFO L93 Difference]: Finished difference Result 730 states and 738 transitions. [2018-04-13 08:23:05,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2018-04-13 08:23:05,756 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 593 [2018-04-13 08:23:05,757 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:05,758 INFO L225 Difference]: With dead ends: 730 [2018-04-13 08:23:05,758 INFO L226 Difference]: Without dead ends: 643 [2018-04-13 08:23:05,760 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 713 GetRequests, 570 SyntacticMatches, 19 SemanticMatches, 124 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6670 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=2717, Invalid=13033, Unknown=0, NotChecked=0, Total=15750 [2018-04-13 08:23:05,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 643 states. [2018-04-13 08:23:05,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 643 to 630. [2018-04-13 08:23:05,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 630 states. [2018-04-13 08:23:05,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 630 states to 630 states and 635 transitions. [2018-04-13 08:23:05,770 INFO L78 Accepts]: Start accepts. Automaton has 630 states and 635 transitions. Word has length 593 [2018-04-13 08:23:05,771 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:05,771 INFO L459 AbstractCegarLoop]: Abstraction has 630 states and 635 transitions. [2018-04-13 08:23:05,771 INFO L460 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-04-13 08:23:05,771 INFO L276 IsEmpty]: Start isEmpty. Operand 630 states and 635 transitions. [2018-04-13 08:23:05,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 678 [2018-04-13 08:23:05,776 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:05,776 INFO L355 BasicCegarLoop]: trace histogram [100, 89, 89, 88, 88, 88, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:05,776 INFO L408 AbstractCegarLoop]: === Iteration 27 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:05,776 INFO L82 PathProgramCache]: Analyzing trace with hash -1742682151, now seen corresponding path program 19 times [2018-04-13 08:23:05,776 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:05,777 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:05,777 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:05,777 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:23:05,777 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:05,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:05,823 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:06,293 INFO L134 CoverageAnalysis]: Checked inductivity of 25993 backedges. 14286 proven. 1218 refuted. 0 times theorem prover too weak. 10489 trivial. 0 not checked. [2018-04-13 08:23:06,294 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:06,294 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:06,294 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:23:06,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:06,364 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:06,961 INFO L134 CoverageAnalysis]: Checked inductivity of 25993 backedges. 14315 proven. 1189 refuted. 0 times theorem prover too weak. 10489 trivial. 0 not checked. [2018-04-13 08:23:06,961 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:06,961 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 29] total 53 [2018-04-13 08:23:06,962 INFO L442 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-04-13 08:23:06,962 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-04-13 08:23:06,963 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=512, Invalid=2244, Unknown=0, NotChecked=0, Total=2756 [2018-04-13 08:23:06,963 INFO L87 Difference]: Start difference. First operand 630 states and 635 transitions. Second operand 53 states. [2018-04-13 08:23:08,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:08,015 INFO L93 Difference]: Finished difference Result 651 states and 655 transitions. [2018-04-13 08:23:08,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-04-13 08:23:08,015 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 677 [2018-04-13 08:23:08,016 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:08,018 INFO L225 Difference]: With dead ends: 651 [2018-04-13 08:23:08,018 INFO L226 Difference]: Without dead ends: 645 [2018-04-13 08:23:08,031 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 741 GetRequests, 656 SyntacticMatches, 0 SemanticMatches, 85 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1910 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1539, Invalid=5943, Unknown=0, NotChecked=0, Total=7482 [2018-04-13 08:23:08,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 645 states. [2018-04-13 08:23:08,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 645 to 636. [2018-04-13 08:23:08,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 636 states. [2018-04-13 08:23:08,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 636 states to 636 states and 640 transitions. [2018-04-13 08:23:08,040 INFO L78 Accepts]: Start accepts. Automaton has 636 states and 640 transitions. Word has length 677 [2018-04-13 08:23:08,041 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:08,041 INFO L459 AbstractCegarLoop]: Abstraction has 636 states and 640 transitions. [2018-04-13 08:23:08,041 INFO L460 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-04-13 08:23:08,041 INFO L276 IsEmpty]: Start isEmpty. Operand 636 states and 640 transitions. [2018-04-13 08:23:08,057 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 684 [2018-04-13 08:23:08,057 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:08,058 INFO L355 BasicCegarLoop]: trace histogram [101, 90, 90, 89, 89, 89, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:08,058 INFO L408 AbstractCegarLoop]: === Iteration 28 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:08,058 INFO L82 PathProgramCache]: Analyzing trace with hash -661149279, now seen corresponding path program 20 times [2018-04-13 08:23:08,058 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:08,058 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:08,059 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:08,059 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:23:08,059 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:08,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:08,094 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:08,577 INFO L134 CoverageAnalysis]: Checked inductivity of 26547 backedges. 6149 proven. 444 refuted. 0 times theorem prover too weak. 19954 trivial. 0 not checked. [2018-04-13 08:23:08,578 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:08,578 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:08,578 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:23:08,617 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:23:08,617 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:23:08,626 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:08,630 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:23:08,630 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:23:08,641 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:23:08,641 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:23:09,466 INFO L134 CoverageAnalysis]: Checked inductivity of 26547 backedges. 6149 proven. 444 refuted. 0 times theorem prover too weak. 19954 trivial. 0 not checked. [2018-04-13 08:23:09,467 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:09,467 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 18] total 19 [2018-04-13 08:23:09,467 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-04-13 08:23:09,467 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-04-13 08:23:09,468 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=147, Invalid=233, Unknown=0, NotChecked=0, Total=380 [2018-04-13 08:23:09,468 INFO L87 Difference]: Start difference. First operand 636 states and 640 transitions. Second operand 20 states. [2018-04-13 08:23:09,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:09,744 INFO L93 Difference]: Finished difference Result 663 states and 669 transitions. [2018-04-13 08:23:09,745 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-04-13 08:23:09,745 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 683 [2018-04-13 08:23:09,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:09,747 INFO L225 Difference]: With dead ends: 663 [2018-04-13 08:23:09,747 INFO L226 Difference]: Without dead ends: 663 [2018-04-13 08:23:09,748 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 713 GetRequests, 658 SyntacticMatches, 24 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 171 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=382, Invalid=674, Unknown=0, NotChecked=0, Total=1056 [2018-04-13 08:23:09,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 663 states. [2018-04-13 08:23:09,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 663 to 642. [2018-04-13 08:23:09,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 642 states. [2018-04-13 08:23:09,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 642 states to 642 states and 647 transitions. [2018-04-13 08:23:09,756 INFO L78 Accepts]: Start accepts. Automaton has 642 states and 647 transitions. Word has length 683 [2018-04-13 08:23:09,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:09,757 INFO L459 AbstractCegarLoop]: Abstraction has 642 states and 647 transitions. [2018-04-13 08:23:09,757 INFO L460 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-04-13 08:23:09,757 INFO L276 IsEmpty]: Start isEmpty. Operand 642 states and 647 transitions. [2018-04-13 08:23:09,762 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 690 [2018-04-13 08:23:09,762 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:09,762 INFO L355 BasicCegarLoop]: trace histogram [102, 91, 91, 90, 90, 90, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:09,762 INFO L408 AbstractCegarLoop]: === Iteration 29 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:09,762 INFO L82 PathProgramCache]: Analyzing trace with hash -1048265559, now seen corresponding path program 21 times [2018-04-13 08:23:09,763 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:09,763 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:09,763 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:09,763 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:23:09,763 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:09,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:09,810 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:10,367 INFO L134 CoverageAnalysis]: Checked inductivity of 27107 backedges. 7115 proven. 412 refuted. 0 times theorem prover too weak. 19580 trivial. 0 not checked. [2018-04-13 08:23:10,367 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:10,367 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:10,367 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:23:10,414 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 14 check-sat command(s) [2018-04-13 08:23:10,414 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:23:10,426 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:11,250 INFO L134 CoverageAnalysis]: Checked inductivity of 27107 backedges. 11329 proven. 1408 refuted. 0 times theorem prover too weak. 14370 trivial. 0 not checked. [2018-04-13 08:23:11,250 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:11,251 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 33] total 58 [2018-04-13 08:23:11,251 INFO L442 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-04-13 08:23:11,251 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-04-13 08:23:11,251 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=559, Invalid=2747, Unknown=0, NotChecked=0, Total=3306 [2018-04-13 08:23:11,252 INFO L87 Difference]: Start difference. First operand 642 states and 647 transitions. Second operand 58 states. [2018-04-13 08:23:12,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:12,412 INFO L93 Difference]: Finished difference Result 745 states and 750 transitions. [2018-04-13 08:23:12,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-04-13 08:23:12,412 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 689 [2018-04-13 08:23:12,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:12,414 INFO L225 Difference]: With dead ends: 745 [2018-04-13 08:23:12,414 INFO L226 Difference]: Without dead ends: 745 [2018-04-13 08:23:12,415 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 756 GetRequests, 662 SyntacticMatches, 0 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2022 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1661, Invalid=7459, Unknown=0, NotChecked=0, Total=9120 [2018-04-13 08:23:12,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 745 states. [2018-04-13 08:23:12,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 745 to 738. [2018-04-13 08:23:12,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 738 states. [2018-04-13 08:23:12,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 738 states to 738 states and 743 transitions. [2018-04-13 08:23:12,424 INFO L78 Accepts]: Start accepts. Automaton has 738 states and 743 transitions. Word has length 689 [2018-04-13 08:23:12,425 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:12,425 INFO L459 AbstractCegarLoop]: Abstraction has 738 states and 743 transitions. [2018-04-13 08:23:12,425 INFO L460 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-04-13 08:23:12,425 INFO L276 IsEmpty]: Start isEmpty. Operand 738 states and 743 transitions. [2018-04-13 08:23:12,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 780 [2018-04-13 08:23:12,430 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:12,431 INFO L355 BasicCegarLoop]: trace histogram [116, 104, 104, 103, 103, 103, 13, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:12,431 INFO L408 AbstractCegarLoop]: === Iteration 30 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:12,431 INFO L82 PathProgramCache]: Analyzing trace with hash 861490130, now seen corresponding path program 22 times [2018-04-13 08:23:12,431 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:12,431 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:12,432 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:12,432 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:23:12,432 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:12,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:12,486 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:13,215 INFO L134 CoverageAnalysis]: Checked inductivity of 35278 backedges. 7728 proven. 520 refuted. 0 times theorem prover too weak. 27030 trivial. 0 not checked. [2018-04-13 08:23:13,215 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:13,215 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:13,216 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:23:13,585 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:23:13,585 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:23:13,606 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:13,608 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:23:13,608 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:23:13,611 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:23:13,611 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:23:15,281 INFO L134 CoverageAnalysis]: Checked inductivity of 35278 backedges. 7728 proven. 520 refuted. 0 times theorem prover too weak. 27030 trivial. 0 not checked. [2018-04-13 08:23:15,281 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:15,281 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19] total 36 [2018-04-13 08:23:15,282 INFO L442 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-04-13 08:23:15,282 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-04-13 08:23:15,282 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=371, Invalid=961, Unknown=0, NotChecked=0, Total=1332 [2018-04-13 08:23:15,282 INFO L87 Difference]: Start difference. First operand 738 states and 743 transitions. Second operand 37 states. [2018-04-13 08:23:15,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:15,695 INFO L93 Difference]: Finished difference Result 752 states and 758 transitions. [2018-04-13 08:23:15,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-04-13 08:23:15,695 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 779 [2018-04-13 08:23:15,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:15,697 INFO L225 Difference]: With dead ends: 752 [2018-04-13 08:23:15,697 INFO L226 Difference]: Without dead ends: 752 [2018-04-13 08:23:15,697 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 811 GetRequests, 738 SyntacticMatches, 24 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 555 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=755, Invalid=1795, Unknown=0, NotChecked=0, Total=2550 [2018-04-13 08:23:15,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 752 states. [2018-04-13 08:23:15,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 752 to 744. [2018-04-13 08:23:15,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 744 states. [2018-04-13 08:23:15,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 744 states to 744 states and 750 transitions. [2018-04-13 08:23:15,703 INFO L78 Accepts]: Start accepts. Automaton has 744 states and 750 transitions. Word has length 779 [2018-04-13 08:23:15,704 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:15,704 INFO L459 AbstractCegarLoop]: Abstraction has 744 states and 750 transitions. [2018-04-13 08:23:15,704 INFO L460 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-04-13 08:23:15,704 INFO L276 IsEmpty]: Start isEmpty. Operand 744 states and 750 transitions. [2018-04-13 08:23:15,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 786 [2018-04-13 08:23:15,708 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:15,708 INFO L355 BasicCegarLoop]: trace histogram [117, 105, 105, 104, 104, 104, 13, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:15,708 INFO L408 AbstractCegarLoop]: === Iteration 31 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:15,708 INFO L82 PathProgramCache]: Analyzing trace with hash 420886042, now seen corresponding path program 23 times [2018-04-13 08:23:15,709 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:15,709 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:15,709 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:15,709 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:23:15,709 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:15,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:15,749 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:16,296 INFO L134 CoverageAnalysis]: Checked inductivity of 35924 backedges. 8853 proven. 485 refuted. 0 times theorem prover too weak. 26586 trivial. 0 not checked. [2018-04-13 08:23:16,296 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:16,296 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:16,297 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:23:17,297 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2018-04-13 08:23:17,298 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:23:17,359 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:18,584 INFO L134 CoverageAnalysis]: Checked inductivity of 35924 backedges. 12804 proven. 6711 refuted. 0 times theorem prover too weak. 16409 trivial. 0 not checked. [2018-04-13 08:23:18,585 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:18,585 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 49] total 66 [2018-04-13 08:23:18,585 INFO L442 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-04-13 08:23:18,586 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-04-13 08:23:18,586 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=565, Invalid=3725, Unknown=0, NotChecked=0, Total=4290 [2018-04-13 08:23:18,586 INFO L87 Difference]: Start difference. First operand 744 states and 750 transitions. Second operand 66 states. [2018-04-13 08:23:20,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:20,184 INFO L93 Difference]: Finished difference Result 952 states and 963 transitions. [2018-04-13 08:23:20,184 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-04-13 08:23:20,184 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 785 [2018-04-13 08:23:20,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:20,187 INFO L225 Difference]: With dead ends: 952 [2018-04-13 08:23:20,187 INFO L226 Difference]: Without dead ends: 952 [2018-04-13 08:23:20,188 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 852 GetRequests, 752 SyntacticMatches, 0 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2278 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=1409, Invalid=8893, Unknown=0, NotChecked=0, Total=10302 [2018-04-13 08:23:20,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 952 states. [2018-04-13 08:23:20,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 952 to 942. [2018-04-13 08:23:20,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 942 states. [2018-04-13 08:23:20,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 942 states to 942 states and 953 transitions. [2018-04-13 08:23:20,196 INFO L78 Accepts]: Start accepts. Automaton has 942 states and 953 transitions. Word has length 785 [2018-04-13 08:23:20,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:20,196 INFO L459 AbstractCegarLoop]: Abstraction has 942 states and 953 transitions. [2018-04-13 08:23:20,196 INFO L460 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-04-13 08:23:20,196 INFO L276 IsEmpty]: Start isEmpty. Operand 942 states and 953 transitions. [2018-04-13 08:23:20,200 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 870 [2018-04-13 08:23:20,200 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:20,201 INFO L355 BasicCegarLoop]: trace histogram [130, 117, 117, 116, 116, 116, 14, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:20,201 INFO L408 AbstractCegarLoop]: === Iteration 32 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:20,201 INFO L82 PathProgramCache]: Analyzing trace with hash -782704581, now seen corresponding path program 24 times [2018-04-13 08:23:20,201 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:20,201 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:20,201 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:20,202 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:23:20,202 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:20,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:20,235 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:20,810 INFO L134 CoverageAnalysis]: Checked inductivity of 44527 backedges. 18991 proven. 4099 refuted. 0 times theorem prover too weak. 21437 trivial. 0 not checked. [2018-04-13 08:23:20,810 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:20,810 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:20,811 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:23:20,994 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2018-04-13 08:23:20,994 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:23:21,034 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:21,071 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:23:21,071 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:23:21,077 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:23:21,078 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:23:22,821 INFO L134 CoverageAnalysis]: Checked inductivity of 44527 backedges. 9965 proven. 4736 refuted. 0 times theorem prover too weak. 29826 trivial. 0 not checked. [2018-04-13 08:23:22,821 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:22,821 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 27] total 58 [2018-04-13 08:23:22,822 INFO L442 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-04-13 08:23:22,822 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-04-13 08:23:22,822 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=447, Invalid=2859, Unknown=0, NotChecked=0, Total=3306 [2018-04-13 08:23:22,822 INFO L87 Difference]: Start difference. First operand 942 states and 953 transitions. Second operand 58 states. [2018-04-13 08:23:25,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:25,686 INFO L93 Difference]: Finished difference Result 1060 states and 1072 transitions. [2018-04-13 08:23:25,686 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2018-04-13 08:23:25,686 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 869 [2018-04-13 08:23:25,687 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:25,688 INFO L225 Difference]: With dead ends: 1060 [2018-04-13 08:23:25,688 INFO L226 Difference]: Without dead ends: 1048 [2018-04-13 08:23:25,689 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 977 GetRequests, 821 SyntacticMatches, 24 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6707 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=2375, Invalid=15447, Unknown=0, NotChecked=0, Total=17822 [2018-04-13 08:23:25,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1048 states. [2018-04-13 08:23:25,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1048 to 924. [2018-04-13 08:23:25,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 924 states. [2018-04-13 08:23:25,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 930 transitions. [2018-04-13 08:23:25,697 INFO L78 Accepts]: Start accepts. Automaton has 924 states and 930 transitions. Word has length 869 [2018-04-13 08:23:25,697 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:25,698 INFO L459 AbstractCegarLoop]: Abstraction has 924 states and 930 transitions. [2018-04-13 08:23:25,698 INFO L460 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-04-13 08:23:25,698 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 930 transitions. [2018-04-13 08:23:25,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 966 [2018-04-13 08:23:25,703 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:25,703 INFO L355 BasicCegarLoop]: trace histogram [145, 131, 131, 130, 130, 130, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:25,703 INFO L408 AbstractCegarLoop]: === Iteration 33 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:25,703 INFO L82 PathProgramCache]: Analyzing trace with hash -422042836, now seen corresponding path program 25 times [2018-04-13 08:23:25,703 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:25,703 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:25,704 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:25,704 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:23:25,704 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:25,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:25,738 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:26,417 INFO L134 CoverageAnalysis]: Checked inductivity of 55660 backedges. 21823 proven. 5232 refuted. 0 times theorem prover too weak. 28605 trivial. 0 not checked. [2018-04-13 08:23:26,418 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:26,418 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:26,418 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:23:26,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:26,471 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:27,218 INFO L134 CoverageAnalysis]: Checked inductivity of 55660 backedges. 29333 proven. 3221 refuted. 0 times theorem prover too weak. 23106 trivial. 0 not checked. [2018-04-13 08:23:27,218 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:27,218 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 33] total 59 [2018-04-13 08:23:27,219 INFO L442 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-04-13 08:23:27,219 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-04-13 08:23:27,219 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=608, Invalid=2814, Unknown=0, NotChecked=0, Total=3422 [2018-04-13 08:23:27,219 INFO L87 Difference]: Start difference. First operand 924 states and 930 transitions. Second operand 59 states. [2018-04-13 08:23:28,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:28,092 INFO L93 Difference]: Finished difference Result 948 states and 952 transitions. [2018-04-13 08:23:28,092 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-04-13 08:23:28,092 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 965 [2018-04-13 08:23:28,092 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:28,094 INFO L225 Difference]: With dead ends: 948 [2018-04-13 08:23:28,094 INFO L226 Difference]: Without dead ends: 939 [2018-04-13 08:23:28,095 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1037 GetRequests, 942 SyntacticMatches, 0 SemanticMatches, 95 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2475 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1902, Invalid=7410, Unknown=0, NotChecked=0, Total=9312 [2018-04-13 08:23:28,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 939 states. [2018-04-13 08:23:28,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 939 to 930. [2018-04-13 08:23:28,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 930 states. [2018-04-13 08:23:28,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 930 states to 930 states and 934 transitions. [2018-04-13 08:23:28,100 INFO L78 Accepts]: Start accepts. Automaton has 930 states and 934 transitions. Word has length 965 [2018-04-13 08:23:28,101 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:28,101 INFO L459 AbstractCegarLoop]: Abstraction has 930 states and 934 transitions. [2018-04-13 08:23:28,101 INFO L460 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-04-13 08:23:28,101 INFO L276 IsEmpty]: Start isEmpty. Operand 930 states and 934 transitions. [2018-04-13 08:23:28,106 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 978 [2018-04-13 08:23:28,106 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:28,106 INFO L355 BasicCegarLoop]: trace histogram [147, 133, 133, 132, 132, 132, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:28,106 INFO L408 AbstractCegarLoop]: === Iteration 34 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:28,106 INFO L82 PathProgramCache]: Analyzing trace with hash -1407253252, now seen corresponding path program 26 times [2018-04-13 08:23:28,106 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:28,107 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:28,107 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:28,107 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:23:28,107 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:28,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:28,146 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:28,832 INFO L134 CoverageAnalysis]: Checked inductivity of 57290 backedges. 23738 proven. 4377 refuted. 0 times theorem prover too weak. 29175 trivial. 0 not checked. [2018-04-13 08:23:28,832 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:28,832 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:28,832 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:23:28,886 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:23:28,886 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:23:28,896 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:29,606 INFO L134 CoverageAnalysis]: Checked inductivity of 57290 backedges. 23767 proven. 4348 refuted. 0 times theorem prover too weak. 29175 trivial. 0 not checked. [2018-04-13 08:23:29,606 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:29,606 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 35] total 62 [2018-04-13 08:23:29,607 INFO L442 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-04-13 08:23:29,607 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-04-13 08:23:29,607 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=662, Invalid=3120, Unknown=0, NotChecked=0, Total=3782 [2018-04-13 08:23:29,608 INFO L87 Difference]: Start difference. First operand 930 states and 934 transitions. Second operand 62 states. [2018-04-13 08:23:30,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:30,645 INFO L93 Difference]: Finished difference Result 958 states and 962 transitions. [2018-04-13 08:23:30,645 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-04-13 08:23:30,645 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 977 [2018-04-13 08:23:30,646 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:30,647 INFO L225 Difference]: With dead ends: 958 [2018-04-13 08:23:30,647 INFO L226 Difference]: Without dead ends: 952 [2018-04-13 08:23:30,648 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1054 GetRequests, 954 SyntacticMatches, 0 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2786 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=2100, Invalid=8202, Unknown=0, NotChecked=0, Total=10302 [2018-04-13 08:23:30,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 952 states. [2018-04-13 08:23:30,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 952 to 940. [2018-04-13 08:23:30,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 940 states. [2018-04-13 08:23:30,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 940 states to 940 states and 944 transitions. [2018-04-13 08:23:30,653 INFO L78 Accepts]: Start accepts. Automaton has 940 states and 944 transitions. Word has length 977 [2018-04-13 08:23:30,653 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:30,653 INFO L459 AbstractCegarLoop]: Abstraction has 940 states and 944 transitions. [2018-04-13 08:23:30,653 INFO L460 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-04-13 08:23:30,653 INFO L276 IsEmpty]: Start isEmpty. Operand 940 states and 944 transitions. [2018-04-13 08:23:30,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 984 [2018-04-13 08:23:30,658 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:30,658 INFO L355 BasicCegarLoop]: trace histogram [148, 134, 134, 133, 133, 133, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:30,658 INFO L408 AbstractCegarLoop]: === Iteration 35 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:30,658 INFO L82 PathProgramCache]: Analyzing trace with hash -642834300, now seen corresponding path program 27 times [2018-04-13 08:23:30,658 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:30,658 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:30,659 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:30,659 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:23:30,659 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:30,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:30,704 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:31,340 INFO L134 CoverageAnalysis]: Checked inductivity of 58114 backedges. 10906 proven. 602 refuted. 0 times theorem prover too weak. 46606 trivial. 0 not checked. [2018-04-13 08:23:31,341 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:31,341 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:31,341 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:23:31,391 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-04-13 08:23:31,391 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:23:31,405 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:31,407 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:23:31,407 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:23:31,409 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:23:31,409 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:23:32,641 INFO L134 CoverageAnalysis]: Checked inductivity of 58114 backedges. 10906 proven. 602 refuted. 0 times theorem prover too weak. 46606 trivial. 0 not checked. [2018-04-13 08:23:32,641 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:32,642 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 20] total 21 [2018-04-13 08:23:32,642 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-04-13 08:23:32,642 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-04-13 08:23:32,642 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=182, Invalid=280, Unknown=0, NotChecked=0, Total=462 [2018-04-13 08:23:32,642 INFO L87 Difference]: Start difference. First operand 940 states and 944 transitions. Second operand 22 states. [2018-04-13 08:23:32,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:32,949 INFO L93 Difference]: Finished difference Result 951 states and 955 transitions. [2018-04-13 08:23:32,949 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-04-13 08:23:32,949 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 983 [2018-04-13 08:23:32,950 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:32,951 INFO L225 Difference]: With dead ends: 951 [2018-04-13 08:23:32,951 INFO L226 Difference]: Without dead ends: 951 [2018-04-13 08:23:32,952 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1017 GetRequests, 952 SyntacticMatches, 30 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 217 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=483, Invalid=849, Unknown=0, NotChecked=0, Total=1332 [2018-04-13 08:23:32,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 951 states. [2018-04-13 08:23:32,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 951 to 942. [2018-04-13 08:23:32,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 942 states. [2018-04-13 08:23:32,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 942 states to 942 states and 946 transitions. [2018-04-13 08:23:32,957 INFO L78 Accepts]: Start accepts. Automaton has 942 states and 946 transitions. Word has length 983 [2018-04-13 08:23:32,957 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:32,957 INFO L459 AbstractCegarLoop]: Abstraction has 942 states and 946 transitions. [2018-04-13 08:23:32,957 INFO L460 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-04-13 08:23:32,957 INFO L276 IsEmpty]: Start isEmpty. Operand 942 states and 946 transitions. [2018-04-13 08:23:32,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 990 [2018-04-13 08:23:32,964 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:32,965 INFO L355 BasicCegarLoop]: trace histogram [149, 135, 135, 134, 134, 134, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:32,965 INFO L408 AbstractCegarLoop]: === Iteration 36 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:32,965 INFO L82 PathProgramCache]: Analyzing trace with hash 1557282124, now seen corresponding path program 28 times [2018-04-13 08:23:32,965 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:32,965 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:32,966 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:32,966 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:23:32,966 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:33,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:33,003 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:33,670 INFO L134 CoverageAnalysis]: Checked inductivity of 58944 backedges. 11648 proven. 690 refuted. 0 times theorem prover too weak. 46606 trivial. 0 not checked. [2018-04-13 08:23:33,670 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:33,670 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:33,671 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:23:34,108 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:23:34,108 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:23:34,129 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:34,132 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:23:34,132 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:23:34,134 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:23:34,134 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:23:34,187 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-04-13 08:23:34,187 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:23:34,190 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-13 08:23:34,190 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:19, output treesize:14 [2018-04-13 08:23:36,439 INFO L134 CoverageAnalysis]: Checked inductivity of 58944 backedges. 25212 proven. 7364 refuted. 0 times theorem prover too weak. 26368 trivial. 0 not checked. [2018-04-13 08:23:36,440 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:36,440 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 47] total 65 [2018-04-13 08:23:36,440 INFO L442 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-04-13 08:23:36,440 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-04-13 08:23:36,441 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=478, Invalid=3812, Unknown=0, NotChecked=0, Total=4290 [2018-04-13 08:23:36,441 INFO L87 Difference]: Start difference. First operand 942 states and 946 transitions. Second operand 66 states. [2018-04-13 08:23:40,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:40,229 INFO L93 Difference]: Finished difference Result 971 states and 977 transitions. [2018-04-13 08:23:40,229 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-04-13 08:23:40,229 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 989 [2018-04-13 08:23:40,230 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:40,231 INFO L225 Difference]: With dead ends: 971 [2018-04-13 08:23:40,231 INFO L226 Difference]: Without dead ends: 971 [2018-04-13 08:23:40,232 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1077 GetRequests, 917 SyntacticMatches, 29 SemanticMatches, 131 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4585 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=1997, Invalid=15559, Unknown=0, NotChecked=0, Total=17556 [2018-04-13 08:23:40,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 971 states. [2018-04-13 08:23:40,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 971 to 948. [2018-04-13 08:23:40,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 948 states. [2018-04-13 08:23:40,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 948 states to 948 states and 953 transitions. [2018-04-13 08:23:40,237 INFO L78 Accepts]: Start accepts. Automaton has 948 states and 953 transitions. Word has length 989 [2018-04-13 08:23:40,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:40,238 INFO L459 AbstractCegarLoop]: Abstraction has 948 states and 953 transitions. [2018-04-13 08:23:40,238 INFO L460 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-04-13 08:23:40,238 INFO L276 IsEmpty]: Start isEmpty. Operand 948 states and 953 transitions. [2018-04-13 08:23:40,242 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 996 [2018-04-13 08:23:40,242 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:40,243 INFO L355 BasicCegarLoop]: trace histogram [150, 136, 136, 135, 135, 135, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:40,243 INFO L408 AbstractCegarLoop]: === Iteration 37 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:40,243 INFO L82 PathProgramCache]: Analyzing trace with hash 1007592468, now seen corresponding path program 29 times [2018-04-13 08:23:40,243 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:40,243 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:40,243 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:40,243 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:23:40,244 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:40,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:40,281 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:41,070 INFO L134 CoverageAnalysis]: Checked inductivity of 59780 backedges. 12390 proven. 784 refuted. 0 times theorem prover too weak. 46606 trivial. 0 not checked. [2018-04-13 08:23:41,070 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:41,070 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:41,071 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:23:42,482 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 31 check-sat command(s) [2018-04-13 08:23:42,483 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:23:42,631 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:43,465 INFO L134 CoverageAnalysis]: Checked inductivity of 59780 backedges. 15400 proven. 5549 refuted. 0 times theorem prover too weak. 38831 trivial. 0 not checked. [2018-04-13 08:23:43,465 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:43,465 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 40] total 60 [2018-04-13 08:23:43,466 INFO L442 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-04-13 08:23:43,466 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-04-13 08:23:43,466 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=485, Invalid=3055, Unknown=0, NotChecked=0, Total=3540 [2018-04-13 08:23:43,467 INFO L87 Difference]: Start difference. First operand 948 states and 953 transitions. Second operand 60 states. [2018-04-13 08:23:45,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:45,493 INFO L93 Difference]: Finished difference Result 1087 states and 1094 transitions. [2018-04-13 08:23:45,494 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-04-13 08:23:45,494 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 995 [2018-04-13 08:23:45,494 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:45,496 INFO L225 Difference]: With dead ends: 1087 [2018-04-13 08:23:45,496 INFO L226 Difference]: Without dead ends: 1087 [2018-04-13 08:23:45,496 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1072 GetRequests, 957 SyntacticMatches, 1 SemanticMatches, 114 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3418 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=2212, Invalid=11128, Unknown=0, NotChecked=0, Total=13340 [2018-04-13 08:23:45,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1087 states. [2018-04-13 08:23:45,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1087 to 1068. [2018-04-13 08:23:45,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1068 states. [2018-04-13 08:23:45,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1068 states to 1068 states and 1075 transitions. [2018-04-13 08:23:45,502 INFO L78 Accepts]: Start accepts. Automaton has 1068 states and 1075 transitions. Word has length 995 [2018-04-13 08:23:45,502 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:45,502 INFO L459 AbstractCegarLoop]: Abstraction has 1068 states and 1075 transitions. [2018-04-13 08:23:45,502 INFO L460 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-04-13 08:23:45,502 INFO L276 IsEmpty]: Start isEmpty. Operand 1068 states and 1075 transitions. [2018-04-13 08:23:45,507 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1104 [2018-04-13 08:23:45,507 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:45,508 INFO L355 BasicCegarLoop]: trace histogram [167, 152, 152, 151, 151, 151, 16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:45,508 INFO L408 AbstractCegarLoop]: === Iteration 38 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:45,508 INFO L82 PathProgramCache]: Analyzing trace with hash 1753664213, now seen corresponding path program 30 times [2018-04-13 08:23:45,508 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:45,508 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:45,509 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:45,509 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:23:45,509 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:45,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:45,553 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:46,263 INFO L134 CoverageAnalysis]: Checked inductivity of 74449 backedges. 29764 proven. 5578 refuted. 0 times theorem prover too weak. 39107 trivial. 0 not checked. [2018-04-13 08:23:46,263 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:46,263 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:46,264 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:23:46,627 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 26 check-sat command(s) [2018-04-13 08:23:46,627 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:23:46,690 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:46,700 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:23:46,700 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:23:46,703 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:23:46,703 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:23:48,783 INFO L134 CoverageAnalysis]: Checked inductivity of 74449 backedges. 14759 proven. 724 refuted. 0 times theorem prover too weak. 58966 trivial. 0 not checked. [2018-04-13 08:23:48,783 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:48,784 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 23] total 60 [2018-04-13 08:23:48,784 INFO L442 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-04-13 08:23:48,784 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-04-13 08:23:48,785 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=3075, Unknown=0, NotChecked=0, Total=3540 [2018-04-13 08:23:48,785 INFO L87 Difference]: Start difference. First operand 1068 states and 1075 transitions. Second operand 60 states. [2018-04-13 08:23:51,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:51,268 INFO L93 Difference]: Finished difference Result 1201 states and 1208 transitions. [2018-04-13 08:23:51,301 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-04-13 08:23:51,301 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 1103 [2018-04-13 08:23:51,302 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:51,304 INFO L225 Difference]: With dead ends: 1201 [2018-04-13 08:23:51,304 INFO L226 Difference]: Without dead ends: 1192 [2018-04-13 08:23:51,305 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1217 GetRequests, 1054 SyntacticMatches, 29 SemanticMatches, 134 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6874 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=2465, Invalid=15895, Unknown=0, NotChecked=0, Total=18360 [2018-04-13 08:23:51,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1192 states. [2018-04-13 08:23:51,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1192 to 1176. [2018-04-13 08:23:51,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1176 states. [2018-04-13 08:23:51,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1176 states to 1176 states and 1182 transitions. [2018-04-13 08:23:51,311 INFO L78 Accepts]: Start accepts. Automaton has 1176 states and 1182 transitions. Word has length 1103 [2018-04-13 08:23:51,311 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:51,311 INFO L459 AbstractCegarLoop]: Abstraction has 1176 states and 1182 transitions. [2018-04-13 08:23:51,311 INFO L460 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-04-13 08:23:51,311 INFO L276 IsEmpty]: Start isEmpty. Operand 1176 states and 1182 transitions. [2018-04-13 08:23:51,317 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1218 [2018-04-13 08:23:51,317 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:51,318 INFO L355 BasicCegarLoop]: trace histogram [185, 169, 169, 168, 168, 168, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:51,318 INFO L408 AbstractCegarLoop]: === Iteration 39 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:51,318 INFO L82 PathProgramCache]: Analyzing trace with hash -230054690, now seen corresponding path program 31 times [2018-04-13 08:23:51,318 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:51,318 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:51,319 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:51,319 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:23:51,319 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:51,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:51,364 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:52,146 INFO L134 CoverageAnalysis]: Checked inductivity of 91768 backedges. 33976 proven. 6853 refuted. 0 times theorem prover too weak. 50939 trivial. 0 not checked. [2018-04-13 08:23:52,146 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:52,147 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:52,147 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:23:52,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:52,220 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:53,147 INFO L134 CoverageAnalysis]: Checked inductivity of 91768 backedges. 34005 proven. 6824 refuted. 0 times theorem prover too weak. 50939 trivial. 0 not checked. [2018-04-13 08:23:53,147 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:53,147 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 39] total 68 [2018-04-13 08:23:53,148 INFO L442 AbstractCegarLoop]: Interpolant automaton has 68 states [2018-04-13 08:23:53,148 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2018-04-13 08:23:53,148 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=782, Invalid=3774, Unknown=0, NotChecked=0, Total=4556 [2018-04-13 08:23:53,148 INFO L87 Difference]: Start difference. First operand 1176 states and 1182 transitions. Second operand 68 states. [2018-04-13 08:23:54,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:54,327 INFO L93 Difference]: Finished difference Result 1200 states and 1205 transitions. [2018-04-13 08:23:54,327 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-04-13 08:23:54,327 INFO L78 Accepts]: Start accepts. Automaton has 68 states. Word has length 1217 [2018-04-13 08:23:54,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:54,330 INFO L225 Difference]: With dead ends: 1200 [2018-04-13 08:23:54,330 INFO L226 Difference]: Without dead ends: 1194 [2018-04-13 08:23:54,330 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1301 GetRequests, 1191 SyntacticMatches, 0 SemanticMatches, 110 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3465 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=2529, Invalid=9903, Unknown=0, NotChecked=0, Total=12432 [2018-04-13 08:23:54,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1194 states. [2018-04-13 08:23:54,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1194 to 1182. [2018-04-13 08:23:54,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1182 states. [2018-04-13 08:23:54,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1182 states to 1182 states and 1187 transitions. [2018-04-13 08:23:54,336 INFO L78 Accepts]: Start accepts. Automaton has 1182 states and 1187 transitions. Word has length 1217 [2018-04-13 08:23:54,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:54,337 INFO L459 AbstractCegarLoop]: Abstraction has 1182 states and 1187 transitions. [2018-04-13 08:23:54,337 INFO L460 AbstractCegarLoop]: Interpolant automaton has 68 states. [2018-04-13 08:23:54,337 INFO L276 IsEmpty]: Start isEmpty. Operand 1182 states and 1187 transitions. [2018-04-13 08:23:54,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1224 [2018-04-13 08:23:54,343 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:54,344 INFO L355 BasicCegarLoop]: trace histogram [186, 170, 170, 169, 169, 169, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:54,344 INFO L408 AbstractCegarLoop]: === Iteration 40 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:54,344 INFO L82 PathProgramCache]: Analyzing trace with hash -929947930, now seen corresponding path program 32 times [2018-04-13 08:23:54,344 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:54,344 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:54,344 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:54,344 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:23:54,344 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:54,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:54,395 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:55,301 INFO L134 CoverageAnalysis]: Checked inductivity of 92812 backedges. 16704 proven. 884 refuted. 0 times theorem prover too weak. 75224 trivial. 0 not checked. [2018-04-13 08:23:55,301 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:55,302 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:55,302 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:23:55,372 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:23:55,372 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:23:55,385 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:55,387 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:23:55,387 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:23:55,389 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:23:55,389 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:23:57,089 INFO L134 CoverageAnalysis]: Checked inductivity of 92812 backedges. 16704 proven. 884 refuted. 0 times theorem prover too weak. 75224 trivial. 0 not checked. [2018-04-13 08:23:57,089 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:57,089 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 23] total 24 [2018-04-13 08:23:57,090 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-04-13 08:23:57,090 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-04-13 08:23:57,090 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=242, Invalid=358, Unknown=0, NotChecked=0, Total=600 [2018-04-13 08:23:57,090 INFO L87 Difference]: Start difference. First operand 1182 states and 1187 transitions. Second operand 25 states. [2018-04-13 08:23:57,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:23:57,476 INFO L93 Difference]: Finished difference Result 1212 states and 1219 transitions. [2018-04-13 08:23:57,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-04-13 08:23:57,477 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 1223 [2018-04-13 08:23:57,477 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:23:57,479 INFO L225 Difference]: With dead ends: 1212 [2018-04-13 08:23:57,479 INFO L226 Difference]: Without dead ends: 1212 [2018-04-13 08:23:57,479 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1263 GetRequests, 1188 SyntacticMatches, 34 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 286 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=657, Invalid=1149, Unknown=0, NotChecked=0, Total=1806 [2018-04-13 08:23:57,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1212 states. [2018-04-13 08:23:57,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1212 to 1188. [2018-04-13 08:23:57,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1188 states. [2018-04-13 08:23:57,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1188 states to 1188 states and 1194 transitions. [2018-04-13 08:23:57,485 INFO L78 Accepts]: Start accepts. Automaton has 1188 states and 1194 transitions. Word has length 1223 [2018-04-13 08:23:57,486 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:23:57,486 INFO L459 AbstractCegarLoop]: Abstraction has 1188 states and 1194 transitions. [2018-04-13 08:23:57,486 INFO L460 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-04-13 08:23:57,486 INFO L276 IsEmpty]: Start isEmpty. Operand 1188 states and 1194 transitions. [2018-04-13 08:23:57,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1230 [2018-04-13 08:23:57,493 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:23:57,493 INFO L355 BasicCegarLoop]: trace histogram [187, 171, 171, 170, 170, 170, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:23:57,493 INFO L408 AbstractCegarLoop]: === Iteration 41 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:23:57,493 INFO L82 PathProgramCache]: Analyzing trace with hash -920557010, now seen corresponding path program 33 times [2018-04-13 08:23:57,493 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:23:57,493 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:23:57,494 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:57,494 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:23:57,494 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:23:57,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:23:57,545 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:23:58,293 INFO L134 CoverageAnalysis]: Checked inductivity of 93862 backedges. 18585 proven. 837 refuted. 0 times theorem prover too weak. 74440 trivial. 0 not checked. [2018-04-13 08:23:58,293 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:23:58,294 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:23:58,294 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:23:58,429 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 19 check-sat command(s) [2018-04-13 08:23:58,429 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:23:58,446 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:23:59,723 INFO L134 CoverageAnalysis]: Checked inductivity of 93862 backedges. 31449 proven. 2758 refuted. 0 times theorem prover too weak. 59655 trivial. 0 not checked. [2018-04-13 08:23:59,723 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:23:59,723 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 43] total 78 [2018-04-13 08:23:59,724 INFO L442 AbstractCegarLoop]: Interpolant automaton has 78 states [2018-04-13 08:23:59,724 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2018-04-13 08:23:59,724 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=994, Invalid=5012, Unknown=0, NotChecked=0, Total=6006 [2018-04-13 08:23:59,724 INFO L87 Difference]: Start difference. First operand 1188 states and 1194 transitions. Second operand 78 states. [2018-04-13 08:24:01,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:24:01,518 INFO L93 Difference]: Finished difference Result 1324 states and 1330 transitions. [2018-04-13 08:24:01,518 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2018-04-13 08:24:01,518 INFO L78 Accepts]: Start accepts. Automaton has 78 states. Word has length 1229 [2018-04-13 08:24:01,519 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:24:01,523 INFO L225 Difference]: With dead ends: 1324 [2018-04-13 08:24:01,523 INFO L226 Difference]: Without dead ends: 1324 [2018-04-13 08:24:01,524 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1321 GetRequests, 1192 SyntacticMatches, 0 SemanticMatches, 129 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3927 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=2976, Invalid=14054, Unknown=0, NotChecked=0, Total=17030 [2018-04-13 08:24:01,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1324 states. [2018-04-13 08:24:01,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1324 to 1314. [2018-04-13 08:24:01,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1314 states. [2018-04-13 08:24:01,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1314 states to 1314 states and 1320 transitions. [2018-04-13 08:24:01,537 INFO L78 Accepts]: Start accepts. Automaton has 1314 states and 1320 transitions. Word has length 1229 [2018-04-13 08:24:01,538 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:24:01,538 INFO L459 AbstractCegarLoop]: Abstraction has 1314 states and 1320 transitions. [2018-04-13 08:24:01,538 INFO L460 AbstractCegarLoop]: Interpolant automaton has 78 states. [2018-04-13 08:24:01,538 INFO L276 IsEmpty]: Start isEmpty. Operand 1314 states and 1320 transitions. [2018-04-13 08:24:01,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1350 [2018-04-13 08:24:01,547 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:24:01,547 INFO L355 BasicCegarLoop]: trace histogram [206, 189, 189, 188, 188, 188, 18, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:24:01,547 INFO L408 AbstractCegarLoop]: === Iteration 42 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:24:01,547 INFO L82 PathProgramCache]: Analyzing trace with hash -616680001, now seen corresponding path program 34 times [2018-04-13 08:24:01,547 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:24:01,547 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:24:01,548 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:01,548 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:24:01,548 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:01,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:24:01,612 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:24:02,733 INFO L134 CoverageAnalysis]: Checked inductivity of 114363 backedges. 19703 proven. 990 refuted. 0 times theorem prover too weak. 93670 trivial. 0 not checked. [2018-04-13 08:24:02,734 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:24:02,734 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:24:02,734 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:24:03,899 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:24:03,899 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:24:03,919 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:24:03,921 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:24:03,921 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:24:03,923 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:24:03,923 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:24:06,344 INFO L134 CoverageAnalysis]: Checked inductivity of 114363 backedges. 19703 proven. 990 refuted. 0 times theorem prover too weak. 93670 trivial. 0 not checked. [2018-04-13 08:24:06,344 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:24:06,344 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 24] total 46 [2018-04-13 08:24:06,345 INFO L442 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-04-13 08:24:06,345 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-04-13 08:24:06,345 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=636, Invalid=1526, Unknown=0, NotChecked=0, Total=2162 [2018-04-13 08:24:06,345 INFO L87 Difference]: Start difference. First operand 1314 states and 1320 transitions. Second operand 47 states. [2018-04-13 08:24:06,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:24:06,972 INFO L93 Difference]: Finished difference Result 1331 states and 1338 transitions. [2018-04-13 08:24:06,972 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-04-13 08:24:06,972 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 1349 [2018-04-13 08:24:06,973 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:24:06,974 INFO L225 Difference]: With dead ends: 1331 [2018-04-13 08:24:06,975 INFO L226 Difference]: Without dead ends: 1331 [2018-04-13 08:24:06,975 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1391 GetRequests, 1293 SyntacticMatches, 34 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 945 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1300, Invalid=2990, Unknown=0, NotChecked=0, Total=4290 [2018-04-13 08:24:06,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1331 states. [2018-04-13 08:24:06,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1331 to 1320. [2018-04-13 08:24:06,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1320 states. [2018-04-13 08:24:06,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1320 states to 1320 states and 1327 transitions. [2018-04-13 08:24:06,982 INFO L78 Accepts]: Start accepts. Automaton has 1320 states and 1327 transitions. Word has length 1349 [2018-04-13 08:24:06,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:24:06,982 INFO L459 AbstractCegarLoop]: Abstraction has 1320 states and 1327 transitions. [2018-04-13 08:24:06,982 INFO L460 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-04-13 08:24:06,982 INFO L276 IsEmpty]: Start isEmpty. Operand 1320 states and 1327 transitions. [2018-04-13 08:24:06,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1356 [2018-04-13 08:24:06,990 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:24:06,991 INFO L355 BasicCegarLoop]: trace histogram [207, 190, 190, 189, 189, 189, 18, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:24:06,991 INFO L408 AbstractCegarLoop]: === Iteration 43 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:24:06,991 INFO L82 PathProgramCache]: Analyzing trace with hash -888325561, now seen corresponding path program 35 times [2018-04-13 08:24:06,991 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:24:06,991 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:24:06,992 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:06,992 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:24:06,992 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:07,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:24:07,054 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:24:07,892 INFO L134 CoverageAnalysis]: Checked inductivity of 115529 backedges. 21803 proven. 940 refuted. 0 times theorem prover too weak. 92786 trivial. 0 not checked. [2018-04-13 08:24:07,893 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:24:07,893 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:24:07,893 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:24:11,352 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 37 check-sat command(s) [2018-04-13 08:24:11,352 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:24:12,032 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:24:13,451 INFO L134 CoverageAnalysis]: Checked inductivity of 115529 backedges. 25975 proven. 9034 refuted. 0 times theorem prover too weak. 80520 trivial. 0 not checked. [2018-04-13 08:24:13,451 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:24:13,452 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 46] total 76 [2018-04-13 08:24:13,452 INFO L442 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-04-13 08:24:13,453 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-04-13 08:24:13,453 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=991, Invalid=4709, Unknown=0, NotChecked=0, Total=5700 [2018-04-13 08:24:13,453 INFO L87 Difference]: Start difference. First operand 1320 states and 1327 transitions. Second operand 76 states. [2018-04-13 08:24:15,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:24:15,097 INFO L93 Difference]: Finished difference Result 1591 states and 1603 transitions. [2018-04-13 08:24:15,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2018-04-13 08:24:15,097 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 1355 [2018-04-13 08:24:15,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:24:15,100 INFO L225 Difference]: With dead ends: 1591 [2018-04-13 08:24:15,100 INFO L226 Difference]: Without dead ends: 1591 [2018-04-13 08:24:15,101 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1445 GetRequests, 1322 SyntacticMatches, 0 SemanticMatches, 123 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3487 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2740, Invalid=12760, Unknown=0, NotChecked=0, Total=15500 [2018-04-13 08:24:15,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1591 states. [2018-04-13 08:24:15,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1591 to 1578. [2018-04-13 08:24:15,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1578 states. [2018-04-13 08:24:15,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 1590 transitions. [2018-04-13 08:24:15,109 INFO L78 Accepts]: Start accepts. Automaton has 1578 states and 1590 transitions. Word has length 1355 [2018-04-13 08:24:15,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:24:15,109 INFO L459 AbstractCegarLoop]: Abstraction has 1578 states and 1590 transitions. [2018-04-13 08:24:15,109 INFO L460 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-04-13 08:24:15,110 INFO L276 IsEmpty]: Start isEmpty. Operand 1578 states and 1590 transitions. [2018-04-13 08:24:15,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1470 [2018-04-13 08:24:15,119 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:24:15,119 INFO L355 BasicCegarLoop]: trace histogram [225, 207, 207, 206, 206, 206, 19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:24:15,119 INFO L408 AbstractCegarLoop]: === Iteration 44 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:24:15,119 INFO L82 PathProgramCache]: Analyzing trace with hash -2030739248, now seen corresponding path program 36 times [2018-04-13 08:24:15,119 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:24:15,119 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:24:15,120 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:15,120 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:24:15,120 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:15,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:24:15,194 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:24:16,295 INFO L134 CoverageAnalysis]: Checked inductivity of 136892 backedges. 42961 proven. 11364 refuted. 0 times theorem prover too weak. 82567 trivial. 0 not checked. [2018-04-13 08:24:16,296 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:24:16,296 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:24:16,296 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:24:18,157 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 39 check-sat command(s) [2018-04-13 08:24:18,157 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:24:18,210 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:24:18,212 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:24:18,212 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:24:18,214 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:24:18,214 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:24:21,765 INFO L134 CoverageAnalysis]: Checked inductivity of 136892 backedges. 33142 proven. 8228 refuted. 0 times theorem prover too weak. 95522 trivial. 0 not checked. [2018-04-13 08:24:21,766 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:24:21,766 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 30] total 71 [2018-04-13 08:24:21,767 INFO L442 AbstractCegarLoop]: Interpolant automaton has 71 states [2018-04-13 08:24:21,767 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2018-04-13 08:24:21,767 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=621, Invalid=4349, Unknown=0, NotChecked=0, Total=4970 [2018-04-13 08:24:21,767 INFO L87 Difference]: Start difference. First operand 1578 states and 1590 transitions. Second operand 71 states. [2018-04-13 08:24:25,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:24:25,468 INFO L93 Difference]: Finished difference Result 1472 states and 1479 transitions. [2018-04-13 08:24:25,468 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-04-13 08:24:25,468 INFO L78 Accepts]: Start accepts. Automaton has 71 states. Word has length 1469 [2018-04-13 08:24:25,469 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:24:25,471 INFO L225 Difference]: With dead ends: 1472 [2018-04-13 08:24:25,471 INFO L226 Difference]: Without dead ends: 1463 [2018-04-13 08:24:25,472 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1595 GetRequests, 1407 SyntacticMatches, 35 SemanticMatches, 153 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7204 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=3750, Invalid=20120, Unknown=0, NotChecked=0, Total=23870 [2018-04-13 08:24:25,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1463 states. [2018-04-13 08:24:25,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1463 to 1446. [2018-04-13 08:24:25,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1446 states. [2018-04-13 08:24:25,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 1453 transitions. [2018-04-13 08:24:25,478 INFO L78 Accepts]: Start accepts. Automaton has 1446 states and 1453 transitions. Word has length 1469 [2018-04-13 08:24:25,479 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:24:25,479 INFO L459 AbstractCegarLoop]: Abstraction has 1446 states and 1453 transitions. [2018-04-13 08:24:25,479 INFO L460 AbstractCegarLoop]: Interpolant automaton has 71 states. [2018-04-13 08:24:25,479 INFO L276 IsEmpty]: Start isEmpty. Operand 1446 states and 1453 transitions. [2018-04-13 08:24:25,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1482 [2018-04-13 08:24:25,488 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:24:25,488 INFO L355 BasicCegarLoop]: trace histogram [227, 209, 209, 208, 208, 208, 19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:24:25,488 INFO L408 AbstractCegarLoop]: === Iteration 45 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:24:25,489 INFO L82 PathProgramCache]: Analyzing trace with hash 177292256, now seen corresponding path program 37 times [2018-04-13 08:24:25,489 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:24:25,489 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:24:25,489 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:25,489 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:24:25,489 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:25,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:24:25,554 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:24:26,691 INFO L134 CoverageAnalysis]: Checked inductivity of 139450 backedges. 47146 proven. 9625 refuted. 0 times theorem prover too weak. 82679 trivial. 0 not checked. [2018-04-13 08:24:26,691 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:24:26,691 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:24:26,692 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:24:26,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:24:26,781 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:24:28,103 INFO L134 CoverageAnalysis]: Checked inductivity of 139450 backedges. 47175 proven. 9596 refuted. 0 times theorem prover too weak. 82679 trivial. 0 not checked. [2018-04-13 08:24:28,103 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:24:28,103 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 43] total 74 [2018-04-13 08:24:28,104 INFO L442 AbstractCegarLoop]: Interpolant automaton has 74 states [2018-04-13 08:24:28,104 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2018-04-13 08:24:28,104 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=918, Invalid=4484, Unknown=0, NotChecked=0, Total=5402 [2018-04-13 08:24:28,104 INFO L87 Difference]: Start difference. First operand 1446 states and 1453 transitions. Second operand 74 states. [2018-04-13 08:24:29,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:24:29,395 INFO L93 Difference]: Finished difference Result 1458 states and 1463 transitions. [2018-04-13 08:24:29,395 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-04-13 08:24:29,396 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 1481 [2018-04-13 08:24:29,396 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:24:29,399 INFO L225 Difference]: With dead ends: 1458 [2018-04-13 08:24:29,399 INFO L226 Difference]: Without dead ends: 1452 [2018-04-13 08:24:29,400 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1573 GetRequests, 1453 SyntacticMatches, 0 SemanticMatches, 120 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4220 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=3002, Invalid=11760, Unknown=0, NotChecked=0, Total=14762 [2018-04-13 08:24:29,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1452 states. [2018-04-13 08:24:29,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1452 to 1446. [2018-04-13 08:24:29,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1446 states. [2018-04-13 08:24:29,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 1451 transitions. [2018-04-13 08:24:29,411 INFO L78 Accepts]: Start accepts. Automaton has 1446 states and 1451 transitions. Word has length 1481 [2018-04-13 08:24:29,412 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:24:29,412 INFO L459 AbstractCegarLoop]: Abstraction has 1446 states and 1451 transitions. [2018-04-13 08:24:29,412 INFO L460 AbstractCegarLoop]: Interpolant automaton has 74 states. [2018-04-13 08:24:29,412 INFO L276 IsEmpty]: Start isEmpty. Operand 1446 states and 1451 transitions. [2018-04-13 08:24:29,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1488 [2018-04-13 08:24:29,428 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:24:29,428 INFO L355 BasicCegarLoop]: trace histogram [228, 210, 210, 209, 209, 209, 19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:24:29,428 INFO L408 AbstractCegarLoop]: === Iteration 46 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:24:29,428 INFO L82 PathProgramCache]: Analyzing trace with hash -1607842712, now seen corresponding path program 38 times [2018-04-13 08:24:29,429 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:24:29,429 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:24:29,429 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:29,429 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:24:29,429 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:29,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:24:29,493 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:24:30,607 INFO L134 CoverageAnalysis]: Checked inductivity of 140738 backedges. 25371 proven. 1049 refuted. 0 times theorem prover too weak. 114318 trivial. 0 not checked. [2018-04-13 08:24:30,607 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:24:30,607 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:24:30,608 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:24:30,691 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:24:30,691 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:24:30,708 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:24:32,348 INFO L134 CoverageAnalysis]: Checked inductivity of 140738 backedges. 43627 proven. 3424 refuted. 0 times theorem prover too weak. 93687 trivial. 0 not checked. [2018-04-13 08:24:32,348 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:24:32,348 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 47] total 86 [2018-04-13 08:24:32,349 INFO L442 AbstractCegarLoop]: Interpolant automaton has 86 states [2018-04-13 08:24:32,349 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2018-04-13 08:24:32,349 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1203, Invalid=6107, Unknown=0, NotChecked=0, Total=7310 [2018-04-13 08:24:32,350 INFO L87 Difference]: Start difference. First operand 1446 states and 1451 transitions. Second operand 86 states. [2018-04-13 08:24:34,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:24:34,255 INFO L93 Difference]: Finished difference Result 1594 states and 1600 transitions. [2018-04-13 08:24:34,255 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 103 states. [2018-04-13 08:24:34,255 INFO L78 Accepts]: Start accepts. Automaton has 86 states. Word has length 1487 [2018-04-13 08:24:34,256 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:24:34,258 INFO L225 Difference]: With dead ends: 1594 [2018-04-13 08:24:34,258 INFO L226 Difference]: Without dead ends: 1594 [2018-04-13 08:24:34,259 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1589 GetRequests, 1446 SyntacticMatches, 0 SemanticMatches, 143 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4864 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=3607, Invalid=17273, Unknown=0, NotChecked=0, Total=20880 [2018-04-13 08:24:34,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1594 states. [2018-04-13 08:24:34,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1594 to 1584. [2018-04-13 08:24:34,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1584 states. [2018-04-13 08:24:34,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1584 states to 1584 states and 1590 transitions. [2018-04-13 08:24:34,269 INFO L78 Accepts]: Start accepts. Automaton has 1584 states and 1590 transitions. Word has length 1487 [2018-04-13 08:24:34,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:24:34,269 INFO L459 AbstractCegarLoop]: Abstraction has 1584 states and 1590 transitions. [2018-04-13 08:24:34,269 INFO L460 AbstractCegarLoop]: Interpolant automaton has 86 states. [2018-04-13 08:24:34,269 INFO L276 IsEmpty]: Start isEmpty. Operand 1584 states and 1590 transitions. [2018-04-13 08:24:34,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1620 [2018-04-13 08:24:34,280 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:24:34,280 INFO L355 BasicCegarLoop]: trace histogram [249, 230, 230, 229, 229, 229, 20, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:24:34,280 INFO L408 AbstractCegarLoop]: === Iteration 47 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:24:34,280 INFO L82 PathProgramCache]: Analyzing trace with hash -2037889527, now seen corresponding path program 39 times [2018-04-13 08:24:34,280 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:24:34,280 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:24:34,281 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:34,281 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:24:34,281 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:34,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:24:34,354 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:24:35,754 INFO L134 CoverageAnalysis]: Checked inductivity of 168439 backedges. 26733 proven. 1220 refuted. 0 times theorem prover too weak. 140486 trivial. 0 not checked. [2018-04-13 08:24:35,754 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:24:35,754 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:24:35,755 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:24:35,938 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2018-04-13 08:24:35,938 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:24:35,986 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:24:35,987 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:24:35,987 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:24:35,989 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:24:35,989 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:24:38,634 INFO L134 CoverageAnalysis]: Checked inductivity of 168439 backedges. 26733 proven. 1220 refuted. 0 times theorem prover too weak. 140486 trivial. 0 not checked. [2018-04-13 08:24:38,634 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:24:38,634 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26] total 27 [2018-04-13 08:24:38,635 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-04-13 08:24:38,635 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-04-13 08:24:38,635 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=311, Invalid=445, Unknown=0, NotChecked=0, Total=756 [2018-04-13 08:24:38,635 INFO L87 Difference]: Start difference. First operand 1584 states and 1590 transitions. Second operand 28 states. [2018-04-13 08:24:39,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:24:39,104 INFO L93 Difference]: Finished difference Result 1601 states and 1608 transitions. [2018-04-13 08:24:39,104 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-04-13 08:24:39,104 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 1619 [2018-04-13 08:24:39,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:24:39,107 INFO L225 Difference]: With dead ends: 1601 [2018-04-13 08:24:39,107 INFO L226 Difference]: Without dead ends: 1601 [2018-04-13 08:24:39,107 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1665 GetRequests, 1578 SyntacticMatches, 40 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 367 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=858, Invalid=1494, Unknown=0, NotChecked=0, Total=2352 [2018-04-13 08:24:39,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1601 states. [2018-04-13 08:24:39,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1601 to 1590. [2018-04-13 08:24:39,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1590 states. [2018-04-13 08:24:39,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1590 states to 1590 states and 1597 transitions. [2018-04-13 08:24:39,119 INFO L78 Accepts]: Start accepts. Automaton has 1590 states and 1597 transitions. Word has length 1619 [2018-04-13 08:24:39,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:24:39,120 INFO L459 AbstractCegarLoop]: Abstraction has 1590 states and 1597 transitions. [2018-04-13 08:24:39,120 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-04-13 08:24:39,120 INFO L276 IsEmpty]: Start isEmpty. Operand 1590 states and 1597 transitions. [2018-04-13 08:24:39,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1626 [2018-04-13 08:24:39,151 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:24:39,151 INFO L355 BasicCegarLoop]: trace histogram [250, 231, 231, 230, 230, 230, 20, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:24:39,151 INFO L408 AbstractCegarLoop]: === Iteration 48 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:24:39,152 INFO L82 PathProgramCache]: Analyzing trace with hash 85486353, now seen corresponding path program 40 times [2018-04-13 08:24:39,152 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:24:39,152 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:24:39,152 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:39,152 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:24:39,152 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:39,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:24:39,223 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:24:40,374 INFO L134 CoverageAnalysis]: Checked inductivity of 169855 backedges. 29307 proven. 1164 refuted. 0 times theorem prover too weak. 139384 trivial. 0 not checked. [2018-04-13 08:24:40,374 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:24:40,374 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:24:40,375 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:24:40,471 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:24:40,472 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:24:40,489 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:24:42,333 INFO L134 CoverageAnalysis]: Checked inductivity of 169855 backedges. 47556 proven. 5909 refuted. 0 times theorem prover too weak. 116390 trivial. 0 not checked. [2018-04-13 08:24:42,333 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:24:42,334 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 49] total 89 [2018-04-13 08:24:42,334 INFO L442 AbstractCegarLoop]: Interpolant automaton has 89 states [2018-04-13 08:24:42,335 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2018-04-13 08:24:42,335 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1293, Invalid=6539, Unknown=0, NotChecked=0, Total=7832 [2018-04-13 08:24:42,335 INFO L87 Difference]: Start difference. First operand 1590 states and 1597 transitions. Second operand 89 states. [2018-04-13 08:24:44,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:24:44,193 INFO L93 Difference]: Finished difference Result 1742 states and 1751 transitions. [2018-04-13 08:24:44,193 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 106 states. [2018-04-13 08:24:44,193 INFO L78 Accepts]: Start accepts. Automaton has 89 states. Word has length 1625 [2018-04-13 08:24:44,194 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:24:44,196 INFO L225 Difference]: With dead ends: 1742 [2018-04-13 08:24:44,196 INFO L226 Difference]: Without dead ends: 1742 [2018-04-13 08:24:44,197 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1731 GetRequests, 1583 SyntacticMatches, 0 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5223 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=3833, Invalid=18517, Unknown=0, NotChecked=0, Total=22350 [2018-04-13 08:24:44,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1742 states. [2018-04-13 08:24:44,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1742 to 1731. [2018-04-13 08:24:44,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1731 states. [2018-04-13 08:24:44,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1731 states to 1731 states and 1740 transitions. [2018-04-13 08:24:44,205 INFO L78 Accepts]: Start accepts. Automaton has 1731 states and 1740 transitions. Word has length 1625 [2018-04-13 08:24:44,206 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:24:44,206 INFO L459 AbstractCegarLoop]: Abstraction has 1731 states and 1740 transitions. [2018-04-13 08:24:44,206 INFO L460 AbstractCegarLoop]: Interpolant automaton has 89 states. [2018-04-13 08:24:44,206 INFO L276 IsEmpty]: Start isEmpty. Operand 1731 states and 1740 transitions. [2018-04-13 08:24:44,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1758 [2018-04-13 08:24:44,222 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:24:44,222 INFO L355 BasicCegarLoop]: trace histogram [271, 251, 251, 250, 250, 250, 21, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:24:44,222 INFO L408 AbstractCegarLoop]: === Iteration 49 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:24:44,222 INFO L82 PathProgramCache]: Analyzing trace with hash 1662420850, now seen corresponding path program 41 times [2018-04-13 08:24:44,222 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:24:44,223 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:24:44,223 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:44,223 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:24:44,223 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:44,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:24:44,301 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:24:45,816 INFO L134 CoverageAnalysis]: Checked inductivity of 200170 backedges. 76348 proven. 6069 refuted. 0 times theorem prover too weak. 117753 trivial. 0 not checked. [2018-04-13 08:24:45,817 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:24:45,817 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:24:45,817 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:24:53,109 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 54 check-sat command(s) [2018-04-13 08:24:53,109 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:24:53,586 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:24:55,188 INFO L134 CoverageAnalysis]: Checked inductivity of 200170 backedges. 57876 proven. 7141 refuted. 0 times theorem prover too weak. 135153 trivial. 0 not checked. [2018-04-13 08:24:55,188 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:24:55,188 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 49] total 90 [2018-04-13 08:24:55,189 INFO L442 AbstractCegarLoop]: Interpolant automaton has 90 states [2018-04-13 08:24:55,190 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 90 interpolants. [2018-04-13 08:24:55,190 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1194, Invalid=6816, Unknown=0, NotChecked=0, Total=8010 [2018-04-13 08:24:55,190 INFO L87 Difference]: Start difference. First operand 1731 states and 1740 transitions. Second operand 90 states. [2018-04-13 08:24:57,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:24:57,665 INFO L93 Difference]: Finished difference Result 1751 states and 1756 transitions. [2018-04-13 08:24:57,665 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 103 states. [2018-04-13 08:24:57,665 INFO L78 Accepts]: Start accepts. Automaton has 90 states. Word has length 1757 [2018-04-13 08:24:57,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:24:57,668 INFO L225 Difference]: With dead ends: 1751 [2018-04-13 08:24:57,668 INFO L226 Difference]: Without dead ends: 1730 [2018-04-13 08:24:57,670 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1886 GetRequests, 1717 SyntacticMatches, 0 SemanticMatches, 169 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9310 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=4637, Invalid=24433, Unknown=0, NotChecked=0, Total=29070 [2018-04-13 08:24:57,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1730 states. [2018-04-13 08:24:57,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1730 to 1722. [2018-04-13 08:24:57,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1722 states. [2018-04-13 08:24:57,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1722 states to 1722 states and 1726 transitions. [2018-04-13 08:24:57,684 INFO L78 Accepts]: Start accepts. Automaton has 1722 states and 1726 transitions. Word has length 1757 [2018-04-13 08:24:57,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:24:57,685 INFO L459 AbstractCegarLoop]: Abstraction has 1722 states and 1726 transitions. [2018-04-13 08:24:57,685 INFO L460 AbstractCegarLoop]: Interpolant automaton has 90 states. [2018-04-13 08:24:57,685 INFO L276 IsEmpty]: Start isEmpty. Operand 1722 states and 1726 transitions. [2018-04-13 08:24:57,697 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1764 [2018-04-13 08:24:57,697 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:24:57,698 INFO L355 BasicCegarLoop]: trace histogram [272, 252, 252, 251, 251, 251, 21, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:24:57,698 INFO L408 AbstractCegarLoop]: === Iteration 50 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:24:57,698 INFO L82 PathProgramCache]: Analyzing trace with hash -840334726, now seen corresponding path program 42 times [2018-04-13 08:24:57,698 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:24:57,698 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:24:57,699 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:57,699 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:24:57,699 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:24:57,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:24:57,783 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:24:59,415 INFO L134 CoverageAnalysis]: Checked inductivity of 201714 backedges. 30800 proven. 1344 refuted. 0 times theorem prover too weak. 169570 trivial. 0 not checked. [2018-04-13 08:24:59,415 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:24:59,415 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:24:59,416 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:24:59,860 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2018-04-13 08:24:59,860 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:24:59,913 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:24:59,915 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:24:59,915 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:24:59,917 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:24:59,917 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:25:03,190 INFO L134 CoverageAnalysis]: Checked inductivity of 201714 backedges. 30800 proven. 1344 refuted. 0 times theorem prover too weak. 169570 trivial. 0 not checked. [2018-04-13 08:25:03,191 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:25:03,191 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 27] total 28 [2018-04-13 08:25:03,192 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-04-13 08:25:03,192 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-04-13 08:25:03,192 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=336, Invalid=476, Unknown=0, NotChecked=0, Total=812 [2018-04-13 08:25:03,192 INFO L87 Difference]: Start difference. First operand 1722 states and 1726 transitions. Second operand 29 states. [2018-04-13 08:25:03,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:25:03,728 INFO L93 Difference]: Finished difference Result 1739 states and 1744 transitions. [2018-04-13 08:25:03,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-04-13 08:25:03,728 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 1763 [2018-04-13 08:25:03,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:25:03,731 INFO L225 Difference]: With dead ends: 1739 [2018-04-13 08:25:03,731 INFO L226 Difference]: Without dead ends: 1739 [2018-04-13 08:25:03,731 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1811 GetRequests, 1720 SyntacticMatches, 42 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 396 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=931, Invalid=1619, Unknown=0, NotChecked=0, Total=2550 [2018-04-13 08:25:03,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1739 states. [2018-04-13 08:25:03,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1739 to 1728. [2018-04-13 08:25:03,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1728 states. [2018-04-13 08:25:03,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1728 states to 1728 states and 1733 transitions. [2018-04-13 08:25:03,738 INFO L78 Accepts]: Start accepts. Automaton has 1728 states and 1733 transitions. Word has length 1763 [2018-04-13 08:25:03,739 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:25:03,739 INFO L459 AbstractCegarLoop]: Abstraction has 1728 states and 1733 transitions. [2018-04-13 08:25:03,739 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-04-13 08:25:03,739 INFO L276 IsEmpty]: Start isEmpty. Operand 1728 states and 1733 transitions. [2018-04-13 08:25:03,751 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1770 [2018-04-13 08:25:03,751 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:25:03,752 INFO L355 BasicCegarLoop]: trace histogram [273, 253, 253, 252, 252, 252, 21, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:25:03,752 INFO L408 AbstractCegarLoop]: === Iteration 51 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:25:03,752 INFO L82 PathProgramCache]: Analyzing trace with hash -818098494, now seen corresponding path program 43 times [2018-04-13 08:25:03,752 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:25:03,752 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:25:03,752 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:25:03,752 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:25:03,752 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:25:03,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:25:03,836 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:25:05,165 INFO L134 CoverageAnalysis]: Checked inductivity of 203264 backedges. 33629 proven. 1285 refuted. 0 times theorem prover too weak. 168350 trivial. 0 not checked. [2018-04-13 08:25:05,165 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:25:05,165 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:25:05,166 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:25:05,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:25:05,290 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:25:07,356 INFO L134 CoverageAnalysis]: Checked inductivity of 203264 backedges. 55060 proven. 6519 refuted. 0 times theorem prover too weak. 141685 trivial. 0 not checked. [2018-04-13 08:25:07,356 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:25:07,357 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 51] total 93 [2018-04-13 08:25:07,357 INFO L442 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-04-13 08:25:07,357 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-04-13 08:25:07,358 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1409, Invalid=7147, Unknown=0, NotChecked=0, Total=8556 [2018-04-13 08:25:07,358 INFO L87 Difference]: Start difference. First operand 1728 states and 1733 transitions. Second operand 93 states. [2018-04-13 08:25:09,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:25:09,499 INFO L93 Difference]: Finished difference Result 1883 states and 1889 transitions. [2018-04-13 08:25:09,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 110 states. [2018-04-13 08:25:09,499 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 1769 [2018-04-13 08:25:09,500 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:25:09,502 INFO L225 Difference]: With dead ends: 1883 [2018-04-13 08:25:09,503 INFO L226 Difference]: Without dead ends: 1883 [2018-04-13 08:25:09,504 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1879 GetRequests, 1725 SyntacticMatches, 0 SemanticMatches, 154 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5662 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=4133, Invalid=20047, Unknown=0, NotChecked=0, Total=24180 [2018-04-13 08:25:09,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1883 states. [2018-04-13 08:25:09,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1883 to 1872. [2018-04-13 08:25:09,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1872 states. [2018-04-13 08:25:09,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1872 states to 1872 states and 1878 transitions. [2018-04-13 08:25:09,518 INFO L78 Accepts]: Start accepts. Automaton has 1872 states and 1878 transitions. Word has length 1769 [2018-04-13 08:25:09,519 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:25:09,519 INFO L459 AbstractCegarLoop]: Abstraction has 1872 states and 1878 transitions. [2018-04-13 08:25:09,519 INFO L460 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-04-13 08:25:09,520 INFO L276 IsEmpty]: Start isEmpty. Operand 1872 states and 1878 transitions. [2018-04-13 08:25:09,543 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1908 [2018-04-13 08:25:09,543 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:25:09,544 INFO L355 BasicCegarLoop]: trace histogram [295, 274, 274, 273, 273, 273, 22, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:25:09,544 INFO L408 AbstractCegarLoop]: === Iteration 52 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:25:09,544 INFO L82 PathProgramCache]: Analyzing trace with hash 1085039659, now seen corresponding path program 44 times [2018-04-13 08:25:09,544 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:25:09,544 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:25:09,545 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:25:09,545 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:25:09,545 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:25:09,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:25:09,656 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:25:11,366 INFO L134 CoverageAnalysis]: Checked inductivity of 237993 backedges. 84836 proven. 8786 refuted. 0 times theorem prover too weak. 144371 trivial. 0 not checked. [2018-04-13 08:25:11,366 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:25:11,367 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:25:11,367 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:25:11,479 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:25:11,479 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:25:11,499 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:25:13,514 INFO L134 CoverageAnalysis]: Checked inductivity of 237993 backedges. 84889 proven. 8733 refuted. 0 times theorem prover too weak. 144371 trivial. 0 not checked. [2018-04-13 08:25:13,514 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:25:13,514 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 49] total 91 [2018-04-13 08:25:13,515 INFO L442 AbstractCegarLoop]: Interpolant automaton has 91 states [2018-04-13 08:25:13,515 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2018-04-13 08:25:13,515 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1472, Invalid=6718, Unknown=0, NotChecked=0, Total=8190 [2018-04-13 08:25:13,515 INFO L87 Difference]: Start difference. First operand 1872 states and 1878 transitions. Second operand 91 states. [2018-04-13 08:25:15,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:25:15,274 INFO L93 Difference]: Finished difference Result 1886 states and 1890 transitions. [2018-04-13 08:25:15,274 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-04-13 08:25:15,274 INFO L78 Accepts]: Start accepts. Automaton has 91 states. Word has length 1907 [2018-04-13 08:25:15,275 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:25:15,277 INFO L225 Difference]: With dead ends: 1886 [2018-04-13 08:25:15,277 INFO L226 Difference]: Without dead ends: 1880 [2018-04-13 08:25:15,279 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2019 GetRequests, 1868 SyntacticMatches, 0 SemanticMatches, 151 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6583 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=4582, Invalid=18674, Unknown=0, NotChecked=0, Total=23256 [2018-04-13 08:25:15,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states. [2018-04-13 08:25:15,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1872. [2018-04-13 08:25:15,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1872 states. [2018-04-13 08:25:15,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1872 states to 1872 states and 1876 transitions. [2018-04-13 08:25:15,294 INFO L78 Accepts]: Start accepts. Automaton has 1872 states and 1876 transitions. Word has length 1907 [2018-04-13 08:25:15,295 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:25:15,295 INFO L459 AbstractCegarLoop]: Abstraction has 1872 states and 1876 transitions. [2018-04-13 08:25:15,295 INFO L460 AbstractCegarLoop]: Interpolant automaton has 91 states. [2018-04-13 08:25:15,295 INFO L276 IsEmpty]: Start isEmpty. Operand 1872 states and 1876 transitions. [2018-04-13 08:25:15,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1914 [2018-04-13 08:25:15,318 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:25:15,319 INFO L355 BasicCegarLoop]: trace histogram [296, 275, 275, 274, 274, 274, 22, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:25:15,319 INFO L408 AbstractCegarLoop]: === Iteration 53 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:25:15,319 INFO L82 PathProgramCache]: Analyzing trace with hash -1885233037, now seen corresponding path program 45 times [2018-04-13 08:25:15,319 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:25:15,319 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:25:15,320 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:25:15,320 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:25:15,320 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:25:15,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:25:15,476 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:25:17,338 INFO L134 CoverageAnalysis]: Checked inductivity of 239677 backedges. 35259 proven. 1474 refuted. 0 times theorem prover too weak. 202944 trivial. 0 not checked. [2018-04-13 08:25:17,339 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:25:17,339 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:25:17,339 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:25:17,541 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 23 check-sat command(s) [2018-04-13 08:25:17,541 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:25:17,606 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:25:17,615 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:25:17,615 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:25:17,617 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:25:17,617 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:25:21,286 INFO L134 CoverageAnalysis]: Checked inductivity of 239677 backedges. 35259 proven. 1474 refuted. 0 times theorem prover too weak. 202944 trivial. 0 not checked. [2018-04-13 08:25:21,286 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:25:21,287 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 28] total 29 [2018-04-13 08:25:21,287 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-04-13 08:25:21,287 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-04-13 08:25:21,287 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=362, Invalid=508, Unknown=0, NotChecked=0, Total=870 [2018-04-13 08:25:21,288 INFO L87 Difference]: Start difference. First operand 1872 states and 1876 transitions. Second operand 30 states. [2018-04-13 08:25:21,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:25:21,867 INFO L93 Difference]: Finished difference Result 1889 states and 1894 transitions. [2018-04-13 08:25:21,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-04-13 08:25:21,868 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 1913 [2018-04-13 08:25:21,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:25:21,871 INFO L225 Difference]: With dead ends: 1889 [2018-04-13 08:25:21,871 INFO L226 Difference]: Without dead ends: 1889 [2018-04-13 08:25:21,871 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1963 GetRequests, 1868 SyntacticMatches, 44 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 426 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1007, Invalid=1749, Unknown=0, NotChecked=0, Total=2756 [2018-04-13 08:25:21,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1889 states. [2018-04-13 08:25:21,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1889 to 1878. [2018-04-13 08:25:21,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1878 states. [2018-04-13 08:25:21,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1878 states to 1878 states and 1883 transitions. [2018-04-13 08:25:21,879 INFO L78 Accepts]: Start accepts. Automaton has 1878 states and 1883 transitions. Word has length 1913 [2018-04-13 08:25:21,880 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:25:21,880 INFO L459 AbstractCegarLoop]: Abstraction has 1878 states and 1883 transitions. [2018-04-13 08:25:21,880 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-04-13 08:25:21,880 INFO L276 IsEmpty]: Start isEmpty. Operand 1878 states and 1883 transitions. [2018-04-13 08:25:21,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1920 [2018-04-13 08:25:21,894 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:25:21,895 INFO L355 BasicCegarLoop]: trace histogram [297, 276, 276, 275, 275, 275, 22, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:25:21,895 INFO L408 AbstractCegarLoop]: === Iteration 54 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:25:21,895 INFO L82 PathProgramCache]: Analyzing trace with hash -275067397, now seen corresponding path program 46 times [2018-04-13 08:25:21,895 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:25:21,895 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:25:21,896 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:25:21,896 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:25:21,896 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:25:21,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:25:21,994 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:25:23,594 INFO L134 CoverageAnalysis]: Checked inductivity of 241367 backedges. 38355 proven. 1412 refuted. 0 times theorem prover too weak. 201600 trivial. 0 not checked. [2018-04-13 08:25:23,595 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:25:23,595 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:25:23,595 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:25:23,715 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:25:23,715 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:25:23,738 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:25:26,047 INFO L134 CoverageAnalysis]: Checked inductivity of 241367 backedges. 63316 proven. 7159 refuted. 0 times theorem prover too weak. 170892 trivial. 0 not checked. [2018-04-13 08:25:26,048 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:25:26,088 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 53] total 97 [2018-04-13 08:25:26,088 INFO L442 AbstractCegarLoop]: Interpolant automaton has 97 states [2018-04-13 08:25:26,089 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2018-04-13 08:25:26,089 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1530, Invalid=7782, Unknown=0, NotChecked=0, Total=9312 [2018-04-13 08:25:26,089 INFO L87 Difference]: Start difference. First operand 1878 states and 1883 transitions. Second operand 97 states. [2018-04-13 08:25:28,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:25:28,248 INFO L93 Difference]: Finished difference Result 2039 states and 2045 transitions. [2018-04-13 08:25:28,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 115 states. [2018-04-13 08:25:28,249 INFO L78 Accepts]: Start accepts. Automaton has 97 states. Word has length 1919 [2018-04-13 08:25:28,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:25:28,252 INFO L225 Difference]: With dead ends: 2039 [2018-04-13 08:25:28,252 INFO L226 Difference]: Without dead ends: 2039 [2018-04-13 08:25:28,253 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2034 GetRequests, 1873 SyntacticMatches, 0 SemanticMatches, 161 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6207 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=4494, Invalid=21912, Unknown=0, NotChecked=0, Total=26406 [2018-04-13 08:25:28,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2039 states. [2018-04-13 08:25:28,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2039 to 2028. [2018-04-13 08:25:28,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2028 states. [2018-04-13 08:25:28,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2028 states to 2028 states and 2034 transitions. [2018-04-13 08:25:28,268 INFO L78 Accepts]: Start accepts. Automaton has 2028 states and 2034 transitions. Word has length 1919 [2018-04-13 08:25:28,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:25:28,269 INFO L459 AbstractCegarLoop]: Abstraction has 2028 states and 2034 transitions. [2018-04-13 08:25:28,269 INFO L460 AbstractCegarLoop]: Interpolant automaton has 97 states. [2018-04-13 08:25:28,269 INFO L276 IsEmpty]: Start isEmpty. Operand 2028 states and 2034 transitions. [2018-04-13 08:25:28,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2064 [2018-04-13 08:25:28,295 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:25:28,296 INFO L355 BasicCegarLoop]: trace histogram [320, 298, 298, 297, 297, 297, 23, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:25:28,296 INFO L408 AbstractCegarLoop]: === Iteration 55 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:25:28,297 INFO L82 PathProgramCache]: Analyzing trace with hash 1741145324, now seen corresponding path program 47 times [2018-04-13 08:25:28,297 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:25:28,297 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:25:28,297 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:25:28,297 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:25:28,298 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:25:28,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:25:28,471 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:25:30,556 INFO L134 CoverageAnalysis]: Checked inductivity of 280918 backedges. 39986 proven. 1610 refuted. 0 times theorem prover too weak. 239322 trivial. 0 not checked. [2018-04-13 08:25:30,557 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:25:30,557 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:25:30,557 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:25:38,536 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 57 check-sat command(s) [2018-04-13 08:25:38,536 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:25:38,973 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:25:41,346 INFO L134 CoverageAnalysis]: Checked inductivity of 280918 backedges. 91238 proven. 13179 refuted. 0 times theorem prover too weak. 176501 trivial. 0 not checked. [2018-04-13 08:25:41,346 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:25:41,346 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 53] total 80 [2018-04-13 08:25:41,347 INFO L442 AbstractCegarLoop]: Interpolant automaton has 80 states [2018-04-13 08:25:41,347 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2018-04-13 08:25:41,347 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=875, Invalid=5445, Unknown=0, NotChecked=0, Total=6320 [2018-04-13 08:25:41,347 INFO L87 Difference]: Start difference. First operand 2028 states and 2034 transitions. Second operand 80 states. [2018-04-13 08:25:45,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:25:45,042 INFO L93 Difference]: Finished difference Result 2051 states and 2056 transitions. [2018-04-13 08:25:45,042 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 82 states. [2018-04-13 08:25:45,042 INFO L78 Accepts]: Start accepts. Automaton has 80 states. Word has length 2063 [2018-04-13 08:25:45,043 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:25:45,045 INFO L225 Difference]: With dead ends: 2051 [2018-04-13 08:25:45,045 INFO L226 Difference]: Without dead ends: 2045 [2018-04-13 08:25:45,047 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2170 GetRequests, 2013 SyntacticMatches, 1 SemanticMatches, 156 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5878 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=4029, Invalid=20777, Unknown=0, NotChecked=0, Total=24806 [2018-04-13 08:25:45,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2045 states. [2018-04-13 08:25:45,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2045 to 2034. [2018-04-13 08:25:45,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2034 states. [2018-04-13 08:25:45,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2034 states to 2034 states and 2039 transitions. [2018-04-13 08:25:45,056 INFO L78 Accepts]: Start accepts. Automaton has 2034 states and 2039 transitions. Word has length 2063 [2018-04-13 08:25:45,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:25:45,057 INFO L459 AbstractCegarLoop]: Abstraction has 2034 states and 2039 transitions. [2018-04-13 08:25:45,057 INFO L460 AbstractCegarLoop]: Interpolant automaton has 80 states. [2018-04-13 08:25:45,057 INFO L276 IsEmpty]: Start isEmpty. Operand 2034 states and 2039 transitions. [2018-04-13 08:25:45,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2076 [2018-04-13 08:25:45,073 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:25:45,074 INFO L355 BasicCegarLoop]: trace histogram [322, 300, 300, 299, 299, 299, 23, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:25:45,074 INFO L408 AbstractCegarLoop]: === Iteration 56 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:25:45,074 INFO L82 PathProgramCache]: Analyzing trace with hash 1843168572, now seen corresponding path program 48 times [2018-04-13 08:25:45,074 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:25:45,074 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:25:45,075 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:25:45,075 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:25:45,075 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:25:45,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:25:45,186 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:25:47,447 INFO L134 CoverageAnalysis]: Checked inductivity of 284584 backedges. 41822 proven. 1752 refuted. 0 times theorem prover too weak. 241010 trivial. 0 not checked. [2018-04-13 08:25:47,447 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:25:47,447 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:25:47,448 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:25:51,171 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-04-13 08:25:51,171 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:25:51,271 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:25:51,273 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:25:51,273 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:25:51,275 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:25:51,275 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:25:56,383 INFO L134 CoverageAnalysis]: Checked inductivity of 284584 backedges. 66418 proven. 10758 refuted. 0 times theorem prover too weak. 207408 trivial. 0 not checked. [2018-04-13 08:25:56,384 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:25:56,384 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 35] total 60 [2018-04-13 08:25:56,384 INFO L442 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-04-13 08:25:56,385 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-04-13 08:25:56,385 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1108, Invalid=2552, Unknown=0, NotChecked=0, Total=3660 [2018-04-13 08:25:56,385 INFO L87 Difference]: Start difference. First operand 2034 states and 2039 transitions. Second operand 61 states. [2018-04-13 08:25:58,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:25:58,200 INFO L93 Difference]: Finished difference Result 2054 states and 2060 transitions. [2018-04-13 08:25:58,200 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-04-13 08:25:58,200 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 2075 [2018-04-13 08:25:58,201 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:25:58,202 INFO L225 Difference]: With dead ends: 2054 [2018-04-13 08:25:58,202 INFO L226 Difference]: Without dead ends: 2054 [2018-04-13 08:25:58,203 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2157 GetRequests, 2000 SyntacticMatches, 46 SemanticMatches, 111 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3993 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=3823, Invalid=8833, Unknown=0, NotChecked=0, Total=12656 [2018-04-13 08:25:58,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2054 states. [2018-04-13 08:25:58,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2054 to 2040. [2018-04-13 08:25:58,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2040 states. [2018-04-13 08:25:58,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2040 states to 2040 states and 2046 transitions. [2018-04-13 08:25:58,214 INFO L78 Accepts]: Start accepts. Automaton has 2040 states and 2046 transitions. Word has length 2075 [2018-04-13 08:25:58,215 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:25:58,215 INFO L459 AbstractCegarLoop]: Abstraction has 2040 states and 2046 transitions. [2018-04-13 08:25:58,215 INFO L460 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-04-13 08:25:58,216 INFO L276 IsEmpty]: Start isEmpty. Operand 2040 states and 2046 transitions. [2018-04-13 08:25:58,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2082 [2018-04-13 08:25:58,233 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:25:58,233 INFO L355 BasicCegarLoop]: trace histogram [323, 301, 301, 300, 300, 300, 23, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:25:58,233 INFO L408 AbstractCegarLoop]: === Iteration 57 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:25:58,234 INFO L82 PathProgramCache]: Analyzing trace with hash 1340028932, now seen corresponding path program 49 times [2018-04-13 08:25:58,234 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:25:58,234 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:25:58,234 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:25:58,234 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:25:58,234 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:25:58,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:25:58,345 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:26:00,470 INFO L134 CoverageAnalysis]: Checked inductivity of 286426 backedges. 43516 proven. 1900 refuted. 0 times theorem prover too weak. 241010 trivial. 0 not checked. [2018-04-13 08:26:00,470 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:26:00,470 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:26:00,470 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:26:00,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:26:00,634 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:26:02,991 INFO L134 CoverageAnalysis]: Checked inductivity of 286426 backedges. 66640 proven. 12495 refuted. 0 times theorem prover too weak. 207291 trivial. 0 not checked. [2018-04-13 08:26:02,991 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:26:02,992 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 56] total 85 [2018-04-13 08:26:02,992 INFO L442 AbstractCegarLoop]: Interpolant automaton has 85 states [2018-04-13 08:26:02,992 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2018-04-13 08:26:02,992 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1040, Invalid=6100, Unknown=0, NotChecked=0, Total=7140 [2018-04-13 08:26:02,993 INFO L87 Difference]: Start difference. First operand 2040 states and 2046 transitions. Second operand 85 states. [2018-04-13 08:26:06,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:26:06,578 INFO L93 Difference]: Finished difference Result 2224 states and 2232 transitions. [2018-04-13 08:26:06,578 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2018-04-13 08:26:06,578 INFO L78 Accepts]: Start accepts. Automaton has 85 states. Word has length 2081 [2018-04-13 08:26:06,579 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:26:06,581 INFO L225 Difference]: With dead ends: 2224 [2018-04-13 08:26:06,581 INFO L226 Difference]: Without dead ends: 2224 [2018-04-13 08:26:06,582 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2192 GetRequests, 2027 SyntacticMatches, 1 SemanticMatches, 164 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7227 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=4942, Invalid=22448, Unknown=0, NotChecked=0, Total=27390 [2018-04-13 08:26:06,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2224 states. [2018-04-13 08:26:06,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2224 to 2202. [2018-04-13 08:26:06,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2202 states. [2018-04-13 08:26:06,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2202 states to 2202 states and 2210 transitions. [2018-04-13 08:26:06,590 INFO L78 Accepts]: Start accepts. Automaton has 2202 states and 2210 transitions. Word has length 2081 [2018-04-13 08:26:06,591 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:26:06,591 INFO L459 AbstractCegarLoop]: Abstraction has 2202 states and 2210 transitions. [2018-04-13 08:26:06,591 INFO L460 AbstractCegarLoop]: Interpolant automaton has 85 states. [2018-04-13 08:26:06,591 INFO L276 IsEmpty]: Start isEmpty. Operand 2202 states and 2210 transitions. [2018-04-13 08:26:06,609 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2238 [2018-04-13 08:26:06,609 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:26:06,609 INFO L355 BasicCegarLoop]: trace histogram [348, 325, 325, 324, 324, 324, 24, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:26:06,609 INFO L408 AbstractCegarLoop]: === Iteration 58 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:26:06,610 INFO L82 PathProgramCache]: Analyzing trace with hash 673171013, now seen corresponding path program 50 times [2018-04-13 08:26:06,610 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:26:06,610 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:26:06,610 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:26:06,610 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:26:06,610 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:26:06,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:26:06,731 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:26:08,900 INFO L134 CoverageAnalysis]: Checked inductivity of 333353 backedges. 107934 proven. 14586 refuted. 0 times theorem prover too weak. 210833 trivial. 0 not checked. [2018-04-13 08:26:08,900 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:26:08,900 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:26:08,901 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:26:09,063 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:26:09,063 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:26:09,088 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:26:11,574 INFO L134 CoverageAnalysis]: Checked inductivity of 333353 backedges. 107987 proven. 14533 refuted. 0 times theorem prover too weak. 210833 trivial. 0 not checked. [2018-04-13 08:26:11,575 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:26:11,602 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 53] total 97 [2018-04-13 08:26:11,603 INFO L442 AbstractCegarLoop]: Interpolant automaton has 97 states [2018-04-13 08:26:11,603 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2018-04-13 08:26:11,603 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1632, Invalid=7680, Unknown=0, NotChecked=0, Total=9312 [2018-04-13 08:26:11,603 INFO L87 Difference]: Start difference. First operand 2202 states and 2210 transitions. Second operand 97 states. [2018-04-13 08:26:13,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:26:13,149 INFO L93 Difference]: Finished difference Result 2214 states and 2220 transitions. [2018-04-13 08:26:13,149 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2018-04-13 08:26:13,149 INFO L78 Accepts]: Start accepts. Automaton has 97 states. Word has length 2237 [2018-04-13 08:26:13,150 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:26:13,152 INFO L225 Difference]: With dead ends: 2214 [2018-04-13 08:26:13,152 INFO L226 Difference]: Without dead ends: 2208 [2018-04-13 08:26:13,153 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2357 GetRequests, 2196 SyntacticMatches, 0 SemanticMatches, 161 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7592 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=5197, Invalid=21209, Unknown=0, NotChecked=0, Total=26406 [2018-04-13 08:26:13,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2208 states. [2018-04-13 08:26:13,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2208 to 2202. [2018-04-13 08:26:13,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2202 states. [2018-04-13 08:26:13,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2202 states to 2202 states and 2208 transitions. [2018-04-13 08:26:13,163 INFO L78 Accepts]: Start accepts. Automaton has 2202 states and 2208 transitions. Word has length 2237 [2018-04-13 08:26:13,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:26:13,164 INFO L459 AbstractCegarLoop]: Abstraction has 2202 states and 2208 transitions. [2018-04-13 08:26:13,164 INFO L460 AbstractCegarLoop]: Interpolant automaton has 97 states. [2018-04-13 08:26:13,164 INFO L276 IsEmpty]: Start isEmpty. Operand 2202 states and 2208 transitions. [2018-04-13 08:26:13,182 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2244 [2018-04-13 08:26:13,182 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:26:13,183 INFO L355 BasicCegarLoop]: trace histogram [349, 326, 326, 325, 325, 325, 24, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:26:13,183 INFO L408 AbstractCegarLoop]: === Iteration 59 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:26:13,183 INFO L82 PathProgramCache]: Analyzing trace with hash 1165444877, now seen corresponding path program 51 times [2018-04-13 08:26:13,183 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:26:13,183 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:26:13,184 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:26:13,184 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:26:13,184 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:26:13,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:26:13,303 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:26:15,305 INFO L134 CoverageAnalysis]: Checked inductivity of 335347 backedges. 51082 proven. 1687 refuted. 0 times theorem prover too weak. 282578 trivial. 0 not checked. [2018-04-13 08:26:15,305 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:26:15,305 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:26:15,306 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:26:15,687 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 26 check-sat command(s) [2018-04-13 08:26:15,687 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:26:15,743 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:26:15,745 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:26:15,745 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:26:15,747 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:26:15,747 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:26:22,414 INFO L134 CoverageAnalysis]: Checked inductivity of 335347 backedges. 77703 proven. 11470 refuted. 0 times theorem prover too weak. 246174 trivial. 0 not checked. [2018-04-13 08:26:22,414 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:26:22,414 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 35] total 89 [2018-04-13 08:26:22,415 INFO L442 AbstractCegarLoop]: Interpolant automaton has 89 states [2018-04-13 08:26:22,415 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2018-04-13 08:26:22,415 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1112, Invalid=6720, Unknown=0, NotChecked=0, Total=7832 [2018-04-13 08:26:22,416 INFO L87 Difference]: Start difference. First operand 2202 states and 2208 transitions. Second operand 89 states. [2018-04-13 08:26:26,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:26:26,954 INFO L93 Difference]: Finished difference Result 2372 states and 2379 transitions. [2018-04-13 08:26:26,955 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 126 states. [2018-04-13 08:26:26,955 INFO L78 Accepts]: Start accepts. Automaton has 89 states. Word has length 2243 [2018-04-13 08:26:26,955 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:26:26,957 INFO L225 Difference]: With dead ends: 2372 [2018-04-13 08:26:26,957 INFO L226 Difference]: Without dead ends: 2372 [2018-04-13 08:26:26,958 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2391 GetRequests, 2166 SyntacticMatches, 44 SemanticMatches, 181 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10805 ImplicationChecksByTransitivity, 5.7s TimeCoverageRelationStatistics Valid=5490, Invalid=27816, Unknown=0, NotChecked=0, Total=33306 [2018-04-13 08:26:26,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2372 states. [2018-04-13 08:26:26,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2372 to 2364. [2018-04-13 08:26:26,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2364 states. [2018-04-13 08:26:26,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2364 states to 2364 states and 2371 transitions. [2018-04-13 08:26:26,967 INFO L78 Accepts]: Start accepts. Automaton has 2364 states and 2371 transitions. Word has length 2243 [2018-04-13 08:26:26,968 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:26:26,968 INFO L459 AbstractCegarLoop]: Abstraction has 2364 states and 2371 transitions. [2018-04-13 08:26:26,968 INFO L460 AbstractCegarLoop]: Interpolant automaton has 89 states. [2018-04-13 08:26:26,968 INFO L276 IsEmpty]: Start isEmpty. Operand 2364 states and 2371 transitions. [2018-04-13 08:26:26,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2400 [2018-04-13 08:26:26,988 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:26:26,989 INFO L355 BasicCegarLoop]: trace histogram [374, 350, 350, 349, 349, 349, 25, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:26:26,989 INFO L408 AbstractCegarLoop]: === Iteration 60 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:26:26,989 INFO L82 PathProgramCache]: Analyzing trace with hash 1286131150, now seen corresponding path program 52 times [2018-04-13 08:26:26,989 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:26:26,989 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:26:26,990 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:26:26,990 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:26:26,990 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:26:27,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:26:27,108 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:26:30,127 INFO L134 CoverageAnalysis]: Checked inductivity of 385984 backedges. 117266 proven. 17669 refuted. 0 times theorem prover too weak. 251049 trivial. 0 not checked. [2018-04-13 08:26:30,127 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:26:30,127 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:26:30,128 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:26:30,315 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:26:30,315 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:26:30,345 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:26:33,149 INFO L134 CoverageAnalysis]: Checked inductivity of 385984 backedges. 92796 proven. 9113 refuted. 0 times theorem prover too weak. 284075 trivial. 0 not checked. [2018-04-13 08:26:33,150 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:26:33,150 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 59] total 112 [2018-04-13 08:26:33,151 INFO L442 AbstractCegarLoop]: Interpolant automaton has 112 states [2018-04-13 08:26:33,151 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 112 interpolants. [2018-04-13 08:26:33,151 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1717, Invalid=10715, Unknown=0, NotChecked=0, Total=12432 [2018-04-13 08:26:33,151 INFO L87 Difference]: Start difference. First operand 2364 states and 2371 transitions. Second operand 112 states. [2018-04-13 08:26:36,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:26:36,975 INFO L93 Difference]: Finished difference Result 2552 states and 2558 transitions. [2018-04-13 08:26:36,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 120 states. [2018-04-13 08:26:36,975 INFO L78 Accepts]: Start accepts. Automaton has 112 states. Word has length 2399 [2018-04-13 08:26:36,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:26:36,979 INFO L225 Difference]: With dead ends: 2552 [2018-04-13 08:26:36,979 INFO L226 Difference]: Without dead ends: 2543 [2018-04-13 08:26:36,982 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2567 GetRequests, 2345 SyntacticMatches, 0 SemanticMatches, 222 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16812 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=7179, Invalid=42773, Unknown=0, NotChecked=0, Total=49952 [2018-04-13 08:26:36,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2543 states. [2018-04-13 08:26:36,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2543 to 2532. [2018-04-13 08:26:36,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2532 states. [2018-04-13 08:26:36,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2532 states to 2532 states and 2538 transitions. [2018-04-13 08:26:36,992 INFO L78 Accepts]: Start accepts. Automaton has 2532 states and 2538 transitions. Word has length 2399 [2018-04-13 08:26:36,993 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:26:36,993 INFO L459 AbstractCegarLoop]: Abstraction has 2532 states and 2538 transitions. [2018-04-13 08:26:36,993 INFO L460 AbstractCegarLoop]: Interpolant automaton has 112 states. [2018-04-13 08:26:36,993 INFO L276 IsEmpty]: Start isEmpty. Operand 2532 states and 2538 transitions. [2018-04-13 08:26:37,016 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2568 [2018-04-13 08:26:37,016 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:26:37,017 INFO L355 BasicCegarLoop]: trace histogram [401, 376, 376, 375, 375, 375, 26, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:26:37,017 INFO L408 AbstractCegarLoop]: === Iteration 61 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:26:37,017 INFO L82 PathProgramCache]: Analyzing trace with hash 185613919, now seen corresponding path program 53 times [2018-04-13 08:26:37,017 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:26:37,017 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:26:37,018 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:26:37,018 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:26:37,018 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:26:37,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:26:37,167 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:26:39,861 INFO L134 CoverageAnalysis]: Checked inductivity of 444775 backedges. 127208 proven. 20874 refuted. 0 times theorem prover too weak. 296693 trivial. 0 not checked. [2018-04-13 08:26:39,861 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:26:39,861 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:26:39,862 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:27:01,812 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 60 check-sat command(s) [2018-04-13 08:27:01,812 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:27:04,123 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:27:08,022 INFO L134 CoverageAnalysis]: Checked inductivity of 444775 backedges. 134159 proven. 17439 refuted. 0 times theorem prover too weak. 293177 trivial. 0 not checked. [2018-04-13 08:27:08,022 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:27:08,023 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 59] total 107 [2018-04-13 08:27:08,024 INFO L442 AbstractCegarLoop]: Interpolant automaton has 107 states [2018-04-13 08:27:08,024 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 107 interpolants. [2018-04-13 08:27:08,025 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1898, Invalid=9444, Unknown=0, NotChecked=0, Total=11342 [2018-04-13 08:27:08,025 INFO L87 Difference]: Start difference. First operand 2532 states and 2538 transitions. Second operand 107 states. [2018-04-13 08:27:11,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:27:11,361 INFO L93 Difference]: Finished difference Result 2546 states and 2550 transitions. [2018-04-13 08:27:11,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 109 states. [2018-04-13 08:27:11,361 INFO L78 Accepts]: Start accepts. Automaton has 107 states. Word has length 2567 [2018-04-13 08:27:11,362 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:27:11,364 INFO L225 Difference]: With dead ends: 2546 [2018-04-13 08:27:11,364 INFO L226 Difference]: Without dead ends: 2540 [2018-04-13 08:27:11,365 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2722 GetRequests, 2520 SyntacticMatches, 0 SemanticMatches, 202 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12289 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=7571, Invalid=33841, Unknown=0, NotChecked=0, Total=41412 [2018-04-13 08:27:11,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2540 states. [2018-04-13 08:27:11,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2540 to 2532. [2018-04-13 08:27:11,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2532 states. [2018-04-13 08:27:11,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2532 states to 2532 states and 2536 transitions. [2018-04-13 08:27:11,375 INFO L78 Accepts]: Start accepts. Automaton has 2532 states and 2536 transitions. Word has length 2567 [2018-04-13 08:27:11,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:27:11,376 INFO L459 AbstractCegarLoop]: Abstraction has 2532 states and 2536 transitions. [2018-04-13 08:27:11,376 INFO L460 AbstractCegarLoop]: Interpolant automaton has 107 states. [2018-04-13 08:27:11,376 INFO L276 IsEmpty]: Start isEmpty. Operand 2532 states and 2536 transitions. [2018-04-13 08:27:11,401 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2574 [2018-04-13 08:27:11,401 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:27:11,401 INFO L355 BasicCegarLoop]: trace histogram [402, 377, 377, 376, 376, 376, 26, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:27:11,401 INFO L408 AbstractCegarLoop]: === Iteration 62 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:27:11,402 INFO L82 PathProgramCache]: Analyzing trace with hash 2140128167, now seen corresponding path program 54 times [2018-04-13 08:27:11,402 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:27:11,402 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:27:11,402 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:27:11,402 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:27:11,402 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:27:11,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:27:11,559 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:27:14,591 INFO L134 CoverageAnalysis]: Checked inductivity of 447079 backedges. 57375 proven. 2054 refuted. 0 times theorem prover too weak. 387650 trivial. 0 not checked. [2018-04-13 08:27:14,591 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:27:14,592 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:27:14,592 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:27:16,827 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 53 check-sat command(s) [2018-04-13 08:27:16,828 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:27:17,044 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:27:17,046 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:27:17,046 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:27:17,048 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:27:17,048 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:27:23,719 INFO L134 CoverageAnalysis]: Checked inductivity of 447079 backedges. 57375 proven. 2054 refuted. 0 times theorem prover too weak. 387650 trivial. 0 not checked. [2018-04-13 08:27:23,719 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:27:23,720 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 32] total 33 [2018-04-13 08:27:23,720 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-04-13 08:27:23,720 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-04-13 08:27:23,720 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=476, Invalid=646, Unknown=0, NotChecked=0, Total=1122 [2018-04-13 08:27:23,720 INFO L87 Difference]: Start difference. First operand 2532 states and 2536 transitions. Second operand 34 states. [2018-04-13 08:27:24,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:27:24,431 INFO L93 Difference]: Finished difference Result 2549 states and 2554 transitions. [2018-04-13 08:27:24,431 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-04-13 08:27:24,432 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 2573 [2018-04-13 08:27:24,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:27:24,434 INFO L225 Difference]: With dead ends: 2549 [2018-04-13 08:27:24,434 INFO L226 Difference]: Without dead ends: 2549 [2018-04-13 08:27:24,435 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2631 GetRequests, 2520 SyntacticMatches, 52 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 556 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1341, Invalid=2319, Unknown=0, NotChecked=0, Total=3660 [2018-04-13 08:27:24,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2549 states. [2018-04-13 08:27:24,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2549 to 2538. [2018-04-13 08:27:24,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2538 states. [2018-04-13 08:27:24,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2538 states to 2538 states and 2543 transitions. [2018-04-13 08:27:24,447 INFO L78 Accepts]: Start accepts. Automaton has 2538 states and 2543 transitions. Word has length 2573 [2018-04-13 08:27:24,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:27:24,448 INFO L459 AbstractCegarLoop]: Abstraction has 2538 states and 2543 transitions. [2018-04-13 08:27:24,448 INFO L460 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-04-13 08:27:24,448 INFO L276 IsEmpty]: Start isEmpty. Operand 2538 states and 2543 transitions. [2018-04-13 08:27:24,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2580 [2018-04-13 08:27:24,473 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:27:24,473 INFO L355 BasicCegarLoop]: trace histogram [403, 378, 378, 377, 377, 377, 26, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:27:24,473 INFO L408 AbstractCegarLoop]: === Iteration 63 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:27:24,474 INFO L82 PathProgramCache]: Analyzing trace with hash -303646161, now seen corresponding path program 55 times [2018-04-13 08:27:24,474 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:27:24,474 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:27:24,474 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:27:24,474 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:27:24,474 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:27:24,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:27:24,630 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:27:27,111 INFO L134 CoverageAnalysis]: Checked inductivity of 449389 backedges. 61659 proven. 1980 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-04-13 08:27:27,111 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:27:27,111 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:27:27,112 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:27:27,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:27:27,349 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:27:30,862 INFO L134 CoverageAnalysis]: Checked inductivity of 449389 backedges. 94782 proven. 16081 refuted. 0 times theorem prover too weak. 338526 trivial. 0 not checked. [2018-04-13 08:27:30,862 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:27:30,862 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 61] total 111 [2018-04-13 08:27:30,863 INFO L442 AbstractCegarLoop]: Interpolant automaton has 111 states [2018-04-13 08:27:30,863 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 111 interpolants. [2018-04-13 08:27:30,863 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2011, Invalid=10199, Unknown=0, NotChecked=0, Total=12210 [2018-04-13 08:27:30,864 INFO L87 Difference]: Start difference. First operand 2538 states and 2543 transitions. Second operand 111 states. [2018-04-13 08:27:34,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:27:34,149 INFO L93 Difference]: Finished difference Result 2723 states and 2729 transitions. [2018-04-13 08:27:34,149 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 131 states. [2018-04-13 08:27:34,149 INFO L78 Accepts]: Start accepts. Automaton has 111 states. Word has length 2579 [2018-04-13 08:27:34,150 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:27:34,152 INFO L225 Difference]: With dead ends: 2723 [2018-04-13 08:27:34,152 INFO L226 Difference]: Without dead ends: 2723 [2018-04-13 08:27:34,153 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2712 GetRequests, 2527 SyntacticMatches, 0 SemanticMatches, 185 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8255 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=5827, Invalid=28955, Unknown=0, NotChecked=0, Total=34782 [2018-04-13 08:27:34,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2723 states. [2018-04-13 08:27:34,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2723 to 2712. [2018-04-13 08:27:34,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2712 states. [2018-04-13 08:27:34,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2712 states to 2712 states and 2718 transitions. [2018-04-13 08:27:34,166 INFO L78 Accepts]: Start accepts. Automaton has 2712 states and 2718 transitions. Word has length 2579 [2018-04-13 08:27:34,167 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:27:34,167 INFO L459 AbstractCegarLoop]: Abstraction has 2712 states and 2718 transitions. [2018-04-13 08:27:34,167 INFO L460 AbstractCegarLoop]: Interpolant automaton has 111 states. [2018-04-13 08:27:34,167 INFO L276 IsEmpty]: Start isEmpty. Operand 2712 states and 2718 transitions. [2018-04-13 08:27:34,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2748 [2018-04-13 08:27:34,194 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:27:34,195 INFO L355 BasicCegarLoop]: trace histogram [430, 404, 404, 403, 403, 403, 27, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:27:34,195 INFO L408 AbstractCegarLoop]: === Iteration 64 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:27:34,195 INFO L82 PathProgramCache]: Analyzing trace with hash -2000509888, now seen corresponding path program 56 times [2018-04-13 08:27:34,195 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:27:34,195 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:27:34,195 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:27:34,196 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:27:34,196 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:27:34,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:27:34,359 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:27:37,524 INFO L134 CoverageAnalysis]: Checked inductivity of 512668 backedges. 140086 proven. 24201 refuted. 0 times theorem prover too weak. 348381 trivial. 0 not checked. [2018-04-13 08:27:37,524 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:27:37,524 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:27:37,525 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:27:37,764 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:27:37,764 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:27:37,800 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:27:41,424 INFO L134 CoverageAnalysis]: Checked inductivity of 512668 backedges. 118671 proven. 6322 refuted. 0 times theorem prover too weak. 387675 trivial. 0 not checked. [2018-04-13 08:27:41,424 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:27:41,424 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 61] total 118 [2018-04-13 08:27:41,425 INFO L442 AbstractCegarLoop]: Interpolant automaton has 118 states [2018-04-13 08:27:41,425 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 118 interpolants. [2018-04-13 08:27:41,426 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1926, Invalid=11880, Unknown=0, NotChecked=0, Total=13806 [2018-04-13 08:27:41,426 INFO L87 Difference]: Start difference. First operand 2712 states and 2718 transitions. Second operand 118 states. [2018-04-13 08:27:45,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:27:45,821 INFO L93 Difference]: Finished difference Result 2728 states and 2732 transitions. [2018-04-13 08:27:45,821 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 128 states. [2018-04-13 08:27:45,821 INFO L78 Accepts]: Start accepts. Automaton has 118 states. Word has length 2747 [2018-04-13 08:27:45,822 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:27:45,824 INFO L225 Difference]: With dead ends: 2728 [2018-04-13 08:27:45,824 INFO L226 Difference]: Without dead ends: 2722 [2018-04-13 08:27:45,825 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2927 GetRequests, 2691 SyntacticMatches, 0 SemanticMatches, 236 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19183 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=8103, Invalid=48303, Unknown=0, NotChecked=0, Total=56406 [2018-04-13 08:27:45,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2722 states. [2018-04-13 08:27:45,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2722 to 2712. [2018-04-13 08:27:45,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2712 states. [2018-04-13 08:27:45,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2712 states to 2712 states and 2716 transitions. [2018-04-13 08:27:45,835 INFO L78 Accepts]: Start accepts. Automaton has 2712 states and 2716 transitions. Word has length 2747 [2018-04-13 08:27:45,836 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:27:45,836 INFO L459 AbstractCegarLoop]: Abstraction has 2712 states and 2716 transitions. [2018-04-13 08:27:45,836 INFO L460 AbstractCegarLoop]: Interpolant automaton has 118 states. [2018-04-13 08:27:45,836 INFO L276 IsEmpty]: Start isEmpty. Operand 2712 states and 2716 transitions. [2018-04-13 08:27:45,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2754 [2018-04-13 08:27:45,862 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:27:45,863 INFO L355 BasicCegarLoop]: trace histogram [431, 405, 405, 404, 404, 404, 27, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:27:45,863 INFO L408 AbstractCegarLoop]: === Iteration 65 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:27:45,863 INFO L82 PathProgramCache]: Analyzing trace with hash -2094076728, now seen corresponding path program 57 times [2018-04-13 08:27:45,863 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:27:45,863 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:27:45,863 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:27:45,863 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:27:45,864 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:27:45,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:27:46,001 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:27:49,420 INFO L134 CoverageAnalysis]: Checked inductivity of 515142 backedges. 64064 proven. 2214 refuted. 0 times theorem prover too weak. 448864 trivial. 0 not checked. [2018-04-13 08:27:49,420 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:27:49,421 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:27:49,421 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:27:49,809 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-04-13 08:27:49,810 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:27:49,942 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:27:49,943 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:27:49,943 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:27:49,954 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:27:49,955 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:27:57,722 INFO L134 CoverageAnalysis]: Checked inductivity of 515142 backedges. 64064 proven. 2214 refuted. 0 times theorem prover too weak. 448864 trivial. 0 not checked. [2018-04-13 08:27:57,723 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:27:57,723 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 33] total 34 [2018-04-13 08:27:57,724 INFO L442 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-04-13 08:27:57,724 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-04-13 08:27:57,724 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=507, Invalid=683, Unknown=0, NotChecked=0, Total=1190 [2018-04-13 08:27:57,724 INFO L87 Difference]: Start difference. First operand 2712 states and 2716 transitions. Second operand 35 states. [2018-04-13 08:27:58,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:27:58,468 INFO L93 Difference]: Finished difference Result 2729 states and 2734 transitions. [2018-04-13 08:27:58,468 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-04-13 08:27:58,468 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 2753 [2018-04-13 08:27:58,469 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:27:58,471 INFO L225 Difference]: With dead ends: 2729 [2018-04-13 08:27:58,471 INFO L226 Difference]: Without dead ends: 2729 [2018-04-13 08:27:58,471 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2813 GetRequests, 2698 SyntacticMatches, 54 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 591 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1432, Invalid=2474, Unknown=0, NotChecked=0, Total=3906 [2018-04-13 08:27:58,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2729 states. [2018-04-13 08:27:58,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2729 to 2718. [2018-04-13 08:27:58,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2718 states. [2018-04-13 08:27:58,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2718 states to 2718 states and 2723 transitions. [2018-04-13 08:27:58,482 INFO L78 Accepts]: Start accepts. Automaton has 2718 states and 2723 transitions. Word has length 2753 [2018-04-13 08:27:58,483 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:27:58,483 INFO L459 AbstractCegarLoop]: Abstraction has 2718 states and 2723 transitions. [2018-04-13 08:27:58,483 INFO L460 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-04-13 08:27:58,483 INFO L276 IsEmpty]: Start isEmpty. Operand 2718 states and 2723 transitions. [2018-04-13 08:27:58,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2760 [2018-04-13 08:27:58,510 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:27:58,510 INFO L355 BasicCegarLoop]: trace histogram [432, 406, 406, 405, 405, 405, 27, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:27:58,510 INFO L408 AbstractCegarLoop]: === Iteration 66 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:27:58,510 INFO L82 PathProgramCache]: Analyzing trace with hash 795920016, now seen corresponding path program 58 times [2018-04-13 08:27:58,510 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:27:58,510 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:27:58,511 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:27:58,511 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:27:58,511 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:27:58,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:27:58,684 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:28:01,508 INFO L134 CoverageAnalysis]: Checked inductivity of 517622 backedges. 68675 proven. 2137 refuted. 0 times theorem prover too weak. 446810 trivial. 0 not checked. [2018-04-13 08:28:01,509 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:28:01,509 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:28:01,509 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:28:01,763 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:28:01,763 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:28:01,801 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:28:06,073 INFO L134 CoverageAnalysis]: Checked inductivity of 517622 backedges. 117136 proven. 10809 refuted. 0 times theorem prover too weak. 389677 trivial. 0 not checked. [2018-04-13 08:28:06,073 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:28:06,073 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 63] total 117 [2018-04-13 08:28:06,074 INFO L442 AbstractCegarLoop]: Interpolant automaton has 117 states [2018-04-13 08:28:06,074 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 117 interpolants. [2018-04-13 08:28:06,075 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2210, Invalid=11362, Unknown=0, NotChecked=0, Total=13572 [2018-04-13 08:28:06,075 INFO L87 Difference]: Start difference. First operand 2718 states and 2723 transitions. Second operand 117 states. [2018-04-13 08:28:09,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:28:09,253 INFO L93 Difference]: Finished difference Result 2909 states and 2915 transitions. [2018-04-13 08:28:09,253 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 140 states. [2018-04-13 08:28:09,254 INFO L78 Accepts]: Start accepts. Automaton has 117 states. Word has length 2759 [2018-04-13 08:28:09,255 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:28:09,257 INFO L225 Difference]: With dead ends: 2909 [2018-04-13 08:28:09,257 INFO L226 Difference]: Without dead ends: 2909 [2018-04-13 08:28:09,259 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2899 GetRequests, 2703 SyntacticMatches, 0 SemanticMatches, 196 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9307 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=6524, Invalid=32482, Unknown=0, NotChecked=0, Total=39006 [2018-04-13 08:28:09,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2909 states. [2018-04-13 08:28:09,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2909 to 2898. [2018-04-13 08:28:09,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2898 states. [2018-04-13 08:28:09,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2898 states to 2898 states and 2904 transitions. [2018-04-13 08:28:09,271 INFO L78 Accepts]: Start accepts. Automaton has 2898 states and 2904 transitions. Word has length 2759 [2018-04-13 08:28:09,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:28:09,272 INFO L459 AbstractCegarLoop]: Abstraction has 2898 states and 2904 transitions. [2018-04-13 08:28:09,272 INFO L460 AbstractCegarLoop]: Interpolant automaton has 117 states. [2018-04-13 08:28:09,272 INFO L276 IsEmpty]: Start isEmpty. Operand 2898 states and 2904 transitions. [2018-04-13 08:28:09,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2934 [2018-04-13 08:28:09,334 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:28:09,334 INFO L355 BasicCegarLoop]: trace histogram [460, 433, 433, 432, 432, 432, 28, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:28:09,334 INFO L408 AbstractCegarLoop]: === Iteration 67 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:28:09,335 INFO L82 PathProgramCache]: Analyzing trace with hash -1868726615, now seen corresponding path program 59 times [2018-04-13 08:28:09,335 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:28:09,335 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:28:09,335 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:28:09,335 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:28:09,335 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:28:09,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:28:09,470 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:28:13,104 INFO L134 CoverageAnalysis]: Checked inductivity of 588033 backedges. 191070 proven. 6882 refuted. 0 times theorem prover too weak. 390081 trivial. 0 not checked. [2018-04-13 08:28:13,105 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:28:13,105 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:28:13,105 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:28:52,027 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 63 check-sat command(s) [2018-04-13 08:28:52,027 INFO L243 tOrderPrioritization]: Conjunction of SSA is unknown [2018-04-13 08:28:55,295 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-13 08:28:55,295 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62] total 62 [2018-04-13 08:28:55,296 INFO L442 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-04-13 08:28:55,296 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-04-13 08:28:55,297 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=851, Invalid=2931, Unknown=0, NotChecked=0, Total=3782 [2018-04-13 08:28:55,297 INFO L87 Difference]: Start difference. First operand 2898 states and 2904 transitions. Second operand 62 states. [2018-04-13 08:28:57,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:28:57,420 INFO L93 Difference]: Finished difference Result 2912 states and 2916 transitions. [2018-04-13 08:28:57,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 87 states. [2018-04-13 08:28:57,420 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 2933 [2018-04-13 08:28:57,421 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:28:57,424 INFO L225 Difference]: With dead ends: 2912 [2018-04-13 08:28:57,424 INFO L226 Difference]: Without dead ends: 2906 [2018-04-13 08:28:57,425 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 145 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 142 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5165 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=3584, Invalid=17008, Unknown=0, NotChecked=0, Total=20592 [2018-04-13 08:28:57,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2906 states. [2018-04-13 08:28:57,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2906 to 2898. [2018-04-13 08:28:57,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2898 states. [2018-04-13 08:28:57,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2898 states to 2898 states and 2902 transitions. [2018-04-13 08:28:57,437 INFO L78 Accepts]: Start accepts. Automaton has 2898 states and 2902 transitions. Word has length 2933 [2018-04-13 08:28:57,438 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:28:57,438 INFO L459 AbstractCegarLoop]: Abstraction has 2898 states and 2902 transitions. [2018-04-13 08:28:57,438 INFO L460 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-04-13 08:28:57,438 INFO L276 IsEmpty]: Start isEmpty. Operand 2898 states and 2902 transitions. [2018-04-13 08:28:57,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2940 [2018-04-13 08:28:57,468 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:28:57,469 INFO L355 BasicCegarLoop]: trace histogram [461, 434, 434, 433, 433, 433, 28, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:28:57,469 INFO L408 AbstractCegarLoop]: === Iteration 68 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:28:57,469 INFO L82 PathProgramCache]: Analyzing trace with hash -326433679, now seen corresponding path program 60 times [2018-04-13 08:28:57,469 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:28:57,469 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:28:57,470 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:28:57,470 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:28:57,470 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:28:57,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:28:57,673 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:29:01,570 INFO L134 CoverageAnalysis]: Checked inductivity of 590683 backedges. 71253 proven. 2380 refuted. 0 times theorem prover too weak. 517050 trivial. 0 not checked. [2018-04-13 08:29:01,570 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:29:01,570 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:29:01,571 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:29:25,219 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 57 check-sat command(s) [2018-04-13 08:29:25,219 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:29:27,079 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:29:27,081 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:29:27,081 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:29:27,083 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:29:27,083 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:29:37,313 INFO L134 CoverageAnalysis]: Checked inductivity of 590683 backedges. 132215 proven. 7364 refuted. 0 times theorem prover too weak. 451104 trivial. 0 not checked. [2018-04-13 08:29:37,314 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:29:37,314 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 41] total 70 [2018-04-13 08:29:37,315 INFO L442 AbstractCegarLoop]: Interpolant automaton has 71 states [2018-04-13 08:29:37,315 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2018-04-13 08:29:37,315 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1460, Invalid=3510, Unknown=0, NotChecked=0, Total=4970 [2018-04-13 08:29:37,315 INFO L87 Difference]: Start difference. First operand 2898 states and 2902 transitions. Second operand 71 states. [2018-04-13 08:29:40,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:29:40,243 INFO L93 Difference]: Finished difference Result 2923 states and 2929 transitions. [2018-04-13 08:29:40,243 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2018-04-13 08:29:40,243 INFO L78 Accepts]: Start accepts. Automaton has 71 states. Word has length 2939 [2018-04-13 08:29:40,244 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:29:40,247 INFO L225 Difference]: With dead ends: 2923 [2018-04-13 08:29:40,247 INFO L226 Difference]: Without dead ends: 2923 [2018-04-13 08:29:40,248 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3037 GetRequests, 2849 SyntacticMatches, 55 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5674 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=5288, Invalid=12802, Unknown=0, NotChecked=0, Total=18090 [2018-04-13 08:29:40,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2923 states. [2018-04-13 08:29:40,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2923 to 2904. [2018-04-13 08:29:40,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2904 states. [2018-04-13 08:29:40,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2904 states to 2904 states and 2909 transitions. [2018-04-13 08:29:40,261 INFO L78 Accepts]: Start accepts. Automaton has 2904 states and 2909 transitions. Word has length 2939 [2018-04-13 08:29:40,262 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:29:40,262 INFO L459 AbstractCegarLoop]: Abstraction has 2904 states and 2909 transitions. [2018-04-13 08:29:40,262 INFO L460 AbstractCegarLoop]: Interpolant automaton has 71 states. [2018-04-13 08:29:40,262 INFO L276 IsEmpty]: Start isEmpty. Operand 2904 states and 2909 transitions. [2018-04-13 08:29:40,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2946 [2018-04-13 08:29:40,292 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:29:40,292 INFO L355 BasicCegarLoop]: trace histogram [462, 435, 435, 434, 434, 434, 28, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:29:40,292 INFO L408 AbstractCegarLoop]: === Iteration 69 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:29:40,292 INFO L82 PathProgramCache]: Analyzing trace with hash -1088636039, now seen corresponding path program 61 times [2018-04-13 08:29:40,292 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:29:40,292 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:29:40,293 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:29:40,293 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:29:40,293 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:29:40,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:29:40,499 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:29:43,564 INFO L134 CoverageAnalysis]: Checked inductivity of 593339 backedges. 76203 proven. 2300 refuted. 0 times theorem prover too weak. 514836 trivial. 0 not checked. [2018-04-13 08:29:43,564 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:29:43,564 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:29:43,565 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:29:43,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:29:43,856 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:29:48,202 INFO L134 CoverageAnalysis]: Checked inductivity of 593339 backedges. 137137 proven. 7312 refuted. 0 times theorem prover too weak. 448890 trivial. 0 not checked. [2018-04-13 08:29:48,202 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:29:48,203 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 65] total 122 [2018-04-13 08:29:48,203 INFO L442 AbstractCegarLoop]: Interpolant automaton has 122 states [2018-04-13 08:29:48,204 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 122 interpolants. [2018-04-13 08:29:48,204 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2391, Invalid=12371, Unknown=0, NotChecked=0, Total=14762 [2018-04-13 08:29:48,204 INFO L87 Difference]: Start difference. First operand 2904 states and 2909 transitions. Second operand 122 states. [2018-04-13 08:29:51,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:29:51,644 INFO L93 Difference]: Finished difference Result 3106 states and 3112 transitions. [2018-04-13 08:29:51,644 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 148 states. [2018-04-13 08:29:51,644 INFO L78 Accepts]: Start accepts. Automaton has 122 states. Word has length 2945 [2018-04-13 08:29:51,645 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:29:51,648 INFO L225 Difference]: With dead ends: 3106 [2018-04-13 08:29:51,648 INFO L226 Difference]: Without dead ends: 3106 [2018-04-13 08:29:51,650 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3092 GetRequests, 2886 SyntacticMatches, 0 SemanticMatches, 206 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10318 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=7189, Invalid=35867, Unknown=0, NotChecked=0, Total=43056 [2018-04-13 08:29:51,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3106 states. [2018-04-13 08:29:51,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3106 to 3096. [2018-04-13 08:29:51,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3096 states. [2018-04-13 08:29:51,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3096 states to 3096 states and 3102 transitions. [2018-04-13 08:29:51,664 INFO L78 Accepts]: Start accepts. Automaton has 3096 states and 3102 transitions. Word has length 2945 [2018-04-13 08:29:51,665 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:29:51,665 INFO L459 AbstractCegarLoop]: Abstraction has 3096 states and 3102 transitions. [2018-04-13 08:29:51,665 INFO L460 AbstractCegarLoop]: Interpolant automaton has 122 states. [2018-04-13 08:29:51,665 INFO L276 IsEmpty]: Start isEmpty. Operand 3096 states and 3102 transitions. [2018-04-13 08:29:51,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3132 [2018-04-13 08:29:51,699 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:29:51,699 INFO L355 BasicCegarLoop]: trace histogram [492, 464, 464, 463, 463, 463, 29, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:29:51,699 INFO L408 AbstractCegarLoop]: === Iteration 70 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:29:51,699 INFO L82 PathProgramCache]: Analyzing trace with hash 1958968098, now seen corresponding path program 62 times [2018-04-13 08:29:51,700 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:29:51,700 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:29:51,700 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:29:51,700 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:29:51,700 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:29:51,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:29:51,934 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:29:56,030 INFO L134 CoverageAnalysis]: Checked inductivity of 674230 backedges. 78960 proven. 2552 refuted. 0 times theorem prover too weak. 592718 trivial. 0 not checked. [2018-04-13 08:29:56,030 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:29:56,031 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:29:56,031 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:29:56,357 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:29:56,357 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:29:56,389 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:29:56,391 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:29:56,391 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:29:56,393 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:29:56,393 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:30:05,629 INFO L134 CoverageAnalysis]: Checked inductivity of 674230 backedges. 78960 proven. 2552 refuted. 0 times theorem prover too weak. 592718 trivial. 0 not checked. [2018-04-13 08:30:05,630 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:30:05,630 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 35] total 36 [2018-04-13 08:30:05,631 INFO L442 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-04-13 08:30:05,631 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-04-13 08:30:05,631 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=572, Invalid=760, Unknown=0, NotChecked=0, Total=1332 [2018-04-13 08:30:05,631 INFO L87 Difference]: Start difference. First operand 3096 states and 3102 transitions. Second operand 37 states. [2018-04-13 08:30:06,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:30:06,456 INFO L93 Difference]: Finished difference Result 3113 states and 3120 transitions. [2018-04-13 08:30:06,457 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-04-13 08:30:06,457 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 3131 [2018-04-13 08:30:06,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:30:06,461 INFO L225 Difference]: With dead ends: 3113 [2018-04-13 08:30:06,462 INFO L226 Difference]: Without dead ends: 3113 [2018-04-13 08:30:06,462 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3195 GetRequests, 3072 SyntacticMatches, 58 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 664 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1623, Invalid=2799, Unknown=0, NotChecked=0, Total=4422 [2018-04-13 08:30:06,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3113 states. [2018-04-13 08:30:06,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3113 to 3102. [2018-04-13 08:30:06,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3102 states. [2018-04-13 08:30:06,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3102 states to 3102 states and 3109 transitions. [2018-04-13 08:30:06,476 INFO L78 Accepts]: Start accepts. Automaton has 3102 states and 3109 transitions. Word has length 3131 [2018-04-13 08:30:06,477 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:30:06,477 INFO L459 AbstractCegarLoop]: Abstraction has 3102 states and 3109 transitions. [2018-04-13 08:30:06,477 INFO L460 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-04-13 08:30:06,477 INFO L276 IsEmpty]: Start isEmpty. Operand 3102 states and 3109 transitions. [2018-04-13 08:30:06,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3138 [2018-04-13 08:30:06,510 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:30:06,510 INFO L355 BasicCegarLoop]: trace histogram [493, 465, 465, 464, 464, 464, 29, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:30:06,510 INFO L408 AbstractCegarLoop]: === Iteration 71 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:30:06,511 INFO L82 PathProgramCache]: Analyzing trace with hash -271341206, now seen corresponding path program 63 times [2018-04-13 08:30:06,511 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:30:06,511 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:30:06,511 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:30:06,511 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:30:06,511 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:30:06,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:30:06,741 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:30:10,215 INFO L134 CoverageAnalysis]: Checked inductivity of 677068 backedges. 84261 proven. 2469 refuted. 0 times theorem prover too weak. 590338 trivial. 0 not checked. [2018-04-13 08:30:10,216 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:30:10,216 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:30:10,216 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:30:10,792 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 31 check-sat command(s) [2018-04-13 08:30:10,793 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:30:10,951 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:30:10,953 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:30:10,953 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:30:10,955 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:30:10,955 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:30:21,619 INFO L134 CoverageAnalysis]: Checked inductivity of 677068 backedges. 81620 proven. 2730 refuted. 0 times theorem prover too weak. 592718 trivial. 0 not checked. [2018-04-13 08:30:21,619 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:30:21,620 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 36] total 99 [2018-04-13 08:30:21,620 INFO L442 AbstractCegarLoop]: Interpolant automaton has 99 states [2018-04-13 08:30:21,621 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 99 interpolants. [2018-04-13 08:30:21,621 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1566, Invalid=8136, Unknown=0, NotChecked=0, Total=9702 [2018-04-13 08:30:21,621 INFO L87 Difference]: Start difference. First operand 3102 states and 3109 transitions. Second operand 99 states. [2018-04-13 08:30:27,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:30:27,437 INFO L93 Difference]: Finished difference Result 3519 states and 3532 transitions. [2018-04-13 08:30:27,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 128 states. [2018-04-13 08:30:27,438 INFO L78 Accepts]: Start accepts. Automaton has 99 states. Word has length 3137 [2018-04-13 08:30:27,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:30:27,441 INFO L225 Difference]: With dead ends: 3519 [2018-04-13 08:30:27,441 INFO L226 Difference]: Without dead ends: 3519 [2018-04-13 08:30:27,443 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3325 GetRequests, 3049 SyntacticMatches, 55 SemanticMatches, 221 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16504 ImplicationChecksByTransitivity, 7.1s TimeCoverageRelationStatistics Valid=8429, Invalid=41077, Unknown=0, NotChecked=0, Total=49506 [2018-04-13 08:30:27,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3519 states. [2018-04-13 08:30:27,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3519 to 3498. [2018-04-13 08:30:27,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3498 states. [2018-04-13 08:30:27,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3498 states to 3498 states and 3511 transitions. [2018-04-13 08:30:27,456 INFO L78 Accepts]: Start accepts. Automaton has 3498 states and 3511 transitions. Word has length 3137 [2018-04-13 08:30:27,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:30:27,457 INFO L459 AbstractCegarLoop]: Abstraction has 3498 states and 3511 transitions. [2018-04-13 08:30:27,457 INFO L460 AbstractCegarLoop]: Interpolant automaton has 99 states. [2018-04-13 08:30:27,457 INFO L276 IsEmpty]: Start isEmpty. Operand 3498 states and 3511 transitions. [2018-04-13 08:30:27,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3324 [2018-04-13 08:30:27,493 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:30:27,494 INFO L355 BasicCegarLoop]: trace histogram [523, 494, 494, 493, 493, 493, 30, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:30:27,494 INFO L408 AbstractCegarLoop]: === Iteration 72 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:30:27,494 INFO L82 PathProgramCache]: Analyzing trace with hash -60354669, now seen corresponding path program 64 times [2018-04-13 08:30:27,494 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:30:27,494 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:30:27,494 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:30:27,495 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:30:27,495 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:30:27,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:30:27,718 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:30:31,865 INFO L134 CoverageAnalysis]: Checked inductivity of 763309 backedges. 216957 proven. 21667 refuted. 0 times theorem prover too weak. 524685 trivial. 0 not checked. [2018-04-13 08:30:31,866 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:30:31,866 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:30:31,866 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:30:32,139 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:30:32,139 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:30:32,179 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:30:36,047 INFO L134 CoverageAnalysis]: Checked inductivity of 763309 backedges. 235133 proven. 2324 refuted. 0 times theorem prover too weak. 525852 trivial. 0 not checked. [2018-04-13 08:30:36,047 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:30:36,048 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 60] total 118 [2018-04-13 08:30:36,049 INFO L442 AbstractCegarLoop]: Interpolant automaton has 118 states [2018-04-13 08:30:36,049 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 118 interpolants. [2018-04-13 08:30:36,050 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2237, Invalid=11569, Unknown=0, NotChecked=0, Total=13806 [2018-04-13 08:30:36,050 INFO L87 Difference]: Start difference. First operand 3498 states and 3511 transitions. Second operand 118 states. [2018-04-13 08:30:40,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:30:40,077 INFO L93 Difference]: Finished difference Result 3309 states and 3316 transitions. [2018-04-13 08:30:40,077 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 115 states. [2018-04-13 08:30:40,077 INFO L78 Accepts]: Start accepts. Automaton has 118 states. Word has length 3323 [2018-04-13 08:30:40,078 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:30:40,081 INFO L225 Difference]: With dead ends: 3309 [2018-04-13 08:30:40,081 INFO L226 Difference]: Without dead ends: 3300 [2018-04-13 08:30:40,083 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3471 GetRequests, 3271 SyntacticMatches, 0 SemanticMatches, 200 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13982 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=6368, Invalid=34234, Unknown=0, NotChecked=0, Total=40602 [2018-04-13 08:30:40,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3300 states. [2018-04-13 08:30:40,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3300 to 3294. [2018-04-13 08:30:40,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3294 states. [2018-04-13 08:30:40,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3294 states to 3294 states and 3301 transitions. [2018-04-13 08:30:40,097 INFO L78 Accepts]: Start accepts. Automaton has 3294 states and 3301 transitions. Word has length 3323 [2018-04-13 08:30:40,097 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:30:40,097 INFO L459 AbstractCegarLoop]: Abstraction has 3294 states and 3301 transitions. [2018-04-13 08:30:40,097 INFO L460 AbstractCegarLoop]: Interpolant automaton has 118 states. [2018-04-13 08:30:40,098 INFO L276 IsEmpty]: Start isEmpty. Operand 3294 states and 3301 transitions. [2018-04-13 08:30:40,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3330 [2018-04-13 08:30:40,134 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:30:40,134 INFO L355 BasicCegarLoop]: trace histogram [524, 495, 495, 494, 494, 494, 30, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:30:40,134 INFO L408 AbstractCegarLoop]: === Iteration 73 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:30:40,135 INFO L82 PathProgramCache]: Analyzing trace with hash -1987098981, now seen corresponding path program 65 times [2018-04-13 08:30:40,135 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:30:40,135 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:30:40,135 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:30:40,135 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:30:40,135 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:30:40,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:30:40,396 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:30:44,553 INFO L134 CoverageAnalysis]: Checked inductivity of 766329 backedges. 224640 proven. 17010 refuted. 0 times theorem prover too weak. 524679 trivial. 0 not checked. [2018-04-13 08:30:44,553 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:30:44,553 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:30:44,554 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:31:43,067 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 74 check-sat command(s) [2018-04-13 08:31:43,067 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:31:49,880 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:31:54,477 INFO L134 CoverageAnalysis]: Checked inductivity of 766329 backedges. 169959 proven. 17263 refuted. 0 times theorem prover too weak. 579107 trivial. 0 not checked. [2018-04-13 08:31:54,478 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:31:54,478 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 65] total 124 [2018-04-13 08:31:54,479 INFO L442 AbstractCegarLoop]: Interpolant automaton has 124 states [2018-04-13 08:31:54,479 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 124 interpolants. [2018-04-13 08:31:54,480 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2316, Invalid=12936, Unknown=0, NotChecked=0, Total=15252 [2018-04-13 08:31:54,480 INFO L87 Difference]: Start difference. First operand 3294 states and 3301 transitions. Second operand 124 states. [2018-04-13 08:31:58,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:31:58,294 INFO L93 Difference]: Finished difference Result 3306 states and 3311 transitions. [2018-04-13 08:31:58,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 121 states. [2018-04-13 08:31:58,294 INFO L78 Accepts]: Start accepts. Automaton has 124 states. Word has length 3329 [2018-04-13 08:31:58,295 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:31:58,298 INFO L225 Difference]: With dead ends: 3306 [2018-04-13 08:31:58,298 INFO L226 Difference]: Without dead ends: 3300 [2018-04-13 08:31:58,300 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3486 GetRequests, 3273 SyntacticMatches, 0 SemanticMatches, 213 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15469 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=7515, Invalid=38495, Unknown=0, NotChecked=0, Total=46010 [2018-04-13 08:31:58,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3300 states. [2018-04-13 08:31:58,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3300 to 3294. [2018-04-13 08:31:58,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3294 states. [2018-04-13 08:31:58,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3294 states to 3294 states and 3299 transitions. [2018-04-13 08:31:58,313 INFO L78 Accepts]: Start accepts. Automaton has 3294 states and 3299 transitions. Word has length 3329 [2018-04-13 08:31:58,314 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:31:58,314 INFO L459 AbstractCegarLoop]: Abstraction has 3294 states and 3299 transitions. [2018-04-13 08:31:58,314 INFO L460 AbstractCegarLoop]: Interpolant automaton has 124 states. [2018-04-13 08:31:58,314 INFO L276 IsEmpty]: Start isEmpty. Operand 3294 states and 3299 transitions. [2018-04-13 08:31:58,350 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3336 [2018-04-13 08:31:58,350 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:31:58,350 INFO L355 BasicCegarLoop]: trace histogram [525, 496, 496, 495, 495, 495, 30, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:31:58,350 INFO L408 AbstractCegarLoop]: === Iteration 74 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:31:58,351 INFO L82 PathProgramCache]: Analyzing trace with hash -1420632349, now seen corresponding path program 66 times [2018-04-13 08:31:58,351 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:31:58,351 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:31:58,351 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:31:58,351 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:31:58,351 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:31:58,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:31:58,594 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:32:02,315 INFO L134 CoverageAnalysis]: Checked inductivity of 769355 backedges. 92867 proven. 2644 refuted. 0 times theorem prover too weak. 673844 trivial. 0 not checked. [2018-04-13 08:32:02,315 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:32:02,316 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:32:02,316 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:32:08,045 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 59 check-sat command(s) [2018-04-13 08:32:08,045 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:32:08,368 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:32:08,370 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:32:08,371 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:32:08,378 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:32:08,378 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:32:20,894 INFO L134 CoverageAnalysis]: Checked inductivity of 769355 backedges. 142824 proven. 37501 refuted. 0 times theorem prover too weak. 589030 trivial. 0 not checked. [2018-04-13 08:32:20,894 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:32:20,895 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 44] total 109 [2018-04-13 08:32:20,895 INFO L442 AbstractCegarLoop]: Interpolant automaton has 109 states [2018-04-13 08:32:20,896 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 109 interpolants. [2018-04-13 08:32:20,896 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1966, Invalid=9806, Unknown=0, NotChecked=0, Total=11772 [2018-04-13 08:32:20,896 INFO L87 Difference]: Start difference. First operand 3294 states and 3299 transitions. Second operand 109 states. [2018-04-13 08:32:26,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:32:26,997 INFO L93 Difference]: Finished difference Result 3494 states and 3500 transitions. [2018-04-13 08:32:26,997 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 153 states. [2018-04-13 08:32:26,997 INFO L78 Accepts]: Start accepts. Automaton has 109 states. Word has length 3335 [2018-04-13 08:32:26,998 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:32:27,002 INFO L225 Difference]: With dead ends: 3494 [2018-04-13 08:32:27,002 INFO L226 Difference]: Without dead ends: 3494 [2018-04-13 08:32:27,004 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3519 GetRequests, 3237 SyntacticMatches, 56 SemanticMatches, 226 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20452 ImplicationChecksByTransitivity, 8.1s TimeCoverageRelationStatistics Valid=8099, Invalid=43657, Unknown=0, NotChecked=0, Total=51756 [2018-04-13 08:32:27,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3494 states. [2018-04-13 08:32:27,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3494 to 3492. [2018-04-13 08:32:27,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3492 states. [2018-04-13 08:32:27,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3492 states to 3492 states and 3498 transitions. [2018-04-13 08:32:27,019 INFO L78 Accepts]: Start accepts. Automaton has 3492 states and 3498 transitions. Word has length 3335 [2018-04-13 08:32:27,020 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:32:27,020 INFO L459 AbstractCegarLoop]: Abstraction has 3492 states and 3498 transitions. [2018-04-13 08:32:27,020 INFO L460 AbstractCegarLoop]: Interpolant automaton has 109 states. [2018-04-13 08:32:27,020 INFO L276 IsEmpty]: Start isEmpty. Operand 3492 states and 3498 transitions. [2018-04-13 08:32:27,098 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3528 [2018-04-13 08:32:27,098 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:32:27,099 INFO L355 BasicCegarLoop]: trace histogram [556, 526, 526, 525, 525, 525, 31, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:32:27,099 INFO L408 AbstractCegarLoop]: === Iteration 75 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:32:27,100 INFO L82 PathProgramCache]: Analyzing trace with hash 970302484, now seen corresponding path program 67 times [2018-04-13 08:32:27,100 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:32:27,100 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:32:27,101 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:32:27,101 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:32:27,101 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:32:27,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:32:27,299 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:32:31,869 INFO L134 CoverageAnalysis]: Checked inductivity of 864330 backedges. 238794 proven. 22329 refuted. 0 times theorem prover too weak. 603207 trivial. 0 not checked. [2018-04-13 08:32:31,869 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:32:31,869 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:32:31,869 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:32:32,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:32:32,254 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:32:37,352 INFO L134 CoverageAnalysis]: Checked inductivity of 864330 backedges. 238871 proven. 22252 refuted. 0 times theorem prover too weak. 603207 trivial. 0 not checked. [2018-04-13 08:32:37,353 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:32:37,353 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 67] total 126 [2018-04-13 08:32:37,354 INFO L442 AbstractCegarLoop]: Interpolant automaton has 126 states [2018-04-13 08:32:37,354 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 126 interpolants. [2018-04-13 08:32:37,355 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2822, Invalid=12928, Unknown=0, NotChecked=0, Total=15750 [2018-04-13 08:32:37,355 INFO L87 Difference]: Start difference. First operand 3492 states and 3498 transitions. Second operand 126 states. [2018-04-13 08:32:40,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:32:40,181 INFO L93 Difference]: Finished difference Result 3506 states and 3510 transitions. [2018-04-13 08:32:40,181 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-04-13 08:32:40,181 INFO L78 Accepts]: Start accepts. Automaton has 126 states. Word has length 3527 [2018-04-13 08:32:40,182 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:32:40,185 INFO L225 Difference]: With dead ends: 3506 [2018-04-13 08:32:40,185 INFO L226 Difference]: Without dead ends: 3500 [2018-04-13 08:32:40,187 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3683 GetRequests, 3471 SyntacticMatches, 0 SemanticMatches, 212 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13354 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=8820, Invalid=36762, Unknown=0, NotChecked=0, Total=45582 [2018-04-13 08:32:40,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3500 states. [2018-04-13 08:32:40,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3500 to 3492. [2018-04-13 08:32:40,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3492 states. [2018-04-13 08:32:40,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3492 states to 3492 states and 3496 transitions. [2018-04-13 08:32:40,202 INFO L78 Accepts]: Start accepts. Automaton has 3492 states and 3496 transitions. Word has length 3527 [2018-04-13 08:32:40,203 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:32:40,203 INFO L459 AbstractCegarLoop]: Abstraction has 3492 states and 3496 transitions. [2018-04-13 08:32:40,203 INFO L460 AbstractCegarLoop]: Interpolant automaton has 126 states. [2018-04-13 08:32:40,203 INFO L276 IsEmpty]: Start isEmpty. Operand 3492 states and 3496 transitions. [2018-04-13 08:32:40,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3534 [2018-04-13 08:32:40,244 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:32:40,244 INFO L355 BasicCegarLoop]: trace histogram [557, 527, 527, 526, 526, 526, 31, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:32:40,244 INFO L408 AbstractCegarLoop]: === Iteration 76 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:32:40,244 INFO L82 PathProgramCache]: Analyzing trace with hash 863075740, now seen corresponding path program 68 times [2018-04-13 08:32:40,244 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:32:40,244 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:32:40,245 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:32:40,245 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:32:40,245 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:32:40,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:32:40,526 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:32:45,364 INFO L134 CoverageAnalysis]: Checked inductivity of 867544 backedges. 96000 proven. 2914 refuted. 0 times theorem prover too weak. 768630 trivial. 0 not checked. [2018-04-13 08:32:45,364 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:32:45,364 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:32:45,365 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:32:45,715 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:32:45,715 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:32:45,747 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:32:45,749 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-13 08:32:45,749 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-13 08:32:45,753 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-13 08:32:45,753 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-13 08:32:57,310 INFO L134 CoverageAnalysis]: Checked inductivity of 867544 backedges. 96000 proven. 2914 refuted. 0 times theorem prover too weak. 768630 trivial. 0 not checked. [2018-04-13 08:32:57,310 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:32:57,311 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 37] total 38 [2018-04-13 08:32:57,311 INFO L442 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-04-13 08:32:57,311 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-04-13 08:32:57,311 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=641, Invalid=841, Unknown=0, NotChecked=0, Total=1482 [2018-04-13 08:32:57,312 INFO L87 Difference]: Start difference. First operand 3492 states and 3496 transitions. Second operand 39 states. [2018-04-13 08:32:58,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:32:58,197 INFO L93 Difference]: Finished difference Result 3509 states and 3514 transitions. [2018-04-13 08:32:58,198 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-04-13 08:32:58,198 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 3533 [2018-04-13 08:32:58,199 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:32:58,202 INFO L225 Difference]: With dead ends: 3509 [2018-04-13 08:32:58,202 INFO L226 Difference]: Without dead ends: 3509 [2018-04-13 08:32:58,203 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3601 GetRequests, 3470 SyntacticMatches, 62 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 741 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1826, Invalid=3144, Unknown=0, NotChecked=0, Total=4970 [2018-04-13 08:32:58,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3509 states. [2018-04-13 08:32:58,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3509 to 3498. [2018-04-13 08:32:58,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3498 states. [2018-04-13 08:32:58,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3498 states to 3498 states and 3503 transitions. [2018-04-13 08:32:58,221 INFO L78 Accepts]: Start accepts. Automaton has 3498 states and 3503 transitions. Word has length 3533 [2018-04-13 08:32:58,222 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:32:58,222 INFO L459 AbstractCegarLoop]: Abstraction has 3498 states and 3503 transitions. [2018-04-13 08:32:58,222 INFO L460 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-04-13 08:32:58,222 INFO L276 IsEmpty]: Start isEmpty. Operand 3498 states and 3503 transitions. [2018-04-13 08:32:58,264 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3540 [2018-04-13 08:32:58,264 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:32:58,264 INFO L355 BasicCegarLoop]: trace histogram [558, 528, 528, 527, 527, 527, 31, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:32:58,264 INFO L408 AbstractCegarLoop]: === Iteration 77 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:32:58,265 INFO L82 PathProgramCache]: Analyzing trace with hash 1982883940, now seen corresponding path program 69 times [2018-04-13 08:32:58,265 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:32:58,265 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:32:58,265 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:32:58,265 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:32:58,265 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:32:58,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:32:58,542 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:02,791 INFO L134 CoverageAnalysis]: Checked inductivity of 870764 backedges. 102039 proven. 2825 refuted. 0 times theorem prover too weak. 765900 trivial. 0 not checked. [2018-04-13 08:33:02,791 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:02,791 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:02,792 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:33:03,614 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2018-04-13 08:33:03,614 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:03,726 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:09,546 INFO L134 CoverageAnalysis]: Checked inductivity of 870764 backedges. 185229 proven. 9110 refuted. 0 times theorem prover too weak. 676425 trivial. 0 not checked. [2018-04-13 08:33:09,546 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:09,547 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 72] total 135 [2018-04-13 08:33:09,547 INFO L442 AbstractCegarLoop]: Interpolant automaton has 135 states [2018-04-13 08:33:09,547 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 135 interpolants. [2018-04-13 08:33:09,548 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2879, Invalid=15211, Unknown=0, NotChecked=0, Total=18090 [2018-04-13 08:33:09,548 INFO L87 Difference]: Start difference. First operand 3498 states and 3503 transitions. Second operand 135 states. [2018-04-13 08:33:13,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:13,816 INFO L93 Difference]: Finished difference Result 3718 states and 3724 transitions. [2018-04-13 08:33:13,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 164 states. [2018-04-13 08:33:13,816 INFO L78 Accepts]: Start accepts. Automaton has 135 states. Word has length 3539 [2018-04-13 08:33:13,818 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:13,820 INFO L225 Difference]: With dead ends: 3718 [2018-04-13 08:33:13,820 INFO L226 Difference]: Without dead ends: 3718 [2018-04-13 08:33:13,823 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3732 GetRequests, 3473 SyntacticMatches, 0 SemanticMatches, 259 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18104 ImplicationChecksByTransitivity, 5.7s TimeCoverageRelationStatistics Valid=9709, Invalid=58151, Unknown=0, NotChecked=0, Total=67860 [2018-04-13 08:33:13,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3718 states. [2018-04-13 08:33:13,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3718 to 3708. [2018-04-13 08:33:13,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3708 states. [2018-04-13 08:33:13,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3708 states to 3708 states and 3714 transitions. [2018-04-13 08:33:13,837 INFO L78 Accepts]: Start accepts. Automaton has 3708 states and 3714 transitions. Word has length 3539 [2018-04-13 08:33:13,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:13,838 INFO L459 AbstractCegarLoop]: Abstraction has 3708 states and 3714 transitions. [2018-04-13 08:33:13,839 INFO L460 AbstractCegarLoop]: Interpolant automaton has 135 states. [2018-04-13 08:33:13,839 INFO L276 IsEmpty]: Start isEmpty. Operand 3708 states and 3714 transitions. [2018-04-13 08:33:13,895 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3744 [2018-04-13 08:33:13,895 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:13,895 INFO L355 BasicCegarLoop]: trace histogram [591, 560, 560, 559, 559, 559, 32, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:13,895 INFO L408 AbstractCegarLoop]: === Iteration 78 === [__U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_read_c__fooErr1RequiresViolation, mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX]=== [2018-04-13 08:33:13,895 INFO L82 PathProgramCache]: Analyzing trace with hash -1634918299, now seen corresponding path program 70 times [2018-04-13 08:33:13,896 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:13,896 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:13,896 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:13,896 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:13,896 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:14,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-04-13 08:33:15,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-04-13 08:33:16,438 INFO L421 BasicCegarLoop]: Counterexample might be feasible [2018-04-13 08:33:16,998 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 13.04 08:33:16 BoogieIcfgContainer [2018-04-13 08:33:16,998 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-04-13 08:33:16,999 INFO L168 Benchmark]: Toolchain (without parser) took 639314.47 ms. Allocated memory was 403.7 MB in the beginning and 3.1 GB in the end (delta: 2.7 GB). Free memory was 342.8 MB in the beginning and 478.9 MB in the end (delta: -136.1 MB). Peak memory consumption was 2.6 GB. Max. memory is 5.3 GB. [2018-04-13 08:33:17,000 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 403.7 MB. Free memory is still 361.3 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-04-13 08:33:17,000 INFO L168 Benchmark]: CACSL2BoogieTranslator took 147.72 ms. Allocated memory is still 403.7 MB. Free memory was 342.8 MB in the beginning and 332.2 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. [2018-04-13 08:33:17,000 INFO L168 Benchmark]: Boogie Preprocessor took 24.74 ms. Allocated memory is still 403.7 MB. Free memory is still 332.2 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-04-13 08:33:17,000 INFO L168 Benchmark]: RCFGBuilder took 219.99 ms. Allocated memory was 403.7 MB in the beginning and 619.2 MB in the end (delta: 215.5 MB). Free memory was 332.2 MB in the beginning and 581.7 MB in the end (delta: -249.5 MB). Peak memory consumption was 25.5 MB. Max. memory is 5.3 GB. [2018-04-13 08:33:17,001 INFO L168 Benchmark]: TraceAbstraction took 638919.24 ms. Allocated memory was 619.2 MB in the beginning and 3.1 GB in the end (delta: 2.5 GB). Free memory was 581.7 MB in the beginning and 478.9 MB in the end (delta: 102.8 MB). Peak memory consumption was 2.6 GB. Max. memory is 5.3 GB. [2018-04-13 08:33:17,002 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 403.7 MB. Free memory is still 361.3 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 147.72 ms. Allocated memory is still 403.7 MB. Free memory was 342.8 MB in the beginning and 332.2 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 24.74 ms. Allocated memory is still 403.7 MB. Free memory is still 332.2 MB. There was no memory consumed. Max. memory is 5.3 GB. * RCFGBuilder took 219.99 ms. Allocated memory was 403.7 MB in the beginning and 619.2 MB in the end (delta: 215.5 MB). Free memory was 332.2 MB in the beginning and 581.7 MB in the end (delta: -249.5 MB). Peak memory consumption was 25.5 MB. Max. memory is 5.3 GB. * TraceAbstraction took 638919.24 ms. Allocated memory was 619.2 MB in the beginning and 3.1 GB in the end (delta: 2.5 GB). Free memory was 581.7 MB in the beginning and 478.9 MB in the end (delta: 102.8 MB). Peak memory consumption was 2.6 GB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: pointer dereference may fail pointer dereference may fail We found a FailurePath: [L24] int i, b[32]; [L25] FCALL char mask[32]; VAL [mask={64:0}] [L26] i = 0 VAL [i=0, mask={64:0}] [L26] COND TRUE i < sizeof(mask) VAL [i=0, mask={64:0}] [L27] EXPR b[i] VAL [i=0, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=0, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=0, b={64:0}, b={64:0}, i=0, size=0] [L17] COND TRUE i <= size + 1 VAL [\old(size)=0, b={64:0}, b={64:0}, i=0, size=0] [L18] EXPR a[i] VAL [\old(size)=0, b={64:0}, b={64:0}, i=0, size=0] [L18] EXPR, FCALL b[i] VAL [\old(size)=0, b={64:0}, b={64:0}, b[i]=34, i=0, size=0] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=0, b={64:0}, b={64:0}, i=1, size=0] [L18] EXPR a[i] VAL [\old(size)=0, b={64:0}, b={64:0}, i=1, size=0] [L18] EXPR, FCALL b[i] VAL [\old(size)=0, b={64:0}, b={64:0}, b[i]=67, i=1, size=0] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=0, b={64:0}, b={64:0}, i=2, size=0] [L20] RET return i; VAL [\old(size)=0, \result=2, b={64:0}, b={64:0}, i=2, size=0] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=2, i=0, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=1, mask={64:0}] [L27] EXPR b[i] VAL [i=1, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=1, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={64:0}, b={64:0}, i=0, size=1] [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={64:0}, b={64:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={64:0}, b={64:0}, i=0, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={64:0}, b={64:0}, b[i]=34, i=0, size=1] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={64:0}, b={64:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={64:0}, b={64:0}, i=1, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={64:0}, b={64:0}, b[i]=67, i=1, size=1] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=1, b={64:0}, b={64:0}, i=2, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={64:0}, b={64:0}, i=2, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={64:0}, b={64:0}, b[i]=33, i=2, size=1] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=1, b={64:0}, b={64:0}, i=3, size=1] [L20] RET return i; VAL [\old(size)=1, \result=3, b={64:0}, b={64:0}, i=3, size=1] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=3, i=1, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=2, mask={64:0}] [L27] EXPR b[i] VAL [i=2, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=2, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={64:0}, b={64:0}, i=0, size=2] [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={64:0}, b={64:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={64:0}, b={64:0}, i=0, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={64:0}, b={64:0}, b[i]=34, i=0, size=2] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={64:0}, b={64:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={64:0}, b={64:0}, i=1, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={64:0}, b={64:0}, b[i]=67, i=1, size=2] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={64:0}, b={64:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={64:0}, b={64:0}, i=2, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={64:0}, b={64:0}, b[i]=33, i=2, size=2] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=2, b={64:0}, b={64:0}, i=3, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={64:0}, b={64:0}, i=3, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={64:0}, b={64:0}, b[i]=43, i=3, size=2] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=2, b={64:0}, b={64:0}, i=4, size=2] [L20] RET return i; VAL [\old(size)=2, \result=4, b={64:0}, b={64:0}, i=4, size=2] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=4, i=2, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=3, mask={64:0}] [L27] EXPR b[i] VAL [i=3, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=3, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={64:0}, b={64:0}, i=0, size=3] [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={64:0}, b={64:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={64:0}, b={64:0}, i=0, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={64:0}, b={64:0}, b[i]=34, i=0, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={64:0}, b={64:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={64:0}, b={64:0}, i=1, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={64:0}, b={64:0}, b[i]=67, i=1, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={64:0}, b={64:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={64:0}, b={64:0}, i=2, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={64:0}, b={64:0}, b[i]=33, i=2, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={64:0}, b={64:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={64:0}, b={64:0}, i=3, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={64:0}, b={64:0}, b[i]=43, i=3, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=3, b={64:0}, b={64:0}, i=4, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={64:0}, b={64:0}, i=4, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={64:0}, b={64:0}, b[i]=55, i=4, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=3, b={64:0}, b={64:0}, i=5, size=3] [L20] RET return i; VAL [\old(size)=3, \result=5, b={64:0}, b={64:0}, i=5, size=3] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=5, i=3, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=4, mask={64:0}] [L27] EXPR b[i] VAL [i=4, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=4, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={64:0}, b={64:0}, i=0, size=4] [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={64:0}, b={64:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={64:0}, b={64:0}, i=0, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={64:0}, b={64:0}, b[i]=34, i=0, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={64:0}, b={64:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={64:0}, b={64:0}, i=1, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={64:0}, b={64:0}, b[i]=67, i=1, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={64:0}, b={64:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={64:0}, b={64:0}, i=2, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={64:0}, b={64:0}, b[i]=33, i=2, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={64:0}, b={64:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={64:0}, b={64:0}, i=3, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={64:0}, b={64:0}, b[i]=43, i=3, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={64:0}, b={64:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={64:0}, b={64:0}, i=4, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={64:0}, b={64:0}, b[i]=55, i=4, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=4, b={64:0}, b={64:0}, i=5, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={64:0}, b={64:0}, i=5, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={64:0}, b={64:0}, b[i]=46, i=5, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=4, b={64:0}, b={64:0}, i=6, size=4] [L20] RET return i; VAL [\old(size)=4, \result=6, b={64:0}, b={64:0}, i=6, size=4] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=6, i=4, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=5, mask={64:0}] [L27] EXPR b[i] VAL [i=5, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=5, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={64:0}, b={64:0}, i=0, size=5] [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={64:0}, b={64:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={64:0}, b={64:0}, i=0, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={64:0}, b={64:0}, b[i]=34, i=0, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={64:0}, b={64:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={64:0}, b={64:0}, i=1, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={64:0}, b={64:0}, b[i]=67, i=1, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={64:0}, b={64:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={64:0}, b={64:0}, i=2, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={64:0}, b={64:0}, b[i]=33, i=2, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={64:0}, b={64:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={64:0}, b={64:0}, i=3, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={64:0}, b={64:0}, b[i]=43, i=3, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={64:0}, b={64:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={64:0}, b={64:0}, i=4, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={64:0}, b={64:0}, b[i]=55, i=4, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={64:0}, b={64:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={64:0}, b={64:0}, i=5, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={64:0}, b={64:0}, b[i]=46, i=5, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=5, b={64:0}, b={64:0}, i=6, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={64:0}, b={64:0}, i=6, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={64:0}, b={64:0}, b[i]=41, i=6, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=5, b={64:0}, b={64:0}, i=7, size=5] [L20] RET return i; VAL [\old(size)=5, \result=7, b={64:0}, b={64:0}, i=7, size=5] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=7, i=5, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=6, mask={64:0}] [L27] EXPR b[i] VAL [i=6, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=6, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={64:0}, b={64:0}, i=0, size=6] [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=0, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=34, i=0, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=1, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=67, i=1, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=2, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=33, i=2, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=3, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=43, i=3, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=4, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=55, i=4, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=5, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=46, i=5, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=6, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=41, i=6, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=6, b={64:0}, b={64:0}, i=7, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={64:0}, b={64:0}, i=7, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={64:0}, b={64:0}, b[i]=60, i=7, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=6, b={64:0}, b={64:0}, i=8, size=6] [L20] RET return i; VAL [\old(size)=6, \result=8, b={64:0}, b={64:0}, i=8, size=6] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=8, i=6, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=7, mask={64:0}] [L27] EXPR b[i] VAL [i=7, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=7, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={64:0}, b={64:0}, i=0, size=7] [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=0, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=34, i=0, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=1, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=67, i=1, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=2, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=33, i=2, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=3, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=43, i=3, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=4, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=55, i=4, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=5, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=46, i=5, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=6, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=41, i=6, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=7, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=60, i=7, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=7, b={64:0}, b={64:0}, i=8, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={64:0}, b={64:0}, i=8, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={64:0}, b={64:0}, b[i]=47, i=8, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=7, b={64:0}, b={64:0}, i=9, size=7] [L20] RET return i; VAL [\old(size)=7, \result=9, b={64:0}, b={64:0}, i=9, size=7] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=9, i=7, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=8, mask={64:0}] [L27] EXPR b[i] VAL [i=8, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=8, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={64:0}, b={64:0}, i=0, size=8] [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=0, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=34, i=0, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=1, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=67, i=1, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=2, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=33, i=2, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=3, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=43, i=3, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=4, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=55, i=4, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=5, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=46, i=5, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=6, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=41, i=6, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=7, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=60, i=7, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=8, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=47, i=8, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=8, b={64:0}, b={64:0}, i=9, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={64:0}, b={64:0}, i=9, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={64:0}, b={64:0}, b[i]=49, i=9, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=8, b={64:0}, b={64:0}, i=10, size=8] [L20] RET return i; VAL [\old(size)=8, \result=10, b={64:0}, b={64:0}, i=10, size=8] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=10, i=8, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=9, mask={64:0}] [L27] EXPR b[i] VAL [i=9, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=9, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={64:0}, b={64:0}, i=0, size=9] [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=0, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=34, i=0, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=1, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=67, i=1, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=2, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=33, i=2, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=3, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=43, i=3, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=4, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=55, i=4, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=5, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=46, i=5, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=6, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=41, i=6, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=7, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=60, i=7, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=8, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=47, i=8, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=9, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=49, i=9, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=9, b={64:0}, b={64:0}, i=10, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={64:0}, b={64:0}, i=10, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={64:0}, b={64:0}, b[i]=44, i=10, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=9, b={64:0}, b={64:0}, i=11, size=9] [L20] RET return i; VAL [\old(size)=9, \result=11, b={64:0}, b={64:0}, i=11, size=9] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=11, i=9, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=10, mask={64:0}] [L27] EXPR b[i] VAL [i=10, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=10, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={64:0}, b={64:0}, i=0, size=10] [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=0, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=34, i=0, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=1, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=67, i=1, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=2, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=33, i=2, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=3, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=43, i=3, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=4, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=55, i=4, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=5, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=46, i=5, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=6, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=41, i=6, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=7, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=60, i=7, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=8, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=47, i=8, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=9, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=49, i=9, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=10, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=44, i=10, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=10, b={64:0}, b={64:0}, i=11, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={64:0}, b={64:0}, i=11, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={64:0}, b={64:0}, b[i]=65, i=11, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=10, b={64:0}, b={64:0}, i=12, size=10] [L20] RET return i; VAL [\old(size)=10, \result=12, b={64:0}, b={64:0}, i=12, size=10] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=12, i=10, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=11, mask={64:0}] [L27] EXPR b[i] VAL [i=11, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=11, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={64:0}, b={64:0}, i=0, size=11] [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=0, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=34, i=0, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=1, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=67, i=1, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=2, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=33, i=2, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=3, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=43, i=3, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=4, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=55, i=4, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=5, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=46, i=5, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=6, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=41, i=6, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=7, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=60, i=7, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=8, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=47, i=8, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=9, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=49, i=9, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=10, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=44, i=10, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=11, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=65, i=11, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=11, b={64:0}, b={64:0}, i=12, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={64:0}, b={64:0}, i=12, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={64:0}, b={64:0}, b[i]=62, i=12, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=11, b={64:0}, b={64:0}, i=13, size=11] [L20] RET return i; VAL [\old(size)=11, \result=13, b={64:0}, b={64:0}, i=13, size=11] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=13, i=11, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=12, mask={64:0}] [L27] EXPR b[i] VAL [i=12, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=12, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={64:0}, b={64:0}, i=0, size=12] [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=0, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=34, i=0, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=1, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=67, i=1, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=2, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=33, i=2, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=3, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=43, i=3, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=4, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=55, i=4, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=5, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=46, i=5, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=6, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=41, i=6, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=7, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=60, i=7, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=8, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=47, i=8, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=9, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=49, i=9, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=10, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=44, i=10, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=11, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=65, i=11, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=12, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=62, i=12, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=12, b={64:0}, b={64:0}, i=13, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={64:0}, b={64:0}, i=13, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={64:0}, b={64:0}, b[i]=66, i=13, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=12, b={64:0}, b={64:0}, i=14, size=12] [L20] RET return i; VAL [\old(size)=12, \result=14, b={64:0}, b={64:0}, i=14, size=12] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=14, i=12, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=13, mask={64:0}] [L27] EXPR b[i] VAL [i=13, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=13, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={64:0}, b={64:0}, i=0, size=13] [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=0, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=34, i=0, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=1, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=67, i=1, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=2, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=33, i=2, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=3, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=43, i=3, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=4, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=55, i=4, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=5, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=46, i=5, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=6, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=41, i=6, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=7, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=60, i=7, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=8, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=47, i=8, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=9, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=49, i=9, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=10, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=44, i=10, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=11, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=65, i=11, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=12, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=62, i=12, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=13, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=66, i=13, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=13, b={64:0}, b={64:0}, i=14, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={64:0}, b={64:0}, i=14, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={64:0}, b={64:0}, b[i]=45, i=14, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=13, b={64:0}, b={64:0}, i=15, size=13] [L20] RET return i; VAL [\old(size)=13, \result=15, b={64:0}, b={64:0}, i=15, size=13] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=15, i=13, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=14, mask={64:0}] [L27] EXPR b[i] VAL [i=14, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=14, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={64:0}, b={64:0}, i=0, size=14] [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=0, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=34, i=0, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=1, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=67, i=1, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=2, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=33, i=2, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=3, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=43, i=3, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=4, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=55, i=4, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=5, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=46, i=5, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=6, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=41, i=6, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=7, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=60, i=7, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=8, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=47, i=8, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=9, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=49, i=9, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=10, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=44, i=10, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=11, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=65, i=11, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=12, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=62, i=12, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=13, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=66, i=13, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=14, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=45, i=14, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=14, b={64:0}, b={64:0}, i=15, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={64:0}, b={64:0}, i=15, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={64:0}, b={64:0}, b[i]=48, i=15, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=14, b={64:0}, b={64:0}, i=16, size=14] [L20] RET return i; VAL [\old(size)=14, \result=16, b={64:0}, b={64:0}, i=16, size=14] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=16, i=14, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=15, mask={64:0}] [L27] EXPR b[i] VAL [i=15, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=15, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={64:0}, b={64:0}, i=0, size=15] [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=0, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=34, i=0, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=1, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=67, i=1, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=2, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=33, i=2, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=3, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=43, i=3, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=4, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=55, i=4, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=5, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=46, i=5, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=6, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=41, i=6, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=7, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=60, i=7, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=8, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=47, i=8, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=9, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=49, i=9, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=10, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=44, i=10, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=11, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=65, i=11, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=12, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=62, i=12, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=13, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=66, i=13, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=14, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=45, i=14, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=15, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=48, i=15, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=15, b={64:0}, b={64:0}, i=16, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={64:0}, b={64:0}, i=16, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={64:0}, b={64:0}, b[i]=57, i=16, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=15, b={64:0}, b={64:0}, i=17, size=15] [L20] RET return i; VAL [\old(size)=15, \result=17, b={64:0}, b={64:0}, i=17, size=15] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=17, i=15, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=16, mask={64:0}] [L27] EXPR b[i] VAL [i=16, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=16, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={64:0}, b={64:0}, i=0, size=16] [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=0, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=34, i=0, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=1, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=67, i=1, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=2, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=33, i=2, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=3, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=43, i=3, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=4, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=55, i=4, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=5, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=46, i=5, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=6, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=41, i=6, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=7, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=60, i=7, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=8, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=47, i=8, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=9, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=49, i=9, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=10, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=44, i=10, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=11, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=65, i=11, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=12, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=62, i=12, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=13, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=66, i=13, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=14, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=45, i=14, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=15, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=48, i=15, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=16, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=57, i=16, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=16, b={64:0}, b={64:0}, i=17, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={64:0}, b={64:0}, i=17, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={64:0}, b={64:0}, b[i]=36, i=17, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=16, b={64:0}, b={64:0}, i=18, size=16] [L20] RET return i; VAL [\old(size)=16, \result=18, b={64:0}, b={64:0}, i=18, size=16] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=18, i=16, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=17, mask={64:0}] [L27] EXPR b[i] VAL [i=17, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=17, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={64:0}, b={64:0}, i=0, size=17] [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=0, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=34, i=0, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=1, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=67, i=1, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=2, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=33, i=2, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=3, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=43, i=3, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=4, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=55, i=4, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=5, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=46, i=5, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=6, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=41, i=6, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=7, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=60, i=7, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=8, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=47, i=8, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=9, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=49, i=9, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=10, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=44, i=10, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=11, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=65, i=11, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=12, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=62, i=12, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=13, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=66, i=13, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=14, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=45, i=14, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=15, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=48, i=15, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=16, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=57, i=16, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=17, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=36, i=17, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=17, b={64:0}, b={64:0}, i=18, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={64:0}, b={64:0}, i=18, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={64:0}, b={64:0}, b[i]=56, i=18, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=17, b={64:0}, b={64:0}, i=19, size=17] [L20] RET return i; VAL [\old(size)=17, \result=19, b={64:0}, b={64:0}, i=19, size=17] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=19, i=17, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=18, mask={64:0}] [L27] EXPR b[i] VAL [i=18, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=18, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={64:0}, b={64:0}, i=0, size=18] [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=0, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=34, i=0, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=1, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=67, i=1, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=2, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=33, i=2, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=3, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=43, i=3, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=4, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=55, i=4, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=5, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=46, i=5, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=6, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=41, i=6, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=7, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=60, i=7, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=8, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=47, i=8, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=9, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=49, i=9, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=10, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=44, i=10, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=11, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=65, i=11, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=12, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=62, i=12, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=13, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=66, i=13, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=14, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=45, i=14, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=15, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=48, i=15, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=16, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=57, i=16, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=17, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=36, i=17, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=18, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=56, i=18, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=18, b={64:0}, b={64:0}, i=19, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={64:0}, b={64:0}, i=19, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={64:0}, b={64:0}, b[i]=58, i=19, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=18, b={64:0}, b={64:0}, i=20, size=18] [L20] RET return i; VAL [\old(size)=18, \result=20, b={64:0}, b={64:0}, i=20, size=18] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=20, i=18, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=19, mask={64:0}] [L27] EXPR b[i] VAL [i=19, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=19, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={64:0}, b={64:0}, i=0, size=19] [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=0, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=34, i=0, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=1, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=67, i=1, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=2, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=33, i=2, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=3, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=43, i=3, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=4, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=55, i=4, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=5, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=46, i=5, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=6, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=41, i=6, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=7, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=60, i=7, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=8, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=47, i=8, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=9, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=49, i=9, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=10, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=44, i=10, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=11, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=65, i=11, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=12, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=62, i=12, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=13, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=66, i=13, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=14, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=45, i=14, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=15, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=48, i=15, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=16, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=57, i=16, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=17, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=36, i=17, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=18, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=56, i=18, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=19, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=58, i=19, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=19, b={64:0}, b={64:0}, i=20, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={64:0}, b={64:0}, i=20, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={64:0}, b={64:0}, b[i]=51, i=20, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=19, b={64:0}, b={64:0}, i=21, size=19] [L20] RET return i; VAL [\old(size)=19, \result=21, b={64:0}, b={64:0}, i=21, size=19] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=21, i=19, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=20, mask={64:0}] [L27] EXPR b[i] VAL [i=20, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=20, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={64:0}, b={64:0}, i=0, size=20] [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=0, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=34, i=0, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=1, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=67, i=1, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=2, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=33, i=2, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=3, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=43, i=3, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=4, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=55, i=4, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=5, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=46, i=5, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=6, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=41, i=6, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=7, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=60, i=7, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=8, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=47, i=8, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=9, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=49, i=9, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=10, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=44, i=10, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=11, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=65, i=11, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=12, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=62, i=12, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=13, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=66, i=13, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=14, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=45, i=14, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=15, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=48, i=15, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=16, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=57, i=16, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=17, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=36, i=17, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=18, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=56, i=18, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=19, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=58, i=19, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=20, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=51, i=20, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=20, b={64:0}, b={64:0}, i=21, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={64:0}, b={64:0}, i=21, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={64:0}, b={64:0}, b[i]=35, i=21, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=20, b={64:0}, b={64:0}, i=22, size=20] [L20] RET return i; VAL [\old(size)=20, \result=22, b={64:0}, b={64:0}, i=22, size=20] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=22, i=20, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=21, mask={64:0}] [L27] EXPR b[i] VAL [i=21, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=21, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={64:0}, b={64:0}, i=0, size=21] [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=0, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=34, i=0, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=1, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=67, i=1, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=2, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=33, i=2, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=3, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=43, i=3, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=4, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=55, i=4, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=5, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=46, i=5, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=6, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=41, i=6, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=7, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=60, i=7, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=8, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=47, i=8, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=9, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=49, i=9, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=10, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=44, i=10, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=11, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=65, i=11, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=12, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=62, i=12, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=13, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=66, i=13, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=14, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=45, i=14, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=15, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=48, i=15, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=16, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=57, i=16, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=17, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=36, i=17, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=18, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=56, i=18, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=19, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=58, i=19, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=20, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=51, i=20, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=21, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=35, i=21, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=21, b={64:0}, b={64:0}, i=22, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={64:0}, b={64:0}, i=22, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={64:0}, b={64:0}, b[i]=42, i=22, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=21, b={64:0}, b={64:0}, i=23, size=21] [L20] RET return i; VAL [\old(size)=21, \result=23, b={64:0}, b={64:0}, i=23, size=21] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=23, i=21, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=22, mask={64:0}] [L27] EXPR b[i] VAL [i=22, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=22, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={64:0}, b={64:0}, i=0, size=22] [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=0, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=34, i=0, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=1, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=67, i=1, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=2, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=33, i=2, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=3, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=43, i=3, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=4, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=55, i=4, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=5, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=46, i=5, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=6, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=41, i=6, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=7, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=60, i=7, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=8, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=47, i=8, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=9, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=49, i=9, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=10, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=44, i=10, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=11, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=65, i=11, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=12, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=62, i=12, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=13, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=66, i=13, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=14, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=45, i=14, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=15, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=48, i=15, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=16, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=57, i=16, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=17, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=36, i=17, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=18, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=56, i=18, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=19, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=58, i=19, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=20, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=51, i=20, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=21, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=35, i=21, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=22, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=42, i=22, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=22, b={64:0}, b={64:0}, i=23, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={64:0}, b={64:0}, i=23, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={64:0}, b={64:0}, b[i]=54, i=23, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=22, b={64:0}, b={64:0}, i=24, size=22] [L20] RET return i; VAL [\old(size)=22, \result=24, b={64:0}, b={64:0}, i=24, size=22] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=24, i=22, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=23, mask={64:0}] [L27] EXPR b[i] VAL [i=23, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=23, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={64:0}, b={64:0}, i=0, size=23] [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=0, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=34, i=0, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=1, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=67, i=1, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=2, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=33, i=2, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=3, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=43, i=3, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=4, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=55, i=4, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=5, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=46, i=5, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=6, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=41, i=6, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=7, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=60, i=7, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=8, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=47, i=8, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=9, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=49, i=9, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=10, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=44, i=10, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=11, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=65, i=11, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=12, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=62, i=12, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=13, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=66, i=13, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=14, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=45, i=14, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=15, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=48, i=15, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=16, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=57, i=16, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=17, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=36, i=17, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=18, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=56, i=18, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=19, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=58, i=19, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=20, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=51, i=20, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=21, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=35, i=21, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=22, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=42, i=22, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=23, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=54, i=23, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=23, b={64:0}, b={64:0}, i=24, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={64:0}, b={64:0}, i=24, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={64:0}, b={64:0}, b[i]=63, i=24, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=23, b={64:0}, b={64:0}, i=25, size=23] [L20] RET return i; VAL [\old(size)=23, \result=25, b={64:0}, b={64:0}, i=25, size=23] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=25, i=23, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=24, mask={64:0}] [L27] EXPR b[i] VAL [i=24, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=24, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={64:0}, b={64:0}, i=0, size=24] [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=0, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=34, i=0, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=1, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=67, i=1, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=2, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=33, i=2, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=3, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=43, i=3, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=4, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=55, i=4, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=5, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=46, i=5, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=6, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=41, i=6, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=7, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=60, i=7, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=8, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=47, i=8, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=9, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=49, i=9, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=10, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=44, i=10, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=11, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=65, i=11, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=12, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=62, i=12, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=13, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=66, i=13, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=14, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=45, i=14, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=15, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=48, i=15, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=16, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=57, i=16, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=17, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=36, i=17, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=18, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=56, i=18, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=19, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=58, i=19, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=20, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=51, i=20, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=21, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=35, i=21, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=22, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=42, i=22, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=23, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=54, i=23, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=24, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=63, i=24, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=24, b={64:0}, b={64:0}, i=25, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={64:0}, b={64:0}, i=25, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={64:0}, b={64:0}, b[i]=61, i=25, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=24, b={64:0}, b={64:0}, i=26, size=24] [L20] RET return i; VAL [\old(size)=24, \result=26, b={64:0}, b={64:0}, i=26, size=24] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=26, i=24, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=25, mask={64:0}] [L27] EXPR b[i] VAL [i=25, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=25, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={64:0}, b={64:0}, i=0, size=25] [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=0, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=34, i=0, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=1, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=67, i=1, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=2, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=33, i=2, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=3, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=43, i=3, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=4, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=55, i=4, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=5, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=46, i=5, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=6, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=41, i=6, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=7, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=60, i=7, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=8, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=47, i=8, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=9, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=49, i=9, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=10, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=44, i=10, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=11, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=65, i=11, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=12, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=62, i=12, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=13, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=66, i=13, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=14, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=45, i=14, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=15, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=48, i=15, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=16, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=57, i=16, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=17, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=36, i=17, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=18, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=56, i=18, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=19, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=58, i=19, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=20, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=51, i=20, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=21, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=35, i=21, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=22, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=42, i=22, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=23, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=54, i=23, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=24, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=63, i=24, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=25, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=61, i=25, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=25, b={64:0}, b={64:0}, i=26, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={64:0}, b={64:0}, i=26, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={64:0}, b={64:0}, b[i]=52, i=26, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=25, b={64:0}, b={64:0}, i=27, size=25] [L20] RET return i; VAL [\old(size)=25, \result=27, b={64:0}, b={64:0}, i=27, size=25] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=27, i=25, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=26, mask={64:0}] [L27] EXPR b[i] VAL [i=26, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=26, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={64:0}, b={64:0}, i=0, size=26] [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=0, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=34, i=0, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=1, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=67, i=1, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=2, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=33, i=2, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=3, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=43, i=3, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=4, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=55, i=4, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=5, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=46, i=5, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=6, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=41, i=6, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=7, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=60, i=7, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=8, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=47, i=8, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=9, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=49, i=9, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=10, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=44, i=10, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=11, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=65, i=11, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=12, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=62, i=12, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=13, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=66, i=13, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=14, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=45, i=14, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=15, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=48, i=15, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=16, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=57, i=16, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=17, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=36, i=17, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=18, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=56, i=18, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=19, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=58, i=19, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=20, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=51, i=20, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=21, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=35, i=21, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=22, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=42, i=22, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=23, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=54, i=23, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=24, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=63, i=24, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=25, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=61, i=25, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=26, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=52, i=26, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=26, b={64:0}, b={64:0}, i=27, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={64:0}, b={64:0}, i=27, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={64:0}, b={64:0}, b[i]=38, i=27, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=26, b={64:0}, b={64:0}, i=28, size=26] [L20] RET return i; VAL [\old(size)=26, \result=28, b={64:0}, b={64:0}, i=28, size=26] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=28, i=26, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=27, mask={64:0}] [L27] EXPR b[i] VAL [i=27, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=27, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={64:0}, b={64:0}, i=0, size=27] [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=0, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=34, i=0, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=1, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=67, i=1, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=2, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=33, i=2, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=3, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=43, i=3, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=4, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=55, i=4, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=5, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=46, i=5, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=6, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=41, i=6, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=7, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=60, i=7, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=8, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=47, i=8, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=9, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=49, i=9, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=10, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=44, i=10, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=11, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=65, i=11, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=12, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=62, i=12, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=13, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=66, i=13, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=14, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=45, i=14, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=15, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=48, i=15, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=16, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=57, i=16, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=17, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=36, i=17, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=18, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=56, i=18, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=19, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=58, i=19, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=20, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=51, i=20, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=21, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=35, i=21, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=22, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=42, i=22, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=23, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=54, i=23, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=24, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=63, i=24, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=25, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=61, i=25, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=26, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=52, i=26, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=27, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=38, i=27, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=27, b={64:0}, b={64:0}, i=28, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={64:0}, b={64:0}, i=28, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={64:0}, b={64:0}, b[i]=39, i=28, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=27, b={64:0}, b={64:0}, i=29, size=27] [L20] RET return i; VAL [\old(size)=27, \result=29, b={64:0}, b={64:0}, i=29, size=27] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=29, i=27, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=28, mask={64:0}] [L27] EXPR b[i] VAL [i=28, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=28, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={64:0}, b={64:0}, i=0, size=28] [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=0, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=34, i=0, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=1, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=67, i=1, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=2, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=33, i=2, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=3, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=43, i=3, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=4, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=55, i=4, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=5, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=46, i=5, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=6, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=41, i=6, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=7, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=60, i=7, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=8, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=47, i=8, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=9, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=49, i=9, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=10, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=44, i=10, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=11, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=65, i=11, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=12, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=62, i=12, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=13, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=66, i=13, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=14, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=45, i=14, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=15, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=48, i=15, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=16, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=57, i=16, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=17, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=36, i=17, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=18, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=56, i=18, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=19, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=58, i=19, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=20, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=51, i=20, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=21, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=35, i=21, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=22, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=42, i=22, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=23, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=54, i=23, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=24, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=63, i=24, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=25, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=61, i=25, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=26, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=52, i=26, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=27, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=38, i=27, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=28, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=39, i=28, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=28, b={64:0}, b={64:0}, i=29, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={64:0}, b={64:0}, i=29, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={64:0}, b={64:0}, b[i]=40, i=29, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=28, b={64:0}, b={64:0}, i=30, size=28] [L20] RET return i; VAL [\old(size)=28, \result=30, b={64:0}, b={64:0}, i=30, size=28] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=30, i=28, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=29, mask={64:0}] [L27] EXPR b[i] VAL [i=29, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=29, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={64:0}, b={64:0}, i=0, size=29] [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=0, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=34, i=0, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=1, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=67, i=1, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=2, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=33, i=2, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=3, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=43, i=3, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=4, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=55, i=4, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=5, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=46, i=5, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=6, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=41, i=6, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=7, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=60, i=7, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=8, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=47, i=8, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=9, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=49, i=9, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=10, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=44, i=10, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=11, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=65, i=11, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=12, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=62, i=12, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=13, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=66, i=13, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=14, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=45, i=14, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=15, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=48, i=15, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=16, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=57, i=16, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=17, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=36, i=17, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=18, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=56, i=18, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=19, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=58, i=19, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=20, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=51, i=20, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=21, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=35, i=21, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=22, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=42, i=22, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=23, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=54, i=23, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=24, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=63, i=24, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=25, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=61, i=25, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=26, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=52, i=26, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=27, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=38, i=27, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=28, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=39, i=28, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=29, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=40, i=29, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=29, b={64:0}, b={64:0}, i=30, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={64:0}, b={64:0}, i=30, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={64:0}, b={64:0}, b[i]=37, i=30, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=29, b={64:0}, b={64:0}, i=31, size=29] [L20] RET return i; VAL [\old(size)=29, \result=31, b={64:0}, b={64:0}, i=31, size=29] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=31, i=29, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=30, mask={64:0}] [L27] EXPR b[i] VAL [i=30, mask={64:0}] [L27] CALL, EXPR foo(mask, i) VAL [\old(size)=30, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={64:0}, b={64:0}, i=0, size=30] [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=0, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=34, i=0, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=1, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=67, i=1, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=2, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=33, i=2, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=3, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=43, i=3, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=4, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=55, i=4, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=5, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=46, i=5, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=6, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=41, i=6, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=7, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=60, i=7, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=8, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=47, i=8, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=9, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=49, i=9, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=10, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=44, i=10, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=11, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=65, i=11, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=12, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=62, i=12, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=13, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=66, i=13, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=14, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=45, i=14, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=15, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=48, i=15, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=16, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=57, i=16, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=17, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=36, i=17, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=18, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=56, i=18, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=19, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=58, i=19, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=20, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=51, i=20, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=21, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=35, i=21, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=22, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=42, i=22, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=23, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=54, i=23, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=24, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=63, i=24, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=25, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=61, i=25, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=26, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=52, i=26, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=27, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=38, i=27, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=28, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=39, i=28, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=29, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=40, i=29, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=30, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=37, i=30, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=30, b={64:0}, b={64:0}, i=31, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={64:0}, b={64:0}, i=31, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={64:0}, b={64:0}, b[i]=53, i=31, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size + 1) VAL [\old(size)=30, b={64:0}, b={64:0}, i=32, size=30] [L20] RET return i; VAL [\old(size)=30, \result=32, b={64:0}, b={64:0}, i=32, size=30] [L27] EXPR foo(mask, i) VAL [foo(mask, i)=32, i=30, mask={64:0}] [L27] b[i] = foo(mask, i) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=31, mask={64:0}] [L27] b[i] VAL [i=31, mask={64:0}] [L27] CALL foo(mask, i) VAL [\old(size)=31, b={64:0}] [L15] char a[33]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={64:0}, b={64:0}, i=0, size=31] [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=0, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=34, i=0, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=1, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=67, i=1, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=2, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=33, i=2, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=3, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=43, i=3, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=4, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=55, i=4, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=5, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=46, i=5, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=6, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=41, i=6, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=7, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=60, i=7, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=8, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=47, i=8, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=9, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=49, i=9, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=10, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=44, i=10, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=11, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=65, i=11, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=12, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=62, i=12, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=13, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=66, i=13, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=14, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=45, i=14, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=15, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=48, i=15, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=16, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=57, i=16, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=17, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=36, i=17, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=18, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=56, i=18, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=19, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=58, i=19, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=20, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=51, i=20, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=21, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=35, i=21, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=22, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=42, i=22, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=23, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=54, i=23, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=24, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=63, i=24, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=25, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=61, i=25, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=26, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=52, i=26, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=27, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=38, i=27, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=28, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=39, i=28, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=29, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=40, i=29, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=30, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=37, i=30, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=31, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={64:0}, b={64:0}, b[i]=53, i=31, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size + 1 VAL [\old(size)=31, b={64:0}, b={64:0}, i=32, size=31] [L18] a[i] VAL [\old(size)=31, b={64:0}, b={64:0}, i=32, size=31] [L18] FCALL b[i] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 46 locations, 6 error locations. UNSAFE Result, 638.8s OverallTime, 78 OverallIterations, 591 TraceHistogramMax, 127.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3408 SDtfs, 65242 SDslu, 47488 SDs, 0 SdLazy, 170421 SolverSat, 9096 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 44.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 108618 GetRequests, 99899 SyntacticMatches, 965 SemanticMatches, 7754 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 339947 ImplicationChecksByTransitivity, 148.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3708occurred in iteration=77, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.6s AutomataMinimizationTime, 77 MinimizatonAttempts, 1319 StatesRemovedByMinimization, 74 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 1.1s SsaConstructionTime, 194.6s SatisfiabilityAnalysisTime, 237.8s InterpolantComputationTime, 214986 NumberOfCodeBlocks, 199003 NumberOfCodeBlocksAsserted, 1191 NumberOfCheckSat, 208163 ConstructedInterpolants, 36368 QuantifiedInterpolants, 1301514018 SizeOfPredicates, 302 NumberOfNonLiveVariables, 195491 ConjunctsInSsa, 2893 ConjunctsInUnsatCore, 147 InterpolantComputations, 7 PerfectInterpolantSequences, 30931616/31554100 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf_AutomizerC.xml/Csv-Benchmark-0-2018-04-13_08-33-17-012.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/ArraysWithLenghtAtDeclaration_false-valid-deref-read.c_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-04-13_08-33-17-012.csv Received shutdown request...