java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv --cacsl2boogietranslator.bitprecise.bitfields false -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c -------------------------------------------------------------------------------- This is Ultimate 0.1.23-408c70d-m [2018-04-13 08:33:18,620 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-04-13 08:33:18,622 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-04-13 08:33:18,635 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-04-13 08:33:18,635 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-04-13 08:33:18,636 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-04-13 08:33:18,637 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-04-13 08:33:18,639 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-04-13 08:33:18,640 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-04-13 08:33:18,641 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-04-13 08:33:18,642 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-04-13 08:33:18,642 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-04-13 08:33:18,643 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-04-13 08:33:18,643 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-04-13 08:33:18,644 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-04-13 08:33:18,646 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-04-13 08:33:18,647 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-04-13 08:33:18,648 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-04-13 08:33:18,649 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-04-13 08:33:18,650 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-04-13 08:33:18,652 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-04-13 08:33:18,652 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-04-13 08:33:18,652 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-04-13 08:33:18,653 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-04-13 08:33:18,654 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-04-13 08:33:18,655 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-04-13 08:33:18,655 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-04-13 08:33:18,655 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-04-13 08:33:18,656 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-04-13 08:33:18,656 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-04-13 08:33:18,657 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-04-13 08:33:18,657 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf [2018-04-13 08:33:18,667 INFO L110 SettingsManager]: Loading preferences was successful [2018-04-13 08:33:18,667 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-04-13 08:33:18,668 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-04-13 08:33:18,668 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-04-13 08:33:18,668 INFO L133 SettingsManager]: * Use SBE=true [2018-04-13 08:33:18,668 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-04-13 08:33:18,668 INFO L133 SettingsManager]: * sizeof long=4 [2018-04-13 08:33:18,669 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-04-13 08:33:18,669 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-04-13 08:33:18,669 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-04-13 08:33:18,669 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-04-13 08:33:18,669 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-04-13 08:33:18,669 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-04-13 08:33:18,669 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-04-13 08:33:18,670 INFO L133 SettingsManager]: * sizeof long double=12 [2018-04-13 08:33:18,670 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-04-13 08:33:18,670 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-04-13 08:33:18,670 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-04-13 08:33:18,670 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-04-13 08:33:18,670 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-13 08:33:18,670 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-04-13 08:33:18,671 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-04-13 08:33:18,671 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-04-13 08:33:18,671 INFO L133 SettingsManager]: * Trace refinement strategy=SMTINTERPOL Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Bitprecise bitfields -> false [2018-04-13 08:33:18,698 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-04-13 08:33:18,709 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully (re)initialized [2018-04-13 08:33:18,712 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-04-13 08:33:18,713 INFO L271 PluginConnector]: Initializing CDTParser... [2018-04-13 08:33:18,713 INFO L276 PluginConnector]: CDTParser initialized [2018-04-13 08:33:18,714 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-04-13 08:33:19,014 INFO L225 CDTParser]: Created temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAG13af7a6f9 [2018-04-13 08:33:19,120 INFO L287 CDTParser]: IsIndexed: true [2018-04-13 08:33:19,120 INFO L288 CDTParser]: Found 1 translation units. [2018-04-13 08:33:19,121 INFO L168 CDTParser]: Scanning ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-04-13 08:33:19,121 INFO L210 ultiparseSymbolTable]: Include resolver: [2018-04-13 08:33:19,122 INFO L215 ultiparseSymbolTable]: [2018-04-13 08:33:19,122 INFO L218 ultiparseSymbolTable]: Function table: [2018-04-13 08:33:19,122 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__foo ('foo') in ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-04-13 08:33:19,122 INFO L221 ultiparseSymbolTable]: Function definition of null ('main') in ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-04-13 08:33:19,122 INFO L227 ultiparseSymbolTable]: Global variable table: [2018-04-13 08:33:19,122 INFO L233 ultiparseSymbolTable]: [2018-04-13 08:33:19,134 INFO L330 CDTParser]: Deleted temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAG13af7a6f9 [2018-04-13 08:33:19,136 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-04-13 08:33:19,137 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-04-13 08:33:19,138 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-04-13 08:33:19,138 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-04-13 08:33:19,142 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-04-13 08:33:19,143 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.04 08:33:19" (1/1) ... [2018-04-13 08:33:19,144 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7bd15aec and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:33:19, skipping insertion in model container [2018-04-13 08:33:19,144 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.04 08:33:19" (1/1) ... [2018-04-13 08:33:19,156 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-13 08:33:19,164 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-13 08:33:19,258 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-13 08:33:19,276 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-13 08:33:19,280 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 9 non ball SCCs. Number of states in SCCs 9. [2018-04-13 08:33:19,286 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:33:19 WrapperNode [2018-04-13 08:33:19,286 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-04-13 08:33:19,287 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-04-13 08:33:19,287 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-04-13 08:33:19,287 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-04-13 08:33:19,296 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:33:19" (1/1) ... [2018-04-13 08:33:19,296 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:33:19" (1/1) ... [2018-04-13 08:33:19,302 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:33:19" (1/1) ... [2018-04-13 08:33:19,303 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:33:19" (1/1) ... [2018-04-13 08:33:19,306 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:33:19" (1/1) ... [2018-04-13 08:33:19,310 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:33:19" (1/1) ... [2018-04-13 08:33:19,311 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:33:19" (1/1) ... [2018-04-13 08:33:19,312 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-04-13 08:33:19,313 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-04-13 08:33:19,313 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-04-13 08:33:19,313 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-04-13 08:33:19,314 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:33:19" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-13 08:33:19,348 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-04-13 08:33:19,348 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-04-13 08:33:19,348 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__foo [2018-04-13 08:33:19,348 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-04-13 08:33:19,348 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__foo [2018-04-13 08:33:19,348 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-04-13 08:33:19,348 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-04-13 08:33:19,349 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-04-13 08:33:19,349 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-04-13 08:33:19,349 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-04-13 08:33:19,349 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-04-13 08:33:19,349 INFO L128 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-04-13 08:33:19,349 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-04-13 08:33:19,525 INFO L259 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-04-13 08:33:19,525 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.04 08:33:19 BoogieIcfgContainer [2018-04-13 08:33:19,525 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-04-13 08:33:19,525 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-04-13 08:33:19,525 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-04-13 08:33:19,527 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-04-13 08:33:19,527 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 13.04 08:33:19" (1/3) ... [2018-04-13 08:33:19,528 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@610f50a0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 13.04 08:33:19, skipping insertion in model container [2018-04-13 08:33:19,528 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.04 08:33:19" (2/3) ... [2018-04-13 08:33:19,528 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@610f50a0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 13.04 08:33:19, skipping insertion in model container [2018-04-13 08:33:19,528 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.04 08:33:19" (3/3) ... [2018-04-13 08:33:19,529 INFO L107 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-04-13 08:33:19,534 INFO L131 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-04-13 08:33:19,538 INFO L143 ceAbstractionStarter]: Appying trace abstraction to program that has 6 error locations. [2018-04-13 08:33:19,561 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-04-13 08:33:19,561 INFO L369 AbstractCegarLoop]: Interprodecural is true [2018-04-13 08:33:19,561 INFO L370 AbstractCegarLoop]: Hoare is false [2018-04-13 08:33:19,561 INFO L371 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-04-13 08:33:19,561 INFO L372 AbstractCegarLoop]: Backedges is TWOTRACK [2018-04-13 08:33:19,561 INFO L373 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-04-13 08:33:19,562 INFO L374 AbstractCegarLoop]: Difference is false [2018-04-13 08:33:19,562 INFO L375 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-04-13 08:33:19,562 INFO L380 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-04-13 08:33:19,562 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-04-13 08:33:19,573 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states. [2018-04-13 08:33:19,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-04-13 08:33:19,579 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:19,580 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:19,580 INFO L408 AbstractCegarLoop]: === Iteration 1 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:19,584 INFO L82 PathProgramCache]: Analyzing trace with hash -895474378, now seen corresponding path program 1 times [2018-04-13 08:33:19,585 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:19,586 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:19,617 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:19,617 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:19,617 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:19,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:19,647 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:19,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:33:19,696 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-13 08:33:19,696 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-04-13 08:33:19,697 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-13 08:33:19,705 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-13 08:33:19,705 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-13 08:33:19,707 INFO L87 Difference]: Start difference. First operand 46 states. Second operand 3 states. [2018-04-13 08:33:19,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:19,753 INFO L93 Difference]: Finished difference Result 63 states and 68 transitions. [2018-04-13 08:33:19,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-13 08:33:19,754 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-04-13 08:33:19,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:19,761 INFO L225 Difference]: With dead ends: 63 [2018-04-13 08:33:19,761 INFO L226 Difference]: Without dead ends: 59 [2018-04-13 08:33:19,762 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-13 08:33:19,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-04-13 08:33:19,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 49. [2018-04-13 08:33:19,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-04-13 08:33:19,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 52 transitions. [2018-04-13 08:33:19,788 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 52 transitions. Word has length 11 [2018-04-13 08:33:19,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:19,788 INFO L459 AbstractCegarLoop]: Abstraction has 49 states and 52 transitions. [2018-04-13 08:33:19,788 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-13 08:33:19,788 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 52 transitions. [2018-04-13 08:33:19,788 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-04-13 08:33:19,788 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:19,788 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:19,789 INFO L408 AbstractCegarLoop]: === Iteration 2 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:19,789 INFO L82 PathProgramCache]: Analyzing trace with hash 1597342241, now seen corresponding path program 1 times [2018-04-13 08:33:19,789 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:19,789 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:19,789 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:19,790 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:19,790 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:19,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:19,800 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:19,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:33:19,817 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-13 08:33:19,818 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-04-13 08:33:19,819 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-13 08:33:19,819 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-13 08:33:19,820 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-13 08:33:19,820 INFO L87 Difference]: Start difference. First operand 49 states and 52 transitions. Second operand 3 states. [2018-04-13 08:33:19,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:19,854 INFO L93 Difference]: Finished difference Result 60 states and 64 transitions. [2018-04-13 08:33:19,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-13 08:33:19,854 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 16 [2018-04-13 08:33:19,855 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:19,856 INFO L225 Difference]: With dead ends: 60 [2018-04-13 08:33:19,856 INFO L226 Difference]: Without dead ends: 60 [2018-04-13 08:33:19,857 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-13 08:33:19,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-04-13 08:33:19,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 52. [2018-04-13 08:33:19,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-04-13 08:33:19,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 56 transitions. [2018-04-13 08:33:19,860 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 56 transitions. Word has length 16 [2018-04-13 08:33:19,860 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:19,860 INFO L459 AbstractCegarLoop]: Abstraction has 52 states and 56 transitions. [2018-04-13 08:33:19,860 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-13 08:33:19,860 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 56 transitions. [2018-04-13 08:33:19,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-04-13 08:33:19,861 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:19,861 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:19,861 INFO L408 AbstractCegarLoop]: === Iteration 3 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:19,861 INFO L82 PathProgramCache]: Analyzing trace with hash -2021997981, now seen corresponding path program 1 times [2018-04-13 08:33:19,861 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:19,861 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:19,862 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:19,862 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:19,862 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:19,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:19,869 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:19,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:33:19,889 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-13 08:33:19,890 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-13 08:33:19,890 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-13 08:33:19,890 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-13 08:33:19,890 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-04-13 08:33:19,890 INFO L87 Difference]: Start difference. First operand 52 states and 56 transitions. Second operand 5 states. [2018-04-13 08:33:19,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:19,944 INFO L93 Difference]: Finished difference Result 51 states and 55 transitions. [2018-04-13 08:33:19,944 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-13 08:33:19,944 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-04-13 08:33:19,945 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:19,945 INFO L225 Difference]: With dead ends: 51 [2018-04-13 08:33:19,945 INFO L226 Difference]: Without dead ends: 51 [2018-04-13 08:33:19,945 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-04-13 08:33:19,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-04-13 08:33:19,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2018-04-13 08:33:19,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-04-13 08:33:19,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 55 transitions. [2018-04-13 08:33:19,948 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 55 transitions. Word has length 17 [2018-04-13 08:33:19,949 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:19,949 INFO L459 AbstractCegarLoop]: Abstraction has 51 states and 55 transitions. [2018-04-13 08:33:19,949 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-13 08:33:19,949 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 55 transitions. [2018-04-13 08:33:19,949 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-04-13 08:33:19,949 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:19,949 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:19,949 INFO L408 AbstractCegarLoop]: === Iteration 4 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:19,949 INFO L82 PathProgramCache]: Analyzing trace with hash -2021997980, now seen corresponding path program 1 times [2018-04-13 08:33:19,949 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:19,950 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:19,950 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:19,950 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:19,950 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:19,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:19,959 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:20,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:33:20,023 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-13 08:33:20,023 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-13 08:33:20,024 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-13 08:33:20,024 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-13 08:33:20,024 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-04-13 08:33:20,024 INFO L87 Difference]: Start difference. First operand 51 states and 55 transitions. Second operand 6 states. [2018-04-13 08:33:20,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:20,087 INFO L93 Difference]: Finished difference Result 53 states and 57 transitions. [2018-04-13 08:33:20,087 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-13 08:33:20,087 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 17 [2018-04-13 08:33:20,087 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:20,088 INFO L225 Difference]: With dead ends: 53 [2018-04-13 08:33:20,088 INFO L226 Difference]: Without dead ends: 53 [2018-04-13 08:33:20,088 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-04-13 08:33:20,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2018-04-13 08:33:20,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 50. [2018-04-13 08:33:20,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-04-13 08:33:20,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-04-13 08:33:20,092 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 17 [2018-04-13 08:33:20,093 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:20,093 INFO L459 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-04-13 08:33:20,093 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-13 08:33:20,093 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-04-13 08:33:20,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-04-13 08:33:20,093 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:20,094 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:20,094 INFO L408 AbstractCegarLoop]: === Iteration 5 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:20,094 INFO L82 PathProgramCache]: Analyzing trace with hash -869005287, now seen corresponding path program 1 times [2018-04-13 08:33:20,094 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:20,094 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:20,095 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:20,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:20,095 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:20,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:20,105 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:20,131 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:33:20,131 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:20,131 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:20,132 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:20,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:20,159 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:20,175 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:33:20,175 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:20,175 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 3 [2018-04-13 08:33:20,176 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-13 08:33:20,176 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-13 08:33:20,176 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-13 08:33:20,176 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 4 states. [2018-04-13 08:33:20,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:20,205 INFO L93 Difference]: Finished difference Result 65 states and 70 transitions. [2018-04-13 08:33:20,206 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-13 08:33:20,206 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 22 [2018-04-13 08:33:20,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:20,207 INFO L225 Difference]: With dead ends: 65 [2018-04-13 08:33:20,207 INFO L226 Difference]: Without dead ends: 65 [2018-04-13 08:33:20,207 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 21 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-13 08:33:20,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2018-04-13 08:33:20,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 56. [2018-04-13 08:33:20,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2018-04-13 08:33:20,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 61 transitions. [2018-04-13 08:33:20,211 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 61 transitions. Word has length 22 [2018-04-13 08:33:20,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:20,212 INFO L459 AbstractCegarLoop]: Abstraction has 56 states and 61 transitions. [2018-04-13 08:33:20,212 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-13 08:33:20,212 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 61 transitions. [2018-04-13 08:33:20,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-04-13 08:33:20,212 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:20,213 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:20,213 INFO L408 AbstractCegarLoop]: === Iteration 6 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:20,213 INFO L82 PathProgramCache]: Analyzing trace with hash -994035242, now seen corresponding path program 1 times [2018-04-13 08:33:20,213 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:20,213 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:20,214 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:20,214 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:20,214 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:20,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:20,221 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:20,241 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:33:20,241 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-13 08:33:20,241 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-13 08:33:20,242 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-13 08:33:20,242 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-13 08:33:20,242 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-04-13 08:33:20,242 INFO L87 Difference]: Start difference. First operand 56 states and 61 transitions. Second operand 5 states. [2018-04-13 08:33:20,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:20,278 INFO L93 Difference]: Finished difference Result 66 states and 71 transitions. [2018-04-13 08:33:20,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-13 08:33:20,278 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 23 [2018-04-13 08:33:20,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:20,279 INFO L225 Difference]: With dead ends: 66 [2018-04-13 08:33:20,279 INFO L226 Difference]: Without dead ends: 66 [2018-04-13 08:33:20,279 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-04-13 08:33:20,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-04-13 08:33:20,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 52. [2018-04-13 08:33:20,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-04-13 08:33:20,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 57 transitions. [2018-04-13 08:33:20,282 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 57 transitions. Word has length 23 [2018-04-13 08:33:20,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:20,282 INFO L459 AbstractCegarLoop]: Abstraction has 52 states and 57 transitions. [2018-04-13 08:33:20,282 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-13 08:33:20,282 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 57 transitions. [2018-04-13 08:33:20,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-04-13 08:33:20,283 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:20,283 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:20,283 INFO L408 AbstractCegarLoop]: === Iteration 7 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:20,283 INFO L82 PathProgramCache]: Analyzing trace with hash -561761263, now seen corresponding path program 2 times [2018-04-13 08:33:20,283 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:20,283 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:20,284 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:20,284 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:20,284 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:20,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:20,291 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:20,321 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:33:20,321 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:20,321 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:20,322 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:33:20,333 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:33:20,333 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:20,336 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:20,387 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:33:20,387 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-04-13 08:33:20,387 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [8] total 12 [2018-04-13 08:33:20,387 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-04-13 08:33:20,387 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-04-13 08:33:20,388 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2018-04-13 08:33:20,388 INFO L87 Difference]: Start difference. First operand 52 states and 57 transitions. Second operand 12 states. [2018-04-13 08:33:20,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:20,507 INFO L93 Difference]: Finished difference Result 88 states and 95 transitions. [2018-04-13 08:33:20,507 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-13 08:33:20,507 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 28 [2018-04-13 08:33:20,508 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:20,508 INFO L225 Difference]: With dead ends: 88 [2018-04-13 08:33:20,509 INFO L226 Difference]: Without dead ends: 88 [2018-04-13 08:33:20,509 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 25 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=87, Invalid=185, Unknown=0, NotChecked=0, Total=272 [2018-04-13 08:33:20,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-04-13 08:33:20,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 72. [2018-04-13 08:33:20,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-04-13 08:33:20,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 79 transitions. [2018-04-13 08:33:20,516 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 79 transitions. Word has length 28 [2018-04-13 08:33:20,516 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:20,516 INFO L459 AbstractCegarLoop]: Abstraction has 72 states and 79 transitions. [2018-04-13 08:33:20,516 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-04-13 08:33:20,517 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 79 transitions. [2018-04-13 08:33:20,517 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-04-13 08:33:20,517 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:20,518 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:20,518 INFO L408 AbstractCegarLoop]: === Iteration 8 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:20,518 INFO L82 PathProgramCache]: Analyzing trace with hash 701046357, now seen corresponding path program 1 times [2018-04-13 08:33:20,518 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:20,518 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:20,519 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:20,519 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:20,519 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:20,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:20,527 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:20,543 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:33:20,543 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:20,543 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:20,544 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:20,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:20,564 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:20,576 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-13 08:33:20,576 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:20,577 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2018-04-13 08:33:20,577 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-13 08:33:20,577 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-13 08:33:20,577 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-04-13 08:33:20,577 INFO L87 Difference]: Start difference. First operand 72 states and 79 transitions. Second operand 5 states. [2018-04-13 08:33:20,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:20,621 INFO L93 Difference]: Finished difference Result 98 states and 106 transitions. [2018-04-13 08:33:20,621 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-13 08:33:20,621 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 31 [2018-04-13 08:33:20,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:20,622 INFO L225 Difference]: With dead ends: 98 [2018-04-13 08:33:20,622 INFO L226 Difference]: Without dead ends: 98 [2018-04-13 08:33:20,623 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-04-13 08:33:20,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-04-13 08:33:20,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 81. [2018-04-13 08:33:20,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-04-13 08:33:20,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 89 transitions. [2018-04-13 08:33:20,628 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 89 transitions. Word has length 31 [2018-04-13 08:33:20,628 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:20,628 INFO L459 AbstractCegarLoop]: Abstraction has 81 states and 89 transitions. [2018-04-13 08:33:20,628 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-13 08:33:20,628 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 89 transitions. [2018-04-13 08:33:20,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-04-13 08:33:20,629 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:20,629 INFO L355 BasicCegarLoop]: trace histogram [4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:20,629 INFO L408 AbstractCegarLoop]: === Iteration 9 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:20,630 INFO L82 PathProgramCache]: Analyzing trace with hash -1455688847, now seen corresponding path program 1 times [2018-04-13 08:33:20,630 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:20,630 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:20,631 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:20,631 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:20,631 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:20,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:20,641 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:20,675 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-04-13 08:33:20,676 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-13 08:33:20,676 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-04-13 08:33:20,676 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-13 08:33:20,676 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-13 08:33:20,677 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-04-13 08:33:20,677 INFO L87 Difference]: Start difference. First operand 81 states and 89 transitions. Second operand 6 states. [2018-04-13 08:33:20,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:20,735 INFO L93 Difference]: Finished difference Result 87 states and 93 transitions. [2018-04-13 08:33:20,735 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-13 08:33:20,735 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 40 [2018-04-13 08:33:20,736 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:20,736 INFO L225 Difference]: With dead ends: 87 [2018-04-13 08:33:20,736 INFO L226 Difference]: Without dead ends: 81 [2018-04-13 08:33:20,737 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-04-13 08:33:20,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2018-04-13 08:33:20,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2018-04-13 08:33:20,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-04-13 08:33:20,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 87 transitions. [2018-04-13 08:33:20,741 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 87 transitions. Word has length 40 [2018-04-13 08:33:20,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:20,741 INFO L459 AbstractCegarLoop]: Abstraction has 81 states and 87 transitions. [2018-04-13 08:33:20,741 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-13 08:33:20,741 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 87 transitions. [2018-04-13 08:33:20,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-04-13 08:33:20,742 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:20,742 INFO L355 BasicCegarLoop]: trace histogram [5, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:20,742 INFO L408 AbstractCegarLoop]: === Iteration 10 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:20,742 INFO L82 PathProgramCache]: Analyzing trace with hash -1559883415, now seen corresponding path program 2 times [2018-04-13 08:33:20,742 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:20,743 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:20,743 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:20,743 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:20,743 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:20,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:20,753 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:20,786 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 26 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-04-13 08:33:20,786 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:20,786 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:20,787 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:33:20,803 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:33:20,803 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:20,805 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:20,831 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 26 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-04-13 08:33:20,832 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:20,832 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 8 [2018-04-13 08:33:20,832 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-13 08:33:20,832 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-13 08:33:20,832 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-04-13 08:33:20,833 INFO L87 Difference]: Start difference. First operand 81 states and 87 transitions. Second operand 8 states. [2018-04-13 08:33:20,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:20,906 INFO L93 Difference]: Finished difference Result 90 states and 94 transitions. [2018-04-13 08:33:20,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-13 08:33:20,907 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 46 [2018-04-13 08:33:20,907 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:20,907 INFO L225 Difference]: With dead ends: 90 [2018-04-13 08:33:20,907 INFO L226 Difference]: Without dead ends: 84 [2018-04-13 08:33:20,908 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2018-04-13 08:33:20,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-04-13 08:33:20,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 81. [2018-04-13 08:33:20,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-04-13 08:33:20,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 85 transitions. [2018-04-13 08:33:20,912 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 85 transitions. Word has length 46 [2018-04-13 08:33:20,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:20,912 INFO L459 AbstractCegarLoop]: Abstraction has 81 states and 85 transitions. [2018-04-13 08:33:20,912 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-13 08:33:20,912 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 85 transitions. [2018-04-13 08:33:20,913 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-04-13 08:33:20,913 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:20,913 INFO L355 BasicCegarLoop]: trace histogram [6, 5, 4, 4, 4, 4, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:20,913 INFO L408 AbstractCegarLoop]: === Iteration 11 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:20,913 INFO L82 PathProgramCache]: Analyzing trace with hash -250620575, now seen corresponding path program 3 times [2018-04-13 08:33:20,914 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:20,914 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:20,914 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:20,914 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:20,915 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:20,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:20,925 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:20,969 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 36 proven. 12 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-04-13 08:33:20,969 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:20,969 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:20,970 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:33:20,978 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-04-13 08:33:20,978 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:20,981 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:21,044 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 37 proven. 14 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-04-13 08:33:21,044 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:21,045 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 8] total 11 [2018-04-13 08:33:21,045 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-04-13 08:33:21,045 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-04-13 08:33:21,045 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=101, Unknown=0, NotChecked=0, Total=132 [2018-04-13 08:33:21,046 INFO L87 Difference]: Start difference. First operand 81 states and 85 transitions. Second operand 12 states. [2018-04-13 08:33:21,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:21,238 INFO L93 Difference]: Finished difference Result 150 states and 157 transitions. [2018-04-13 08:33:21,238 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-04-13 08:33:21,238 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 52 [2018-04-13 08:33:21,239 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:21,239 INFO L225 Difference]: With dead ends: 150 [2018-04-13 08:33:21,239 INFO L226 Difference]: Without dead ends: 150 [2018-04-13 08:33:21,240 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 45 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=88, Invalid=254, Unknown=0, NotChecked=0, Total=342 [2018-04-13 08:33:21,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-04-13 08:33:21,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 113. [2018-04-13 08:33:21,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-04-13 08:33:21,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 120 transitions. [2018-04-13 08:33:21,243 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 120 transitions. Word has length 52 [2018-04-13 08:33:21,243 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:21,243 INFO L459 AbstractCegarLoop]: Abstraction has 113 states and 120 transitions. [2018-04-13 08:33:21,243 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-04-13 08:33:21,243 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 120 transitions. [2018-04-13 08:33:21,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-04-13 08:33:21,244 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:21,244 INFO L355 BasicCegarLoop]: trace histogram [6, 4, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:21,244 INFO L408 AbstractCegarLoop]: === Iteration 12 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:21,244 INFO L82 PathProgramCache]: Analyzing trace with hash 404087573, now seen corresponding path program 1 times [2018-04-13 08:33:21,244 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:21,244 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:21,244 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:21,245 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:21,245 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:21,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:21,257 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:21,301 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 43 proven. 7 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-13 08:33:21,301 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:21,301 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:21,302 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:21,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:21,314 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:21,346 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-04-13 08:33:21,346 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:21,347 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 5] total 11 [2018-04-13 08:33:21,347 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-13 08:33:21,347 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-13 08:33:21,347 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2018-04-13 08:33:21,347 INFO L87 Difference]: Start difference. First operand 113 states and 120 transitions. Second operand 11 states. [2018-04-13 08:33:21,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:21,444 INFO L93 Difference]: Finished difference Result 133 states and 142 transitions. [2018-04-13 08:33:21,444 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-04-13 08:33:21,444 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 67 [2018-04-13 08:33:21,445 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:21,446 INFO L225 Difference]: With dead ends: 133 [2018-04-13 08:33:21,446 INFO L226 Difference]: Without dead ends: 133 [2018-04-13 08:33:21,446 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=55, Invalid=155, Unknown=0, NotChecked=0, Total=210 [2018-04-13 08:33:21,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2018-04-13 08:33:21,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 92. [2018-04-13 08:33:21,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-04-13 08:33:21,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 96 transitions. [2018-04-13 08:33:21,449 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 96 transitions. Word has length 67 [2018-04-13 08:33:21,449 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:21,449 INFO L459 AbstractCegarLoop]: Abstraction has 92 states and 96 transitions. [2018-04-13 08:33:21,450 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-13 08:33:21,450 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 96 transitions. [2018-04-13 08:33:21,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-04-13 08:33:21,450 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:21,450 INFO L355 BasicCegarLoop]: trace histogram [11, 9, 8, 8, 8, 8, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:21,450 INFO L408 AbstractCegarLoop]: === Iteration 13 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:21,451 INFO L82 PathProgramCache]: Analyzing trace with hash 784130209, now seen corresponding path program 4 times [2018-04-13 08:33:21,451 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:21,451 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:21,451 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:21,451 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:21,451 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:21,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:21,462 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:21,509 INFO L134 CoverageAnalysis]: Checked inductivity of 250 backedges. 181 proven. 10 refuted. 0 times theorem prover too weak. 59 trivial. 0 not checked. [2018-04-13 08:33:21,509 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:21,510 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:21,510 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:33:21,522 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:33:21,523 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:21,526 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:21,640 INFO L134 CoverageAnalysis]: Checked inductivity of 250 backedges. 178 proven. 14 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-04-13 08:33:21,640 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:21,640 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 11] total 17 [2018-04-13 08:33:21,641 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-04-13 08:33:21,641 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-04-13 08:33:21,641 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=223, Unknown=0, NotChecked=0, Total=272 [2018-04-13 08:33:21,642 INFO L87 Difference]: Start difference. First operand 92 states and 96 transitions. Second operand 17 states. [2018-04-13 08:33:21,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:21,971 INFO L93 Difference]: Finished difference Result 157 states and 161 transitions. [2018-04-13 08:33:21,973 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-04-13 08:33:21,973 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 88 [2018-04-13 08:33:21,974 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:21,975 INFO L225 Difference]: With dead ends: 157 [2018-04-13 08:33:21,975 INFO L226 Difference]: Without dead ends: 148 [2018-04-13 08:33:21,976 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 110 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 152 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=139, Invalid=673, Unknown=0, NotChecked=0, Total=812 [2018-04-13 08:33:21,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-04-13 08:33:21,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 140. [2018-04-13 08:33:21,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-04-13 08:33:21,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 144 transitions. [2018-04-13 08:33:21,981 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 144 transitions. Word has length 88 [2018-04-13 08:33:21,981 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:21,981 INFO L459 AbstractCegarLoop]: Abstraction has 140 states and 144 transitions. [2018-04-13 08:33:21,981 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-04-13 08:33:21,981 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 144 transitions. [2018-04-13 08:33:21,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2018-04-13 08:33:21,982 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:21,982 INFO L355 BasicCegarLoop]: trace histogram [16, 13, 12, 12, 12, 12, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:21,982 INFO L408 AbstractCegarLoop]: === Iteration 14 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:21,982 INFO L82 PathProgramCache]: Analyzing trace with hash -1650581535, now seen corresponding path program 5 times [2018-04-13 08:33:21,982 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:21,983 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:21,983 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:21,983 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:21,984 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:21,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:21,999 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:22,071 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 401 proven. 24 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-04-13 08:33:22,072 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:22,072 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:22,072 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:33:22,105 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2018-04-13 08:33:22,106 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:22,113 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:22,175 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 401 proven. 24 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-04-13 08:33:22,176 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:22,176 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 14 [2018-04-13 08:33:22,176 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-04-13 08:33:22,176 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-04-13 08:33:22,176 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2018-04-13 08:33:22,177 INFO L87 Difference]: Start difference. First operand 140 states and 144 transitions. Second operand 14 states. [2018-04-13 08:33:22,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:22,302 INFO L93 Difference]: Finished difference Result 152 states and 154 transitions. [2018-04-13 08:33:22,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-13 08:33:22,303 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 124 [2018-04-13 08:33:22,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:22,304 INFO L225 Difference]: With dead ends: 152 [2018-04-13 08:33:22,304 INFO L226 Difference]: Without dead ends: 146 [2018-04-13 08:33:22,304 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 135 GetRequests, 121 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 49 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=174, Unknown=0, NotChecked=0, Total=240 [2018-04-13 08:33:22,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-04-13 08:33:22,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 140. [2018-04-13 08:33:22,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-04-13 08:33:22,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 142 transitions. [2018-04-13 08:33:22,309 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 142 transitions. Word has length 124 [2018-04-13 08:33:22,309 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:22,309 INFO L459 AbstractCegarLoop]: Abstraction has 140 states and 142 transitions. [2018-04-13 08:33:22,309 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-04-13 08:33:22,309 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 142 transitions. [2018-04-13 08:33:22,310 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-04-13 08:33:22,311 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:22,311 INFO L355 BasicCegarLoop]: trace histogram [17, 14, 13, 13, 13, 13, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:22,311 INFO L408 AbstractCegarLoop]: === Iteration 15 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:22,311 INFO L82 PathProgramCache]: Analyzing trace with hash 1018374617, now seen corresponding path program 6 times [2018-04-13 08:33:22,311 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:22,311 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:22,312 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:22,312 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:22,312 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:22,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:22,329 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:22,395 INFO L134 CoverageAnalysis]: Checked inductivity of 642 backedges. 273 proven. 48 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2018-04-13 08:33:22,396 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:22,396 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:22,397 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:33:22,434 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2018-04-13 08:33:22,434 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:22,440 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:22,569 INFO L134 CoverageAnalysis]: Checked inductivity of 642 backedges. 276 proven. 48 refuted. 0 times theorem prover too weak. 318 trivial. 0 not checked. [2018-04-13 08:33:22,569 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:22,569 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 11] total 16 [2018-04-13 08:33:22,569 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-04-13 08:33:22,570 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-04-13 08:33:22,570 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=226, Unknown=0, NotChecked=0, Total=272 [2018-04-13 08:33:22,570 INFO L87 Difference]: Start difference. First operand 140 states and 142 transitions. Second operand 17 states. [2018-04-13 08:33:22,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:22,982 INFO L93 Difference]: Finished difference Result 206 states and 211 transitions. [2018-04-13 08:33:22,982 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-04-13 08:33:22,982 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 130 [2018-04-13 08:33:22,982 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:22,983 INFO L225 Difference]: With dead ends: 206 [2018-04-13 08:33:22,983 INFO L226 Difference]: Without dead ends: 206 [2018-04-13 08:33:22,984 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 144 GetRequests, 120 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 95 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=113, Invalid=487, Unknown=0, NotChecked=0, Total=600 [2018-04-13 08:33:22,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2018-04-13 08:33:22,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 182. [2018-04-13 08:33:22,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-04-13 08:33:22,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 186 transitions. [2018-04-13 08:33:22,988 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 186 transitions. Word has length 130 [2018-04-13 08:33:22,989 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:22,989 INFO L459 AbstractCegarLoop]: Abstraction has 182 states and 186 transitions. [2018-04-13 08:33:22,989 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-04-13 08:33:22,989 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 186 transitions. [2018-04-13 08:33:22,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2018-04-13 08:33:22,991 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:22,991 INFO L355 BasicCegarLoop]: trace histogram [23, 19, 18, 18, 18, 18, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:22,991 INFO L408 AbstractCegarLoop]: === Iteration 16 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:22,991 INFO L82 PathProgramCache]: Analyzing trace with hash -1774140143, now seen corresponding path program 7 times [2018-04-13 08:33:22,991 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:22,991 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:22,992 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:22,992 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:22,992 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:23,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:23,009 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:23,106 INFO L134 CoverageAnalysis]: Checked inductivity of 1216 backedges. 806 proven. 44 refuted. 0 times theorem prover too weak. 366 trivial. 0 not checked. [2018-04-13 08:33:23,107 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:23,107 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:23,108 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:23,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:23,133 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:23,199 INFO L134 CoverageAnalysis]: Checked inductivity of 1216 backedges. 806 proven. 44 refuted. 0 times theorem prover too weak. 366 trivial. 0 not checked. [2018-04-13 08:33:23,200 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:23,200 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 17 [2018-04-13 08:33:23,200 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-04-13 08:33:23,200 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-04-13 08:33:23,201 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=76, Invalid=196, Unknown=0, NotChecked=0, Total=272 [2018-04-13 08:33:23,201 INFO L87 Difference]: Start difference. First operand 182 states and 186 transitions. Second operand 17 states. [2018-04-13 08:33:23,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:23,311 INFO L93 Difference]: Finished difference Result 204 states and 207 transitions. [2018-04-13 08:33:23,311 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-13 08:33:23,311 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 172 [2018-04-13 08:33:23,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:23,312 INFO L225 Difference]: With dead ends: 204 [2018-04-13 08:33:23,312 INFO L226 Difference]: Without dead ends: 198 [2018-04-13 08:33:23,313 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 186 GetRequests, 168 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 91 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=100, Invalid=280, Unknown=0, NotChecked=0, Total=380 [2018-04-13 08:33:23,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states. [2018-04-13 08:33:23,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 188. [2018-04-13 08:33:23,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 188 states. [2018-04-13 08:33:23,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 191 transitions. [2018-04-13 08:33:23,317 INFO L78 Accepts]: Start accepts. Automaton has 188 states and 191 transitions. Word has length 172 [2018-04-13 08:33:23,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:23,318 INFO L459 AbstractCegarLoop]: Abstraction has 188 states and 191 transitions. [2018-04-13 08:33:23,318 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-04-13 08:33:23,318 INFO L276 IsEmpty]: Start isEmpty. Operand 188 states and 191 transitions. [2018-04-13 08:33:23,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2018-04-13 08:33:23,319 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:23,319 INFO L355 BasicCegarLoop]: trace histogram [24, 20, 19, 19, 19, 19, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:23,320 INFO L408 AbstractCegarLoop]: === Iteration 17 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:23,320 INFO L82 PathProgramCache]: Analyzing trace with hash 1375873801, now seen corresponding path program 8 times [2018-04-13 08:33:23,320 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:23,320 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:23,321 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:23,321 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:23,321 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:23,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:23,340 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:23,407 INFO L134 CoverageAnalysis]: Checked inductivity of 1335 backedges. 510 proven. 75 refuted. 0 times theorem prover too weak. 750 trivial. 0 not checked. [2018-04-13 08:33:23,407 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:23,407 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:23,408 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:33:23,431 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:33:23,432 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:23,436 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:23,470 INFO L134 CoverageAnalysis]: Checked inductivity of 1335 backedges. 510 proven. 75 refuted. 0 times theorem prover too weak. 750 trivial. 0 not checked. [2018-04-13 08:33:23,470 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:23,471 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 9 [2018-04-13 08:33:23,471 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-13 08:33:23,471 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-13 08:33:23,471 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=56, Unknown=0, NotChecked=0, Total=90 [2018-04-13 08:33:23,472 INFO L87 Difference]: Start difference. First operand 188 states and 191 transitions. Second operand 10 states. [2018-04-13 08:33:23,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:23,542 INFO L93 Difference]: Finished difference Result 216 states and 221 transitions. [2018-04-13 08:33:23,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-13 08:33:23,542 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 178 [2018-04-13 08:33:23,542 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:23,543 INFO L225 Difference]: With dead ends: 216 [2018-04-13 08:33:23,543 INFO L226 Difference]: Without dead ends: 216 [2018-04-13 08:33:23,544 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 189 GetRequests, 177 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=116, Unknown=0, NotChecked=0, Total=182 [2018-04-13 08:33:23,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-04-13 08:33:23,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 194. [2018-04-13 08:33:23,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194 states. [2018-04-13 08:33:23,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 198 transitions. [2018-04-13 08:33:23,548 INFO L78 Accepts]: Start accepts. Automaton has 194 states and 198 transitions. Word has length 178 [2018-04-13 08:33:23,548 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:23,549 INFO L459 AbstractCegarLoop]: Abstraction has 194 states and 198 transitions. [2018-04-13 08:33:23,549 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-13 08:33:23,549 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 198 transitions. [2018-04-13 08:33:23,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2018-04-13 08:33:23,551 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:23,551 INFO L355 BasicCegarLoop]: trace histogram [25, 21, 20, 20, 20, 20, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:23,551 INFO L408 AbstractCegarLoop]: === Iteration 18 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:23,551 INFO L82 PathProgramCache]: Analyzing trace with hash 2106090241, now seen corresponding path program 9 times [2018-04-13 08:33:23,551 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:23,552 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:23,552 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:23,552 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:23,552 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:23,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:23,569 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:23,707 INFO L134 CoverageAnalysis]: Checked inductivity of 1460 backedges. 697 proven. 69 refuted. 0 times theorem prover too weak. 694 trivial. 0 not checked. [2018-04-13 08:33:23,707 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:23,707 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:23,708 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:33:23,730 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-04-13 08:33:23,730 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:23,734 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:23,801 INFO L134 CoverageAnalysis]: Checked inductivity of 1460 backedges. 633 proven. 58 refuted. 0 times theorem prover too weak. 769 trivial. 0 not checked. [2018-04-13 08:33:23,801 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:23,801 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 11] total 20 [2018-04-13 08:33:23,802 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-04-13 08:33:23,802 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-04-13 08:33:23,802 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=301, Unknown=0, NotChecked=0, Total=380 [2018-04-13 08:33:23,802 INFO L87 Difference]: Start difference. First operand 194 states and 198 transitions. Second operand 20 states. [2018-04-13 08:33:24,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:24,071 INFO L93 Difference]: Finished difference Result 250 states and 255 transitions. [2018-04-13 08:33:24,071 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-04-13 08:33:24,071 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 184 [2018-04-13 08:33:24,072 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:24,072 INFO L225 Difference]: With dead ends: 250 [2018-04-13 08:33:24,072 INFO L226 Difference]: Without dead ends: 250 [2018-04-13 08:33:24,073 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 211 GetRequests, 181 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 139 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=254, Invalid=738, Unknown=0, NotChecked=0, Total=992 [2018-04-13 08:33:24,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 250 states. [2018-04-13 08:33:24,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 250 to 248. [2018-04-13 08:33:24,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 248 states. [2018-04-13 08:33:24,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 248 states to 248 states and 253 transitions. [2018-04-13 08:33:24,076 INFO L78 Accepts]: Start accepts. Automaton has 248 states and 253 transitions. Word has length 184 [2018-04-13 08:33:24,076 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:24,076 INFO L459 AbstractCegarLoop]: Abstraction has 248 states and 253 transitions. [2018-04-13 08:33:24,076 INFO L460 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-04-13 08:33:24,076 INFO L276 IsEmpty]: Start isEmpty. Operand 248 states and 253 transitions. [2018-04-13 08:33:24,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2018-04-13 08:33:24,078 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:24,078 INFO L355 BasicCegarLoop]: trace histogram [31, 26, 25, 25, 25, 25, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:24,078 INFO L408 AbstractCegarLoop]: === Iteration 19 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:24,078 INFO L82 PathProgramCache]: Analyzing trace with hash 1356019769, now seen corresponding path program 10 times [2018-04-13 08:33:24,078 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:24,078 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:24,079 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:24,079 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:24,079 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:24,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:24,091 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:24,227 INFO L134 CoverageAnalysis]: Checked inductivity of 2280 backedges. 1404 proven. 70 refuted. 0 times theorem prover too weak. 806 trivial. 0 not checked. [2018-04-13 08:33:24,227 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:24,227 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:24,227 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:33:24,242 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:33:24,243 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:24,247 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:24,444 INFO L134 CoverageAnalysis]: Checked inductivity of 2280 backedges. 1256 proven. 274 refuted. 0 times theorem prover too weak. 750 trivial. 0 not checked. [2018-04-13 08:33:24,444 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:24,444 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 19] total 30 [2018-04-13 08:33:24,444 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-04-13 08:33:24,444 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-04-13 08:33:24,445 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=146, Invalid=724, Unknown=0, NotChecked=0, Total=870 [2018-04-13 08:33:24,445 INFO L87 Difference]: Start difference. First operand 248 states and 253 transitions. Second operand 30 states. [2018-04-13 08:33:24,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:24,942 INFO L93 Difference]: Finished difference Result 316 states and 319 transitions. [2018-04-13 08:33:24,943 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-04-13 08:33:24,943 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 226 [2018-04-13 08:33:24,943 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:24,944 INFO L225 Difference]: With dead ends: 316 [2018-04-13 08:33:24,945 INFO L226 Difference]: Without dead ends: 307 [2018-04-13 08:33:24,946 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 261 GetRequests, 211 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 780 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=412, Invalid=2240, Unknown=0, NotChecked=0, Total=2652 [2018-04-13 08:33:24,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307 states. [2018-04-13 08:33:24,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307 to 248. [2018-04-13 08:33:24,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 248 states. [2018-04-13 08:33:24,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 248 states to 248 states and 251 transitions. [2018-04-13 08:33:24,952 INFO L78 Accepts]: Start accepts. Automaton has 248 states and 251 transitions. Word has length 226 [2018-04-13 08:33:24,953 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:24,953 INFO L459 AbstractCegarLoop]: Abstraction has 248 states and 251 transitions. [2018-04-13 08:33:24,953 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-04-13 08:33:24,953 INFO L276 IsEmpty]: Start isEmpty. Operand 248 states and 251 transitions. [2018-04-13 08:33:24,954 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 233 [2018-04-13 08:33:24,954 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:24,954 INFO L355 BasicCegarLoop]: trace histogram [32, 27, 26, 26, 26, 26, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:24,954 INFO L408 AbstractCegarLoop]: === Iteration 20 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:24,954 INFO L82 PathProgramCache]: Analyzing trace with hash 901554225, now seen corresponding path program 11 times [2018-04-13 08:33:24,955 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:24,955 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:24,955 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:24,956 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:24,956 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:24,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:24,979 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:25,099 INFO L134 CoverageAnalysis]: Checked inductivity of 2443 backedges. 850 proven. 108 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-04-13 08:33:25,100 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:25,100 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:25,100 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:33:25,197 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2018-04-13 08:33:25,197 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:25,224 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:25,301 INFO L134 CoverageAnalysis]: Checked inductivity of 2443 backedges. 1009 proven. 285 refuted. 0 times theorem prover too weak. 1149 trivial. 0 not checked. [2018-04-13 08:33:25,301 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:25,301 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 16 [2018-04-13 08:33:25,302 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-04-13 08:33:25,302 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-04-13 08:33:25,302 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=200, Unknown=0, NotChecked=0, Total=272 [2018-04-13 08:33:25,302 INFO L87 Difference]: Start difference. First operand 248 states and 251 transitions. Second operand 17 states. [2018-04-13 08:33:25,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:25,427 INFO L93 Difference]: Finished difference Result 266 states and 270 transitions. [2018-04-13 08:33:25,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-04-13 08:33:25,427 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 232 [2018-04-13 08:33:25,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:25,428 INFO L225 Difference]: With dead ends: 266 [2018-04-13 08:33:25,428 INFO L226 Difference]: Without dead ends: 266 [2018-04-13 08:33:25,428 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 240 GetRequests, 223 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 97 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=72, Invalid=200, Unknown=0, NotChecked=0, Total=272 [2018-04-13 08:33:25,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 266 states. [2018-04-13 08:33:25,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 266 to 254. [2018-04-13 08:33:25,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 254 states. [2018-04-13 08:33:25,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254 states to 254 states and 258 transitions. [2018-04-13 08:33:25,433 INFO L78 Accepts]: Start accepts. Automaton has 254 states and 258 transitions. Word has length 232 [2018-04-13 08:33:25,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:25,434 INFO L459 AbstractCegarLoop]: Abstraction has 254 states and 258 transitions. [2018-04-13 08:33:25,434 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-04-13 08:33:25,434 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 258 transitions. [2018-04-13 08:33:25,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 239 [2018-04-13 08:33:25,435 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:25,435 INFO L355 BasicCegarLoop]: trace histogram [33, 28, 27, 27, 27, 27, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:25,436 INFO L408 AbstractCegarLoop]: === Iteration 21 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:25,436 INFO L82 PathProgramCache]: Analyzing trace with hash -1429186007, now seen corresponding path program 12 times [2018-04-13 08:33:25,436 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:25,436 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:25,437 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:25,437 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:25,437 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:25,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:25,457 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:25,635 INFO L134 CoverageAnalysis]: Checked inductivity of 2612 backedges. 1112 proven. 100 refuted. 0 times theorem prover too weak. 1400 trivial. 0 not checked. [2018-04-13 08:33:25,636 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:25,636 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:25,636 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:33:25,737 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-04-13 08:33:25,737 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:25,746 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:25,894 INFO L134 CoverageAnalysis]: Checked inductivity of 2612 backedges. 980 proven. 147 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-04-13 08:33:25,895 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:25,895 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 10] total 27 [2018-04-13 08:33:25,895 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-04-13 08:33:25,896 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-04-13 08:33:25,896 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=116, Invalid=586, Unknown=0, NotChecked=0, Total=702 [2018-04-13 08:33:25,896 INFO L87 Difference]: Start difference. First operand 254 states and 258 transitions. Second operand 27 states. [2018-04-13 08:33:26,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:26,412 INFO L93 Difference]: Finished difference Result 334 states and 340 transitions. [2018-04-13 08:33:26,413 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-04-13 08:33:26,413 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 238 [2018-04-13 08:33:26,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:26,414 INFO L225 Difference]: With dead ends: 334 [2018-04-13 08:33:26,414 INFO L226 Difference]: Without dead ends: 334 [2018-04-13 08:33:26,414 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 277 GetRequests, 230 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 483 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=487, Invalid=1865, Unknown=0, NotChecked=0, Total=2352 [2018-04-13 08:33:26,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 334 states. [2018-04-13 08:33:26,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 334 to 314. [2018-04-13 08:33:26,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 314 states. [2018-04-13 08:33:26,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 314 states to 314 states and 320 transitions. [2018-04-13 08:33:26,418 INFO L78 Accepts]: Start accepts. Automaton has 314 states and 320 transitions. Word has length 238 [2018-04-13 08:33:26,418 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:26,418 INFO L459 AbstractCegarLoop]: Abstraction has 314 states and 320 transitions. [2018-04-13 08:33:26,418 INFO L460 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-04-13 08:33:26,418 INFO L276 IsEmpty]: Start isEmpty. Operand 314 states and 320 transitions. [2018-04-13 08:33:26,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 293 [2018-04-13 08:33:26,419 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:26,419 INFO L355 BasicCegarLoop]: trace histogram [41, 35, 34, 34, 34, 34, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:26,419 INFO L408 AbstractCegarLoop]: === Iteration 22 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:26,420 INFO L82 PathProgramCache]: Analyzing trace with hash -1258320047, now seen corresponding path program 13 times [2018-04-13 08:33:26,420 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:26,420 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:26,420 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:26,420 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:26,420 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:26,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:26,435 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:26,726 INFO L134 CoverageAnalysis]: Checked inductivity of 4098 backedges. 2399 proven. 102 refuted. 0 times theorem prover too weak. 1597 trivial. 0 not checked. [2018-04-13 08:33:26,726 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:26,726 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:26,727 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:26,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:26,762 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:27,017 INFO L134 CoverageAnalysis]: Checked inductivity of 4098 backedges. 1632 proven. 114 refuted. 0 times theorem prover too weak. 2352 trivial. 0 not checked. [2018-04-13 08:33:27,017 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:27,017 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 19] total 33 [2018-04-13 08:33:27,018 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-04-13 08:33:27,018 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-04-13 08:33:27,018 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=157, Invalid=899, Unknown=0, NotChecked=0, Total=1056 [2018-04-13 08:33:27,018 INFO L87 Difference]: Start difference. First operand 314 states and 320 transitions. Second operand 33 states. [2018-04-13 08:33:27,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:27,763 INFO L93 Difference]: Finished difference Result 394 states and 399 transitions. [2018-04-13 08:33:27,765 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-04-13 08:33:27,765 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 292 [2018-04-13 08:33:27,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:27,767 INFO L225 Difference]: With dead ends: 394 [2018-04-13 08:33:27,767 INFO L226 Difference]: Without dead ends: 385 [2018-04-13 08:33:27,768 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 283 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 792 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=431, Invalid=2761, Unknown=0, NotChecked=0, Total=3192 [2018-04-13 08:33:27,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 385 states. [2018-04-13 08:33:27,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 385 to 374. [2018-04-13 08:33:27,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 374 states. [2018-04-13 08:33:27,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 374 states to 374 states and 379 transitions. [2018-04-13 08:33:27,776 INFO L78 Accepts]: Start accepts. Automaton has 374 states and 379 transitions. Word has length 292 [2018-04-13 08:33:27,776 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:27,776 INFO L459 AbstractCegarLoop]: Abstraction has 374 states and 379 transitions. [2018-04-13 08:33:27,776 INFO L460 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-04-13 08:33:27,776 INFO L276 IsEmpty]: Start isEmpty. Operand 374 states and 379 transitions. [2018-04-13 08:33:27,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 353 [2018-04-13 08:33:27,778 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:27,778 INFO L355 BasicCegarLoop]: trace histogram [50, 43, 42, 42, 42, 42, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:27,778 INFO L408 AbstractCegarLoop]: === Iteration 23 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:27,778 INFO L82 PathProgramCache]: Analyzing trace with hash -604052879, now seen corresponding path program 14 times [2018-04-13 08:33:27,778 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:27,779 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:27,780 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:27,780 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:27,780 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:27,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:27,814 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:28,029 INFO L134 CoverageAnalysis]: Checked inductivity of 6181 backedges. 3323 proven. 140 refuted. 0 times theorem prover too weak. 2718 trivial. 0 not checked. [2018-04-13 08:33:28,030 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:28,030 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:28,031 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:33:28,066 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:33:28,066 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:28,074 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:28,270 INFO L134 CoverageAnalysis]: Checked inductivity of 6181 backedges. 3323 proven. 140 refuted. 0 times theorem prover too weak. 2718 trivial. 0 not checked. [2018-04-13 08:33:28,271 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:28,271 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 26 [2018-04-13 08:33:28,271 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-04-13 08:33:28,271 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-04-13 08:33:28,271 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=169, Invalid=481, Unknown=0, NotChecked=0, Total=650 [2018-04-13 08:33:28,271 INFO L87 Difference]: Start difference. First operand 374 states and 379 transitions. Second operand 26 states. [2018-04-13 08:33:28,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:28,670 INFO L93 Difference]: Finished difference Result 389 states and 392 transitions. [2018-04-13 08:33:28,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-04-13 08:33:28,671 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 352 [2018-04-13 08:33:28,671 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:28,672 INFO L225 Difference]: With dead ends: 389 [2018-04-13 08:33:28,672 INFO L226 Difference]: Without dead ends: 383 [2018-04-13 08:33:28,673 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 375 GetRequests, 345 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 289 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=244, Invalid=748, Unknown=0, NotChecked=0, Total=992 [2018-04-13 08:33:28,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 383 states. [2018-04-13 08:33:28,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 383 to 374. [2018-04-13 08:33:28,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 374 states. [2018-04-13 08:33:28,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 374 states to 374 states and 377 transitions. [2018-04-13 08:33:28,681 INFO L78 Accepts]: Start accepts. Automaton has 374 states and 377 transitions. Word has length 352 [2018-04-13 08:33:28,681 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:28,681 INFO L459 AbstractCegarLoop]: Abstraction has 374 states and 377 transitions. [2018-04-13 08:33:28,681 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-04-13 08:33:28,681 INFO L276 IsEmpty]: Start isEmpty. Operand 374 states and 377 transitions. [2018-04-13 08:33:28,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 359 [2018-04-13 08:33:28,684 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:28,684 INFO L355 BasicCegarLoop]: trace histogram [51, 44, 43, 43, 43, 43, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:28,684 INFO L408 AbstractCegarLoop]: === Iteration 24 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:28,685 INFO L82 PathProgramCache]: Analyzing trace with hash 608157801, now seen corresponding path program 15 times [2018-04-13 08:33:28,685 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:28,685 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:28,686 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:28,686 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:28,686 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:28,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:28,713 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:28,844 INFO L134 CoverageAnalysis]: Checked inductivity of 6450 backedges. 1911 proven. 192 refuted. 0 times theorem prover too weak. 4347 trivial. 0 not checked. [2018-04-13 08:33:28,844 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:28,844 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:28,845 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:33:28,895 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-04-13 08:33:28,895 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:28,906 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:28,989 INFO L134 CoverageAnalysis]: Checked inductivity of 6450 backedges. 1911 proven. 192 refuted. 0 times theorem prover too weak. 4347 trivial. 0 not checked. [2018-04-13 08:33:28,989 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:28,989 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2018-04-13 08:33:28,990 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-13 08:33:28,990 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-13 08:33:28,990 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-04-13 08:33:28,990 INFO L87 Difference]: Start difference. First operand 374 states and 377 transitions. Second operand 11 states. [2018-04-13 08:33:29,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:29,247 INFO L93 Difference]: Finished difference Result 392 states and 396 transitions. [2018-04-13 08:33:29,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-13 08:33:29,248 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 358 [2018-04-13 08:33:29,248 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:29,249 INFO L225 Difference]: With dead ends: 392 [2018-04-13 08:33:29,249 INFO L226 Difference]: Without dead ends: 392 [2018-04-13 08:33:29,250 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 368 GetRequests, 357 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-04-13 08:33:29,250 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states. [2018-04-13 08:33:29,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 380. [2018-04-13 08:33:29,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 380 states. [2018-04-13 08:33:29,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 380 states to 380 states and 384 transitions. [2018-04-13 08:33:29,256 INFO L78 Accepts]: Start accepts. Automaton has 380 states and 384 transitions. Word has length 358 [2018-04-13 08:33:29,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:29,256 INFO L459 AbstractCegarLoop]: Abstraction has 380 states and 384 transitions. [2018-04-13 08:33:29,256 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-13 08:33:29,256 INFO L276 IsEmpty]: Start isEmpty. Operand 380 states and 384 transitions. [2018-04-13 08:33:29,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 365 [2018-04-13 08:33:29,258 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:29,259 INFO L355 BasicCegarLoop]: trace histogram [52, 45, 44, 44, 44, 44, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:29,259 INFO L408 AbstractCegarLoop]: === Iteration 25 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:29,259 INFO L82 PathProgramCache]: Analyzing trace with hash -992448415, now seen corresponding path program 16 times [2018-04-13 08:33:29,259 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:29,259 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:29,260 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:29,260 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:29,260 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:29,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:29,289 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:29,486 INFO L134 CoverageAnalysis]: Checked inductivity of 6725 backedges. 2359 proven. 180 refuted. 0 times theorem prover too weak. 4186 trivial. 0 not checked. [2018-04-13 08:33:29,486 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:29,486 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:29,486 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:33:29,514 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:33:29,514 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:29,521 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:30,042 INFO L134 CoverageAnalysis]: Checked inductivity of 6725 backedges. 3433 proven. 652 refuted. 0 times theorem prover too weak. 2640 trivial. 0 not checked. [2018-04-13 08:33:30,042 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:30,043 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 25] total 42 [2018-04-13 08:33:30,043 INFO L442 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-04-13 08:33:30,044 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-04-13 08:33:30,044 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=301, Invalid=1421, Unknown=0, NotChecked=0, Total=1722 [2018-04-13 08:33:30,044 INFO L87 Difference]: Start difference. First operand 380 states and 384 transitions. Second operand 42 states. [2018-04-13 08:33:31,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:31,169 INFO L93 Difference]: Finished difference Result 463 states and 468 transitions. [2018-04-13 08:33:31,170 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-04-13 08:33:31,170 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 364 [2018-04-13 08:33:31,171 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:31,172 INFO L225 Difference]: With dead ends: 463 [2018-04-13 08:33:31,172 INFO L226 Difference]: Without dead ends: 463 [2018-04-13 08:33:31,174 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 411 GetRequests, 345 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 948 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=879, Invalid=3677, Unknown=0, NotChecked=0, Total=4556 [2018-04-13 08:33:31,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463 states. [2018-04-13 08:33:31,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463 to 452. [2018-04-13 08:33:31,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 452 states. [2018-04-13 08:33:31,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 452 states to 452 states and 457 transitions. [2018-04-13 08:33:31,181 INFO L78 Accepts]: Start accepts. Automaton has 452 states and 457 transitions. Word has length 364 [2018-04-13 08:33:31,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:31,182 INFO L459 AbstractCegarLoop]: Abstraction has 452 states and 457 transitions. [2018-04-13 08:33:31,182 INFO L460 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-04-13 08:33:31,182 INFO L276 IsEmpty]: Start isEmpty. Operand 452 states and 457 transitions. [2018-04-13 08:33:31,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 431 [2018-04-13 08:33:31,184 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:31,185 INFO L355 BasicCegarLoop]: trace histogram [62, 54, 53, 53, 53, 53, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:31,185 INFO L408 AbstractCegarLoop]: === Iteration 26 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:31,185 INFO L82 PathProgramCache]: Analyzing trace with hash 64648569, now seen corresponding path program 17 times [2018-04-13 08:33:31,185 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:31,185 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:31,186 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:31,186 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:31,186 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:31,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:31,218 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:31,408 INFO L134 CoverageAnalysis]: Checked inductivity of 9667 backedges. 2668 proven. 243 refuted. 0 times theorem prover too weak. 6756 trivial. 0 not checked. [2018-04-13 08:33:31,409 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:31,409 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:31,409 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:33:31,643 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 23 check-sat command(s) [2018-04-13 08:33:31,643 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:31,744 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:31,946 INFO L134 CoverageAnalysis]: Checked inductivity of 9667 backedges. 2696 proven. 1638 refuted. 0 times theorem prover too weak. 5333 trivial. 0 not checked. [2018-04-13 08:33:31,946 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:31,947 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 19] total 25 [2018-04-13 08:33:31,948 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-04-13 08:33:31,948 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-04-13 08:33:31,948 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=181, Invalid=469, Unknown=0, NotChecked=0, Total=650 [2018-04-13 08:33:31,948 INFO L87 Difference]: Start difference. First operand 452 states and 457 transitions. Second operand 26 states. [2018-04-13 08:33:32,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:32,131 INFO L93 Difference]: Finished difference Result 470 states and 476 transitions. [2018-04-13 08:33:32,131 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-04-13 08:33:32,131 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 430 [2018-04-13 08:33:32,132 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:32,133 INFO L225 Difference]: With dead ends: 470 [2018-04-13 08:33:32,133 INFO L226 Difference]: Without dead ends: 470 [2018-04-13 08:33:32,134 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 445 GetRequests, 417 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 306 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=232, Invalid=638, Unknown=0, NotChecked=0, Total=870 [2018-04-13 08:33:32,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 470 states. [2018-04-13 08:33:32,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 470 to 458. [2018-04-13 08:33:32,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 458 states. [2018-04-13 08:33:32,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 458 states to 458 states and 464 transitions. [2018-04-13 08:33:32,141 INFO L78 Accepts]: Start accepts. Automaton has 458 states and 464 transitions. Word has length 430 [2018-04-13 08:33:32,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:32,141 INFO L459 AbstractCegarLoop]: Abstraction has 458 states and 464 transitions. [2018-04-13 08:33:32,142 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-04-13 08:33:32,142 INFO L276 IsEmpty]: Start isEmpty. Operand 458 states and 464 transitions. [2018-04-13 08:33:32,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 437 [2018-04-13 08:33:32,144 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:32,144 INFO L355 BasicCegarLoop]: trace histogram [63, 55, 54, 54, 54, 54, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:32,144 INFO L408 AbstractCegarLoop]: === Iteration 27 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:32,145 INFO L82 PathProgramCache]: Analyzing trace with hash 523966833, now seen corresponding path program 18 times [2018-04-13 08:33:32,145 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:32,145 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:32,145 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:32,145 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:32,146 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:32,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:32,178 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:32,524 INFO L134 CoverageAnalysis]: Checked inductivity of 10004 backedges. 3227 proven. 229 refuted. 0 times theorem prover too weak. 6548 trivial. 0 not checked. [2018-04-13 08:33:32,524 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:32,524 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:32,525 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:33:32,715 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 21 check-sat command(s) [2018-04-13 08:33:32,716 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:32,730 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:33,088 INFO L134 CoverageAnalysis]: Checked inductivity of 10004 backedges. 4033 proven. 1197 refuted. 0 times theorem prover too weak. 4774 trivial. 0 not checked. [2018-04-13 08:33:33,088 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:33,088 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 19] total 37 [2018-04-13 08:33:33,089 INFO L442 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-04-13 08:33:33,089 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-04-13 08:33:33,090 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=205, Invalid=1127, Unknown=0, NotChecked=0, Total=1332 [2018-04-13 08:33:33,090 INFO L87 Difference]: Start difference. First operand 458 states and 464 transitions. Second operand 37 states. [2018-04-13 08:33:34,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:34,067 INFO L93 Difference]: Finished difference Result 544 states and 552 transitions. [2018-04-13 08:33:34,067 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-04-13 08:33:34,067 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 436 [2018-04-13 08:33:34,068 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:34,069 INFO L225 Difference]: With dead ends: 544 [2018-04-13 08:33:34,069 INFO L226 Difference]: Without dead ends: 544 [2018-04-13 08:33:34,071 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 487 GetRequests, 424 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 836 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=866, Invalid=3294, Unknown=0, NotChecked=0, Total=4160 [2018-04-13 08:33:34,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 544 states. [2018-04-13 08:33:34,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 544 to 533. [2018-04-13 08:33:34,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 533 states. [2018-04-13 08:33:34,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 533 states and 541 transitions. [2018-04-13 08:33:34,079 INFO L78 Accepts]: Start accepts. Automaton has 533 states and 541 transitions. Word has length 436 [2018-04-13 08:33:34,080 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:34,080 INFO L459 AbstractCegarLoop]: Abstraction has 533 states and 541 transitions. [2018-04-13 08:33:34,080 INFO L460 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-04-13 08:33:34,080 INFO L276 IsEmpty]: Start isEmpty. Operand 533 states and 541 transitions. [2018-04-13 08:33:34,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 503 [2018-04-13 08:33:34,083 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:34,083 INFO L355 BasicCegarLoop]: trace histogram [73, 64, 63, 63, 63, 63, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:34,084 INFO L408 AbstractCegarLoop]: === Iteration 28 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:34,084 INFO L82 PathProgramCache]: Analyzing trace with hash 282969737, now seen corresponding path program 19 times [2018-04-13 08:33:34,084 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:34,084 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:34,085 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:34,085 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:34,085 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:34,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:34,117 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:34,424 INFO L134 CoverageAnalysis]: Checked inductivity of 13536 backedges. 6446 proven. 234 refuted. 0 times theorem prover too weak. 6856 trivial. 0 not checked. [2018-04-13 08:33:34,424 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:34,424 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:34,425 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:34,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:34,474 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:34,664 INFO L134 CoverageAnalysis]: Checked inductivity of 13536 backedges. 6446 proven. 234 refuted. 0 times theorem prover too weak. 6856 trivial. 0 not checked. [2018-04-13 08:33:34,664 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:34,665 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 32 [2018-04-13 08:33:34,665 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-13 08:33:34,665 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-13 08:33:34,665 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=251, Invalid=741, Unknown=0, NotChecked=0, Total=992 [2018-04-13 08:33:34,665 INFO L87 Difference]: Start difference. First operand 533 states and 541 transitions. Second operand 32 states. [2018-04-13 08:33:35,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:35,059 INFO L93 Difference]: Finished difference Result 554 states and 558 transitions. [2018-04-13 08:33:35,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-04-13 08:33:35,079 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 502 [2018-04-13 08:33:35,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:35,080 INFO L225 Difference]: With dead ends: 554 [2018-04-13 08:33:35,080 INFO L226 Difference]: Without dead ends: 533 [2018-04-13 08:33:35,081 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 531 GetRequests, 493 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 481 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=375, Invalid=1185, Unknown=0, NotChecked=0, Total=1560 [2018-04-13 08:33:35,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 533 states. [2018-04-13 08:33:35,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 533 to 524. [2018-04-13 08:33:35,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 524 states. [2018-04-13 08:33:35,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 524 states to 524 states and 527 transitions. [2018-04-13 08:33:35,086 INFO L78 Accepts]: Start accepts. Automaton has 524 states and 527 transitions. Word has length 502 [2018-04-13 08:33:35,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:35,086 INFO L459 AbstractCegarLoop]: Abstraction has 524 states and 527 transitions. [2018-04-13 08:33:35,086 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-13 08:33:35,086 INFO L276 IsEmpty]: Start isEmpty. Operand 524 states and 527 transitions. [2018-04-13 08:33:35,088 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 509 [2018-04-13 08:33:35,088 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:35,088 INFO L355 BasicCegarLoop]: trace histogram [74, 65, 64, 64, 64, 64, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:35,088 INFO L408 AbstractCegarLoop]: === Iteration 29 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:35,088 INFO L82 PathProgramCache]: Analyzing trace with hash 870003329, now seen corresponding path program 20 times [2018-04-13 08:33:35,088 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:35,088 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:35,089 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:35,089 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:35,089 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:35,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:35,113 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:35,385 INFO L134 CoverageAnalysis]: Checked inductivity of 13935 backedges. 3600 proven. 300 refuted. 0 times theorem prover too weak. 10035 trivial. 0 not checked. [2018-04-13 08:33:35,386 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:35,386 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:35,386 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:33:35,430 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:33:35,430 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:35,438 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:35,529 INFO L134 CoverageAnalysis]: Checked inductivity of 13935 backedges. 3600 proven. 300 refuted. 0 times theorem prover too weak. 10035 trivial. 0 not checked. [2018-04-13 08:33:35,529 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:35,529 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 14 [2018-04-13 08:33:35,530 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-04-13 08:33:35,530 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-04-13 08:33:35,530 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=136, Unknown=0, NotChecked=0, Total=210 [2018-04-13 08:33:35,530 INFO L87 Difference]: Start difference. First operand 524 states and 527 transitions. Second operand 15 states. [2018-04-13 08:33:35,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:35,718 INFO L93 Difference]: Finished difference Result 542 states and 546 transitions. [2018-04-13 08:33:35,718 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-04-13 08:33:35,718 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 508 [2018-04-13 08:33:35,719 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:35,720 INFO L225 Difference]: With dead ends: 542 [2018-04-13 08:33:35,720 INFO L226 Difference]: Without dead ends: 542 [2018-04-13 08:33:35,721 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 529 GetRequests, 507 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=181, Invalid=371, Unknown=0, NotChecked=0, Total=552 [2018-04-13 08:33:35,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 542 states. [2018-04-13 08:33:35,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 542 to 530. [2018-04-13 08:33:35,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 530 states. [2018-04-13 08:33:35,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 530 states to 530 states and 534 transitions. [2018-04-13 08:33:35,726 INFO L78 Accepts]: Start accepts. Automaton has 530 states and 534 transitions. Word has length 508 [2018-04-13 08:33:35,726 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:35,726 INFO L459 AbstractCegarLoop]: Abstraction has 530 states and 534 transitions. [2018-04-13 08:33:35,726 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-04-13 08:33:35,726 INFO L276 IsEmpty]: Start isEmpty. Operand 530 states and 534 transitions. [2018-04-13 08:33:35,728 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 515 [2018-04-13 08:33:35,728 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:35,728 INFO L355 BasicCegarLoop]: trace histogram [75, 66, 65, 65, 65, 65, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:35,728 INFO L408 AbstractCegarLoop]: === Iteration 30 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:35,728 INFO L82 PathProgramCache]: Analyzing trace with hash -265555847, now seen corresponding path program 21 times [2018-04-13 08:33:35,728 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:35,729 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:35,729 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:35,729 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:35,729 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:35,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:35,749 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:36,138 INFO L134 CoverageAnalysis]: Checked inductivity of 14340 backedges. 4282 proven. 284 refuted. 0 times theorem prover too weak. 9774 trivial. 0 not checked. [2018-04-13 08:33:36,138 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:36,138 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:36,139 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:33:36,222 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-04-13 08:33:36,222 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:36,235 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:36,957 INFO L134 CoverageAnalysis]: Checked inductivity of 14340 backedges. 5125 proven. 1949 refuted. 0 times theorem prover too weak. 7266 trivial. 0 not checked. [2018-04-13 08:33:36,957 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:36,958 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 28] total 53 [2018-04-13 08:33:36,958 INFO L442 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-04-13 08:33:36,959 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-04-13 08:33:36,959 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=363, Invalid=2393, Unknown=0, NotChecked=0, Total=2756 [2018-04-13 08:33:36,960 INFO L87 Difference]: Start difference. First operand 530 states and 534 transitions. Second operand 53 states. [2018-04-13 08:33:38,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:38,140 INFO L93 Difference]: Finished difference Result 616 states and 621 transitions. [2018-04-13 08:33:38,140 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-04-13 08:33:38,140 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 514 [2018-04-13 08:33:38,140 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:38,141 INFO L225 Difference]: With dead ends: 616 [2018-04-13 08:33:38,141 INFO L226 Difference]: Without dead ends: 616 [2018-04-13 08:33:38,143 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 575 GetRequests, 488 SyntacticMatches, 0 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1941 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1242, Invalid=6590, Unknown=0, NotChecked=0, Total=7832 [2018-04-13 08:33:38,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 616 states. [2018-04-13 08:33:38,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 616 to 608. [2018-04-13 08:33:38,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 608 states. [2018-04-13 08:33:38,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 608 states to 608 states and 613 transitions. [2018-04-13 08:33:38,148 INFO L78 Accepts]: Start accepts. Automaton has 608 states and 613 transitions. Word has length 514 [2018-04-13 08:33:38,148 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:38,148 INFO L459 AbstractCegarLoop]: Abstraction has 608 states and 613 transitions. [2018-04-13 08:33:38,148 INFO L460 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-04-13 08:33:38,148 INFO L276 IsEmpty]: Start isEmpty. Operand 608 states and 613 transitions. [2018-04-13 08:33:38,150 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 587 [2018-04-13 08:33:38,150 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:38,150 INFO L355 BasicCegarLoop]: trace histogram [86, 76, 75, 75, 75, 75, 11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:38,150 INFO L408 AbstractCegarLoop]: === Iteration 31 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:38,151 INFO L82 PathProgramCache]: Analyzing trace with hash -579703415, now seen corresponding path program 22 times [2018-04-13 08:33:38,151 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:38,151 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:38,151 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:38,151 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:38,151 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:38,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:38,177 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:38,490 INFO L134 CoverageAnalysis]: Checked inductivity of 18985 backedges. 8549 proven. 290 refuted. 0 times theorem prover too weak. 10146 trivial. 0 not checked. [2018-04-13 08:33:38,490 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:38,490 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:38,491 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:33:38,515 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:33:38,515 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:38,521 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:39,105 INFO L134 CoverageAnalysis]: Checked inductivity of 18985 backedges. 7956 proven. 994 refuted. 0 times theorem prover too weak. 10035 trivial. 0 not checked. [2018-04-13 08:33:39,106 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:39,106 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 29] total 50 [2018-04-13 08:33:39,106 INFO L442 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-04-13 08:33:39,107 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-04-13 08:33:39,107 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=396, Invalid=2054, Unknown=0, NotChecked=0, Total=2450 [2018-04-13 08:33:39,107 INFO L87 Difference]: Start difference. First operand 608 states and 613 transitions. Second operand 50 states. [2018-04-13 08:33:40,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:40,122 INFO L93 Difference]: Finished difference Result 625 states and 628 transitions. [2018-04-13 08:33:40,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-04-13 08:33:40,122 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 586 [2018-04-13 08:33:40,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:40,124 INFO L225 Difference]: With dead ends: 625 [2018-04-13 08:33:40,124 INFO L226 Difference]: Without dead ends: 619 [2018-04-13 08:33:40,126 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 651 GetRequests, 561 SyntacticMatches, 0 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2735 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1182, Invalid=7190, Unknown=0, NotChecked=0, Total=8372 [2018-04-13 08:33:40,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 619 states. [2018-04-13 08:33:40,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 619 to 608. [2018-04-13 08:33:40,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 608 states. [2018-04-13 08:33:40,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 608 states to 608 states and 611 transitions. [2018-04-13 08:33:40,131 INFO L78 Accepts]: Start accepts. Automaton has 608 states and 611 transitions. Word has length 586 [2018-04-13 08:33:40,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:40,131 INFO L459 AbstractCegarLoop]: Abstraction has 608 states and 611 transitions. [2018-04-13 08:33:40,131 INFO L460 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-04-13 08:33:40,131 INFO L276 IsEmpty]: Start isEmpty. Operand 608 states and 611 transitions. [2018-04-13 08:33:40,133 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 593 [2018-04-13 08:33:40,134 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:40,134 INFO L355 BasicCegarLoop]: trace histogram [87, 77, 76, 76, 76, 76, 11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:40,134 INFO L408 AbstractCegarLoop]: === Iteration 32 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:40,134 INFO L82 PathProgramCache]: Analyzing trace with hash 1818728833, now seen corresponding path program 23 times [2018-04-13 08:33:40,134 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:40,134 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:40,135 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:40,135 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:40,135 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:40,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:40,157 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:40,359 INFO L134 CoverageAnalysis]: Checked inductivity of 19458 backedges. 4725 proven. 363 refuted. 0 times theorem prover too weak. 14370 trivial. 0 not checked. [2018-04-13 08:33:40,359 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:40,359 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:40,360 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:33:40,736 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 26 check-sat command(s) [2018-04-13 08:33:40,736 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:40,802 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:41,044 INFO L134 CoverageAnalysis]: Checked inductivity of 19458 backedges. 4725 proven. 363 refuted. 0 times theorem prover too weak. 14370 trivial. 0 not checked. [2018-04-13 08:33:41,044 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:41,044 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 26 [2018-04-13 08:33:41,044 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-04-13 08:33:41,045 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-04-13 08:33:41,045 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=195, Invalid=507, Unknown=0, NotChecked=0, Total=702 [2018-04-13 08:33:41,045 INFO L87 Difference]: Start difference. First operand 608 states and 611 transitions. Second operand 27 states. [2018-04-13 08:33:41,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:41,319 INFO L93 Difference]: Finished difference Result 626 states and 630 transitions. [2018-04-13 08:33:41,319 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-13 08:33:41,319 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 592 [2018-04-13 08:33:41,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:41,320 INFO L225 Difference]: With dead ends: 626 [2018-04-13 08:33:41,321 INFO L226 Difference]: Without dead ends: 626 [2018-04-13 08:33:41,321 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 605 GetRequests, 579 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 294 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=195, Invalid=507, Unknown=0, NotChecked=0, Total=702 [2018-04-13 08:33:41,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states. [2018-04-13 08:33:41,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 614. [2018-04-13 08:33:41,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 614 states. [2018-04-13 08:33:41,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 614 states to 614 states and 618 transitions. [2018-04-13 08:33:41,326 INFO L78 Accepts]: Start accepts. Automaton has 614 states and 618 transitions. Word has length 592 [2018-04-13 08:33:41,326 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:41,326 INFO L459 AbstractCegarLoop]: Abstraction has 614 states and 618 transitions. [2018-04-13 08:33:41,326 INFO L460 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-04-13 08:33:41,326 INFO L276 IsEmpty]: Start isEmpty. Operand 614 states and 618 transitions. [2018-04-13 08:33:41,328 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 599 [2018-04-13 08:33:41,328 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:41,329 INFO L355 BasicCegarLoop]: trace histogram [88, 78, 77, 77, 77, 77, 11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:41,329 INFO L408 AbstractCegarLoop]: === Iteration 33 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:41,329 INFO L82 PathProgramCache]: Analyzing trace with hash 831461241, now seen corresponding path program 24 times [2018-04-13 08:33:41,329 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:41,329 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:41,329 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:41,329 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:41,329 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:41,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:41,353 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:41,654 INFO L134 CoverageAnalysis]: Checked inductivity of 19937 backedges. 5542 proven. 345 refuted. 0 times theorem prover too weak. 14050 trivial. 0 not checked. [2018-04-13 08:33:41,654 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:41,654 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:41,655 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:33:41,769 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2018-04-13 08:33:41,769 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:41,780 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:42,046 INFO L134 CoverageAnalysis]: Checked inductivity of 19937 backedges. 5202 proven. 322 refuted. 0 times theorem prover too weak. 14413 trivial. 0 not checked. [2018-04-13 08:33:42,047 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:42,047 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 17] total 32 [2018-04-13 08:33:42,048 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-13 08:33:42,048 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-13 08:33:42,048 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=211, Invalid=781, Unknown=0, NotChecked=0, Total=992 [2018-04-13 08:33:42,049 INFO L87 Difference]: Start difference. First operand 614 states and 618 transitions. Second operand 32 states. [2018-04-13 08:33:42,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:42,677 INFO L93 Difference]: Finished difference Result 700 states and 705 transitions. [2018-04-13 08:33:42,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-04-13 08:33:42,677 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 598 [2018-04-13 08:33:42,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:42,678 INFO L225 Difference]: With dead ends: 700 [2018-04-13 08:33:42,678 INFO L226 Difference]: Without dead ends: 700 [2018-04-13 08:33:42,679 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 649 GetRequests, 595 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 472 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=743, Invalid=2337, Unknown=0, NotChecked=0, Total=3080 [2018-04-13 08:33:42,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 700 states. [2018-04-13 08:33:42,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 700 to 698. [2018-04-13 08:33:42,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 698 states. [2018-04-13 08:33:42,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 698 states to 698 states and 703 transitions. [2018-04-13 08:33:42,684 INFO L78 Accepts]: Start accepts. Automaton has 698 states and 703 transitions. Word has length 598 [2018-04-13 08:33:42,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:42,684 INFO L459 AbstractCegarLoop]: Abstraction has 698 states and 703 transitions. [2018-04-13 08:33:42,684 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-13 08:33:42,684 INFO L276 IsEmpty]: Start isEmpty. Operand 698 states and 703 transitions. [2018-04-13 08:33:42,688 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 677 [2018-04-13 08:33:42,688 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:42,688 INFO L355 BasicCegarLoop]: trace histogram [100, 89, 88, 88, 88, 88, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:42,688 INFO L408 AbstractCegarLoop]: === Iteration 34 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:42,689 INFO L82 PathProgramCache]: Analyzing trace with hash -1107841919, now seen corresponding path program 25 times [2018-04-13 08:33:42,689 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:42,689 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:42,689 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:42,689 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:42,689 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:42,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:42,719 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:43,248 INFO L134 CoverageAnalysis]: Checked inductivity of 25905 backedges. 11061 proven. 352 refuted. 0 times theorem prover too weak. 14492 trivial. 0 not checked. [2018-04-13 08:33:43,249 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:43,249 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:43,249 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:43,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:43,307 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:43,626 INFO L134 CoverageAnalysis]: Checked inductivity of 25905 backedges. 11061 proven. 352 refuted. 0 times theorem prover too weak. 14492 trivial. 0 not checked. [2018-04-13 08:33:43,626 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:43,626 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 38 [2018-04-13 08:33:43,627 INFO L442 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-04-13 08:33:43,627 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-04-13 08:33:43,627 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=349, Invalid=1057, Unknown=0, NotChecked=0, Total=1406 [2018-04-13 08:33:43,627 INFO L87 Difference]: Start difference. First operand 698 states and 703 transitions. Second operand 38 states. [2018-04-13 08:33:44,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:44,071 INFO L93 Difference]: Finished difference Result 713 states and 716 transitions. [2018-04-13 08:33:44,072 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-04-13 08:33:44,072 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 676 [2018-04-13 08:33:44,072 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:44,073 INFO L225 Difference]: With dead ends: 713 [2018-04-13 08:33:44,073 INFO L226 Difference]: Without dead ends: 707 [2018-04-13 08:33:44,073 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 711 GetRequests, 665 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 721 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=534, Invalid=1722, Unknown=0, NotChecked=0, Total=2256 [2018-04-13 08:33:44,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 707 states. [2018-04-13 08:33:44,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 707 to 698. [2018-04-13 08:33:44,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 698 states. [2018-04-13 08:33:44,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 698 states to 698 states and 701 transitions. [2018-04-13 08:33:44,081 INFO L78 Accepts]: Start accepts. Automaton has 698 states and 701 transitions. Word has length 676 [2018-04-13 08:33:44,081 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:44,081 INFO L459 AbstractCegarLoop]: Abstraction has 698 states and 701 transitions. [2018-04-13 08:33:44,081 INFO L460 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-04-13 08:33:44,081 INFO L276 IsEmpty]: Start isEmpty. Operand 698 states and 701 transitions. [2018-04-13 08:33:44,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 683 [2018-04-13 08:33:44,086 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:44,086 INFO L355 BasicCegarLoop]: trace histogram [101, 90, 89, 89, 89, 89, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:44,086 INFO L408 AbstractCegarLoop]: === Iteration 35 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:44,087 INFO L82 PathProgramCache]: Analyzing trace with hash 1344323193, now seen corresponding path program 26 times [2018-04-13 08:33:44,087 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:44,087 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:44,087 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:44,087 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:44,088 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:44,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:44,131 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:44,385 INFO L134 CoverageAnalysis]: Checked inductivity of 26458 backedges. 6061 proven. 432 refuted. 0 times theorem prover too weak. 19965 trivial. 0 not checked. [2018-04-13 08:33:44,385 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:44,385 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:44,386 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:33:44,417 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:33:44,417 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:44,424 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:44,648 INFO L134 CoverageAnalysis]: Checked inductivity of 26458 backedges. 6061 proven. 432 refuted. 0 times theorem prover too weak. 19965 trivial. 0 not checked. [2018-04-13 08:33:44,649 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:44,649 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 16 [2018-04-13 08:33:44,650 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-04-13 08:33:44,650 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-04-13 08:33:44,650 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=194, Unknown=0, NotChecked=0, Total=272 [2018-04-13 08:33:44,650 INFO L87 Difference]: Start difference. First operand 698 states and 701 transitions. Second operand 17 states. [2018-04-13 08:33:44,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:44,859 INFO L93 Difference]: Finished difference Result 716 states and 720 transitions. [2018-04-13 08:33:44,859 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-04-13 08:33:44,859 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 682 [2018-04-13 08:33:44,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:44,860 INFO L225 Difference]: With dead ends: 716 [2018-04-13 08:33:44,861 INFO L226 Difference]: Without dead ends: 716 [2018-04-13 08:33:44,861 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 707 GetRequests, 681 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 129 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=207, Invalid=549, Unknown=0, NotChecked=0, Total=756 [2018-04-13 08:33:44,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 716 states. [2018-04-13 08:33:44,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 716 to 704. [2018-04-13 08:33:44,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 704 states. [2018-04-13 08:33:44,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 704 states to 704 states and 708 transitions. [2018-04-13 08:33:44,868 INFO L78 Accepts]: Start accepts. Automaton has 704 states and 708 transitions. Word has length 682 [2018-04-13 08:33:44,868 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:44,868 INFO L459 AbstractCegarLoop]: Abstraction has 704 states and 708 transitions. [2018-04-13 08:33:44,868 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-04-13 08:33:44,868 INFO L276 IsEmpty]: Start isEmpty. Operand 704 states and 708 transitions. [2018-04-13 08:33:44,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 689 [2018-04-13 08:33:44,873 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:44,873 INFO L355 BasicCegarLoop]: trace histogram [102, 91, 90, 90, 90, 90, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:44,873 INFO L408 AbstractCegarLoop]: === Iteration 36 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:44,873 INFO L82 PathProgramCache]: Analyzing trace with hash 1172742769, now seen corresponding path program 27 times [2018-04-13 08:33:44,873 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:44,873 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:44,873 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:44,874 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:44,874 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:44,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:44,905 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:45,333 INFO L134 CoverageAnalysis]: Checked inductivity of 27017 backedges. 7025 proven. 412 refuted. 0 times theorem prover too weak. 19580 trivial. 0 not checked. [2018-04-13 08:33:45,333 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:45,333 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:45,334 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:33:45,379 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 14 check-sat command(s) [2018-04-13 08:33:45,379 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:45,389 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:45,773 INFO L134 CoverageAnalysis]: Checked inductivity of 27017 backedges. 6545 proven. 507 refuted. 0 times theorem prover too weak. 19965 trivial. 0 not checked. [2018-04-13 08:33:45,773 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:45,773 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 16] total 45 [2018-04-13 08:33:45,774 INFO L442 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-04-13 08:33:45,774 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-04-13 08:33:45,774 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=323, Invalid=1657, Unknown=0, NotChecked=0, Total=1980 [2018-04-13 08:33:45,774 INFO L87 Difference]: Start difference. First operand 704 states and 708 transitions. Second operand 45 states. [2018-04-13 08:33:46,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:46,866 INFO L93 Difference]: Finished difference Result 820 states and 826 transitions. [2018-04-13 08:33:46,866 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-04-13 08:33:46,866 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 688 [2018-04-13 08:33:46,866 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:46,867 INFO L225 Difference]: With dead ends: 820 [2018-04-13 08:33:46,867 INFO L226 Difference]: Without dead ends: 820 [2018-04-13 08:33:46,868 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 757 GetRequests, 674 SyntacticMatches, 0 SemanticMatches, 83 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1644 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1435, Invalid=5705, Unknown=0, NotChecked=0, Total=7140 [2018-04-13 08:33:46,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 820 states. [2018-04-13 08:33:46,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 820 to 800. [2018-04-13 08:33:46,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 800 states. [2018-04-13 08:33:46,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 800 states to 800 states and 806 transitions. [2018-04-13 08:33:46,875 INFO L78 Accepts]: Start accepts. Automaton has 800 states and 806 transitions. Word has length 688 [2018-04-13 08:33:46,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:46,875 INFO L459 AbstractCegarLoop]: Abstraction has 800 states and 806 transitions. [2018-04-13 08:33:46,875 INFO L460 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-04-13 08:33:46,875 INFO L276 IsEmpty]: Start isEmpty. Operand 800 states and 806 transitions. [2018-04-13 08:33:46,881 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 779 [2018-04-13 08:33:46,881 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:46,881 INFO L355 BasicCegarLoop]: trace histogram [116, 104, 103, 103, 103, 103, 13, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:46,881 INFO L408 AbstractCegarLoop]: === Iteration 37 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:46,882 INFO L82 PathProgramCache]: Analyzing trace with hash -1896000663, now seen corresponding path program 28 times [2018-04-13 08:33:46,882 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:46,882 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:46,882 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:46,883 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:46,883 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:46,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:46,929 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:47,368 INFO L134 CoverageAnalysis]: Checked inductivity of 35175 backedges. 14576 proven. 420 refuted. 0 times theorem prover too weak. 20179 trivial. 0 not checked. [2018-04-13 08:33:47,368 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:47,369 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:47,369 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:33:47,400 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:33:47,400 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:47,407 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:48,267 INFO L134 CoverageAnalysis]: Checked inductivity of 35175 backedges. 13728 proven. 1482 refuted. 0 times theorem prover too weak. 19965 trivial. 0 not checked. [2018-04-13 08:33:48,267 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:48,267 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 34] total 59 [2018-04-13 08:33:48,267 INFO L442 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-04-13 08:33:48,268 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-04-13 08:33:48,268 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=547, Invalid=2875, Unknown=0, NotChecked=0, Total=3422 [2018-04-13 08:33:48,268 INFO L87 Difference]: Start difference. First operand 800 states and 806 transitions. Second operand 59 states. [2018-04-13 08:33:49,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:49,591 INFO L93 Difference]: Finished difference Result 814 states and 818 transitions. [2018-04-13 08:33:49,591 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-04-13 08:33:49,591 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 778 [2018-04-13 08:33:49,592 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:49,593 INFO L225 Difference]: With dead ends: 814 [2018-04-13 08:33:49,593 INFO L226 Difference]: Without dead ends: 808 [2018-04-13 08:33:49,594 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 855 GetRequests, 748 SyntacticMatches, 0 SemanticMatches, 107 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3946 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1618, Invalid=10154, Unknown=0, NotChecked=0, Total=11772 [2018-04-13 08:33:49,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 808 states. [2018-04-13 08:33:49,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 808 to 800. [2018-04-13 08:33:49,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 800 states. [2018-04-13 08:33:49,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 800 states to 800 states and 804 transitions. [2018-04-13 08:33:49,600 INFO L78 Accepts]: Start accepts. Automaton has 800 states and 804 transitions. Word has length 778 [2018-04-13 08:33:49,601 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:49,601 INFO L459 AbstractCegarLoop]: Abstraction has 800 states and 804 transitions. [2018-04-13 08:33:49,601 INFO L460 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-04-13 08:33:49,601 INFO L276 IsEmpty]: Start isEmpty. Operand 800 states and 804 transitions. [2018-04-13 08:33:49,605 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 785 [2018-04-13 08:33:49,605 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:49,605 INFO L355 BasicCegarLoop]: trace histogram [117, 105, 104, 104, 104, 104, 13, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:49,605 INFO L408 AbstractCegarLoop]: === Iteration 38 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:49,606 INFO L82 PathProgramCache]: Analyzing trace with hash 895063905, now seen corresponding path program 29 times [2018-04-13 08:33:49,606 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:49,606 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:49,606 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:49,606 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:49,606 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:49,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:49,636 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:50,087 INFO L134 CoverageAnalysis]: Checked inductivity of 35820 backedges. 8749 proven. 485 refuted. 0 times theorem prover too weak. 26586 trivial. 0 not checked. [2018-04-13 08:33:50,087 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:50,087 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:50,088 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:33:50,647 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2018-04-13 08:33:50,647 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:50,734 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:51,384 INFO L134 CoverageAnalysis]: Checked inductivity of 35820 backedges. 8627 proven. 2768 refuted. 0 times theorem prover too weak. 24425 trivial. 0 not checked. [2018-04-13 08:33:51,385 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:51,385 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 39] total 56 [2018-04-13 08:33:51,385 INFO L442 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-04-13 08:33:51,385 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-04-13 08:33:51,385 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=550, Invalid=2530, Unknown=0, NotChecked=0, Total=3080 [2018-04-13 08:33:51,386 INFO L87 Difference]: Start difference. First operand 800 states and 804 transitions. Second operand 56 states. [2018-04-13 08:33:52,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:52,485 INFO L93 Difference]: Finished difference Result 898 states and 902 transitions. [2018-04-13 08:33:52,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-04-13 08:33:52,485 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 784 [2018-04-13 08:33:52,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:52,487 INFO L225 Difference]: With dead ends: 898 [2018-04-13 08:33:52,487 INFO L226 Difference]: Without dead ends: 898 [2018-04-13 08:33:52,487 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 846 GetRequests, 761 SyntacticMatches, 0 SemanticMatches, 85 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1534 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1443, Invalid=6039, Unknown=0, NotChecked=0, Total=7482 [2018-04-13 08:33:52,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 898 states. [2018-04-13 08:33:52,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 898 to 890. [2018-04-13 08:33:52,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 890 states. [2018-04-13 08:33:52,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 890 states to 890 states and 894 transitions. [2018-04-13 08:33:52,492 INFO L78 Accepts]: Start accepts. Automaton has 890 states and 894 transitions. Word has length 784 [2018-04-13 08:33:52,493 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:52,493 INFO L459 AbstractCegarLoop]: Abstraction has 890 states and 894 transitions. [2018-04-13 08:33:52,493 INFO L460 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-04-13 08:33:52,493 INFO L276 IsEmpty]: Start isEmpty. Operand 890 states and 894 transitions. [2018-04-13 08:33:52,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 875 [2018-04-13 08:33:52,497 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:52,498 INFO L355 BasicCegarLoop]: trace histogram [131, 118, 117, 117, 117, 117, 14, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:52,498 INFO L408 AbstractCegarLoop]: === Iteration 39 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:52,498 INFO L82 PathProgramCache]: Analyzing trace with hash -165184423, now seen corresponding path program 30 times [2018-04-13 08:33:52,498 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:52,498 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:52,499 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:52,499 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:52,499 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:52,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:52,531 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:52,963 INFO L134 CoverageAnalysis]: Checked inductivity of 45136 backedges. 17456 proven. 494 refuted. 0 times theorem prover too weak. 27186 trivial. 0 not checked. [2018-04-13 08:33:52,964 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:52,964 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:52,964 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:33:53,161 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2018-04-13 08:33:53,161 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:53,188 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:53,593 INFO L134 CoverageAnalysis]: Checked inductivity of 45136 backedges. 9431 proven. 534 refuted. 0 times theorem prover too weak. 35171 trivial. 0 not checked. [2018-04-13 08:33:53,593 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:53,593 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 20] total 49 [2018-04-13 08:33:53,594 INFO L442 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-04-13 08:33:53,594 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-04-13 08:33:53,594 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=359, Invalid=1993, Unknown=0, NotChecked=0, Total=2352 [2018-04-13 08:33:53,594 INFO L87 Difference]: Start difference. First operand 890 states and 894 transitions. Second operand 49 states. [2018-04-13 08:33:55,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:55,080 INFO L93 Difference]: Finished difference Result 1007 states and 1010 transitions. [2018-04-13 08:33:55,080 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 87 states. [2018-04-13 08:33:55,081 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 874 [2018-04-13 08:33:55,081 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:55,082 INFO L225 Difference]: With dead ends: 1007 [2018-04-13 08:33:55,083 INFO L226 Difference]: Without dead ends: 998 [2018-04-13 08:33:55,084 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 986 GetRequests, 870 SyntacticMatches, 0 SemanticMatches, 116 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4062 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=2165, Invalid=11641, Unknown=0, NotChecked=0, Total=13806 [2018-04-13 08:33:55,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 998 states. [2018-04-13 08:33:55,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 998 to 986. [2018-04-13 08:33:55,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 986 states. [2018-04-13 08:33:55,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 986 states to 986 states and 989 transitions. [2018-04-13 08:33:55,170 INFO L78 Accepts]: Start accepts. Automaton has 986 states and 989 transitions. Word has length 874 [2018-04-13 08:33:55,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:55,170 INFO L459 AbstractCegarLoop]: Abstraction has 986 states and 989 transitions. [2018-04-13 08:33:55,170 INFO L460 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-04-13 08:33:55,170 INFO L276 IsEmpty]: Start isEmpty. Operand 986 states and 989 transitions. [2018-04-13 08:33:55,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 977 [2018-04-13 08:33:55,175 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:55,175 INFO L355 BasicCegarLoop]: trace histogram [147, 133, 132, 132, 132, 132, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:55,175 INFO L408 AbstractCegarLoop]: === Iteration 40 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:55,175 INFO L82 PathProgramCache]: Analyzing trace with hash 1060225345, now seen corresponding path program 31 times [2018-04-13 08:33:55,175 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:55,175 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:55,176 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:55,176 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:55,176 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:55,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:55,218 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:55,763 INFO L134 CoverageAnalysis]: Checked inductivity of 57158 backedges. 20675 proven. 574 refuted. 0 times theorem prover too weak. 35909 trivial. 0 not checked. [2018-04-13 08:33:55,763 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:55,763 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:55,763 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:55,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:55,813 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:56,291 INFO L134 CoverageAnalysis]: Checked inductivity of 57158 backedges. 20675 proven. 574 refuted. 0 times theorem prover too weak. 35909 trivial. 0 not checked. [2018-04-13 08:33:56,292 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:56,292 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 47 [2018-04-13 08:33:56,292 INFO L442 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-04-13 08:33:56,293 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-04-13 08:33:56,293 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=526, Invalid=1636, Unknown=0, NotChecked=0, Total=2162 [2018-04-13 08:33:56,293 INFO L87 Difference]: Start difference. First operand 986 states and 989 transitions. Second operand 47 states. [2018-04-13 08:33:56,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:56,645 INFO L93 Difference]: Finished difference Result 1015 states and 1018 transitions. [2018-04-13 08:33:56,645 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-04-13 08:33:56,645 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 976 [2018-04-13 08:33:56,646 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:56,647 INFO L225 Difference]: With dead ends: 1015 [2018-04-13 08:33:56,647 INFO L226 Difference]: Without dead ends: 1009 [2018-04-13 08:33:56,648 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1020 GetRequests, 962 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1171 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=825, Invalid=2715, Unknown=0, NotChecked=0, Total=3540 [2018-04-13 08:33:56,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1009 states. [2018-04-13 08:33:56,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1009 to 997. [2018-04-13 08:33:56,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 997 states. [2018-04-13 08:33:56,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 997 states to 997 states and 1000 transitions. [2018-04-13 08:33:56,653 INFO L78 Accepts]: Start accepts. Automaton has 997 states and 1000 transitions. Word has length 976 [2018-04-13 08:33:56,653 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:56,653 INFO L459 AbstractCegarLoop]: Abstraction has 997 states and 1000 transitions. [2018-04-13 08:33:56,653 INFO L460 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-04-13 08:33:56,654 INFO L276 IsEmpty]: Start isEmpty. Operand 997 states and 1000 transitions. [2018-04-13 08:33:56,658 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 983 [2018-04-13 08:33:56,658 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:56,658 INFO L355 BasicCegarLoop]: trace histogram [148, 134, 133, 133, 133, 133, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:56,658 INFO L408 AbstractCegarLoop]: === Iteration 41 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:56,658 INFO L82 PathProgramCache]: Analyzing trace with hash -1744157895, now seen corresponding path program 32 times [2018-04-13 08:33:56,658 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:56,658 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:56,659 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:56,659 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:33:56,659 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:56,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:56,695 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:57,014 INFO L134 CoverageAnalysis]: Checked inductivity of 57981 backedges. 10773 proven. 588 refuted. 0 times theorem prover too weak. 46620 trivial. 0 not checked. [2018-04-13 08:33:57,014 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:57,014 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:57,015 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:33:57,061 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:33:57,061 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:57,071 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:57,329 INFO L134 CoverageAnalysis]: Checked inductivity of 57981 backedges. 10773 proven. 588 refuted. 0 times theorem prover too weak. 46620 trivial. 0 not checked. [2018-04-13 08:33:57,329 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:57,329 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 18 [2018-04-13 08:33:57,329 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-04-13 08:33:57,330 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-04-13 08:33:57,330 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=128, Invalid=214, Unknown=0, NotChecked=0, Total=342 [2018-04-13 08:33:57,330 INFO L87 Difference]: Start difference. First operand 997 states and 1000 transitions. Second operand 19 states. [2018-04-13 08:33:57,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:57,501 INFO L93 Difference]: Finished difference Result 1008 states and 1011 transitions. [2018-04-13 08:33:57,501 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-04-13 08:33:57,501 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 982 [2018-04-13 08:33:57,501 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:57,503 INFO L225 Difference]: With dead ends: 1008 [2018-04-13 08:33:57,503 INFO L226 Difference]: Without dead ends: 1008 [2018-04-13 08:33:57,503 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1011 GetRequests, 981 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 152 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=335, Invalid=657, Unknown=0, NotChecked=0, Total=992 [2018-04-13 08:33:57,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1008 states. [2018-04-13 08:33:57,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1008 to 998. [2018-04-13 08:33:57,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 998 states. [2018-04-13 08:33:57,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 998 states to 998 states and 1001 transitions. [2018-04-13 08:33:57,508 INFO L78 Accepts]: Start accepts. Automaton has 998 states and 1001 transitions. Word has length 982 [2018-04-13 08:33:57,509 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:57,509 INFO L459 AbstractCegarLoop]: Abstraction has 998 states and 1001 transitions. [2018-04-13 08:33:57,509 INFO L460 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-04-13 08:33:57,509 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1001 transitions. [2018-04-13 08:33:57,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 989 [2018-04-13 08:33:57,513 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:57,514 INFO L355 BasicCegarLoop]: trace histogram [149, 135, 134, 134, 134, 134, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:57,514 INFO L408 AbstractCegarLoop]: === Iteration 42 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:57,514 INFO L82 PathProgramCache]: Analyzing trace with hash -1639344335, now seen corresponding path program 33 times [2018-04-13 08:33:57,514 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:57,514 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:57,514 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:57,515 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:57,515 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:57,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:57,551 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:57,914 INFO L134 CoverageAnalysis]: Checked inductivity of 58810 backedges. 11515 proven. 675 refuted. 0 times theorem prover too weak. 46620 trivial. 0 not checked. [2018-04-13 08:33:57,914 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:57,914 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:57,915 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:33:57,963 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-04-13 08:33:57,963 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:57,977 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:33:58,196 INFO L134 CoverageAnalysis]: Checked inductivity of 58810 backedges. 11515 proven. 675 refuted. 0 times theorem prover too weak. 46620 trivial. 0 not checked. [2018-04-13 08:33:58,196 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:33:58,196 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 19 [2018-04-13 08:33:58,197 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-04-13 08:33:58,197 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-04-13 08:33:58,197 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=159, Invalid=221, Unknown=0, NotChecked=0, Total=380 [2018-04-13 08:33:58,197 INFO L87 Difference]: Start difference. First operand 998 states and 1001 transitions. Second operand 20 states. [2018-04-13 08:33:58,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:33:58,374 INFO L93 Difference]: Finished difference Result 1026 states and 1031 transitions. [2018-04-13 08:33:58,374 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-04-13 08:33:58,374 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 988 [2018-04-13 08:33:58,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:33:58,376 INFO L225 Difference]: With dead ends: 1026 [2018-04-13 08:33:58,376 INFO L226 Difference]: Without dead ends: 1026 [2018-04-13 08:33:58,377 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1019 GetRequests, 987 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 159 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=411, Invalid=711, Unknown=0, NotChecked=0, Total=1122 [2018-04-13 08:33:58,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1026 states. [2018-04-13 08:33:58,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1026 to 1004. [2018-04-13 08:33:58,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1004 states. [2018-04-13 08:33:58,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1004 states to 1004 states and 1008 transitions. [2018-04-13 08:33:58,382 INFO L78 Accepts]: Start accepts. Automaton has 1004 states and 1008 transitions. Word has length 988 [2018-04-13 08:33:58,383 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:33:58,383 INFO L459 AbstractCegarLoop]: Abstraction has 1004 states and 1008 transitions. [2018-04-13 08:33:58,383 INFO L460 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-04-13 08:33:58,383 INFO L276 IsEmpty]: Start isEmpty. Operand 1004 states and 1008 transitions. [2018-04-13 08:33:58,387 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 995 [2018-04-13 08:33:58,387 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:33:58,387 INFO L355 BasicCegarLoop]: trace histogram [150, 136, 135, 135, 135, 135, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:33:58,387 INFO L408 AbstractCegarLoop]: === Iteration 43 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:33:58,388 INFO L82 PathProgramCache]: Analyzing trace with hash -1652027095, now seen corresponding path program 34 times [2018-04-13 08:33:58,388 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:33:58,388 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:33:58,388 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:58,388 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:33:58,388 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:33:58,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:33:58,424 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:33:58,982 INFO L134 CoverageAnalysis]: Checked inductivity of 59645 backedges. 12992 proven. 649 refuted. 0 times theorem prover too weak. 46004 trivial. 0 not checked. [2018-04-13 08:33:58,982 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:33:58,982 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:33:58,982 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:33:59,022 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:33:59,022 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:33:59,031 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:00,164 INFO L134 CoverageAnalysis]: Checked inductivity of 59645 backedges. 21640 proven. 2164 refuted. 0 times theorem prover too weak. 35841 trivial. 0 not checked. [2018-04-13 08:34:00,164 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:00,165 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 39] total 70 [2018-04-13 08:34:00,165 INFO L442 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-04-13 08:34:00,165 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-04-13 08:34:00,166 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=805, Invalid=4025, Unknown=0, NotChecked=0, Total=4830 [2018-04-13 08:34:00,166 INFO L87 Difference]: Start difference. First operand 1004 states and 1008 transitions. Second operand 70 states. [2018-04-13 08:34:01,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:34:01,608 INFO L93 Difference]: Finished difference Result 1126 states and 1130 transitions. [2018-04-13 08:34:01,608 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-04-13 08:34:01,608 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 994 [2018-04-13 08:34:01,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:34:01,610 INFO L225 Difference]: With dead ends: 1126 [2018-04-13 08:34:01,610 INFO L226 Difference]: Without dead ends: 1126 [2018-04-13 08:34:01,611 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1076 GetRequests, 961 SyntacticMatches, 0 SemanticMatches, 115 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3090 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2405, Invalid=11167, Unknown=0, NotChecked=0, Total=13572 [2018-04-13 08:34:01,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1126 states. [2018-04-13 08:34:01,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1126 to 1118. [2018-04-13 08:34:01,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1118 states. [2018-04-13 08:34:01,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1118 states to 1118 states and 1122 transitions. [2018-04-13 08:34:01,617 INFO L78 Accepts]: Start accepts. Automaton has 1118 states and 1122 transitions. Word has length 994 [2018-04-13 08:34:01,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:34:01,618 INFO L459 AbstractCegarLoop]: Abstraction has 1118 states and 1122 transitions. [2018-04-13 08:34:01,618 INFO L460 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-04-13 08:34:01,618 INFO L276 IsEmpty]: Start isEmpty. Operand 1118 states and 1122 transitions. [2018-04-13 08:34:01,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1103 [2018-04-13 08:34:01,623 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:34:01,623 INFO L355 BasicCegarLoop]: trace histogram [167, 152, 151, 151, 151, 151, 16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:34:01,623 INFO L408 AbstractCegarLoop]: === Iteration 44 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:34:01,624 INFO L82 PathProgramCache]: Analyzing trace with hash -1560222711, now seen corresponding path program 35 times [2018-04-13 08:34:01,624 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:34:01,624 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:34:01,624 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:01,624 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:34:01,624 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:01,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:01,668 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:34:02,400 INFO L134 CoverageAnalysis]: Checked inductivity of 74298 backedges. 13875 proven. 768 refuted. 0 times theorem prover too weak. 59655 trivial. 0 not checked. [2018-04-13 08:34:02,400 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:34:02,400 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:34:02,400 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:34:05,373 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 32 check-sat command(s) [2018-04-13 08:34:05,373 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:34:05,851 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:06,201 INFO L134 CoverageAnalysis]: Checked inductivity of 74298 backedges. 13875 proven. 768 refuted. 0 times theorem prover too weak. 59655 trivial. 0 not checked. [2018-04-13 08:34:06,202 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:06,202 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19] total 19 [2018-04-13 08:34:06,203 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-04-13 08:34:06,203 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-04-13 08:34:06,203 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=342, Unknown=0, NotChecked=0, Total=380 [2018-04-13 08:34:06,203 INFO L87 Difference]: Start difference. First operand 1118 states and 1122 transitions. Second operand 20 states. [2018-04-13 08:34:06,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:34:06,705 INFO L93 Difference]: Finished difference Result 1133 states and 1138 transitions. [2018-04-13 08:34:06,705 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-04-13 08:34:06,705 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 1102 [2018-04-13 08:34:06,705 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:34:06,708 INFO L225 Difference]: With dead ends: 1133 [2018-04-13 08:34:06,708 INFO L226 Difference]: Without dead ends: 1133 [2018-04-13 08:34:06,708 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1120 GetRequests, 1099 SyntacticMatches, 3 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=38, Invalid=342, Unknown=0, NotChecked=0, Total=380 [2018-04-13 08:34:06,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1133 states. [2018-04-13 08:34:06,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1133 to 1124. [2018-04-13 08:34:06,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1124 states. [2018-04-13 08:34:06,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1124 states to 1124 states and 1129 transitions. [2018-04-13 08:34:06,715 INFO L78 Accepts]: Start accepts. Automaton has 1124 states and 1129 transitions. Word has length 1102 [2018-04-13 08:34:06,715 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:34:06,715 INFO L459 AbstractCegarLoop]: Abstraction has 1124 states and 1129 transitions. [2018-04-13 08:34:06,715 INFO L460 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-04-13 08:34:06,715 INFO L276 IsEmpty]: Start isEmpty. Operand 1124 states and 1129 transitions. [2018-04-13 08:34:06,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1109 [2018-04-13 08:34:06,720 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:34:06,721 INFO L355 BasicCegarLoop]: trace histogram [168, 153, 152, 152, 152, 152, 16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:34:06,721 INFO L408 AbstractCegarLoop]: === Iteration 45 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:34:06,721 INFO L82 PathProgramCache]: Analyzing trace with hash -120038399, now seen corresponding path program 36 times [2018-04-13 08:34:06,721 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:34:06,721 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:34:06,722 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:06,722 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:34:06,722 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:06,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:06,778 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:34:07,445 INFO L134 CoverageAnalysis]: Checked inductivity of 75237 backedges. 15547 proven. 740 refuted. 0 times theorem prover too weak. 58950 trivial. 0 not checked. [2018-04-13 08:34:07,445 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:34:07,446 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:34:07,446 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:34:07,723 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 26 check-sat command(s) [2018-04-13 08:34:07,723 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:34:07,810 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:08,183 INFO L134 CoverageAnalysis]: Checked inductivity of 75237 backedges. 14812 proven. 707 refuted. 0 times theorem prover too weak. 59718 trivial. 0 not checked. [2018-04-13 08:34:08,184 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:08,184 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 22] total 42 [2018-04-13 08:34:08,184 INFO L442 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-04-13 08:34:08,184 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-04-13 08:34:08,185 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=376, Invalid=1346, Unknown=0, NotChecked=0, Total=1722 [2018-04-13 08:34:08,185 INFO L87 Difference]: Start difference. First operand 1124 states and 1129 transitions. Second operand 42 states. [2018-04-13 08:34:08,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:34:08,975 INFO L93 Difference]: Finished difference Result 1362 states and 1372 transitions. [2018-04-13 08:34:08,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-04-13 08:34:08,975 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 1108 [2018-04-13 08:34:08,975 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:34:08,977 INFO L225 Difference]: With dead ends: 1362 [2018-04-13 08:34:08,977 INFO L226 Difference]: Without dead ends: 1362 [2018-04-13 08:34:08,978 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1179 GetRequests, 1105 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 887 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1343, Invalid=4357, Unknown=0, NotChecked=0, Total=5700 [2018-04-13 08:34:08,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1362 states. [2018-04-13 08:34:08,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1362 to 1358. [2018-04-13 08:34:08,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1358 states. [2018-04-13 08:34:08,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1358 states to 1358 states and 1368 transitions. [2018-04-13 08:34:08,987 INFO L78 Accepts]: Start accepts. Automaton has 1358 states and 1368 transitions. Word has length 1108 [2018-04-13 08:34:08,988 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:34:08,988 INFO L459 AbstractCegarLoop]: Abstraction has 1358 states and 1368 transitions. [2018-04-13 08:34:08,988 INFO L460 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-04-13 08:34:08,988 INFO L276 IsEmpty]: Start isEmpty. Operand 1358 states and 1368 transitions. [2018-04-13 08:34:08,998 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1211 [2018-04-13 08:34:08,998 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:34:08,998 INFO L355 BasicCegarLoop]: trace histogram [184, 168, 167, 167, 167, 167, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:34:08,998 INFO L408 AbstractCegarLoop]: === Iteration 46 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:34:08,998 INFO L82 PathProgramCache]: Analyzing trace with hash -1367851287, now seen corresponding path program 37 times [2018-04-13 08:34:08,998 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:34:08,998 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:34:08,999 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:08,999 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:34:08,999 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:09,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:09,042 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:34:09,738 INFO L134 CoverageAnalysis]: Checked inductivity of 90563 backedges. 28558 proven. 2167 refuted. 0 times theorem prover too weak. 59838 trivial. 0 not checked. [2018-04-13 08:34:09,738 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:34:09,738 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:34:09,739 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:34:09,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:09,801 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:10,399 INFO L134 CoverageAnalysis]: Checked inductivity of 90563 backedges. 40543 proven. 660 refuted. 0 times theorem prover too weak. 49360 trivial. 0 not checked. [2018-04-13 08:34:10,399 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:10,426 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 50 [2018-04-13 08:34:10,427 INFO L442 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-04-13 08:34:10,427 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-04-13 08:34:10,427 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=593, Invalid=1857, Unknown=0, NotChecked=0, Total=2450 [2018-04-13 08:34:10,427 INFO L87 Difference]: Start difference. First operand 1358 states and 1368 transitions. Second operand 50 states. [2018-04-13 08:34:10,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:34:10,915 INFO L93 Difference]: Finished difference Result 1244 states and 1248 transitions. [2018-04-13 08:34:10,915 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-04-13 08:34:10,915 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 1210 [2018-04-13 08:34:10,915 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:34:10,917 INFO L225 Difference]: With dead ends: 1244 [2018-04-13 08:34:10,917 INFO L226 Difference]: Without dead ends: 1235 [2018-04-13 08:34:10,917 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1257 GetRequests, 1195 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1345 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=936, Invalid=3096, Unknown=0, NotChecked=0, Total=4032 [2018-04-13 08:34:10,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1235 states. [2018-04-13 08:34:10,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1235 to 1232. [2018-04-13 08:34:10,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1232 states. [2018-04-13 08:34:10,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1232 states to 1232 states and 1236 transitions. [2018-04-13 08:34:10,924 INFO L78 Accepts]: Start accepts. Automaton has 1232 states and 1236 transitions. Word has length 1210 [2018-04-13 08:34:10,924 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:34:10,924 INFO L459 AbstractCegarLoop]: Abstraction has 1232 states and 1236 transitions. [2018-04-13 08:34:10,924 INFO L460 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-04-13 08:34:10,924 INFO L276 IsEmpty]: Start isEmpty. Operand 1232 states and 1236 transitions. [2018-04-13 08:34:10,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1217 [2018-04-13 08:34:10,931 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:34:10,931 INFO L355 BasicCegarLoop]: trace histogram [185, 169, 168, 168, 168, 168, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:34:10,931 INFO L408 AbstractCegarLoop]: === Iteration 47 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:34:10,931 INFO L82 PathProgramCache]: Analyzing trace with hash 1881913057, now seen corresponding path program 38 times [2018-04-13 08:34:10,931 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:34:10,931 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:34:10,932 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:10,932 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:34:10,932 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:10,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:10,974 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:34:11,687 INFO L134 CoverageAnalysis]: Checked inductivity of 91600 backedges. 31016 proven. 752 refuted. 0 times theorem prover too weak. 59832 trivial. 0 not checked. [2018-04-13 08:34:11,687 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:34:11,687 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:34:11,687 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:34:11,746 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:34:11,746 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:34:11,757 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:12,448 INFO L134 CoverageAnalysis]: Checked inductivity of 91600 backedges. 31016 proven. 752 refuted. 0 times theorem prover too weak. 59832 trivial. 0 not checked. [2018-04-13 08:34:12,448 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:12,448 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 53 [2018-04-13 08:34:12,449 INFO L442 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-04-13 08:34:12,449 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-04-13 08:34:12,449 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=664, Invalid=2092, Unknown=0, NotChecked=0, Total=2756 [2018-04-13 08:34:12,449 INFO L87 Difference]: Start difference. First operand 1232 states and 1236 transitions. Second operand 53 states. [2018-04-13 08:34:13,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:34:13,031 INFO L93 Difference]: Finished difference Result 1244 states and 1246 transitions. [2018-04-13 08:34:13,031 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-04-13 08:34:13,031 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 1216 [2018-04-13 08:34:13,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:34:13,033 INFO L225 Difference]: With dead ends: 1244 [2018-04-13 08:34:13,033 INFO L226 Difference]: Without dead ends: 1238 [2018-04-13 08:34:13,034 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1266 GetRequests, 1200 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1531 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1054, Invalid=3502, Unknown=0, NotChecked=0, Total=4556 [2018-04-13 08:34:13,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1238 states. [2018-04-13 08:34:13,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1238 to 1232. [2018-04-13 08:34:13,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1232 states. [2018-04-13 08:34:13,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1232 states to 1232 states and 1234 transitions. [2018-04-13 08:34:13,041 INFO L78 Accepts]: Start accepts. Automaton has 1232 states and 1234 transitions. Word has length 1216 [2018-04-13 08:34:13,041 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:34:13,041 INFO L459 AbstractCegarLoop]: Abstraction has 1232 states and 1234 transitions. [2018-04-13 08:34:13,041 INFO L460 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-04-13 08:34:13,041 INFO L276 IsEmpty]: Start isEmpty. Operand 1232 states and 1234 transitions. [2018-04-13 08:34:13,047 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1223 [2018-04-13 08:34:13,048 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:34:13,048 INFO L355 BasicCegarLoop]: trace histogram [186, 170, 169, 169, 169, 169, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:34:13,048 INFO L408 AbstractCegarLoop]: === Iteration 48 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:34:13,048 INFO L82 PathProgramCache]: Analyzing trace with hash -460291879, now seen corresponding path program 39 times [2018-04-13 08:34:13,048 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:34:13,048 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:34:13,049 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:13,049 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:34:13,049 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:13,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:13,098 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:34:13,598 INFO L134 CoverageAnalysis]: Checked inductivity of 92643 backedges. 16536 proven. 867 refuted. 0 times theorem prover too weak. 75240 trivial. 0 not checked. [2018-04-13 08:34:13,598 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:34:13,598 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:34:13,599 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:34:13,659 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2018-04-13 08:34:13,659 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:34:13,676 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:14,258 INFO L134 CoverageAnalysis]: Checked inductivity of 92643 backedges. 16552 proven. 867 refuted. 0 times theorem prover too weak. 75224 trivial. 0 not checked. [2018-04-13 08:34:14,258 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:14,258 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 22] total 41 [2018-04-13 08:34:14,259 INFO L442 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-04-13 08:34:14,259 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-04-13 08:34:14,259 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=441, Invalid=1281, Unknown=0, NotChecked=0, Total=1722 [2018-04-13 08:34:14,259 INFO L87 Difference]: Start difference. First operand 1232 states and 1234 transitions. Second operand 42 states. [2018-04-13 08:34:14,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:34:14,813 INFO L93 Difference]: Finished difference Result 1247 states and 1250 transitions. [2018-04-13 08:34:14,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-04-13 08:34:14,814 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 1222 [2018-04-13 08:34:14,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:34:14,816 INFO L225 Difference]: With dead ends: 1247 [2018-04-13 08:34:14,816 INFO L226 Difference]: Without dead ends: 1247 [2018-04-13 08:34:14,816 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1259 GetRequests, 1201 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1113 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=872, Invalid=2668, Unknown=0, NotChecked=0, Total=3540 [2018-04-13 08:34:14,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1247 states. [2018-04-13 08:34:14,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1247 to 1238. [2018-04-13 08:34:14,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1238 states. [2018-04-13 08:34:14,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1238 states to 1238 states and 1241 transitions. [2018-04-13 08:34:14,824 INFO L78 Accepts]: Start accepts. Automaton has 1238 states and 1241 transitions. Word has length 1222 [2018-04-13 08:34:14,824 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:34:14,824 INFO L459 AbstractCegarLoop]: Abstraction has 1238 states and 1241 transitions. [2018-04-13 08:34:14,825 INFO L460 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-04-13 08:34:14,825 INFO L276 IsEmpty]: Start isEmpty. Operand 1238 states and 1241 transitions. [2018-04-13 08:34:14,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1229 [2018-04-13 08:34:14,831 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:34:14,831 INFO L355 BasicCegarLoop]: trace histogram [187, 171, 170, 170, 170, 170, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:34:14,831 INFO L408 AbstractCegarLoop]: === Iteration 49 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:34:14,832 INFO L82 PathProgramCache]: Analyzing trace with hash -632087343, now seen corresponding path program 40 times [2018-04-13 08:34:14,832 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:34:14,832 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:34:14,832 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:14,832 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:34:14,832 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:14,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:14,912 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:34:15,627 INFO L134 CoverageAnalysis]: Checked inductivity of 93692 backedges. 18415 proven. 837 refuted. 0 times theorem prover too weak. 74440 trivial. 0 not checked. [2018-04-13 08:34:15,627 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:34:15,627 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:34:15,627 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:34:15,703 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:34:15,703 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:34:15,713 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:16,979 INFO L134 CoverageAnalysis]: Checked inductivity of 93692 backedges. 31279 proven. 2758 refuted. 0 times theorem prover too weak. 59655 trivial. 0 not checked. [2018-04-13 08:34:16,979 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:16,979 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 43] total 78 [2018-04-13 08:34:16,980 INFO L442 AbstractCegarLoop]: Interpolant automaton has 78 states [2018-04-13 08:34:16,980 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2018-04-13 08:34:16,980 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=994, Invalid=5012, Unknown=0, NotChecked=0, Total=6006 [2018-04-13 08:34:16,980 INFO L87 Difference]: Start difference. First operand 1238 states and 1241 transitions. Second operand 78 states. [2018-04-13 08:34:18,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:34:18,550 INFO L93 Difference]: Finished difference Result 1372 states and 1376 transitions. [2018-04-13 08:34:18,550 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2018-04-13 08:34:18,550 INFO L78 Accepts]: Start accepts. Automaton has 78 states. Word has length 1228 [2018-04-13 08:34:18,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:34:18,553 INFO L225 Difference]: With dead ends: 1372 [2018-04-13 08:34:18,553 INFO L226 Difference]: Without dead ends: 1372 [2018-04-13 08:34:18,554 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1320 GetRequests, 1191 SyntacticMatches, 0 SemanticMatches, 129 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3927 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2976, Invalid=14054, Unknown=0, NotChecked=0, Total=17030 [2018-04-13 08:34:18,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states. [2018-04-13 08:34:18,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1364. [2018-04-13 08:34:18,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1364 states. [2018-04-13 08:34:18,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1364 states to 1364 states and 1368 transitions. [2018-04-13 08:34:18,560 INFO L78 Accepts]: Start accepts. Automaton has 1364 states and 1368 transitions. Word has length 1228 [2018-04-13 08:34:18,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:34:18,561 INFO L459 AbstractCegarLoop]: Abstraction has 1364 states and 1368 transitions. [2018-04-13 08:34:18,561 INFO L460 AbstractCegarLoop]: Interpolant automaton has 78 states. [2018-04-13 08:34:18,561 INFO L276 IsEmpty]: Start isEmpty. Operand 1364 states and 1368 transitions. [2018-04-13 08:34:18,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1349 [2018-04-13 08:34:18,568 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:34:18,569 INFO L355 BasicCegarLoop]: trace histogram [206, 189, 188, 188, 188, 188, 18, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:34:18,569 INFO L408 AbstractCegarLoop]: === Iteration 50 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:34:18,569 INFO L82 PathProgramCache]: Analyzing trace with hash -1478054495, now seen corresponding path program 41 times [2018-04-13 08:34:18,569 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:34:18,569 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:34:18,570 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:18,570 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:34:18,570 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:18,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:18,625 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:34:19,231 INFO L134 CoverageAnalysis]: Checked inductivity of 114175 backedges. 19516 proven. 972 refuted. 0 times theorem prover too weak. 93687 trivial. 0 not checked. [2018-04-13 08:34:19,231 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:34:19,231 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:34:19,232 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:34:21,574 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 37 check-sat command(s) [2018-04-13 08:34:21,574 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:34:21,992 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:22,527 INFO L134 CoverageAnalysis]: Checked inductivity of 114175 backedges. 19516 proven. 972 refuted. 0 times theorem prover too weak. 93687 trivial. 0 not checked. [2018-04-13 08:34:22,528 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:22,528 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 40 [2018-04-13 08:34:22,529 INFO L442 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-04-13 08:34:22,529 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-04-13 08:34:22,529 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=420, Invalid=1220, Unknown=0, NotChecked=0, Total=1640 [2018-04-13 08:34:22,529 INFO L87 Difference]: Start difference. First operand 1364 states and 1368 transitions. Second operand 41 states. [2018-04-13 08:34:22,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:34:22,946 INFO L93 Difference]: Finished difference Result 1379 states and 1384 transitions. [2018-04-13 08:34:22,947 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-04-13 08:34:22,947 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 1348 [2018-04-13 08:34:22,947 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:34:22,949 INFO L225 Difference]: With dead ends: 1379 [2018-04-13 08:34:22,949 INFO L226 Difference]: Without dead ends: 1379 [2018-04-13 08:34:22,949 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1368 GetRequests, 1328 SyntacticMatches, 1 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 715 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=420, Invalid=1220, Unknown=0, NotChecked=0, Total=1640 [2018-04-13 08:34:22,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1379 states. [2018-04-13 08:34:22,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1379 to 1370. [2018-04-13 08:34:22,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1370 states. [2018-04-13 08:34:22,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1370 states to 1370 states and 1375 transitions. [2018-04-13 08:34:22,956 INFO L78 Accepts]: Start accepts. Automaton has 1370 states and 1375 transitions. Word has length 1348 [2018-04-13 08:34:22,957 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:34:22,957 INFO L459 AbstractCegarLoop]: Abstraction has 1370 states and 1375 transitions. [2018-04-13 08:34:22,957 INFO L460 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-04-13 08:34:22,957 INFO L276 IsEmpty]: Start isEmpty. Operand 1370 states and 1375 transitions. [2018-04-13 08:34:22,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1355 [2018-04-13 08:34:22,964 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:34:22,965 INFO L355 BasicCegarLoop]: trace histogram [207, 190, 189, 189, 189, 189, 18, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:34:22,965 INFO L408 AbstractCegarLoop]: === Iteration 51 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:34:22,965 INFO L82 PathProgramCache]: Analyzing trace with hash 724997017, now seen corresponding path program 42 times [2018-04-13 08:34:22,965 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:34:22,965 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:34:22,965 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:22,965 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:34:22,965 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:23,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:23,018 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:34:23,898 INFO L134 CoverageAnalysis]: Checked inductivity of 115340 backedges. 21614 proven. 940 refuted. 0 times theorem prover too weak. 92786 trivial. 0 not checked. [2018-04-13 08:34:23,898 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:34:23,898 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:34:23,899 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:34:25,719 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 36 check-sat command(s) [2018-04-13 08:34:25,719 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:34:25,857 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:26,496 INFO L134 CoverageAnalysis]: Checked inductivity of 115340 backedges. 20567 proven. 5569 refuted. 0 times theorem prover too weak. 89204 trivial. 0 not checked. [2018-04-13 08:34:26,496 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:26,496 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 28] total 51 [2018-04-13 08:34:26,497 INFO L442 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-04-13 08:34:26,497 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-04-13 08:34:26,497 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=459, Invalid=2091, Unknown=0, NotChecked=0, Total=2550 [2018-04-13 08:34:26,497 INFO L87 Difference]: Start difference. First operand 1370 states and 1375 transitions. Second operand 51 states. [2018-04-13 08:34:27,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:34:27,466 INFO L93 Difference]: Finished difference Result 1635 states and 1645 transitions. [2018-04-13 08:34:27,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-04-13 08:34:27,466 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 1354 [2018-04-13 08:34:27,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:34:27,469 INFO L225 Difference]: With dead ends: 1635 [2018-04-13 08:34:27,469 INFO L226 Difference]: Without dead ends: 1635 [2018-04-13 08:34:27,470 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1436 GetRequests, 1346 SyntacticMatches, 0 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1585 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1784, Invalid=6588, Unknown=0, NotChecked=0, Total=8372 [2018-04-13 08:34:27,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1635 states. [2018-04-13 08:34:27,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1635 to 1628. [2018-04-13 08:34:27,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1628 states. [2018-04-13 08:34:27,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1628 states to 1628 states and 1638 transitions. [2018-04-13 08:34:27,482 INFO L78 Accepts]: Start accepts. Automaton has 1628 states and 1638 transitions. Word has length 1354 [2018-04-13 08:34:27,482 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:34:27,482 INFO L459 AbstractCegarLoop]: Abstraction has 1628 states and 1638 transitions. [2018-04-13 08:34:27,483 INFO L460 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-04-13 08:34:27,483 INFO L276 IsEmpty]: Start isEmpty. Operand 1628 states and 1638 transitions. [2018-04-13 08:34:27,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1469 [2018-04-13 08:34:27,491 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:34:27,492 INFO L355 BasicCegarLoop]: trace histogram [225, 207, 206, 206, 206, 206, 19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:34:27,492 INFO L408 AbstractCegarLoop]: === Iteration 52 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:34:27,492 INFO L82 PathProgramCache]: Analyzing trace with hash 839607921, now seen corresponding path program 43 times [2018-04-13 08:34:27,492 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:34:27,492 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:34:27,493 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:27,493 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:34:27,493 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:27,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:27,546 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:34:28,506 INFO L134 CoverageAnalysis]: Checked inductivity of 136686 backedges. 40033 proven. 2761 refuted. 0 times theorem prover too weak. 93892 trivial. 0 not checked. [2018-04-13 08:34:28,506 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:34:28,506 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:34:28,507 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:34:28,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:28,589 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:29,396 INFO L134 CoverageAnalysis]: Checked inductivity of 136686 backedges. 57190 proven. 850 refuted. 0 times theorem prover too weak. 78646 trivial. 0 not checked. [2018-04-13 08:34:29,396 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:29,396 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 56 [2018-04-13 08:34:29,397 INFO L442 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-04-13 08:34:29,397 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-04-13 08:34:29,397 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=739, Invalid=2341, Unknown=0, NotChecked=0, Total=3080 [2018-04-13 08:34:29,397 INFO L87 Difference]: Start difference. First operand 1628 states and 1638 transitions. Second operand 56 states. [2018-04-13 08:34:30,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:34:30,115 INFO L93 Difference]: Finished difference Result 1502 states and 1506 transitions. [2018-04-13 08:34:30,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-04-13 08:34:30,116 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 1468 [2018-04-13 08:34:30,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:34:30,119 INFO L225 Difference]: With dead ends: 1502 [2018-04-13 08:34:30,119 INFO L226 Difference]: Without dead ends: 1493 [2018-04-13 08:34:30,119 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1521 GetRequests, 1451 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1729 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1179, Invalid=3933, Unknown=0, NotChecked=0, Total=5112 [2018-04-13 08:34:30,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1493 states. [2018-04-13 08:34:30,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1493 to 1490. [2018-04-13 08:34:30,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1490 states. [2018-04-13 08:34:30,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1490 states to 1490 states and 1494 transitions. [2018-04-13 08:34:30,129 INFO L78 Accepts]: Start accepts. Automaton has 1490 states and 1494 transitions. Word has length 1468 [2018-04-13 08:34:30,129 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:34:30,129 INFO L459 AbstractCegarLoop]: Abstraction has 1490 states and 1494 transitions. [2018-04-13 08:34:30,129 INFO L460 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-04-13 08:34:30,129 INFO L276 IsEmpty]: Start isEmpty. Operand 1490 states and 1494 transitions. [2018-04-13 08:34:30,138 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1475 [2018-04-13 08:34:30,138 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:34:30,139 INFO L355 BasicCegarLoop]: trace histogram [226, 208, 207, 207, 207, 207, 19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:34:30,139 INFO L408 AbstractCegarLoop]: === Iteration 53 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:34:30,139 INFO L82 PathProgramCache]: Analyzing trace with hash -637855639, now seen corresponding path program 44 times [2018-04-13 08:34:30,139 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:34:30,139 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:34:30,140 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:30,140 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:34:30,140 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:30,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:30,232 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:34:31,356 INFO L134 CoverageAnalysis]: Checked inductivity of 137961 backedges. 43121 proven. 954 refuted. 0 times theorem prover too weak. 93886 trivial. 0 not checked. [2018-04-13 08:34:31,356 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:34:31,356 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:34:31,357 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:34:31,432 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:34:31,432 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:34:31,445 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:32,561 INFO L134 CoverageAnalysis]: Checked inductivity of 137961 backedges. 23606 proven. 1009 refuted. 0 times theorem prover too weak. 113346 trivial. 0 not checked. [2018-04-13 08:34:32,561 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:32,561 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 35] total 74 [2018-04-13 08:34:32,562 INFO L442 AbstractCegarLoop]: Interpolant automaton has 74 states [2018-04-13 08:34:32,562 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2018-04-13 08:34:32,563 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=719, Invalid=4683, Unknown=0, NotChecked=0, Total=5402 [2018-04-13 08:34:32,563 INFO L87 Difference]: Start difference. First operand 1490 states and 1494 transitions. Second operand 74 states. [2018-04-13 08:34:34,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:34:34,526 INFO L93 Difference]: Finished difference Result 1637 states and 1640 transitions. [2018-04-13 08:34:34,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-04-13 08:34:34,526 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 1474 [2018-04-13 08:34:34,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:34:34,529 INFO L225 Difference]: With dead ends: 1637 [2018-04-13 08:34:34,529 INFO L226 Difference]: Without dead ends: 1628 [2018-04-13 08:34:34,531 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1607 GetRequests, 1460 SyntacticMatches, 0 SemanticMatches, 147 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6154 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2749, Invalid=19303, Unknown=0, NotChecked=0, Total=22052 [2018-04-13 08:34:34,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1628 states. [2018-04-13 08:34:34,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1628 to 1616. [2018-04-13 08:34:34,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1616 states. [2018-04-13 08:34:34,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1616 states to 1616 states and 1619 transitions. [2018-04-13 08:34:34,538 INFO L78 Accepts]: Start accepts. Automaton has 1616 states and 1619 transitions. Word has length 1474 [2018-04-13 08:34:34,538 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:34:34,538 INFO L459 AbstractCegarLoop]: Abstraction has 1616 states and 1619 transitions. [2018-04-13 08:34:34,538 INFO L460 AbstractCegarLoop]: Interpolant automaton has 74 states. [2018-04-13 08:34:34,538 INFO L276 IsEmpty]: Start isEmpty. Operand 1616 states and 1619 transitions. [2018-04-13 08:34:34,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1607 [2018-04-13 08:34:34,548 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:34:34,548 INFO L355 BasicCegarLoop]: trace histogram [247, 228, 227, 227, 227, 227, 20, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:34:34,548 INFO L408 AbstractCegarLoop]: === Iteration 54 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:34:34,549 INFO L82 PathProgramCache]: Analyzing trace with hash -119949527, now seen corresponding path program 45 times [2018-04-13 08:34:34,549 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:34:34,549 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:34:34,549 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:34,549 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:34:34,549 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:34,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:34,606 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:34:35,759 INFO L134 CoverageAnalysis]: Checked inductivity of 165398 backedges. 48915 proven. 1064 refuted. 0 times theorem prover too weak. 115419 trivial. 0 not checked. [2018-04-13 08:34:35,759 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:34:35,759 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:34:35,760 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:34:35,831 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 20 check-sat command(s) [2018-04-13 08:34:35,831 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:34:35,850 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:36,798 INFO L134 CoverageAnalysis]: Checked inductivity of 165398 backedges. 25096 proven. 1083 refuted. 0 times theorem prover too weak. 139219 trivial. 0 not checked. [2018-04-13 08:34:36,798 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:36,799 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 21] total 62 [2018-04-13 08:34:36,800 INFO L442 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-04-13 08:34:36,800 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-04-13 08:34:36,800 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=483, Invalid=3299, Unknown=0, NotChecked=0, Total=3782 [2018-04-13 08:34:36,800 INFO L87 Difference]: Start difference. First operand 1616 states and 1619 transitions. Second operand 62 states. [2018-04-13 08:34:38,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:34:38,969 INFO L93 Difference]: Finished difference Result 1644 states and 1647 transitions. [2018-04-13 08:34:38,969 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-04-13 08:34:38,969 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 1606 [2018-04-13 08:34:38,970 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:34:38,973 INFO L225 Difference]: With dead ends: 1644 [2018-04-13 08:34:38,973 INFO L226 Difference]: Without dead ends: 1638 [2018-04-13 08:34:38,974 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1684 GetRequests, 1587 SyntacticMatches, 0 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2469 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=991, Invalid=8711, Unknown=0, NotChecked=0, Total=9702 [2018-04-13 08:34:38,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1638 states. [2018-04-13 08:34:38,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1638 to 1628. [2018-04-13 08:34:38,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1628 states. [2018-04-13 08:34:38,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1628 states to 1628 states and 1631 transitions. [2018-04-13 08:34:38,983 INFO L78 Accepts]: Start accepts. Automaton has 1628 states and 1631 transitions. Word has length 1606 [2018-04-13 08:34:38,983 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:34:38,983 INFO L459 AbstractCegarLoop]: Abstraction has 1628 states and 1631 transitions. [2018-04-13 08:34:38,983 INFO L460 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-04-13 08:34:38,983 INFO L276 IsEmpty]: Start isEmpty. Operand 1628 states and 1631 transitions. [2018-04-13 08:34:38,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1619 [2018-04-13 08:34:38,993 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:34:38,994 INFO L355 BasicCegarLoop]: trace histogram [249, 230, 229, 229, 229, 229, 20, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:34:38,994 INFO L408 AbstractCegarLoop]: === Iteration 55 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:34:38,994 INFO L82 PathProgramCache]: Analyzing trace with hash 180154649, now seen corresponding path program 46 times [2018-04-13 08:34:38,994 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:34:38,994 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:34:38,995 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:38,995 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:34:38,995 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:39,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:39,067 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:34:39,907 INFO L134 CoverageAnalysis]: Checked inductivity of 168210 backedges. 26505 proven. 1200 refuted. 0 times theorem prover too weak. 140505 trivial. 0 not checked. [2018-04-13 08:34:39,907 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:34:39,907 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:34:39,908 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:34:40,086 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:34:40,086 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:34:40,111 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:40,858 INFO L134 CoverageAnalysis]: Checked inductivity of 168210 backedges. 26505 proven. 1200 refuted. 0 times theorem prover too weak. 140505 trivial. 0 not checked. [2018-04-13 08:34:40,858 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:40,859 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 22] total 43 [2018-04-13 08:34:40,860 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-04-13 08:34:40,860 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-04-13 08:34:40,860 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=443, Invalid=1449, Unknown=0, NotChecked=0, Total=1892 [2018-04-13 08:34:40,860 INFO L87 Difference]: Start difference. First operand 1628 states and 1631 transitions. Second operand 44 states. [2018-04-13 08:34:41,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:34:41,465 INFO L93 Difference]: Finished difference Result 1656 states and 1661 transitions. [2018-04-13 08:34:41,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-04-13 08:34:41,466 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 1618 [2018-04-13 08:34:41,466 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:34:41,468 INFO L225 Difference]: With dead ends: 1656 [2018-04-13 08:34:41,468 INFO L226 Difference]: Without dead ends: 1656 [2018-04-13 08:34:41,469 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1640 GetRequests, 1598 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 741 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=443, Invalid=1449, Unknown=0, NotChecked=0, Total=1892 [2018-04-13 08:34:41,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1656 states. [2018-04-13 08:34:41,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1656 to 1634. [2018-04-13 08:34:41,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1634 states. [2018-04-13 08:34:41,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1634 states to 1634 states and 1638 transitions. [2018-04-13 08:34:41,475 INFO L78 Accepts]: Start accepts. Automaton has 1634 states and 1638 transitions. Word has length 1618 [2018-04-13 08:34:41,476 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:34:41,476 INFO L459 AbstractCegarLoop]: Abstraction has 1634 states and 1638 transitions. [2018-04-13 08:34:41,476 INFO L460 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-04-13 08:34:41,476 INFO L276 IsEmpty]: Start isEmpty. Operand 1634 states and 1638 transitions. [2018-04-13 08:34:41,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1625 [2018-04-13 08:34:41,486 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:34:41,486 INFO L355 BasicCegarLoop]: trace histogram [250, 231, 230, 230, 230, 230, 20, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:34:41,487 INFO L408 AbstractCegarLoop]: === Iteration 56 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:34:41,487 INFO L82 PathProgramCache]: Analyzing trace with hash -1560650479, now seen corresponding path program 47 times [2018-04-13 08:34:41,487 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:34:41,487 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:34:41,487 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:41,487 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:34:41,487 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:41,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:41,588 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:34:42,717 INFO L134 CoverageAnalysis]: Checked inductivity of 169625 backedges. 29077 proven. 1164 refuted. 0 times theorem prover too weak. 139384 trivial. 0 not checked. [2018-04-13 08:34:42,718 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:34:42,718 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:34:42,718 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:34:47,619 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 49 check-sat command(s) [2018-04-13 08:34:47,619 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:34:48,219 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:49,820 INFO L134 CoverageAnalysis]: Checked inductivity of 169625 backedges. 29011 proven. 6824 refuted. 0 times theorem prover too weak. 133790 trivial. 0 not checked. [2018-04-13 08:34:49,820 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:49,821 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 50] total 74 [2018-04-13 08:34:49,821 INFO L442 AbstractCegarLoop]: Interpolant automaton has 74 states [2018-04-13 08:34:49,821 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2018-04-13 08:34:49,822 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1083, Invalid=4319, Unknown=0, NotChecked=0, Total=5402 [2018-04-13 08:34:49,822 INFO L87 Difference]: Start difference. First operand 1634 states and 1638 transitions. Second operand 74 states. [2018-04-13 08:34:51,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:34:51,236 INFO L93 Difference]: Finished difference Result 1789 states and 1794 transitions. [2018-04-13 08:34:51,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2018-04-13 08:34:51,236 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 1624 [2018-04-13 08:34:51,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:34:51,240 INFO L225 Difference]: With dead ends: 1789 [2018-04-13 08:34:51,240 INFO L226 Difference]: Without dead ends: 1789 [2018-04-13 08:34:51,242 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1714 GetRequests, 1597 SyntacticMatches, 0 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2712 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2962, Invalid=11080, Unknown=0, NotChecked=0, Total=14042 [2018-04-13 08:34:51,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1789 states. [2018-04-13 08:34:51,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1789 to 1778. [2018-04-13 08:34:51,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1778 states. [2018-04-13 08:34:51,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1778 states to 1778 states and 1783 transitions. [2018-04-13 08:34:51,255 INFO L78 Accepts]: Start accepts. Automaton has 1778 states and 1783 transitions. Word has length 1624 [2018-04-13 08:34:51,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:34:51,256 INFO L459 AbstractCegarLoop]: Abstraction has 1778 states and 1783 transitions. [2018-04-13 08:34:51,256 INFO L460 AbstractCegarLoop]: Interpolant automaton has 74 states. [2018-04-13 08:34:51,256 INFO L276 IsEmpty]: Start isEmpty. Operand 1778 states and 1783 transitions. [2018-04-13 08:34:51,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1757 [2018-04-13 08:34:51,271 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:34:51,271 INFO L355 BasicCegarLoop]: trace histogram [271, 251, 250, 250, 250, 250, 21, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:34:51,272 INFO L408 AbstractCegarLoop]: === Iteration 57 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:34:51,272 INFO L82 PathProgramCache]: Analyzing trace with hash 963996625, now seen corresponding path program 48 times [2018-04-13 08:34:51,272 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:34:51,272 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:34:51,272 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:51,272 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:34:51,272 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:51,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:51,339 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:34:52,902 INFO L134 CoverageAnalysis]: Checked inductivity of 199920 backedges. 55569 proven. 3846 refuted. 0 times theorem prover too weak. 140505 trivial. 0 not checked. [2018-04-13 08:34:52,902 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:34:52,902 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:34:52,903 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:34:53,577 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2018-04-13 08:34:53,577 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:34:53,620 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:54,827 INFO L134 CoverageAnalysis]: Checked inductivity of 199920 backedges. 30421 proven. 1323 refuted. 0 times theorem prover too weak. 168176 trivial. 0 not checked. [2018-04-13 08:34:54,827 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:54,828 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 24] total 73 [2018-04-13 08:34:54,828 INFO L442 AbstractCegarLoop]: Interpolant automaton has 73 states [2018-04-13 08:34:54,828 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2018-04-13 08:34:54,828 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=819, Invalid=4437, Unknown=0, NotChecked=0, Total=5256 [2018-04-13 08:34:54,829 INFO L87 Difference]: Start difference. First operand 1778 states and 1783 transitions. Second operand 73 states. [2018-04-13 08:34:56,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:34:56,854 INFO L93 Difference]: Finished difference Result 2080 states and 2090 transitions. [2018-04-13 08:34:56,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2018-04-13 08:34:56,854 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 1756 [2018-04-13 08:34:56,855 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:34:56,858 INFO L225 Difference]: With dead ends: 2080 [2018-04-13 08:34:56,858 INFO L226 Difference]: Without dead ends: 2080 [2018-04-13 08:34:56,859 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1870 GetRequests, 1734 SyntacticMatches, 0 SemanticMatches, 136 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4536 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=4305, Invalid=14601, Unknown=0, NotChecked=0, Total=18906 [2018-04-13 08:34:56,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2080 states. [2018-04-13 08:34:56,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2080 to 1928. [2018-04-13 08:34:56,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1928 states. [2018-04-13 08:34:56,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 1936 transitions. [2018-04-13 08:34:56,868 INFO L78 Accepts]: Start accepts. Automaton has 1928 states and 1936 transitions. Word has length 1756 [2018-04-13 08:34:56,868 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:34:56,868 INFO L459 AbstractCegarLoop]: Abstraction has 1928 states and 1936 transitions. [2018-04-13 08:34:56,868 INFO L460 AbstractCegarLoop]: Interpolant automaton has 73 states. [2018-04-13 08:34:56,868 INFO L276 IsEmpty]: Start isEmpty. Operand 1928 states and 1936 transitions. [2018-04-13 08:34:56,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1769 [2018-04-13 08:34:56,880 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:34:56,880 INFO L355 BasicCegarLoop]: trace histogram [273, 253, 252, 252, 252, 252, 21, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:34:56,880 INFO L408 AbstractCegarLoop]: === Iteration 58 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:34:56,881 INFO L82 PathProgramCache]: Analyzing trace with hash 1179183553, now seen corresponding path program 49 times [2018-04-13 08:34:56,881 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:34:56,881 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:34:56,881 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:56,881 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:34:56,881 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:34:56,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:56,953 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:34:58,391 INFO L134 CoverageAnalysis]: Checked inductivity of 203012 backedges. 33377 proven. 1285 refuted. 0 times theorem prover too weak. 168350 trivial. 0 not checked. [2018-04-13 08:34:58,391 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:34:58,391 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:34:58,392 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:34:58,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:34:58,502 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:34:59,928 INFO L134 CoverageAnalysis]: Checked inductivity of 203012 backedges. 33442 proven. 1220 refuted. 0 times theorem prover too weak. 168350 trivial. 0 not checked. [2018-04-13 08:34:59,928 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:34:59,928 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 47] total 72 [2018-04-13 08:34:59,929 INFO L442 AbstractCegarLoop]: Interpolant automaton has 72 states [2018-04-13 08:34:59,929 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2018-04-13 08:34:59,929 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1177, Invalid=3935, Unknown=0, NotChecked=0, Total=5112 [2018-04-13 08:34:59,929 INFO L87 Difference]: Start difference. First operand 1928 states and 1936 transitions. Second operand 72 states. [2018-04-13 08:35:01,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:35:01,291 INFO L93 Difference]: Finished difference Result 2226 states and 2238 transitions. [2018-04-13 08:35:01,291 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-04-13 08:35:01,291 INFO L78 Accepts]: Start accepts. Automaton has 72 states. Word has length 1768 [2018-04-13 08:35:01,292 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:35:01,295 INFO L225 Difference]: With dead ends: 2226 [2018-04-13 08:35:01,295 INFO L226 Difference]: Without dead ends: 2226 [2018-04-13 08:35:01,295 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1858 GetRequests, 1745 SyntacticMatches, 0 SemanticMatches, 113 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2204 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=3324, Invalid=9786, Unknown=0, NotChecked=0, Total=13110 [2018-04-13 08:35:01,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2226 states. [2018-04-13 08:35:01,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2226 to 2213. [2018-04-13 08:35:01,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2213 states. [2018-04-13 08:35:01,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2213 states to 2213 states and 2225 transitions. [2018-04-13 08:35:01,306 INFO L78 Accepts]: Start accepts. Automaton has 2213 states and 2225 transitions. Word has length 1768 [2018-04-13 08:35:01,307 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:35:01,307 INFO L459 AbstractCegarLoop]: Abstraction has 2213 states and 2225 transitions. [2018-04-13 08:35:01,307 INFO L460 AbstractCegarLoop]: Interpolant automaton has 72 states. [2018-04-13 08:35:01,307 INFO L276 IsEmpty]: Start isEmpty. Operand 2213 states and 2225 transitions. [2018-04-13 08:35:01,321 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1901 [2018-04-13 08:35:01,321 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:35:01,322 INFO L355 BasicCegarLoop]: trace histogram [294, 273, 272, 272, 272, 272, 22, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:35:01,322 INFO L408 AbstractCegarLoop]: === Iteration 59 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:35:01,322 INFO L82 PathProgramCache]: Analyzing trace with hash -1197311871, now seen corresponding path program 50 times [2018-04-13 08:35:01,322 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:35:01,322 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:35:01,323 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:01,323 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:35:01,323 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:01,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:35:01,410 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:35:03,279 INFO L134 CoverageAnalysis]: Checked inductivity of 236043 backedges. 66333 proven. 1302 refuted. 0 times theorem prover too weak. 168408 trivial. 0 not checked. [2018-04-13 08:35:03,279 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:35:03,279 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:35:03,280 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:35:03,382 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:35:03,383 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:35:03,403 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:35:04,760 INFO L134 CoverageAnalysis]: Checked inductivity of 236043 backedges. 66333 proven. 1302 refuted. 0 times theorem prover too weak. 168408 trivial. 0 not checked. [2018-04-13 08:35:04,760 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:35:04,761 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46] total 68 [2018-04-13 08:35:04,761 INFO L442 AbstractCegarLoop]: Interpolant automaton has 68 states [2018-04-13 08:35:04,761 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2018-04-13 08:35:04,762 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1079, Invalid=3477, Unknown=0, NotChecked=0, Total=4556 [2018-04-13 08:35:04,762 INFO L87 Difference]: Start difference. First operand 2213 states and 2225 transitions. Second operand 68 states. [2018-04-13 08:35:05,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:35:05,617 INFO L93 Difference]: Finished difference Result 2090 states and 2094 transitions. [2018-04-13 08:35:05,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-04-13 08:35:05,617 INFO L78 Accepts]: Start accepts. Automaton has 68 states. Word has length 1900 [2018-04-13 08:35:05,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:35:05,620 INFO L225 Difference]: With dead ends: 2090 [2018-04-13 08:35:05,620 INFO L226 Difference]: Without dead ends: 1937 [2018-04-13 08:35:05,621 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1965 GetRequests, 1879 SyntacticMatches, 0 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2641 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1749, Invalid=5907, Unknown=0, NotChecked=0, Total=7656 [2018-04-13 08:35:05,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1937 states. [2018-04-13 08:35:05,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1937 to 1928. [2018-04-13 08:35:05,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1928 states. [2018-04-13 08:35:05,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 1931 transitions. [2018-04-13 08:35:05,631 INFO L78 Accepts]: Start accepts. Automaton has 1928 states and 1931 transitions. Word has length 1900 [2018-04-13 08:35:05,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:35:05,632 INFO L459 AbstractCegarLoop]: Abstraction has 1928 states and 1931 transitions. [2018-04-13 08:35:05,632 INFO L460 AbstractCegarLoop]: Interpolant automaton has 68 states. [2018-04-13 08:35:05,632 INFO L276 IsEmpty]: Start isEmpty. Operand 1928 states and 1931 transitions. [2018-04-13 08:35:05,646 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1913 [2018-04-13 08:35:05,646 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:35:05,647 INFO L355 BasicCegarLoop]: trace histogram [296, 275, 274, 274, 274, 274, 22, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:35:05,647 INFO L408 AbstractCegarLoop]: === Iteration 60 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:35:05,647 INFO L82 PathProgramCache]: Analyzing trace with hash 1548555889, now seen corresponding path program 51 times [2018-04-13 08:35:05,647 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:35:05,648 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:35:05,648 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:05,648 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:35:05,648 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:05,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:35:05,740 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:35:06,891 INFO L134 CoverageAnalysis]: Checked inductivity of 239403 backedges. 34986 proven. 1452 refuted. 0 times theorem prover too weak. 202965 trivial. 0 not checked. [2018-04-13 08:35:06,891 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:35:06,891 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:35:06,891 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:35:07,061 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 23 check-sat command(s) [2018-04-13 08:35:07,061 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:35:07,105 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:35:07,994 INFO L134 CoverageAnalysis]: Checked inductivity of 239403 backedges. 34986 proven. 1452 refuted. 0 times theorem prover too weak. 202965 trivial. 0 not checked. [2018-04-13 08:35:07,994 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:35:07,994 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 29 [2018-04-13 08:35:07,995 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-04-13 08:35:07,995 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-04-13 08:35:07,995 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=320, Invalid=550, Unknown=0, NotChecked=0, Total=870 [2018-04-13 08:35:07,995 INFO L87 Difference]: Start difference. First operand 1928 states and 1931 transitions. Second operand 30 states. [2018-04-13 08:35:08,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:35:08,353 INFO L93 Difference]: Finished difference Result 1946 states and 1950 transitions. [2018-04-13 08:35:08,353 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-04-13 08:35:08,353 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 1912 [2018-04-13 08:35:08,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:35:08,356 INFO L225 Difference]: With dead ends: 1946 [2018-04-13 08:35:08,357 INFO L226 Difference]: Without dead ends: 1946 [2018-04-13 08:35:08,357 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1957 GetRequests, 1908 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 385 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=886, Invalid=1664, Unknown=0, NotChecked=0, Total=2550 [2018-04-13 08:35:08,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1946 states. [2018-04-13 08:35:08,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1946 to 1934. [2018-04-13 08:35:08,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1934 states. [2018-04-13 08:35:08,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1934 states to 1934 states and 1938 transitions. [2018-04-13 08:35:08,367 INFO L78 Accepts]: Start accepts. Automaton has 1934 states and 1938 transitions. Word has length 1912 [2018-04-13 08:35:08,367 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:35:08,367 INFO L459 AbstractCegarLoop]: Abstraction has 1934 states and 1938 transitions. [2018-04-13 08:35:08,367 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-04-13 08:35:08,367 INFO L276 IsEmpty]: Start isEmpty. Operand 1934 states and 1938 transitions. [2018-04-13 08:35:08,382 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1919 [2018-04-13 08:35:08,382 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:35:08,382 INFO L355 BasicCegarLoop]: trace histogram [297, 276, 275, 275, 275, 275, 22, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:35:08,383 INFO L408 AbstractCegarLoop]: === Iteration 61 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:35:08,383 INFO L82 PathProgramCache]: Analyzing trace with hash -29417367, now seen corresponding path program 52 times [2018-04-13 08:35:08,383 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:35:08,383 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:35:08,383 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:08,383 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:35:08,384 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:08,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:35:08,520 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:35:10,095 INFO L134 CoverageAnalysis]: Checked inductivity of 241092 backedges. 38080 proven. 1412 refuted. 0 times theorem prover too weak. 201600 trivial. 0 not checked. [2018-04-13 08:35:10,095 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:35:10,095 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:35:10,096 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:35:10,192 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:35:10,192 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:35:10,213 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:35:12,672 INFO L134 CoverageAnalysis]: Checked inductivity of 241092 backedges. 66944 proven. 4558 refuted. 0 times theorem prover too weak. 169590 trivial. 0 not checked. [2018-04-13 08:35:12,672 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:35:12,672 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 53] total 98 [2018-04-13 08:35:12,673 INFO L442 AbstractCegarLoop]: Interpolant automaton has 98 states [2018-04-13 08:35:12,673 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2018-04-13 08:35:12,673 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1554, Invalid=7952, Unknown=0, NotChecked=0, Total=9506 [2018-04-13 08:35:12,673 INFO L87 Difference]: Start difference. First operand 1934 states and 1938 transitions. Second operand 98 states. [2018-04-13 08:35:15,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:35:15,084 INFO L93 Difference]: Finished difference Result 2101 states and 2106 transitions. [2018-04-13 08:35:15,084 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 118 states. [2018-04-13 08:35:15,085 INFO L78 Accepts]: Start accepts. Automaton has 98 states. Word has length 1918 [2018-04-13 08:35:15,085 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:35:15,088 INFO L225 Difference]: With dead ends: 2101 [2018-04-13 08:35:15,088 INFO L226 Difference]: Without dead ends: 2101 [2018-04-13 08:35:15,090 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2035 GetRequests, 1871 SyntacticMatches, 0 SemanticMatches, 164 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6457 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=4666, Invalid=22724, Unknown=0, NotChecked=0, Total=27390 [2018-04-13 08:35:15,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2101 states. [2018-04-13 08:35:15,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2101 to 2090. [2018-04-13 08:35:15,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2090 states. [2018-04-13 08:35:15,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2090 states to 2090 states and 2095 transitions. [2018-04-13 08:35:15,107 INFO L78 Accepts]: Start accepts. Automaton has 2090 states and 2095 transitions. Word has length 1918 [2018-04-13 08:35:15,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:35:15,108 INFO L459 AbstractCegarLoop]: Abstraction has 2090 states and 2095 transitions. [2018-04-13 08:35:15,108 INFO L460 AbstractCegarLoop]: Interpolant automaton has 98 states. [2018-04-13 08:35:15,109 INFO L276 IsEmpty]: Start isEmpty. Operand 2090 states and 2095 transitions. [2018-04-13 08:35:15,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2069 [2018-04-13 08:35:15,136 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:35:15,136 INFO L355 BasicCegarLoop]: trace histogram [321, 299, 298, 298, 298, 298, 23, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:35:15,136 INFO L408 AbstractCegarLoop]: === Iteration 62 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:35:15,137 INFO L82 PathProgramCache]: Analyzing trace with hash -1453135599, now seen corresponding path program 53 times [2018-04-13 08:35:15,137 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:35:15,137 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:35:15,138 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:15,138 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:35:15,138 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:15,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:35:15,248 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:35:16,546 INFO L134 CoverageAnalysis]: Checked inductivity of 282450 backedges. 39831 proven. 1587 refuted. 0 times theorem prover too weak. 241032 trivial. 0 not checked. [2018-04-13 08:35:16,546 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:35:16,546 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:35:16,546 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:35:27,934 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 58 check-sat command(s) [2018-04-13 08:35:27,934 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:35:30,049 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:35:31,898 INFO L134 CoverageAnalysis]: Checked inductivity of 282450 backedges. 39831 proven. 1587 refuted. 0 times theorem prover too weak. 241032 trivial. 0 not checked. [2018-04-13 08:35:31,898 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:35:31,898 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 50 [2018-04-13 08:35:31,899 INFO L442 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-04-13 08:35:31,899 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-04-13 08:35:31,899 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=675, Invalid=1875, Unknown=0, NotChecked=0, Total=2550 [2018-04-13 08:35:31,899 INFO L87 Difference]: Start difference. First operand 2090 states and 2095 transitions. Second operand 51 states. [2018-04-13 08:35:32,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:35:32,492 INFO L93 Difference]: Finished difference Result 2108 states and 2114 transitions. [2018-04-13 08:35:32,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-04-13 08:35:32,493 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 2068 [2018-04-13 08:35:32,493 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:35:32,496 INFO L225 Difference]: With dead ends: 2108 [2018-04-13 08:35:32,496 INFO L226 Difference]: Without dead ends: 2108 [2018-04-13 08:35:32,496 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2093 GetRequests, 2043 SyntacticMatches, 1 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1170 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=675, Invalid=1875, Unknown=0, NotChecked=0, Total=2550 [2018-04-13 08:35:32,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2108 states. [2018-04-13 08:35:32,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2108 to 2096. [2018-04-13 08:35:32,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2096 states. [2018-04-13 08:35:32,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2096 states to 2096 states and 2102 transitions. [2018-04-13 08:35:32,507 INFO L78 Accepts]: Start accepts. Automaton has 2096 states and 2102 transitions. Word has length 2068 [2018-04-13 08:35:32,507 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:35:32,507 INFO L459 AbstractCegarLoop]: Abstraction has 2096 states and 2102 transitions. [2018-04-13 08:35:32,507 INFO L460 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-04-13 08:35:32,507 INFO L276 IsEmpty]: Start isEmpty. Operand 2096 states and 2102 transitions. [2018-04-13 08:35:32,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2075 [2018-04-13 08:35:32,523 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:35:32,523 INFO L355 BasicCegarLoop]: trace histogram [322, 300, 299, 299, 299, 299, 23, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:35:32,523 INFO L408 AbstractCegarLoop]: === Iteration 63 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:35:32,524 INFO L82 PathProgramCache]: Analyzing trace with hash 1410628361, now seen corresponding path program 54 times [2018-04-13 08:35:32,524 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:35:32,524 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:35:32,524 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:32,524 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:35:32,525 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:32,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:35:32,614 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:35:34,334 INFO L134 CoverageAnalysis]: Checked inductivity of 284285 backedges. 43204 proven. 1545 refuted. 0 times theorem prover too weak. 239536 trivial. 0 not checked. [2018-04-13 08:35:34,334 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:35:34,334 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:35:34,335 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:35:35,451 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-04-13 08:35:35,451 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:35:35,515 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:35:36,991 INFO L134 CoverageAnalysis]: Checked inductivity of 284285 backedges. 41525 proven. 1728 refuted. 0 times theorem prover too weak. 241032 trivial. 0 not checked. [2018-04-13 08:35:36,991 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:35:36,992 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 27] total 78 [2018-04-13 08:35:36,992 INFO L442 AbstractCegarLoop]: Interpolant automaton has 78 states [2018-04-13 08:35:36,993 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2018-04-13 08:35:36,993 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=983, Invalid=5023, Unknown=0, NotChecked=0, Total=6006 [2018-04-13 08:35:36,993 INFO L87 Difference]: Start difference. First operand 2096 states and 2102 transitions. Second operand 78 states. [2018-04-13 08:35:39,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:35:39,706 INFO L93 Difference]: Finished difference Result 2442 states and 2454 transitions. [2018-04-13 08:35:39,706 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2018-04-13 08:35:39,706 INFO L78 Accepts]: Start accepts. Automaton has 78 states. Word has length 2074 [2018-04-13 08:35:39,707 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:35:39,709 INFO L225 Difference]: With dead ends: 2442 [2018-04-13 08:35:39,710 INFO L226 Difference]: Without dead ends: 2442 [2018-04-13 08:35:39,711 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2199 GetRequests, 2049 SyntacticMatches, 0 SemanticMatches, 150 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5622 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=4539, Invalid=18413, Unknown=0, NotChecked=0, Total=22952 [2018-04-13 08:35:39,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2442 states. [2018-04-13 08:35:39,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2442 to 2420. [2018-04-13 08:35:39,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2420 states. [2018-04-13 08:35:39,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2420 states to 2420 states and 2432 transitions. [2018-04-13 08:35:39,724 INFO L78 Accepts]: Start accepts. Automaton has 2420 states and 2432 transitions. Word has length 2074 [2018-04-13 08:35:39,725 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:35:39,725 INFO L459 AbstractCegarLoop]: Abstraction has 2420 states and 2432 transitions. [2018-04-13 08:35:39,725 INFO L460 AbstractCegarLoop]: Interpolant automaton has 78 states. [2018-04-13 08:35:39,725 INFO L276 IsEmpty]: Start isEmpty. Operand 2420 states and 2432 transitions. [2018-04-13 08:35:39,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2225 [2018-04-13 08:35:39,744 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:35:39,744 INFO L355 BasicCegarLoop]: trace histogram [346, 323, 322, 322, 322, 322, 24, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:35:39,744 INFO L408 AbstractCegarLoop]: === Iteration 64 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:35:39,745 INFO L82 PathProgramCache]: Analyzing trace with hash -251719759, now seen corresponding path program 55 times [2018-04-13 08:35:39,745 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:35:39,745 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:35:39,745 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:39,745 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:35:39,745 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:39,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:35:39,854 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:35:41,817 INFO L134 CoverageAnalysis]: Checked inductivity of 329061 backedges. 83061 proven. 4561 refuted. 0 times theorem prover too weak. 241439 trivial. 0 not checked. [2018-04-13 08:35:41,818 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:35:41,818 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:35:41,818 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:35:41,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:35:41,959 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:35:44,496 INFO L134 CoverageAnalysis]: Checked inductivity of 329061 backedges. 48535 proven. 1610 refuted. 0 times theorem prover too weak. 278916 trivial. 0 not checked. [2018-04-13 08:35:44,497 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:35:44,497 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 53] total 99 [2018-04-13 08:35:44,498 INFO L442 AbstractCegarLoop]: Interpolant automaton has 99 states [2018-04-13 08:35:44,498 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 99 interpolants. [2018-04-13 08:35:44,498 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1281, Invalid=8421, Unknown=0, NotChecked=0, Total=9702 [2018-04-13 08:35:44,498 INFO L87 Difference]: Start difference. First operand 2420 states and 2432 transitions. Second operand 99 states. [2018-04-13 08:35:46,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:35:46,962 INFO L93 Difference]: Finished difference Result 2443 states and 2451 transitions. [2018-04-13 08:35:46,962 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2018-04-13 08:35:46,962 INFO L78 Accepts]: Start accepts. Automaton has 99 states. Word has length 2224 [2018-04-13 08:35:46,963 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:35:46,965 INFO L225 Difference]: With dead ends: 2443 [2018-04-13 08:35:46,965 INFO L226 Difference]: Without dead ends: 2431 [2018-04-13 08:35:46,967 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2369 GetRequests, 2198 SyntacticMatches, 0 SemanticMatches, 171 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8548 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=3332, Invalid=26424, Unknown=0, NotChecked=0, Total=29756 [2018-04-13 08:35:46,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2431 states. [2018-04-13 08:35:46,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2431 to 2414. [2018-04-13 08:35:46,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2414 states. [2018-04-13 08:35:46,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2414 states to 2414 states and 2422 transitions. [2018-04-13 08:35:46,979 INFO L78 Accepts]: Start accepts. Automaton has 2414 states and 2422 transitions. Word has length 2224 [2018-04-13 08:35:46,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:35:46,980 INFO L459 AbstractCegarLoop]: Abstraction has 2414 states and 2422 transitions. [2018-04-13 08:35:46,980 INFO L460 AbstractCegarLoop]: Interpolant automaton has 99 states. [2018-04-13 08:35:46,980 INFO L276 IsEmpty]: Start isEmpty. Operand 2414 states and 2422 transitions. [2018-04-13 08:35:47,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2381 [2018-04-13 08:35:47,002 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:35:47,002 INFO L355 BasicCegarLoop]: trace histogram [371, 347, 346, 346, 346, 346, 25, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:35:47,002 INFO L408 AbstractCegarLoop]: === Iteration 65 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:35:47,003 INFO L82 PathProgramCache]: Analyzing trace with hash -1553431983, now seen corresponding path program 56 times [2018-04-13 08:35:47,003 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:35:47,003 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:35:47,003 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:47,003 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:35:47,003 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:47,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:35:47,116 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:35:49,311 INFO L134 CoverageAnalysis]: Checked inductivity of 379236 backedges. 91753 proven. 4835 refuted. 0 times theorem prover too weak. 282648 trivial. 0 not checked. [2018-04-13 08:35:49,311 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:35:49,311 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:35:49,312 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:35:49,457 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:35:49,457 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:35:49,484 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:35:51,396 INFO L134 CoverageAnalysis]: Checked inductivity of 379236 backedges. 131097 proven. 1564 refuted. 0 times theorem prover too weak. 246575 trivial. 0 not checked. [2018-04-13 08:35:51,397 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:35:51,397 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 74 [2018-04-13 08:35:51,398 INFO L442 AbstractCegarLoop]: Interpolant automaton has 74 states [2018-04-13 08:35:51,398 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2018-04-13 08:35:51,398 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1273, Invalid=4129, Unknown=0, NotChecked=0, Total=5402 [2018-04-13 08:35:51,398 INFO L87 Difference]: Start difference. First operand 2414 states and 2422 transitions. Second operand 74 states. [2018-04-13 08:35:52,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:35:52,340 INFO L93 Difference]: Finished difference Result 2429 states and 2434 transitions. [2018-04-13 08:35:52,340 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-04-13 08:35:52,340 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 2380 [2018-04-13 08:35:52,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:35:52,344 INFO L225 Difference]: With dead ends: 2429 [2018-04-13 08:35:52,344 INFO L226 Difference]: Without dead ends: 2420 [2018-04-13 08:35:52,344 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2451 GetRequests, 2357 SyntacticMatches, 0 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3169 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=2076, Invalid=7044, Unknown=0, NotChecked=0, Total=9120 [2018-04-13 08:35:52,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2420 states. [2018-04-13 08:35:52,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2420 to 2414. [2018-04-13 08:35:52,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2414 states. [2018-04-13 08:35:52,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2414 states to 2414 states and 2419 transitions. [2018-04-13 08:35:52,354 INFO L78 Accepts]: Start accepts. Automaton has 2414 states and 2419 transitions. Word has length 2380 [2018-04-13 08:35:52,355 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:35:52,355 INFO L459 AbstractCegarLoop]: Abstraction has 2414 states and 2419 transitions. [2018-04-13 08:35:52,355 INFO L460 AbstractCegarLoop]: Interpolant automaton has 74 states. [2018-04-13 08:35:52,355 INFO L276 IsEmpty]: Start isEmpty. Operand 2414 states and 2419 transitions. [2018-04-13 08:35:52,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2393 [2018-04-13 08:35:52,376 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:35:52,377 INFO L355 BasicCegarLoop]: trace histogram [373, 349, 348, 348, 348, 348, 25, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:35:52,377 INFO L408 AbstractCegarLoop]: === Iteration 66 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:35:52,377 INFO L82 PathProgramCache]: Analyzing trace with hash -1174542271, now seen corresponding path program 57 times [2018-04-13 08:35:52,377 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:35:52,377 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:35:52,378 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:52,378 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:35:52,378 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:52,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:35:52,479 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:35:54,655 INFO L134 CoverageAnalysis]: Checked inductivity of 383496 backedges. 97316 proven. 1704 refuted. 0 times theorem prover too weak. 284476 trivial. 0 not checked. [2018-04-13 08:35:54,655 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:35:54,656 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:35:54,656 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:35:55,008 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 26 check-sat command(s) [2018-04-13 08:35:55,009 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:35:55,096 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:35:56,952 INFO L134 CoverageAnalysis]: Checked inductivity of 383496 backedges. 50667 proven. 1875 refuted. 0 times theorem prover too weak. 330954 trivial. 0 not checked. [2018-04-13 08:35:56,952 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:35:56,952 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 28] total 79 [2018-04-13 08:35:56,953 INFO L442 AbstractCegarLoop]: Interpolant automaton has 79 states [2018-04-13 08:35:56,953 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2018-04-13 08:35:56,953 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1058, Invalid=5104, Unknown=0, NotChecked=0, Total=6162 [2018-04-13 08:35:56,954 INFO L87 Difference]: Start difference. First operand 2414 states and 2419 transitions. Second operand 79 states. [2018-04-13 08:35:58,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:35:58,857 INFO L93 Difference]: Finished difference Result 2438 states and 2442 transitions. [2018-04-13 08:35:58,857 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2018-04-13 08:35:58,857 INFO L78 Accepts]: Start accepts. Automaton has 79 states. Word has length 2392 [2018-04-13 08:35:58,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:35:58,860 INFO L225 Difference]: With dead ends: 2438 [2018-04-13 08:35:58,860 INFO L226 Difference]: Without dead ends: 2432 [2018-04-13 08:35:58,860 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2490 GetRequests, 2366 SyntacticMatches, 0 SemanticMatches, 124 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4308 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=3226, Invalid=12524, Unknown=0, NotChecked=0, Total=15750 [2018-04-13 08:35:58,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2432 states. [2018-04-13 08:35:58,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2432 to 2420. [2018-04-13 08:35:58,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2420 states. [2018-04-13 08:35:58,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2420 states to 2420 states and 2424 transitions. [2018-04-13 08:35:58,870 INFO L78 Accepts]: Start accepts. Automaton has 2420 states and 2424 transitions. Word has length 2392 [2018-04-13 08:35:58,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:35:58,871 INFO L459 AbstractCegarLoop]: Abstraction has 2420 states and 2424 transitions. [2018-04-13 08:35:58,871 INFO L460 AbstractCegarLoop]: Interpolant automaton has 79 states. [2018-04-13 08:35:58,871 INFO L276 IsEmpty]: Start isEmpty. Operand 2420 states and 2424 transitions. [2018-04-13 08:35:58,892 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2405 [2018-04-13 08:35:58,892 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:35:58,893 INFO L355 BasicCegarLoop]: trace histogram [375, 351, 350, 350, 350, 350, 25, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:35:58,893 INFO L408 AbstractCegarLoop]: === Iteration 67 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:35:58,893 INFO L82 PathProgramCache]: Analyzing trace with hash -1945223631, now seen corresponding path program 58 times [2018-04-13 08:35:58,893 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:35:58,893 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:35:58,894 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:58,894 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:35:58,894 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:35:59,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:35:59,010 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:36:01,260 INFO L134 CoverageAnalysis]: Checked inductivity of 387780 backedges. 54787 proven. 1829 refuted. 0 times theorem prover too weak. 331164 trivial. 0 not checked. [2018-04-13 08:36:01,260 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:36:01,260 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:36:01,261 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:36:01,406 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:36:01,406 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:36:01,445 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:36:05,166 INFO L134 CoverageAnalysis]: Checked inductivity of 387780 backedges. 97715 proven. 5854 refuted. 0 times theorem prover too weak. 284211 trivial. 0 not checked. [2018-04-13 08:36:05,166 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:36:05,166 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 59] total 110 [2018-04-13 08:36:05,167 INFO L442 AbstractCegarLoop]: Interpolant automaton has 110 states [2018-04-13 08:36:05,167 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 110 interpolants. [2018-04-13 08:36:05,168 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1950, Invalid=10040, Unknown=0, NotChecked=0, Total=11990 [2018-04-13 08:36:05,168 INFO L87 Difference]: Start difference. First operand 2420 states and 2424 transitions. Second operand 110 states. [2018-04-13 08:36:08,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:36:08,316 INFO L93 Difference]: Finished difference Result 2605 states and 2610 transitions. [2018-04-13 08:36:08,316 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 133 states. [2018-04-13 08:36:08,316 INFO L78 Accepts]: Start accepts. Automaton has 110 states. Word has length 2404 [2018-04-13 08:36:08,317 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:36:08,319 INFO L225 Difference]: With dead ends: 2605 [2018-04-13 08:36:08,320 INFO L226 Difference]: Without dead ends: 2605 [2018-04-13 08:36:08,321 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2536 GetRequests, 2351 SyntacticMatches, 0 SemanticMatches, 185 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8275 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=5860, Invalid=28922, Unknown=0, NotChecked=0, Total=34782 [2018-04-13 08:36:08,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2605 states. [2018-04-13 08:36:08,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2605 to 2594. [2018-04-13 08:36:08,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2594 states. [2018-04-13 08:36:08,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2594 states to 2594 states and 2599 transitions. [2018-04-13 08:36:08,334 INFO L78 Accepts]: Start accepts. Automaton has 2594 states and 2599 transitions. Word has length 2404 [2018-04-13 08:36:08,335 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:36:08,335 INFO L459 AbstractCegarLoop]: Abstraction has 2594 states and 2599 transitions. [2018-04-13 08:36:08,335 INFO L460 AbstractCegarLoop]: Interpolant automaton has 110 states. [2018-04-13 08:36:08,335 INFO L276 IsEmpty]: Start isEmpty. Operand 2594 states and 2599 transitions. [2018-04-13 08:36:08,359 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2573 [2018-04-13 08:36:08,359 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:36:08,360 INFO L355 BasicCegarLoop]: trace histogram [402, 377, 376, 376, 376, 376, 26, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:36:08,360 INFO L408 AbstractCegarLoop]: === Iteration 68 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:36:08,360 INFO L82 PathProgramCache]: Analyzing trace with hash -585611583, now seen corresponding path program 59 times [2018-04-13 08:36:08,360 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:36:08,361 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:36:08,361 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:36:08,361 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:36:08,361 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:36:08,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:36:08,481 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:36:10,412 INFO L134 CoverageAnalysis]: Checked inductivity of 446703 backedges. 57000 proven. 2028 refuted. 0 times theorem prover too weak. 387675 trivial. 0 not checked. [2018-04-13 08:36:10,413 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:36:10,413 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:36:10,413 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:36:26,525 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 61 check-sat command(s) [2018-04-13 08:36:26,526 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:36:27,359 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:36:29,044 INFO L134 CoverageAnalysis]: Checked inductivity of 446703 backedges. 57000 proven. 2028 refuted. 0 times theorem prover too weak. 387675 trivial. 0 not checked. [2018-04-13 08:36:29,044 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:36:29,045 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 36 [2018-04-13 08:36:29,045 INFO L442 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-04-13 08:36:29,046 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-04-13 08:36:29,046 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=421, Invalid=911, Unknown=0, NotChecked=0, Total=1332 [2018-04-13 08:36:29,046 INFO L87 Difference]: Start difference. First operand 2594 states and 2599 transitions. Second operand 37 states. [2018-04-13 08:36:29,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:36:29,566 INFO L93 Difference]: Finished difference Result 2612 states and 2618 transitions. [2018-04-13 08:36:29,566 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-04-13 08:36:29,566 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 2572 [2018-04-13 08:36:29,567 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:36:29,569 INFO L225 Difference]: With dead ends: 2612 [2018-04-13 08:36:29,569 INFO L226 Difference]: Without dead ends: 2612 [2018-04-13 08:36:29,570 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2625 GetRequests, 2565 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 647 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1184, Invalid=2598, Unknown=0, NotChecked=0, Total=3782 [2018-04-13 08:36:29,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2612 states. [2018-04-13 08:36:29,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2612 to 2600. [2018-04-13 08:36:29,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2600 states. [2018-04-13 08:36:29,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2600 states to 2600 states and 2606 transitions. [2018-04-13 08:36:29,581 INFO L78 Accepts]: Start accepts. Automaton has 2600 states and 2606 transitions. Word has length 2572 [2018-04-13 08:36:29,582 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:36:29,582 INFO L459 AbstractCegarLoop]: Abstraction has 2600 states and 2606 transitions. [2018-04-13 08:36:29,582 INFO L460 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-04-13 08:36:29,582 INFO L276 IsEmpty]: Start isEmpty. Operand 2600 states and 2606 transitions. [2018-04-13 08:36:29,605 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2579 [2018-04-13 08:36:29,605 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:36:29,606 INFO L355 BasicCegarLoop]: trace histogram [403, 378, 377, 377, 377, 377, 26, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:36:29,606 INFO L408 AbstractCegarLoop]: === Iteration 69 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:36:29,606 INFO L82 PathProgramCache]: Analyzing trace with hash 769184953, now seen corresponding path program 60 times [2018-04-13 08:36:29,606 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:36:29,606 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:36:29,607 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:36:29,607 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:36:29,607 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:36:29,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:36:29,732 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:36:32,192 INFO L134 CoverageAnalysis]: Checked inductivity of 449012 backedges. 61282 proven. 1980 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-04-13 08:36:32,192 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:36:32,192 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:36:32,193 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:36:47,749 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 55 check-sat command(s) [2018-04-13 08:36:47,750 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:36:48,476 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:36:50,822 INFO L134 CoverageAnalysis]: Checked inductivity of 449012 backedges. 59150 proven. 2187 refuted. 0 times theorem prover too weak. 387675 trivial. 0 not checked. [2018-04-13 08:36:50,823 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:36:50,823 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 30] total 87 [2018-04-13 08:36:50,823 INFO L442 AbstractCegarLoop]: Interpolant automaton has 87 states [2018-04-13 08:36:50,824 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2018-04-13 08:36:50,824 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1226, Invalid=6256, Unknown=0, NotChecked=0, Total=7482 [2018-04-13 08:36:50,824 INFO L87 Difference]: Start difference. First operand 2600 states and 2606 transitions. Second operand 87 states. [2018-04-13 08:36:54,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:36:54,100 INFO L93 Difference]: Finished difference Result 2982 states and 2994 transitions. [2018-04-13 08:36:54,100 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 114 states. [2018-04-13 08:36:54,100 INFO L78 Accepts]: Start accepts. Automaton has 87 states. Word has length 2578 [2018-04-13 08:36:54,101 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:36:54,103 INFO L225 Difference]: With dead ends: 2982 [2018-04-13 08:36:54,104 INFO L226 Difference]: Without dead ends: 2982 [2018-04-13 08:36:54,105 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2718 GetRequests, 2550 SyntacticMatches, 0 SemanticMatches, 168 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7095 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=5670, Invalid=23060, Unknown=0, NotChecked=0, Total=28730 [2018-04-13 08:36:54,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2982 states. [2018-04-13 08:36:54,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2982 to 2960. [2018-04-13 08:36:54,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2960 states. [2018-04-13 08:36:54,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2960 states to 2960 states and 2972 transitions. [2018-04-13 08:36:54,118 INFO L78 Accepts]: Start accepts. Automaton has 2960 states and 2972 transitions. Word has length 2578 [2018-04-13 08:36:54,119 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:36:54,119 INFO L459 AbstractCegarLoop]: Abstraction has 2960 states and 2972 transitions. [2018-04-13 08:36:54,119 INFO L460 AbstractCegarLoop]: Interpolant automaton has 87 states. [2018-04-13 08:36:54,119 INFO L276 IsEmpty]: Start isEmpty. Operand 2960 states and 2972 transitions. [2018-04-13 08:36:54,146 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2747 [2018-04-13 08:36:54,146 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:36:54,146 INFO L355 BasicCegarLoop]: trace histogram [430, 404, 403, 403, 403, 403, 27, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:36:54,146 INFO L408 AbstractCegarLoop]: === Iteration 70 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:36:54,147 INFO L82 PathProgramCache]: Analyzing trace with hash -1990215351, now seen corresponding path program 61 times [2018-04-13 08:36:54,147 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:36:54,147 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:36:54,147 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:36:54,147 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:36:54,147 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:36:54,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:36:54,285 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:36:57,146 INFO L134 CoverageAnalysis]: Checked inductivity of 512265 backedges. 118275 proven. 5857 refuted. 0 times theorem prover too weak. 388133 trivial. 0 not checked. [2018-04-13 08:36:57,146 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:36:57,146 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:36:57,147 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:36:57,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:36:57,335 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:36:59,724 INFO L134 CoverageAnalysis]: Checked inductivity of 512265 backedges. 170362 proven. 1850 refuted. 0 times theorem prover too weak. 340053 trivial. 0 not checked. [2018-04-13 08:36:59,724 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:36:59,724 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54] total 80 [2018-04-13 08:36:59,725 INFO L442 AbstractCegarLoop]: Interpolant automaton has 80 states [2018-04-13 08:36:59,725 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2018-04-13 08:36:59,725 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1483, Invalid=4837, Unknown=0, NotChecked=0, Total=6320 [2018-04-13 08:36:59,725 INFO L87 Difference]: Start difference. First operand 2960 states and 2972 transitions. Second operand 80 states. [2018-04-13 08:37:01,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:37:01,135 INFO L93 Difference]: Finished difference Result 2789 states and 2795 transitions. [2018-04-13 08:37:01,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-04-13 08:37:01,136 INFO L78 Accepts]: Start accepts. Automaton has 80 states. Word has length 2746 [2018-04-13 08:37:01,136 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:37:01,139 INFO L225 Difference]: With dead ends: 2789 [2018-04-13 08:37:01,139 INFO L226 Difference]: Without dead ends: 2780 [2018-04-13 08:37:01,139 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2823 GetRequests, 2721 SyntacticMatches, 0 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3745 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=2431, Invalid=8281, Unknown=0, NotChecked=0, Total=10712 [2018-04-13 08:37:01,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2780 states. [2018-04-13 08:37:01,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2780 to 2774. [2018-04-13 08:37:01,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2774 states. [2018-04-13 08:37:01,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2774 states to 2774 states and 2780 transitions. [2018-04-13 08:37:01,157 INFO L78 Accepts]: Start accepts. Automaton has 2774 states and 2780 transitions. Word has length 2746 [2018-04-13 08:37:01,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:37:01,158 INFO L459 AbstractCegarLoop]: Abstraction has 2774 states and 2780 transitions. [2018-04-13 08:37:01,158 INFO L460 AbstractCegarLoop]: Interpolant automaton has 80 states. [2018-04-13 08:37:01,158 INFO L276 IsEmpty]: Start isEmpty. Operand 2774 states and 2780 transitions. [2018-04-13 08:37:01,191 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2753 [2018-04-13 08:37:01,191 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:37:01,191 INFO L355 BasicCegarLoop]: trace histogram [431, 405, 404, 404, 404, 404, 27, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:37:01,191 INFO L408 AbstractCegarLoop]: === Iteration 71 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:37:01,191 INFO L82 PathProgramCache]: Analyzing trace with hash -1606031039, now seen corresponding path program 62 times [2018-04-13 08:37:01,191 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:37:01,191 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:37:01,192 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:37:01,192 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:37:01,192 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:37:01,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:37:01,330 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:37:04,143 INFO L134 CoverageAnalysis]: Checked inductivity of 514738 backedges. 124609 proven. 2002 refuted. 0 times theorem prover too weak. 388127 trivial. 0 not checked. [2018-04-13 08:37:04,143 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:37:04,143 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:37:04,143 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:37:04,312 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:37:04,312 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:37:04,342 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:37:07,663 INFO L134 CoverageAnalysis]: Checked inductivity of 514738 backedges. 68182 proven. 2054 refuted. 0 times theorem prover too weak. 444502 trivial. 0 not checked. [2018-04-13 08:37:07,664 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:37:07,664 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 59] total 113 [2018-04-13 08:37:07,665 INFO L442 AbstractCegarLoop]: Interpolant automaton has 113 states [2018-04-13 08:37:07,665 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 113 interpolants. [2018-04-13 08:37:07,665 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1657, Invalid=10999, Unknown=0, NotChecked=0, Total=12656 [2018-04-13 08:37:07,665 INFO L87 Difference]: Start difference. First operand 2774 states and 2780 transitions. Second operand 113 states. [2018-04-13 08:37:10,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:37:10,517 INFO L93 Difference]: Finished difference Result 2974 states and 2979 transitions. [2018-04-13 08:37:10,517 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 116 states. [2018-04-13 08:37:10,517 INFO L78 Accepts]: Start accepts. Automaton has 113 states. Word has length 2752 [2018-04-13 08:37:10,518 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:37:10,520 INFO L225 Difference]: With dead ends: 2974 [2018-04-13 08:37:10,520 INFO L226 Difference]: Without dead ends: 2965 [2018-04-13 08:37:10,522 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2918 GetRequests, 2723 SyntacticMatches, 0 SemanticMatches, 195 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11192 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=4291, Invalid=34321, Unknown=0, NotChecked=0, Total=38612 [2018-04-13 08:37:10,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2965 states. [2018-04-13 08:37:10,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2965 to 2954. [2018-04-13 08:37:10,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2954 states. [2018-04-13 08:37:10,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2954 states to 2954 states and 2959 transitions. [2018-04-13 08:37:10,533 INFO L78 Accepts]: Start accepts. Automaton has 2954 states and 2959 transitions. Word has length 2752 [2018-04-13 08:37:10,533 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:37:10,533 INFO L459 AbstractCegarLoop]: Abstraction has 2954 states and 2959 transitions. [2018-04-13 08:37:10,533 INFO L460 AbstractCegarLoop]: Interpolant automaton has 113 states. [2018-04-13 08:37:10,533 INFO L276 IsEmpty]: Start isEmpty. Operand 2954 states and 2959 transitions. [2018-04-13 08:37:10,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2933 [2018-04-13 08:37:10,563 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:37:10,563 INFO L355 BasicCegarLoop]: trace histogram [460, 433, 432, 432, 432, 432, 28, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:37:10,563 INFO L408 AbstractCegarLoop]: === Iteration 72 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:37:10,563 INFO L82 PathProgramCache]: Analyzing trace with hash 684728257, now seen corresponding path program 63 times [2018-04-13 08:37:10,563 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:37:10,563 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:37:10,564 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:37:10,564 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:37:10,564 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:37:10,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:37:10,693 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:37:14,204 INFO L134 CoverageAnalysis]: Checked inductivity of 587601 backedges. 136253 proven. 2160 refuted. 0 times theorem prover too weak. 449188 trivial. 0 not checked. [2018-04-13 08:37:14,205 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:37:14,205 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:37:14,205 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:37:14,588 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 29 check-sat command(s) [2018-04-13 08:37:14,588 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:37:14,665 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:37:17,057 INFO L134 CoverageAnalysis]: Checked inductivity of 587601 backedges. 70650 proven. 2352 refuted. 0 times theorem prover too weak. 514599 trivial. 0 not checked. [2018-04-13 08:37:17,057 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:37:17,058 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 31] total 88 [2018-04-13 08:37:17,058 INFO L442 AbstractCegarLoop]: Interpolant automaton has 88 states [2018-04-13 08:37:17,058 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2018-04-13 08:37:17,059 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1310, Invalid=6346, Unknown=0, NotChecked=0, Total=7656 [2018-04-13 08:37:17,059 INFO L87 Difference]: Start difference. First operand 2954 states and 2959 transitions. Second operand 88 states. [2018-04-13 08:37:19,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:37:19,127 INFO L93 Difference]: Finished difference Result 2978 states and 2982 transitions. [2018-04-13 08:37:19,127 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-04-13 08:37:19,127 INFO L78 Accepts]: Start accepts. Automaton has 88 states. Word has length 2932 [2018-04-13 08:37:19,128 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:37:19,130 INFO L225 Difference]: With dead ends: 2978 [2018-04-13 08:37:19,130 INFO L226 Difference]: Without dead ends: 2972 [2018-04-13 08:37:19,131 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3042 GetRequests, 2903 SyntacticMatches, 0 SemanticMatches, 139 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5454 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=4033, Invalid=15707, Unknown=0, NotChecked=0, Total=19740 [2018-04-13 08:37:19,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2972 states. [2018-04-13 08:37:19,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2972 to 2960. [2018-04-13 08:37:19,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2960 states. [2018-04-13 08:37:19,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2960 states to 2960 states and 2964 transitions. [2018-04-13 08:37:19,143 INFO L78 Accepts]: Start accepts. Automaton has 2960 states and 2964 transitions. Word has length 2932 [2018-04-13 08:37:19,144 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:37:19,144 INFO L459 AbstractCegarLoop]: Abstraction has 2960 states and 2964 transitions. [2018-04-13 08:37:19,144 INFO L460 AbstractCegarLoop]: Interpolant automaton has 88 states. [2018-04-13 08:37:19,144 INFO L276 IsEmpty]: Start isEmpty. Operand 2960 states and 2964 transitions. [2018-04-13 08:37:19,173 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2945 [2018-04-13 08:37:19,173 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:37:19,174 INFO L355 BasicCegarLoop]: trace histogram [462, 435, 434, 434, 434, 434, 28, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:37:19,174 INFO L408 AbstractCegarLoop]: === Iteration 73 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:37:19,174 INFO L82 PathProgramCache]: Analyzing trace with hash 1350317489, now seen corresponding path program 64 times [2018-04-13 08:37:19,174 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:37:19,174 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:37:19,175 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:37:19,175 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:37:19,175 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:37:19,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:37:19,324 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:37:22,379 INFO L134 CoverageAnalysis]: Checked inductivity of 592905 backedges. 75769 proven. 2300 refuted. 0 times theorem prover too weak. 514836 trivial. 0 not checked. [2018-04-13 08:37:22,379 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:37:22,379 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:37:22,380 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:37:22,564 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:37:22,565 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:37:22,602 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:37:26,878 INFO L134 CoverageAnalysis]: Checked inductivity of 592905 backedges. 136703 proven. 7312 refuted. 0 times theorem prover too weak. 448890 trivial. 0 not checked. [2018-04-13 08:37:26,878 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:37:26,879 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 65] total 122 [2018-04-13 08:37:26,879 INFO L442 AbstractCegarLoop]: Interpolant automaton has 122 states [2018-04-13 08:37:26,880 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 122 interpolants. [2018-04-13 08:37:26,880 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2391, Invalid=12371, Unknown=0, NotChecked=0, Total=14762 [2018-04-13 08:37:26,880 INFO L87 Difference]: Start difference. First operand 2960 states and 2964 transitions. Second operand 122 states. [2018-04-13 08:37:30,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:37:30,275 INFO L93 Difference]: Finished difference Result 3163 states and 3168 transitions. [2018-04-13 08:37:30,275 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 148 states. [2018-04-13 08:37:30,276 INFO L78 Accepts]: Start accepts. Automaton has 122 states. Word has length 2944 [2018-04-13 08:37:30,277 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:37:30,281 INFO L225 Difference]: With dead ends: 3163 [2018-04-13 08:37:30,281 INFO L226 Difference]: Without dead ends: 3163 [2018-04-13 08:37:30,283 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3091 GetRequests, 2885 SyntacticMatches, 0 SemanticMatches, 206 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10318 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=7189, Invalid=35867, Unknown=0, NotChecked=0, Total=43056 [2018-04-13 08:37:30,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3163 states. [2018-04-13 08:37:30,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3163 to 3152. [2018-04-13 08:37:30,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3152 states. [2018-04-13 08:37:30,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3152 states to 3152 states and 3157 transitions. [2018-04-13 08:37:30,329 INFO L78 Accepts]: Start accepts. Automaton has 3152 states and 3157 transitions. Word has length 2944 [2018-04-13 08:37:30,331 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:37:30,331 INFO L459 AbstractCegarLoop]: Abstraction has 3152 states and 3157 transitions. [2018-04-13 08:37:30,331 INFO L460 AbstractCegarLoop]: Interpolant automaton has 122 states. [2018-04-13 08:37:30,331 INFO L276 IsEmpty]: Start isEmpty. Operand 3152 states and 3157 transitions. [2018-04-13 08:37:30,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3131 [2018-04-13 08:37:30,366 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:37:30,367 INFO L355 BasicCegarLoop]: trace histogram [492, 464, 463, 463, 463, 463, 29, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:37:30,367 INFO L408 AbstractCegarLoop]: === Iteration 74 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:37:30,367 INFO L82 PathProgramCache]: Analyzing trace with hash -1959658967, now seen corresponding path program 65 times [2018-04-13 08:37:30,367 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:37:30,367 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:37:30,368 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:37:30,368 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:37:30,368 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:37:30,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:37:30,538 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:37:33,204 INFO L134 CoverageAnalysis]: Checked inductivity of 673767 backedges. 78498 proven. 2523 refuted. 0 times theorem prover too weak. 592746 trivial. 0 not checked. [2018-04-13 08:37:33,204 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:37:33,204 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:37:33,205 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:38:09,124 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 64 check-sat command(s) [2018-04-13 08:38:09,124 INFO L243 tOrderPrioritization]: Conjunction of SSA is unknown [2018-04-13 08:38:11,883 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-13 08:38:11,883 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2018-04-13 08:38:11,883 INFO L442 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-04-13 08:38:11,883 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-04-13 08:38:11,883 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=471, Invalid=585, Unknown=0, NotChecked=0, Total=1056 [2018-04-13 08:38:11,883 INFO L87 Difference]: Start difference. First operand 3152 states and 3157 transitions. Second operand 33 states. [2018-04-13 08:38:12,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:38:12,413 INFO L93 Difference]: Finished difference Result 3170 states and 3176 transitions. [2018-04-13 08:38:12,413 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-04-13 08:38:12,413 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 3130 [2018-04-13 08:38:12,414 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:38:12,417 INFO L225 Difference]: With dead ends: 3170 [2018-04-13 08:38:12,417 INFO L226 Difference]: Without dead ends: 3170 [2018-04-13 08:38:12,417 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 435 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=1367, Invalid=2293, Unknown=0, NotChecked=0, Total=3660 [2018-04-13 08:38:12,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3170 states. [2018-04-13 08:38:12,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3170 to 3158. [2018-04-13 08:38:12,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3158 states. [2018-04-13 08:38:12,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3158 states to 3158 states and 3164 transitions. [2018-04-13 08:38:12,430 INFO L78 Accepts]: Start accepts. Automaton has 3158 states and 3164 transitions. Word has length 3130 [2018-04-13 08:38:12,431 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:38:12,431 INFO L459 AbstractCegarLoop]: Abstraction has 3158 states and 3164 transitions. [2018-04-13 08:38:12,431 INFO L460 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-04-13 08:38:12,431 INFO L276 IsEmpty]: Start isEmpty. Operand 3158 states and 3164 transitions. [2018-04-13 08:38:12,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3137 [2018-04-13 08:38:12,464 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:38:12,465 INFO L355 BasicCegarLoop]: trace histogram [493, 465, 464, 464, 464, 464, 29, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:38:12,465 INFO L408 AbstractCegarLoop]: === Iteration 75 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:38:12,465 INFO L82 PathProgramCache]: Analyzing trace with hash -1641522655, now seen corresponding path program 66 times [2018-04-13 08:38:12,465 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:38:12,465 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:38:12,465 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:38:12,465 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:38:12,465 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:38:12,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:38:12,639 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:38:16,798 INFO L134 CoverageAnalysis]: Checked inductivity of 676604 backedges. 83797 proven. 2469 refuted. 0 times theorem prover too weak. 590338 trivial. 0 not checked. [2018-04-13 08:38:16,798 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:38:16,799 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:38:16,799 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:38:32,967 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 59 check-sat command(s) [2018-04-13 08:38:32,967 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:38:35,576 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:38:38,601 INFO L134 CoverageAnalysis]: Checked inductivity of 676604 backedges. 85327 proven. 30537 refuted. 0 times theorem prover too weak. 560740 trivial. 0 not checked. [2018-04-13 08:38:38,602 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:38:38,602 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 39] total 81 [2018-04-13 08:38:38,603 INFO L442 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-04-13 08:38:38,603 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-04-13 08:38:38,603 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1115, Invalid=5365, Unknown=0, NotChecked=0, Total=6480 [2018-04-13 08:38:38,603 INFO L87 Difference]: Start difference. First operand 3158 states and 3164 transitions. Second operand 81 states. [2018-04-13 08:38:40,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:38:40,977 INFO L93 Difference]: Finished difference Result 3555 states and 3566 transitions. [2018-04-13 08:38:40,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 118 states. [2018-04-13 08:38:40,977 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 3136 [2018-04-13 08:38:40,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:38:40,981 INFO L225 Difference]: With dead ends: 3555 [2018-04-13 08:38:40,981 INFO L226 Difference]: Without dead ends: 3555 [2018-04-13 08:38:40,982 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3270 GetRequests, 3120 SyntacticMatches, 0 SemanticMatches, 150 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4968 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=4717, Invalid=18235, Unknown=0, NotChecked=0, Total=22952 [2018-04-13 08:38:40,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3555 states. [2018-04-13 08:38:40,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3555 to 3548. [2018-04-13 08:38:41,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3548 states. [2018-04-13 08:38:41,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3548 states to 3548 states and 3559 transitions. [2018-04-13 08:38:41,004 INFO L78 Accepts]: Start accepts. Automaton has 3548 states and 3559 transitions. Word has length 3136 [2018-04-13 08:38:41,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:38:41,005 INFO L459 AbstractCegarLoop]: Abstraction has 3548 states and 3559 transitions. [2018-04-13 08:38:41,006 INFO L460 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-04-13 08:38:41,006 INFO L276 IsEmpty]: Start isEmpty. Operand 3548 states and 3559 transitions. [2018-04-13 08:38:41,044 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3317 [2018-04-13 08:38:41,044 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:38:41,044 INFO L355 BasicCegarLoop]: trace histogram [522, 493, 492, 492, 492, 492, 30, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:38:41,044 INFO L408 AbstractCegarLoop]: === Iteration 76 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:38:41,045 INFO L82 PathProgramCache]: Analyzing trace with hash 955945121, now seen corresponding path program 67 times [2018-04-13 08:38:41,045 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:38:41,045 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:38:41,045 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:38:41,045 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:38:41,045 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:38:41,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:38:41,212 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:38:44,949 INFO L134 CoverageAnalysis]: Checked inductivity of 759803 backedges. 159416 proven. 7315 refuted. 0 times theorem prover too weak. 593072 trivial. 0 not checked. [2018-04-13 08:38:44,949 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:38:44,949 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:38:44,949 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:38:45,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:38:45,185 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:38:48,457 INFO L134 CoverageAnalysis]: Checked inductivity of 759803 backedges. 166897 proven. 2494 refuted. 0 times theorem prover too weak. 590412 trivial. 0 not checked. [2018-04-13 08:38:48,458 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:38:48,458 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 62] total 92 [2018-04-13 08:38:48,459 INFO L442 AbstractCegarLoop]: Interpolant automaton has 92 states [2018-04-13 08:38:48,459 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2018-04-13 08:38:48,459 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1893, Invalid=6479, Unknown=0, NotChecked=0, Total=8372 [2018-04-13 08:38:48,459 INFO L87 Difference]: Start difference. First operand 3548 states and 3559 transitions. Second operand 92 states. [2018-04-13 08:38:49,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:38:49,424 INFO L93 Difference]: Finished difference Result 3368 states and 3371 transitions. [2018-04-13 08:38:49,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-04-13 08:38:49,424 INFO L78 Accepts]: Start accepts. Automaton has 92 states. Word has length 3316 [2018-04-13 08:38:49,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:38:49,429 INFO L225 Difference]: With dead ends: 3368 [2018-04-13 08:38:49,429 INFO L226 Difference]: Without dead ends: 3353 [2018-04-13 08:38:49,430 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3403 GetRequests, 3285 SyntacticMatches, 0 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5066 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=3166, Invalid=11114, Unknown=0, NotChecked=0, Total=14280 [2018-04-13 08:38:49,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3353 states. [2018-04-13 08:38:49,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3353 to 3344. [2018-04-13 08:38:49,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3344 states. [2018-04-13 08:38:49,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3344 states to 3344 states and 3347 transitions. [2018-04-13 08:38:49,451 INFO L78 Accepts]: Start accepts. Automaton has 3344 states and 3347 transitions. Word has length 3316 [2018-04-13 08:38:49,453 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:38:49,453 INFO L459 AbstractCegarLoop]: Abstraction has 3344 states and 3347 transitions. [2018-04-13 08:38:49,453 INFO L460 AbstractCegarLoop]: Interpolant automaton has 92 states. [2018-04-13 08:38:49,453 INFO L276 IsEmpty]: Start isEmpty. Operand 3344 states and 3347 transitions. [2018-04-13 08:38:49,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3329 [2018-04-13 08:38:49,514 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:38:49,515 INFO L355 BasicCegarLoop]: trace histogram [524, 495, 494, 494, 494, 494, 30, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:38:49,515 INFO L408 AbstractCegarLoop]: === Iteration 77 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:38:49,515 INFO L82 PathProgramCache]: Analyzing trace with hash 1908539025, now seen corresponding path program 68 times [2018-04-13 08:38:49,515 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:38:49,515 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:38:49,516 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:38:49,516 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:38:49,516 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:38:49,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:38:49,805 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:38:52,731 INFO L134 CoverageAnalysis]: Checked inductivity of 765835 backedges. 86710 proven. 2700 refuted. 0 times theorem prover too weak. 676425 trivial. 0 not checked. [2018-04-13 08:38:52,731 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:38:52,731 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:38:52,732 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-13 08:38:52,966 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-13 08:38:52,967 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:38:53,004 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:38:55,462 INFO L134 CoverageAnalysis]: Checked inductivity of 765835 backedges. 86710 proven. 2700 refuted. 0 times theorem prover too weak. 676425 trivial. 0 not checked. [2018-04-13 08:38:55,462 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:38:55,463 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 34 [2018-04-13 08:38:55,463 INFO L442 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-04-13 08:38:55,463 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-04-13 08:38:55,463 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=504, Invalid=686, Unknown=0, NotChecked=0, Total=1190 [2018-04-13 08:38:55,464 INFO L87 Difference]: Start difference. First operand 3344 states and 3347 transitions. Second operand 35 states. [2018-04-13 08:38:55,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:38:55,970 INFO L93 Difference]: Finished difference Result 3362 states and 3366 transitions. [2018-04-13 08:38:55,970 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-04-13 08:38:55,970 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 3328 [2018-04-13 08:38:55,971 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:38:55,974 INFO L225 Difference]: With dead ends: 3362 [2018-04-13 08:38:55,975 INFO L226 Difference]: Without dead ends: 3362 [2018-04-13 08:38:55,975 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3389 GetRequests, 3327 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 576 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1431, Invalid=2601, Unknown=0, NotChecked=0, Total=4032 [2018-04-13 08:38:55,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3362 states. [2018-04-13 08:38:55,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3362 to 3350. [2018-04-13 08:38:55,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3350 states. [2018-04-13 08:38:55,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3350 states to 3350 states and 3354 transitions. [2018-04-13 08:38:55,990 INFO L78 Accepts]: Start accepts. Automaton has 3350 states and 3354 transitions. Word has length 3328 [2018-04-13 08:38:55,991 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:38:55,991 INFO L459 AbstractCegarLoop]: Abstraction has 3350 states and 3354 transitions. [2018-04-13 08:38:55,991 INFO L460 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-04-13 08:38:55,991 INFO L276 IsEmpty]: Start isEmpty. Operand 3350 states and 3354 transitions. [2018-04-13 08:38:56,029 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3335 [2018-04-13 08:38:56,029 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:38:56,029 INFO L355 BasicCegarLoop]: trace histogram [525, 496, 495, 495, 495, 495, 30, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:38:56,029 INFO L408 AbstractCegarLoop]: === Iteration 78 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:38:56,030 INFO L82 PathProgramCache]: Analyzing trace with hash 1865248905, now seen corresponding path program 69 times [2018-04-13 08:38:56,030 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:38:56,030 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:38:56,030 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:38:56,030 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:38:56,030 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:38:56,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:38:56,226 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:39:00,092 INFO L134 CoverageAnalysis]: Checked inductivity of 768860 backedges. 92372 proven. 2644 refuted. 0 times theorem prover too weak. 673844 trivial. 0 not checked. [2018-04-13 08:39:00,092 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:39:00,092 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:39:00,093 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-13 08:39:00,816 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 32 check-sat command(s) [2018-04-13 08:39:00,817 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:39:01,025 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:39:05,885 INFO L134 CoverageAnalysis]: Checked inductivity of 768860 backedges. 164981 proven. 9523 refuted. 0 times theorem prover too weak. 594356 trivial. 0 not checked. [2018-04-13 08:39:05,885 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:39:05,885 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 48] total 113 [2018-04-13 08:39:05,886 INFO L442 AbstractCegarLoop]: Interpolant automaton has 113 states [2018-04-13 08:39:05,886 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 113 interpolants. [2018-04-13 08:39:05,887 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1718, Invalid=10938, Unknown=0, NotChecked=0, Total=12656 [2018-04-13 08:39:05,887 INFO L87 Difference]: Start difference. First operand 3350 states and 3354 transitions. Second operand 113 states. [2018-04-13 08:39:11,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:39:11,191 INFO L93 Difference]: Finished difference Result 3565 states and 3570 transitions. [2018-04-13 08:39:11,191 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 159 states. [2018-04-13 08:39:11,191 INFO L78 Accepts]: Start accepts. Automaton has 113 states. Word has length 3334 [2018-04-13 08:39:11,193 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:39:11,195 INFO L225 Difference]: With dead ends: 3565 [2018-04-13 08:39:11,195 INFO L226 Difference]: Without dead ends: 3565 [2018-04-13 08:39:11,196 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3520 GetRequests, 3288 SyntacticMatches, 0 SemanticMatches, 232 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13924 ImplicationChecksByTransitivity, 5.8s TimeCoverageRelationStatistics Valid=8474, Invalid=46048, Unknown=0, NotChecked=0, Total=54522 [2018-04-13 08:39:11,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3565 states. [2018-04-13 08:39:11,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3565 to 3554. [2018-04-13 08:39:11,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3554 states. [2018-04-13 08:39:11,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3554 states to 3554 states and 3559 transitions. [2018-04-13 08:39:11,209 INFO L78 Accepts]: Start accepts. Automaton has 3554 states and 3559 transitions. Word has length 3334 [2018-04-13 08:39:11,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:39:11,210 INFO L459 AbstractCegarLoop]: Abstraction has 3554 states and 3559 transitions. [2018-04-13 08:39:11,210 INFO L460 AbstractCegarLoop]: Interpolant automaton has 113 states. [2018-04-13 08:39:11,210 INFO L276 IsEmpty]: Start isEmpty. Operand 3554 states and 3559 transitions. [2018-04-13 08:39:11,252 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3533 [2018-04-13 08:39:11,253 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:39:11,253 INFO L355 BasicCegarLoop]: trace histogram [557, 527, 526, 526, 526, 526, 31, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:39:11,253 INFO L408 AbstractCegarLoop]: === Iteration 79 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:39:11,253 INFO L82 PathProgramCache]: Analyzing trace with hash 1387026673, now seen corresponding path program 70 times [2018-04-13 08:39:11,253 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:39:11,253 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:39:11,254 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:39:11,254 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:39:11,254 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:39:11,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:39:11,462 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:39:14,809 INFO L134 CoverageAnalysis]: Checked inductivity of 867018 backedges. 95475 proven. 2883 refuted. 0 times theorem prover too weak. 768660 trivial. 0 not checked. [2018-04-13 08:39:14,809 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:39:14,809 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:39:14,810 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-13 08:39:15,555 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-13 08:39:15,555 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:39:15,628 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:39:18,623 INFO L134 CoverageAnalysis]: Checked inductivity of 867018 backedges. 95475 proven. 2883 refuted. 0 times theorem prover too weak. 768660 trivial. 0 not checked. [2018-04-13 08:39:18,623 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:39:18,624 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 33] total 65 [2018-04-13 08:39:18,624 INFO L442 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-04-13 08:39:18,624 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-04-13 08:39:18,625 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1122, Invalid=3168, Unknown=0, NotChecked=0, Total=4290 [2018-04-13 08:39:18,625 INFO L87 Difference]: Start difference. First operand 3554 states and 3559 transitions. Second operand 66 states. [2018-04-13 08:39:20,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:39:20,044 INFO L93 Difference]: Finished difference Result 3572 states and 3578 transitions. [2018-04-13 08:39:20,045 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-04-13 08:39:20,045 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 3532 [2018-04-13 08:39:20,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:39:20,048 INFO L225 Difference]: With dead ends: 3572 [2018-04-13 08:39:20,048 INFO L226 Difference]: Without dead ends: 3572 [2018-04-13 08:39:20,049 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3565 GetRequests, 3501 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1923 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=1122, Invalid=3168, Unknown=0, NotChecked=0, Total=4290 [2018-04-13 08:39:20,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3572 states. [2018-04-13 08:39:20,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3572 to 3560. [2018-04-13 08:39:20,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3560 states. [2018-04-13 08:39:20,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3560 states to 3560 states and 3566 transitions. [2018-04-13 08:39:20,063 INFO L78 Accepts]: Start accepts. Automaton has 3560 states and 3566 transitions. Word has length 3532 [2018-04-13 08:39:20,064 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:39:20,064 INFO L459 AbstractCegarLoop]: Abstraction has 3560 states and 3566 transitions. [2018-04-13 08:39:20,064 INFO L460 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-04-13 08:39:20,064 INFO L276 IsEmpty]: Start isEmpty. Operand 3560 states and 3566 transitions. [2018-04-13 08:39:20,106 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3539 [2018-04-13 08:39:20,106 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:39:20,106 INFO L355 BasicCegarLoop]: trace histogram [558, 528, 527, 527, 527, 527, 31, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:39:20,106 INFO L408 AbstractCegarLoop]: === Iteration 80 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:39:20,107 INFO L82 PathProgramCache]: Analyzing trace with hash 1069712105, now seen corresponding path program 71 times [2018-04-13 08:39:20,107 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:39:20,107 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:39:20,107 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:39:20,107 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:39:20,107 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:39:20,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:39:20,315 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:39:24,611 INFO L134 CoverageAnalysis]: Checked inductivity of 870237 backedges. 101512 proven. 2825 refuted. 0 times theorem prover too weak. 765900 trivial. 0 not checked. [2018-04-13 08:39:24,612 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:39:24,612 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:39:24,612 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-13 08:40:21,067 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 83 check-sat command(s) [2018-04-13 08:40:21,067 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:40:24,986 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:40:29,688 INFO L134 CoverageAnalysis]: Checked inductivity of 870237 backedges. 101369 proven. 16141 refuted. 0 times theorem prover too weak. 752727 trivial. 0 not checked. [2018-04-13 08:40:29,688 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:40:29,689 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 72] total 107 [2018-04-13 08:40:29,689 INFO L442 AbstractCegarLoop]: Interpolant automaton has 107 states [2018-04-13 08:40:29,690 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 107 interpolants. [2018-04-13 08:40:29,690 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2337, Invalid=9005, Unknown=0, NotChecked=0, Total=11342 [2018-04-13 08:40:29,690 INFO L87 Difference]: Start difference. First operand 3560 states and 3566 transitions. Second operand 107 states. [2018-04-13 08:40:32,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:40:32,295 INFO L93 Difference]: Finished difference Result 3987 states and 3998 transitions. [2018-04-13 08:40:32,295 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 108 states. [2018-04-13 08:40:32,295 INFO L78 Accepts]: Start accepts. Automaton has 107 states. Word has length 3538 [2018-04-13 08:40:32,296 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:40:32,299 INFO L225 Difference]: With dead ends: 3987 [2018-04-13 08:40:32,299 INFO L226 Difference]: Without dead ends: 3987 [2018-04-13 08:40:32,300 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3672 GetRequests, 3500 SyntacticMatches, 0 SemanticMatches, 172 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5737 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=6559, Invalid=23543, Unknown=0, NotChecked=0, Total=30102 [2018-04-13 08:40:32,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3987 states. [2018-04-13 08:40:32,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3987 to 3974. [2018-04-13 08:40:32,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3974 states. [2018-04-13 08:40:32,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3974 states to 3974 states and 3985 transitions. [2018-04-13 08:40:32,318 INFO L78 Accepts]: Start accepts. Automaton has 3974 states and 3985 transitions. Word has length 3538 [2018-04-13 08:40:32,319 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:40:32,319 INFO L459 AbstractCegarLoop]: Abstraction has 3974 states and 3985 transitions. [2018-04-13 08:40:32,319 INFO L460 AbstractCegarLoop]: Interpolant automaton has 107 states. [2018-04-13 08:40:32,319 INFO L276 IsEmpty]: Start isEmpty. Operand 3974 states and 3985 transitions. [2018-04-13 08:40:32,367 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3731 [2018-04-13 08:40:32,367 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:40:32,367 INFO L355 BasicCegarLoop]: trace histogram [589, 558, 557, 557, 557, 557, 32, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:40:32,367 INFO L408 AbstractCegarLoop]: === Iteration 81 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:40:32,367 INFO L82 PathProgramCache]: Analyzing trace with hash 1063316313, now seen corresponding path program 72 times [2018-04-13 08:40:32,368 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:40:32,368 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:40:32,368 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:40:32,368 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:40:32,368 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:40:32,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:40:32,595 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:40:37,118 INFO L134 CoverageAnalysis]: Checked inductivity of 971078 backedges. 193693 proven. 8377 refuted. 0 times theorem prover too weak. 769008 trivial. 0 not checked. [2018-04-13 08:40:37,118 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:40:37,118 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:40:37,118 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-13 08:40:40,584 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 65 check-sat command(s) [2018-04-13 08:40:40,584 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-13 08:40:40,821 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:40:44,988 INFO L134 CoverageAnalysis]: Checked inductivity of 971078 backedges. 185382 proven. 14331 refuted. 0 times theorem prover too weak. 771365 trivial. 0 not checked. [2018-04-13 08:40:44,988 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:40:44,989 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 41] total 103 [2018-04-13 08:40:44,989 INFO L442 AbstractCegarLoop]: Interpolant automaton has 103 states [2018-04-13 08:40:44,990 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2018-04-13 08:40:44,990 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2101, Invalid=8405, Unknown=0, NotChecked=0, Total=10506 [2018-04-13 08:40:44,990 INFO L87 Difference]: Start difference. First operand 3974 states and 3985 transitions. Second operand 103 states. [2018-04-13 08:40:48,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:40:48,795 INFO L93 Difference]: Finished difference Result 3784 states and 3789 transitions. [2018-04-13 08:40:48,795 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 161 states. [2018-04-13 08:40:48,795 INFO L78 Accepts]: Start accepts. Automaton has 103 states. Word has length 3730 [2018-04-13 08:40:48,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:40:48,799 INFO L225 Difference]: With dead ends: 3784 [2018-04-13 08:40:48,799 INFO L226 Difference]: Without dead ends: 3775 [2018-04-13 08:40:48,801 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3947 GetRequests, 3692 SyntacticMatches, 0 SemanticMatches, 255 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23102 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=10880, Invalid=54912, Unknown=0, NotChecked=0, Total=65792 [2018-04-13 08:40:48,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3775 states. [2018-04-13 08:40:48,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3775 to 3758. [2018-04-13 08:40:48,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3758 states. [2018-04-13 08:40:48,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3758 states to 3758 states and 3763 transitions. [2018-04-13 08:40:48,816 INFO L78 Accepts]: Start accepts. Automaton has 3758 states and 3763 transitions. Word has length 3730 [2018-04-13 08:40:48,816 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:40:48,817 INFO L459 AbstractCegarLoop]: Abstraction has 3758 states and 3763 transitions. [2018-04-13 08:40:48,817 INFO L460 AbstractCegarLoop]: Interpolant automaton has 103 states. [2018-04-13 08:40:48,817 INFO L276 IsEmpty]: Start isEmpty. Operand 3758 states and 3763 transitions. [2018-04-13 08:40:48,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3737 [2018-04-13 08:40:48,862 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:40:48,863 INFO L355 BasicCegarLoop]: trace histogram [590, 559, 558, 558, 558, 558, 32, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:40:48,863 INFO L408 AbstractCegarLoop]: === Iteration 82 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:40:48,863 INFO L82 PathProgramCache]: Analyzing trace with hash 832196433, now seen corresponding path program 73 times [2018-04-13 08:40:48,863 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:40:48,863 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:40:48,864 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:40:48,864 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-13 08:40:48,864 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:40:49,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:40:49,073 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-13 08:40:53,674 INFO L134 CoverageAnalysis]: Checked inductivity of 974485 backedges. 202631 proven. 2852 refuted. 0 times theorem prover too weak. 769002 trivial. 0 not checked. [2018-04-13 08:40:53,675 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-13 08:40:53,675 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-13 08:40:53,675 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:40:53,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-13 08:40:53,993 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-13 08:40:57,996 INFO L134 CoverageAnalysis]: Checked inductivity of 974485 backedges. 202631 proven. 2852 refuted. 0 times theorem prover too weak. 769002 trivial. 0 not checked. [2018-04-13 08:40:57,996 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-13 08:40:57,997 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 66] total 98 [2018-04-13 08:40:57,997 INFO L442 AbstractCegarLoop]: Interpolant automaton has 98 states [2018-04-13 08:40:57,998 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2018-04-13 08:40:57,998 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2209, Invalid=7297, Unknown=0, NotChecked=0, Total=9506 [2018-04-13 08:40:57,998 INFO L87 Difference]: Start difference. First operand 3758 states and 3763 transitions. Second operand 98 states. [2018-04-13 08:40:59,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-13 08:40:59,405 INFO L93 Difference]: Finished difference Result 3773 states and 3776 transitions. [2018-04-13 08:40:59,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2018-04-13 08:40:59,405 INFO L78 Accepts]: Start accepts. Automaton has 98 states. Word has length 3736 [2018-04-13 08:40:59,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-13 08:40:59,409 INFO L225 Difference]: With dead ends: 3773 [2018-04-13 08:40:59,409 INFO L226 Difference]: Without dead ends: 3767 [2018-04-13 08:40:59,410 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3831 GetRequests, 3705 SyntacticMatches, 0 SemanticMatches, 126 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5761 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=3664, Invalid=12592, Unknown=0, NotChecked=0, Total=16256 [2018-04-13 08:40:59,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3767 states. [2018-04-13 08:40:59,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3767 to 3758. [2018-04-13 08:40:59,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3758 states. [2018-04-13 08:40:59,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3758 states to 3758 states and 3761 transitions. [2018-04-13 08:40:59,425 INFO L78 Accepts]: Start accepts. Automaton has 3758 states and 3761 transitions. Word has length 3736 [2018-04-13 08:40:59,426 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-13 08:40:59,426 INFO L459 AbstractCegarLoop]: Abstraction has 3758 states and 3761 transitions. [2018-04-13 08:40:59,426 INFO L460 AbstractCegarLoop]: Interpolant automaton has 98 states. [2018-04-13 08:40:59,426 INFO L276 IsEmpty]: Start isEmpty. Operand 3758 states and 3761 transitions. [2018-04-13 08:40:59,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3743 [2018-04-13 08:40:59,474 INFO L347 BasicCegarLoop]: Found error trace [2018-04-13 08:40:59,474 INFO L355 BasicCegarLoop]: trace histogram [591, 560, 559, 559, 559, 559, 32, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-13 08:40:59,474 INFO L408 AbstractCegarLoop]: === Iteration 83 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-13 08:40:59,474 INFO L82 PathProgramCache]: Analyzing trace with hash 1353057609, now seen corresponding path program 74 times [2018-04-13 08:40:59,475 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-13 08:40:59,475 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-13 08:40:59,475 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:40:59,475 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-13 08:40:59,475 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-13 08:41:00,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-04-13 08:41:00,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-04-13 08:41:01,678 INFO L421 BasicCegarLoop]: Counterexample might be feasible [2018-04-13 08:41:02,197 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 13.04 08:41:02 BoogieIcfgContainer [2018-04-13 08:41:02,197 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-04-13 08:41:02,198 INFO L168 Benchmark]: Toolchain (without parser) took 463061.15 ms. Allocated memory was 402.7 MB in the beginning and 3.1 GB in the end (delta: 2.7 GB). Free memory was 345.6 MB in the beginning and 1.9 GB in the end (delta: -1.5 GB). Peak memory consumption was 2.5 GB. Max. memory is 5.3 GB. [2018-04-13 08:41:02,199 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 402.7 MB. Free memory is still 364.4 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-04-13 08:41:02,199 INFO L168 Benchmark]: CACSL2BoogieTranslator took 148.97 ms. Allocated memory is still 402.7 MB. Free memory was 345.6 MB in the beginning and 334.9 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. [2018-04-13 08:41:02,200 INFO L168 Benchmark]: Boogie Preprocessor took 25.24 ms. Allocated memory is still 402.7 MB. Free memory was 334.9 MB in the beginning and 333.6 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. [2018-04-13 08:41:02,200 INFO L168 Benchmark]: RCFGBuilder took 212.40 ms. Allocated memory was 402.7 MB in the beginning and 617.6 MB in the end (delta: 215.0 MB). Free memory was 333.6 MB in the beginning and 581.8 MB in the end (delta: -248.1 MB). Peak memory consumption was 24.9 MB. Max. memory is 5.3 GB. [2018-04-13 08:41:02,200 INFO L168 Benchmark]: TraceAbstraction took 462671.86 ms. Allocated memory was 617.6 MB in the beginning and 3.1 GB in the end (delta: 2.5 GB). Free memory was 580.1 MB in the beginning and 1.9 GB in the end (delta: -1.3 GB). Peak memory consumption was 2.5 GB. Max. memory is 5.3 GB. [2018-04-13 08:41:02,202 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 402.7 MB. Free memory is still 364.4 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 148.97 ms. Allocated memory is still 402.7 MB. Free memory was 345.6 MB in the beginning and 334.9 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 25.24 ms. Allocated memory is still 402.7 MB. Free memory was 334.9 MB in the beginning and 333.6 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. * RCFGBuilder took 212.40 ms. Allocated memory was 402.7 MB in the beginning and 617.6 MB in the end (delta: 215.0 MB). Free memory was 333.6 MB in the beginning and 581.8 MB in the end (delta: -248.1 MB). Peak memory consumption was 24.9 MB. Max. memory is 5.3 GB. * TraceAbstraction took 462671.86 ms. Allocated memory was 617.6 MB in the beginning and 3.1 GB in the end (delta: 2.5 GB). Free memory was 580.1 MB in the beginning and 1.9 GB in the end (delta: -1.3 GB). Peak memory consumption was 2.5 GB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: array index can be out of bounds array index can be out of bounds We found a FailurePath: [L24] int i, b[32]; [L25] FCALL char mask[32]; VAL [mask={43:0}] [L26] i = 0 VAL [i=0, mask={43:0}] [L26] COND TRUE i < sizeof(mask) VAL [i=0, mask={43:0}] [L27] EXPR b[i] VAL [i=0, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=1, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={43:0}, b={43:0}, i=0, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={43:0}, b={43:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={43:0}, b={43:0}, i=0, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={43:0}, b={43:0}, b[i]=53, i=0, size=1] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=1, b={43:0}, b={43:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={43:0}, b={43:0}, i=1, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={43:0}, b={43:0}, b[i]=50, i=1, size=1] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=1, b={43:0}, b={43:0}, i=2, size=1] [L20] RET return i; VAL [\old(size)=1, \result=2, b={43:0}, b={43:0}, i=2, size=1] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=2, i=0, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=1, mask={43:0}] [L27] EXPR b[i] VAL [i=1, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=2, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={43:0}, b={43:0}, i=0, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={43:0}, b={43:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={43:0}, b={43:0}, i=0, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={43:0}, b={43:0}, b[i]=53, i=0, size=2] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=2, b={43:0}, b={43:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={43:0}, b={43:0}, i=1, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={43:0}, b={43:0}, b[i]=50, i=1, size=2] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=2, b={43:0}, b={43:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={43:0}, b={43:0}, i=2, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={43:0}, b={43:0}, b[i]=59, i=2, size=2] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=2, b={43:0}, b={43:0}, i=3, size=2] [L20] RET return i; VAL [\old(size)=2, \result=3, b={43:0}, b={43:0}, i=3, size=2] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=3, i=1, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=2, mask={43:0}] [L27] EXPR b[i] VAL [i=2, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=3, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={43:0}, b={43:0}, i=0, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={43:0}, b={43:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={43:0}, b={43:0}, i=0, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={43:0}, b={43:0}, b[i]=53, i=0, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=3, b={43:0}, b={43:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={43:0}, b={43:0}, i=1, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={43:0}, b={43:0}, b[i]=50, i=1, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=3, b={43:0}, b={43:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={43:0}, b={43:0}, i=2, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={43:0}, b={43:0}, b[i]=59, i=2, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=3, b={43:0}, b={43:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={43:0}, b={43:0}, i=3, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={43:0}, b={43:0}, b[i]=41, i=3, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=3, b={43:0}, b={43:0}, i=4, size=3] [L20] RET return i; VAL [\old(size)=3, \result=4, b={43:0}, b={43:0}, i=4, size=3] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=4, i=2, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=3, mask={43:0}] [L27] EXPR b[i] VAL [i=3, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=4, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={43:0}, b={43:0}, i=0, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={43:0}, b={43:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={43:0}, b={43:0}, i=0, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={43:0}, b={43:0}, b[i]=53, i=0, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=4, b={43:0}, b={43:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={43:0}, b={43:0}, i=1, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={43:0}, b={43:0}, b[i]=50, i=1, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=4, b={43:0}, b={43:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={43:0}, b={43:0}, i=2, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={43:0}, b={43:0}, b[i]=59, i=2, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=4, b={43:0}, b={43:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={43:0}, b={43:0}, i=3, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={43:0}, b={43:0}, b[i]=41, i=3, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=4, b={43:0}, b={43:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={43:0}, b={43:0}, i=4, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={43:0}, b={43:0}, b[i]=52, i=4, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=4, b={43:0}, b={43:0}, i=5, size=4] [L20] RET return i; VAL [\old(size)=4, \result=5, b={43:0}, b={43:0}, i=5, size=4] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=5, i=3, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=4, mask={43:0}] [L27] EXPR b[i] VAL [i=4, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=5, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={43:0}, b={43:0}, i=0, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={43:0}, b={43:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={43:0}, b={43:0}, i=0, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={43:0}, b={43:0}, b[i]=53, i=0, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=5, b={43:0}, b={43:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={43:0}, b={43:0}, i=1, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={43:0}, b={43:0}, b[i]=50, i=1, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=5, b={43:0}, b={43:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={43:0}, b={43:0}, i=2, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={43:0}, b={43:0}, b[i]=59, i=2, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=5, b={43:0}, b={43:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={43:0}, b={43:0}, i=3, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={43:0}, b={43:0}, b[i]=41, i=3, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=5, b={43:0}, b={43:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={43:0}, b={43:0}, i=4, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={43:0}, b={43:0}, b[i]=52, i=4, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=5, b={43:0}, b={43:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={43:0}, b={43:0}, i=5, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={43:0}, b={43:0}, b[i]=35, i=5, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=5, b={43:0}, b={43:0}, i=6, size=5] [L20] RET return i; VAL [\old(size)=5, \result=6, b={43:0}, b={43:0}, i=6, size=5] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=6, i=4, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=5, mask={43:0}] [L27] EXPR b[i] VAL [i=5, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=6, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={43:0}, b={43:0}, i=0, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={43:0}, b={43:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={43:0}, b={43:0}, i=0, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={43:0}, b={43:0}, b[i]=53, i=0, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=6, b={43:0}, b={43:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={43:0}, b={43:0}, i=1, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={43:0}, b={43:0}, b[i]=50, i=1, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=6, b={43:0}, b={43:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={43:0}, b={43:0}, i=2, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={43:0}, b={43:0}, b[i]=59, i=2, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=6, b={43:0}, b={43:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={43:0}, b={43:0}, i=3, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={43:0}, b={43:0}, b[i]=41, i=3, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=6, b={43:0}, b={43:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={43:0}, b={43:0}, i=4, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={43:0}, b={43:0}, b[i]=52, i=4, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=6, b={43:0}, b={43:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={43:0}, b={43:0}, i=5, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={43:0}, b={43:0}, b[i]=35, i=5, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=6, b={43:0}, b={43:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={43:0}, b={43:0}, i=6, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={43:0}, b={43:0}, b[i]=34, i=6, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=6, b={43:0}, b={43:0}, i=7, size=6] [L20] RET return i; VAL [\old(size)=6, \result=7, b={43:0}, b={43:0}, i=7, size=6] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=7, i=5, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=6, mask={43:0}] [L27] EXPR b[i] VAL [i=6, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=7, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={43:0}, b={43:0}, i=0, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=0, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=53, i=0, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=1, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=50, i=1, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=2, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=59, i=2, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=3, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=41, i=3, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=4, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=52, i=4, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=5, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=35, i=5, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=6, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=34, i=6, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=7, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=51, i=7, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=7, b={43:0}, b={43:0}, i=8, size=7] [L20] RET return i; VAL [\old(size)=7, \result=8, b={43:0}, b={43:0}, i=8, size=7] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=8, i=6, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=7, mask={43:0}] [L27] EXPR b[i] VAL [i=7, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=8, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={43:0}, b={43:0}, i=0, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=0, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=53, i=0, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=1, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=50, i=1, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=2, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=59, i=2, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=3, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=41, i=3, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=4, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=52, i=4, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=5, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=35, i=5, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=6, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=34, i=6, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=7, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=51, i=7, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=8, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=36, i=8, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=8, b={43:0}, b={43:0}, i=9, size=8] [L20] RET return i; VAL [\old(size)=8, \result=9, b={43:0}, b={43:0}, i=9, size=8] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=9, i=7, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=8, mask={43:0}] [L27] EXPR b[i] VAL [i=8, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=9, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={43:0}, b={43:0}, i=0, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=0, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=53, i=0, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=1, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=50, i=1, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=2, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=59, i=2, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=3, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=41, i=3, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=4, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=52, i=4, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=5, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=35, i=5, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=6, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=34, i=6, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=7, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=51, i=7, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=8, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=36, i=8, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=9, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=37, i=9, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=9, b={43:0}, b={43:0}, i=10, size=9] [L20] RET return i; VAL [\old(size)=9, \result=10, b={43:0}, b={43:0}, i=10, size=9] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=10, i=8, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=9, mask={43:0}] [L27] EXPR b[i] VAL [i=9, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=10, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={43:0}, b={43:0}, i=0, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=0, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=53, i=0, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=1, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=50, i=1, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=2, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=59, i=2, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=3, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=41, i=3, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=4, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=52, i=4, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=5, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=35, i=5, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=6, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=34, i=6, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=7, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=51, i=7, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=8, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=36, i=8, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=9, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=37, i=9, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=10, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=42, i=10, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=10, b={43:0}, b={43:0}, i=11, size=10] [L20] RET return i; VAL [\old(size)=10, \result=11, b={43:0}, b={43:0}, i=11, size=10] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=11, i=9, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=10, mask={43:0}] [L27] EXPR b[i] VAL [i=10, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=11, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={43:0}, b={43:0}, i=0, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=0, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=53, i=0, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=1, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=50, i=1, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=2, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=59, i=2, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=3, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=41, i=3, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=4, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=52, i=4, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=5, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=35, i=5, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=6, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=34, i=6, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=7, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=51, i=7, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=8, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=36, i=8, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=9, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=37, i=9, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=10, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=42, i=10, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=11, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=62, i=11, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=11, b={43:0}, b={43:0}, i=12, size=11] [L20] RET return i; VAL [\old(size)=11, \result=12, b={43:0}, b={43:0}, i=12, size=11] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=12, i=10, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=11, mask={43:0}] [L27] EXPR b[i] VAL [i=11, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=12, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={43:0}, b={43:0}, i=0, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=0, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=53, i=0, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=1, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=50, i=1, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=2, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=59, i=2, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=3, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=41, i=3, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=4, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=52, i=4, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=5, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=35, i=5, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=6, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=34, i=6, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=7, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=51, i=7, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=8, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=36, i=8, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=9, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=37, i=9, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=10, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=42, i=10, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=11, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=62, i=11, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=12, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=61, i=12, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=12, b={43:0}, b={43:0}, i=13, size=12] [L20] RET return i; VAL [\old(size)=12, \result=13, b={43:0}, b={43:0}, i=13, size=12] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=13, i=11, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=12, mask={43:0}] [L27] EXPR b[i] VAL [i=12, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=13, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={43:0}, b={43:0}, i=0, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=0, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=53, i=0, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=1, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=50, i=1, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=2, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=59, i=2, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=3, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=41, i=3, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=4, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=52, i=4, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=5, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=35, i=5, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=6, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=34, i=6, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=7, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=51, i=7, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=8, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=36, i=8, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=9, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=37, i=9, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=10, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=42, i=10, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=11, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=62, i=11, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=12, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=61, i=12, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=13, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=63, i=13, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=13, b={43:0}, b={43:0}, i=14, size=13] [L20] RET return i; VAL [\old(size)=13, \result=14, b={43:0}, b={43:0}, i=14, size=13] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=14, i=12, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=13, mask={43:0}] [L27] EXPR b[i] VAL [i=13, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=14, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={43:0}, b={43:0}, i=0, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=0, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=53, i=0, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=1, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=50, i=1, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=2, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=59, i=2, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=3, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=41, i=3, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=4, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=52, i=4, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=5, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=35, i=5, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=6, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=34, i=6, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=7, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=51, i=7, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=8, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=36, i=8, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=9, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=37, i=9, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=10, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=42, i=10, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=11, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=62, i=11, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=12, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=61, i=12, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=13, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=63, i=13, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=14, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=40, i=14, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=14, b={43:0}, b={43:0}, i=15, size=14] [L20] RET return i; VAL [\old(size)=14, \result=15, b={43:0}, b={43:0}, i=15, size=14] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=15, i=13, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=14, mask={43:0}] [L27] EXPR b[i] VAL [i=14, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=15, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={43:0}, b={43:0}, i=0, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=0, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=53, i=0, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=1, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=50, i=1, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=2, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=59, i=2, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=3, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=41, i=3, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=4, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=52, i=4, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=5, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=35, i=5, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=6, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=34, i=6, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=7, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=51, i=7, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=8, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=36, i=8, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=9, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=37, i=9, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=10, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=42, i=10, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=11, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=62, i=11, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=12, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=61, i=12, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=13, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=63, i=13, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=14, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=40, i=14, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=15, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=48, i=15, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=15, b={43:0}, b={43:0}, i=16, size=15] [L20] RET return i; VAL [\old(size)=15, \result=16, b={43:0}, b={43:0}, i=16, size=15] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=16, i=14, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=15, mask={43:0}] [L27] EXPR b[i] VAL [i=15, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=16, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={43:0}, b={43:0}, i=0, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=0, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=53, i=0, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=1, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=50, i=1, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=2, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=59, i=2, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=3, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=41, i=3, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=4, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=52, i=4, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=5, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=35, i=5, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=6, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=34, i=6, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=7, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=51, i=7, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=8, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=36, i=8, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=9, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=37, i=9, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=10, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=42, i=10, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=11, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=62, i=11, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=12, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=61, i=12, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=13, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=63, i=13, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=14, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=40, i=14, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=15, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=48, i=15, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=16, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=54, i=16, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=16, b={43:0}, b={43:0}, i=17, size=16] [L20] RET return i; VAL [\old(size)=16, \result=17, b={43:0}, b={43:0}, i=17, size=16] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=17, i=15, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=16, mask={43:0}] [L27] EXPR b[i] VAL [i=16, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=17, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={43:0}, b={43:0}, i=0, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=0, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=53, i=0, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=1, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=50, i=1, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=2, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=59, i=2, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=3, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=41, i=3, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=4, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=52, i=4, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=5, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=35, i=5, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=6, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=34, i=6, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=7, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=51, i=7, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=8, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=36, i=8, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=9, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=37, i=9, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=10, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=42, i=10, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=11, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=62, i=11, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=12, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=61, i=12, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=13, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=63, i=13, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=14, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=40, i=14, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=15, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=48, i=15, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=16, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=54, i=16, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=17, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=64, i=17, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=17, b={43:0}, b={43:0}, i=18, size=17] [L20] RET return i; VAL [\old(size)=17, \result=18, b={43:0}, b={43:0}, i=18, size=17] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=18, i=16, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=17, mask={43:0}] [L27] EXPR b[i] VAL [i=17, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=18, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={43:0}, b={43:0}, i=0, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=0, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=53, i=0, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=1, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=50, i=1, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=2, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=59, i=2, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=3, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=41, i=3, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=4, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=52, i=4, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=5, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=35, i=5, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=6, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=34, i=6, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=7, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=51, i=7, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=8, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=36, i=8, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=9, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=37, i=9, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=10, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=42, i=10, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=11, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=62, i=11, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=12, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=61, i=12, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=13, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=63, i=13, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=14, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=40, i=14, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=15, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=48, i=15, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=16, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=54, i=16, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=17, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=64, i=17, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=18, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=44, i=18, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=18, b={43:0}, b={43:0}, i=19, size=18] [L20] RET return i; VAL [\old(size)=18, \result=19, b={43:0}, b={43:0}, i=19, size=18] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=19, i=17, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=18, mask={43:0}] [L27] EXPR b[i] VAL [i=18, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=19, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={43:0}, b={43:0}, i=0, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=0, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=53, i=0, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=1, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=50, i=1, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=2, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=59, i=2, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=3, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=41, i=3, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=4, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=52, i=4, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=5, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=35, i=5, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=6, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=34, i=6, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=7, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=51, i=7, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=8, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=36, i=8, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=9, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=37, i=9, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=10, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=42, i=10, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=11, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=62, i=11, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=12, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=61, i=12, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=13, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=63, i=13, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=14, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=40, i=14, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=15, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=48, i=15, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=16, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=54, i=16, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=17, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=64, i=17, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=18, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=44, i=18, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=19, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=58, i=19, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=19, b={43:0}, b={43:0}, i=20, size=19] [L20] RET return i; VAL [\old(size)=19, \result=20, b={43:0}, b={43:0}, i=20, size=19] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=20, i=18, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=19, mask={43:0}] [L27] EXPR b[i] VAL [i=19, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=20, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={43:0}, b={43:0}, i=0, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=0, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=53, i=0, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=1, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=50, i=1, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=2, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=59, i=2, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=3, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=41, i=3, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=4, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=52, i=4, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=5, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=35, i=5, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=6, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=34, i=6, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=7, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=51, i=7, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=8, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=36, i=8, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=9, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=37, i=9, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=10, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=42, i=10, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=11, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=62, i=11, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=12, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=61, i=12, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=13, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=63, i=13, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=14, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=40, i=14, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=15, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=48, i=15, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=16, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=54, i=16, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=17, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=64, i=17, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=18, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=44, i=18, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=19, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=58, i=19, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=20, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=55, i=20, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=20, b={43:0}, b={43:0}, i=21, size=20] [L20] RET return i; VAL [\old(size)=20, \result=21, b={43:0}, b={43:0}, i=21, size=20] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=21, i=19, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=20, mask={43:0}] [L27] EXPR b[i] VAL [i=20, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=21, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={43:0}, b={43:0}, i=0, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=0, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=53, i=0, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=1, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=50, i=1, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=2, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=59, i=2, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=3, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=41, i=3, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=4, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=52, i=4, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=5, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=35, i=5, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=6, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=34, i=6, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=7, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=51, i=7, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=8, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=36, i=8, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=9, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=37, i=9, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=10, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=42, i=10, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=11, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=62, i=11, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=12, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=61, i=12, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=13, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=63, i=13, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=14, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=40, i=14, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=15, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=48, i=15, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=16, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=54, i=16, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=17, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=64, i=17, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=18, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=44, i=18, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=19, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=58, i=19, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=20, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=55, i=20, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=21, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=33, i=21, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=21, b={43:0}, b={43:0}, i=22, size=21] [L20] RET return i; VAL [\old(size)=21, \result=22, b={43:0}, b={43:0}, i=22, size=21] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=22, i=20, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=21, mask={43:0}] [L27] EXPR b[i] VAL [i=21, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=22, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={43:0}, b={43:0}, i=0, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=0, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=53, i=0, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=1, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=50, i=1, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=2, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=59, i=2, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=3, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=41, i=3, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=4, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=52, i=4, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=5, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=35, i=5, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=6, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=34, i=6, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=7, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=51, i=7, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=8, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=36, i=8, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=9, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=37, i=9, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=10, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=42, i=10, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=11, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=62, i=11, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=12, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=61, i=12, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=13, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=63, i=13, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=14, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=40, i=14, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=15, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=48, i=15, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=16, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=54, i=16, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=17, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=64, i=17, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=18, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=44, i=18, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=19, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=58, i=19, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=20, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=55, i=20, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=21, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=33, i=21, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=22, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=47, i=22, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=22, b={43:0}, b={43:0}, i=23, size=22] [L20] RET return i; VAL [\old(size)=22, \result=23, b={43:0}, b={43:0}, i=23, size=22] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=23, i=21, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=22, mask={43:0}] [L27] EXPR b[i] VAL [i=22, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=23, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={43:0}, b={43:0}, i=0, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=0, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=53, i=0, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=1, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=50, i=1, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=2, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=59, i=2, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=3, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=41, i=3, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=4, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=52, i=4, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=5, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=35, i=5, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=6, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=34, i=6, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=7, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=51, i=7, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=8, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=36, i=8, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=9, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=37, i=9, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=10, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=42, i=10, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=11, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=62, i=11, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=12, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=61, i=12, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=13, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=63, i=13, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=14, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=40, i=14, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=15, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=48, i=15, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=16, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=54, i=16, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=17, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=64, i=17, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=18, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=44, i=18, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=19, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=58, i=19, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=20, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=55, i=20, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=21, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=33, i=21, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=22, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=47, i=22, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=23, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=46, i=23, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=23, b={43:0}, b={43:0}, i=24, size=23] [L20] RET return i; VAL [\old(size)=23, \result=24, b={43:0}, b={43:0}, i=24, size=23] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=24, i=22, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=23, mask={43:0}] [L27] EXPR b[i] VAL [i=23, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=24, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={43:0}, b={43:0}, i=0, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=0, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=53, i=0, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=1, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=50, i=1, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=2, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=59, i=2, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=3, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=41, i=3, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=4, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=52, i=4, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=5, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=35, i=5, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=6, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=34, i=6, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=7, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=51, i=7, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=8, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=36, i=8, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=9, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=37, i=9, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=10, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=42, i=10, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=11, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=62, i=11, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=12, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=61, i=12, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=13, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=63, i=13, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=14, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=40, i=14, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=15, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=48, i=15, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=16, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=54, i=16, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=17, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=64, i=17, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=18, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=44, i=18, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=19, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=58, i=19, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=20, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=55, i=20, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=21, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=33, i=21, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=22, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=47, i=22, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=23, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=46, i=23, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=24, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=67, i=24, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=24, b={43:0}, b={43:0}, i=25, size=24] [L20] RET return i; VAL [\old(size)=24, \result=25, b={43:0}, b={43:0}, i=25, size=24] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=25, i=23, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=24, mask={43:0}] [L27] EXPR b[i] VAL [i=24, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=25, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={43:0}, b={43:0}, i=0, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=0, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=53, i=0, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=1, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=50, i=1, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=2, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=59, i=2, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=3, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=41, i=3, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=4, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=52, i=4, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=5, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=35, i=5, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=6, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=34, i=6, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=7, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=51, i=7, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=8, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=36, i=8, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=9, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=37, i=9, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=10, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=42, i=10, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=11, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=62, i=11, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=12, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=61, i=12, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=13, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=63, i=13, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=14, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=40, i=14, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=15, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=48, i=15, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=16, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=54, i=16, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=17, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=64, i=17, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=18, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=44, i=18, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=19, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=58, i=19, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=20, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=55, i=20, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=21, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=33, i=21, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=22, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=47, i=22, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=23, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=46, i=23, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=24, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=67, i=24, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=25, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=45, i=25, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=25, b={43:0}, b={43:0}, i=26, size=25] [L20] RET return i; VAL [\old(size)=25, \result=26, b={43:0}, b={43:0}, i=26, size=25] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=26, i=24, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=25, mask={43:0}] [L27] EXPR b[i] VAL [i=25, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=26, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={43:0}, b={43:0}, i=0, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=0, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=53, i=0, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=1, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=50, i=1, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=2, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=59, i=2, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=3, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=41, i=3, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=4, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=52, i=4, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=5, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=35, i=5, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=6, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=34, i=6, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=7, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=51, i=7, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=8, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=36, i=8, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=9, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=37, i=9, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=10, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=42, i=10, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=11, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=62, i=11, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=12, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=61, i=12, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=13, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=63, i=13, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=14, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=40, i=14, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=15, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=48, i=15, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=16, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=54, i=16, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=17, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=64, i=17, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=18, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=44, i=18, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=19, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=58, i=19, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=20, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=55, i=20, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=21, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=33, i=21, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=22, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=47, i=22, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=23, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=46, i=23, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=24, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=67, i=24, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=25, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=45, i=25, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=26, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=56, i=26, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=26, b={43:0}, b={43:0}, i=27, size=26] [L20] RET return i; VAL [\old(size)=26, \result=27, b={43:0}, b={43:0}, i=27, size=26] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=27, i=25, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=26, mask={43:0}] [L27] EXPR b[i] VAL [i=26, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=27, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={43:0}, b={43:0}, i=0, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=0, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=53, i=0, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=1, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=50, i=1, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=2, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=59, i=2, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=3, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=41, i=3, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=4, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=52, i=4, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=5, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=35, i=5, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=6, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=34, i=6, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=7, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=51, i=7, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=8, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=36, i=8, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=9, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=37, i=9, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=10, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=42, i=10, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=11, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=62, i=11, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=12, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=61, i=12, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=13, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=63, i=13, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=14, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=40, i=14, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=15, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=48, i=15, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=16, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=54, i=16, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=17, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=64, i=17, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=18, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=44, i=18, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=19, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=58, i=19, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=20, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=55, i=20, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=21, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=33, i=21, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=22, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=47, i=22, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=23, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=46, i=23, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=24, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=67, i=24, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=25, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=45, i=25, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=26, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=56, i=26, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=27, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=38, i=27, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=27, b={43:0}, b={43:0}, i=28, size=27] [L20] RET return i; VAL [\old(size)=27, \result=28, b={43:0}, b={43:0}, i=28, size=27] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=28, i=26, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=27, mask={43:0}] [L27] EXPR b[i] VAL [i=27, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=28, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={43:0}, b={43:0}, i=0, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=0, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=53, i=0, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=1, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=50, i=1, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=2, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=59, i=2, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=3, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=41, i=3, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=4, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=52, i=4, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=5, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=35, i=5, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=6, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=34, i=6, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=7, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=51, i=7, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=8, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=36, i=8, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=9, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=37, i=9, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=10, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=42, i=10, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=11, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=62, i=11, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=12, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=61, i=12, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=13, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=63, i=13, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=14, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=40, i=14, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=15, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=48, i=15, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=16, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=54, i=16, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=17, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=64, i=17, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=18, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=44, i=18, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=19, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=58, i=19, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=20, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=55, i=20, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=21, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=33, i=21, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=22, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=47, i=22, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=23, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=46, i=23, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=24, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=67, i=24, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=25, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=45, i=25, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=26, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=56, i=26, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=27, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=38, i=27, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=28, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=65, i=28, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=28, b={43:0}, b={43:0}, i=29, size=28] [L20] RET return i; VAL [\old(size)=28, \result=29, b={43:0}, b={43:0}, i=29, size=28] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=29, i=27, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=28, mask={43:0}] [L27] EXPR b[i] VAL [i=28, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=29, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={43:0}, b={43:0}, i=0, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=0, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=53, i=0, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=1, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=50, i=1, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=2, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=59, i=2, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=3, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=41, i=3, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=4, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=52, i=4, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=5, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=35, i=5, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=6, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=34, i=6, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=7, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=51, i=7, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=8, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=36, i=8, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=9, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=37, i=9, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=10, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=42, i=10, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=11, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=62, i=11, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=12, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=61, i=12, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=13, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=63, i=13, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=14, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=40, i=14, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=15, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=48, i=15, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=16, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=54, i=16, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=17, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=64, i=17, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=18, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=44, i=18, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=19, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=58, i=19, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=20, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=55, i=20, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=21, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=33, i=21, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=22, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=47, i=22, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=23, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=46, i=23, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=24, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=67, i=24, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=25, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=45, i=25, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=26, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=56, i=26, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=27, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=38, i=27, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=28, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=65, i=28, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=29, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=66, i=29, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=29, b={43:0}, b={43:0}, i=30, size=29] [L20] RET return i; VAL [\old(size)=29, \result=30, b={43:0}, b={43:0}, i=30, size=29] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=30, i=28, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=29, mask={43:0}] [L27] EXPR b[i] VAL [i=29, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=30, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={43:0}, b={43:0}, i=0, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=0, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=53, i=0, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=1, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=50, i=1, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=2, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=59, i=2, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=3, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=41, i=3, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=4, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=52, i=4, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=5, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=35, i=5, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=6, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=34, i=6, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=7, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=51, i=7, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=8, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=36, i=8, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=9, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=37, i=9, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=10, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=42, i=10, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=11, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=62, i=11, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=12, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=61, i=12, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=13, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=63, i=13, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=14, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=40, i=14, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=15, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=48, i=15, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=16, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=54, i=16, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=17, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=64, i=17, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=18, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=44, i=18, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=19, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=58, i=19, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=20, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=55, i=20, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=21, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=33, i=21, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=22, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=47, i=22, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=23, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=46, i=23, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=24, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=67, i=24, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=25, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=45, i=25, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=26, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=56, i=26, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=27, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=38, i=27, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=28, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=65, i=28, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=29, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=66, i=29, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=30, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=39, i=30, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=30, b={43:0}, b={43:0}, i=31, size=30] [L20] RET return i; VAL [\old(size)=30, \result=31, b={43:0}, b={43:0}, i=31, size=30] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=31, i=29, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=30, mask={43:0}] [L27] EXPR b[i] VAL [i=30, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=31, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={43:0}, b={43:0}, i=0, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=0, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=53, i=0, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=1, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=50, i=1, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=2, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=59, i=2, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=3, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=41, i=3, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=4, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=52, i=4, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=5, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=35, i=5, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=6, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=34, i=6, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=7, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=51, i=7, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=8, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=36, i=8, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=9, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=37, i=9, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=10, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=42, i=10, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=11, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=62, i=11, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=12, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=61, i=12, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=13, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=63, i=13, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=14, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=40, i=14, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=15, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=48, i=15, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=16, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=54, i=16, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=17, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=64, i=17, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=18, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=44, i=18, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=19, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=58, i=19, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=20, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=55, i=20, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=21, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=33, i=21, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=22, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=47, i=22, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=23, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=46, i=23, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=24, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=67, i=24, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=25, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=45, i=25, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=26, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=56, i=26, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=27, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=38, i=27, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=28, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=65, i=28, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=29, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=66, i=29, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=30, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=39, i=30, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=31, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=57, i=31, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=31, b={43:0}, b={43:0}, i=32, size=31] [L20] RET return i; VAL [\old(size)=31, \result=32, b={43:0}, b={43:0}, i=32, size=31] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=32, i=30, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=31, mask={43:0}] [L27] b[i] VAL [i=31, mask={43:0}] [L27] CALL foo(mask, i + 1) VAL [\old(size)=32, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=32, b={43:0}, b={43:0}, i=0, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=0, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=0, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=53, i=0, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=1, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=1, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=50, i=1, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=2, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=2, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=59, i=2, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=3, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=3, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=41, i=3, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=4, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=4, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=52, i=4, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=5, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=5, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=35, i=5, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=6, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=6, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=34, i=6, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=7, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=7, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=51, i=7, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=8, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=8, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=36, i=8, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=9, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=9, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=37, i=9, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=10, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=10, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=42, i=10, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=11, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=11, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=62, i=11, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=12, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=12, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=61, i=12, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=13, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=13, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=63, i=13, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=14, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=14, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=40, i=14, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=15, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=15, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=48, i=15, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=16, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=16, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=54, i=16, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=17, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=17, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=64, i=17, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=18, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=18, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=44, i=18, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=19, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=19, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=58, i=19, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=20, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=20, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=55, i=20, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=21, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=21, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=33, i=21, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=22, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=22, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=47, i=22, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=23, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=23, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=46, i=23, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=24, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=24, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=67, i=24, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=25, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=25, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=45, i=25, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=26, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=26, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=56, i=26, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=27, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=27, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=38, i=27, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=28, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=28, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=65, i=28, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=29, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=29, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=66, i=29, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=30, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=30, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=39, i=30, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=31, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=31, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=57, i=31, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=32, size=32] [L18] a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=32, size=32] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 46 locations, 6 error locations. UNSAFE Result, 462.6s OverallTime, 83 OverallIterations, 591 TraceHistogramMax, 82.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3556 SDtfs, 44699 SDslu, 46143 SDs, 0 SdLazy, 139965 SolverSat, 6163 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 33.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 105095 GetRequests, 99064 SyntacticMatches, 15 SemanticMatches, 6016 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 199941 ImplicationChecksByTransitivity, 84.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3974occurred in iteration=80, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.7s AutomataMinimizationTime, 82 MinimizatonAttempts, 1128 StatesRemovedByMinimization, 80 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 1.1s SsaConstructionTime, 181.7s SatisfiabilityAnalysisTime, 131.6s InterpolantComputationTime, 210766 NumberOfCodeBlocks, 196629 NumberOfCodeBlocksAsserted, 1230 NumberOfCheckSat, 203737 ConstructedInterpolants, 0 QuantifiedInterpolants, 633128408 SizeOfPredicates, 175 NumberOfNonLiveVariables, 194749 ConjunctsInSsa, 2357 ConjunctsInUnsatCore, 157 InterpolantComputations, 7 PerfectInterpolantSequences, 30474781/30741309 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf_AutomizerC.xml/Csv-Benchmark-0-2018-04-13_08-41-02-213.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-04-13_08-41-02-213.csv Received shutdown request...