/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf -i ../../../trunk/examples/svcomp/systemc/transmitter.02.cil.c -------------------------------------------------------------------------------- This is Ultimate 0.1.25-86f66a4 [2020-07-07 11:36:16,900 INFO L177 SettingsManager]: Resetting all preferences to default values... [2020-07-07 11:36:16,904 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2020-07-07 11:36:16,922 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2020-07-07 11:36:16,922 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2020-07-07 11:36:16,923 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2020-07-07 11:36:16,925 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2020-07-07 11:36:16,927 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2020-07-07 11:36:16,928 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2020-07-07 11:36:16,929 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2020-07-07 11:36:16,930 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2020-07-07 11:36:16,931 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2020-07-07 11:36:16,931 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2020-07-07 11:36:16,932 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2020-07-07 11:36:16,933 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2020-07-07 11:36:16,935 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2020-07-07 11:36:16,935 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2020-07-07 11:36:16,936 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2020-07-07 11:36:16,938 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2020-07-07 11:36:16,941 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2020-07-07 11:36:16,944 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2020-07-07 11:36:16,946 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2020-07-07 11:36:16,947 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2020-07-07 11:36:16,948 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2020-07-07 11:36:16,953 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2020-07-07 11:36:16,957 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2020-07-07 11:36:16,958 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2020-07-07 11:36:16,960 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2020-07-07 11:36:16,961 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2020-07-07 11:36:16,962 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2020-07-07 11:36:16,963 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2020-07-07 11:36:16,963 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2020-07-07 11:36:16,964 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2020-07-07 11:36:16,964 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2020-07-07 11:36:16,965 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2020-07-07 11:36:16,965 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2020-07-07 11:36:16,966 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/default/automizer/svcomp-Reach-32bit-Automizer_Default.epf [2020-07-07 11:36:16,982 INFO L113 SettingsManager]: Loading preferences was successful [2020-07-07 11:36:16,982 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2020-07-07 11:36:16,984 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2020-07-07 11:36:16,985 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2020-07-07 11:36:16,985 INFO L138 SettingsManager]: * Use SBE=true [2020-07-07 11:36:16,985 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2020-07-07 11:36:16,985 INFO L138 SettingsManager]: * sizeof long=4 [2020-07-07 11:36:16,985 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2020-07-07 11:36:16,986 INFO L138 SettingsManager]: * sizeof POINTER=4 [2020-07-07 11:36:16,986 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2020-07-07 11:36:16,986 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2020-07-07 11:36:16,986 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2020-07-07 11:36:16,986 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2020-07-07 11:36:16,987 INFO L138 SettingsManager]: * sizeof long double=12 [2020-07-07 11:36:16,987 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2020-07-07 11:36:16,987 INFO L138 SettingsManager]: * Use constant arrays=true [2020-07-07 11:36:16,987 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2020-07-07 11:36:16,988 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2020-07-07 11:36:16,988 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2020-07-07 11:36:16,988 INFO L138 SettingsManager]: * To the following directory=./dump/ [2020-07-07 11:36:16,988 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2020-07-07 11:36:16,988 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2020-07-07 11:36:16,989 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2020-07-07 11:36:16,989 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2020-07-07 11:36:16,989 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2020-07-07 11:36:16,989 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2020-07-07 11:36:16,989 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2020-07-07 11:36:16,990 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2020-07-07 11:36:16,990 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2020-07-07 11:36:16,990 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2020-07-07 11:36:17,320 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2020-07-07 11:36:17,335 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2020-07-07 11:36:17,339 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2020-07-07 11:36:17,340 INFO L271 PluginConnector]: Initializing CDTParser... [2020-07-07 11:36:17,341 INFO L275 PluginConnector]: CDTParser initialized [2020-07-07 11:36:17,341 INFO L429 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/systemc/transmitter.02.cil.c [2020-07-07 11:36:17,408 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b2abe41af/49243f278f08474db8a95d7bd07f2495/FLAGec2ec3e9c [2020-07-07 11:36:17,976 INFO L306 CDTParser]: Found 1 translation units. [2020-07-07 11:36:17,977 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/systemc/transmitter.02.cil.c [2020-07-07 11:36:17,997 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b2abe41af/49243f278f08474db8a95d7bd07f2495/FLAGec2ec3e9c [2020-07-07 11:36:18,347 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b2abe41af/49243f278f08474db8a95d7bd07f2495 [2020-07-07 11:36:18,367 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2020-07-07 11:36:18,371 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2020-07-07 11:36:18,380 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2020-07-07 11:36:18,380 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2020-07-07 11:36:18,387 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2020-07-07 11:36:18,388 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.07 11:36:18" (1/1) ... [2020-07-07 11:36:18,393 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@598b209e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.07 11:36:18, skipping insertion in model container [2020-07-07 11:36:18,394 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.07 11:36:18" (1/1) ... [2020-07-07 11:36:18,409 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2020-07-07 11:36:18,492 INFO L178 MainTranslator]: Built tables and reachable declarations [2020-07-07 11:36:18,830 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-07-07 11:36:18,839 INFO L203 MainTranslator]: Completed pre-run [2020-07-07 11:36:18,999 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-07-07 11:36:19,030 INFO L208 MainTranslator]: Completed translation [2020-07-07 11:36:19,030 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.07 11:36:19 WrapperNode [2020-07-07 11:36:19,030 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2020-07-07 11:36:19,031 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2020-07-07 11:36:19,031 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2020-07-07 11:36:19,032 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2020-07-07 11:36:19,048 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.07 11:36:19" (1/1) ... [2020-07-07 11:36:19,048 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.07 11:36:19" (1/1) ... [2020-07-07 11:36:19,057 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.07 11:36:19" (1/1) ... [2020-07-07 11:36:19,058 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.07 11:36:19" (1/1) ... [2020-07-07 11:36:19,069 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.07 11:36:19" (1/1) ... [2020-07-07 11:36:19,081 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.07 11:36:19" (1/1) ... [2020-07-07 11:36:19,084 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.07 11:36:19" (1/1) ... [2020-07-07 11:36:19,088 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2020-07-07 11:36:19,089 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2020-07-07 11:36:19,089 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2020-07-07 11:36:19,090 INFO L275 PluginConnector]: RCFGBuilder initialized [2020-07-07 11:36:19,093 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.07 11:36:19" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2020-07-07 11:36:19,173 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2020-07-07 11:36:19,174 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2020-07-07 11:36:19,174 INFO L138 BoogieDeclarations]: Found implementation of procedure error [2020-07-07 11:36:19,174 INFO L138 BoogieDeclarations]: Found implementation of procedure master [2020-07-07 11:36:19,174 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit1 [2020-07-07 11:36:19,174 INFO L138 BoogieDeclarations]: Found implementation of procedure transmit2 [2020-07-07 11:36:19,175 INFO L138 BoogieDeclarations]: Found implementation of procedure is_master_triggered [2020-07-07 11:36:19,175 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit1_triggered [2020-07-07 11:36:19,175 INFO L138 BoogieDeclarations]: Found implementation of procedure is_transmit2_triggered [2020-07-07 11:36:19,175 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2020-07-07 11:36:19,176 INFO L138 BoogieDeclarations]: Found implementation of procedure init_threads [2020-07-07 11:36:19,176 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2020-07-07 11:36:19,176 INFO L138 BoogieDeclarations]: Found implementation of procedure eval [2020-07-07 11:36:19,176 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2020-07-07 11:36:19,177 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2020-07-07 11:36:19,177 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2020-07-07 11:36:19,177 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2020-07-07 11:36:19,178 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_time_events [2020-07-07 11:36:19,178 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_time_events [2020-07-07 11:36:19,178 INFO L138 BoogieDeclarations]: Found implementation of procedure init_model [2020-07-07 11:36:19,179 INFO L138 BoogieDeclarations]: Found implementation of procedure stop_simulation [2020-07-07 11:36:19,179 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2020-07-07 11:36:19,179 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2020-07-07 11:36:19,179 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2020-07-07 11:36:19,180 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2020-07-07 11:36:19,180 INFO L130 BoogieDeclarations]: Found specification of procedure error [2020-07-07 11:36:19,180 INFO L130 BoogieDeclarations]: Found specification of procedure is_master_triggered [2020-07-07 11:36:19,180 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit1_triggered [2020-07-07 11:36:19,180 INFO L130 BoogieDeclarations]: Found specification of procedure is_transmit2_triggered [2020-07-07 11:36:19,180 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2020-07-07 11:36:19,181 INFO L130 BoogieDeclarations]: Found specification of procedure master [2020-07-07 11:36:19,181 INFO L130 BoogieDeclarations]: Found specification of procedure transmit1 [2020-07-07 11:36:19,181 INFO L130 BoogieDeclarations]: Found specification of procedure transmit2 [2020-07-07 11:36:19,181 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2020-07-07 11:36:19,181 INFO L130 BoogieDeclarations]: Found specification of procedure init_threads [2020-07-07 11:36:19,181 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2020-07-07 11:36:19,182 INFO L130 BoogieDeclarations]: Found specification of procedure eval [2020-07-07 11:36:19,182 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2020-07-07 11:36:19,182 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2020-07-07 11:36:19,182 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2020-07-07 11:36:19,182 INFO L130 BoogieDeclarations]: Found specification of procedure fire_time_events [2020-07-07 11:36:19,182 INFO L130 BoogieDeclarations]: Found specification of procedure reset_time_events [2020-07-07 11:36:19,182 INFO L130 BoogieDeclarations]: Found specification of procedure init_model [2020-07-07 11:36:19,183 INFO L130 BoogieDeclarations]: Found specification of procedure stop_simulation [2020-07-07 11:36:19,183 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2020-07-07 11:36:19,183 INFO L130 BoogieDeclarations]: Found specification of procedure main [2020-07-07 11:36:19,183 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2020-07-07 11:36:19,183 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2020-07-07 11:36:19,836 INFO L290 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2020-07-07 11:36:19,837 INFO L295 CfgBuilder]: Removed 6 assume(true) statements. [2020-07-07 11:36:19,844 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.07 11:36:19 BoogieIcfgContainer [2020-07-07 11:36:19,845 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2020-07-07 11:36:19,846 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2020-07-07 11:36:19,846 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2020-07-07 11:36:19,850 INFO L275 PluginConnector]: TraceAbstraction initialized [2020-07-07 11:36:19,850 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.07 11:36:18" (1/3) ... [2020-07-07 11:36:19,853 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@59db66ec and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.07 11:36:19, skipping insertion in model container [2020-07-07 11:36:19,853 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.07 11:36:19" (2/3) ... [2020-07-07 11:36:19,854 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@59db66ec and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.07 11:36:19, skipping insertion in model container [2020-07-07 11:36:19,855 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.07 11:36:19" (3/3) ... [2020-07-07 11:36:19,857 INFO L109 eAbstractionObserver]: Analyzing ICFG transmitter.02.cil.c [2020-07-07 11:36:19,868 INFO L157 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2020-07-07 11:36:19,879 INFO L169 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2020-07-07 11:36:19,893 INFO L251 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2020-07-07 11:36:19,921 INFO L375 AbstractCegarLoop]: Interprodecural is true [2020-07-07 11:36:19,922 INFO L376 AbstractCegarLoop]: Hoare is true [2020-07-07 11:36:19,922 INFO L377 AbstractCegarLoop]: Compute interpolants for FPandBP [2020-07-07 11:36:19,922 INFO L378 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2020-07-07 11:36:19,922 INFO L379 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-07-07 11:36:19,922 INFO L380 AbstractCegarLoop]: Difference is false [2020-07-07 11:36:19,923 INFO L381 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-07-07 11:36:19,923 INFO L385 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2020-07-07 11:36:19,952 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states. [2020-07-07 11:36:19,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2020-07-07 11:36:19,967 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:36:19,968 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:36:19,968 INFO L427 AbstractCegarLoop]: === Iteration 1 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:36:19,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:36:19,974 INFO L82 PathProgramCache]: Analyzing trace with hash 1996614335, now seen corresponding path program 1 times [2020-07-07 11:36:19,981 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:36:19,982 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2695140] [2020-07-07 11:36:19,982 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:36:20,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:20,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:20,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:20,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:20,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:20,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:20,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:20,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:20,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:20,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:20,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:20,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:20,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-07 11:36:20,703 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2695140] [2020-07-07 11:36:20,705 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:36:20,705 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2020-07-07 11:36:20,706 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [723229868] [2020-07-07 11:36:20,715 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2020-07-07 11:36:20,715 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:36:20,732 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2020-07-07 11:36:20,735 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2020-07-07 11:36:20,739 INFO L87 Difference]: Start difference. First operand 169 states. Second operand 8 states. [2020-07-07 11:36:22,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:36:22,949 INFO L93 Difference]: Finished difference Result 412 states and 626 transitions. [2020-07-07 11:36:22,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2020-07-07 11:36:22,952 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 90 [2020-07-07 11:36:22,954 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:36:22,973 INFO L225 Difference]: With dead ends: 412 [2020-07-07 11:36:22,974 INFO L226 Difference]: Without dead ends: 247 [2020-07-07 11:36:22,982 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=62, Invalid=148, Unknown=0, NotChecked=0, Total=210 [2020-07-07 11:36:23,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states. [2020-07-07 11:36:23,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 160. [2020-07-07 11:36:23,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2020-07-07 11:36:23,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 212 transitions. [2020-07-07 11:36:23,088 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 212 transitions. Word has length 90 [2020-07-07 11:36:23,089 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:36:23,089 INFO L479 AbstractCegarLoop]: Abstraction has 160 states and 212 transitions. [2020-07-07 11:36:23,089 INFO L480 AbstractCegarLoop]: Interpolant automaton has 8 states. [2020-07-07 11:36:23,089 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 212 transitions. [2020-07-07 11:36:23,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2020-07-07 11:36:23,095 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:36:23,095 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:36:23,096 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2020-07-07 11:36:23,096 INFO L427 AbstractCegarLoop]: === Iteration 2 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:36:23,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:36:23,097 INFO L82 PathProgramCache]: Analyzing trace with hash -387310403, now seen corresponding path program 1 times [2020-07-07 11:36:23,097 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:36:23,097 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150752967] [2020-07-07 11:36:23,097 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:36:23,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:23,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:23,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:23,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:23,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:23,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:23,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:23,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:23,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:23,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:23,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:23,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:23,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-07 11:36:23,437 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [150752967] [2020-07-07 11:36:23,437 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:36:23,437 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2020-07-07 11:36:23,438 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [783387048] [2020-07-07 11:36:23,441 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2020-07-07 11:36:23,442 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:36:23,442 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2020-07-07 11:36:23,443 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2020-07-07 11:36:23,443 INFO L87 Difference]: Start difference. First operand 160 states and 212 transitions. Second operand 9 states. [2020-07-07 11:36:26,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:36:26,104 INFO L93 Difference]: Finished difference Result 579 states and 839 transitions. [2020-07-07 11:36:26,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2020-07-07 11:36:26,105 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 90 [2020-07-07 11:36:26,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:36:26,111 INFO L225 Difference]: With dead ends: 579 [2020-07-07 11:36:26,112 INFO L226 Difference]: Without dead ends: 439 [2020-07-07 11:36:26,114 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 26 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=91, Invalid=215, Unknown=0, NotChecked=0, Total=306 [2020-07-07 11:36:26,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 439 states. [2020-07-07 11:36:26,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 439 to 294. [2020-07-07 11:36:26,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 294 states. [2020-07-07 11:36:26,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 294 states to 294 states and 393 transitions. [2020-07-07 11:36:26,192 INFO L78 Accepts]: Start accepts. Automaton has 294 states and 393 transitions. Word has length 90 [2020-07-07 11:36:26,192 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:36:26,192 INFO L479 AbstractCegarLoop]: Abstraction has 294 states and 393 transitions. [2020-07-07 11:36:26,192 INFO L480 AbstractCegarLoop]: Interpolant automaton has 9 states. [2020-07-07 11:36:26,193 INFO L276 IsEmpty]: Start isEmpty. Operand 294 states and 393 transitions. [2020-07-07 11:36:26,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2020-07-07 11:36:26,195 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:36:26,195 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:36:26,196 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2020-07-07 11:36:26,196 INFO L427 AbstractCegarLoop]: === Iteration 3 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:36:26,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:36:26,196 INFO L82 PathProgramCache]: Analyzing trace with hash 1952833149, now seen corresponding path program 1 times [2020-07-07 11:36:26,196 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:36:26,197 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253629577] [2020-07-07 11:36:26,197 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:36:26,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:26,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:26,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:26,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:26,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:26,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:26,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:26,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:26,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:26,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:26,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:26,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:26,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-07 11:36:26,483 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253629577] [2020-07-07 11:36:26,484 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:36:26,484 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2020-07-07 11:36:26,484 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1570071975] [2020-07-07 11:36:26,485 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2020-07-07 11:36:26,485 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:36:26,485 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2020-07-07 11:36:26,486 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2020-07-07 11:36:26,486 INFO L87 Difference]: Start difference. First operand 294 states and 393 transitions. Second operand 10 states. [2020-07-07 11:36:27,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:36:27,851 INFO L93 Difference]: Finished difference Result 704 states and 993 transitions. [2020-07-07 11:36:27,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2020-07-07 11:36:27,852 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 90 [2020-07-07 11:36:27,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:36:27,864 INFO L225 Difference]: With dead ends: 704 [2020-07-07 11:36:27,865 INFO L226 Difference]: Without dead ends: 430 [2020-07-07 11:36:27,867 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=65, Invalid=145, Unknown=0, NotChecked=0, Total=210 [2020-07-07 11:36:27,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states. [2020-07-07 11:36:27,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 294. [2020-07-07 11:36:27,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 294 states. [2020-07-07 11:36:27,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 294 states to 294 states and 386 transitions. [2020-07-07 11:36:27,922 INFO L78 Accepts]: Start accepts. Automaton has 294 states and 386 transitions. Word has length 90 [2020-07-07 11:36:27,922 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:36:27,923 INFO L479 AbstractCegarLoop]: Abstraction has 294 states and 386 transitions. [2020-07-07 11:36:27,923 INFO L480 AbstractCegarLoop]: Interpolant automaton has 10 states. [2020-07-07 11:36:27,923 INFO L276 IsEmpty]: Start isEmpty. Operand 294 states and 386 transitions. [2020-07-07 11:36:27,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2020-07-07 11:36:27,925 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:36:27,925 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:36:27,925 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2020-07-07 11:36:27,926 INFO L427 AbstractCegarLoop]: === Iteration 4 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:36:27,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:36:27,926 INFO L82 PathProgramCache]: Analyzing trace with hash 227206333, now seen corresponding path program 1 times [2020-07-07 11:36:27,926 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:36:27,927 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1451424057] [2020-07-07 11:36:27,927 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:36:27,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:28,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:28,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:28,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:28,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:28,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:28,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:28,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:28,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:28,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:28,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:28,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:28,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-07 11:36:28,195 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1451424057] [2020-07-07 11:36:28,196 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:36:28,196 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2020-07-07 11:36:28,197 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657487806] [2020-07-07 11:36:28,198 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2020-07-07 11:36:28,198 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:36:28,199 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2020-07-07 11:36:28,199 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2020-07-07 11:36:28,199 INFO L87 Difference]: Start difference. First operand 294 states and 386 transitions. Second operand 10 states. [2020-07-07 11:36:29,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:36:29,819 INFO L93 Difference]: Finished difference Result 700 states and 971 transitions. [2020-07-07 11:36:29,821 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2020-07-07 11:36:29,821 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 90 [2020-07-07 11:36:29,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:36:29,842 INFO L225 Difference]: With dead ends: 700 [2020-07-07 11:36:29,842 INFO L226 Difference]: Without dead ends: 426 [2020-07-07 11:36:29,844 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=65, Invalid=145, Unknown=0, NotChecked=0, Total=210 [2020-07-07 11:36:29,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 426 states. [2020-07-07 11:36:29,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 426 to 294. [2020-07-07 11:36:29,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 294 states. [2020-07-07 11:36:29,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 294 states to 294 states and 379 transitions. [2020-07-07 11:36:29,931 INFO L78 Accepts]: Start accepts. Automaton has 294 states and 379 transitions. Word has length 90 [2020-07-07 11:36:29,934 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:36:29,934 INFO L479 AbstractCegarLoop]: Abstraction has 294 states and 379 transitions. [2020-07-07 11:36:29,935 INFO L480 AbstractCegarLoop]: Interpolant automaton has 10 states. [2020-07-07 11:36:29,943 INFO L276 IsEmpty]: Start isEmpty. Operand 294 states and 379 transitions. [2020-07-07 11:36:29,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2020-07-07 11:36:29,953 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:36:29,953 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:36:29,953 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2020-07-07 11:36:29,954 INFO L427 AbstractCegarLoop]: === Iteration 5 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:36:29,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:36:29,956 INFO L82 PathProgramCache]: Analyzing trace with hash 1418466941, now seen corresponding path program 1 times [2020-07-07 11:36:29,956 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:36:29,957 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1728698248] [2020-07-07 11:36:29,957 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:36:29,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:30,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:30,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:30,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:30,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:30,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:30,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:30,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:30,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:30,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:30,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:30,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:30,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-07 11:36:30,275 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1728698248] [2020-07-07 11:36:30,275 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:36:30,275 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2020-07-07 11:36:30,276 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083298079] [2020-07-07 11:36:30,276 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2020-07-07 11:36:30,277 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:36:30,277 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2020-07-07 11:36:30,277 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2020-07-07 11:36:30,277 INFO L87 Difference]: Start difference. First operand 294 states and 379 transitions. Second operand 10 states. [2020-07-07 11:36:32,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:36:32,407 INFO L93 Difference]: Finished difference Result 855 states and 1230 transitions. [2020-07-07 11:36:32,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2020-07-07 11:36:32,413 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 90 [2020-07-07 11:36:32,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:36:32,418 INFO L225 Difference]: With dead ends: 855 [2020-07-07 11:36:32,419 INFO L226 Difference]: Without dead ends: 581 [2020-07-07 11:36:32,422 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 25 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=123, Invalid=297, Unknown=0, NotChecked=0, Total=420 [2020-07-07 11:36:32,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 581 states. [2020-07-07 11:36:32,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 581 to 366. [2020-07-07 11:36:32,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 366 states. [2020-07-07 11:36:32,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 366 states to 366 states and 457 transitions. [2020-07-07 11:36:32,469 INFO L78 Accepts]: Start accepts. Automaton has 366 states and 457 transitions. Word has length 90 [2020-07-07 11:36:32,469 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:36:32,469 INFO L479 AbstractCegarLoop]: Abstraction has 366 states and 457 transitions. [2020-07-07 11:36:32,469 INFO L480 AbstractCegarLoop]: Interpolant automaton has 10 states. [2020-07-07 11:36:32,469 INFO L276 IsEmpty]: Start isEmpty. Operand 366 states and 457 transitions. [2020-07-07 11:36:32,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2020-07-07 11:36:32,472 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:36:32,473 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:36:32,473 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2020-07-07 11:36:32,474 INFO L427 AbstractCegarLoop]: === Iteration 6 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:36:32,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:36:32,474 INFO L82 PathProgramCache]: Analyzing trace with hash 1504622653, now seen corresponding path program 1 times [2020-07-07 11:36:32,475 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:36:32,475 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305277700] [2020-07-07 11:36:32,475 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:36:32,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:32,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:32,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:32,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:32,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:32,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:32,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:32,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:32,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:32,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:32,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:32,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:32,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-07 11:36:32,669 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1305277700] [2020-07-07 11:36:32,669 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:36:32,669 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2020-07-07 11:36:32,669 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2098729927] [2020-07-07 11:36:32,670 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2020-07-07 11:36:32,670 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:36:32,670 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2020-07-07 11:36:32,671 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2020-07-07 11:36:32,671 INFO L87 Difference]: Start difference. First operand 366 states and 457 transitions. Second operand 10 states. [2020-07-07 11:36:34,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:36:34,591 INFO L93 Difference]: Finished difference Result 877 states and 1164 transitions. [2020-07-07 11:36:34,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2020-07-07 11:36:34,591 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 90 [2020-07-07 11:36:34,592 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:36:34,597 INFO L225 Difference]: With dead ends: 877 [2020-07-07 11:36:34,598 INFO L226 Difference]: Without dead ends: 532 [2020-07-07 11:36:34,600 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=84, Invalid=222, Unknown=0, NotChecked=0, Total=306 [2020-07-07 11:36:34,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states. [2020-07-07 11:36:34,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 376. [2020-07-07 11:36:34,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 376 states. [2020-07-07 11:36:34,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 376 states to 376 states and 465 transitions. [2020-07-07 11:36:34,655 INFO L78 Accepts]: Start accepts. Automaton has 376 states and 465 transitions. Word has length 90 [2020-07-07 11:36:34,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:36:34,656 INFO L479 AbstractCegarLoop]: Abstraction has 376 states and 465 transitions. [2020-07-07 11:36:34,656 INFO L480 AbstractCegarLoop]: Interpolant automaton has 10 states. [2020-07-07 11:36:34,657 INFO L276 IsEmpty]: Start isEmpty. Operand 376 states and 465 transitions. [2020-07-07 11:36:34,658 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2020-07-07 11:36:34,659 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:36:34,659 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:36:34,660 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2020-07-07 11:36:34,660 INFO L427 AbstractCegarLoop]: === Iteration 7 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:36:34,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:36:34,661 INFO L82 PathProgramCache]: Analyzing trace with hash -523963457, now seen corresponding path program 1 times [2020-07-07 11:36:34,661 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:36:34,661 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497993857] [2020-07-07 11:36:34,661 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:36:34,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:34,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:34,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:34,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:34,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:34,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:34,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:34,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:34,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:34,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:34,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:34,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:34,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-07 11:36:34,914 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [497993857] [2020-07-07 11:36:34,914 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:36:34,914 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2020-07-07 11:36:34,915 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1840919444] [2020-07-07 11:36:34,915 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2020-07-07 11:36:34,915 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:36:34,916 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2020-07-07 11:36:34,916 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2020-07-07 11:36:34,916 INFO L87 Difference]: Start difference. First operand 376 states and 465 transitions. Second operand 10 states. [2020-07-07 11:36:37,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:36:37,206 INFO L93 Difference]: Finished difference Result 915 states and 1208 transitions. [2020-07-07 11:36:37,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2020-07-07 11:36:37,210 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 90 [2020-07-07 11:36:37,211 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:36:37,221 INFO L225 Difference]: With dead ends: 915 [2020-07-07 11:36:37,221 INFO L226 Difference]: Without dead ends: 560 [2020-07-07 11:36:37,227 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=91, Invalid=251, Unknown=0, NotChecked=0, Total=342 [2020-07-07 11:36:37,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 560 states. [2020-07-07 11:36:37,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 560 to 396. [2020-07-07 11:36:37,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 396 states. [2020-07-07 11:36:37,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 396 states to 396 states and 485 transitions. [2020-07-07 11:36:37,281 INFO L78 Accepts]: Start accepts. Automaton has 396 states and 485 transitions. Word has length 90 [2020-07-07 11:36:37,283 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:36:37,283 INFO L479 AbstractCegarLoop]: Abstraction has 396 states and 485 transitions. [2020-07-07 11:36:37,283 INFO L480 AbstractCegarLoop]: Interpolant automaton has 10 states. [2020-07-07 11:36:37,284 INFO L276 IsEmpty]: Start isEmpty. Operand 396 states and 485 transitions. [2020-07-07 11:36:37,285 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2020-07-07 11:36:37,285 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:36:37,285 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:36:37,286 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2020-07-07 11:36:37,286 INFO L427 AbstractCegarLoop]: === Iteration 8 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:36:37,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:36:37,287 INFO L82 PathProgramCache]: Analyzing trace with hash -275816963, now seen corresponding path program 1 times [2020-07-07 11:36:37,288 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:36:37,289 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022699145] [2020-07-07 11:36:37,290 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:36:37,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:37,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:37,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:37,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:37,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:37,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:37,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:37,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:37,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:37,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:37,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:37,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:37,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-07 11:36:37,573 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1022699145] [2020-07-07 11:36:37,573 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:36:37,574 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2020-07-07 11:36:37,574 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [676387591] [2020-07-07 11:36:37,575 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2020-07-07 11:36:37,576 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:36:37,576 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2020-07-07 11:36:37,577 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2020-07-07 11:36:37,577 INFO L87 Difference]: Start difference. First operand 396 states and 485 transitions. Second operand 10 states. [2020-07-07 11:36:39,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:36:39,506 INFO L93 Difference]: Finished difference Result 939 states and 1222 transitions. [2020-07-07 11:36:39,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2020-07-07 11:36:39,507 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 90 [2020-07-07 11:36:39,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:36:39,512 INFO L225 Difference]: With dead ends: 939 [2020-07-07 11:36:39,512 INFO L226 Difference]: Without dead ends: 564 [2020-07-07 11:36:39,516 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=91, Invalid=251, Unknown=0, NotChecked=0, Total=342 [2020-07-07 11:36:39,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 564 states. [2020-07-07 11:36:39,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 564 to 406. [2020-07-07 11:36:39,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 406 states. [2020-07-07 11:36:39,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 406 states to 406 states and 493 transitions. [2020-07-07 11:36:39,566 INFO L78 Accepts]: Start accepts. Automaton has 406 states and 493 transitions. Word has length 90 [2020-07-07 11:36:39,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:36:39,566 INFO L479 AbstractCegarLoop]: Abstraction has 406 states and 493 transitions. [2020-07-07 11:36:39,567 INFO L480 AbstractCegarLoop]: Interpolant automaton has 10 states. [2020-07-07 11:36:39,567 INFO L276 IsEmpty]: Start isEmpty. Operand 406 states and 493 transitions. [2020-07-07 11:36:39,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2020-07-07 11:36:39,568 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:36:39,568 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:36:39,568 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2020-07-07 11:36:39,568 INFO L427 AbstractCegarLoop]: === Iteration 9 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:36:39,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:36:39,569 INFO L82 PathProgramCache]: Analyzing trace with hash -348203521, now seen corresponding path program 1 times [2020-07-07 11:36:39,569 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:36:39,569 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265688140] [2020-07-07 11:36:39,569 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:36:39,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:39,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:39,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:39,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:39,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:39,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:39,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:39,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:39,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:39,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:39,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:39,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:39,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-07 11:36:39,818 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265688140] [2020-07-07 11:36:39,819 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:36:39,820 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2020-07-07 11:36:39,829 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101919185] [2020-07-07 11:36:39,830 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2020-07-07 11:36:39,833 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:36:39,833 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2020-07-07 11:36:39,837 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2020-07-07 11:36:39,838 INFO L87 Difference]: Start difference. First operand 406 states and 493 transitions. Second operand 10 states. [2020-07-07 11:36:42,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:36:42,226 INFO L93 Difference]: Finished difference Result 1144 states and 1493 transitions. [2020-07-07 11:36:42,226 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2020-07-07 11:36:42,226 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 90 [2020-07-07 11:36:42,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:36:42,235 INFO L225 Difference]: With dead ends: 1144 [2020-07-07 11:36:42,236 INFO L226 Difference]: Without dead ends: 758 [2020-07-07 11:36:42,238 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 28 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 116 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=161, Invalid=439, Unknown=0, NotChecked=0, Total=600 [2020-07-07 11:36:42,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 758 states. [2020-07-07 11:36:42,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 758 to 467. [2020-07-07 11:36:42,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 467 states. [2020-07-07 11:36:42,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 467 states to 467 states and 547 transitions. [2020-07-07 11:36:42,336 INFO L78 Accepts]: Start accepts. Automaton has 467 states and 547 transitions. Word has length 90 [2020-07-07 11:36:42,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:36:42,337 INFO L479 AbstractCegarLoop]: Abstraction has 467 states and 547 transitions. [2020-07-07 11:36:42,337 INFO L480 AbstractCegarLoop]: Interpolant automaton has 10 states. [2020-07-07 11:36:42,337 INFO L276 IsEmpty]: Start isEmpty. Operand 467 states and 547 transitions. [2020-07-07 11:36:42,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2020-07-07 11:36:42,340 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:36:42,341 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:36:42,341 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2020-07-07 11:36:42,341 INFO L427 AbstractCegarLoop]: === Iteration 10 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:36:42,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:36:42,341 INFO L82 PathProgramCache]: Analyzing trace with hash -286163907, now seen corresponding path program 1 times [2020-07-07 11:36:42,342 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:36:42,342 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462406894] [2020-07-07 11:36:42,342 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:36:42,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:42,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:42,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:42,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:42,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:42,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:42,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:42,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:42,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:42,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:42,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:42,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:42,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-07 11:36:42,516 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1462406894] [2020-07-07 11:36:42,516 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:36:42,516 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2020-07-07 11:36:42,516 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440195367] [2020-07-07 11:36:42,517 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2020-07-07 11:36:42,517 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:36:42,517 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2020-07-07 11:36:42,517 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2020-07-07 11:36:42,518 INFO L87 Difference]: Start difference. First operand 467 states and 547 transitions. Second operand 7 states. [2020-07-07 11:36:44,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:36:44,517 INFO L93 Difference]: Finished difference Result 1503 states and 1877 transitions. [2020-07-07 11:36:44,517 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2020-07-07 11:36:44,518 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 90 [2020-07-07 11:36:44,519 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:36:44,529 INFO L225 Difference]: With dead ends: 1503 [2020-07-07 11:36:44,530 INFO L226 Difference]: Without dead ends: 1058 [2020-07-07 11:36:44,534 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=60, Invalid=122, Unknown=0, NotChecked=0, Total=182 [2020-07-07 11:36:44,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1058 states. [2020-07-07 11:36:44,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1058 to 847. [2020-07-07 11:36:44,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 847 states. [2020-07-07 11:36:44,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 847 states to 847 states and 1018 transitions. [2020-07-07 11:36:44,670 INFO L78 Accepts]: Start accepts. Automaton has 847 states and 1018 transitions. Word has length 90 [2020-07-07 11:36:44,673 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:36:44,673 INFO L479 AbstractCegarLoop]: Abstraction has 847 states and 1018 transitions. [2020-07-07 11:36:44,673 INFO L480 AbstractCegarLoop]: Interpolant automaton has 7 states. [2020-07-07 11:36:44,673 INFO L276 IsEmpty]: Start isEmpty. Operand 847 states and 1018 transitions. [2020-07-07 11:36:44,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2020-07-07 11:36:44,676 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:36:44,676 INFO L422 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:36:44,676 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2020-07-07 11:36:44,676 INFO L427 AbstractCegarLoop]: === Iteration 11 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:36:44,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:36:44,677 INFO L82 PathProgramCache]: Analyzing trace with hash 1417763379, now seen corresponding path program 1 times [2020-07-07 11:36:44,677 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:36:44,678 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [685287421] [2020-07-07 11:36:44,678 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:36:44,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:44,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:44,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:44,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:44,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:44,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:44,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:44,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:44,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:44,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:44,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:44,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:44,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-07-07 11:36:44,913 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [685287421] [2020-07-07 11:36:44,913 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:36:44,914 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2020-07-07 11:36:44,914 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1211047530] [2020-07-07 11:36:44,914 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2020-07-07 11:36:44,915 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:36:44,915 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2020-07-07 11:36:44,916 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2020-07-07 11:36:44,916 INFO L87 Difference]: Start difference. First operand 847 states and 1018 transitions. Second operand 7 states. [2020-07-07 11:36:46,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:36:46,976 INFO L93 Difference]: Finished difference Result 2813 states and 3701 transitions. [2020-07-07 11:36:46,977 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2020-07-07 11:36:46,977 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 91 [2020-07-07 11:36:46,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:36:46,991 INFO L225 Difference]: With dead ends: 2813 [2020-07-07 11:36:46,991 INFO L226 Difference]: Without dead ends: 1993 [2020-07-07 11:36:46,999 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 27 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=60, Invalid=122, Unknown=0, NotChecked=0, Total=182 [2020-07-07 11:36:47,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1993 states. [2020-07-07 11:36:47,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1993 to 1710. [2020-07-07 11:36:47,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1710 states. [2020-07-07 11:36:47,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1710 states to 1710 states and 2141 transitions. [2020-07-07 11:36:47,214 INFO L78 Accepts]: Start accepts. Automaton has 1710 states and 2141 transitions. Word has length 91 [2020-07-07 11:36:47,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:36:47,214 INFO L479 AbstractCegarLoop]: Abstraction has 1710 states and 2141 transitions. [2020-07-07 11:36:47,214 INFO L480 AbstractCegarLoop]: Interpolant automaton has 7 states. [2020-07-07 11:36:47,215 INFO L276 IsEmpty]: Start isEmpty. Operand 1710 states and 2141 transitions. [2020-07-07 11:36:47,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2020-07-07 11:36:47,219 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:36:47,219 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:36:47,219 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2020-07-07 11:36:47,219 INFO L427 AbstractCegarLoop]: === Iteration 12 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:36:47,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:36:47,220 INFO L82 PathProgramCache]: Analyzing trace with hash 1387972843, now seen corresponding path program 1 times [2020-07-07 11:36:47,220 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:36:47,221 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007342242] [2020-07-07 11:36:47,221 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:36:47,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:47,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:47,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:47,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:47,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:47,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:47,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:47,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:47,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:47,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:47,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:47,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:47,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:47,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:47,430 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2020-07-07 11:36:47,431 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1007342242] [2020-07-07 11:36:47,431 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:36:47,431 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2020-07-07 11:36:47,432 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1491132913] [2020-07-07 11:36:47,433 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2020-07-07 11:36:47,433 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:36:47,434 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2020-07-07 11:36:47,434 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2020-07-07 11:36:47,434 INFO L87 Difference]: Start difference. First operand 1710 states and 2141 transitions. Second operand 9 states. [2020-07-07 11:36:49,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:36:49,317 INFO L93 Difference]: Finished difference Result 3845 states and 5084 transitions. [2020-07-07 11:36:49,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2020-07-07 11:36:49,317 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 111 [2020-07-07 11:36:49,317 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:36:49,332 INFO L225 Difference]: With dead ends: 3845 [2020-07-07 11:36:49,333 INFO L226 Difference]: Without dead ends: 2157 [2020-07-07 11:36:49,340 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=80, Invalid=192, Unknown=0, NotChecked=0, Total=272 [2020-07-07 11:36:49,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2157 states. [2020-07-07 11:36:49,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2157 to 1767. [2020-07-07 11:36:49,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1767 states. [2020-07-07 11:36:49,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1767 states to 1767 states and 2232 transitions. [2020-07-07 11:36:49,608 INFO L78 Accepts]: Start accepts. Automaton has 1767 states and 2232 transitions. Word has length 111 [2020-07-07 11:36:49,608 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:36:49,608 INFO L479 AbstractCegarLoop]: Abstraction has 1767 states and 2232 transitions. [2020-07-07 11:36:49,608 INFO L480 AbstractCegarLoop]: Interpolant automaton has 9 states. [2020-07-07 11:36:49,608 INFO L276 IsEmpty]: Start isEmpty. Operand 1767 states and 2232 transitions. [2020-07-07 11:36:49,610 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2020-07-07 11:36:49,610 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:36:49,610 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:36:49,611 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2020-07-07 11:36:49,611 INFO L427 AbstractCegarLoop]: === Iteration 13 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:36:49,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:36:49,612 INFO L82 PathProgramCache]: Analyzing trace with hash 36587625, now seen corresponding path program 1 times [2020-07-07 11:36:49,612 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:36:49,612 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [472925857] [2020-07-07 11:36:49,612 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:36:49,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:49,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:49,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:49,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:49,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:49,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:49,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:49,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:49,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:49,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:49,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:49,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:49,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:49,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:49,827 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2020-07-07 11:36:49,827 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [472925857] [2020-07-07 11:36:49,827 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:36:49,827 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2020-07-07 11:36:49,828 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [358272915] [2020-07-07 11:36:49,828 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2020-07-07 11:36:49,828 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:36:49,829 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2020-07-07 11:36:49,829 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2020-07-07 11:36:49,829 INFO L87 Difference]: Start difference. First operand 1767 states and 2232 transitions. Second operand 8 states. [2020-07-07 11:36:52,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:36:52,679 INFO L93 Difference]: Finished difference Result 5835 states and 7942 transitions. [2020-07-07 11:36:52,680 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2020-07-07 11:36:52,681 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 111 [2020-07-07 11:36:52,681 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:36:52,714 INFO L225 Difference]: With dead ends: 5835 [2020-07-07 11:36:52,714 INFO L226 Difference]: Without dead ends: 3120 [2020-07-07 11:36:52,735 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 34 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=106, Invalid=236, Unknown=0, NotChecked=0, Total=342 [2020-07-07 11:36:52,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3120 states. [2020-07-07 11:36:53,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3120 to 2788. [2020-07-07 11:36:53,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2788 states. [2020-07-07 11:36:53,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2788 states to 2788 states and 3646 transitions. [2020-07-07 11:36:53,228 INFO L78 Accepts]: Start accepts. Automaton has 2788 states and 3646 transitions. Word has length 111 [2020-07-07 11:36:53,228 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:36:53,228 INFO L479 AbstractCegarLoop]: Abstraction has 2788 states and 3646 transitions. [2020-07-07 11:36:53,228 INFO L480 AbstractCegarLoop]: Interpolant automaton has 8 states. [2020-07-07 11:36:53,228 INFO L276 IsEmpty]: Start isEmpty. Operand 2788 states and 3646 transitions. [2020-07-07 11:36:53,234 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2020-07-07 11:36:53,234 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:36:53,234 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:36:53,235 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2020-07-07 11:36:53,235 INFO L427 AbstractCegarLoop]: === Iteration 14 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:36:53,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:36:53,235 INFO L82 PathProgramCache]: Analyzing trace with hash -1178118941, now seen corresponding path program 1 times [2020-07-07 11:36:53,235 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:36:53,245 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681472190] [2020-07-07 11:36:53,246 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:36:53,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:53,577 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2020-07-07 11:36:53,579 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1681472190] [2020-07-07 11:36:53,579 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:36:53,580 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2020-07-07 11:36:53,580 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [636957631] [2020-07-07 11:36:53,581 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2020-07-07 11:36:53,582 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:36:53,583 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2020-07-07 11:36:53,583 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2020-07-07 11:36:53,583 INFO L87 Difference]: Start difference. First operand 2788 states and 3646 transitions. Second operand 9 states. [2020-07-07 11:36:57,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:36:57,200 INFO L93 Difference]: Finished difference Result 8089 states and 11637 transitions. [2020-07-07 11:36:57,201 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2020-07-07 11:36:57,201 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 155 [2020-07-07 11:36:57,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:36:57,249 INFO L225 Difference]: With dead ends: 8089 [2020-07-07 11:36:57,249 INFO L226 Difference]: Without dead ends: 5323 [2020-07-07 11:36:57,279 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 44 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=125, Invalid=295, Unknown=0, NotChecked=0, Total=420 [2020-07-07 11:36:57,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5323 states. [2020-07-07 11:36:58,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5323 to 4852. [2020-07-07 11:36:58,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4852 states. [2020-07-07 11:36:58,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4852 states to 4852 states and 6633 transitions. [2020-07-07 11:36:58,354 INFO L78 Accepts]: Start accepts. Automaton has 4852 states and 6633 transitions. Word has length 155 [2020-07-07 11:36:58,354 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:36:58,355 INFO L479 AbstractCegarLoop]: Abstraction has 4852 states and 6633 transitions. [2020-07-07 11:36:58,355 INFO L480 AbstractCegarLoop]: Interpolant automaton has 9 states. [2020-07-07 11:36:58,355 INFO L276 IsEmpty]: Start isEmpty. Operand 4852 states and 6633 transitions. [2020-07-07 11:36:58,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2020-07-07 11:36:58,366 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:36:58,366 INFO L422 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:36:58,367 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2020-07-07 11:36:58,367 INFO L427 AbstractCegarLoop]: === Iteration 15 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:36:58,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:36:58,368 INFO L82 PathProgramCache]: Analyzing trace with hash -390866386, now seen corresponding path program 1 times [2020-07-07 11:36:58,369 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:36:58,369 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1977036824] [2020-07-07 11:36:58,370 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:36:58,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:36:58,798 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2020-07-07 11:36:58,799 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1977036824] [2020-07-07 11:36:58,799 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:36:58,800 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2020-07-07 11:36:58,800 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1969528214] [2020-07-07 11:36:58,801 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2020-07-07 11:36:58,802 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:36:58,802 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2020-07-07 11:36:58,802 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2020-07-07 11:36:58,803 INFO L87 Difference]: Start difference. First operand 4852 states and 6633 transitions. Second operand 10 states. [2020-07-07 11:37:03,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:37:03,019 INFO L93 Difference]: Finished difference Result 12975 states and 19533 transitions. [2020-07-07 11:37:03,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2020-07-07 11:37:03,020 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 156 [2020-07-07 11:37:03,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:37:03,077 INFO L225 Difference]: With dead ends: 12975 [2020-07-07 11:37:03,077 INFO L226 Difference]: Without dead ends: 6726 [2020-07-07 11:37:03,136 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 47 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 105 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=137, Invalid=415, Unknown=0, NotChecked=0, Total=552 [2020-07-07 11:37:03,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6726 states. [2020-07-07 11:37:04,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6726 to 6174. [2020-07-07 11:37:04,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6174 states. [2020-07-07 11:37:04,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6174 states to 6174 states and 8297 transitions. [2020-07-07 11:37:04,170 INFO L78 Accepts]: Start accepts. Automaton has 6174 states and 8297 transitions. Word has length 156 [2020-07-07 11:37:04,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:37:04,173 INFO L479 AbstractCegarLoop]: Abstraction has 6174 states and 8297 transitions. [2020-07-07 11:37:04,173 INFO L480 AbstractCegarLoop]: Interpolant automaton has 10 states. [2020-07-07 11:37:04,173 INFO L276 IsEmpty]: Start isEmpty. Operand 6174 states and 8297 transitions. [2020-07-07 11:37:04,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 208 [2020-07-07 11:37:04,186 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:37:04,187 INFO L422 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:37:04,188 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2020-07-07 11:37:04,188 INFO L427 AbstractCegarLoop]: === Iteration 16 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:37:04,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:37:04,189 INFO L82 PathProgramCache]: Analyzing trace with hash -1382123670, now seen corresponding path program 1 times [2020-07-07 11:37:04,189 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:37:04,189 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1690261823] [2020-07-07 11:37:04,189 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:37:04,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-07-07 11:37:04,644 INFO L134 CoverageAnalysis]: Checked inductivity of 114 backedges. 41 proven. 0 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2020-07-07 11:37:04,645 INFO L354 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1690261823] [2020-07-07 11:37:04,649 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-07-07 11:37:04,650 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2020-07-07 11:37:04,650 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442668880] [2020-07-07 11:37:04,652 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2020-07-07 11:37:04,653 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-07-07 11:37:04,653 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2020-07-07 11:37:04,654 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2020-07-07 11:37:04,654 INFO L87 Difference]: Start difference. First operand 6174 states and 8297 transitions. Second operand 11 states. [2020-07-07 11:37:08,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-07-07 11:37:08,194 INFO L93 Difference]: Finished difference Result 12270 states and 16979 transitions. [2020-07-07 11:37:08,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2020-07-07 11:37:08,195 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 207 [2020-07-07 11:37:08,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2020-07-07 11:37:08,215 INFO L225 Difference]: With dead ends: 12270 [2020-07-07 11:37:08,215 INFO L226 Difference]: Without dead ends: 3143 [2020-07-07 11:37:08,244 INFO L675 BasicCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 125 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=158, Invalid=492, Unknown=0, NotChecked=0, Total=650 [2020-07-07 11:37:08,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3143 states. [2020-07-07 11:37:08,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3143 to 2950. [2020-07-07 11:37:08,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2950 states. [2020-07-07 11:37:08,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2950 states to 2950 states and 3443 transitions. [2020-07-07 11:37:08,511 INFO L78 Accepts]: Start accepts. Automaton has 2950 states and 3443 transitions. Word has length 207 [2020-07-07 11:37:08,511 INFO L84 Accepts]: Finished accepts. word is rejected. [2020-07-07 11:37:08,511 INFO L479 AbstractCegarLoop]: Abstraction has 2950 states and 3443 transitions. [2020-07-07 11:37:08,511 INFO L480 AbstractCegarLoop]: Interpolant automaton has 11 states. [2020-07-07 11:37:08,512 INFO L276 IsEmpty]: Start isEmpty. Operand 2950 states and 3443 transitions. [2020-07-07 11:37:08,517 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 209 [2020-07-07 11:37:08,517 INFO L414 BasicCegarLoop]: Found error trace [2020-07-07 11:37:08,517 INFO L422 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-07-07 11:37:08,517 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2020-07-07 11:37:08,518 INFO L427 AbstractCegarLoop]: === Iteration 17 === [errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2020-07-07 11:37:08,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-07-07 11:37:08,518 INFO L82 PathProgramCache]: Analyzing trace with hash 89354437, now seen corresponding path program 1 times [2020-07-07 11:37:08,519 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-07-07 11:37:08,519 INFO L354 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [602203958] [2020-07-07 11:37:08,519 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-07-07 11:37:08,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-07 11:37:08,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-07-07 11:37:08,668 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-07-07 11:37:08,669 INFO L520 BasicCegarLoop]: Counterexample might be feasible [2020-07-07 11:37:08,669 WARN L516 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2020-07-07 11:37:08,884 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.07 11:37:08 BoogieIcfgContainer [2020-07-07 11:37:08,884 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2020-07-07 11:37:08,887 INFO L168 Benchmark]: Toolchain (without parser) took 50517.06 ms. Allocated memory was 135.8 MB in the beginning and 753.9 MB in the end (delta: 618.1 MB). Free memory was 100.1 MB in the beginning and 305.0 MB in the end (delta: -204.9 MB). Peak memory consumption was 413.3 MB. Max. memory is 7.1 GB. [2020-07-07 11:37:08,890 INFO L168 Benchmark]: CDTParser took 0.23 ms. Allocated memory is still 135.8 MB. Free memory was 118.9 MB in the beginning and 118.7 MB in the end (delta: 209.9 kB). Peak memory consumption was 209.9 kB. Max. memory is 7.1 GB. [2020-07-07 11:37:08,893 INFO L168 Benchmark]: CACSL2BoogieTranslator took 650.89 ms. Allocated memory was 135.8 MB in the beginning and 201.9 MB in the end (delta: 66.1 MB). Free memory was 99.9 MB in the beginning and 177.4 MB in the end (delta: -77.5 MB). Peak memory consumption was 24.8 MB. Max. memory is 7.1 GB. [2020-07-07 11:37:08,897 INFO L168 Benchmark]: Boogie Preprocessor took 57.55 ms. Allocated memory is still 201.9 MB. Free memory was 177.4 MB in the beginning and 175.3 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 7.1 GB. [2020-07-07 11:37:08,898 INFO L168 Benchmark]: RCFGBuilder took 755.74 ms. Allocated memory is still 201.9 MB. Free memory was 175.3 MB in the beginning and 139.6 MB in the end (delta: 35.6 MB). Peak memory consumption was 35.6 MB. Max. memory is 7.1 GB. [2020-07-07 11:37:08,902 INFO L168 Benchmark]: TraceAbstraction took 49037.66 ms. Allocated memory was 201.9 MB in the beginning and 753.9 MB in the end (delta: 552.1 MB). Free memory was 138.9 MB in the beginning and 305.0 MB in the end (delta: -166.1 MB). Peak memory consumption was 386.0 MB. Max. memory is 7.1 GB. [2020-07-07 11:37:08,907 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.23 ms. Allocated memory is still 135.8 MB. Free memory was 118.9 MB in the beginning and 118.7 MB in the end (delta: 209.9 kB). Peak memory consumption was 209.9 kB. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 650.89 ms. Allocated memory was 135.8 MB in the beginning and 201.9 MB in the end (delta: 66.1 MB). Free memory was 99.9 MB in the beginning and 177.4 MB in the end (delta: -77.5 MB). Peak memory consumption was 24.8 MB. Max. memory is 7.1 GB. * Boogie Preprocessor took 57.55 ms. Allocated memory is still 201.9 MB. Free memory was 177.4 MB in the beginning and 175.3 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 7.1 GB. * RCFGBuilder took 755.74 ms. Allocated memory is still 201.9 MB. Free memory was 175.3 MB in the beginning and 139.6 MB in the end (delta: 35.6 MB). Peak memory consumption was 35.6 MB. Max. memory is 7.1 GB. * TraceAbstraction took 49037.66 ms. Allocated memory was 201.9 MB in the beginning and 753.9 MB in the end (delta: 552.1 MB). Free memory was 138.9 MB in the beginning and 305.0 MB in the end (delta: -166.1 MB). Peak memory consumption was 386.0 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 11]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int m_st ; [L19] int t1_st ; [L20] int t2_st ; [L21] int m_i ; [L22] int t1_i ; [L23] int t2_i ; [L24] int M_E = 2; [L25] int T1_E = 2; [L26] int T2_E = 2; [L27] int E_1 = 2; [L28] int E_2 = 2; VAL [\old(E_1)=17, \old(E_2)=6, \old(M_E)=14, \old(m_i)=8, \old(m_pc)=12, \old(m_st)=13, \old(T1_E)=4, \old(t1_i)=16, \old(t1_pc)=9, \old(t1_st)=5, \old(T2_E)=15, \old(t2_i)=7, \old(t2_pc)=10, \old(t2_st)=11, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L563] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L567] CALL init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, T2_E=2, t2_i=0, t2_pc=0, t2_st=0] [L477] m_i = 1 [L478] t1_i = 1 [L479] t2_i = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L567] RET init_model() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L568] CALL start_simulation() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L504] int kernel_st ; [L505] int tmp ; [L506] int tmp___0 ; [L510] kernel_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L511] FCALL update_channels() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L512] CALL init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L211] COND TRUE m_i == 1 [L212] m_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L216] COND TRUE t1_i == 1 [L217] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L221] COND TRUE t2_i == 1 [L222] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L512] RET init_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L513] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L324] COND FALSE !(M_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L329] COND FALSE !(T1_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L334] COND FALSE !(T2_E == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(E_1 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(E_2 == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L513] RET fire_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L514] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L146] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L158] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L165] COND FALSE !(t1_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L175] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L177] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L401] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L184] COND FALSE !(t2_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L194] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L196] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=0, __retres1=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L409] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0] [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=0, tmp___0=0, tmp___1=0] [L514] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L515] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L357] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L362] COND FALSE !(T1_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L367] COND FALSE !(T2_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L515] RET reset_delta_events() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L518] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L521] kernel_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, kernel_st=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L522] CALL eval() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L257] int tmp ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L261] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L231] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L252] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1] [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND FALSE !(\read(tmp_ndt_1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0] [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND TRUE \read(tmp_ndt_2) [L290] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=-1] [L291] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L78] COND TRUE t1_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L89] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=1, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L91] t1_pc = 1 [L92] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0] [L291] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, tmp=1, tmp_ndt_1=0, tmp_ndt_2=-1] [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND TRUE \read(tmp_ndt_3) [L304] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1, tmp=1, tmp_ndt_1=0, tmp_ndt_2=-1, tmp_ndt_3=1] [L305] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L113] COND TRUE t2_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L124] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=0, t2_st=1] [L126] t2_pc = 1 [L127] t2_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L305] RET transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=-1, tmp_ndt_3=1] [L261] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=-1, tmp_ndt_3=1] [L264] CALL, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L231] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L252] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, \result=1, __retres1=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L264] RET, EXPR exists_runnable_thread() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=-1, tmp_ndt_3=1] [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=0, tmp_ndt_2=-1, tmp_ndt_3=1] [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND TRUE \read(tmp_ndt_1) [L276] m_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=-2, tmp_ndt_2=-1, tmp_ndt_3=1] [L277] CALL master() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L37] COND TRUE m_pc == 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L48] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L51] E_1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L52] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L425] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L146] COND FALSE !(m_pc == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L158] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_master_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L165] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L166] COND TRUE E_1 == 1 [L167] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=1, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L177] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=1, __retres1=1, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L401] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_transmit1_triggered()=1, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND TRUE \read(tmp___0) [L404] t1_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L184] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L185] COND FALSE !(E_2 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L194] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L196] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L409] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, is_transmit2_triggered()=0, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1] [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE !(\read(tmp___1)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=1, tmp___1=0] [L425] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L52] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=1, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L53] E_1 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L56] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=0, m_st=1, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L58] m_pc = 1 [L59] m_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=1, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=2, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L277] RET master() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=0, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=-2, tmp_ndt_2=-1, tmp_ndt_3=1] [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND TRUE \read(tmp_ndt_2) [L290] t1_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=1, tmp_ndt_1=-2, tmp_ndt_2=3, tmp_ndt_3=1] [L291] CALL transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L78] COND FALSE !(t1_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L81] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L97] E_2 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L98] CALL immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L425] CALL activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] CALL, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L143] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L146] COND TRUE m_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L147] COND FALSE !(M_E == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L156] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L158] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] RET, EXPR is_master_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_master_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] CALL, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L162] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L165] COND TRUE t1_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L166] COND FALSE !(E_1 == 1) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L175] __retres1 = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L177] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=0, __retres1=0, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L401] RET, EXPR is_transmit1_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_transmit1_triggered()=0, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0] [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=0] [L409] CALL, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L181] int __retres1 ; VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L184] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L185] COND TRUE E_2 == 1 [L186] __retres1 = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, __retres1=1, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L196] return (__retres1); VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, \result=1, __retres1=1, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2] [L409] RET, EXPR is_transmit2_triggered() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, is_transmit2_triggered()=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=2, tmp=0, tmp___0=0] [L409] tmp___1 = is_transmit2_triggered() [L411] COND TRUE \read(tmp___1) [L412] t2_st = 0 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, tmp=0, tmp___0=0, tmp___1=1] [L425] RET activate_threads() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L98] RET immediate_notify() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=1, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L99] E_2 = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L89] COND TRUE 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=1, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L91] t1_pc = 1 [L92] t1_st = 2 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=2, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=1, \old(t1_st)=1, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=2, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0] [L291] RET transmit1() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=0, tmp=1, tmp_ndt_1=-2, tmp_ndt_2=3, tmp_ndt_3=1] [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND TRUE \read(tmp_ndt_3) [L304] t2_st = 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=0, \old(t2_st)=0, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1, tmp=1, tmp_ndt_1=-2, tmp_ndt_2=3, tmp_ndt_3=1] [L305] CALL transmit2() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L113] COND FALSE !(t2_pc == 0) VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L116] COND TRUE t2_pc == 1 VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L132] CALL error() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] [L11] __VERIFIER_error() VAL [\old(E_1)=2, \old(E_2)=2, \old(M_E)=2, \old(m_i)=0, \old(m_pc)=0, \old(m_st)=0, \old(T1_E)=2, \old(t1_i)=0, \old(t1_pc)=0, \old(t1_st)=0, \old(T2_E)=2, \old(t2_i)=0, \old(t2_pc)=1, \old(t2_st)=1, E_1=2, E_2=2, M_E=2, m_i=1, m_pc=1, m_st=2, T1_E=2, t1_i=1, t1_pc=1, t1_st=2, T2_E=2, t2_i=1, t2_pc=1, t2_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 23 procedures, 169 locations, 1 error locations. Started 1 CEGAR loops. VerificationResult: UNSAFE, OverallTime: 48.7s, OverallIterations: 17, TraceHistogramMax: 3, AutomataDifference: 39.2s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 2605 SDtfs, 11531 SDslu, 735 SDs, 0 SdLazy, 15801 SolverSat, 5841 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 23.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 756 GetRequests, 486 SyntacticMatches, 2 SemanticMatches, 268 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 797 ImplicationChecksByTransitivity, 6.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=6174occurred in iteration=15, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 4.0s AutomataMinimizationTime, 16 MinimizatonAttempts, 3916 StatesRemovedByMinimization, 16 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 3.9s InterpolantComputationTime, 1939 NumberOfCodeBlocks, 1939 NumberOfCodeBlocksAsserted, 17 NumberOfCheckSat, 1715 ConstructedInterpolants, 0 QuantifiedInterpolants, 487945 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 16 InterpolantComputations, 16 PerfectInterpolantSequences, 237/237 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...