java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml -s ../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf -i ../../../trunk/examples/programs/heapseparator/speedup-poc-dd-3-limited.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.24-f57a05f [2019-01-07 22:10:16,612 INFO L170 SettingsManager]: Resetting all preferences to default values... [2019-01-07 22:10:16,614 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2019-01-07 22:10:16,627 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2019-01-07 22:10:16,660 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf [2019-01-07 22:10:16,674 INFO L110 SettingsManager]: Loading preferences was successful [2019-01-07 22:10:16,674 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2019-01-07 22:10:16,675 INFO L131 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2019-01-07 22:10:16,675 INFO L133 SettingsManager]: * Show backtranslation warnings=false [2019-01-07 22:10:16,675 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-01-07 22:10:16,675 INFO L133 SettingsManager]: * User list type=DISABLED [2019-01-07 22:10:16,675 INFO L133 SettingsManager]: * Inline calls to unimplemented procedures=true [2019-01-07 22:10:16,676 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-01-07 22:10:16,676 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-01-07 22:10:16,676 INFO L133 SettingsManager]: * Underlying domain=OctagonDomain [2019-01-07 22:10:16,676 INFO L133 SettingsManager]: * Abstract domain=ArrayDomain [2019-01-07 22:10:16,676 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-01-07 22:10:16,677 INFO L133 SettingsManager]: * Interval Domain=false [2019-01-07 22:10:16,677 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-01-07 22:10:16,677 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2019-01-07 22:10:16,678 INFO L133 SettingsManager]: * Use SBE=true [2019-01-07 22:10:16,678 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-01-07 22:10:16,678 INFO L133 SettingsManager]: * sizeof long=4 [2019-01-07 22:10:16,678 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2019-01-07 22:10:16,679 INFO L133 SettingsManager]: * sizeof POINTER=4 [2019-01-07 22:10:16,679 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2019-01-07 22:10:16,679 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-01-07 22:10:16,679 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-01-07 22:10:16,679 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-01-07 22:10:16,680 INFO L133 SettingsManager]: * sizeof long double=12 [2019-01-07 22:10:16,680 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2019-01-07 22:10:16,680 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-01-07 22:10:16,680 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-01-07 22:10:16,680 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-01-07 22:10:16,681 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2019-01-07 22:10:16,681 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-01-07 22:10:16,681 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-01-07 22:10:16,681 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-01-07 22:10:16,681 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-01-07 22:10:16,682 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2019-01-07 22:10:16,682 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-01-07 22:10:16,682 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-01-07 22:10:16,682 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-01-07 22:10:16,682 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2019-01-07 22:10:16,719 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-01-07 22:10:16,734 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-01-07 22:10:16,738 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-01-07 22:10:16,740 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2019-01-07 22:10:16,740 INFO L276 PluginConnector]: Boogie PL CUP Parser initialized [2019-01-07 22:10:16,741 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-3-limited.bpl [2019-01-07 22:10:16,742 INFO L111 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-3-limited.bpl' [2019-01-07 22:10:16,781 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-01-07 22:10:16,783 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-01-07 22:10:16,784 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-01-07 22:10:16,784 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-01-07 22:10:16,784 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2019-01-07 22:10:16,801 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 07.01 10:10:16" (1/1) ... [2019-01-07 22:10:16,814 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 07.01 10:10:16" (1/1) ... [2019-01-07 22:10:16,837 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-01-07 22:10:16,838 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-01-07 22:10:16,838 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-01-07 22:10:16,838 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2019-01-07 22:10:16,850 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 07.01 10:10:16" (1/1) ... [2019-01-07 22:10:16,850 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 07.01 10:10:16" (1/1) ... [2019-01-07 22:10:16,851 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 07.01 10:10:16" (1/1) ... [2019-01-07 22:10:16,852 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 07.01 10:10:16" (1/1) ... [2019-01-07 22:10:16,855 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 07.01 10:10:16" (1/1) ... [2019-01-07 22:10:16,859 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 07.01 10:10:16" (1/1) ... [2019-01-07 22:10:16,860 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 07.01 10:10:16" (1/1) ... [2019-01-07 22:10:16,861 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-01-07 22:10:16,862 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-01-07 22:10:16,862 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-01-07 22:10:16,862 INFO L276 PluginConnector]: RCFGBuilder initialized [2019-01-07 22:10:16,863 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 07.01 10:10:16" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-01-07 22:10:16,922 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-01-07 22:10:16,922 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-01-07 22:10:17,201 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-01-07 22:10:17,201 INFO L286 CfgBuilder]: Removed 9 assue(true) statements. [2019-01-07 22:10:17,202 INFO L202 PluginConnector]: Adding new model speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.01 10:10:17 BoogieIcfgContainer [2019-01-07 22:10:17,203 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-01-07 22:10:17,204 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-01-07 22:10:17,204 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-01-07 22:10:17,207 INFO L276 PluginConnector]: TraceAbstraction initialized [2019-01-07 22:10:17,207 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 07.01 10:10:16" (1/2) ... [2019-01-07 22:10:17,208 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@d73f8c and model type speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.01 10:10:17, skipping insertion in model container [2019-01-07 22:10:17,209 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.01 10:10:17" (2/2) ... [2019-01-07 22:10:17,210 INFO L112 eAbstractionObserver]: Analyzing ICFG speedup-poc-dd-3-limited.bpl [2019-01-07 22:10:17,221 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-01-07 22:10:17,232 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2019-01-07 22:10:17,253 INFO L257 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2019-01-07 22:10:17,296 INFO L382 AbstractCegarLoop]: Interprodecural is true [2019-01-07 22:10:17,296 INFO L383 AbstractCegarLoop]: Hoare is true [2019-01-07 22:10:17,296 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-01-07 22:10:17,296 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-01-07 22:10:17,297 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-01-07 22:10:17,297 INFO L387 AbstractCegarLoop]: Difference is false [2019-01-07 22:10:17,297 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-01-07 22:10:17,298 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-01-07 22:10:17,313 INFO L276 IsEmpty]: Start isEmpty. Operand 9 states. [2019-01-07 22:10:17,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3 [2019-01-07 22:10:17,319 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:10:17,320 INFO L402 BasicCegarLoop]: trace histogram [1, 1] [2019-01-07 22:10:17,323 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:10:17,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:10:17,330 INFO L82 PathProgramCache]: Analyzing trace with hash 976, now seen corresponding path program 1 times [2019-01-07 22:10:17,333 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:10:17,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:10:17,382 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:10:17,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:10:17,382 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:10:17,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:10:17,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:10:17,516 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-07 22:10:17,516 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-07 22:10:17,516 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:10:17,524 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-07 22:10:17,541 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-07 22:10:17,542 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-07 22:10:17,545 INFO L87 Difference]: Start difference. First operand 9 states. Second operand 3 states. [2019-01-07 22:10:17,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:10:17,747 INFO L93 Difference]: Finished difference Result 17 states and 21 transitions. [2019-01-07 22:10:17,748 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-07 22:10:17,749 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 2 [2019-01-07 22:10:17,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:10:17,762 INFO L225 Difference]: With dead ends: 17 [2019-01-07 22:10:17,763 INFO L226 Difference]: Without dead ends: 12 [2019-01-07 22:10:17,766 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-07 22:10:17,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states. [2019-01-07 22:10:17,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 8. [2019-01-07 22:10:17,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8 states. [2019-01-07 22:10:17,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 13 transitions. [2019-01-07 22:10:17,802 INFO L78 Accepts]: Start accepts. Automaton has 8 states and 13 transitions. Word has length 2 [2019-01-07 22:10:17,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:10:17,803 INFO L480 AbstractCegarLoop]: Abstraction has 8 states and 13 transitions. [2019-01-07 22:10:17,804 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-07 22:10:17,804 INFO L276 IsEmpty]: Start isEmpty. Operand 8 states and 13 transitions. [2019-01-07 22:10:17,804 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-07 22:10:17,804 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:10:17,805 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-07 22:10:17,805 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:10:17,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:10:17,806 INFO L82 PathProgramCache]: Analyzing trace with hash 30304, now seen corresponding path program 1 times [2019-01-07 22:10:17,806 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:10:17,807 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:10:17,807 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:10:17,807 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:10:17,807 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:10:17,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:10:17,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:10:17,919 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-07 22:10:17,919 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-07 22:10:17,920 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:10:17,921 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-07 22:10:17,924 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-07 22:10:17,924 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-07 22:10:17,924 INFO L87 Difference]: Start difference. First operand 8 states and 13 transitions. Second operand 3 states. [2019-01-07 22:10:18,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:10:18,063 INFO L93 Difference]: Finished difference Result 12 states and 16 transitions. [2019-01-07 22:10:18,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-07 22:10:18,064 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-01-07 22:10:18,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:10:18,065 INFO L225 Difference]: With dead ends: 12 [2019-01-07 22:10:18,066 INFO L226 Difference]: Without dead ends: 11 [2019-01-07 22:10:18,066 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-07 22:10:18,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2019-01-07 22:10:18,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 9. [2019-01-07 22:10:18,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9 states. [2019-01-07 22:10:18,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 14 transitions. [2019-01-07 22:10:18,071 INFO L78 Accepts]: Start accepts. Automaton has 9 states and 14 transitions. Word has length 3 [2019-01-07 22:10:18,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:10:18,072 INFO L480 AbstractCegarLoop]: Abstraction has 9 states and 14 transitions. [2019-01-07 22:10:18,072 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-07 22:10:18,072 INFO L276 IsEmpty]: Start isEmpty. Operand 9 states and 14 transitions. [2019-01-07 22:10:18,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-07 22:10:18,072 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:10:18,073 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-07 22:10:18,073 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:10:18,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:10:18,073 INFO L82 PathProgramCache]: Analyzing trace with hash 29992, now seen corresponding path program 1 times [2019-01-07 22:10:18,074 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:10:18,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:10:18,075 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:10:18,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:10:18,075 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:10:18,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:10:18,166 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:10:18,167 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:10:18,167 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:10:18,168 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-07 22:10:18,170 INFO L207 CegarAbsIntRunner]: [0], [6], [15] [2019-01-07 22:10:18,232 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-07 22:10:18,232 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-07 22:10:25,706 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-07 22:10:25,708 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-07 22:10:25,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:10:25,714 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-07 22:10:26,072 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 71.43% of their original sizes. [2019-01-07 22:10:26,072 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-07 22:10:28,233 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_69 Int) (v_idx_67 Int) (v_idx_68 Int) (v_idx_72 Int) (v_idx_73 Int) (v_idx_70 Int) (v_idx_71 Int)) (exists ((v_b_113_1 Int) (v_b_112_1 Int) (v_v_999_1 Int) (v_v_1005_1 Int) (v_v_1001_1 Int) (v_v_1003_1 Int) (v_b_115_1 Int) (v_b_114_1 Int) (v_v_1000_1 Int)) (let ((.cse2 (+ v_b_114_1 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ v_b_112_1 1))) (and (<= (+ v_b_112_1 2) v_b_115_1) (<= .cse0 v_b_112_1) (or (< v_idx_73 v_b_115_1) (= (select |c_#memory_int| v_idx_73) v_v_1005_1)) (<= .cse1 v_b_113_1) (or (< v_idx_72 v_b_114_1) (<= v_b_115_1 v_idx_72) (= 0 (select |c_#memory_int| v_idx_72))) (<= v_b_115_1 .cse2) (or (= (select |c_#memory_int| v_idx_68) v_v_1000_1) (<= .cse0 v_idx_68) (< v_idx_68 c_ULTIMATE.start_main_p1)) (<= .cse2 v_b_115_1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_1) (or (< v_idx_69 .cse0) (<= v_b_112_1 v_idx_69) (= (select |c_#memory_int| v_idx_69) v_v_1001_1)) (<= .cse3 v_b_113_1) (or (= v_v_999_1 (select |c_#memory_int| v_idx_67)) (<= c_ULTIMATE.start_main_p1 v_idx_67)) (or (< v_idx_71 v_b_113_1) (<= v_b_114_1 v_idx_71) (= (select |c_#memory_int| v_idx_71) v_v_1003_1)) (or (<= v_b_113_1 v_idx_70) (= 0 (select |c_#memory_int| v_idx_70)) (< v_idx_70 v_b_112_1)) (<= v_b_113_1 .cse3) (<= v_b_113_1 v_b_114_1) (<= .cse1 v_b_114_1) (<= (+ v_b_113_1 1) v_b_115_1) (<= 0 (* 2 v_v_1000_1)) (<= 0 v_v_1000_1) (<= .cse3 v_b_114_1))))) is different from false [2019-01-07 22:10:30,259 WARN L860 $PredicateComparison]: unable to prove that (forall ((v_idx_69 Int) (v_idx_67 Int) (v_idx_68 Int) (v_idx_72 Int) (v_idx_73 Int) (v_idx_70 Int) (v_idx_71 Int)) (exists ((v_b_113_1 Int) (v_b_112_1 Int) (v_v_999_1 Int) (v_v_1005_1 Int) (v_v_1001_1 Int) (v_v_1003_1 Int) (v_b_115_1 Int) (v_b_114_1 Int) (v_v_1000_1 Int)) (let ((.cse2 (+ v_b_114_1 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ v_b_112_1 1))) (and (<= (+ v_b_112_1 2) v_b_115_1) (<= .cse0 v_b_112_1) (or (< v_idx_73 v_b_115_1) (= (select |c_#memory_int| v_idx_73) v_v_1005_1)) (<= .cse1 v_b_113_1) (or (< v_idx_72 v_b_114_1) (<= v_b_115_1 v_idx_72) (= 0 (select |c_#memory_int| v_idx_72))) (<= v_b_115_1 .cse2) (or (= (select |c_#memory_int| v_idx_68) v_v_1000_1) (<= .cse0 v_idx_68) (< v_idx_68 c_ULTIMATE.start_main_p1)) (<= .cse2 v_b_115_1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_1) (or (< v_idx_69 .cse0) (<= v_b_112_1 v_idx_69) (= (select |c_#memory_int| v_idx_69) v_v_1001_1)) (<= .cse3 v_b_113_1) (or (= v_v_999_1 (select |c_#memory_int| v_idx_67)) (<= c_ULTIMATE.start_main_p1 v_idx_67)) (or (< v_idx_71 v_b_113_1) (<= v_b_114_1 v_idx_71) (= (select |c_#memory_int| v_idx_71) v_v_1003_1)) (or (<= v_b_113_1 v_idx_70) (= 0 (select |c_#memory_int| v_idx_70)) (< v_idx_70 v_b_112_1)) (<= v_b_113_1 .cse3) (<= v_b_113_1 v_b_114_1) (<= .cse1 v_b_114_1) (<= (+ v_b_113_1 1) v_b_115_1) (<= 0 (* 2 v_v_1000_1)) (<= 0 v_v_1000_1) (<= .cse3 v_b_114_1))))) is different from true [2019-01-07 22:10:32,543 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_78 Int) (v_idx_79 Int) (v_idx_76 Int) (v_idx_77 Int) (v_idx_74 Int) (v_idx_75 Int) (v_idx_80 Int)) (exists ((v_b_113_1 Int) (v_b_112_1 Int) (v_v_999_1 Int) (v_v_1005_1 Int) (v_v_1001_1 Int) (v_v_1003_1 Int) (v_b_115_1 Int) (v_b_114_1 Int) (v_v_1000_1 Int)) (let ((.cse2 (+ v_b_114_1 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ v_b_112_1 1))) (and (<= (+ v_b_112_1 2) v_b_115_1) (<= .cse0 v_b_112_1) (or (<= v_b_112_1 v_idx_76) (= (select |c_#memory_int| v_idx_76) v_v_1001_1) (< v_idx_76 .cse0)) (<= .cse1 v_b_113_1) (or (= (select |c_#memory_int| v_idx_80) v_v_1005_1) (< v_idx_80 v_b_115_1)) (<= v_b_115_1 .cse2) (<= .cse2 v_b_115_1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_1) (or (< v_idx_77 v_b_112_1) (= (select |c_#memory_int| v_idx_77) 0) (<= v_b_113_1 v_idx_77)) (or (= (select |c_#memory_int| v_idx_75) v_v_1000_1) (< v_idx_75 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_75)) (<= .cse3 v_b_113_1) (<= v_b_113_1 .cse3) (<= v_b_113_1 v_b_114_1) (<= .cse1 v_b_114_1) (or (= (select |c_#memory_int| v_idx_79) 0) (< v_idx_79 v_b_114_1) (<= v_b_115_1 v_idx_79)) (or (= (select |c_#memory_int| v_idx_74) v_v_999_1) (<= c_ULTIMATE.start_main_p1 v_idx_74)) (<= (+ v_b_113_1 1) v_b_115_1) (<= 0 (* 2 v_v_1000_1)) (<= 0 v_v_1000_1) (<= .cse3 v_b_114_1) (or (= (select |c_#memory_int| v_idx_78) v_v_1003_1) (<= v_b_114_1 v_idx_78) (< v_idx_78 v_b_113_1)))))) is different from false [2019-01-07 22:10:32,606 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-07 22:10:32,606 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-07 22:10:32,607 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-07 22:10:32,607 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-07 22:10:32,607 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:10:32,608 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-07 22:10:32,608 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-07 22:10:32,608 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=2, Unknown=3, NotChecked=2, Total=12 [2019-01-07 22:10:32,609 INFO L87 Difference]: Start difference. First operand 9 states and 14 transitions. Second operand 4 states. [2019-01-07 22:10:36,636 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_69 Int) (v_idx_67 Int) (v_idx_68 Int) (v_idx_72 Int) (v_idx_73 Int) (v_idx_70 Int) (v_idx_71 Int)) (exists ((v_b_113_1 Int) (v_b_112_1 Int) (v_v_999_1 Int) (v_v_1005_1 Int) (v_v_1001_1 Int) (v_v_1003_1 Int) (v_b_115_1 Int) (v_b_114_1 Int) (v_v_1000_1 Int)) (let ((.cse2 (+ v_b_114_1 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ v_b_112_1 1))) (and (<= (+ v_b_112_1 2) v_b_115_1) (<= .cse0 v_b_112_1) (or (< v_idx_73 v_b_115_1) (= (select |c_#memory_int| v_idx_73) v_v_1005_1)) (<= .cse1 v_b_113_1) (or (< v_idx_72 v_b_114_1) (<= v_b_115_1 v_idx_72) (= 0 (select |c_#memory_int| v_idx_72))) (<= v_b_115_1 .cse2) (or (= (select |c_#memory_int| v_idx_68) v_v_1000_1) (<= .cse0 v_idx_68) (< v_idx_68 c_ULTIMATE.start_main_p1)) (<= .cse2 v_b_115_1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_1) (or (< v_idx_69 .cse0) (<= v_b_112_1 v_idx_69) (= (select |c_#memory_int| v_idx_69) v_v_1001_1)) (<= .cse3 v_b_113_1) (or (= v_v_999_1 (select |c_#memory_int| v_idx_67)) (<= c_ULTIMATE.start_main_p1 v_idx_67)) (or (< v_idx_71 v_b_113_1) (<= v_b_114_1 v_idx_71) (= (select |c_#memory_int| v_idx_71) v_v_1003_1)) (or (<= v_b_113_1 v_idx_70) (= 0 (select |c_#memory_int| v_idx_70)) (< v_idx_70 v_b_112_1)) (<= v_b_113_1 .cse3) (<= v_b_113_1 v_b_114_1) (<= .cse1 v_b_114_1) (<= (+ v_b_113_1 1) v_b_115_1) (<= 0 (* 2 v_v_1000_1)) (<= 0 v_v_1000_1) (<= .cse3 v_b_114_1))))) (forall ((v_idx_78 Int) (v_idx_79 Int) (v_idx_76 Int) (v_idx_77 Int) (v_idx_74 Int) (v_idx_75 Int) (v_idx_80 Int)) (exists ((v_b_113_1 Int) (v_b_112_1 Int) (v_v_999_1 Int) (v_v_1005_1 Int) (v_v_1001_1 Int) (v_v_1003_1 Int) (v_b_115_1 Int) (v_b_114_1 Int) (v_v_1000_1 Int)) (let ((.cse6 (+ v_b_114_1 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ v_b_112_1 1))) (and (<= (+ v_b_112_1 2) v_b_115_1) (<= .cse4 v_b_112_1) (or (<= v_b_112_1 v_idx_76) (= (select |c_#memory_int| v_idx_76) v_v_1001_1) (< v_idx_76 .cse4)) (<= .cse5 v_b_113_1) (or (= (select |c_#memory_int| v_idx_80) v_v_1005_1) (< v_idx_80 v_b_115_1)) (<= v_b_115_1 .cse6) (<= .cse6 v_b_115_1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_1) (or (< v_idx_77 v_b_112_1) (= (select |c_#memory_int| v_idx_77) 0) (<= v_b_113_1 v_idx_77)) (or (= (select |c_#memory_int| v_idx_75) v_v_1000_1) (< v_idx_75 c_ULTIMATE.start_main_p1) (<= .cse4 v_idx_75)) (<= .cse7 v_b_113_1) (<= v_b_113_1 .cse7) (<= v_b_113_1 v_b_114_1) (<= .cse5 v_b_114_1) (or (= (select |c_#memory_int| v_idx_79) 0) (< v_idx_79 v_b_114_1) (<= v_b_115_1 v_idx_79)) (or (= (select |c_#memory_int| v_idx_74) v_v_999_1) (<= c_ULTIMATE.start_main_p1 v_idx_74)) (<= (+ v_b_113_1 1) v_b_115_1) (<= 0 (* 2 v_v_1000_1)) (<= 0 v_v_1000_1) (<= .cse7 v_b_114_1) (or (= (select |c_#memory_int| v_idx_78) v_v_1003_1) (<= v_b_114_1 v_idx_78) (< v_idx_78 v_b_113_1))))))) is different from false [2019-01-07 22:10:59,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:10:59,073 INFO L93 Difference]: Finished difference Result 11 states and 19 transitions. [2019-01-07 22:10:59,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-07 22:10:59,074 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-07 22:10:59,074 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:10:59,075 INFO L225 Difference]: With dead ends: 11 [2019-01-07 22:10:59,075 INFO L226 Difference]: Without dead ends: 10 [2019-01-07 22:10:59,075 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 10.5s TimeCoverageRelationStatistics Valid=7, Invalid=3, Unknown=4, NotChecked=6, Total=20 [2019-01-07 22:10:59,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states. [2019-01-07 22:10:59,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2019-01-07 22:10:59,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2019-01-07 22:10:59,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 18 transitions. [2019-01-07 22:10:59,080 INFO L78 Accepts]: Start accepts. Automaton has 10 states and 18 transitions. Word has length 3 [2019-01-07 22:10:59,080 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:10:59,081 INFO L480 AbstractCegarLoop]: Abstraction has 10 states and 18 transitions. [2019-01-07 22:10:59,081 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-07 22:10:59,081 INFO L276 IsEmpty]: Start isEmpty. Operand 10 states and 18 transitions. [2019-01-07 22:10:59,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-07 22:10:59,082 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:10:59,082 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-07 22:10:59,082 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:10:59,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:10:59,083 INFO L82 PathProgramCache]: Analyzing trace with hash 30116, now seen corresponding path program 1 times [2019-01-07 22:10:59,083 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:10:59,084 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:10:59,084 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:10:59,085 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:10:59,085 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:10:59,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:10:59,244 WARN L181 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 20 DAG size of output: 13 [2019-01-07 22:10:59,251 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:10:59,252 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:10:59,252 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:10:59,252 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-07 22:10:59,252 INFO L207 CegarAbsIntRunner]: [0], [10], [15] [2019-01-07 22:10:59,254 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-07 22:10:59,254 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-07 22:11:03,394 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-07 22:11:03,394 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-07 22:11:03,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:11:03,395 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-07 22:11:03,659 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 64.29% of their original sizes. [2019-01-07 22:11:03,659 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-07 22:11:05,871 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_148 Int) (v_idx_149 Int) (v_idx_147 Int) (v_idx_151 Int) (v_idx_152 Int) (v_idx_150 Int) (v_idx_153 Int)) (exists ((v_v_1170_2 Int) (v_v_1166_2 Int) (v_v_1168_2 Int) (v_v_1167_2 Int) (v_b_105_2 Int) (v_v_1164_2 Int) (v_b_104_2 Int)) (let ((.cse0 (+ v_b_104_2 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_105_2 .cse0) (<= v_v_1167_2 0) (or (= (select |c_#memory_int| v_idx_149) v_v_1166_2) (<= c_ULTIMATE.start_main_p2 v_idx_149) (< v_idx_149 .cse1)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_105_2) (or (= (select |c_#memory_int| v_idx_153) v_v_1170_2) (< v_idx_153 v_b_105_2)) (<= .cse2 v_b_104_2) (<= (* 2 v_v_1167_2) 0) (or (< v_idx_150 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_150) v_v_1167_2) (<= .cse2 v_idx_150)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_105_2) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_104_2) (<= .cse0 v_b_105_2) (<= .cse1 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_151) v_v_1168_2) (<= v_b_104_2 v_idx_151) (< v_idx_151 .cse2)) (or (= (select |c_#memory_int| v_idx_147) v_v_1164_2) (<= c_ULTIMATE.start_main_p1 v_idx_147)) (or (= (select |c_#memory_int| v_idx_148) 0) (<= .cse1 v_idx_148) (< v_idx_148 c_ULTIMATE.start_main_p1)) (or (<= v_b_105_2 v_idx_152) (= (select |c_#memory_int| v_idx_152) 0) (< v_idx_152 v_b_104_2)))))) is different from false [2019-01-07 22:11:08,146 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_159 Int) (v_idx_157 Int) (v_idx_158 Int) (v_idx_160 Int) (v_idx_155 Int) (v_idx_156 Int) (v_idx_154 Int)) (exists ((v_v_1170_2 Int) (v_v_1166_2 Int) (v_v_1168_2 Int) (v_v_1167_2 Int) (v_b_102_2 Int) (v_b_103_2 Int) (v_b_105_2 Int) (v_v_1164_2 Int) (v_b_104_2 Int)) (let ((.cse1 (+ v_b_102_2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ v_b_104_2 1))) (and (<= v_b_105_2 .cse0) (<= v_v_1167_2 0) (<= (+ v_b_102_2 2) v_b_105_2) (<= .cse1 v_b_104_2) (or (<= v_b_105_2 v_idx_159) (= (select |c_#memory_int| v_idx_159) 0) (< v_idx_159 v_b_104_2)) (or (< v_idx_160 v_b_105_2) (= (select |c_#memory_int| v_idx_160) v_v_1170_2)) (<= .cse2 v_b_103_2) (<= v_b_103_2 v_b_104_2) (<= (* 2 v_v_1167_2) 0) (<= .cse1 v_b_103_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_154) (= (select |c_#memory_int| v_idx_154) v_v_1164_2)) (or (< v_idx_155 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_155)) (<= .cse3 v_idx_155)) (or (<= v_b_104_2 v_idx_158) (< v_idx_158 v_b_103_2) (= (select |c_#memory_int| v_idx_158) v_v_1168_2)) (or (<= v_b_102_2 v_idx_156) (= (select |c_#memory_int| v_idx_156) v_v_1166_2) (< v_idx_156 .cse3)) (<= v_b_103_2 .cse1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_105_2) (<= .cse2 v_b_104_2) (<= .cse3 v_b_102_2) (<= (+ v_b_103_2 1) v_b_105_2) (<= .cse0 v_b_105_2) (or (<= v_b_103_2 v_idx_157) (= (select |c_#memory_int| v_idx_157) v_v_1167_2) (< v_idx_157 v_b_102_2)))))) is different from false [2019-01-07 22:11:08,198 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-07 22:11:08,198 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-07 22:11:08,198 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-07 22:11:08,198 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-07 22:11:08,199 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:11:08,199 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-07 22:11:08,199 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-07 22:11:08,199 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-07 22:11:08,199 INFO L87 Difference]: Start difference. First operand 10 states and 18 transitions. Second operand 4 states. [2019-01-07 22:11:10,622 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_148 Int) (v_idx_149 Int) (v_idx_147 Int) (v_idx_151 Int) (v_idx_152 Int) (v_idx_150 Int) (v_idx_153 Int)) (exists ((v_v_1170_2 Int) (v_v_1166_2 Int) (v_v_1168_2 Int) (v_v_1167_2 Int) (v_b_105_2 Int) (v_v_1164_2 Int) (v_b_104_2 Int)) (let ((.cse0 (+ v_b_104_2 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_105_2 .cse0) (<= v_v_1167_2 0) (or (= (select |c_#memory_int| v_idx_149) v_v_1166_2) (<= c_ULTIMATE.start_main_p2 v_idx_149) (< v_idx_149 .cse1)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_105_2) (or (= (select |c_#memory_int| v_idx_153) v_v_1170_2) (< v_idx_153 v_b_105_2)) (<= .cse2 v_b_104_2) (<= (* 2 v_v_1167_2) 0) (or (< v_idx_150 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_150) v_v_1167_2) (<= .cse2 v_idx_150)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_105_2) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_104_2) (<= .cse0 v_b_105_2) (<= .cse1 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_151) v_v_1168_2) (<= v_b_104_2 v_idx_151) (< v_idx_151 .cse2)) (or (= (select |c_#memory_int| v_idx_147) v_v_1164_2) (<= c_ULTIMATE.start_main_p1 v_idx_147)) (or (= (select |c_#memory_int| v_idx_148) 0) (<= .cse1 v_idx_148) (< v_idx_148 c_ULTIMATE.start_main_p1)) (or (<= v_b_105_2 v_idx_152) (= (select |c_#memory_int| v_idx_152) 0) (< v_idx_152 v_b_104_2)))))) (forall ((v_idx_159 Int) (v_idx_157 Int) (v_idx_158 Int) (v_idx_160 Int) (v_idx_155 Int) (v_idx_156 Int) (v_idx_154 Int)) (exists ((v_v_1170_2 Int) (v_v_1166_2 Int) (v_v_1168_2 Int) (v_v_1167_2 Int) (v_b_102_2 Int) (v_b_103_2 Int) (v_b_105_2 Int) (v_v_1164_2 Int) (v_b_104_2 Int)) (let ((.cse4 (+ v_b_102_2 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 2)) (.cse6 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ v_b_104_2 1))) (and (<= v_b_105_2 .cse3) (<= v_v_1167_2 0) (<= (+ v_b_102_2 2) v_b_105_2) (<= .cse4 v_b_104_2) (or (<= v_b_105_2 v_idx_159) (= (select |c_#memory_int| v_idx_159) 0) (< v_idx_159 v_b_104_2)) (or (< v_idx_160 v_b_105_2) (= (select |c_#memory_int| v_idx_160) v_v_1170_2)) (<= .cse5 v_b_103_2) (<= v_b_103_2 v_b_104_2) (<= (* 2 v_v_1167_2) 0) (<= .cse4 v_b_103_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_154) (= (select |c_#memory_int| v_idx_154) v_v_1164_2)) (or (< v_idx_155 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_155)) (<= .cse6 v_idx_155)) (or (<= v_b_104_2 v_idx_158) (< v_idx_158 v_b_103_2) (= (select |c_#memory_int| v_idx_158) v_v_1168_2)) (or (<= v_b_102_2 v_idx_156) (= (select |c_#memory_int| v_idx_156) v_v_1166_2) (< v_idx_156 .cse6)) (<= v_b_103_2 .cse4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_105_2) (<= .cse5 v_b_104_2) (<= .cse6 v_b_102_2) (<= (+ v_b_103_2 1) v_b_105_2) (<= .cse3 v_b_105_2) (or (<= v_b_103_2 v_idx_157) (= (select |c_#memory_int| v_idx_157) v_v_1167_2) (< v_idx_157 v_b_102_2))))))) is different from false [2019-01-07 22:11:21,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:11:21,132 INFO L93 Difference]: Finished difference Result 12 states and 23 transitions. [2019-01-07 22:11:21,132 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-07 22:11:21,132 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-07 22:11:21,132 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:11:21,133 INFO L225 Difference]: With dead ends: 12 [2019-01-07 22:11:21,133 INFO L226 Difference]: Without dead ends: 11 [2019-01-07 22:11:21,133 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 6.9s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-07 22:11:21,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2019-01-07 22:11:21,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 10. [2019-01-07 22:11:21,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2019-01-07 22:11:21,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 18 transitions. [2019-01-07 22:11:21,140 INFO L78 Accepts]: Start accepts. Automaton has 10 states and 18 transitions. Word has length 3 [2019-01-07 22:11:21,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:11:21,140 INFO L480 AbstractCegarLoop]: Abstraction has 10 states and 18 transitions. [2019-01-07 22:11:21,140 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-07 22:11:21,140 INFO L276 IsEmpty]: Start isEmpty. Operand 10 states and 18 transitions. [2019-01-07 22:11:21,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-07 22:11:21,141 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:11:21,141 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-07 22:11:21,141 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:11:21,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:11:21,142 INFO L82 PathProgramCache]: Analyzing trace with hash 30178, now seen corresponding path program 1 times [2019-01-07 22:11:21,142 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:11:21,143 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:11:21,143 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:11:21,143 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:11:21,143 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:11:21,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:11:21,296 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:11:21,296 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:11:21,297 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:11:21,297 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-07 22:11:21,297 INFO L207 CegarAbsIntRunner]: [0], [12], [15] [2019-01-07 22:11:21,298 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-07 22:11:21,299 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-07 22:11:25,290 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-07 22:11:25,290 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-07 22:11:25,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:11:25,291 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-07 22:11:25,485 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 64.29% of their original sizes. [2019-01-07 22:11:25,485 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-07 22:11:27,988 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_229 Int) (v_idx_227 Int) (v_idx_228 Int) (v_idx_232 Int) (v_idx_233 Int) (v_idx_230 Int) (v_idx_231 Int)) (exists ((v_v_1170_3 Int) (v_v_1169_3 Int) (v_v_1168_3 Int) (v_v_1164_3 Int) (v_v_1166_3 Int) (v_b_102_3 Int) (v_b_103_3 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse2 (+ v_b_102_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ c_ULTIMATE.start_main_p1 1))) (and (<= .cse0 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_232) v_v_1169_3) (< v_idx_232 c_ULTIMATE.start_main_p3) (<= .cse1 v_idx_232)) (or (= (select |c_#memory_int| v_idx_227) v_v_1164_3) (<= c_ULTIMATE.start_main_p1 v_idx_227)) (<= .cse2 v_b_103_3) (or (= (select |c_#memory_int| v_idx_229) v_v_1166_3) (< v_idx_229 .cse3) (<= v_b_102_3 v_idx_229)) (or (< v_idx_228 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_228)) (<= .cse3 v_idx_228)) (or (< v_idx_233 .cse1) (= (select |c_#memory_int| v_idx_233) v_v_1170_3)) (<= .cse2 c_ULTIMATE.start_main_p3) (or (< v_idx_231 v_b_103_3) (<= c_ULTIMATE.start_main_p3 v_idx_231) (= (select |c_#memory_int| v_idx_231) v_v_1168_3)) (<= v_b_103_3 c_ULTIMATE.start_main_p3) (<= v_b_103_3 .cse2) (<= .cse0 v_b_103_3) (<= .cse3 v_b_102_3) (<= 0 (* 2 v_v_1169_3)) (or (= 0 (select |c_#memory_int| v_idx_230)) (<= v_b_103_3 v_idx_230) (< v_idx_230 v_b_102_3)) (<= 0 v_v_1169_3))))) is different from false [2019-01-07 22:11:30,743 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_236 Int) (v_idx_237 Int) (v_idx_234 Int) (v_idx_235 Int) (v_idx_238 Int) (v_idx_239 Int) (v_idx_240 Int)) (exists ((v_v_1170_3 Int) (v_v_1169_3 Int) (v_v_1168_3 Int) (v_b_105_3 Int) (v_v_1164_3 Int) (v_v_1166_3 Int) (v_b_102_3 Int) (v_b_104_3 Int) (v_b_103_3 Int)) (let ((.cse0 (+ v_b_102_3 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ v_b_104_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (<= .cse0 v_b_103_3) (or (<= v_b_105_3 v_idx_239) (< v_idx_239 v_b_104_3) (= (select |c_#memory_int| v_idx_239) v_v_1169_3)) (or (= 0 (select |c_#memory_int| v_idx_235)) (<= .cse1 v_idx_235) (< v_idx_235 c_ULTIMATE.start_main_p1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_234) (= (select |c_#memory_int| v_idx_234) v_v_1164_3)) (<= v_b_103_3 .cse0) (<= .cse2 v_b_103_3) (<= .cse1 v_b_102_3) (<= .cse0 v_b_104_3) (<= 0 (* 2 v_v_1169_3)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_105_3) (<= v_b_105_3 .cse3) (<= 0 v_v_1169_3) (<= v_b_103_3 v_b_104_3) (or (<= v_b_104_3 v_idx_238) (< v_idx_238 v_b_103_3) (= (select |c_#memory_int| v_idx_238) v_v_1168_3)) (<= .cse2 v_b_104_3) (or (= (select |c_#memory_int| v_idx_240) v_v_1170_3) (< v_idx_240 v_b_105_3)) (<= .cse3 v_b_105_3) (<= (+ v_b_102_3 2) v_b_105_3) (or (<= v_b_103_3 v_idx_237) (< v_idx_237 v_b_102_3) (= 0 (select |c_#memory_int| v_idx_237))) (or (< v_idx_236 .cse1) (= (select |c_#memory_int| v_idx_236) v_v_1166_3) (<= v_b_102_3 v_idx_236)) (<= (+ v_b_103_3 1) v_b_105_3))))) is different from false [2019-01-07 22:11:30,871 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-07 22:11:30,871 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-07 22:11:30,871 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-07 22:11:30,871 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-07 22:11:30,871 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:11:30,872 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-07 22:11:30,872 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-07 22:11:30,872 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-07 22:11:30,872 INFO L87 Difference]: Start difference. First operand 10 states and 18 transitions. Second operand 4 states. [2019-01-07 22:11:33,410 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_229 Int) (v_idx_227 Int) (v_idx_228 Int) (v_idx_232 Int) (v_idx_233 Int) (v_idx_230 Int) (v_idx_231 Int)) (exists ((v_v_1170_3 Int) (v_v_1169_3 Int) (v_v_1168_3 Int) (v_v_1164_3 Int) (v_v_1166_3 Int) (v_b_102_3 Int) (v_b_103_3 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse2 (+ v_b_102_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ c_ULTIMATE.start_main_p1 1))) (and (<= .cse0 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_232) v_v_1169_3) (< v_idx_232 c_ULTIMATE.start_main_p3) (<= .cse1 v_idx_232)) (or (= (select |c_#memory_int| v_idx_227) v_v_1164_3) (<= c_ULTIMATE.start_main_p1 v_idx_227)) (<= .cse2 v_b_103_3) (or (= (select |c_#memory_int| v_idx_229) v_v_1166_3) (< v_idx_229 .cse3) (<= v_b_102_3 v_idx_229)) (or (< v_idx_228 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_228)) (<= .cse3 v_idx_228)) (or (< v_idx_233 .cse1) (= (select |c_#memory_int| v_idx_233) v_v_1170_3)) (<= .cse2 c_ULTIMATE.start_main_p3) (or (< v_idx_231 v_b_103_3) (<= c_ULTIMATE.start_main_p3 v_idx_231) (= (select |c_#memory_int| v_idx_231) v_v_1168_3)) (<= v_b_103_3 c_ULTIMATE.start_main_p3) (<= v_b_103_3 .cse2) (<= .cse0 v_b_103_3) (<= .cse3 v_b_102_3) (<= 0 (* 2 v_v_1169_3)) (or (= 0 (select |c_#memory_int| v_idx_230)) (<= v_b_103_3 v_idx_230) (< v_idx_230 v_b_102_3)) (<= 0 v_v_1169_3))))) (forall ((v_idx_236 Int) (v_idx_237 Int) (v_idx_234 Int) (v_idx_235 Int) (v_idx_238 Int) (v_idx_239 Int) (v_idx_240 Int)) (exists ((v_v_1170_3 Int) (v_v_1169_3 Int) (v_v_1168_3 Int) (v_b_105_3 Int) (v_v_1164_3 Int) (v_v_1166_3 Int) (v_b_102_3 Int) (v_b_104_3 Int) (v_b_103_3 Int)) (let ((.cse4 (+ v_b_102_3 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ v_b_104_3 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1))) (and (<= .cse4 v_b_103_3) (or (<= v_b_105_3 v_idx_239) (< v_idx_239 v_b_104_3) (= (select |c_#memory_int| v_idx_239) v_v_1169_3)) (or (= 0 (select |c_#memory_int| v_idx_235)) (<= .cse5 v_idx_235) (< v_idx_235 c_ULTIMATE.start_main_p1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_234) (= (select |c_#memory_int| v_idx_234) v_v_1164_3)) (<= v_b_103_3 .cse4) (<= .cse6 v_b_103_3) (<= .cse5 v_b_102_3) (<= .cse4 v_b_104_3) (<= 0 (* 2 v_v_1169_3)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_105_3) (<= v_b_105_3 .cse7) (<= 0 v_v_1169_3) (<= v_b_103_3 v_b_104_3) (or (<= v_b_104_3 v_idx_238) (< v_idx_238 v_b_103_3) (= (select |c_#memory_int| v_idx_238) v_v_1168_3)) (<= .cse6 v_b_104_3) (or (= (select |c_#memory_int| v_idx_240) v_v_1170_3) (< v_idx_240 v_b_105_3)) (<= .cse7 v_b_105_3) (<= (+ v_b_102_3 2) v_b_105_3) (or (<= v_b_103_3 v_idx_237) (< v_idx_237 v_b_102_3) (= 0 (select |c_#memory_int| v_idx_237))) (or (< v_idx_236 .cse5) (= (select |c_#memory_int| v_idx_236) v_v_1166_3) (<= v_b_102_3 v_idx_236)) (<= (+ v_b_103_3 1) v_b_105_3)))))) is different from false [2019-01-07 22:11:44,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:11:44,993 INFO L93 Difference]: Finished difference Result 12 states and 23 transitions. [2019-01-07 22:11:44,993 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-07 22:11:44,993 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-07 22:11:44,993 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:11:44,993 INFO L225 Difference]: With dead ends: 12 [2019-01-07 22:11:44,994 INFO L226 Difference]: Without dead ends: 11 [2019-01-07 22:11:44,994 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 8.0s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-07 22:11:44,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2019-01-07 22:11:45,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 10. [2019-01-07 22:11:45,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2019-01-07 22:11:45,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 18 transitions. [2019-01-07 22:11:45,001 INFO L78 Accepts]: Start accepts. Automaton has 10 states and 18 transitions. Word has length 3 [2019-01-07 22:11:45,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:11:45,001 INFO L480 AbstractCegarLoop]: Abstraction has 10 states and 18 transitions. [2019-01-07 22:11:45,001 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-07 22:11:45,002 INFO L276 IsEmpty]: Start isEmpty. Operand 10 states and 18 transitions. [2019-01-07 22:11:45,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-07 22:11:45,002 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:11:45,002 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-07 22:11:45,003 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:11:45,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:11:45,003 INFO L82 PathProgramCache]: Analyzing trace with hash 939474, now seen corresponding path program 1 times [2019-01-07 22:11:45,003 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:11:45,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:11:45,004 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:11:45,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:11:45,004 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:11:45,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:11:45,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:11:45,049 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-07 22:11:45,049 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-07 22:11:45,049 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:11:45,050 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-07 22:11:45,050 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-07 22:11:45,050 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-07 22:11:45,050 INFO L87 Difference]: Start difference. First operand 10 states and 18 transitions. Second operand 3 states. [2019-01-07 22:11:45,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:11:45,146 INFO L93 Difference]: Finished difference Result 12 states and 19 transitions. [2019-01-07 22:11:45,146 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-07 22:11:45,147 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 4 [2019-01-07 22:11:45,147 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:11:45,147 INFO L225 Difference]: With dead ends: 12 [2019-01-07 22:11:45,147 INFO L226 Difference]: Without dead ends: 9 [2019-01-07 22:11:45,148 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-07 22:11:45,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states. [2019-01-07 22:11:45,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2019-01-07 22:11:45,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9 states. [2019-01-07 22:11:45,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 16 transitions. [2019-01-07 22:11:45,154 INFO L78 Accepts]: Start accepts. Automaton has 9 states and 16 transitions. Word has length 4 [2019-01-07 22:11:45,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:11:45,155 INFO L480 AbstractCegarLoop]: Abstraction has 9 states and 16 transitions. [2019-01-07 22:11:45,155 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-07 22:11:45,155 INFO L276 IsEmpty]: Start isEmpty. Operand 9 states and 16 transitions. [2019-01-07 22:11:45,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-07 22:11:45,155 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:11:45,156 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-07 22:11:45,156 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:11:45,156 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:11:45,156 INFO L82 PathProgramCache]: Analyzing trace with hash 929800, now seen corresponding path program 1 times [2019-01-07 22:11:45,156 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:11:45,157 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:11:45,158 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:11:45,158 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:11:45,158 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:11:45,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:11:45,484 WARN L181 SmtUtils]: Spent 245.00 ms on a formula simplification. DAG size of input: 19 DAG size of output: 13 [2019-01-07 22:11:45,526 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:11:45,526 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:11:45,526 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:11:45,527 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-07 22:11:45,527 INFO L207 CegarAbsIntRunner]: [0], [6], [16], [17] [2019-01-07 22:11:45,528 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-07 22:11:45,529 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-07 22:11:51,614 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-07 22:11:51,615 INFO L272 AbstractInterpreter]: Visited 4 different actions 16 times. Merged at 2 different actions 8 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-07 22:11:51,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:11:51,615 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-07 22:11:51,928 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 61.9% of their original sizes. [2019-01-07 22:11:51,928 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-07 22:11:54,660 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_346 Int) (v_idx_344 Int) (v_idx_345 Int) (v_idx_342 Int) (v_idx_343 Int) (v_idx_340 Int) (v_idx_341 Int)) (exists ((v_b_131_4 Int) (v_v_1703_2 Int) (v_b_130_4 Int) (v_v_1705_4 Int) (v_v_1704_4 Int) (v_v_1709_2 Int) (v_v_1707_4 Int)) (let ((.cse2 (+ v_b_130_4 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1))) (and (or (< v_idx_342 .cse0) (= (select |c_#memory_int| v_idx_342) v_v_1705_4) (<= c_ULTIMATE.start_main_p2 v_idx_342)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_4) (or (= (select |c_#memory_int| v_idx_343) 0) (<= .cse1 v_idx_343) (< v_idx_343 c_ULTIMATE.start_main_p2)) (<= .cse2 v_b_131_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_340) (= (select |c_#memory_int| v_idx_340) v_v_1703_2)) (or (< v_idx_345 v_b_130_4) (= 0 (select |c_#memory_int| v_idx_345)) (<= v_b_131_4 v_idx_345)) (<= 0 (* 2 v_v_1704_4)) (<= 0 v_v_1704_4) (<= .cse1 v_b_130_4) (or (= (select |c_#memory_int| v_idx_341) v_v_1704_4) (< v_idx_341 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_341)) (or (< v_idx_346 v_b_131_4) (= (select |c_#memory_int| v_idx_346) v_v_1709_2)) (<= v_b_131_4 .cse2) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_4) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_4) (<= .cse0 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_344) v_v_1707_4) (< v_idx_344 .cse1) (<= v_b_130_4 v_idx_344)))))) is different from false [2019-01-07 22:11:57,191 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_347 Int) (v_idx_348 Int) (v_idx_349 Int) (v_idx_350 Int) (v_idx_353 Int) (v_idx_351 Int) (v_idx_352 Int)) (exists ((v_b_131_4 Int) (v_v_1703_2 Int) (v_b_130_4 Int) (v_v_1705_4 Int) (v_v_1704_4 Int) (v_v_1707_4 Int) (v_v_1709_2 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_130_4 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= 0 (select |c_#memory_int| v_idx_352)) (< v_idx_352 v_b_130_4) (<= v_b_131_4 v_idx_352)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_4) (or (= 0 (select |c_#memory_int| v_idx_350)) (<= .cse0 v_idx_350) (< v_idx_350 c_ULTIMATE.start_main_p2)) (<= .cse1 v_b_131_4) (or (= (select |c_#memory_int| v_idx_347) v_v_1703_2) (<= c_ULTIMATE.start_main_p1 v_idx_347)) (<= 0 (* 2 v_v_1704_4)) (or (< v_idx_351 .cse0) (<= v_b_130_4 v_idx_351) (= (select |c_#memory_int| v_idx_351) v_v_1707_4)) (or (= (select |c_#memory_int| v_idx_348) v_v_1704_4) (< v_idx_348 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_348)) (or (<= c_ULTIMATE.start_main_p2 v_idx_349) (< v_idx_349 .cse2) (= (select |c_#memory_int| v_idx_349) v_v_1705_4)) (<= 0 v_v_1704_4) (<= .cse0 v_b_130_4) (or (< v_idx_353 v_b_131_4) (= (select |c_#memory_int| v_idx_353) v_v_1709_2)) (<= v_b_131_4 .cse1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_4) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_4) (<= .cse2 c_ULTIMATE.start_main_p2))))) is different from false [2019-01-07 22:11:59,466 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_357 Int) (v_idx_358 Int) (v_idx_355 Int) (v_idx_356 Int) (v_idx_359 Int) (v_idx_360 Int) (v_idx_354 Int)) (exists ((v_b_131_4 Int) (v_v_1703_2 Int) (v_b_130_4 Int) (v_b_127_4 Int) (v_v_1705_4 Int) (v_v_2001_1 Int) (v_b_138_4 Int) (v_v_1707_4 Int) (v_v_1709_2 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_130_4 1)) (.cse0 (+ v_b_138_4 1))) (and (or (< v_idx_356 v_b_127_4) (= (select |c_#memory_int| v_idx_356) v_v_1705_4) (<= c_ULTIMATE.start_main_p2 v_idx_356)) (or (<= v_b_131_4 v_idx_359) (= 0 (select |c_#memory_int| v_idx_359)) (< v_idx_359 v_b_130_4)) (<= 0 v_v_2001_1) (<= .cse0 v_b_127_4) (<= .cse1 v_b_131_4) (or (= (select |c_#memory_int| v_idx_358) v_v_1707_4) (<= v_b_130_4 v_idx_358) (< v_idx_358 .cse2)) (<= (+ v_b_138_4 2) v_b_130_4) (or (= 0 (select |c_#memory_int| v_idx_357)) (<= .cse2 v_idx_357) (< v_idx_357 c_ULTIMATE.start_main_p2)) (<= .cse0 c_ULTIMATE.start_main_p2) (<= (+ v_b_138_4 3) v_b_131_4) (<= (+ v_b_127_4 1) v_b_130_4) (<= (+ v_b_127_4 2) v_b_131_4) (<= .cse2 v_b_130_4) (<= v_b_131_4 .cse1) (or (<= v_b_138_4 v_idx_354) (= (select |c_#memory_int| v_idx_354) v_v_1703_2)) (or (< v_idx_355 v_b_138_4) (= (select |c_#memory_int| v_idx_355) v_v_2001_1) (<= v_b_127_4 v_idx_355)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_4) (<= v_b_127_4 .cse0) (<= 0 (* 2 v_v_2001_1)) (or (< v_idx_360 v_b_131_4) (= (select |c_#memory_int| v_idx_360) v_v_1709_2)) (<= v_b_127_4 c_ULTIMATE.start_main_p2))))) is different from false [2019-01-07 22:11:59,527 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-07 22:11:59,528 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-07 22:11:59,528 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-07 22:11:59,528 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [2] total 5 [2019-01-07 22:11:59,528 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:11:59,528 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-07 22:11:59,529 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-07 22:11:59,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-07 22:11:59,529 INFO L87 Difference]: Start difference. First operand 9 states and 16 transitions. Second operand 5 states. [2019-01-07 22:12:02,074 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_347 Int) (v_idx_348 Int) (v_idx_349 Int) (v_idx_350 Int) (v_idx_353 Int) (v_idx_351 Int) (v_idx_352 Int)) (exists ((v_b_131_4 Int) (v_v_1703_2 Int) (v_b_130_4 Int) (v_v_1705_4 Int) (v_v_1704_4 Int) (v_v_1707_4 Int) (v_v_1709_2 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_130_4 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= 0 (select |c_#memory_int| v_idx_352)) (< v_idx_352 v_b_130_4) (<= v_b_131_4 v_idx_352)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_4) (or (= 0 (select |c_#memory_int| v_idx_350)) (<= .cse0 v_idx_350) (< v_idx_350 c_ULTIMATE.start_main_p2)) (<= .cse1 v_b_131_4) (or (= (select |c_#memory_int| v_idx_347) v_v_1703_2) (<= c_ULTIMATE.start_main_p1 v_idx_347)) (<= 0 (* 2 v_v_1704_4)) (or (< v_idx_351 .cse0) (<= v_b_130_4 v_idx_351) (= (select |c_#memory_int| v_idx_351) v_v_1707_4)) (or (= (select |c_#memory_int| v_idx_348) v_v_1704_4) (< v_idx_348 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_348)) (or (<= c_ULTIMATE.start_main_p2 v_idx_349) (< v_idx_349 .cse2) (= (select |c_#memory_int| v_idx_349) v_v_1705_4)) (<= 0 v_v_1704_4) (<= .cse0 v_b_130_4) (or (< v_idx_353 v_b_131_4) (= (select |c_#memory_int| v_idx_353) v_v_1709_2)) (<= v_b_131_4 .cse1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_4) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_4) (<= .cse2 c_ULTIMATE.start_main_p2))))) (forall ((v_idx_346 Int) (v_idx_344 Int) (v_idx_345 Int) (v_idx_342 Int) (v_idx_343 Int) (v_idx_340 Int) (v_idx_341 Int)) (exists ((v_b_131_4 Int) (v_v_1703_2 Int) (v_b_130_4 Int) (v_v_1705_4 Int) (v_v_1704_4 Int) (v_v_1709_2 Int) (v_v_1707_4 Int)) (let ((.cse5 (+ v_b_130_4 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1)) (.cse4 (+ c_ULTIMATE.start_main_p2 1))) (and (or (< v_idx_342 .cse3) (= (select |c_#memory_int| v_idx_342) v_v_1705_4) (<= c_ULTIMATE.start_main_p2 v_idx_342)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_4) (or (= (select |c_#memory_int| v_idx_343) 0) (<= .cse4 v_idx_343) (< v_idx_343 c_ULTIMATE.start_main_p2)) (<= .cse5 v_b_131_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_340) (= (select |c_#memory_int| v_idx_340) v_v_1703_2)) (or (< v_idx_345 v_b_130_4) (= 0 (select |c_#memory_int| v_idx_345)) (<= v_b_131_4 v_idx_345)) (<= 0 (* 2 v_v_1704_4)) (<= 0 v_v_1704_4) (<= .cse4 v_b_130_4) (or (= (select |c_#memory_int| v_idx_341) v_v_1704_4) (< v_idx_341 c_ULTIMATE.start_main_p1) (<= .cse3 v_idx_341)) (or (< v_idx_346 v_b_131_4) (= (select |c_#memory_int| v_idx_346) v_v_1709_2)) (<= v_b_131_4 .cse5) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_4) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_4) (<= .cse3 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_344) v_v_1707_4) (< v_idx_344 .cse4) (<= v_b_130_4 v_idx_344)))))) (forall ((v_idx_357 Int) (v_idx_358 Int) (v_idx_355 Int) (v_idx_356 Int) (v_idx_359 Int) (v_idx_360 Int) (v_idx_354 Int)) (exists ((v_b_131_4 Int) (v_v_1703_2 Int) (v_b_130_4 Int) (v_b_127_4 Int) (v_v_1705_4 Int) (v_v_2001_1 Int) (v_b_138_4 Int) (v_v_1707_4 Int) (v_v_1709_2 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p2 1)) (.cse7 (+ v_b_130_4 1)) (.cse6 (+ v_b_138_4 1))) (and (or (< v_idx_356 v_b_127_4) (= (select |c_#memory_int| v_idx_356) v_v_1705_4) (<= c_ULTIMATE.start_main_p2 v_idx_356)) (or (<= v_b_131_4 v_idx_359) (= 0 (select |c_#memory_int| v_idx_359)) (< v_idx_359 v_b_130_4)) (<= 0 v_v_2001_1) (<= .cse6 v_b_127_4) (<= .cse7 v_b_131_4) (or (= (select |c_#memory_int| v_idx_358) v_v_1707_4) (<= v_b_130_4 v_idx_358) (< v_idx_358 .cse8)) (<= (+ v_b_138_4 2) v_b_130_4) (or (= 0 (select |c_#memory_int| v_idx_357)) (<= .cse8 v_idx_357) (< v_idx_357 c_ULTIMATE.start_main_p2)) (<= .cse6 c_ULTIMATE.start_main_p2) (<= (+ v_b_138_4 3) v_b_131_4) (<= (+ v_b_127_4 1) v_b_130_4) (<= (+ v_b_127_4 2) v_b_131_4) (<= .cse8 v_b_130_4) (<= v_b_131_4 .cse7) (or (<= v_b_138_4 v_idx_354) (= (select |c_#memory_int| v_idx_354) v_v_1703_2)) (or (< v_idx_355 v_b_138_4) (= (select |c_#memory_int| v_idx_355) v_v_2001_1) (<= v_b_127_4 v_idx_355)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_4) (<= v_b_127_4 .cse6) (<= 0 (* 2 v_v_2001_1)) (or (< v_idx_360 v_b_131_4) (= (select |c_#memory_int| v_idx_360) v_v_1709_2)) (<= v_b_127_4 c_ULTIMATE.start_main_p2)))))) is different from false [2019-01-07 22:12:24,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:12:24,115 INFO L93 Difference]: Finished difference Result 12 states and 22 transitions. [2019-01-07 22:12:24,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-07 22:12:24,116 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-07 22:12:24,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:12:24,117 INFO L225 Difference]: With dead ends: 12 [2019-01-07 22:12:24,117 INFO L226 Difference]: Without dead ends: 11 [2019-01-07 22:12:24,118 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 10.1s TimeCoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-07 22:12:24,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2019-01-07 22:12:24,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2019-01-07 22:12:24,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11 states. [2019-01-07 22:12:24,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 21 transitions. [2019-01-07 22:12:24,126 INFO L78 Accepts]: Start accepts. Automaton has 11 states and 21 transitions. Word has length 4 [2019-01-07 22:12:24,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:12:24,127 INFO L480 AbstractCegarLoop]: Abstraction has 11 states and 21 transitions. [2019-01-07 22:12:24,127 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-07 22:12:24,127 INFO L276 IsEmpty]: Start isEmpty. Operand 11 states and 21 transitions. [2019-01-07 22:12:24,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-07 22:12:24,127 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:12:24,128 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1] [2019-01-07 22:12:24,128 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:12:24,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:12:24,128 INFO L82 PathProgramCache]: Analyzing trace with hash 929488, now seen corresponding path program 2 times [2019-01-07 22:12:24,128 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:12:24,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:12:24,129 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:12:24,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:12:24,129 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:12:24,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:12:24,175 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:12:24,176 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:12:24,176 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:12:24,176 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-07 22:12:24,177 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-07 22:12:24,177 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:12:24,177 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-07 22:12:24,187 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-07 22:12:24,187 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-07 22:12:24,196 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-07 22:12:24,196 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-07 22:12:24,202 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-07 22:12:24,232 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-07 22:12:24,240 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:12:24,241 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-07 22:12:24,281 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:12:24,304 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:12:24,305 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-07 22:12:24,306 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-07 22:12:24,419 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-07 22:12:24,425 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-07 22:12:24,438 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-07 22:12:24,439 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:19, output treesize:22 [2019-01-07 22:12:24,469 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:12:24,471 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:12:24,473 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:12:24,476 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:12:24,477 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 28 [2019-01-07 22:12:24,478 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-07 22:12:24,577 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-07 22:12:24,577 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-07 22:12:24,747 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:12:24,771 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:12:24,796 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:12:24,821 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:12:24,847 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:12:24,872 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:12:24,872 INFO L303 Elim1Store]: Index analysis took 163 ms [2019-01-07 22:12:24,873 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 40 [2019-01-07 22:12:24,874 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-07 22:12:24,946 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-07 22:12:24,947 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-07 22:12:24,964 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:12:24,964 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-07 22:12:24,971 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:12:24,991 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-01-07 22:12:24,991 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 7 [2019-01-07 22:12:24,991 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:12:24,992 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-07 22:12:24,992 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-07 22:12:24,992 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=41, Unknown=0, NotChecked=0, Total=72 [2019-01-07 22:12:24,993 INFO L87 Difference]: Start difference. First operand 11 states and 21 transitions. Second operand 5 states. [2019-01-07 22:12:25,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:12:25,085 INFO L93 Difference]: Finished difference Result 18 states and 40 transitions. [2019-01-07 22:12:25,086 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-07 22:12:25,086 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-07 22:12:25,086 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:12:25,087 INFO L225 Difference]: With dead ends: 18 [2019-01-07 22:12:25,087 INFO L226 Difference]: Without dead ends: 17 [2019-01-07 22:12:25,088 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=41, Unknown=0, NotChecked=0, Total=72 [2019-01-07 22:12:25,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2019-01-07 22:12:25,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 14. [2019-01-07 22:12:25,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2019-01-07 22:12:25,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 35 transitions. [2019-01-07 22:12:25,100 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 35 transitions. Word has length 4 [2019-01-07 22:12:25,100 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:12:25,100 INFO L480 AbstractCegarLoop]: Abstraction has 14 states and 35 transitions. [2019-01-07 22:12:25,100 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-07 22:12:25,100 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 35 transitions. [2019-01-07 22:12:25,101 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-07 22:12:25,101 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:12:25,101 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-07 22:12:25,101 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:12:25,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:12:25,102 INFO L82 PathProgramCache]: Analyzing trace with hash 929612, now seen corresponding path program 1 times [2019-01-07 22:12:25,102 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:12:25,103 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:12:25,103 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-07 22:12:25,103 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:12:25,103 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:12:25,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:12:25,418 WARN L181 SmtUtils]: Spent 270.00 ms on a formula simplification. DAG size of input: 17 DAG size of output: 9 [2019-01-07 22:12:25,452 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:12:25,453 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:12:25,453 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:12:25,453 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-07 22:12:25,453 INFO L207 CegarAbsIntRunner]: [0], [6], [10], [15] [2019-01-07 22:12:25,456 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-07 22:12:25,457 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-07 22:12:36,289 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-07 22:12:36,289 INFO L272 AbstractInterpreter]: Visited 4 different actions 31 times. Merged at 2 different actions 9 times. Widened at 2 different actions 5 times. Found 11 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-07 22:12:36,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:12:36,289 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-07 22:12:36,625 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 61.9% of their original sizes. [2019-01-07 22:12:36,625 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-07 22:12:39,106 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_465 Int) (v_idx_466 Int) (v_idx_460 Int) (v_idx_463 Int) (v_idx_464 Int) (v_idx_461 Int) (v_idx_462 Int)) (exists ((v_v_3679_1 Int) (v_v_3678_1 Int) (v_b_319_1 Int) (v_b_318_1 Int) (v_v_3675_1 Int) (v_v_3681_1 Int) (v_v_3677_1 Int) (v_v_3676_1 Int)) (let ((.cse1 (+ v_b_318_1 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_v_3678_1 v_v_3676_1) (<= 0 (* 2 v_v_3676_1)) (or (= (select |c_#memory_int| v_idx_461) v_v_3676_1) (< v_idx_461 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_461)) (<= v_b_319_1 .cse1) (or (< v_idx_465 v_b_318_1) (= (select |c_#memory_int| v_idx_465) 0) (<= v_b_319_1 v_idx_465)) (<= .cse1 v_b_319_1) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_318_1) (<= .cse2 v_b_318_1) (or (<= v_b_318_1 v_idx_464) (< v_idx_464 .cse2) (= (select |c_#memory_int| v_idx_464) v_v_3679_1)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_319_1) (<= 0 v_v_3676_1) (or (< v_idx_463 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_463) v_v_3678_1) (<= .cse2 v_idx_463)) (or (< v_idx_466 v_b_319_1) (= (select |c_#memory_int| v_idx_466) v_v_3681_1)) (<= (* 2 v_v_3678_1) 0) (<= .cse0 c_ULTIMATE.start_main_p2) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_319_1) (<= v_v_3678_1 0) (or (<= c_ULTIMATE.start_main_p2 v_idx_462) (< v_idx_462 .cse0) (= (select |c_#memory_int| v_idx_462) v_v_3677_1)) (or (= (select |c_#memory_int| v_idx_460) v_v_3675_1) (<= c_ULTIMATE.start_main_p1 v_idx_460)))))) is different from false [2019-01-07 22:12:41,554 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_467 Int) (v_idx_468 Int) (v_idx_469 Int) (v_idx_470 Int) (v_idx_471 Int) (v_idx_472 Int) (v_idx_473 Int)) (exists ((v_v_3679_1 Int) (v_v_3678_1 Int) (v_b_319_1 Int) (v_b_318_1 Int) (v_v_3675_1 Int) (v_v_3677_1 Int) (v_v_3681_1 Int) (v_v_3676_1 Int)) (let ((.cse1 (+ v_b_318_1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_467) (= (select |c_#memory_int| v_idx_467) v_v_3675_1)) (<= v_v_3678_1 v_v_3676_1) (<= 0 (* 2 v_v_3676_1)) (or (< v_idx_470 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_470) v_v_3678_1) (<= .cse0 v_idx_470)) (<= v_b_319_1 .cse1) (or (= (select |c_#memory_int| v_idx_473) v_v_3681_1) (< v_idx_473 v_b_319_1)) (<= .cse1 v_b_319_1) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_318_1) (or (<= c_ULTIMATE.start_main_p2 v_idx_469) (= (select |c_#memory_int| v_idx_469) v_v_3677_1) (< v_idx_469 .cse2)) (<= .cse0 v_b_318_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_319_1) (or (< v_idx_472 v_b_318_1) (<= v_b_319_1 v_idx_472) (= (select |c_#memory_int| v_idx_472) 0)) (<= 0 v_v_3676_1) (or (= (select |c_#memory_int| v_idx_471) v_v_3679_1) (<= v_b_318_1 v_idx_471) (< v_idx_471 .cse0)) (<= (* 2 v_v_3678_1) 0) (<= .cse2 c_ULTIMATE.start_main_p2) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_319_1) (<= v_v_3678_1 0) (or (= (select |c_#memory_int| v_idx_468) v_v_3676_1) (< v_idx_468 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_468)))))) is different from false [2019-01-07 22:12:44,401 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_478 Int) (v_idx_479 Int) (v_idx_476 Int) (v_idx_477 Int) (v_idx_480 Int) (v_idx_474 Int) (v_idx_475 Int)) (exists ((v_v_3679_1 Int) (v_b_317_1 Int) (v_v_3678_1 Int) (v_b_316_1 Int) (v_b_319_1 Int) (v_b_318_1 Int) (v_v_3675_1 Int) (v_v_3681_1 Int) (v_v_3677_1 Int) (v_v_3676_1 Int)) (let ((.cse1 (+ v_b_318_1 1)) (.cse0 (+ v_b_316_1 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_v_3678_1 v_v_3676_1) (<= 0 (* 2 v_v_3676_1)) (<= v_b_317_1 .cse0) (<= v_b_319_1 .cse1) (<= v_b_317_1 v_b_318_1) (<= .cse1 v_b_319_1) (<= .cse2 v_b_318_1) (<= .cse3 v_b_316_1) (<= (+ v_b_316_1 2) v_b_319_1) (<= .cse0 v_b_318_1) (<= (+ v_b_317_1 1) v_b_319_1) (or (= (select |c_#memory_int| v_idx_479) 0) (< v_idx_479 v_b_318_1) (<= v_b_319_1 v_idx_479)) (or (= (select |c_#memory_int| v_idx_477) v_v_3678_1) (<= v_b_317_1 v_idx_477) (< v_idx_477 v_b_316_1)) (<= .cse0 v_b_317_1) (or (= (select |c_#memory_int| v_idx_478) v_v_3679_1) (< v_idx_478 v_b_317_1) (<= v_b_318_1 v_idx_478)) (<= 0 v_v_3676_1) (or (= (select |c_#memory_int| v_idx_474) v_v_3675_1) (<= c_ULTIMATE.start_main_p1 v_idx_474)) (<= .cse2 v_b_317_1) (or (= (select |c_#memory_int| v_idx_475) v_v_3676_1) (<= .cse3 v_idx_475) (< v_idx_475 c_ULTIMATE.start_main_p1)) (or (< v_idx_480 v_b_319_1) (= (select |c_#memory_int| v_idx_480) v_v_3681_1)) (<= (* 2 v_v_3678_1) 0) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_319_1) (<= v_v_3678_1 0) (or (< v_idx_476 .cse3) (<= v_b_316_1 v_idx_476) (= (select |c_#memory_int| v_idx_476) v_v_3677_1)))))) is different from false [2019-01-07 22:12:44,481 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-07 22:12:44,481 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-07 22:12:44,482 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-07 22:12:44,482 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 6 [2019-01-07 22:12:44,482 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:12:44,482 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-07 22:12:44,482 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-07 22:12:44,483 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-07 22:12:44,483 INFO L87 Difference]: Start difference. First operand 14 states and 35 transitions. Second operand 5 states. [2019-01-07 22:12:47,012 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_467 Int) (v_idx_468 Int) (v_idx_469 Int) (v_idx_470 Int) (v_idx_471 Int) (v_idx_472 Int) (v_idx_473 Int)) (exists ((v_v_3679_1 Int) (v_v_3678_1 Int) (v_b_319_1 Int) (v_b_318_1 Int) (v_v_3675_1 Int) (v_v_3677_1 Int) (v_v_3681_1 Int) (v_v_3676_1 Int)) (let ((.cse1 (+ v_b_318_1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_467) (= (select |c_#memory_int| v_idx_467) v_v_3675_1)) (<= v_v_3678_1 v_v_3676_1) (<= 0 (* 2 v_v_3676_1)) (or (< v_idx_470 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_470) v_v_3678_1) (<= .cse0 v_idx_470)) (<= v_b_319_1 .cse1) (or (= (select |c_#memory_int| v_idx_473) v_v_3681_1) (< v_idx_473 v_b_319_1)) (<= .cse1 v_b_319_1) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_318_1) (or (<= c_ULTIMATE.start_main_p2 v_idx_469) (= (select |c_#memory_int| v_idx_469) v_v_3677_1) (< v_idx_469 .cse2)) (<= .cse0 v_b_318_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_319_1) (or (< v_idx_472 v_b_318_1) (<= v_b_319_1 v_idx_472) (= (select |c_#memory_int| v_idx_472) 0)) (<= 0 v_v_3676_1) (or (= (select |c_#memory_int| v_idx_471) v_v_3679_1) (<= v_b_318_1 v_idx_471) (< v_idx_471 .cse0)) (<= (* 2 v_v_3678_1) 0) (<= .cse2 c_ULTIMATE.start_main_p2) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_319_1) (<= v_v_3678_1 0) (or (= (select |c_#memory_int| v_idx_468) v_v_3676_1) (< v_idx_468 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_468)))))) (forall ((v_idx_465 Int) (v_idx_466 Int) (v_idx_460 Int) (v_idx_463 Int) (v_idx_464 Int) (v_idx_461 Int) (v_idx_462 Int)) (exists ((v_v_3679_1 Int) (v_v_3678_1 Int) (v_b_319_1 Int) (v_b_318_1 Int) (v_v_3675_1 Int) (v_v_3681_1 Int) (v_v_3677_1 Int) (v_v_3676_1 Int)) (let ((.cse4 (+ v_b_318_1 1)) (.cse5 (+ c_ULTIMATE.start_main_p2 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_v_3678_1 v_v_3676_1) (<= 0 (* 2 v_v_3676_1)) (or (= (select |c_#memory_int| v_idx_461) v_v_3676_1) (< v_idx_461 c_ULTIMATE.start_main_p1) (<= .cse3 v_idx_461)) (<= v_b_319_1 .cse4) (or (< v_idx_465 v_b_318_1) (= (select |c_#memory_int| v_idx_465) 0) (<= v_b_319_1 v_idx_465)) (<= .cse4 v_b_319_1) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_318_1) (<= .cse5 v_b_318_1) (or (<= v_b_318_1 v_idx_464) (< v_idx_464 .cse5) (= (select |c_#memory_int| v_idx_464) v_v_3679_1)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_319_1) (<= 0 v_v_3676_1) (or (< v_idx_463 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_463) v_v_3678_1) (<= .cse5 v_idx_463)) (or (< v_idx_466 v_b_319_1) (= (select |c_#memory_int| v_idx_466) v_v_3681_1)) (<= (* 2 v_v_3678_1) 0) (<= .cse3 c_ULTIMATE.start_main_p2) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_319_1) (<= v_v_3678_1 0) (or (<= c_ULTIMATE.start_main_p2 v_idx_462) (< v_idx_462 .cse3) (= (select |c_#memory_int| v_idx_462) v_v_3677_1)) (or (= (select |c_#memory_int| v_idx_460) v_v_3675_1) (<= c_ULTIMATE.start_main_p1 v_idx_460)))))) (forall ((v_idx_478 Int) (v_idx_479 Int) (v_idx_476 Int) (v_idx_477 Int) (v_idx_480 Int) (v_idx_474 Int) (v_idx_475 Int)) (exists ((v_v_3679_1 Int) (v_b_317_1 Int) (v_v_3678_1 Int) (v_b_316_1 Int) (v_b_319_1 Int) (v_b_318_1 Int) (v_v_3675_1 Int) (v_v_3681_1 Int) (v_v_3677_1 Int) (v_v_3676_1 Int)) (let ((.cse7 (+ v_b_318_1 1)) (.cse6 (+ v_b_316_1 1)) (.cse8 (+ c_ULTIMATE.start_main_p1 2)) (.cse9 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_v_3678_1 v_v_3676_1) (<= 0 (* 2 v_v_3676_1)) (<= v_b_317_1 .cse6) (<= v_b_319_1 .cse7) (<= v_b_317_1 v_b_318_1) (<= .cse7 v_b_319_1) (<= .cse8 v_b_318_1) (<= .cse9 v_b_316_1) (<= (+ v_b_316_1 2) v_b_319_1) (<= .cse6 v_b_318_1) (<= (+ v_b_317_1 1) v_b_319_1) (or (= (select |c_#memory_int| v_idx_479) 0) (< v_idx_479 v_b_318_1) (<= v_b_319_1 v_idx_479)) (or (= (select |c_#memory_int| v_idx_477) v_v_3678_1) (<= v_b_317_1 v_idx_477) (< v_idx_477 v_b_316_1)) (<= .cse6 v_b_317_1) (or (= (select |c_#memory_int| v_idx_478) v_v_3679_1) (< v_idx_478 v_b_317_1) (<= v_b_318_1 v_idx_478)) (<= 0 v_v_3676_1) (or (= (select |c_#memory_int| v_idx_474) v_v_3675_1) (<= c_ULTIMATE.start_main_p1 v_idx_474)) (<= .cse8 v_b_317_1) (or (= (select |c_#memory_int| v_idx_475) v_v_3676_1) (<= .cse9 v_idx_475) (< v_idx_475 c_ULTIMATE.start_main_p1)) (or (< v_idx_480 v_b_319_1) (= (select |c_#memory_int| v_idx_480) v_v_3681_1)) (<= (* 2 v_v_3678_1) 0) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_319_1) (<= v_v_3678_1 0) (or (< v_idx_476 .cse9) (<= v_b_316_1 v_idx_476) (= (select |c_#memory_int| v_idx_476) v_v_3677_1))))))) is different from false [2019-01-07 22:13:13,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:13:13,061 INFO L93 Difference]: Finished difference Result 16 states and 40 transitions. [2019-01-07 22:13:13,061 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-07 22:13:13,061 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-07 22:13:13,062 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:13:13,062 INFO L225 Difference]: With dead ends: 16 [2019-01-07 22:13:13,062 INFO L226 Difference]: Without dead ends: 15 [2019-01-07 22:13:13,063 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 10.3s TimeCoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-07 22:13:13,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states. [2019-01-07 22:13:13,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 14. [2019-01-07 22:13:13,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2019-01-07 22:13:13,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 35 transitions. [2019-01-07 22:13:13,073 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 35 transitions. Word has length 4 [2019-01-07 22:13:13,073 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:13:13,073 INFO L480 AbstractCegarLoop]: Abstraction has 14 states and 35 transitions. [2019-01-07 22:13:13,073 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-07 22:13:13,074 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 35 transitions. [2019-01-07 22:13:13,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-07 22:13:13,074 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:13:13,074 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-07 22:13:13,074 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:13:13,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:13:13,075 INFO L82 PathProgramCache]: Analyzing trace with hash 933644, now seen corresponding path program 1 times [2019-01-07 22:13:13,075 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:13:13,076 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:13:13,076 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:13:13,076 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:13:13,076 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:13:13,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:13:13,116 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:13:13,116 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:13:13,116 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:13:13,116 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-07 22:13:13,116 INFO L207 CegarAbsIntRunner]: [0], [10], [16], [17] [2019-01-07 22:13:13,117 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-07 22:13:13,117 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-07 22:13:18,281 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-07 22:13:18,281 INFO L272 AbstractInterpreter]: Visited 4 different actions 16 times. Merged at 2 different actions 8 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-07 22:13:18,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:13:18,282 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-07 22:13:18,584 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 61.9% of their original sizes. [2019-01-07 22:13:18,584 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-07 22:13:21,045 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_586 Int) (v_idx_580 Int) (v_idx_581 Int) (v_idx_584 Int) (v_idx_585 Int) (v_idx_582 Int) (v_idx_583 Int)) (exists ((v_v_1508_6 Int) (v_v_1514_6 Int) (v_v_1512_6 Int) (v_v_1511_6 Int) (v_v_1510_6 Int) (v_b_121_6 Int) (v_b_120_6 Int)) (let ((.cse0 (+ v_b_120_6 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) v_b_120_6) (<= v_b_121_6 .cse0) (or (< v_idx_581 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_581) (= (select |c_#memory_int| v_idx_581) 0)) (or (<= v_b_121_6 v_idx_585) (= (select |c_#memory_int| v_idx_585) 0) (< v_idx_585 v_b_120_6)) (<= v_v_1511_6 0) (<= .cse2 v_b_120_6) (or (= (select |c_#memory_int| v_idx_586) v_v_1514_6) (< v_idx_586 v_b_121_6)) (<= .cse0 v_b_121_6) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_121_6) (or (< v_idx_583 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_583) v_v_1511_6) (<= .cse2 v_idx_583)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_121_6) (<= (* 2 v_v_1511_6) 0) (or (< v_idx_584 .cse2) (<= v_b_120_6 v_idx_584) (= (select |c_#memory_int| v_idx_584) v_v_1512_6)) (or (<= c_ULTIMATE.start_main_p1 v_idx_580) (= (select |c_#memory_int| v_idx_580) v_v_1508_6)) (or (= (select |c_#memory_int| v_idx_582) v_v_1510_6) (< v_idx_582 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_582)) (<= .cse1 c_ULTIMATE.start_main_p2))))) is different from false [2019-01-07 22:13:23,269 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_588 Int) (v_idx_589 Int) (v_idx_587 Int) (v_idx_591 Int) (v_idx_592 Int) (v_idx_590 Int) (v_idx_593 Int)) (exists ((v_v_1508_6 Int) (v_v_1514_6 Int) (v_v_1512_6 Int) (v_v_1511_6 Int) (v_v_1510_6 Int) (v_b_121_6 Int) (v_b_120_6 Int)) (let ((.cse0 (+ v_b_120_6 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) v_b_120_6) (<= v_b_121_6 .cse0) (or (< v_idx_590 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_590) v_v_1511_6) (<= .cse1 v_idx_590)) (<= v_v_1511_6 0) (or (< v_idx_588 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_588) (= (select |c_#memory_int| v_idx_588) 0)) (or (= (select |c_#memory_int| v_idx_587) v_v_1508_6) (<= c_ULTIMATE.start_main_p1 v_idx_587)) (<= .cse1 v_b_120_6) (or (= 0 (select |c_#memory_int| v_idx_592)) (< v_idx_592 v_b_120_6) (<= v_b_121_6 v_idx_592)) (<= .cse0 v_b_121_6) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_121_6) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_121_6) (or (< v_idx_591 .cse1) (= (select |c_#memory_int| v_idx_591) v_v_1512_6) (<= v_b_120_6 v_idx_591)) (<= (* 2 v_v_1511_6) 0) (or (< v_idx_589 .cse2) (= (select |c_#memory_int| v_idx_589) v_v_1510_6) (<= c_ULTIMATE.start_main_p2 v_idx_589)) (<= .cse2 c_ULTIMATE.start_main_p2) (or (< v_idx_593 v_b_121_6) (= (select |c_#memory_int| v_idx_593) v_v_1514_6)))))) is different from false [2019-01-07 22:13:25,436 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_599 Int) (v_idx_600 Int) (v_idx_597 Int) (v_idx_598 Int) (v_idx_595 Int) (v_idx_596 Int) (v_idx_594 Int)) (exists ((v_v_1508_6 Int) (v_b_117_6 Int) (v_b_128_6 Int) (v_v_1514_6 Int) (v_v_1512_6 Int) (v_v_1511_6 Int) (v_v_1510_6 Int) (v_b_121_6 Int) (v_b_120_6 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_128_6 1)) (.cse2 (+ v_b_120_6 1))) (and (<= .cse0 v_b_117_6) (or (= (select |c_#memory_int| v_idx_597) v_v_1511_6) (< v_idx_597 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_597)) (<= v_b_121_6 .cse2) (or (= (select |c_#memory_int| v_idx_596) v_v_1510_6) (<= c_ULTIMATE.start_main_p2 v_idx_596) (< v_idx_596 v_b_117_6)) (or (= (select |c_#memory_int| v_idx_600) v_v_1514_6) (< v_idx_600 v_b_121_6)) (<= v_v_1511_6 0) (<= .cse1 v_b_120_6) (or (<= v_b_120_6 v_idx_598) (< v_idx_598 .cse1) (= (select |c_#memory_int| v_idx_598) v_v_1512_6)) (<= (+ v_b_128_6 2) v_b_120_6) (<= v_b_117_6 .cse0) (<= .cse0 c_ULTIMATE.start_main_p2) (<= .cse2 v_b_121_6) (<= (+ v_b_117_6 1) v_b_120_6) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_121_6) (<= (* 2 v_v_1511_6) 0) (<= v_b_117_6 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_599) 0) (<= v_b_121_6 v_idx_599) (< v_idx_599 v_b_120_6)) (<= (+ v_b_128_6 3) v_b_121_6) (<= (+ v_b_117_6 2) v_b_121_6) (or (<= v_b_128_6 v_idx_594) (= (select |c_#memory_int| v_idx_594) v_v_1508_6)) (or (<= v_b_117_6 v_idx_595) (< v_idx_595 v_b_128_6) (= (select |c_#memory_int| v_idx_595) 0)))))) is different from false [2019-01-07 22:13:25,513 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-07 22:13:25,514 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-07 22:13:25,514 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-07 22:13:25,514 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [2] total 5 [2019-01-07 22:13:25,514 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:13:25,514 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-07 22:13:25,515 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-07 22:13:25,515 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-07 22:13:25,515 INFO L87 Difference]: Start difference. First operand 14 states and 35 transitions. Second operand 5 states. [2019-01-07 22:13:27,918 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_599 Int) (v_idx_600 Int) (v_idx_597 Int) (v_idx_598 Int) (v_idx_595 Int) (v_idx_596 Int) (v_idx_594 Int)) (exists ((v_v_1508_6 Int) (v_b_117_6 Int) (v_b_128_6 Int) (v_v_1514_6 Int) (v_v_1512_6 Int) (v_v_1511_6 Int) (v_v_1510_6 Int) (v_b_121_6 Int) (v_b_120_6 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_128_6 1)) (.cse2 (+ v_b_120_6 1))) (and (<= .cse0 v_b_117_6) (or (= (select |c_#memory_int| v_idx_597) v_v_1511_6) (< v_idx_597 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_597)) (<= v_b_121_6 .cse2) (or (= (select |c_#memory_int| v_idx_596) v_v_1510_6) (<= c_ULTIMATE.start_main_p2 v_idx_596) (< v_idx_596 v_b_117_6)) (or (= (select |c_#memory_int| v_idx_600) v_v_1514_6) (< v_idx_600 v_b_121_6)) (<= v_v_1511_6 0) (<= .cse1 v_b_120_6) (or (<= v_b_120_6 v_idx_598) (< v_idx_598 .cse1) (= (select |c_#memory_int| v_idx_598) v_v_1512_6)) (<= (+ v_b_128_6 2) v_b_120_6) (<= v_b_117_6 .cse0) (<= .cse0 c_ULTIMATE.start_main_p2) (<= .cse2 v_b_121_6) (<= (+ v_b_117_6 1) v_b_120_6) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_121_6) (<= (* 2 v_v_1511_6) 0) (<= v_b_117_6 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_599) 0) (<= v_b_121_6 v_idx_599) (< v_idx_599 v_b_120_6)) (<= (+ v_b_128_6 3) v_b_121_6) (<= (+ v_b_117_6 2) v_b_121_6) (or (<= v_b_128_6 v_idx_594) (= (select |c_#memory_int| v_idx_594) v_v_1508_6)) (or (<= v_b_117_6 v_idx_595) (< v_idx_595 v_b_128_6) (= (select |c_#memory_int| v_idx_595) 0)))))) (forall ((v_idx_588 Int) (v_idx_589 Int) (v_idx_587 Int) (v_idx_591 Int) (v_idx_592 Int) (v_idx_590 Int) (v_idx_593 Int)) (exists ((v_v_1508_6 Int) (v_v_1514_6 Int) (v_v_1512_6 Int) (v_v_1511_6 Int) (v_v_1510_6 Int) (v_b_121_6 Int) (v_b_120_6 Int)) (let ((.cse3 (+ v_b_120_6 1)) (.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) v_b_120_6) (<= v_b_121_6 .cse3) (or (< v_idx_590 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_590) v_v_1511_6) (<= .cse4 v_idx_590)) (<= v_v_1511_6 0) (or (< v_idx_588 c_ULTIMATE.start_main_p1) (<= .cse5 v_idx_588) (= (select |c_#memory_int| v_idx_588) 0)) (or (= (select |c_#memory_int| v_idx_587) v_v_1508_6) (<= c_ULTIMATE.start_main_p1 v_idx_587)) (<= .cse4 v_b_120_6) (or (= 0 (select |c_#memory_int| v_idx_592)) (< v_idx_592 v_b_120_6) (<= v_b_121_6 v_idx_592)) (<= .cse3 v_b_121_6) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_121_6) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_121_6) (or (< v_idx_591 .cse4) (= (select |c_#memory_int| v_idx_591) v_v_1512_6) (<= v_b_120_6 v_idx_591)) (<= (* 2 v_v_1511_6) 0) (or (< v_idx_589 .cse5) (= (select |c_#memory_int| v_idx_589) v_v_1510_6) (<= c_ULTIMATE.start_main_p2 v_idx_589)) (<= .cse5 c_ULTIMATE.start_main_p2) (or (< v_idx_593 v_b_121_6) (= (select |c_#memory_int| v_idx_593) v_v_1514_6)))))) (forall ((v_idx_586 Int) (v_idx_580 Int) (v_idx_581 Int) (v_idx_584 Int) (v_idx_585 Int) (v_idx_582 Int) (v_idx_583 Int)) (exists ((v_v_1508_6 Int) (v_v_1514_6 Int) (v_v_1512_6 Int) (v_v_1511_6 Int) (v_v_1510_6 Int) (v_b_121_6 Int) (v_b_120_6 Int)) (let ((.cse6 (+ v_b_120_6 1)) (.cse8 (+ c_ULTIMATE.start_main_p2 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) v_b_120_6) (<= v_b_121_6 .cse6) (or (< v_idx_581 c_ULTIMATE.start_main_p1) (<= .cse7 v_idx_581) (= (select |c_#memory_int| v_idx_581) 0)) (or (<= v_b_121_6 v_idx_585) (= (select |c_#memory_int| v_idx_585) 0) (< v_idx_585 v_b_120_6)) (<= v_v_1511_6 0) (<= .cse8 v_b_120_6) (or (= (select |c_#memory_int| v_idx_586) v_v_1514_6) (< v_idx_586 v_b_121_6)) (<= .cse6 v_b_121_6) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_121_6) (or (< v_idx_583 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_583) v_v_1511_6) (<= .cse8 v_idx_583)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_121_6) (<= (* 2 v_v_1511_6) 0) (or (< v_idx_584 .cse8) (<= v_b_120_6 v_idx_584) (= (select |c_#memory_int| v_idx_584) v_v_1512_6)) (or (<= c_ULTIMATE.start_main_p1 v_idx_580) (= (select |c_#memory_int| v_idx_580) v_v_1508_6)) (or (= (select |c_#memory_int| v_idx_582) v_v_1510_6) (< v_idx_582 .cse7) (<= c_ULTIMATE.start_main_p2 v_idx_582)) (<= .cse7 c_ULTIMATE.start_main_p2)))))) is different from false [2019-01-07 22:13:42,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:13:42,910 INFO L93 Difference]: Finished difference Result 17 states and 41 transitions. [2019-01-07 22:13:42,910 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-07 22:13:42,910 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-07 22:13:42,911 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:13:42,911 INFO L225 Difference]: With dead ends: 17 [2019-01-07 22:13:42,911 INFO L226 Difference]: Without dead ends: 16 [2019-01-07 22:13:42,912 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 9.3s TimeCoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-07 22:13:42,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-07 22:13:42,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2019-01-07 22:13:42,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-07 22:13:42,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 39 transitions. [2019-01-07 22:13:42,925 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 39 transitions. Word has length 4 [2019-01-07 22:13:42,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:13:42,925 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 39 transitions. [2019-01-07 22:13:42,925 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-07 22:13:42,925 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 39 transitions. [2019-01-07 22:13:42,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-07 22:13:42,926 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:13:42,926 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1] [2019-01-07 22:13:42,926 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:13:42,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:13:42,926 INFO L82 PathProgramCache]: Analyzing trace with hash 933456, now seen corresponding path program 2 times [2019-01-07 22:13:42,927 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:13:42,927 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:13:42,927 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:13:42,928 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:13:42,928 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:13:42,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:13:42,990 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-07 22:13:42,990 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:13:42,990 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:13:42,990 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-07 22:13:42,991 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-07 22:13:42,991 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:13:42,991 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-07 22:13:43,000 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-07 22:13:43,000 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-07 22:13:43,005 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-07 22:13:43,006 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-07 22:13:43,007 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-07 22:13:43,014 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-07 22:13:43,021 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:13:43,021 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-07 22:13:43,037 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:13:43,040 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:13:43,041 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-07 22:13:43,042 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-07 22:13:43,058 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-07 22:13:43,067 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-07 22:13:43,085 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-07 22:13:43,085 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:19, output treesize:22 [2019-01-07 22:13:43,120 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:13:43,126 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:13:43,127 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:13:43,127 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:13:43,128 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-07 22:13:43,129 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-07 22:13:43,164 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-07 22:13:43,165 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-07 22:13:43,185 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:13:43,189 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:13:43,192 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:13:43,193 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:13:43,193 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:13:43,194 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:13:43,195 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 40 [2019-01-07 22:13:43,196 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-07 22:13:43,221 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-07 22:13:43,222 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:22 [2019-01-07 22:13:43,243 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:13:43,244 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-07 22:13:43,292 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:13:43,311 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-07 22:13:43,312 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 3, 3] total 8 [2019-01-07 22:13:43,312 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-07 22:13:43,312 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-01-07 22:13:43,312 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-01-07 22:13:43,312 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=53, Unknown=0, NotChecked=0, Total=90 [2019-01-07 22:13:43,312 INFO L87 Difference]: Start difference. First operand 15 states and 39 transitions. Second operand 7 states. [2019-01-07 22:13:43,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:13:43,592 INFO L93 Difference]: Finished difference Result 29 states and 57 transitions. [2019-01-07 22:13:43,593 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-07 22:13:43,593 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 4 [2019-01-07 22:13:43,593 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:13:43,596 INFO L225 Difference]: With dead ends: 29 [2019-01-07 22:13:43,596 INFO L226 Difference]: Without dead ends: 28 [2019-01-07 22:13:43,597 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-01-07 22:13:43,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2019-01-07 22:13:43,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 17. [2019-01-07 22:13:43,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2019-01-07 22:13:43,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 47 transitions. [2019-01-07 22:13:43,614 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 47 transitions. Word has length 4 [2019-01-07 22:13:43,614 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:13:43,614 INFO L480 AbstractCegarLoop]: Abstraction has 17 states and 47 transitions. [2019-01-07 22:13:43,614 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-01-07 22:13:43,614 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 47 transitions. [2019-01-07 22:13:43,614 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-07 22:13:43,615 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:13:43,615 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-07 22:13:43,615 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:13:43,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:13:43,615 INFO L82 PathProgramCache]: Analyzing trace with hash 933518, now seen corresponding path program 1 times [2019-01-07 22:13:43,615 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:13:43,616 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:13:43,616 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-07 22:13:43,616 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:13:43,616 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:13:43,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:13:43,733 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:13:43,733 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:13:43,733 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:13:43,733 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-07 22:13:43,733 INFO L207 CegarAbsIntRunner]: [0], [10], [12], [15] [2019-01-07 22:13:43,734 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-07 22:13:43,734 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-07 22:13:53,052 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-07 22:13:53,052 INFO L272 AbstractInterpreter]: Visited 4 different actions 28 times. Merged at 2 different actions 8 times. Widened at 2 different actions 4 times. Found 10 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-07 22:13:53,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:13:53,053 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-07 22:13:53,380 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 57.14% of their original sizes. [2019-01-07 22:13:53,380 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-07 22:13:55,851 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_702 Int) (v_idx_703 Int) (v_idx_700 Int) (v_idx_701 Int) (v_idx_706 Int) (v_idx_704 Int) (v_idx_705 Int)) (exists ((v_v_3095_2 Int) (v_v_3096_2 Int) (v_v_3094_2 Int) (v_v_3092_2 Int) (v_v_3097_2 Int) (v_v_3098_2 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= v_v_3095_2 0) (<= 0 v_v_3097_2) (<= (* 2 v_v_3095_2) 0) (or (= (select |c_#memory_int| v_idx_705) v_v_3097_2) (< v_idx_705 c_ULTIMATE.start_main_p3) (<= .cse0 v_idx_705)) (or (<= c_ULTIMATE.start_main_p1 v_idx_700) (= (select |c_#memory_int| v_idx_700) v_v_3092_2)) (or (< v_idx_702 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_702) (= (select |c_#memory_int| v_idx_702) v_v_3094_2)) (<= 0 (* 2 v_v_3097_2)) (or (< v_idx_706 .cse0) (= (select |c_#memory_int| v_idx_706) v_v_3098_2)) (<= .cse2 c_ULTIMATE.start_main_p3) (<= v_v_3095_2 v_v_3097_2) (or (<= .cse2 v_idx_703) (= (select |c_#memory_int| v_idx_703) v_v_3095_2) (< v_idx_703 c_ULTIMATE.start_main_p2)) (or (<= c_ULTIMATE.start_main_p3 v_idx_704) (< v_idx_704 .cse2) (= (select |c_#memory_int| v_idx_704) v_v_3096_2)) (or (= (select |c_#memory_int| v_idx_701) 0) (<= .cse1 v_idx_701) (< v_idx_701 c_ULTIMATE.start_main_p1)) (<= .cse1 c_ULTIMATE.start_main_p2))))) is different from false [2019-01-07 22:13:58,520 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_710 Int) (v_idx_713 Int) (v_idx_711 Int) (v_idx_712 Int) (v_idx_707 Int) (v_idx_708 Int) (v_idx_709 Int)) (exists ((v_v_3095_2 Int) (v_v_3096_2 Int) (v_v_3094_2 Int) (v_v_3092_2 Int) (v_b_255_4 Int) (v_b_254_4 Int) (v_v_3097_2 Int) (v_v_3098_2 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ v_b_254_4 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse0 v_b_254_4) (<= .cse1 c_ULTIMATE.start_main_p3) (<= v_v_3095_2 0) (<= 0 v_v_3097_2) (<= (* 2 v_v_3095_2) 0) (<= v_b_255_4 .cse2) (or (= (select |c_#memory_int| v_idx_707) v_v_3092_2) (<= c_ULTIMATE.start_main_p1 v_idx_707)) (<= v_b_255_4 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_3097_2)) (<= .cse2 v_b_255_4) (or (= (select |c_#memory_int| v_idx_708) 0) (<= .cse0 v_idx_708) (< v_idx_708 c_ULTIMATE.start_main_p1)) (or (<= v_b_254_4 v_idx_709) (= (select |c_#memory_int| v_idx_709) v_v_3094_2) (< v_idx_709 .cse0)) (or (<= v_b_255_4 v_idx_710) (= (select |c_#memory_int| v_idx_710) v_v_3095_2) (< v_idx_710 v_b_254_4)) (<= v_v_3095_2 v_v_3097_2) (or (= (select |c_#memory_int| v_idx_711) v_v_3096_2) (<= c_ULTIMATE.start_main_p3 v_idx_711) (< v_idx_711 v_b_255_4)) (or (<= .cse3 v_idx_712) (< v_idx_712 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_712) v_v_3097_2)) (<= .cse2 c_ULTIMATE.start_main_p3) (<= .cse1 v_b_255_4) (or (< v_idx_713 .cse3) (= (select |c_#memory_int| v_idx_713) v_v_3098_2)))))) is different from false [2019-01-07 22:14:00,856 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_720 Int) (v_idx_714 Int) (v_idx_717 Int) (v_idx_718 Int) (v_idx_715 Int) (v_idx_716 Int) (v_idx_719 Int)) (exists ((v_v_3095_2 Int) (v_v_3096_2 Int) (v_v_3094_2 Int) (v_v_3092_2 Int) (v_b_255_4 Int) (v_b_256_3 Int) (v_b_254_4 Int) (v_v_3097_2 Int) (v_b_257_3 Int) (v_v_3098_2 Int)) (let ((.cse2 (+ v_b_256_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ v_b_254_4 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 2))) (and (<= .cse0 v_b_254_4) (<= .cse1 v_b_256_3) (<= v_v_3095_2 0) (<= .cse2 v_b_257_3) (<= 0 v_v_3097_2) (or (<= v_b_255_4 v_idx_717) (= (select |c_#memory_int| v_idx_717) v_v_3095_2) (< v_idx_717 v_b_254_4)) (<= (* 2 v_v_3095_2) 0) (<= v_b_255_4 .cse3) (or (= (select |c_#memory_int| v_idx_720) v_v_3098_2) (< v_idx_720 v_b_257_3)) (or (< v_idx_718 v_b_255_4) (<= v_b_256_3 v_idx_718) (= (select |c_#memory_int| v_idx_718) v_v_3096_2)) (<= v_b_257_3 .cse2) (or (<= .cse0 v_idx_715) (< v_idx_715 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_715) 0)) (<= 0 (* 2 v_v_3097_2)) (or (< v_idx_716 .cse0) (<= v_b_254_4 v_idx_716) (= (select |c_#memory_int| v_idx_716) v_v_3094_2)) (<= .cse3 v_b_255_4) (<= v_b_255_4 v_b_256_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_257_3) (<= (+ v_b_254_4 2) v_b_257_3) (<= v_v_3095_2 v_v_3097_2) (<= .cse3 v_b_256_3) (<= (+ v_b_255_4 1) v_b_257_3) (or (= (select |c_#memory_int| v_idx_714) v_v_3092_2) (<= c_ULTIMATE.start_main_p1 v_idx_714)) (<= .cse1 v_b_255_4) (or (= (select |c_#memory_int| v_idx_719) v_v_3097_2) (<= v_b_257_3 v_idx_719) (< v_idx_719 v_b_256_3)))))) is different from false [2019-01-07 22:14:00,933 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-07 22:14:00,934 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-07 22:14:00,934 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-07 22:14:00,934 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 6 [2019-01-07 22:14:00,934 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:14:00,934 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-07 22:14:00,934 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-07 22:14:00,934 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-07 22:14:00,935 INFO L87 Difference]: Start difference. First operand 17 states and 47 transitions. Second operand 5 states. [2019-01-07 22:14:03,473 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_720 Int) (v_idx_714 Int) (v_idx_717 Int) (v_idx_718 Int) (v_idx_715 Int) (v_idx_716 Int) (v_idx_719 Int)) (exists ((v_v_3095_2 Int) (v_v_3096_2 Int) (v_v_3094_2 Int) (v_v_3092_2 Int) (v_b_255_4 Int) (v_b_256_3 Int) (v_b_254_4 Int) (v_v_3097_2 Int) (v_b_257_3 Int) (v_v_3098_2 Int)) (let ((.cse2 (+ v_b_256_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ v_b_254_4 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 2))) (and (<= .cse0 v_b_254_4) (<= .cse1 v_b_256_3) (<= v_v_3095_2 0) (<= .cse2 v_b_257_3) (<= 0 v_v_3097_2) (or (<= v_b_255_4 v_idx_717) (= (select |c_#memory_int| v_idx_717) v_v_3095_2) (< v_idx_717 v_b_254_4)) (<= (* 2 v_v_3095_2) 0) (<= v_b_255_4 .cse3) (or (= (select |c_#memory_int| v_idx_720) v_v_3098_2) (< v_idx_720 v_b_257_3)) (or (< v_idx_718 v_b_255_4) (<= v_b_256_3 v_idx_718) (= (select |c_#memory_int| v_idx_718) v_v_3096_2)) (<= v_b_257_3 .cse2) (or (<= .cse0 v_idx_715) (< v_idx_715 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_715) 0)) (<= 0 (* 2 v_v_3097_2)) (or (< v_idx_716 .cse0) (<= v_b_254_4 v_idx_716) (= (select |c_#memory_int| v_idx_716) v_v_3094_2)) (<= .cse3 v_b_255_4) (<= v_b_255_4 v_b_256_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_257_3) (<= (+ v_b_254_4 2) v_b_257_3) (<= v_v_3095_2 v_v_3097_2) (<= .cse3 v_b_256_3) (<= (+ v_b_255_4 1) v_b_257_3) (or (= (select |c_#memory_int| v_idx_714) v_v_3092_2) (<= c_ULTIMATE.start_main_p1 v_idx_714)) (<= .cse1 v_b_255_4) (or (= (select |c_#memory_int| v_idx_719) v_v_3097_2) (<= v_b_257_3 v_idx_719) (< v_idx_719 v_b_256_3)))))) (forall ((v_idx_710 Int) (v_idx_713 Int) (v_idx_711 Int) (v_idx_712 Int) (v_idx_707 Int) (v_idx_708 Int) (v_idx_709 Int)) (exists ((v_v_3095_2 Int) (v_v_3096_2 Int) (v_v_3094_2 Int) (v_v_3092_2 Int) (v_b_255_4 Int) (v_b_254_4 Int) (v_v_3097_2 Int) (v_v_3098_2 Int)) (let ((.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse6 (+ v_b_254_4 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse4 v_b_254_4) (<= .cse5 c_ULTIMATE.start_main_p3) (<= v_v_3095_2 0) (<= 0 v_v_3097_2) (<= (* 2 v_v_3095_2) 0) (<= v_b_255_4 .cse6) (or (= (select |c_#memory_int| v_idx_707) v_v_3092_2) (<= c_ULTIMATE.start_main_p1 v_idx_707)) (<= v_b_255_4 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_3097_2)) (<= .cse6 v_b_255_4) (or (= (select |c_#memory_int| v_idx_708) 0) (<= .cse4 v_idx_708) (< v_idx_708 c_ULTIMATE.start_main_p1)) (or (<= v_b_254_4 v_idx_709) (= (select |c_#memory_int| v_idx_709) v_v_3094_2) (< v_idx_709 .cse4)) (or (<= v_b_255_4 v_idx_710) (= (select |c_#memory_int| v_idx_710) v_v_3095_2) (< v_idx_710 v_b_254_4)) (<= v_v_3095_2 v_v_3097_2) (or (= (select |c_#memory_int| v_idx_711) v_v_3096_2) (<= c_ULTIMATE.start_main_p3 v_idx_711) (< v_idx_711 v_b_255_4)) (or (<= .cse7 v_idx_712) (< v_idx_712 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_712) v_v_3097_2)) (<= .cse6 c_ULTIMATE.start_main_p3) (<= .cse5 v_b_255_4) (or (< v_idx_713 .cse7) (= (select |c_#memory_int| v_idx_713) v_v_3098_2)))))) (forall ((v_idx_702 Int) (v_idx_703 Int) (v_idx_700 Int) (v_idx_701 Int) (v_idx_706 Int) (v_idx_704 Int) (v_idx_705 Int)) (exists ((v_v_3095_2 Int) (v_v_3096_2 Int) (v_v_3094_2 Int) (v_v_3092_2 Int) (v_v_3097_2 Int) (v_v_3098_2 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p3 1)) (.cse10 (+ c_ULTIMATE.start_main_p2 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= v_v_3095_2 0) (<= 0 v_v_3097_2) (<= (* 2 v_v_3095_2) 0) (or (= (select |c_#memory_int| v_idx_705) v_v_3097_2) (< v_idx_705 c_ULTIMATE.start_main_p3) (<= .cse8 v_idx_705)) (or (<= c_ULTIMATE.start_main_p1 v_idx_700) (= (select |c_#memory_int| v_idx_700) v_v_3092_2)) (or (< v_idx_702 .cse9) (<= c_ULTIMATE.start_main_p2 v_idx_702) (= (select |c_#memory_int| v_idx_702) v_v_3094_2)) (<= 0 (* 2 v_v_3097_2)) (or (< v_idx_706 .cse8) (= (select |c_#memory_int| v_idx_706) v_v_3098_2)) (<= .cse10 c_ULTIMATE.start_main_p3) (<= v_v_3095_2 v_v_3097_2) (or (<= .cse10 v_idx_703) (= (select |c_#memory_int| v_idx_703) v_v_3095_2) (< v_idx_703 c_ULTIMATE.start_main_p2)) (or (<= c_ULTIMATE.start_main_p3 v_idx_704) (< v_idx_704 .cse10) (= (select |c_#memory_int| v_idx_704) v_v_3096_2)) (or (= (select |c_#memory_int| v_idx_701) 0) (<= .cse9 v_idx_701) (< v_idx_701 c_ULTIMATE.start_main_p1)) (<= .cse9 c_ULTIMATE.start_main_p2)))))) is different from false [2019-01-07 22:14:18,170 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_720 Int) (v_idx_714 Int) (v_idx_717 Int) (v_idx_718 Int) (v_idx_715 Int) (v_idx_716 Int) (v_idx_719 Int)) (exists ((v_v_3095_2 Int) (v_v_3096_2 Int) (v_v_3094_2 Int) (v_v_3092_2 Int) (v_b_255_4 Int) (v_b_256_3 Int) (v_b_254_4 Int) (v_v_3097_2 Int) (v_b_257_3 Int) (v_v_3098_2 Int)) (let ((.cse2 (+ v_b_256_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ v_b_254_4 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 2))) (and (<= .cse0 v_b_254_4) (<= .cse1 v_b_256_3) (<= v_v_3095_2 0) (<= .cse2 v_b_257_3) (<= 0 v_v_3097_2) (or (<= v_b_255_4 v_idx_717) (= (select |c_#memory_int| v_idx_717) v_v_3095_2) (< v_idx_717 v_b_254_4)) (<= (* 2 v_v_3095_2) 0) (<= v_b_255_4 .cse3) (or (= (select |c_#memory_int| v_idx_720) v_v_3098_2) (< v_idx_720 v_b_257_3)) (or (< v_idx_718 v_b_255_4) (<= v_b_256_3 v_idx_718) (= (select |c_#memory_int| v_idx_718) v_v_3096_2)) (<= v_b_257_3 .cse2) (or (<= .cse0 v_idx_715) (< v_idx_715 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_715) 0)) (<= 0 (* 2 v_v_3097_2)) (or (< v_idx_716 .cse0) (<= v_b_254_4 v_idx_716) (= (select |c_#memory_int| v_idx_716) v_v_3094_2)) (<= .cse3 v_b_255_4) (<= v_b_255_4 v_b_256_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_257_3) (<= (+ v_b_254_4 2) v_b_257_3) (<= v_v_3095_2 v_v_3097_2) (<= .cse3 v_b_256_3) (<= (+ v_b_255_4 1) v_b_257_3) (or (= (select |c_#memory_int| v_idx_714) v_v_3092_2) (<= c_ULTIMATE.start_main_p1 v_idx_714)) (<= .cse1 v_b_255_4) (or (= (select |c_#memory_int| v_idx_719) v_v_3097_2) (<= v_b_257_3 v_idx_719) (< v_idx_719 v_b_256_3)))))) (forall ((v_idx_710 Int) (v_idx_713 Int) (v_idx_711 Int) (v_idx_712 Int) (v_idx_707 Int) (v_idx_708 Int) (v_idx_709 Int)) (exists ((v_v_3095_2 Int) (v_v_3096_2 Int) (v_v_3094_2 Int) (v_v_3092_2 Int) (v_b_255_4 Int) (v_b_254_4 Int) (v_v_3097_2 Int) (v_v_3098_2 Int)) (let ((.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse6 (+ v_b_254_4 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse4 v_b_254_4) (<= .cse5 c_ULTIMATE.start_main_p3) (<= v_v_3095_2 0) (<= 0 v_v_3097_2) (<= (* 2 v_v_3095_2) 0) (<= v_b_255_4 .cse6) (or (= (select |c_#memory_int| v_idx_707) v_v_3092_2) (<= c_ULTIMATE.start_main_p1 v_idx_707)) (<= v_b_255_4 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_3097_2)) (<= .cse6 v_b_255_4) (or (= (select |c_#memory_int| v_idx_708) 0) (<= .cse4 v_idx_708) (< v_idx_708 c_ULTIMATE.start_main_p1)) (or (<= v_b_254_4 v_idx_709) (= (select |c_#memory_int| v_idx_709) v_v_3094_2) (< v_idx_709 .cse4)) (or (<= v_b_255_4 v_idx_710) (= (select |c_#memory_int| v_idx_710) v_v_3095_2) (< v_idx_710 v_b_254_4)) (<= v_v_3095_2 v_v_3097_2) (or (= (select |c_#memory_int| v_idx_711) v_v_3096_2) (<= c_ULTIMATE.start_main_p3 v_idx_711) (< v_idx_711 v_b_255_4)) (or (<= .cse7 v_idx_712) (< v_idx_712 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_712) v_v_3097_2)) (<= .cse6 c_ULTIMATE.start_main_p3) (<= .cse5 v_b_255_4) (or (< v_idx_713 .cse7) (= (select |c_#memory_int| v_idx_713) v_v_3098_2))))))) is different from false [2019-01-07 22:14:23,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:14:23,540 INFO L93 Difference]: Finished difference Result 21 states and 57 transitions. [2019-01-07 22:14:23,540 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-07 22:14:23,540 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-07 22:14:23,540 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:14:23,541 INFO L225 Difference]: With dead ends: 21 [2019-01-07 22:14:23,541 INFO L226 Difference]: Without dead ends: 20 [2019-01-07 22:14:23,541 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.6s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-07 22:14:23,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-01-07 22:14:23,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 17. [2019-01-07 22:14:23,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2019-01-07 22:14:23,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 47 transitions. [2019-01-07 22:14:23,557 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 47 transitions. Word has length 4 [2019-01-07 22:14:23,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:14:23,557 INFO L480 AbstractCegarLoop]: Abstraction has 17 states and 47 transitions. [2019-01-07 22:14:23,557 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-07 22:14:23,557 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 47 transitions. [2019-01-07 22:14:23,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-07 22:14:23,557 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:14:23,557 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-07 22:14:23,558 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:14:23,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:14:23,558 INFO L82 PathProgramCache]: Analyzing trace with hash 935566, now seen corresponding path program 1 times [2019-01-07 22:14:23,558 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:14:23,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:14:23,559 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:14:23,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:14:23,559 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:14:23,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:14:23,644 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:14:23,645 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:14:23,645 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:14:23,645 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-07 22:14:23,645 INFO L207 CegarAbsIntRunner]: [0], [12], [16], [17] [2019-01-07 22:14:23,646 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-07 22:14:23,646 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-07 22:14:28,882 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-07 22:14:28,883 INFO L272 AbstractInterpreter]: Visited 4 different actions 16 times. Merged at 2 different actions 8 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-07 22:14:28,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:14:28,883 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-07 22:14:29,132 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 57.14% of their original sizes. [2019-01-07 22:14:29,133 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-07 22:14:31,547 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_820 Int) (v_idx_823 Int) (v_idx_824 Int) (v_idx_821 Int) (v_idx_822 Int) (v_idx_825 Int) (v_idx_826 Int)) (exists ((v_v_1648_8 Int) (v_v_1649_8 Int) (v_v_1647_8 Int) (v_v_1645_7 Int) (v_v_1643_8 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_823) 0) (<= .cse0 v_idx_823) (< v_idx_823 c_ULTIMATE.start_main_p2)) (or (<= c_ULTIMATE.start_main_p3 v_idx_824) (= (select |c_#memory_int| v_idx_824) v_v_1647_8) (< v_idx_824 .cse0)) (or (<= .cse1 v_idx_825) (< v_idx_825 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_825) v_v_1648_8)) (or (<= c_ULTIMATE.start_main_p2 v_idx_822) (< v_idx_822 .cse2) (= (select |c_#memory_int| v_idx_822) v_v_1645_7)) (<= 0 (* 2 v_v_1648_8)) (or (< v_idx_821 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_821) (= (select |c_#memory_int| v_idx_821) 0)) (or (= (select |c_#memory_int| v_idx_826) v_v_1649_8) (< v_idx_826 .cse1)) (<= .cse2 c_ULTIMATE.start_main_p2) (or (<= c_ULTIMATE.start_main_p1 v_idx_820) (= (select |c_#memory_int| v_idx_820) v_v_1643_8)) (<= 0 v_v_1648_8) (<= .cse0 c_ULTIMATE.start_main_p3))))) is different from false [2019-01-07 22:14:34,162 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_830 Int) (v_idx_831 Int) (v_idx_832 Int) (v_idx_833 Int) (v_idx_827 Int) (v_idx_828 Int) (v_idx_829 Int)) (exists ((v_v_1648_8 Int) (v_v_1649_8 Int) (v_v_1647_8 Int) (v_v_1645_7 Int) (v_b_131_8 Int) (v_v_1643_8 Int) (v_b_130_8 Int)) (let ((.cse1 (+ v_b_130_8 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_833 v_b_131_8) (= (select |c_#memory_int| v_idx_833) v_v_1649_8)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_8) (or (<= .cse0 v_idx_830) (= (select |c_#memory_int| v_idx_830) 0) (< v_idx_830 c_ULTIMATE.start_main_p2)) (or (<= v_b_131_8 v_idx_832) (< v_idx_832 v_b_130_8) (= (select |c_#memory_int| v_idx_832) v_v_1648_8)) (<= 0 v_v_1648_8) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_8) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_8) (<= v_b_131_8 .cse1) (or (< v_idx_828 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_828) (= (select |c_#memory_int| v_idx_828) 0)) (<= .cse1 v_b_131_8) (<= .cse0 v_b_130_8) (<= 0 (* 2 v_v_1648_8)) (or (= (select |c_#memory_int| v_idx_831) v_v_1647_8) (< v_idx_831 .cse0) (<= v_b_130_8 v_idx_831)) (or (= (select |c_#memory_int| v_idx_827) v_v_1643_8) (<= c_ULTIMATE.start_main_p1 v_idx_827)) (<= .cse2 c_ULTIMATE.start_main_p2) (or (<= c_ULTIMATE.start_main_p2 v_idx_829) (= (select |c_#memory_int| v_idx_829) v_v_1645_7) (< v_idx_829 .cse2)))))) is different from false [2019-01-07 22:14:36,605 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_840 Int) (v_idx_834 Int) (v_idx_835 Int) (v_idx_838 Int) (v_idx_839 Int) (v_idx_836 Int) (v_idx_837 Int)) (exists ((v_v_1648_8 Int) (v_v_1649_8 Int) (v_b_127_8 Int) (v_v_1647_8 Int) (v_v_1645_7 Int) (v_b_131_8 Int) (v_v_1643_8 Int) (v_b_130_8 Int) (v_b_146_8 Int)) (let ((.cse1 (+ v_b_130_8 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_146_8 1))) (and (or (= (select |c_#memory_int| v_idx_840) v_v_1649_8) (< v_idx_840 v_b_131_8)) (or (< v_idx_839 v_b_130_8) (= (select |c_#memory_int| v_idx_839) v_v_1648_8) (<= v_b_131_8 v_idx_839)) (<= (+ v_b_146_8 3) v_b_131_8) (<= v_b_127_8 c_ULTIMATE.start_main_p2) (<= (+ v_b_146_8 2) v_b_130_8) (or (<= v_b_127_8 v_idx_835) (= (select |c_#memory_int| v_idx_835) 0) (< v_idx_835 v_b_146_8)) (or (= (select |c_#memory_int| v_idx_837) 0) (<= .cse0 v_idx_837) (< v_idx_837 c_ULTIMATE.start_main_p2)) (or (<= c_ULTIMATE.start_main_p2 v_idx_836) (< v_idx_836 v_b_127_8) (= (select |c_#memory_int| v_idx_836) v_v_1645_7)) (<= 0 v_v_1648_8) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_8) (<= v_b_131_8 .cse1) (or (<= v_b_130_8 v_idx_838) (< v_idx_838 .cse0) (= (select |c_#memory_int| v_idx_838) v_v_1647_8)) (<= .cse1 v_b_131_8) (or (= (select |c_#memory_int| v_idx_834) v_v_1643_8) (<= v_b_146_8 v_idx_834)) (<= .cse0 v_b_130_8) (<= 0 (* 2 v_v_1648_8)) (<= v_b_127_8 .cse2) (<= (+ v_b_127_8 2) v_b_131_8) (<= .cse2 v_b_127_8) (<= (+ v_b_127_8 1) v_b_130_8) (<= .cse2 c_ULTIMATE.start_main_p2))))) is different from false [2019-01-07 22:14:36,674 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-07 22:14:36,674 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-07 22:14:36,674 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-07 22:14:36,675 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [2] total 5 [2019-01-07 22:14:36,675 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:14:36,675 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-07 22:14:36,675 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-07 22:14:36,675 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-07 22:14:36,675 INFO L87 Difference]: Start difference. First operand 17 states and 47 transitions. Second operand 5 states. [2019-01-07 22:14:39,174 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_820 Int) (v_idx_823 Int) (v_idx_824 Int) (v_idx_821 Int) (v_idx_822 Int) (v_idx_825 Int) (v_idx_826 Int)) (exists ((v_v_1648_8 Int) (v_v_1649_8 Int) (v_v_1647_8 Int) (v_v_1645_7 Int) (v_v_1643_8 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_823) 0) (<= .cse0 v_idx_823) (< v_idx_823 c_ULTIMATE.start_main_p2)) (or (<= c_ULTIMATE.start_main_p3 v_idx_824) (= (select |c_#memory_int| v_idx_824) v_v_1647_8) (< v_idx_824 .cse0)) (or (<= .cse1 v_idx_825) (< v_idx_825 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_825) v_v_1648_8)) (or (<= c_ULTIMATE.start_main_p2 v_idx_822) (< v_idx_822 .cse2) (= (select |c_#memory_int| v_idx_822) v_v_1645_7)) (<= 0 (* 2 v_v_1648_8)) (or (< v_idx_821 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_821) (= (select |c_#memory_int| v_idx_821) 0)) (or (= (select |c_#memory_int| v_idx_826) v_v_1649_8) (< v_idx_826 .cse1)) (<= .cse2 c_ULTIMATE.start_main_p2) (or (<= c_ULTIMATE.start_main_p1 v_idx_820) (= (select |c_#memory_int| v_idx_820) v_v_1643_8)) (<= 0 v_v_1648_8) (<= .cse0 c_ULTIMATE.start_main_p3))))) (forall ((v_idx_840 Int) (v_idx_834 Int) (v_idx_835 Int) (v_idx_838 Int) (v_idx_839 Int) (v_idx_836 Int) (v_idx_837 Int)) (exists ((v_v_1648_8 Int) (v_v_1649_8 Int) (v_b_127_8 Int) (v_v_1647_8 Int) (v_v_1645_7 Int) (v_b_131_8 Int) (v_v_1643_8 Int) (v_b_130_8 Int) (v_b_146_8 Int)) (let ((.cse4 (+ v_b_130_8 1)) (.cse3 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ v_b_146_8 1))) (and (or (= (select |c_#memory_int| v_idx_840) v_v_1649_8) (< v_idx_840 v_b_131_8)) (or (< v_idx_839 v_b_130_8) (= (select |c_#memory_int| v_idx_839) v_v_1648_8) (<= v_b_131_8 v_idx_839)) (<= (+ v_b_146_8 3) v_b_131_8) (<= v_b_127_8 c_ULTIMATE.start_main_p2) (<= (+ v_b_146_8 2) v_b_130_8) (or (<= v_b_127_8 v_idx_835) (= (select |c_#memory_int| v_idx_835) 0) (< v_idx_835 v_b_146_8)) (or (= (select |c_#memory_int| v_idx_837) 0) (<= .cse3 v_idx_837) (< v_idx_837 c_ULTIMATE.start_main_p2)) (or (<= c_ULTIMATE.start_main_p2 v_idx_836) (< v_idx_836 v_b_127_8) (= (select |c_#memory_int| v_idx_836) v_v_1645_7)) (<= 0 v_v_1648_8) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_8) (<= v_b_131_8 .cse4) (or (<= v_b_130_8 v_idx_838) (< v_idx_838 .cse3) (= (select |c_#memory_int| v_idx_838) v_v_1647_8)) (<= .cse4 v_b_131_8) (or (= (select |c_#memory_int| v_idx_834) v_v_1643_8) (<= v_b_146_8 v_idx_834)) (<= .cse3 v_b_130_8) (<= 0 (* 2 v_v_1648_8)) (<= v_b_127_8 .cse5) (<= (+ v_b_127_8 2) v_b_131_8) (<= .cse5 v_b_127_8) (<= (+ v_b_127_8 1) v_b_130_8) (<= .cse5 c_ULTIMATE.start_main_p2))))) (forall ((v_idx_830 Int) (v_idx_831 Int) (v_idx_832 Int) (v_idx_833 Int) (v_idx_827 Int) (v_idx_828 Int) (v_idx_829 Int)) (exists ((v_v_1648_8 Int) (v_v_1649_8 Int) (v_v_1647_8 Int) (v_v_1645_7 Int) (v_b_131_8 Int) (v_v_1643_8 Int) (v_b_130_8 Int)) (let ((.cse7 (+ v_b_130_8 1)) (.cse6 (+ c_ULTIMATE.start_main_p2 1)) (.cse8 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_833 v_b_131_8) (= (select |c_#memory_int| v_idx_833) v_v_1649_8)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_8) (or (<= .cse6 v_idx_830) (= (select |c_#memory_int| v_idx_830) 0) (< v_idx_830 c_ULTIMATE.start_main_p2)) (or (<= v_b_131_8 v_idx_832) (< v_idx_832 v_b_130_8) (= (select |c_#memory_int| v_idx_832) v_v_1648_8)) (<= 0 v_v_1648_8) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_8) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_8) (<= v_b_131_8 .cse7) (or (< v_idx_828 c_ULTIMATE.start_main_p1) (<= .cse8 v_idx_828) (= (select |c_#memory_int| v_idx_828) 0)) (<= .cse7 v_b_131_8) (<= .cse6 v_b_130_8) (<= 0 (* 2 v_v_1648_8)) (or (= (select |c_#memory_int| v_idx_831) v_v_1647_8) (< v_idx_831 .cse6) (<= v_b_130_8 v_idx_831)) (or (= (select |c_#memory_int| v_idx_827) v_v_1643_8) (<= c_ULTIMATE.start_main_p1 v_idx_827)) (<= .cse8 c_ULTIMATE.start_main_p2) (or (<= c_ULTIMATE.start_main_p2 v_idx_829) (= (select |c_#memory_int| v_idx_829) v_v_1645_7) (< v_idx_829 .cse8))))))) is different from false [2019-01-07 22:15:09,450 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_840 Int) (v_idx_834 Int) (v_idx_835 Int) (v_idx_838 Int) (v_idx_839 Int) (v_idx_836 Int) (v_idx_837 Int)) (exists ((v_v_1648_8 Int) (v_v_1649_8 Int) (v_b_127_8 Int) (v_v_1647_8 Int) (v_v_1645_7 Int) (v_b_131_8 Int) (v_v_1643_8 Int) (v_b_130_8 Int) (v_b_146_8 Int)) (let ((.cse1 (+ v_b_130_8 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_146_8 1))) (and (or (= (select |c_#memory_int| v_idx_840) v_v_1649_8) (< v_idx_840 v_b_131_8)) (or (< v_idx_839 v_b_130_8) (= (select |c_#memory_int| v_idx_839) v_v_1648_8) (<= v_b_131_8 v_idx_839)) (<= (+ v_b_146_8 3) v_b_131_8) (<= v_b_127_8 c_ULTIMATE.start_main_p2) (<= (+ v_b_146_8 2) v_b_130_8) (or (<= v_b_127_8 v_idx_835) (= (select |c_#memory_int| v_idx_835) 0) (< v_idx_835 v_b_146_8)) (or (= (select |c_#memory_int| v_idx_837) 0) (<= .cse0 v_idx_837) (< v_idx_837 c_ULTIMATE.start_main_p2)) (or (<= c_ULTIMATE.start_main_p2 v_idx_836) (< v_idx_836 v_b_127_8) (= (select |c_#memory_int| v_idx_836) v_v_1645_7)) (<= 0 v_v_1648_8) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_8) (<= v_b_131_8 .cse1) (or (<= v_b_130_8 v_idx_838) (< v_idx_838 .cse0) (= (select |c_#memory_int| v_idx_838) v_v_1647_8)) (<= .cse1 v_b_131_8) (or (= (select |c_#memory_int| v_idx_834) v_v_1643_8) (<= v_b_146_8 v_idx_834)) (<= .cse0 v_b_130_8) (<= 0 (* 2 v_v_1648_8)) (<= v_b_127_8 .cse2) (<= (+ v_b_127_8 2) v_b_131_8) (<= .cse2 v_b_127_8) (<= (+ v_b_127_8 1) v_b_130_8) (<= .cse2 c_ULTIMATE.start_main_p2))))) (forall ((v_idx_830 Int) (v_idx_831 Int) (v_idx_832 Int) (v_idx_833 Int) (v_idx_827 Int) (v_idx_828 Int) (v_idx_829 Int)) (exists ((v_v_1648_8 Int) (v_v_1649_8 Int) (v_v_1647_8 Int) (v_v_1645_7 Int) (v_b_131_8 Int) (v_v_1643_8 Int) (v_b_130_8 Int)) (let ((.cse4 (+ v_b_130_8 1)) (.cse3 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_833 v_b_131_8) (= (select |c_#memory_int| v_idx_833) v_v_1649_8)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_8) (or (<= .cse3 v_idx_830) (= (select |c_#memory_int| v_idx_830) 0) (< v_idx_830 c_ULTIMATE.start_main_p2)) (or (<= v_b_131_8 v_idx_832) (< v_idx_832 v_b_130_8) (= (select |c_#memory_int| v_idx_832) v_v_1648_8)) (<= 0 v_v_1648_8) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_8) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_8) (<= v_b_131_8 .cse4) (or (< v_idx_828 c_ULTIMATE.start_main_p1) (<= .cse5 v_idx_828) (= (select |c_#memory_int| v_idx_828) 0)) (<= .cse4 v_b_131_8) (<= .cse3 v_b_130_8) (<= 0 (* 2 v_v_1648_8)) (or (= (select |c_#memory_int| v_idx_831) v_v_1647_8) (< v_idx_831 .cse3) (<= v_b_130_8 v_idx_831)) (or (= (select |c_#memory_int| v_idx_827) v_v_1643_8) (<= c_ULTIMATE.start_main_p1 v_idx_827)) (<= .cse5 c_ULTIMATE.start_main_p2) (or (<= c_ULTIMATE.start_main_p2 v_idx_829) (= (select |c_#memory_int| v_idx_829) v_v_1645_7) (< v_idx_829 .cse5))))))) is different from false [2019-01-07 22:15:13,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:15:13,754 INFO L93 Difference]: Finished difference Result 20 states and 53 transitions. [2019-01-07 22:15:13,754 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-07 22:15:13,754 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-07 22:15:13,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:15:13,754 INFO L225 Difference]: With dead ends: 20 [2019-01-07 22:15:13,754 INFO L226 Difference]: Without dead ends: 19 [2019-01-07 22:15:13,755 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.4s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-07 22:15:13,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2019-01-07 22:15:13,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 18. [2019-01-07 22:15:13,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2019-01-07 22:15:13,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 51 transitions. [2019-01-07 22:15:13,776 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 51 transitions. Word has length 4 [2019-01-07 22:15:13,776 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:15:13,776 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 51 transitions. [2019-01-07 22:15:13,776 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-07 22:15:13,776 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 51 transitions. [2019-01-07 22:15:13,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-07 22:15:13,777 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:15:13,777 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-07 22:15:13,777 INFO L423 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:15:13,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:15:13,777 INFO L82 PathProgramCache]: Analyzing trace with hash 935378, now seen corresponding path program 2 times [2019-01-07 22:15:13,777 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:15:13,778 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:15:13,778 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:15:13,778 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:15:13,779 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:15:13,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:15:13,924 WARN L181 SmtUtils]: Spent 102.00 ms on a formula simplification. DAG size of input: 30 DAG size of output: 17 [2019-01-07 22:15:13,953 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:15:13,954 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:15:13,954 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:15:13,954 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-07 22:15:13,954 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-07 22:15:13,954 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:15:13,954 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-07 22:15:13,962 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-07 22:15:13,962 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-07 22:15:13,967 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-07 22:15:13,967 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-07 22:15:13,968 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-07 22:15:13,970 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-07 22:15:13,972 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:15:13,973 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-07 22:15:13,976 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:15:13,978 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:15:13,979 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-07 22:15:13,980 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-07 22:15:13,999 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-07 22:15:14,009 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-07 22:15:14,025 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-07 22:15:14,025 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:19, output treesize:22 [2019-01-07 22:15:14,046 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:15:14,047 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:15:14,048 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:15:14,049 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:15:14,050 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-07 22:15:14,050 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-07 22:15:14,079 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-07 22:15:14,079 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-07 22:15:14,102 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:15:14,103 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:15:14,104 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:15:14,111 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:15:14,111 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:15:14,112 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:15:14,113 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 48 [2019-01-07 22:15:14,114 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-07 22:15:14,159 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-07 22:15:14,160 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-07 22:15:14,175 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:15:14,175 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-07 22:15:14,205 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:15:14,224 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-07 22:15:14,224 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 9 [2019-01-07 22:15:14,224 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-07 22:15:14,224 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-01-07 22:15:14,225 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-01-07 22:15:14,225 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=66, Unknown=0, NotChecked=0, Total=110 [2019-01-07 22:15:14,225 INFO L87 Difference]: Start difference. First operand 18 states and 51 transitions. Second operand 8 states. [2019-01-07 22:15:14,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:15:14,526 INFO L93 Difference]: Finished difference Result 37 states and 88 transitions. [2019-01-07 22:15:14,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-07 22:15:14,527 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 4 [2019-01-07 22:15:14,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:15:14,528 INFO L225 Difference]: With dead ends: 37 [2019-01-07 22:15:14,528 INFO L226 Difference]: Without dead ends: 36 [2019-01-07 22:15:14,528 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=62, Invalid=94, Unknown=0, NotChecked=0, Total=156 [2019-01-07 22:15:14,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-01-07 22:15:14,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 20. [2019-01-07 22:15:14,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-01-07 22:15:14,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 59 transitions. [2019-01-07 22:15:14,553 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 59 transitions. Word has length 4 [2019-01-07 22:15:14,553 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:15:14,553 INFO L480 AbstractCegarLoop]: Abstraction has 20 states and 59 transitions. [2019-01-07 22:15:14,553 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-01-07 22:15:14,553 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 59 transitions. [2019-01-07 22:15:14,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-07 22:15:14,554 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:15:14,554 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-07 22:15:14,554 INFO L423 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:15:14,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:15:14,554 INFO L82 PathProgramCache]: Analyzing trace with hash 28823850, now seen corresponding path program 1 times [2019-01-07 22:15:14,554 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:15:14,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:15:14,555 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-07 22:15:14,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:15:14,555 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:15:14,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:15:14,633 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:15:14,634 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:15:14,634 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:15:14,634 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-07 22:15:14,634 INFO L207 CegarAbsIntRunner]: [0], [6], [16], [18], [19] [2019-01-07 22:15:14,636 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-07 22:15:14,636 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-07 22:15:21,267 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-07 22:15:21,267 INFO L272 AbstractInterpreter]: Visited 5 different actions 21 times. Merged at 3 different actions 12 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-07 22:15:21,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:15:21,268 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-07 22:15:21,632 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 53.57% of their original sizes. [2019-01-07 22:15:21,632 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-07 22:15:23,982 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_973 Int) (v_idx_974 Int) (v_idx_977 Int) (v_idx_978 Int) (v_idx_975 Int) (v_idx_976 Int) (v_idx_979 Int)) (exists ((v_v_1751_7 Int) (v_v_1753_7 Int) (v_v_1747_9 Int) (v_v_1749_9 Int) (v_v_1748_9 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 v_v_1748_9) (or (<= .cse0 v_idx_974) (= (select |c_#memory_int| v_idx_974) v_v_1748_9) (< v_idx_974 c_ULTIMATE.start_main_p1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_973) (= (select |c_#memory_int| v_idx_973) v_v_1747_9)) (or (= (select |c_#memory_int| v_idx_977) v_v_1751_7) (<= c_ULTIMATE.start_main_p3 v_idx_977) (< v_idx_977 .cse1)) (or (< v_idx_976 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_976) (= (select |c_#memory_int| v_idx_976) 0)) (or (= (select |c_#memory_int| v_idx_979) v_v_1753_7) (< v_idx_979 .cse2)) (<= 0 (* 2 v_v_1748_9)) (<= .cse0 c_ULTIMATE.start_main_p2) (or (= 0 (select |c_#memory_int| v_idx_978)) (<= .cse2 v_idx_978) (< v_idx_978 c_ULTIMATE.start_main_p3)) (or (< v_idx_975 .cse0) (= (select |c_#memory_int| v_idx_975) v_v_1749_9) (<= c_ULTIMATE.start_main_p2 v_idx_975)) (<= .cse1 c_ULTIMATE.start_main_p3))))) is different from false [2019-01-07 22:15:26,518 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_984 Int) (v_idx_985 Int) (v_idx_982 Int) (v_idx_983 Int) (v_idx_986 Int) (v_idx_980 Int) (v_idx_981 Int)) (exists ((v_v_1751_7 Int) (v_v_1753_7 Int) (v_v_1747_9 Int) (v_v_1749_9 Int) (v_v_1748_9 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_984) v_v_1751_7) (<= c_ULTIMATE.start_main_p3 v_idx_984) (< v_idx_984 .cse0)) (<= 0 v_v_1748_9) (or (= (select |c_#memory_int| v_idx_982) v_v_1749_9) (< v_idx_982 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_982)) (or (< v_idx_986 .cse2) (= (select |c_#memory_int| v_idx_986) v_v_1753_7)) (or (= (select |c_#memory_int| v_idx_983) 0) (< v_idx_983 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_983)) (or (<= .cse1 v_idx_981) (< v_idx_981 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_981) v_v_1748_9)) (or (= (select |c_#memory_int| v_idx_980) v_v_1747_9) (<= c_ULTIMATE.start_main_p1 v_idx_980)) (<= 0 (* 2 v_v_1748_9)) (<= .cse1 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_985) 0) (<= .cse2 v_idx_985) (< v_idx_985 c_ULTIMATE.start_main_p3)) (<= .cse0 c_ULTIMATE.start_main_p3))))) is different from false [2019-01-07 22:15:29,142 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_993 Int) (v_idx_988 Int) (v_idx_989 Int) (v_idx_987 Int) (v_idx_991 Int) (v_idx_992 Int) (v_idx_990 Int)) (exists ((v_b_148_9 Int) (v_v_1751_7 Int) (v_v_1753_7 Int) (v_v_1747_9 Int) (v_v_2231_6 Int) (v_v_1749_9 Int) (v_b_133_9 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_148_9 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ v_b_133_9 1) c_ULTIMATE.start_main_p3) (or (< v_idx_991 .cse0) (= (select |c_#memory_int| v_idx_991) v_v_1751_7) (<= c_ULTIMATE.start_main_p3 v_idx_991)) (<= 0 v_v_2231_6) (<= v_b_133_9 .cse1) (or (= (select |c_#memory_int| v_idx_990) 0) (<= .cse0 v_idx_990) (< v_idx_990 c_ULTIMATE.start_main_p2)) (<= 0 (* 2 v_v_2231_6)) (<= .cse0 c_ULTIMATE.start_main_p3) (<= .cse1 c_ULTIMATE.start_main_p2) (<= v_b_133_9 c_ULTIMATE.start_main_p2) (<= .cse1 v_b_133_9) (or (<= v_b_133_9 v_idx_988) (= (select |c_#memory_int| v_idx_988) v_v_2231_6) (< v_idx_988 v_b_148_9)) (<= (+ v_b_148_9 2) c_ULTIMATE.start_main_p3) (or (<= .cse2 v_idx_992) (= (select |c_#memory_int| v_idx_992) 0) (< v_idx_992 c_ULTIMATE.start_main_p3)) (or (= (select |c_#memory_int| v_idx_993) v_v_1753_7) (< v_idx_993 .cse2)) (or (= (select |c_#memory_int| v_idx_987) v_v_1747_9) (<= v_b_148_9 v_idx_987)) (or (= (select |c_#memory_int| v_idx_989) v_v_1749_9) (< v_idx_989 v_b_133_9) (<= c_ULTIMATE.start_main_p2 v_idx_989)))))) is different from false [2019-01-07 22:15:31,479 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_995 Int) (v_idx_996 Int) (v_idx_994 Int) (v_idx_999 Int) (v_idx_1000 Int) (v_idx_997 Int) (v_idx_998 Int)) (exists ((v_b_148_9 Int) (v_b_160_9 Int) (v_v_1751_7 Int) (v_v_1753_7 Int) (v_v_1747_9 Int) (v_b_135_9 Int) (v_v_2231_6 Int) (v_v_1749_9 Int) (v_b_133_9 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ v_b_133_9 1)) (.cse4 (+ v_b_148_9 1)) (.cse2 (+ v_b_148_9 2)) (.cse1 (+ v_b_160_9 1))) (and (<= .cse0 c_ULTIMATE.start_main_p3) (<= .cse1 c_ULTIMATE.start_main_p3) (<= v_b_133_9 v_b_160_9) (<= v_b_135_9 c_ULTIMATE.start_main_p3) (<= .cse2 v_b_135_9) (or (= 0 (select |c_#memory_int| v_idx_999)) (<= .cse3 v_idx_999) (< v_idx_999 c_ULTIMATE.start_main_p3)) (or (< v_idx_1000 .cse3) (= (select |c_#memory_int| v_idx_1000) v_v_1753_7)) (<= 0 v_v_2231_6) (or (<= v_b_160_9 v_idx_996) (= (select |c_#memory_int| v_idx_996) v_v_1749_9) (< v_idx_996 v_b_133_9)) (<= v_b_135_9 .cse1) (<= v_b_133_9 .cse4) (<= 0 (* 2 v_v_2231_6)) (or (<= c_ULTIMATE.start_main_p3 v_idx_998) (= (select |c_#memory_int| v_idx_998) v_v_1751_7) (< v_idx_998 v_b_135_9)) (<= .cse4 v_b_160_9) (<= .cse0 v_b_135_9) (or (= (select |c_#memory_int| v_idx_995) v_v_2231_6) (< v_idx_995 v_b_148_9) (<= v_b_133_9 v_idx_995)) (or (<= v_b_148_9 v_idx_994) (= (select |c_#memory_int| v_idx_994) v_v_1747_9)) (or (= (select |c_#memory_int| v_idx_997) 0) (<= v_b_135_9 v_idx_997) (< v_idx_997 v_b_160_9)) (<= .cse4 v_b_133_9) (<= .cse2 c_ULTIMATE.start_main_p3) (<= .cse1 v_b_135_9))))) is different from false [2019-01-07 22:15:31,543 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-07 22:15:31,543 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-07 22:15:31,544 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-07 22:15:31,544 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [2] total 6 [2019-01-07 22:15:31,544 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:15:31,544 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-07 22:15:31,544 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-07 22:15:31,544 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-07 22:15:31,544 INFO L87 Difference]: Start difference. First operand 20 states and 59 transitions. Second operand 6 states. [2019-01-07 22:15:34,113 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_984 Int) (v_idx_985 Int) (v_idx_982 Int) (v_idx_983 Int) (v_idx_986 Int) (v_idx_980 Int) (v_idx_981 Int)) (exists ((v_v_1751_7 Int) (v_v_1753_7 Int) (v_v_1747_9 Int) (v_v_1749_9 Int) (v_v_1748_9 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_984) v_v_1751_7) (<= c_ULTIMATE.start_main_p3 v_idx_984) (< v_idx_984 .cse0)) (<= 0 v_v_1748_9) (or (= (select |c_#memory_int| v_idx_982) v_v_1749_9) (< v_idx_982 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_982)) (or (< v_idx_986 .cse2) (= (select |c_#memory_int| v_idx_986) v_v_1753_7)) (or (= (select |c_#memory_int| v_idx_983) 0) (< v_idx_983 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_983)) (or (<= .cse1 v_idx_981) (< v_idx_981 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_981) v_v_1748_9)) (or (= (select |c_#memory_int| v_idx_980) v_v_1747_9) (<= c_ULTIMATE.start_main_p1 v_idx_980)) (<= 0 (* 2 v_v_1748_9)) (<= .cse1 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_985) 0) (<= .cse2 v_idx_985) (< v_idx_985 c_ULTIMATE.start_main_p3)) (<= .cse0 c_ULTIMATE.start_main_p3))))) (forall ((v_idx_993 Int) (v_idx_988 Int) (v_idx_989 Int) (v_idx_987 Int) (v_idx_991 Int) (v_idx_992 Int) (v_idx_990 Int)) (exists ((v_b_148_9 Int) (v_v_1751_7 Int) (v_v_1753_7 Int) (v_v_1747_9 Int) (v_v_2231_6 Int) (v_v_1749_9 Int) (v_b_133_9 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p2 1)) (.cse4 (+ v_b_148_9 1)) (.cse5 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ v_b_133_9 1) c_ULTIMATE.start_main_p3) (or (< v_idx_991 .cse3) (= (select |c_#memory_int| v_idx_991) v_v_1751_7) (<= c_ULTIMATE.start_main_p3 v_idx_991)) (<= 0 v_v_2231_6) (<= v_b_133_9 .cse4) (or (= (select |c_#memory_int| v_idx_990) 0) (<= .cse3 v_idx_990) (< v_idx_990 c_ULTIMATE.start_main_p2)) (<= 0 (* 2 v_v_2231_6)) (<= .cse3 c_ULTIMATE.start_main_p3) (<= .cse4 c_ULTIMATE.start_main_p2) (<= v_b_133_9 c_ULTIMATE.start_main_p2) (<= .cse4 v_b_133_9) (or (<= v_b_133_9 v_idx_988) (= (select |c_#memory_int| v_idx_988) v_v_2231_6) (< v_idx_988 v_b_148_9)) (<= (+ v_b_148_9 2) c_ULTIMATE.start_main_p3) (or (<= .cse5 v_idx_992) (= (select |c_#memory_int| v_idx_992) 0) (< v_idx_992 c_ULTIMATE.start_main_p3)) (or (= (select |c_#memory_int| v_idx_993) v_v_1753_7) (< v_idx_993 .cse5)) (or (= (select |c_#memory_int| v_idx_987) v_v_1747_9) (<= v_b_148_9 v_idx_987)) (or (= (select |c_#memory_int| v_idx_989) v_v_1749_9) (< v_idx_989 v_b_133_9) (<= c_ULTIMATE.start_main_p2 v_idx_989)))))) (forall ((v_idx_973 Int) (v_idx_974 Int) (v_idx_977 Int) (v_idx_978 Int) (v_idx_975 Int) (v_idx_976 Int) (v_idx_979 Int)) (exists ((v_v_1751_7 Int) (v_v_1753_7 Int) (v_v_1747_9 Int) (v_v_1749_9 Int) (v_v_1748_9 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p3 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 v_v_1748_9) (or (<= .cse6 v_idx_974) (= (select |c_#memory_int| v_idx_974) v_v_1748_9) (< v_idx_974 c_ULTIMATE.start_main_p1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_973) (= (select |c_#memory_int| v_idx_973) v_v_1747_9)) (or (= (select |c_#memory_int| v_idx_977) v_v_1751_7) (<= c_ULTIMATE.start_main_p3 v_idx_977) (< v_idx_977 .cse7)) (or (< v_idx_976 c_ULTIMATE.start_main_p2) (<= .cse7 v_idx_976) (= (select |c_#memory_int| v_idx_976) 0)) (or (= (select |c_#memory_int| v_idx_979) v_v_1753_7) (< v_idx_979 .cse8)) (<= 0 (* 2 v_v_1748_9)) (<= .cse6 c_ULTIMATE.start_main_p2) (or (= 0 (select |c_#memory_int| v_idx_978)) (<= .cse8 v_idx_978) (< v_idx_978 c_ULTIMATE.start_main_p3)) (or (< v_idx_975 .cse6) (= (select |c_#memory_int| v_idx_975) v_v_1749_9) (<= c_ULTIMATE.start_main_p2 v_idx_975)) (<= .cse7 c_ULTIMATE.start_main_p3))))) (forall ((v_idx_995 Int) (v_idx_996 Int) (v_idx_994 Int) (v_idx_999 Int) (v_idx_1000 Int) (v_idx_997 Int) (v_idx_998 Int)) (exists ((v_b_148_9 Int) (v_b_160_9 Int) (v_v_1751_7 Int) (v_v_1753_7 Int) (v_v_1747_9 Int) (v_b_135_9 Int) (v_v_2231_6 Int) (v_v_1749_9 Int) (v_b_133_9 Int)) (let ((.cse12 (+ c_ULTIMATE.start_main_p3 1)) (.cse9 (+ v_b_133_9 1)) (.cse13 (+ v_b_148_9 1)) (.cse11 (+ v_b_148_9 2)) (.cse10 (+ v_b_160_9 1))) (and (<= .cse9 c_ULTIMATE.start_main_p3) (<= .cse10 c_ULTIMATE.start_main_p3) (<= v_b_133_9 v_b_160_9) (<= v_b_135_9 c_ULTIMATE.start_main_p3) (<= .cse11 v_b_135_9) (or (= 0 (select |c_#memory_int| v_idx_999)) (<= .cse12 v_idx_999) (< v_idx_999 c_ULTIMATE.start_main_p3)) (or (< v_idx_1000 .cse12) (= (select |c_#memory_int| v_idx_1000) v_v_1753_7)) (<= 0 v_v_2231_6) (or (<= v_b_160_9 v_idx_996) (= (select |c_#memory_int| v_idx_996) v_v_1749_9) (< v_idx_996 v_b_133_9)) (<= v_b_135_9 .cse10) (<= v_b_133_9 .cse13) (<= 0 (* 2 v_v_2231_6)) (or (<= c_ULTIMATE.start_main_p3 v_idx_998) (= (select |c_#memory_int| v_idx_998) v_v_1751_7) (< v_idx_998 v_b_135_9)) (<= .cse13 v_b_160_9) (<= .cse9 v_b_135_9) (or (= (select |c_#memory_int| v_idx_995) v_v_2231_6) (< v_idx_995 v_b_148_9) (<= v_b_133_9 v_idx_995)) (or (<= v_b_148_9 v_idx_994) (= (select |c_#memory_int| v_idx_994) v_v_1747_9)) (or (= (select |c_#memory_int| v_idx_997) 0) (<= v_b_135_9 v_idx_997) (< v_idx_997 v_b_160_9)) (<= .cse13 v_b_133_9) (<= .cse11 c_ULTIMATE.start_main_p3) (<= .cse10 v_b_135_9)))))) is different from false [2019-01-07 22:16:00,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:16:00,417 INFO L93 Difference]: Finished difference Result 23 states and 61 transitions. [2019-01-07 22:16:00,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-07 22:16:00,418 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2019-01-07 22:16:00,418 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:16:00,418 INFO L225 Difference]: With dead ends: 23 [2019-01-07 22:16:00,418 INFO L226 Difference]: Without dead ends: 20 [2019-01-07 22:16:00,419 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.4s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-07 22:16:00,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-01-07 22:16:00,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-01-07 22:16:00,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-01-07 22:16:00,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 58 transitions. [2019-01-07 22:16:00,439 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 58 transitions. Word has length 5 [2019-01-07 22:16:00,439 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:16:00,439 INFO L480 AbstractCegarLoop]: Abstraction has 20 states and 58 transitions. [2019-01-07 22:16:00,439 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-01-07 22:16:00,439 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 58 transitions. [2019-01-07 22:16:00,440 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-07 22:16:00,440 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:16:00,440 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1] [2019-01-07 22:16:00,440 INFO L423 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:16:00,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:16:00,441 INFO L82 PathProgramCache]: Analyzing trace with hash 28814176, now seen corresponding path program 2 times [2019-01-07 22:16:00,441 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:16:00,441 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:16:00,441 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:16:00,442 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:16:00,442 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:16:00,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:16:00,506 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2019-01-07 22:16:00,506 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-07 22:16:00,507 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-01-07 22:16:00,507 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:16:00,507 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-07 22:16:00,507 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-07 22:16:00,507 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-01-07 22:16:00,507 INFO L87 Difference]: Start difference. First operand 20 states and 58 transitions. Second operand 4 states. [2019-01-07 22:16:00,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:16:00,577 INFO L93 Difference]: Finished difference Result 25 states and 65 transitions. [2019-01-07 22:16:00,577 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-07 22:16:00,577 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 5 [2019-01-07 22:16:00,577 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:16:00,578 INFO L225 Difference]: With dead ends: 25 [2019-01-07 22:16:00,578 INFO L226 Difference]: Without dead ends: 24 [2019-01-07 22:16:00,579 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-01-07 22:16:00,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2019-01-07 22:16:00,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 21. [2019-01-07 22:16:00,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-01-07 22:16:00,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 62 transitions. [2019-01-07 22:16:00,602 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 62 transitions. Word has length 5 [2019-01-07 22:16:00,602 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:16:00,602 INFO L480 AbstractCegarLoop]: Abstraction has 21 states and 62 transitions. [2019-01-07 22:16:00,602 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-07 22:16:00,602 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 62 transitions. [2019-01-07 22:16:00,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-07 22:16:00,603 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:16:00,603 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1] [2019-01-07 22:16:00,603 INFO L423 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:16:00,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:16:00,603 INFO L82 PathProgramCache]: Analyzing trace with hash 28813988, now seen corresponding path program 2 times [2019-01-07 22:16:00,603 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:16:00,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:16:00,604 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-07 22:16:00,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:16:00,604 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:16:00,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:16:00,711 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:16:00,711 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:16:00,712 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:16:00,712 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-07 22:16:00,712 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-07 22:16:00,712 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:16:00,712 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-07 22:16:00,720 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-07 22:16:00,721 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-07 22:16:00,726 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-01-07 22:16:00,727 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-07 22:16:00,727 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-07 22:16:00,734 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-07 22:16:00,737 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:00,738 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-07 22:16:00,742 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:00,745 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:00,745 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-07 22:16:00,746 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-07 22:16:00,870 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-07 22:16:00,876 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-07 22:16:00,888 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-07 22:16:00,888 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:19, output treesize:22 [2019-01-07 22:16:00,911 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:00,912 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:00,913 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:00,914 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:00,915 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 28 [2019-01-07 22:16:00,916 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-07 22:16:00,933 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-07 22:16:00,934 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-07 22:16:00,994 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:01,015 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:01,024 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:01,025 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:01,026 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:01,026 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:01,027 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 40 [2019-01-07 22:16:01,028 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-07 22:16:01,045 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-07 22:16:01,045 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-07 22:16:01,069 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:01,070 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:01,071 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:01,072 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:01,072 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:01,074 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:16:01,075 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 40 [2019-01-07 22:16:01,076 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-07 22:16:01,160 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-07 22:16:01,161 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-07 22:16:01,175 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:16:01,175 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-07 22:16:01,211 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 5 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:16:01,231 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-07 22:16:01,231 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 12 [2019-01-07 22:16:01,231 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-07 22:16:01,232 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-01-07 22:16:01,232 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-01-07 22:16:01,232 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=111, Unknown=0, NotChecked=0, Total=182 [2019-01-07 22:16:01,232 INFO L87 Difference]: Start difference. First operand 21 states and 62 transitions. Second operand 10 states. [2019-01-07 22:16:01,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:16:01,739 INFO L93 Difference]: Finished difference Result 55 states and 133 transitions. [2019-01-07 22:16:01,746 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-01-07 22:16:01,746 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 5 [2019-01-07 22:16:01,746 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:16:01,747 INFO L225 Difference]: With dead ends: 55 [2019-01-07 22:16:01,747 INFO L226 Difference]: Without dead ends: 54 [2019-01-07 22:16:01,748 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 58 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=81, Invalid=129, Unknown=0, NotChecked=0, Total=210 [2019-01-07 22:16:01,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-01-07 22:16:01,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 23. [2019-01-07 22:16:01,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23 states. [2019-01-07 22:16:01,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 70 transitions. [2019-01-07 22:16:01,772 INFO L78 Accepts]: Start accepts. Automaton has 23 states and 70 transitions. Word has length 5 [2019-01-07 22:16:01,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:16:01,773 INFO L480 AbstractCegarLoop]: Abstraction has 23 states and 70 transitions. [2019-01-07 22:16:01,773 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-01-07 22:16:01,773 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 70 transitions. [2019-01-07 22:16:01,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-07 22:16:01,773 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:16:01,774 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-07 22:16:01,774 INFO L423 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:16:01,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:16:01,774 INFO L82 PathProgramCache]: Analyzing trace with hash 28818020, now seen corresponding path program 1 times [2019-01-07 22:16:01,774 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:16:01,775 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:16:01,775 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-07 22:16:01,775 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:16:01,775 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:16:01,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:16:01,868 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:16:01,868 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:16:01,868 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:16:01,869 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-07 22:16:01,869 INFO L207 CegarAbsIntRunner]: [0], [6], [10], [16], [17] [2019-01-07 22:16:01,870 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-07 22:16:01,870 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-07 22:16:16,677 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-07 22:16:16,678 INFO L272 AbstractInterpreter]: Visited 5 different actions 37 times. Merged at 3 different actions 16 times. Widened at 2 different actions 6 times. Found 10 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-07 22:16:16,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:16:16,678 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-07 22:16:17,168 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 60.71% of their original sizes. [2019-01-07 22:16:17,169 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-07 22:16:19,608 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1137 Int) (v_idx_1136 Int) (v_idx_1135 Int) (v_idx_1134 Int) (v_idx_1133 Int) (v_idx_1139 Int) (v_idx_1138 Int)) (exists ((v_v_4531_2 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_v_4525_1 Int) (v_v_4526_1 Int)) (let ((.cse2 (+ v_b_338_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_1139 v_b_339_3) (= (select |c_#memory_int| v_idx_1139) v_v_4531_2)) (or (<= c_ULTIMATE.start_main_p2 v_idx_1135) (= (select |c_#memory_int| v_idx_1135) v_v_4527_1) (< v_idx_1135 .cse0)) (<= .cse1 v_b_338_3) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_338_3) (<= .cse2 v_b_339_3) (or (< v_idx_1138 v_b_338_3) (<= v_b_339_3 v_idx_1138) (= 0 (select |c_#memory_int| v_idx_1138))) (<= v_v_4528_2 0) (<= (* 2 v_v_4528_2) 0) (or (= (select |c_#memory_int| v_idx_1133) v_v_4525_1) (<= c_ULTIMATE.start_main_p1 v_idx_1133)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= v_b_339_3 .cse2) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_339_3) (or (= (select |c_#memory_int| v_idx_1137) v_v_4529_2) (< v_idx_1137 .cse1) (<= v_b_338_3 v_idx_1137)) (or (<= .cse0 v_idx_1134) (< v_idx_1134 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1134) v_v_4526_1)) (or (= (select |c_#memory_int| v_idx_1136) v_v_4528_2) (< v_idx_1136 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_1136)) (<= 0 v_v_4526_1) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_v_4528_2 v_v_4526_1) (<= 0 (* 2 v_v_4526_1)))))) is different from false [2019-01-07 22:16:26,494 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1146 Int) (v_idx_1145 Int) (v_idx_1144 Int) (v_idx_1143 Int) (v_idx_1142 Int) (v_idx_1141 Int) (v_idx_1140 Int)) (exists ((v_v_4531_2 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_v_4525_1 Int) (v_v_4526_1 Int)) (let ((.cse2 (+ v_b_338_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_1141 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1141) v_v_4526_1) (<= .cse0 v_idx_1141)) (<= .cse1 v_b_338_3) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_338_3) (<= .cse2 v_b_339_3) (<= v_v_4528_2 0) (<= (* 2 v_v_4528_2) 0) (or (< v_idx_1145 v_b_338_3) (= 0 (select |c_#memory_int| v_idx_1145)) (<= v_b_339_3 v_idx_1145)) (or (<= c_ULTIMATE.start_main_p1 v_idx_1140) (= (select |c_#memory_int| v_idx_1140) v_v_4525_1)) (or (< v_idx_1143 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_1143) (= (select |c_#memory_int| v_idx_1143) v_v_4528_2)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= v_b_339_3 .cse2) (or (<= c_ULTIMATE.start_main_p2 v_idx_1142) (= (select |c_#memory_int| v_idx_1142) v_v_4527_1) (< v_idx_1142 .cse0)) (or (= (select |c_#memory_int| v_idx_1146) v_v_4531_2) (< v_idx_1146 v_b_339_3)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_339_3) (or (<= v_b_338_3 v_idx_1144) (< v_idx_1144 .cse1) (= (select |c_#memory_int| v_idx_1144) v_v_4529_2)) (<= 0 v_v_4526_1) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_v_4528_2 v_v_4526_1) (<= 0 (* 2 v_v_4526_1)))))) is different from false [2019-01-07 22:16:29,000 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1148 Int) (v_idx_1147 Int) (v_idx_1153 Int) (v_idx_1152 Int) (v_idx_1151 Int) (v_idx_1150 Int) (v_idx_1149 Int)) (exists ((v_v_4531_2 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_v_4525_1 Int) (v_v_4526_1 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_338_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= (select |c_#memory_int| v_idx_1150) v_v_4528_2) (<= .cse0 v_idx_1150) (< v_idx_1150 c_ULTIMATE.start_main_p2)) (<= .cse0 v_b_338_3) (or (< v_idx_1149 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_1149) (= (select |c_#memory_int| v_idx_1149) v_v_4527_1)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_338_3) (<= .cse2 v_b_339_3) (<= v_v_4528_2 0) (or (<= v_b_338_3 v_idx_1151) (= (select |c_#memory_int| v_idx_1151) v_v_4529_2) (< v_idx_1151 .cse0)) (<= (* 2 v_v_4528_2) 0) (or (<= .cse1 v_idx_1148) (= (select |c_#memory_int| v_idx_1148) v_v_4526_1) (< v_idx_1148 c_ULTIMATE.start_main_p1)) (or (< v_idx_1153 v_b_339_3) (= (select |c_#memory_int| v_idx_1153) v_v_4531_2)) (or (<= v_b_339_3 v_idx_1152) (< v_idx_1152 v_b_338_3) (= (select |c_#memory_int| v_idx_1152) 0)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= v_b_339_3 .cse2) (or (= (select |c_#memory_int| v_idx_1147) v_v_4525_1) (<= c_ULTIMATE.start_main_p1 v_idx_1147)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_339_3) (<= 0 v_v_4526_1) (<= .cse1 c_ULTIMATE.start_main_p2) (<= v_v_4528_2 v_v_4526_1) (<= 0 (* 2 v_v_4526_1)))))) is different from false [2019-01-07 22:16:31,682 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1159 Int) (v_idx_1158 Int) (v_idx_1157 Int) (v_idx_1156 Int) (v_idx_1155 Int) (v_idx_1154 Int) (v_idx_1160 Int)) (exists ((v_v_4531_2 Int) (v_b_362_3 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_v_4887_1 Int) (v_b_335_3 Int) (v_v_4525_1 Int)) (let ((.cse1 (+ v_b_338_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_362_3 1))) (and (or (< v_idx_1156 v_b_335_3) (<= c_ULTIMATE.start_main_p2 v_idx_1156) (= (select |c_#memory_int| v_idx_1156) v_v_4527_1)) (or (= (select |c_#memory_int| v_idx_1160) v_v_4531_2) (< v_idx_1160 v_b_339_3)) (<= .cse0 v_b_338_3) (<= (+ v_b_335_3 2) v_b_339_3) (<= .cse1 v_b_339_3) (<= v_v_4528_2 0) (<= (* 2 v_v_4528_2) 0) (<= 0 (* 2 v_v_4887_1)) (or (<= v_b_335_3 v_idx_1155) (< v_idx_1155 v_b_362_3) (= (select |c_#memory_int| v_idx_1155) v_v_4887_1)) (<= 0 v_v_4887_1) (<= (+ v_b_362_3 3) v_b_339_3) (or (= (select |c_#memory_int| v_idx_1158) v_v_4529_2) (< v_idx_1158 .cse0) (<= v_b_338_3 v_idx_1158)) (or (<= v_b_362_3 v_idx_1154) (= (select |c_#memory_int| v_idx_1154) v_v_4525_1)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= v_v_4528_2 v_v_4887_1) (<= .cse2 v_b_335_3) (<= v_b_335_3 c_ULTIMATE.start_main_p2) (<= v_b_339_3 .cse1) (<= (+ v_b_362_3 2) v_b_338_3) (<= .cse2 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_1157) v_v_4528_2) (< v_idx_1157 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_1157)) (or (= 0 (select |c_#memory_int| v_idx_1159)) (< v_idx_1159 v_b_338_3) (<= v_b_339_3 v_idx_1159)) (<= (+ v_b_335_3 1) v_b_338_3) (<= v_b_335_3 .cse2))))) is different from false [2019-01-07 22:16:31,794 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-07 22:16:31,794 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-07 22:16:31,795 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-07 22:16:31,795 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [3] total 7 [2019-01-07 22:16:31,795 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:16:31,795 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-07 22:16:31,795 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-07 22:16:31,795 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-07 22:16:31,796 INFO L87 Difference]: Start difference. First operand 23 states and 70 transitions. Second operand 6 states. [2019-01-07 22:16:34,480 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_1137 Int) (v_idx_1136 Int) (v_idx_1135 Int) (v_idx_1134 Int) (v_idx_1133 Int) (v_idx_1139 Int) (v_idx_1138 Int)) (exists ((v_v_4531_2 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_v_4525_1 Int) (v_v_4526_1 Int)) (let ((.cse2 (+ v_b_338_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_1139 v_b_339_3) (= (select |c_#memory_int| v_idx_1139) v_v_4531_2)) (or (<= c_ULTIMATE.start_main_p2 v_idx_1135) (= (select |c_#memory_int| v_idx_1135) v_v_4527_1) (< v_idx_1135 .cse0)) (<= .cse1 v_b_338_3) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_338_3) (<= .cse2 v_b_339_3) (or (< v_idx_1138 v_b_338_3) (<= v_b_339_3 v_idx_1138) (= 0 (select |c_#memory_int| v_idx_1138))) (<= v_v_4528_2 0) (<= (* 2 v_v_4528_2) 0) (or (= (select |c_#memory_int| v_idx_1133) v_v_4525_1) (<= c_ULTIMATE.start_main_p1 v_idx_1133)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= v_b_339_3 .cse2) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_339_3) (or (= (select |c_#memory_int| v_idx_1137) v_v_4529_2) (< v_idx_1137 .cse1) (<= v_b_338_3 v_idx_1137)) (or (<= .cse0 v_idx_1134) (< v_idx_1134 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1134) v_v_4526_1)) (or (= (select |c_#memory_int| v_idx_1136) v_v_4528_2) (< v_idx_1136 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_1136)) (<= 0 v_v_4526_1) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_v_4528_2 v_v_4526_1) (<= 0 (* 2 v_v_4526_1)))))) (forall ((v_idx_1148 Int) (v_idx_1147 Int) (v_idx_1153 Int) (v_idx_1152 Int) (v_idx_1151 Int) (v_idx_1150 Int) (v_idx_1149 Int)) (exists ((v_v_4531_2 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_v_4525_1 Int) (v_v_4526_1 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ v_b_338_3 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= (select |c_#memory_int| v_idx_1150) v_v_4528_2) (<= .cse3 v_idx_1150) (< v_idx_1150 c_ULTIMATE.start_main_p2)) (<= .cse3 v_b_338_3) (or (< v_idx_1149 .cse4) (<= c_ULTIMATE.start_main_p2 v_idx_1149) (= (select |c_#memory_int| v_idx_1149) v_v_4527_1)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_338_3) (<= .cse5 v_b_339_3) (<= v_v_4528_2 0) (or (<= v_b_338_3 v_idx_1151) (= (select |c_#memory_int| v_idx_1151) v_v_4529_2) (< v_idx_1151 .cse3)) (<= (* 2 v_v_4528_2) 0) (or (<= .cse4 v_idx_1148) (= (select |c_#memory_int| v_idx_1148) v_v_4526_1) (< v_idx_1148 c_ULTIMATE.start_main_p1)) (or (< v_idx_1153 v_b_339_3) (= (select |c_#memory_int| v_idx_1153) v_v_4531_2)) (or (<= v_b_339_3 v_idx_1152) (< v_idx_1152 v_b_338_3) (= (select |c_#memory_int| v_idx_1152) 0)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= v_b_339_3 .cse5) (or (= (select |c_#memory_int| v_idx_1147) v_v_4525_1) (<= c_ULTIMATE.start_main_p1 v_idx_1147)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_339_3) (<= 0 v_v_4526_1) (<= .cse4 c_ULTIMATE.start_main_p2) (<= v_v_4528_2 v_v_4526_1) (<= 0 (* 2 v_v_4526_1)))))) (forall ((v_idx_1146 Int) (v_idx_1145 Int) (v_idx_1144 Int) (v_idx_1143 Int) (v_idx_1142 Int) (v_idx_1141 Int) (v_idx_1140 Int)) (exists ((v_v_4531_2 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_v_4525_1 Int) (v_v_4526_1 Int)) (let ((.cse8 (+ v_b_338_3 1)) (.cse7 (+ c_ULTIMATE.start_main_p2 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_1141 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1141) v_v_4526_1) (<= .cse6 v_idx_1141)) (<= .cse7 v_b_338_3) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_338_3) (<= .cse8 v_b_339_3) (<= v_v_4528_2 0) (<= (* 2 v_v_4528_2) 0) (or (< v_idx_1145 v_b_338_3) (= 0 (select |c_#memory_int| v_idx_1145)) (<= v_b_339_3 v_idx_1145)) (or (<= c_ULTIMATE.start_main_p1 v_idx_1140) (= (select |c_#memory_int| v_idx_1140) v_v_4525_1)) (or (< v_idx_1143 c_ULTIMATE.start_main_p2) (<= .cse7 v_idx_1143) (= (select |c_#memory_int| v_idx_1143) v_v_4528_2)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= v_b_339_3 .cse8) (or (<= c_ULTIMATE.start_main_p2 v_idx_1142) (= (select |c_#memory_int| v_idx_1142) v_v_4527_1) (< v_idx_1142 .cse6)) (or (= (select |c_#memory_int| v_idx_1146) v_v_4531_2) (< v_idx_1146 v_b_339_3)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_339_3) (or (<= v_b_338_3 v_idx_1144) (< v_idx_1144 .cse7) (= (select |c_#memory_int| v_idx_1144) v_v_4529_2)) (<= 0 v_v_4526_1) (<= .cse6 c_ULTIMATE.start_main_p2) (<= v_v_4528_2 v_v_4526_1) (<= 0 (* 2 v_v_4526_1)))))) (forall ((v_idx_1159 Int) (v_idx_1158 Int) (v_idx_1157 Int) (v_idx_1156 Int) (v_idx_1155 Int) (v_idx_1154 Int) (v_idx_1160 Int)) (exists ((v_v_4531_2 Int) (v_b_362_3 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_v_4887_1 Int) (v_b_335_3 Int) (v_v_4525_1 Int)) (let ((.cse10 (+ v_b_338_3 1)) (.cse9 (+ c_ULTIMATE.start_main_p2 1)) (.cse11 (+ v_b_362_3 1))) (and (or (< v_idx_1156 v_b_335_3) (<= c_ULTIMATE.start_main_p2 v_idx_1156) (= (select |c_#memory_int| v_idx_1156) v_v_4527_1)) (or (= (select |c_#memory_int| v_idx_1160) v_v_4531_2) (< v_idx_1160 v_b_339_3)) (<= .cse9 v_b_338_3) (<= (+ v_b_335_3 2) v_b_339_3) (<= .cse10 v_b_339_3) (<= v_v_4528_2 0) (<= (* 2 v_v_4528_2) 0) (<= 0 (* 2 v_v_4887_1)) (or (<= v_b_335_3 v_idx_1155) (< v_idx_1155 v_b_362_3) (= (select |c_#memory_int| v_idx_1155) v_v_4887_1)) (<= 0 v_v_4887_1) (<= (+ v_b_362_3 3) v_b_339_3) (or (= (select |c_#memory_int| v_idx_1158) v_v_4529_2) (< v_idx_1158 .cse9) (<= v_b_338_3 v_idx_1158)) (or (<= v_b_362_3 v_idx_1154) (= (select |c_#memory_int| v_idx_1154) v_v_4525_1)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= v_v_4528_2 v_v_4887_1) (<= .cse11 v_b_335_3) (<= v_b_335_3 c_ULTIMATE.start_main_p2) (<= v_b_339_3 .cse10) (<= (+ v_b_362_3 2) v_b_338_3) (<= .cse11 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_1157) v_v_4528_2) (< v_idx_1157 c_ULTIMATE.start_main_p2) (<= .cse9 v_idx_1157)) (or (= 0 (select |c_#memory_int| v_idx_1159)) (< v_idx_1159 v_b_338_3) (<= v_b_339_3 v_idx_1159)) (<= (+ v_b_335_3 1) v_b_338_3) (<= v_b_335_3 .cse11)))))) is different from false [2019-01-07 22:17:01,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:17:01,019 INFO L93 Difference]: Finished difference Result 27 states and 77 transitions. [2019-01-07 22:17:01,020 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-07 22:17:01,020 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2019-01-07 22:17:01,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:17:01,020 INFO L225 Difference]: With dead ends: 27 [2019-01-07 22:17:01,020 INFO L226 Difference]: Without dead ends: 26 [2019-01-07 22:17:01,021 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 17.1s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-07 22:17:01,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2019-01-07 22:17:01,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 24. [2019-01-07 22:17:01,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2019-01-07 22:17:01,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 74 transitions. [2019-01-07 22:17:01,052 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 74 transitions. Word has length 5 [2019-01-07 22:17:01,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:17:01,053 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 74 transitions. [2019-01-07 22:17:01,053 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-01-07 22:17:01,053 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 74 transitions. [2019-01-07 22:17:01,053 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-07 22:17:01,053 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:17:01,053 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-07 22:17:01,054 INFO L423 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:17:01,054 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:17:01,054 INFO L82 PathProgramCache]: Analyzing trace with hash 28819942, now seen corresponding path program 1 times [2019-01-07 22:17:01,054 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:17:01,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:17:01,055 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:17:01,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:17:01,055 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:17:01,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:17:01,262 WARN L181 SmtUtils]: Spent 157.00 ms on a formula simplification. DAG size of input: 29 DAG size of output: 17 [2019-01-07 22:17:01,302 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-07 22:17:01,302 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:17:01,303 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:17:01,303 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-07 22:17:01,303 INFO L207 CegarAbsIntRunner]: [0], [6], [12], [16], [17] [2019-01-07 22:17:01,305 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-07 22:17:01,305 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-07 22:17:14,701 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-07 22:17:14,702 INFO L272 AbstractInterpreter]: Visited 5 different actions 37 times. Merged at 3 different actions 16 times. Widened at 2 different actions 6 times. Found 10 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-07 22:17:14,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:17:14,702 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-07 22:17:15,118 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 53.57% of their original sizes. [2019-01-07 22:17:15,119 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-07 22:17:17,595 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1299 Int) (v_idx_1298 Int) (v_idx_1297 Int) (v_idx_1296 Int) (v_idx_1295 Int) (v_idx_1294 Int) (v_idx_1293 Int)) (exists ((v_v_4485_3 Int) (v_v_4484_3 Int) (v_v_4486_3 Int) (v_v_4480_3 Int) (v_v_4482_2 Int) (v_v_4481_2 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_1293) v_v_4480_3) (<= c_ULTIMATE.start_main_p1 v_idx_1293)) (or (= (select |c_#memory_int| v_idx_1298) v_v_4485_3) (<= .cse0 v_idx_1298) (< v_idx_1298 c_ULTIMATE.start_main_p3)) (<= 0 (* 2 v_v_4481_2)) (or (< v_idx_1297 .cse1) (<= c_ULTIMATE.start_main_p3 v_idx_1297) (= (select |c_#memory_int| v_idx_1297) v_v_4484_3)) (<= .cse1 c_ULTIMATE.start_main_p3) (or (<= .cse1 v_idx_1296) (= 0 (select |c_#memory_int| v_idx_1296)) (< v_idx_1296 c_ULTIMATE.start_main_p2)) (<= 0 (* 2 v_v_4485_3)) (or (< v_idx_1294 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_1294) (= (select |c_#memory_int| v_idx_1294) v_v_4481_2)) (<= 0 v_v_4485_3) (<= .cse2 c_ULTIMATE.start_main_p2) (or (< v_idx_1299 .cse0) (= (select |c_#memory_int| v_idx_1299) v_v_4486_3)) (or (< v_idx_1295 .cse2) (<= c_ULTIMATE.start_main_p2 v_idx_1295) (= (select |c_#memory_int| v_idx_1295) v_v_4482_2)) (<= 0 v_v_4481_2) (<= 0 (+ v_v_4485_3 v_v_4481_2)))))) is different from false [2019-01-07 22:17:20,209 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1302 Int) (v_idx_1301 Int) (v_idx_1300 Int) (v_idx_1306 Int) (v_idx_1305 Int) (v_idx_1304 Int) (v_idx_1303 Int)) (exists ((v_v_4485_3 Int) (v_v_4484_3 Int) (v_v_4486_3 Int) (v_v_4482_2 Int) (v_v_4480_3 Int) (v_v_4481_2 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p3 v_idx_1304) (< v_idx_1304 .cse0) (= (select |c_#memory_int| v_idx_1304) v_v_4484_3)) (or (<= c_ULTIMATE.start_main_p2 v_idx_1302) (= (select |c_#memory_int| v_idx_1302) v_v_4482_2) (< v_idx_1302 .cse1)) (<= 0 (* 2 v_v_4481_2)) (or (<= .cse1 v_idx_1301) (< v_idx_1301 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1301) v_v_4481_2)) (<= .cse0 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_4485_3)) (or (= (select |c_#memory_int| v_idx_1305) v_v_4485_3) (<= .cse2 v_idx_1305) (< v_idx_1305 c_ULTIMATE.start_main_p3)) (or (= (select |c_#memory_int| v_idx_1306) v_v_4486_3) (< v_idx_1306 .cse2)) (or (= (select |c_#memory_int| v_idx_1300) v_v_4480_3) (<= c_ULTIMATE.start_main_p1 v_idx_1300)) (<= 0 v_v_4485_3) (or (< v_idx_1303 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1303)) (<= .cse0 v_idx_1303)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= 0 v_v_4481_2) (<= 0 (+ v_v_4485_3 v_v_4481_2)))))) is different from false [2019-01-07 22:17:22,824 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1313 Int) (v_idx_1312 Int) (v_idx_1311 Int) (v_idx_1310 Int) (v_idx_1309 Int) (v_idx_1308 Int) (v_idx_1307 Int)) (exists ((v_v_4485_3 Int) (v_v_4484_3 Int) (v_v_4486_3 Int) (v_b_349_4 Int) (v_b_348_4 Int) (v_v_4482_2 Int) (v_v_4480_3 Int) (v_v_4481_2 Int)) (let ((.cse2 (+ v_b_348_4 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= 0 (select |c_#memory_int| v_idx_1310)) (< v_idx_1310 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_1310)) (or (< v_idx_1308 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_1308) (= (select |c_#memory_int| v_idx_1308) v_v_4481_2)) (<= v_b_349_4 .cse2) (<= 0 (* 2 v_v_4481_2)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_348_4) (or (< v_idx_1311 .cse0) (<= v_b_348_4 v_idx_1311) (= (select |c_#memory_int| v_idx_1311) v_v_4484_3)) (or (<= v_b_349_4 v_idx_1312) (= (select |c_#memory_int| v_idx_1312) v_v_4485_3) (< v_idx_1312 v_b_348_4)) (<= 0 (* 2 v_v_4485_3)) (<= .cse2 v_b_349_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_349_4) (<= 0 v_v_4485_3) (<= .cse1 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_1313) v_v_4486_3) (< v_idx_1313 v_b_349_4)) (<= .cse0 v_b_348_4) (or (= (select |c_#memory_int| v_idx_1309) v_v_4482_2) (< v_idx_1309 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_1309)) (<= 0 v_v_4481_2) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_349_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_1307) (= (select |c_#memory_int| v_idx_1307) v_v_4480_3)) (<= 0 (+ v_v_4485_3 v_v_4481_2)))))) is different from false [2019-01-07 22:17:25,204 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1320 Int) (v_idx_1319 Int) (v_idx_1318 Int) (v_idx_1317 Int) (v_idx_1316 Int) (v_idx_1315 Int) (v_idx_1314 Int)) (exists ((v_v_4485_3 Int) (v_b_372_4 Int) (v_v_4484_3 Int) (v_v_4486_3 Int) (v_b_349_4 Int) (v_b_348_4 Int) (v_v_4842_2 Int) (v_b_345_4 Int) (v_v_4482_2 Int) (v_v_4480_3 Int)) (let ((.cse1 (+ v_b_372_4 1)) (.cse0 (+ v_b_348_4 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1))) (and (<= 0 v_v_4842_2) (<= (+ v_b_345_4 2) v_b_349_4) (or (< v_idx_1320 v_b_349_4) (= (select |c_#memory_int| v_idx_1320) v_v_4486_3)) (or (< v_idx_1315 v_b_372_4) (= (select |c_#memory_int| v_idx_1315) v_v_4842_2) (<= v_b_345_4 v_idx_1315)) (<= v_b_349_4 .cse0) (<= (+ v_b_372_4 3) v_b_349_4) (<= v_b_345_4 c_ULTIMATE.start_main_p2) (<= v_b_345_4 .cse1) (<= 0 (+ v_v_4485_3 v_v_4842_2)) (<= .cse1 v_b_345_4) (or (< v_idx_1318 .cse2) (<= v_b_348_4 v_idx_1318) (= (select |c_#memory_int| v_idx_1318) v_v_4484_3)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= (+ v_b_372_4 2) v_b_348_4) (<= 0 (* 2 v_v_4485_3)) (<= (+ v_b_345_4 1) v_b_348_4) (or (< v_idx_1316 v_b_345_4) (= (select |c_#memory_int| v_idx_1316) v_v_4482_2) (<= c_ULTIMATE.start_main_p2 v_idx_1316)) (<= .cse0 v_b_349_4) (or (<= v_b_349_4 v_idx_1319) (= (select |c_#memory_int| v_idx_1319) v_v_4485_3) (< v_idx_1319 v_b_348_4)) (<= 0 v_v_4485_3) (or (<= .cse2 v_idx_1317) (< v_idx_1317 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1317))) (<= .cse2 v_b_348_4) (<= 0 (* 2 v_v_4842_2)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_349_4) (or (<= v_b_372_4 v_idx_1314) (= (select |c_#memory_int| v_idx_1314) v_v_4480_3)))))) is different from false [2019-01-07 22:17:25,276 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-07 22:17:25,276 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-07 22:17:25,277 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-07 22:17:25,277 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [3] total 7 [2019-01-07 22:17:25,277 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:17:25,277 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-07 22:17:25,277 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-07 22:17:25,277 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-07 22:17:25,278 INFO L87 Difference]: Start difference. First operand 24 states and 74 transitions. Second operand 6 states. [2019-01-07 22:17:27,998 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_1320 Int) (v_idx_1319 Int) (v_idx_1318 Int) (v_idx_1317 Int) (v_idx_1316 Int) (v_idx_1315 Int) (v_idx_1314 Int)) (exists ((v_v_4485_3 Int) (v_b_372_4 Int) (v_v_4484_3 Int) (v_v_4486_3 Int) (v_b_349_4 Int) (v_b_348_4 Int) (v_v_4842_2 Int) (v_b_345_4 Int) (v_v_4482_2 Int) (v_v_4480_3 Int)) (let ((.cse1 (+ v_b_372_4 1)) (.cse0 (+ v_b_348_4 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1))) (and (<= 0 v_v_4842_2) (<= (+ v_b_345_4 2) v_b_349_4) (or (< v_idx_1320 v_b_349_4) (= (select |c_#memory_int| v_idx_1320) v_v_4486_3)) (or (< v_idx_1315 v_b_372_4) (= (select |c_#memory_int| v_idx_1315) v_v_4842_2) (<= v_b_345_4 v_idx_1315)) (<= v_b_349_4 .cse0) (<= (+ v_b_372_4 3) v_b_349_4) (<= v_b_345_4 c_ULTIMATE.start_main_p2) (<= v_b_345_4 .cse1) (<= 0 (+ v_v_4485_3 v_v_4842_2)) (<= .cse1 v_b_345_4) (or (< v_idx_1318 .cse2) (<= v_b_348_4 v_idx_1318) (= (select |c_#memory_int| v_idx_1318) v_v_4484_3)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= (+ v_b_372_4 2) v_b_348_4) (<= 0 (* 2 v_v_4485_3)) (<= (+ v_b_345_4 1) v_b_348_4) (or (< v_idx_1316 v_b_345_4) (= (select |c_#memory_int| v_idx_1316) v_v_4482_2) (<= c_ULTIMATE.start_main_p2 v_idx_1316)) (<= .cse0 v_b_349_4) (or (<= v_b_349_4 v_idx_1319) (= (select |c_#memory_int| v_idx_1319) v_v_4485_3) (< v_idx_1319 v_b_348_4)) (<= 0 v_v_4485_3) (or (<= .cse2 v_idx_1317) (< v_idx_1317 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1317))) (<= .cse2 v_b_348_4) (<= 0 (* 2 v_v_4842_2)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_349_4) (or (<= v_b_372_4 v_idx_1314) (= (select |c_#memory_int| v_idx_1314) v_v_4480_3)))))) (forall ((v_idx_1299 Int) (v_idx_1298 Int) (v_idx_1297 Int) (v_idx_1296 Int) (v_idx_1295 Int) (v_idx_1294 Int) (v_idx_1293 Int)) (exists ((v_v_4485_3 Int) (v_v_4484_3 Int) (v_v_4486_3 Int) (v_v_4480_3 Int) (v_v_4482_2 Int) (v_v_4481_2 Int)) (let ((.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse3 (+ c_ULTIMATE.start_main_p3 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_1293) v_v_4480_3) (<= c_ULTIMATE.start_main_p1 v_idx_1293)) (or (= (select |c_#memory_int| v_idx_1298) v_v_4485_3) (<= .cse3 v_idx_1298) (< v_idx_1298 c_ULTIMATE.start_main_p3)) (<= 0 (* 2 v_v_4481_2)) (or (< v_idx_1297 .cse4) (<= c_ULTIMATE.start_main_p3 v_idx_1297) (= (select |c_#memory_int| v_idx_1297) v_v_4484_3)) (<= .cse4 c_ULTIMATE.start_main_p3) (or (<= .cse4 v_idx_1296) (= 0 (select |c_#memory_int| v_idx_1296)) (< v_idx_1296 c_ULTIMATE.start_main_p2)) (<= 0 (* 2 v_v_4485_3)) (or (< v_idx_1294 c_ULTIMATE.start_main_p1) (<= .cse5 v_idx_1294) (= (select |c_#memory_int| v_idx_1294) v_v_4481_2)) (<= 0 v_v_4485_3) (<= .cse5 c_ULTIMATE.start_main_p2) (or (< v_idx_1299 .cse3) (= (select |c_#memory_int| v_idx_1299) v_v_4486_3)) (or (< v_idx_1295 .cse5) (<= c_ULTIMATE.start_main_p2 v_idx_1295) (= (select |c_#memory_int| v_idx_1295) v_v_4482_2)) (<= 0 v_v_4481_2) (<= 0 (+ v_v_4485_3 v_v_4481_2)))))) (forall ((v_idx_1313 Int) (v_idx_1312 Int) (v_idx_1311 Int) (v_idx_1310 Int) (v_idx_1309 Int) (v_idx_1308 Int) (v_idx_1307 Int)) (exists ((v_v_4485_3 Int) (v_v_4484_3 Int) (v_v_4486_3 Int) (v_b_349_4 Int) (v_b_348_4 Int) (v_v_4482_2 Int) (v_v_4480_3 Int) (v_v_4481_2 Int)) (let ((.cse8 (+ v_b_348_4 1)) (.cse6 (+ c_ULTIMATE.start_main_p2 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= 0 (select |c_#memory_int| v_idx_1310)) (< v_idx_1310 c_ULTIMATE.start_main_p2) (<= .cse6 v_idx_1310)) (or (< v_idx_1308 c_ULTIMATE.start_main_p1) (<= .cse7 v_idx_1308) (= (select |c_#memory_int| v_idx_1308) v_v_4481_2)) (<= v_b_349_4 .cse8) (<= 0 (* 2 v_v_4481_2)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_348_4) (or (< v_idx_1311 .cse6) (<= v_b_348_4 v_idx_1311) (= (select |c_#memory_int| v_idx_1311) v_v_4484_3)) (or (<= v_b_349_4 v_idx_1312) (= (select |c_#memory_int| v_idx_1312) v_v_4485_3) (< v_idx_1312 v_b_348_4)) (<= 0 (* 2 v_v_4485_3)) (<= .cse8 v_b_349_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_349_4) (<= 0 v_v_4485_3) (<= .cse7 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_1313) v_v_4486_3) (< v_idx_1313 v_b_349_4)) (<= .cse6 v_b_348_4) (or (= (select |c_#memory_int| v_idx_1309) v_v_4482_2) (< v_idx_1309 .cse7) (<= c_ULTIMATE.start_main_p2 v_idx_1309)) (<= 0 v_v_4481_2) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_349_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_1307) (= (select |c_#memory_int| v_idx_1307) v_v_4480_3)) (<= 0 (+ v_v_4485_3 v_v_4481_2)))))) (forall ((v_idx_1302 Int) (v_idx_1301 Int) (v_idx_1300 Int) (v_idx_1306 Int) (v_idx_1305 Int) (v_idx_1304 Int) (v_idx_1303 Int)) (exists ((v_v_4485_3 Int) (v_v_4484_3 Int) (v_v_4486_3 Int) (v_v_4482_2 Int) (v_v_4480_3 Int) (v_v_4481_2 Int)) (let ((.cse11 (+ c_ULTIMATE.start_main_p3 1)) (.cse9 (+ c_ULTIMATE.start_main_p2 1)) (.cse10 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p3 v_idx_1304) (< v_idx_1304 .cse9) (= (select |c_#memory_int| v_idx_1304) v_v_4484_3)) (or (<= c_ULTIMATE.start_main_p2 v_idx_1302) (= (select |c_#memory_int| v_idx_1302) v_v_4482_2) (< v_idx_1302 .cse10)) (<= 0 (* 2 v_v_4481_2)) (or (<= .cse10 v_idx_1301) (< v_idx_1301 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1301) v_v_4481_2)) (<= .cse9 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_4485_3)) (or (= (select |c_#memory_int| v_idx_1305) v_v_4485_3) (<= .cse11 v_idx_1305) (< v_idx_1305 c_ULTIMATE.start_main_p3)) (or (= (select |c_#memory_int| v_idx_1306) v_v_4486_3) (< v_idx_1306 .cse11)) (or (= (select |c_#memory_int| v_idx_1300) v_v_4480_3) (<= c_ULTIMATE.start_main_p1 v_idx_1300)) (<= 0 v_v_4485_3) (or (< v_idx_1303 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1303)) (<= .cse9 v_idx_1303)) (<= .cse10 c_ULTIMATE.start_main_p2) (<= 0 v_v_4481_2) (<= 0 (+ v_v_4485_3 v_v_4481_2))))))) is different from false [2019-01-07 22:17:49,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:17:49,631 INFO L93 Difference]: Finished difference Result 28 states and 81 transitions. [2019-01-07 22:17:49,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-07 22:17:49,632 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2019-01-07 22:17:49,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:17:49,632 INFO L225 Difference]: With dead ends: 28 [2019-01-07 22:17:49,632 INFO L226 Difference]: Without dead ends: 27 [2019-01-07 22:17:49,633 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.6s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-07 22:17:49,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2019-01-07 22:17:49,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 24. [2019-01-07 22:17:49,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2019-01-07 22:17:49,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 74 transitions. [2019-01-07 22:17:49,660 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 74 transitions. Word has length 5 [2019-01-07 22:17:49,660 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:17:49,660 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 74 transitions. [2019-01-07 22:17:49,660 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-01-07 22:17:49,660 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 74 transitions. [2019-01-07 22:17:49,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-07 22:17:49,660 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:17:49,661 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-07 22:17:49,661 INFO L423 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:17:49,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:17:49,661 INFO L82 PathProgramCache]: Analyzing trace with hash 28943014, now seen corresponding path program 1 times [2019-01-07 22:17:49,661 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:17:49,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:17:49,662 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:17:49,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:17:49,662 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:17:49,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:17:49,739 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-07 22:17:49,740 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-07 22:17:49,740 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-01-07 22:17:49,740 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:17:49,741 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-07 22:17:49,741 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-07 22:17:49,741 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-01-07 22:17:49,741 INFO L87 Difference]: Start difference. First operand 24 states and 74 transitions. Second operand 4 states. [2019-01-07 22:17:49,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:17:49,796 INFO L93 Difference]: Finished difference Result 29 states and 78 transitions. [2019-01-07 22:17:49,797 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-07 22:17:49,797 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 5 [2019-01-07 22:17:49,797 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:17:49,798 INFO L225 Difference]: With dead ends: 29 [2019-01-07 22:17:49,798 INFO L226 Difference]: Without dead ends: 26 [2019-01-07 22:17:49,798 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-01-07 22:17:49,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2019-01-07 22:17:49,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 25. [2019-01-07 22:17:49,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-01-07 22:17:49,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 74 transitions. [2019-01-07 22:17:49,825 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 74 transitions. Word has length 5 [2019-01-07 22:17:49,825 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:17:49,825 INFO L480 AbstractCegarLoop]: Abstraction has 25 states and 74 transitions. [2019-01-07 22:17:49,826 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-07 22:17:49,826 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 74 transitions. [2019-01-07 22:17:49,826 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-07 22:17:49,826 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:17:49,826 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-07 22:17:49,826 INFO L423 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:17:49,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:17:49,827 INFO L82 PathProgramCache]: Analyzing trace with hash 28933340, now seen corresponding path program 2 times [2019-01-07 22:17:49,827 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:17:49,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:17:49,828 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-07 22:17:49,828 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:17:49,828 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:17:49,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:17:49,909 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:17:49,910 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:17:49,910 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:17:49,910 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-07 22:17:49,911 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-07 22:17:49,911 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:17:49,911 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-07 22:17:49,928 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-07 22:17:49,929 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-07 22:17:49,936 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-07 22:17:49,937 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-07 22:17:49,937 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-07 22:17:49,945 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-07 22:17:49,947 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:17:49,948 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-07 22:17:49,950 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:17:49,951 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:17:49,952 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-07 22:17:49,952 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-07 22:17:49,963 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-07 22:17:49,969 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-07 22:17:49,980 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-07 22:17:49,980 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:19, output treesize:22 [2019-01-07 22:17:50,005 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:17:50,007 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:17:50,008 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:17:50,009 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:17:50,010 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-07 22:17:50,011 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-07 22:17:50,034 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-07 22:17:50,035 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-07 22:17:50,053 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:17:50,054 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:17:50,055 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:17:50,056 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:17:50,057 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:17:50,058 INFO L701 Elim1Store]: detected not equals via solver [2019-01-07 22:17:50,059 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 42 [2019-01-07 22:17:50,060 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-07 22:17:50,087 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-07 22:17:50,087 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:24 [2019-01-07 22:17:50,107 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:17:50,108 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-07 22:17:50,187 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:17:50,208 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-07 22:17:50,208 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 9 [2019-01-07 22:17:50,208 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-07 22:17:50,208 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-01-07 22:17:50,208 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-01-07 22:17:50,208 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-01-07 22:17:50,209 INFO L87 Difference]: Start difference. First operand 25 states and 74 transitions. Second operand 8 states. [2019-01-07 22:17:50,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-07 22:17:50,515 INFO L93 Difference]: Finished difference Result 39 states and 95 transitions. [2019-01-07 22:17:50,515 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-01-07 22:17:50,515 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 5 [2019-01-07 22:17:50,515 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-07 22:17:50,516 INFO L225 Difference]: With dead ends: 39 [2019-01-07 22:17:50,516 INFO L226 Difference]: Without dead ends: 37 [2019-01-07 22:17:50,517 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=53, Invalid=79, Unknown=0, NotChecked=0, Total=132 [2019-01-07 22:17:50,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2019-01-07 22:17:50,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 24. [2019-01-07 22:17:50,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2019-01-07 22:17:50,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 71 transitions. [2019-01-07 22:17:50,545 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 71 transitions. Word has length 5 [2019-01-07 22:17:50,545 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-07 22:17:50,545 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 71 transitions. [2019-01-07 22:17:50,545 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-01-07 22:17:50,545 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 71 transitions. [2019-01-07 22:17:50,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-07 22:17:50,545 INFO L394 BasicCegarLoop]: Found error trace [2019-01-07 22:17:50,545 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-07 22:17:50,546 INFO L423 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-07 22:17:50,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:17:50,546 INFO L82 PathProgramCache]: Analyzing trace with hash 28939106, now seen corresponding path program 1 times [2019-01-07 22:17:50,546 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-07 22:17:50,547 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:17:50,547 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-07 22:17:50,547 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-07 22:17:50,547 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-07 22:17:50,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-07 22:17:50,620 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-07 22:17:50,621 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-07 22:17:50,621 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-07 22:17:50,621 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-07 22:17:50,621 INFO L207 CegarAbsIntRunner]: [0], [10], [12], [16], [17] [2019-01-07 22:17:50,622 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-07 22:17:50,622 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-07 22:18:05,157 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-07 22:18:05,157 INFO L272 AbstractInterpreter]: Visited 5 different actions 37 times. Merged at 3 different actions 16 times. Widened at 2 different actions 6 times. Found 10 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-07 22:18:05,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-07 22:18:05,157 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-07 22:18:05,656 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 53.57% of their original sizes. [2019-01-07 22:18:05,656 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-07 22:18:08,090 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1456 Int) (v_idx_1455 Int) (v_idx_1454 Int) (v_idx_1453 Int) (v_idx_1459 Int) (v_idx_1458 Int) (v_idx_1457 Int)) (exists ((v_v_4645_3 Int) (v_v_4647_3 Int) (v_v_4649_3 Int) (v_v_4648_3 Int) (v_v_4650_3 Int) (v_v_4651_3 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_1454 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_1454) (= (select |c_#memory_int| v_idx_1454) 0)) (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= v_v_4648_3 0) (<= v_v_4648_3 v_v_4650_3) (<= 0 v_v_4650_3) (<= 0 (* 2 v_v_4650_3)) (or (= (select |c_#memory_int| v_idx_1456) v_v_4648_3) (<= .cse1 v_idx_1456) (< v_idx_1456 c_ULTIMATE.start_main_p2)) (or (= (select |c_#memory_int| v_idx_1453) v_v_4645_3) (<= c_ULTIMATE.start_main_p1 v_idx_1453)) (<= .cse1 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_1457) v_v_4649_3) (<= c_ULTIMATE.start_main_p3 v_idx_1457) (< v_idx_1457 .cse1)) (or (= (select |c_#memory_int| v_idx_1459) v_v_4651_3) (< v_idx_1459 .cse2)) (<= (* 2 v_v_4648_3) 0) (or (< v_idx_1458 c_ULTIMATE.start_main_p3) (<= .cse2 v_idx_1458) (= (select |c_#memory_int| v_idx_1458) v_v_4650_3)) (or (= (select |c_#memory_int| v_idx_1455) v_v_4647_3) (<= c_ULTIMATE.start_main_p2 v_idx_1455) (< v_idx_1455 .cse0)) (<= .cse0 c_ULTIMATE.start_main_p2))))) is different from false [2019-01-07 22:18:10,701 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1466 Int) (v_idx_1465 Int) (v_idx_1464 Int) (v_idx_1463 Int) (v_idx_1462 Int) (v_idx_1461 Int) (v_idx_1460 Int)) (exists ((v_v_4645_3 Int) (v_v_4647_3 Int) (v_v_4649_3 Int) (v_v_4648_3 Int) (v_v_4650_3 Int) (v_v_4651_3 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p1 v_idx_1460) (= (select |c_#memory_int| v_idx_1460) v_v_4645_3)) (or (< v_idx_1461 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_1461)) (<= .cse0 v_idx_1461)) (or (= (select |c_#memory_int| v_idx_1466) v_v_4651_3) (< v_idx_1466 .cse1)) (<= v_v_4648_3 0) (<= v_v_4648_3 v_v_4650_3) (<= 0 v_v_4650_3) (or (< v_idx_1463 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1463) v_v_4648_3) (<= .cse2 v_idx_1463)) (<= 0 (* 2 v_v_4650_3)) (<= .cse2 c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p2 v_idx_1462) (< v_idx_1462 .cse0) (= (select |c_#memory_int| v_idx_1462) v_v_4647_3)) (or (<= c_ULTIMATE.start_main_p3 v_idx_1464) (= (select |c_#memory_int| v_idx_1464) v_v_4649_3) (< v_idx_1464 .cse2)) (<= (* 2 v_v_4648_3) 0) (or (<= .cse1 v_idx_1465) (= (select |c_#memory_int| v_idx_1465) v_v_4650_3) (< v_idx_1465 c_ULTIMATE.start_main_p3)) (<= .cse0 c_ULTIMATE.start_main_p2))))) is different from false [2019-01-07 22:18:13,353 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1467 Int) (v_idx_1473 Int) (v_idx_1472 Int) (v_idx_1471 Int) (v_idx_1470 Int) (v_idx_1469 Int) (v_idx_1468 Int)) (exists ((v_v_4645_3 Int) (v_v_4647_3 Int) (v_v_4649_3 Int) (v_v_4648_3 Int) (v_b_359_5 Int) (v_b_358_5 Int) (v_v_4650_3 Int) (v_v_4651_3 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_358_5 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_1467) (= (select |c_#memory_int| v_idx_1467) v_v_4645_3)) (or (<= v_b_358_5 v_idx_1471) (= (select |c_#memory_int| v_idx_1471) v_v_4649_3) (< v_idx_1471 .cse0)) (<= v_v_4648_3 0) (<= v_b_359_5 .cse1) (<= v_v_4648_3 v_v_4650_3) (<= .cse0 v_b_358_5) (or (< v_idx_1470 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1470) v_v_4648_3) (<= .cse0 v_idx_1470)) (<= .cse1 v_b_359_5) (<= 0 v_v_4650_3) (or (= (select |c_#memory_int| v_idx_1473) v_v_4651_3) (< v_idx_1473 v_b_359_5)) (<= 0 (* 2 v_v_4650_3)) (or (= 0 (select |c_#memory_int| v_idx_1468)) (<= .cse2 v_idx_1468) (< v_idx_1468 c_ULTIMATE.start_main_p1)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_359_5) (or (<= v_b_359_5 v_idx_1472) (< v_idx_1472 v_b_358_5) (= (select |c_#memory_int| v_idx_1472) v_v_4650_3)) (or (= (select |c_#memory_int| v_idx_1469) v_v_4647_3) (<= c_ULTIMATE.start_main_p2 v_idx_1469) (< v_idx_1469 .cse2)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_359_5) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_358_5) (<= (* 2 v_v_4648_3) 0) (<= .cse2 c_ULTIMATE.start_main_p2))))) is different from false [2019-01-07 22:18:15,586 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1478 Int) (v_idx_1477 Int) (v_idx_1476 Int) (v_idx_1475 Int) (v_idx_1474 Int) (v_idx_1480 Int) (v_idx_1479 Int)) (exists ((v_v_4645_3 Int) (v_b_382_5 Int) (v_v_4647_3 Int) (v_v_4649_3 Int) (v_v_4648_3 Int) (v_b_359_5 Int) (v_b_358_5 Int) (v_v_4650_3 Int) (v_b_355_5 Int) (v_v_4651_3 Int)) (let ((.cse0 (+ v_b_358_5 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_382_5 1))) (and (or (= (select |c_#memory_int| v_idx_1479) v_v_4650_3) (<= v_b_359_5 v_idx_1479) (< v_idx_1479 v_b_358_5)) (<= v_v_4648_3 0) (<= v_b_359_5 .cse0) (<= v_v_4648_3 v_v_4650_3) (<= (+ v_b_382_5 3) v_b_359_5) (<= .cse1 v_b_358_5) (<= (+ v_b_382_5 2) v_b_358_5) (<= .cse2 v_b_355_5) (<= .cse0 v_b_359_5) (<= 0 v_v_4650_3) (or (< v_idx_1478 .cse1) (= (select |c_#memory_int| v_idx_1478) v_v_4649_3) (<= v_b_358_5 v_idx_1478)) (<= v_b_355_5 .cse2) (or (<= v_b_382_5 v_idx_1474) (= (select |c_#memory_int| v_idx_1474) v_v_4645_3)) (<= 0 (* 2 v_v_4650_3)) (or (<= v_b_355_5 v_idx_1475) (< v_idx_1475 v_b_382_5) (= 0 (select |c_#memory_int| v_idx_1475))) (or (<= .cse1 v_idx_1477) (< v_idx_1477 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1477) v_v_4648_3)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_359_5) (<= (+ v_b_355_5 1) v_b_358_5) (or (<= c_ULTIMATE.start_main_p2 v_idx_1476) (= (select |c_#memory_int| v_idx_1476) v_v_4647_3) (< v_idx_1476 v_b_355_5)) (or (= (select |c_#memory_int| v_idx_1480) v_v_4651_3) (< v_idx_1480 v_b_359_5)) (<= v_b_355_5 c_ULTIMATE.start_main_p2) (<= (* 2 v_v_4648_3) 0) (<= .cse2 c_ULTIMATE.start_main_p2) (<= (+ v_b_355_5 2) v_b_359_5))))) is different from false [2019-01-07 22:18:15,656 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-07 22:18:15,656 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-07 22:18:15,656 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-07 22:18:15,656 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [3] total 7 [2019-01-07 22:18:15,656 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-07 22:18:15,657 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-07 22:18:15,657 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-07 22:18:15,657 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-07 22:18:15,657 INFO L87 Difference]: Start difference. First operand 24 states and 71 transitions. Second operand 6 states. [2019-01-07 22:18:18,297 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_1467 Int) (v_idx_1473 Int) (v_idx_1472 Int) (v_idx_1471 Int) (v_idx_1470 Int) (v_idx_1469 Int) (v_idx_1468 Int)) (exists ((v_v_4645_3 Int) (v_v_4647_3 Int) (v_v_4649_3 Int) (v_v_4648_3 Int) (v_b_359_5 Int) (v_b_358_5 Int) (v_v_4650_3 Int) (v_v_4651_3 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_358_5 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_1467) (= (select |c_#memory_int| v_idx_1467) v_v_4645_3)) (or (<= v_b_358_5 v_idx_1471) (= (select |c_#memory_int| v_idx_1471) v_v_4649_3) (< v_idx_1471 .cse0)) (<= v_v_4648_3 0) (<= v_b_359_5 .cse1) (<= v_v_4648_3 v_v_4650_3) (<= .cse0 v_b_358_5) (or (< v_idx_1470 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1470) v_v_4648_3) (<= .cse0 v_idx_1470)) (<= .cse1 v_b_359_5) (<= 0 v_v_4650_3) (or (= (select |c_#memory_int| v_idx_1473) v_v_4651_3) (< v_idx_1473 v_b_359_5)) (<= 0 (* 2 v_v_4650_3)) (or (= 0 (select |c_#memory_int| v_idx_1468)) (<= .cse2 v_idx_1468) (< v_idx_1468 c_ULTIMATE.start_main_p1)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_359_5) (or (<= v_b_359_5 v_idx_1472) (< v_idx_1472 v_b_358_5) (= (select |c_#memory_int| v_idx_1472) v_v_4650_3)) (or (= (select |c_#memory_int| v_idx_1469) v_v_4647_3) (<= c_ULTIMATE.start_main_p2 v_idx_1469) (< v_idx_1469 .cse2)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_359_5) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_358_5) (<= (* 2 v_v_4648_3) 0) (<= .cse2 c_ULTIMATE.start_main_p2))))) (forall ((v_idx_1456 Int) (v_idx_1455 Int) (v_idx_1454 Int) (v_idx_1453 Int) (v_idx_1459 Int) (v_idx_1458 Int) (v_idx_1457 Int)) (exists ((v_v_4645_3 Int) (v_v_4647_3 Int) (v_v_4649_3 Int) (v_v_4648_3 Int) (v_v_4650_3 Int) (v_v_4651_3 Int)) (let ((.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ c_ULTIMATE.start_main_p3 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_1454 c_ULTIMATE.start_main_p1) (<= .cse3 v_idx_1454) (= (select |c_#memory_int| v_idx_1454) 0)) (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= v_v_4648_3 0) (<= v_v_4648_3 v_v_4650_3) (<= 0 v_v_4650_3) (<= 0 (* 2 v_v_4650_3)) (or (= (select |c_#memory_int| v_idx_1456) v_v_4648_3) (<= .cse4 v_idx_1456) (< v_idx_1456 c_ULTIMATE.start_main_p2)) (or (= (select |c_#memory_int| v_idx_1453) v_v_4645_3) (<= c_ULTIMATE.start_main_p1 v_idx_1453)) (<= .cse4 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_1457) v_v_4649_3) (<= c_ULTIMATE.start_main_p3 v_idx_1457) (< v_idx_1457 .cse4)) (or (= (select |c_#memory_int| v_idx_1459) v_v_4651_3) (< v_idx_1459 .cse5)) (<= (* 2 v_v_4648_3) 0) (or (< v_idx_1458 c_ULTIMATE.start_main_p3) (<= .cse5 v_idx_1458) (= (select |c_#memory_int| v_idx_1458) v_v_4650_3)) (or (= (select |c_#memory_int| v_idx_1455) v_v_4647_3) (<= c_ULTIMATE.start_main_p2 v_idx_1455) (< v_idx_1455 .cse3)) (<= .cse3 c_ULTIMATE.start_main_p2))))) (forall ((v_idx_1478 Int) (v_idx_1477 Int) (v_idx_1476 Int) (v_idx_1475 Int) (v_idx_1474 Int) (v_idx_1480 Int) (v_idx_1479 Int)) (exists ((v_v_4645_3 Int) (v_b_382_5 Int) (v_v_4647_3 Int) (v_v_4649_3 Int) (v_v_4648_3 Int) (v_b_359_5 Int) (v_b_358_5 Int) (v_v_4650_3 Int) (v_b_355_5 Int) (v_v_4651_3 Int)) (let ((.cse6 (+ v_b_358_5 1)) (.cse7 (+ c_ULTIMATE.start_main_p2 1)) (.cse8 (+ v_b_382_5 1))) (and (or (= (select |c_#memory_int| v_idx_1479) v_v_4650_3) (<= v_b_359_5 v_idx_1479) (< v_idx_1479 v_b_358_5)) (<= v_v_4648_3 0) (<= v_b_359_5 .cse6) (<= v_v_4648_3 v_v_4650_3) (<= (+ v_b_382_5 3) v_b_359_5) (<= .cse7 v_b_358_5) (<= (+ v_b_382_5 2) v_b_358_5) (<= .cse8 v_b_355_5) (<= .cse6 v_b_359_5) (<= 0 v_v_4650_3) (or (< v_idx_1478 .cse7) (= (select |c_#memory_int| v_idx_1478) v_v_4649_3) (<= v_b_358_5 v_idx_1478)) (<= v_b_355_5 .cse8) (or (<= v_b_382_5 v_idx_1474) (= (select |c_#memory_int| v_idx_1474) v_v_4645_3)) (<= 0 (* 2 v_v_4650_3)) (or (<= v_b_355_5 v_idx_1475) (< v_idx_1475 v_b_382_5) (= 0 (select |c_#memory_int| v_idx_1475))) (or (<= .cse7 v_idx_1477) (< v_idx_1477 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1477) v_v_4648_3)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_359_5) (<= (+ v_b_355_5 1) v_b_358_5) (or (<= c_ULTIMATE.start_main_p2 v_idx_1476) (= (select |c_#memory_int| v_idx_1476) v_v_4647_3) (< v_idx_1476 v_b_355_5)) (or (= (select |c_#memory_int| v_idx_1480) v_v_4651_3) (< v_idx_1480 v_b_359_5)) (<= v_b_355_5 c_ULTIMATE.start_main_p2) (<= (* 2 v_v_4648_3) 0) (<= .cse8 c_ULTIMATE.start_main_p2) (<= (+ v_b_355_5 2) v_b_359_5))))) (forall ((v_idx_1466 Int) (v_idx_1465 Int) (v_idx_1464 Int) (v_idx_1463 Int) (v_idx_1462 Int) (v_idx_1461 Int) (v_idx_1460 Int)) (exists ((v_v_4645_3 Int) (v_v_4647_3 Int) (v_v_4649_3 Int) (v_v_4648_3 Int) (v_v_4650_3 Int) (v_v_4651_3 Int)) (let ((.cse11 (+ c_ULTIMATE.start_main_p2 1)) (.cse10 (+ c_ULTIMATE.start_main_p3 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p1 v_idx_1460) (= (select |c_#memory_int| v_idx_1460) v_v_4645_3)) (or (< v_idx_1461 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_1461)) (<= .cse9 v_idx_1461)) (or (= (select |c_#memory_int| v_idx_1466) v_v_4651_3) (< v_idx_1466 .cse10)) (<= v_v_4648_3 0) (<= v_v_4648_3 v_v_4650_3) (<= 0 v_v_4650_3) (or (< v_idx_1463 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1463) v_v_4648_3) (<= .cse11 v_idx_1463)) (<= 0 (* 2 v_v_4650_3)) (<= .cse11 c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p2 v_idx_1462) (< v_idx_1462 .cse9) (= (select |c_#memory_int| v_idx_1462) v_v_4647_3)) (or (<= c_ULTIMATE.start_main_p3 v_idx_1464) (= (select |c_#memory_int| v_idx_1464) v_v_4649_3) (< v_idx_1464 .cse11)) (<= (* 2 v_v_4648_3) 0) (or (<= .cse10 v_idx_1465) (= (select |c_#memory_int| v_idx_1465) v_v_4650_3) (< v_idx_1465 c_ULTIMATE.start_main_p3)) (<= .cse9 c_ULTIMATE.start_main_p2)))))) is different from false [2019-01-07 22:18:18,843 WARN L194 Executor]: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000) stderr output: (error "out of memory") [2019-01-07 22:18:18,843 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-07 22:18:18,844 FATAL L265 ToolchainWalker]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:208) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parseCheckSatResult(Executor.java:225) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Scriptor.checkSat(Scriptor.java:155) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.WrapperScript.checkSat(WrapperScript.java:116) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.managedscript.ManagedScript.checkSat(ManagedScript.java:141) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.hoaretriple.IncrementalHoareTripleChecker.checkValidity(IncrementalHoareTripleChecker.java:666) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.hoaretriple.IncrementalHoareTripleChecker.checkInternal(IncrementalHoareTripleChecker.java:133) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.AbsIntHoareTripleChecker.checkInternal(AbsIntHoareTripleChecker.java:186) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.CachingHoareTripleChecker.checkInternal(CachingHoareTripleChecker.java:98) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.AbstractInterpolantAutomaton$InternalSuccessorComputationHelper.computeSuccWithSolver(AbstractInterpolantAutomaton.java:359) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.BasicAbstractInterpolantAutomaton.chooseFalseSuccessor2(BasicAbstractInterpolantAutomaton.java:106) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.BasicAbstractInterpolantAutomaton.computeSuccs(BasicAbstractInterpolantAutomaton.java:72) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.BasicAbstractInterpolantAutomaton.computeSuccs(BasicAbstractInterpolantAutomaton.java:1) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.AbstractInterpolantAutomaton.internalSuccessors(AbstractInterpolantAutomaton.java:234) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.AbstractInterpolantAutomaton.internalSuccessors(AbstractInterpolantAutomaton.java:1) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.TotalizeNwa.internalSuccessors(TotalizeNwa.java:213) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ComplementDeterministicNwa.internalSuccessors(ComplementDeterministicNwa.java:121) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ProductNwa.internalSuccessors(ProductNwa.java:216) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ProductNwa.internalSuccessors(ProductNwa.java:208) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates$ReachableStatesComputation.addInternalsAndSuccessors(NestedWordAutomatonReachableStates.java:1066) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates$ReachableStatesComputation.(NestedWordAutomatonReachableStates.java:968) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates.(NestedWordAutomatonReachableStates.java:188) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.Difference.computeDifference(Difference.java:137) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.Difference.(Difference.java:90) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.computeAutomataDifference(BasicCegarLoop.java:699) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.refineAbstraction(BasicCegarLoop.java:628) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:472) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:376) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:334) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:174) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:126) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:123) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:316) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) Caused by: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: EOF at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser$Action$.CUP$do_action(Parser.java:1427) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser.do_action(Parser.java:630) at com.github.jhoenicke.javacup.runtime.LRParser.parse(LRParser.java:419) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:205) ... 41 more [2019-01-07 22:18:18,848 INFO L168 Benchmark]: Toolchain (without parser) took 482066.49 ms. Allocated memory was 1.5 GB in the beginning and 4.2 GB in the end (delta: 2.6 GB). Free memory was 1.5 GB in the beginning and 3.8 GB in the end (delta: -2.4 GB). Peak memory consumption was 260.0 MB. Max. memory is 7.1 GB. [2019-01-07 22:18:18,849 INFO L168 Benchmark]: Boogie PL CUP Parser took 0.23 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2019-01-07 22:18:18,850 INFO L168 Benchmark]: Boogie Procedure Inliner took 53.65 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2019-01-07 22:18:18,850 INFO L168 Benchmark]: Boogie Preprocessor took 23.69 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2019-01-07 22:18:18,850 INFO L168 Benchmark]: RCFGBuilder took 340.71 ms. Allocated memory is still 1.5 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 21.1 MB). Peak memory consumption was 21.1 MB. Max. memory is 7.1 GB. [2019-01-07 22:18:18,851 INFO L168 Benchmark]: TraceAbstraction took 481644.17 ms. Allocated memory was 1.5 GB in the beginning and 4.2 GB in the end (delta: 2.6 GB). Free memory was 1.4 GB in the beginning and 3.8 GB in the end (delta: -2.4 GB). Peak memory consumption was 238.8 MB. Max. memory is 7.1 GB. [2019-01-07 22:18:18,854 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.23 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 53.65 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 23.69 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 340.71 ms. Allocated memory is still 1.5 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 21.1 MB). Peak memory consumption was 21.1 MB. Max. memory is 7.1 GB. * TraceAbstraction took 481644.17 ms. Allocated memory was 1.5 GB in the beginning and 4.2 GB in the end (delta: 2.6 GB). Free memory was 1.4 GB in the beginning and 3.8 GB in the end (delta: -2.4 GB). Peak memory consumption was 238.8 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") : de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:208) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request...