java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml -s ../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf -i ../../../trunk/examples/programs/heapseparator/speedup-poc-dd-3-limited.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.24-f57a05f [2019-01-08 14:33:15,810 INFO L170 SettingsManager]: Resetting all preferences to default values... [2019-01-08 14:33:15,812 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2019-01-08 14:33:15,827 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2019-01-08 14:33:15,887 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf [2019-01-08 14:33:15,906 INFO L110 SettingsManager]: Loading preferences was successful [2019-01-08 14:33:15,907 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2019-01-08 14:33:15,908 INFO L131 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2019-01-08 14:33:15,908 INFO L133 SettingsManager]: * Show backtranslation warnings=false [2019-01-08 14:33:15,909 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-01-08 14:33:15,909 INFO L133 SettingsManager]: * User list type=DISABLED [2019-01-08 14:33:15,909 INFO L133 SettingsManager]: * Inline calls to unimplemented procedures=true [2019-01-08 14:33:15,909 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-01-08 14:33:15,909 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-01-08 14:33:15,910 INFO L133 SettingsManager]: * Underlying domain=OctagonDomain [2019-01-08 14:33:15,910 INFO L133 SettingsManager]: * Abstract domain=ArrayDomain [2019-01-08 14:33:15,911 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-01-08 14:33:15,911 INFO L133 SettingsManager]: * Interval Domain=false [2019-01-08 14:33:15,911 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-01-08 14:33:15,912 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2019-01-08 14:33:15,912 INFO L133 SettingsManager]: * Use SBE=true [2019-01-08 14:33:15,912 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-01-08 14:33:15,912 INFO L133 SettingsManager]: * sizeof long=4 [2019-01-08 14:33:15,912 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2019-01-08 14:33:15,914 INFO L133 SettingsManager]: * sizeof POINTER=4 [2019-01-08 14:33:15,915 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2019-01-08 14:33:15,915 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-01-08 14:33:15,915 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-01-08 14:33:15,915 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-01-08 14:33:15,915 INFO L133 SettingsManager]: * sizeof long double=12 [2019-01-08 14:33:15,916 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2019-01-08 14:33:15,916 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-01-08 14:33:15,916 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-01-08 14:33:15,916 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-01-08 14:33:15,916 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2019-01-08 14:33:15,916 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-08 14:33:15,917 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-01-08 14:33:15,917 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-01-08 14:33:15,917 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-01-08 14:33:15,917 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2019-01-08 14:33:15,917 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-01-08 14:33:15,918 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in [2019-01-08 14:33:15,918 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-01-08 14:33:15,918 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2019-01-08 14:33:15,973 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-01-08 14:33:15,995 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-01-08 14:33:16,002 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-01-08 14:33:16,004 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2019-01-08 14:33:16,005 INFO L276 PluginConnector]: Boogie PL CUP Parser initialized [2019-01-08 14:33:16,005 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-3-limited.bpl [2019-01-08 14:33:16,006 INFO L111 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-3-limited.bpl' [2019-01-08 14:33:16,053 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-01-08 14:33:16,055 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-01-08 14:33:16,055 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-01-08 14:33:16,056 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-01-08 14:33:16,056 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2019-01-08 14:33:16,072 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:16" (1/1) ... [2019-01-08 14:33:16,083 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:16" (1/1) ... [2019-01-08 14:33:16,108 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-01-08 14:33:16,109 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-01-08 14:33:16,109 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-01-08 14:33:16,109 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2019-01-08 14:33:16,121 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:16" (1/1) ... [2019-01-08 14:33:16,121 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:16" (1/1) ... [2019-01-08 14:33:16,122 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:16" (1/1) ... [2019-01-08 14:33:16,123 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:16" (1/1) ... [2019-01-08 14:33:16,126 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:16" (1/1) ... [2019-01-08 14:33:16,129 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:16" (1/1) ... [2019-01-08 14:33:16,131 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:16" (1/1) ... [2019-01-08 14:33:16,132 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-01-08 14:33:16,133 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-01-08 14:33:16,133 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-01-08 14:33:16,133 INFO L276 PluginConnector]: RCFGBuilder initialized [2019-01-08 14:33:16,134 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:16" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-08 14:33:16,199 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-01-08 14:33:16,200 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-01-08 14:33:16,505 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-01-08 14:33:16,505 INFO L286 CfgBuilder]: Removed 9 assue(true) statements. [2019-01-08 14:33:16,507 INFO L202 PluginConnector]: Adding new model speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.01 02:33:16 BoogieIcfgContainer [2019-01-08 14:33:16,507 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-01-08 14:33:16,508 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-01-08 14:33:16,508 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-01-08 14:33:16,511 INFO L276 PluginConnector]: TraceAbstraction initialized [2019-01-08 14:33:16,512 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:16" (1/2) ... [2019-01-08 14:33:16,513 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7746a32 and model type speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.01 02:33:16, skipping insertion in model container [2019-01-08 14:33:16,513 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.01 02:33:16" (2/2) ... [2019-01-08 14:33:16,515 INFO L112 eAbstractionObserver]: Analyzing ICFG speedup-poc-dd-3-limited.bpl [2019-01-08 14:33:16,526 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-01-08 14:33:16,535 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2019-01-08 14:33:16,553 INFO L257 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2019-01-08 14:33:16,589 INFO L382 AbstractCegarLoop]: Interprodecural is true [2019-01-08 14:33:16,590 INFO L383 AbstractCegarLoop]: Hoare is true [2019-01-08 14:33:16,590 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-01-08 14:33:16,590 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-01-08 14:33:16,590 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-01-08 14:33:16,590 INFO L387 AbstractCegarLoop]: Difference is false [2019-01-08 14:33:16,591 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-01-08 14:33:16,591 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-01-08 14:33:16,607 INFO L276 IsEmpty]: Start isEmpty. Operand 9 states. [2019-01-08 14:33:16,613 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3 [2019-01-08 14:33:16,614 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:33:16,615 INFO L402 BasicCegarLoop]: trace histogram [1, 1] [2019-01-08 14:33:16,617 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:33:16,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:33:16,624 INFO L82 PathProgramCache]: Analyzing trace with hash 976, now seen corresponding path program 1 times [2019-01-08 14:33:16,627 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:33:16,684 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:33:16,684 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:33:16,684 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:33:16,685 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:33:16,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:33:16,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:33:16,877 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-08 14:33:16,877 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-08 14:33:16,877 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:33:16,888 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-08 14:33:16,906 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-08 14:33:16,907 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:33:16,910 INFO L87 Difference]: Start difference. First operand 9 states. Second operand 3 states. [2019-01-08 14:33:17,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:33:17,128 INFO L93 Difference]: Finished difference Result 17 states and 21 transitions. [2019-01-08 14:33:17,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-08 14:33:17,130 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 2 [2019-01-08 14:33:17,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:33:17,144 INFO L225 Difference]: With dead ends: 17 [2019-01-08 14:33:17,145 INFO L226 Difference]: Without dead ends: 12 [2019-01-08 14:33:17,148 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:33:17,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states. [2019-01-08 14:33:17,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 8. [2019-01-08 14:33:17,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8 states. [2019-01-08 14:33:17,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 13 transitions. [2019-01-08 14:33:17,186 INFO L78 Accepts]: Start accepts. Automaton has 8 states and 13 transitions. Word has length 2 [2019-01-08 14:33:17,187 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:33:17,187 INFO L480 AbstractCegarLoop]: Abstraction has 8 states and 13 transitions. [2019-01-08 14:33:17,188 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-08 14:33:17,188 INFO L276 IsEmpty]: Start isEmpty. Operand 8 states and 13 transitions. [2019-01-08 14:33:17,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:33:17,188 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:33:17,189 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:33:17,189 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:33:17,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:33:17,189 INFO L82 PathProgramCache]: Analyzing trace with hash 30304, now seen corresponding path program 1 times [2019-01-08 14:33:17,190 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:33:17,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:33:17,191 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:33:17,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:33:17,191 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:33:17,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:33:17,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:33:17,230 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-08 14:33:17,231 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-08 14:33:17,231 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:33:17,233 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-08 14:33:17,233 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-08 14:33:17,234 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:33:17,234 INFO L87 Difference]: Start difference. First operand 8 states and 13 transitions. Second operand 3 states. [2019-01-08 14:33:17,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:33:17,313 INFO L93 Difference]: Finished difference Result 12 states and 16 transitions. [2019-01-08 14:33:17,313 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-08 14:33:17,313 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-01-08 14:33:17,313 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:33:17,314 INFO L225 Difference]: With dead ends: 12 [2019-01-08 14:33:17,314 INFO L226 Difference]: Without dead ends: 11 [2019-01-08 14:33:17,315 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:33:17,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2019-01-08 14:33:17,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 9. [2019-01-08 14:33:17,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9 states. [2019-01-08 14:33:17,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 14 transitions. [2019-01-08 14:33:17,319 INFO L78 Accepts]: Start accepts. Automaton has 9 states and 14 transitions. Word has length 3 [2019-01-08 14:33:17,319 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:33:17,319 INFO L480 AbstractCegarLoop]: Abstraction has 9 states and 14 transitions. [2019-01-08 14:33:17,319 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-08 14:33:17,319 INFO L276 IsEmpty]: Start isEmpty. Operand 9 states and 14 transitions. [2019-01-08 14:33:17,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:33:17,320 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:33:17,320 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:33:17,321 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:33:17,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:33:17,321 INFO L82 PathProgramCache]: Analyzing trace with hash 29992, now seen corresponding path program 1 times [2019-01-08 14:33:17,321 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:33:17,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:33:17,322 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:33:17,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:33:17,323 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:33:17,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:33:17,412 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:33:17,412 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:33:17,412 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:33:17,413 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:33:17,415 INFO L207 CegarAbsIntRunner]: [0], [6], [15] [2019-01-08 14:33:17,477 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:33:17,478 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:33:25,490 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:33:25,491 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:33:25,496 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:33:25,496 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:33:25,815 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 71.43% of their original sizes. [2019-01-08 14:33:25,816 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:33:27,967 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_69 Int) (v_idx_67 Int) (v_idx_68 Int) (v_idx_72 Int) (v_idx_73 Int) (v_idx_70 Int) (v_idx_71 Int)) (exists ((v_v_1290_1 Int) (v_b_102_1 Int) (v_v_1288_1 Int) (v_b_104_1 Int) (v_b_103_1 Int) (v_v_1284_1 Int) (v_v_1285_1 Int) (v_b_105_1 Int) (v_v_1286_1 Int)) (let ((.cse1 (+ v_b_104_1 1)) (.cse2 (+ v_b_102_1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= (select |c_#memory_int| v_idx_68) v_v_1285_1) (<= .cse0 v_idx_68) (< v_idx_68 c_ULTIMATE.start_main_p1)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_105_1) (<= v_b_105_1 .cse1) (or (<= c_ULTIMATE.start_main_p1 v_idx_67) (= (select |c_#memory_int| v_idx_67) v_v_1284_1)) (or (<= v_b_104_1 v_idx_71) (= (select |c_#memory_int| v_idx_71) v_v_1288_1) (< v_idx_71 v_b_103_1)) (or (< v_idx_70 v_b_102_1) (<= v_b_103_1 v_idx_70) (= 0 (select |c_#memory_int| v_idx_70))) (<= v_b_103_1 v_b_104_1) (<= (+ v_b_102_1 2) v_b_105_1) (or (= (select |c_#memory_int| v_idx_73) v_v_1290_1) (< v_idx_73 v_b_105_1)) (<= .cse2 v_b_103_1) (<= 0 v_v_1285_1) (<= v_b_103_1 .cse2) (<= .cse1 v_b_105_1) (<= .cse3 v_b_104_1) (<= .cse2 v_b_104_1) (<= 0 (* 2 v_v_1285_1)) (<= .cse0 v_b_102_1) (or (<= v_b_105_1 v_idx_72) (< v_idx_72 v_b_104_1) (= 0 (select |c_#memory_int| v_idx_72))) (<= .cse3 v_b_103_1) (<= (+ v_b_103_1 1) v_b_105_1) (or (= (select |c_#memory_int| v_idx_69) v_v_1286_1) (< v_idx_69 .cse0) (<= v_b_102_1 v_idx_69)))))) is different from false [2019-01-08 14:33:30,526 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_78 Int) (v_idx_79 Int) (v_idx_76 Int) (v_idx_77 Int) (v_idx_74 Int) (v_idx_75 Int) (v_idx_80 Int)) (exists ((v_v_1290_1 Int) (v_b_102_1 Int) (v_v_1288_1 Int) (v_b_104_1 Int) (v_b_103_1 Int) (v_v_1284_1 Int) (v_v_1285_1 Int) (v_b_105_1 Int) (v_v_1286_1 Int)) (let ((.cse0 (+ v_b_104_1 1)) (.cse1 (+ v_b_102_1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 3) v_b_105_1) (<= v_b_105_1 .cse0) (or (< v_idx_79 v_b_104_1) (= (select |c_#memory_int| v_idx_79) 0) (<= v_b_105_1 v_idx_79)) (or (<= v_b_104_1 v_idx_78) (< v_idx_78 v_b_103_1) (= (select |c_#memory_int| v_idx_78) v_v_1288_1)) (<= v_b_103_1 v_b_104_1) (<= (+ v_b_102_1 2) v_b_105_1) (<= .cse1 v_b_103_1) (<= 0 v_v_1285_1) (or (< v_idx_77 v_b_102_1) (= (select |c_#memory_int| v_idx_77) 0) (<= v_b_103_1 v_idx_77)) (or (= (select |c_#memory_int| v_idx_75) v_v_1285_1) (< v_idx_75 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_75)) (<= v_b_103_1 .cse1) (<= .cse0 v_b_105_1) (<= .cse3 v_b_104_1) (<= .cse1 v_b_104_1) (or (= (select |c_#memory_int| v_idx_74) v_v_1284_1) (<= c_ULTIMATE.start_main_p1 v_idx_74)) (<= 0 (* 2 v_v_1285_1)) (<= .cse2 v_b_102_1) (<= .cse3 v_b_103_1) (<= (+ v_b_103_1 1) v_b_105_1) (or (< v_idx_80 v_b_105_1) (= (select |c_#memory_int| v_idx_80) v_v_1290_1)) (or (<= v_b_102_1 v_idx_76) (< v_idx_76 .cse2) (= (select |c_#memory_int| v_idx_76) v_v_1286_1)))))) is different from false [2019-01-08 14:33:30,649 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:33:30,649 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:33:30,650 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:33:30,650 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:33:30,650 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:33:30,651 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:33:30,651 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:33:30,651 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-08 14:33:30,652 INFO L87 Difference]: Start difference. First operand 9 states and 14 transitions. Second operand 4 states. [2019-01-08 14:33:34,876 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_78 Int) (v_idx_79 Int) (v_idx_76 Int) (v_idx_77 Int) (v_idx_74 Int) (v_idx_75 Int) (v_idx_80 Int)) (exists ((v_v_1290_1 Int) (v_b_102_1 Int) (v_v_1288_1 Int) (v_b_104_1 Int) (v_b_103_1 Int) (v_v_1284_1 Int) (v_v_1285_1 Int) (v_b_105_1 Int) (v_v_1286_1 Int)) (let ((.cse0 (+ v_b_104_1 1)) (.cse1 (+ v_b_102_1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 3) v_b_105_1) (<= v_b_105_1 .cse0) (or (< v_idx_79 v_b_104_1) (= (select |c_#memory_int| v_idx_79) 0) (<= v_b_105_1 v_idx_79)) (or (<= v_b_104_1 v_idx_78) (< v_idx_78 v_b_103_1) (= (select |c_#memory_int| v_idx_78) v_v_1288_1)) (<= v_b_103_1 v_b_104_1) (<= (+ v_b_102_1 2) v_b_105_1) (<= .cse1 v_b_103_1) (<= 0 v_v_1285_1) (or (< v_idx_77 v_b_102_1) (= (select |c_#memory_int| v_idx_77) 0) (<= v_b_103_1 v_idx_77)) (or (= (select |c_#memory_int| v_idx_75) v_v_1285_1) (< v_idx_75 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_75)) (<= v_b_103_1 .cse1) (<= .cse0 v_b_105_1) (<= .cse3 v_b_104_1) (<= .cse1 v_b_104_1) (or (= (select |c_#memory_int| v_idx_74) v_v_1284_1) (<= c_ULTIMATE.start_main_p1 v_idx_74)) (<= 0 (* 2 v_v_1285_1)) (<= .cse2 v_b_102_1) (<= .cse3 v_b_103_1) (<= (+ v_b_103_1 1) v_b_105_1) (or (< v_idx_80 v_b_105_1) (= (select |c_#memory_int| v_idx_80) v_v_1290_1)) (or (<= v_b_102_1 v_idx_76) (< v_idx_76 .cse2) (= (select |c_#memory_int| v_idx_76) v_v_1286_1)))))) (forall ((v_idx_69 Int) (v_idx_67 Int) (v_idx_68 Int) (v_idx_72 Int) (v_idx_73 Int) (v_idx_70 Int) (v_idx_71 Int)) (exists ((v_v_1290_1 Int) (v_b_102_1 Int) (v_v_1288_1 Int) (v_b_104_1 Int) (v_b_103_1 Int) (v_v_1284_1 Int) (v_v_1285_1 Int) (v_b_105_1 Int) (v_v_1286_1 Int)) (let ((.cse5 (+ v_b_104_1 1)) (.cse6 (+ v_b_102_1 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= (select |c_#memory_int| v_idx_68) v_v_1285_1) (<= .cse4 v_idx_68) (< v_idx_68 c_ULTIMATE.start_main_p1)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_105_1) (<= v_b_105_1 .cse5) (or (<= c_ULTIMATE.start_main_p1 v_idx_67) (= (select |c_#memory_int| v_idx_67) v_v_1284_1)) (or (<= v_b_104_1 v_idx_71) (= (select |c_#memory_int| v_idx_71) v_v_1288_1) (< v_idx_71 v_b_103_1)) (or (< v_idx_70 v_b_102_1) (<= v_b_103_1 v_idx_70) (= 0 (select |c_#memory_int| v_idx_70))) (<= v_b_103_1 v_b_104_1) (<= (+ v_b_102_1 2) v_b_105_1) (or (= (select |c_#memory_int| v_idx_73) v_v_1290_1) (< v_idx_73 v_b_105_1)) (<= .cse6 v_b_103_1) (<= 0 v_v_1285_1) (<= v_b_103_1 .cse6) (<= .cse5 v_b_105_1) (<= .cse7 v_b_104_1) (<= .cse6 v_b_104_1) (<= 0 (* 2 v_v_1285_1)) (<= .cse4 v_b_102_1) (or (<= v_b_105_1 v_idx_72) (< v_idx_72 v_b_104_1) (= 0 (select |c_#memory_int| v_idx_72))) (<= .cse7 v_b_103_1) (<= (+ v_b_103_1 1) v_b_105_1) (or (= (select |c_#memory_int| v_idx_69) v_v_1286_1) (< v_idx_69 .cse4) (<= v_b_102_1 v_idx_69))))))) is different from false [2019-01-08 14:34:03,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:34:03,170 INFO L93 Difference]: Finished difference Result 11 states and 19 transitions. [2019-01-08 14:34:03,170 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-08 14:34:03,171 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-08 14:34:03,171 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:34:03,171 INFO L225 Difference]: With dead ends: 11 [2019-01-08 14:34:03,171 INFO L226 Difference]: Without dead ends: 10 [2019-01-08 14:34:03,172 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 9.0s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:34:03,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states. [2019-01-08 14:34:03,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2019-01-08 14:34:03,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2019-01-08 14:34:03,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 18 transitions. [2019-01-08 14:34:03,177 INFO L78 Accepts]: Start accepts. Automaton has 10 states and 18 transitions. Word has length 3 [2019-01-08 14:34:03,177 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:34:03,178 INFO L480 AbstractCegarLoop]: Abstraction has 10 states and 18 transitions. [2019-01-08 14:34:03,178 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:34:03,178 INFO L276 IsEmpty]: Start isEmpty. Operand 10 states and 18 transitions. [2019-01-08 14:34:03,178 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:34:03,178 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:34:03,179 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:34:03,179 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:34:03,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:34:03,180 INFO L82 PathProgramCache]: Analyzing trace with hash 30116, now seen corresponding path program 1 times [2019-01-08 14:34:03,180 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:34:03,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:34:03,181 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:34:03,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:34:03,181 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:34:03,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:34:03,370 WARN L181 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 20 DAG size of output: 13 [2019-01-08 14:34:03,379 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:34:03,380 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:34:03,380 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:34:03,380 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:34:03,380 INFO L207 CegarAbsIntRunner]: [0], [10], [15] [2019-01-08 14:34:03,383 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:34:03,383 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:34:07,388 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:34:07,388 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:34:07,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:34:07,389 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:34:07,598 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 64.29% of their original sizes. [2019-01-08 14:34:07,598 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:34:10,092 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_148 Int) (v_idx_149 Int) (v_idx_147 Int) (v_idx_151 Int) (v_idx_152 Int) (v_idx_150 Int) (v_idx_153 Int)) (exists ((v_v_1016_2 Int) (v_v_1018_2 Int) (v_v_1017_2 Int) (v_v_1014_2 Int) (v_b_105_2 Int) (v_b_104_2 Int) (v_v_1020_2 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_104_2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_105_2 .cse0) (or (= (select |c_#memory_int| v_idx_151) v_v_1018_2) (<= v_b_104_2 v_idx_151) (< v_idx_151 .cse1)) (<= (* 2 v_v_1017_2) 0) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_105_2) (<= .cse1 v_b_104_2) (or (= (select |c_#memory_int| v_idx_149) v_v_1016_2) (<= c_ULTIMATE.start_main_p2 v_idx_149) (< v_idx_149 .cse2)) (or (= (select |c_#memory_int| v_idx_153) v_v_1020_2) (< v_idx_153 v_b_105_2)) (or (< v_idx_150 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_150) v_v_1017_2) (<= .cse1 v_idx_150)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_105_2) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_104_2) (<= .cse0 v_b_105_2) (or (= (select |c_#memory_int| v_idx_147) v_v_1014_2) (<= c_ULTIMATE.start_main_p1 v_idx_147)) (<= .cse2 c_ULTIMATE.start_main_p2) (<= v_v_1017_2 0) (or (= (select |c_#memory_int| v_idx_148) 0) (<= .cse2 v_idx_148) (< v_idx_148 c_ULTIMATE.start_main_p1)) (or (<= v_b_105_2 v_idx_152) (= (select |c_#memory_int| v_idx_152) 0) (< v_idx_152 v_b_104_2)))))) is different from false [2019-01-08 14:34:12,455 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_159 Int) (v_idx_157 Int) (v_idx_158 Int) (v_idx_160 Int) (v_idx_155 Int) (v_idx_156 Int) (v_idx_154 Int)) (exists ((v_v_1016_2 Int) (v_v_1018_2 Int) (v_v_1017_2 Int) (v_v_1014_2 Int) (v_b_102_2 Int) (v_b_103_2 Int) (v_b_105_2 Int) (v_b_104_2 Int) (v_v_1020_2 Int)) (let ((.cse1 (+ v_b_102_2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse0 (+ v_b_104_2 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_105_2 .cse0) (<= (+ v_b_102_2 2) v_b_105_2) (<= .cse1 v_b_104_2) (<= (* 2 v_v_1017_2) 0) (or (<= v_b_105_2 v_idx_159) (= (select |c_#memory_int| v_idx_159) 0) (< v_idx_159 v_b_104_2)) (or (<= v_b_104_2 v_idx_158) (< v_idx_158 v_b_103_2) (= (select |c_#memory_int| v_idx_158) v_v_1018_2)) (<= .cse2 v_b_103_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_154) (= (select |c_#memory_int| v_idx_154) v_v_1014_2)) (<= v_b_103_2 v_b_104_2) (<= .cse1 v_b_103_2) (or (= (select |c_#memory_int| v_idx_157) v_v_1017_2) (<= v_b_103_2 v_idx_157) (< v_idx_157 v_b_102_2)) (or (< v_idx_155 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_155)) (<= .cse3 v_idx_155)) (<= v_b_103_2 .cse1) (or (< v_idx_160 v_b_105_2) (= (select |c_#memory_int| v_idx_160) v_v_1020_2)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_105_2) (<= .cse2 v_b_104_2) (<= .cse3 v_b_102_2) (<= (+ v_b_103_2 1) v_b_105_2) (<= .cse0 v_b_105_2) (<= v_v_1017_2 0) (or (<= v_b_102_2 v_idx_156) (< v_idx_156 .cse3) (= (select |c_#memory_int| v_idx_156) v_v_1016_2)))))) is different from false [2019-01-08 14:34:12,511 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:34:12,511 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:34:12,511 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:34:12,511 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:34:12,511 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:34:12,512 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:34:12,512 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:34:12,512 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-08 14:34:12,512 INFO L87 Difference]: Start difference. First operand 10 states and 18 transitions. Second operand 4 states. [2019-01-08 14:34:14,968 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_159 Int) (v_idx_157 Int) (v_idx_158 Int) (v_idx_160 Int) (v_idx_155 Int) (v_idx_156 Int) (v_idx_154 Int)) (exists ((v_v_1016_2 Int) (v_v_1018_2 Int) (v_v_1017_2 Int) (v_v_1014_2 Int) (v_b_102_2 Int) (v_b_103_2 Int) (v_b_105_2 Int) (v_b_104_2 Int) (v_v_1020_2 Int)) (let ((.cse1 (+ v_b_102_2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse0 (+ v_b_104_2 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_105_2 .cse0) (<= (+ v_b_102_2 2) v_b_105_2) (<= .cse1 v_b_104_2) (<= (* 2 v_v_1017_2) 0) (or (<= v_b_105_2 v_idx_159) (= (select |c_#memory_int| v_idx_159) 0) (< v_idx_159 v_b_104_2)) (or (<= v_b_104_2 v_idx_158) (< v_idx_158 v_b_103_2) (= (select |c_#memory_int| v_idx_158) v_v_1018_2)) (<= .cse2 v_b_103_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_154) (= (select |c_#memory_int| v_idx_154) v_v_1014_2)) (<= v_b_103_2 v_b_104_2) (<= .cse1 v_b_103_2) (or (= (select |c_#memory_int| v_idx_157) v_v_1017_2) (<= v_b_103_2 v_idx_157) (< v_idx_157 v_b_102_2)) (or (< v_idx_155 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_155)) (<= .cse3 v_idx_155)) (<= v_b_103_2 .cse1) (or (< v_idx_160 v_b_105_2) (= (select |c_#memory_int| v_idx_160) v_v_1020_2)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_105_2) (<= .cse2 v_b_104_2) (<= .cse3 v_b_102_2) (<= (+ v_b_103_2 1) v_b_105_2) (<= .cse0 v_b_105_2) (<= v_v_1017_2 0) (or (<= v_b_102_2 v_idx_156) (< v_idx_156 .cse3) (= (select |c_#memory_int| v_idx_156) v_v_1016_2)))))) (forall ((v_idx_148 Int) (v_idx_149 Int) (v_idx_147 Int) (v_idx_151 Int) (v_idx_152 Int) (v_idx_150 Int) (v_idx_153 Int)) (exists ((v_v_1016_2 Int) (v_v_1018_2 Int) (v_v_1017_2 Int) (v_v_1014_2 Int) (v_b_105_2 Int) (v_b_104_2 Int) (v_v_1020_2 Int)) (let ((.cse5 (+ c_ULTIMATE.start_main_p2 1)) (.cse4 (+ v_b_104_2 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_105_2 .cse4) (or (= (select |c_#memory_int| v_idx_151) v_v_1018_2) (<= v_b_104_2 v_idx_151) (< v_idx_151 .cse5)) (<= (* 2 v_v_1017_2) 0) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_105_2) (<= .cse5 v_b_104_2) (or (= (select |c_#memory_int| v_idx_149) v_v_1016_2) (<= c_ULTIMATE.start_main_p2 v_idx_149) (< v_idx_149 .cse6)) (or (= (select |c_#memory_int| v_idx_153) v_v_1020_2) (< v_idx_153 v_b_105_2)) (or (< v_idx_150 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_150) v_v_1017_2) (<= .cse5 v_idx_150)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_105_2) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_104_2) (<= .cse4 v_b_105_2) (or (= (select |c_#memory_int| v_idx_147) v_v_1014_2) (<= c_ULTIMATE.start_main_p1 v_idx_147)) (<= .cse6 c_ULTIMATE.start_main_p2) (<= v_v_1017_2 0) (or (= (select |c_#memory_int| v_idx_148) 0) (<= .cse6 v_idx_148) (< v_idx_148 c_ULTIMATE.start_main_p1)) (or (<= v_b_105_2 v_idx_152) (= (select |c_#memory_int| v_idx_152) 0) (< v_idx_152 v_b_104_2))))))) is different from false [2019-01-08 14:34:27,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:34:27,344 INFO L93 Difference]: Finished difference Result 12 states and 23 transitions. [2019-01-08 14:34:27,344 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-08 14:34:27,344 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-08 14:34:27,344 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:34:27,345 INFO L225 Difference]: With dead ends: 12 [2019-01-08 14:34:27,345 INFO L226 Difference]: Without dead ends: 11 [2019-01-08 14:34:27,345 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.4s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:34:27,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2019-01-08 14:34:27,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 10. [2019-01-08 14:34:27,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2019-01-08 14:34:27,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 18 transitions. [2019-01-08 14:34:27,352 INFO L78 Accepts]: Start accepts. Automaton has 10 states and 18 transitions. Word has length 3 [2019-01-08 14:34:27,352 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:34:27,352 INFO L480 AbstractCegarLoop]: Abstraction has 10 states and 18 transitions. [2019-01-08 14:34:27,352 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:34:27,352 INFO L276 IsEmpty]: Start isEmpty. Operand 10 states and 18 transitions. [2019-01-08 14:34:27,353 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:34:27,353 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:34:27,353 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:34:27,353 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:34:27,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:34:27,354 INFO L82 PathProgramCache]: Analyzing trace with hash 30178, now seen corresponding path program 1 times [2019-01-08 14:34:27,354 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:34:27,355 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:34:27,355 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:34:27,355 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:34:27,355 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:34:27,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:34:27,421 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:34:27,421 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:34:27,422 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:34:27,422 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:34:27,422 INFO L207 CegarAbsIntRunner]: [0], [12], [15] [2019-01-08 14:34:27,423 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:34:27,423 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:34:31,113 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:34:31,113 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:34:31,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:34:31,114 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:34:31,322 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 64.29% of their original sizes. [2019-01-08 14:34:31,322 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:34:33,805 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_229 Int) (v_idx_227 Int) (v_idx_228 Int) (v_idx_232 Int) (v_idx_233 Int) (v_idx_230 Int) (v_idx_231 Int)) (exists ((v_v_1149_3 Int) (v_v_1153_3 Int) (v_v_1154_3 Int) (v_v_1155_3 Int) (v_b_113_3 Int) (v_b_112_3 Int) (v_v_1151_3 Int)) (let ((.cse1 (+ v_b_112_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse0 c_ULTIMATE.start_main_p3) (<= v_b_113_3 .cse1) (<= 0 v_v_1154_3) (or (< v_idx_228 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_228)) (<= .cse2 v_idx_228)) (<= v_b_113_3 c_ULTIMATE.start_main_p3) (<= .cse1 c_ULTIMATE.start_main_p3) (<= .cse1 v_b_113_3) (<= .cse0 v_b_113_3) (or (< v_idx_229 .cse2) (= (select |c_#memory_int| v_idx_229) v_v_1151_3) (<= v_b_112_3 v_idx_229)) (<= .cse2 v_b_112_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_227) (= (select |c_#memory_int| v_idx_227) v_v_1149_3)) (or (< v_idx_233 .cse3) (= (select |c_#memory_int| v_idx_233) v_v_1155_3)) (or (= (select |c_#memory_int| v_idx_232) v_v_1154_3) (< v_idx_232 c_ULTIMATE.start_main_p3) (<= .cse3 v_idx_232)) (or (= 0 (select |c_#memory_int| v_idx_230)) (<= v_b_113_3 v_idx_230) (< v_idx_230 v_b_112_3)) (or (< v_idx_231 v_b_113_3) (= (select |c_#memory_int| v_idx_231) v_v_1153_3) (<= c_ULTIMATE.start_main_p3 v_idx_231)) (<= 0 (* 2 v_v_1154_3)))))) is different from false [2019-01-08 14:34:36,140 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_236 Int) (v_idx_237 Int) (v_idx_234 Int) (v_idx_235 Int) (v_idx_238 Int) (v_idx_239 Int) (v_idx_240 Int)) (exists ((v_v_1149_3 Int) (v_v_1153_3 Int) (v_v_1154_3 Int) (v_v_1155_3 Int) (v_b_113_3 Int) (v_b_112_3 Int) (v_v_1151_3 Int) (v_b_115_3 Int) (v_b_114_3 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ v_b_114_3 1)) (.cse0 (+ v_b_112_3 1))) (and (<= v_b_113_3 .cse0) (<= 0 v_v_1154_3) (or (= 0 (select |c_#memory_int| v_idx_235)) (<= .cse1 v_idx_235) (< v_idx_235 c_ULTIMATE.start_main_p1)) (or (< v_idx_236 .cse1) (= (select |c_#memory_int| v_idx_236) v_v_1151_3) (<= v_b_112_3 v_idx_236)) (<= .cse0 v_b_113_3) (<= .cse2 v_b_113_3) (<= v_b_115_3 .cse3) (<= .cse2 v_b_114_3) (<= .cse1 v_b_112_3) (or (< v_idx_240 v_b_115_3) (= (select |c_#memory_int| v_idx_240) v_v_1155_3)) (<= v_b_113_3 v_b_114_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_3) (<= (+ v_b_112_3 2) v_b_115_3) (<= .cse3 v_b_115_3) (or (<= v_b_113_3 v_idx_237) (< v_idx_237 v_b_112_3) (= 0 (select |c_#memory_int| v_idx_237))) (<= .cse0 v_b_114_3) (<= (+ v_b_113_3 1) v_b_115_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_234) (= (select |c_#memory_int| v_idx_234) v_v_1149_3)) (or (<= v_b_115_3 v_idx_239) (= (select |c_#memory_int| v_idx_239) v_v_1154_3) (< v_idx_239 v_b_114_3)) (or (< v_idx_238 v_b_113_3) (<= v_b_114_3 v_idx_238) (= (select |c_#memory_int| v_idx_238) v_v_1153_3)) (<= 0 (* 2 v_v_1154_3)))))) is different from false [2019-01-08 14:34:36,351 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:34:36,351 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:34:36,351 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:34:36,351 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:34:36,351 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:34:36,352 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:34:36,352 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:34:36,352 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-08 14:34:36,352 INFO L87 Difference]: Start difference. First operand 10 states and 18 transitions. Second operand 4 states. [2019-01-08 14:34:38,870 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_236 Int) (v_idx_237 Int) (v_idx_234 Int) (v_idx_235 Int) (v_idx_238 Int) (v_idx_239 Int) (v_idx_240 Int)) (exists ((v_v_1149_3 Int) (v_v_1153_3 Int) (v_v_1154_3 Int) (v_v_1155_3 Int) (v_b_113_3 Int) (v_b_112_3 Int) (v_v_1151_3 Int) (v_b_115_3 Int) (v_b_114_3 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ v_b_114_3 1)) (.cse0 (+ v_b_112_3 1))) (and (<= v_b_113_3 .cse0) (<= 0 v_v_1154_3) (or (= 0 (select |c_#memory_int| v_idx_235)) (<= .cse1 v_idx_235) (< v_idx_235 c_ULTIMATE.start_main_p1)) (or (< v_idx_236 .cse1) (= (select |c_#memory_int| v_idx_236) v_v_1151_3) (<= v_b_112_3 v_idx_236)) (<= .cse0 v_b_113_3) (<= .cse2 v_b_113_3) (<= v_b_115_3 .cse3) (<= .cse2 v_b_114_3) (<= .cse1 v_b_112_3) (or (< v_idx_240 v_b_115_3) (= (select |c_#memory_int| v_idx_240) v_v_1155_3)) (<= v_b_113_3 v_b_114_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_3) (<= (+ v_b_112_3 2) v_b_115_3) (<= .cse3 v_b_115_3) (or (<= v_b_113_3 v_idx_237) (< v_idx_237 v_b_112_3) (= 0 (select |c_#memory_int| v_idx_237))) (<= .cse0 v_b_114_3) (<= (+ v_b_113_3 1) v_b_115_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_234) (= (select |c_#memory_int| v_idx_234) v_v_1149_3)) (or (<= v_b_115_3 v_idx_239) (= (select |c_#memory_int| v_idx_239) v_v_1154_3) (< v_idx_239 v_b_114_3)) (or (< v_idx_238 v_b_113_3) (<= v_b_114_3 v_idx_238) (= (select |c_#memory_int| v_idx_238) v_v_1153_3)) (<= 0 (* 2 v_v_1154_3)))))) (forall ((v_idx_229 Int) (v_idx_227 Int) (v_idx_228 Int) (v_idx_232 Int) (v_idx_233 Int) (v_idx_230 Int) (v_idx_231 Int)) (exists ((v_v_1149_3 Int) (v_v_1153_3 Int) (v_v_1154_3 Int) (v_v_1155_3 Int) (v_b_113_3 Int) (v_b_112_3 Int) (v_v_1151_3 Int)) (let ((.cse5 (+ v_b_112_3 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 2)) (.cse6 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse4 c_ULTIMATE.start_main_p3) (<= v_b_113_3 .cse5) (<= 0 v_v_1154_3) (or (< v_idx_228 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_228)) (<= .cse6 v_idx_228)) (<= v_b_113_3 c_ULTIMATE.start_main_p3) (<= .cse5 c_ULTIMATE.start_main_p3) (<= .cse5 v_b_113_3) (<= .cse4 v_b_113_3) (or (< v_idx_229 .cse6) (= (select |c_#memory_int| v_idx_229) v_v_1151_3) (<= v_b_112_3 v_idx_229)) (<= .cse6 v_b_112_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_227) (= (select |c_#memory_int| v_idx_227) v_v_1149_3)) (or (< v_idx_233 .cse7) (= (select |c_#memory_int| v_idx_233) v_v_1155_3)) (or (= (select |c_#memory_int| v_idx_232) v_v_1154_3) (< v_idx_232 c_ULTIMATE.start_main_p3) (<= .cse7 v_idx_232)) (or (= 0 (select |c_#memory_int| v_idx_230)) (<= v_b_113_3 v_idx_230) (< v_idx_230 v_b_112_3)) (or (< v_idx_231 v_b_113_3) (= (select |c_#memory_int| v_idx_231) v_v_1153_3) (<= c_ULTIMATE.start_main_p3 v_idx_231)) (<= 0 (* 2 v_v_1154_3))))))) is different from false [2019-01-08 14:34:49,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:34:49,191 INFO L93 Difference]: Finished difference Result 12 states and 23 transitions. [2019-01-08 14:34:49,191 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-08 14:34:49,191 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-08 14:34:49,191 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:34:49,192 INFO L225 Difference]: With dead ends: 12 [2019-01-08 14:34:49,192 INFO L226 Difference]: Without dead ends: 11 [2019-01-08 14:34:49,193 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.6s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:34:49,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2019-01-08 14:34:49,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 10. [2019-01-08 14:34:49,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2019-01-08 14:34:49,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 18 transitions. [2019-01-08 14:34:49,200 INFO L78 Accepts]: Start accepts. Automaton has 10 states and 18 transitions. Word has length 3 [2019-01-08 14:34:49,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:34:49,200 INFO L480 AbstractCegarLoop]: Abstraction has 10 states and 18 transitions. [2019-01-08 14:34:49,200 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:34:49,200 INFO L276 IsEmpty]: Start isEmpty. Operand 10 states and 18 transitions. [2019-01-08 14:34:49,201 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-08 14:34:49,201 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:34:49,201 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-08 14:34:49,201 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:34:49,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:34:49,201 INFO L82 PathProgramCache]: Analyzing trace with hash 939474, now seen corresponding path program 1 times [2019-01-08 14:34:49,202 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:34:49,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:34:49,202 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:34:49,203 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:34:49,203 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:34:49,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:34:49,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:34:49,267 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-08 14:34:49,267 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-08 14:34:49,267 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:34:49,267 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-08 14:34:49,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-08 14:34:49,268 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:34:49,268 INFO L87 Difference]: Start difference. First operand 10 states and 18 transitions. Second operand 3 states. [2019-01-08 14:34:49,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:34:49,310 INFO L93 Difference]: Finished difference Result 12 states and 19 transitions. [2019-01-08 14:34:49,311 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-08 14:34:49,311 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 4 [2019-01-08 14:34:49,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:34:49,311 INFO L225 Difference]: With dead ends: 12 [2019-01-08 14:34:49,312 INFO L226 Difference]: Without dead ends: 9 [2019-01-08 14:34:49,313 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:34:49,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states. [2019-01-08 14:34:49,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2019-01-08 14:34:49,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9 states. [2019-01-08 14:34:49,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 16 transitions. [2019-01-08 14:34:49,320 INFO L78 Accepts]: Start accepts. Automaton has 9 states and 16 transitions. Word has length 4 [2019-01-08 14:34:49,320 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:34:49,320 INFO L480 AbstractCegarLoop]: Abstraction has 9 states and 16 transitions. [2019-01-08 14:34:49,321 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-08 14:34:49,321 INFO L276 IsEmpty]: Start isEmpty. Operand 9 states and 16 transitions. [2019-01-08 14:34:49,321 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-08 14:34:49,321 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:34:49,321 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-08 14:34:49,322 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:34:49,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:34:49,322 INFO L82 PathProgramCache]: Analyzing trace with hash 929800, now seen corresponding path program 1 times [2019-01-08 14:34:49,322 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:34:49,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:34:49,323 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:34:49,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:34:49,324 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:34:49,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:34:49,544 WARN L181 SmtUtils]: Spent 171.00 ms on a formula simplification. DAG size of input: 19 DAG size of output: 13 [2019-01-08 14:34:49,555 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:34:49,556 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:34:49,556 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:34:49,556 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-08 14:34:49,556 INFO L207 CegarAbsIntRunner]: [0], [6], [16], [17] [2019-01-08 14:34:49,557 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:34:49,557 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:34:55,619 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:34:55,620 INFO L272 AbstractInterpreter]: Visited 4 different actions 16 times. Merged at 2 different actions 8 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:34:55,620 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:34:55,620 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:34:55,900 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 61.9% of their original sizes. [2019-01-08 14:34:55,900 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:34:58,359 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_346 Int) (v_idx_344 Int) (v_idx_345 Int) (v_idx_342 Int) (v_idx_343 Int) (v_idx_340 Int) (v_idx_341 Int)) (exists ((v_v_1673_3 Int) (v_b_131_4 Int) (v_b_130_4 Int) (v_v_1677_4 Int) (v_v_1679_3 Int) (v_v_1674_4 Int) (v_v_1675_4 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_130_4 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_342 .cse0) (= (select |c_#memory_int| v_idx_342) v_v_1675_4) (<= c_ULTIMATE.start_main_p2 v_idx_342)) (<= 0 v_v_1674_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_4) (or (= (select |c_#memory_int| v_idx_343) 0) (<= .cse1 v_idx_343) (< v_idx_343 c_ULTIMATE.start_main_p2)) (or (< v_idx_344 .cse1) (= (select |c_#memory_int| v_idx_344) v_v_1677_4) (<= v_b_130_4 v_idx_344)) (<= .cse2 v_b_131_4) (or (< v_idx_345 v_b_130_4) (= 0 (select |c_#memory_int| v_idx_345)) (<= v_b_131_4 v_idx_345)) (or (< v_idx_341 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_341) (= (select |c_#memory_int| v_idx_341) v_v_1674_4)) (<= .cse1 v_b_130_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_340) (= (select |c_#memory_int| v_idx_340) v_v_1673_3)) (<= v_b_131_4 .cse2) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_4) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_4) (<= .cse0 c_ULTIMATE.start_main_p2) (or (< v_idx_346 v_b_131_4) (= (select |c_#memory_int| v_idx_346) v_v_1679_3)) (<= 0 (* 2 v_v_1674_4)))))) is different from false [2019-01-08 14:35:00,685 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_347 Int) (v_idx_348 Int) (v_idx_349 Int) (v_idx_350 Int) (v_idx_353 Int) (v_idx_351 Int) (v_idx_352 Int)) (exists ((v_v_1673_3 Int) (v_b_131_4 Int) (v_b_130_4 Int) (v_v_1677_4 Int) (v_v_1679_3 Int) (v_v_1674_4 Int) (v_v_1675_4 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_130_4 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= 0 v_v_1674_4) (or (= 0 (select |c_#memory_int| v_idx_352)) (< v_idx_352 v_b_130_4) (<= v_b_131_4 v_idx_352)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_4) (or (= 0 (select |c_#memory_int| v_idx_350)) (<= .cse0 v_idx_350) (< v_idx_350 c_ULTIMATE.start_main_p2)) (<= .cse1 v_b_131_4) (or (= (select |c_#memory_int| v_idx_353) v_v_1679_3) (< v_idx_353 v_b_131_4)) (<= .cse0 v_b_130_4) (or (< v_idx_348 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_348) (= (select |c_#memory_int| v_idx_348) v_v_1674_4)) (or (= (select |c_#memory_int| v_idx_351) v_v_1677_4) (< v_idx_351 .cse0) (<= v_b_130_4 v_idx_351)) (or (= (select |c_#memory_int| v_idx_349) v_v_1675_4) (<= c_ULTIMATE.start_main_p2 v_idx_349) (< v_idx_349 .cse2)) (<= v_b_131_4 .cse1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_4) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_4) (<= .cse2 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_347) v_v_1673_3) (<= c_ULTIMATE.start_main_p1 v_idx_347)) (<= 0 (* 2 v_v_1674_4)))))) is different from false [2019-01-08 14:35:02,820 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_357 Int) (v_idx_358 Int) (v_idx_355 Int) (v_idx_356 Int) (v_idx_359 Int) (v_idx_360 Int) (v_idx_354 Int)) (exists ((v_v_1673_3 Int) (v_b_131_4 Int) (v_b_130_4 Int) (v_v_1677_4 Int) (v_b_127_4 Int) (v_v_1679_3 Int) (v_v_1971_2 Int) (v_v_1675_4 Int) (v_b_138_4 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_130_4 1)) (.cse0 (+ v_b_138_4 1))) (and (or (<= v_b_131_4 v_idx_359) (= 0 (select |c_#memory_int| v_idx_359)) (< v_idx_359 v_b_130_4)) (or (< v_idx_360 v_b_131_4) (= (select |c_#memory_int| v_idx_360) v_v_1679_3)) (<= .cse0 v_b_127_4) (or (= (select |c_#memory_int| v_idx_354) v_v_1673_3) (<= v_b_138_4 v_idx_354)) (<= .cse1 v_b_131_4) (or (<= v_b_130_4 v_idx_358) (< v_idx_358 .cse2) (= (select |c_#memory_int| v_idx_358) v_v_1677_4)) (<= 0 v_v_1971_2) (<= (+ v_b_138_4 2) v_b_130_4) (or (= 0 (select |c_#memory_int| v_idx_357)) (<= .cse2 v_idx_357) (< v_idx_357 c_ULTIMATE.start_main_p2)) (<= .cse0 c_ULTIMATE.start_main_p2) (<= (+ v_b_138_4 3) v_b_131_4) (<= (+ v_b_127_4 1) v_b_130_4) (<= (+ v_b_127_4 2) v_b_131_4) (<= .cse2 v_b_130_4) (<= v_b_131_4 .cse1) (<= 0 (* 2 v_v_1971_2)) (or (< v_idx_355 v_b_138_4) (<= v_b_127_4 v_idx_355) (= (select |c_#memory_int| v_idx_355) v_v_1971_2)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_4) (<= v_b_127_4 .cse0) (or (< v_idx_356 v_b_127_4) (<= c_ULTIMATE.start_main_p2 v_idx_356) (= (select |c_#memory_int| v_idx_356) v_v_1675_4)) (<= v_b_127_4 c_ULTIMATE.start_main_p2))))) is different from false [2019-01-08 14:35:02,868 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-08 14:35:02,869 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:35:02,869 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:35:02,869 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [2] total 5 [2019-01-08 14:35:02,869 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:35:02,869 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-08 14:35:02,869 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-08 14:35:02,870 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:35:02,870 INFO L87 Difference]: Start difference. First operand 9 states and 16 transitions. Second operand 5 states. [2019-01-08 14:35:05,381 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_346 Int) (v_idx_344 Int) (v_idx_345 Int) (v_idx_342 Int) (v_idx_343 Int) (v_idx_340 Int) (v_idx_341 Int)) (exists ((v_v_1673_3 Int) (v_b_131_4 Int) (v_b_130_4 Int) (v_v_1677_4 Int) (v_v_1679_3 Int) (v_v_1674_4 Int) (v_v_1675_4 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_130_4 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_342 .cse0) (= (select |c_#memory_int| v_idx_342) v_v_1675_4) (<= c_ULTIMATE.start_main_p2 v_idx_342)) (<= 0 v_v_1674_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_4) (or (= (select |c_#memory_int| v_idx_343) 0) (<= .cse1 v_idx_343) (< v_idx_343 c_ULTIMATE.start_main_p2)) (or (< v_idx_344 .cse1) (= (select |c_#memory_int| v_idx_344) v_v_1677_4) (<= v_b_130_4 v_idx_344)) (<= .cse2 v_b_131_4) (or (< v_idx_345 v_b_130_4) (= 0 (select |c_#memory_int| v_idx_345)) (<= v_b_131_4 v_idx_345)) (or (< v_idx_341 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_341) (= (select |c_#memory_int| v_idx_341) v_v_1674_4)) (<= .cse1 v_b_130_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_340) (= (select |c_#memory_int| v_idx_340) v_v_1673_3)) (<= v_b_131_4 .cse2) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_4) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_4) (<= .cse0 c_ULTIMATE.start_main_p2) (or (< v_idx_346 v_b_131_4) (= (select |c_#memory_int| v_idx_346) v_v_1679_3)) (<= 0 (* 2 v_v_1674_4)))))) (forall ((v_idx_357 Int) (v_idx_358 Int) (v_idx_355 Int) (v_idx_356 Int) (v_idx_359 Int) (v_idx_360 Int) (v_idx_354 Int)) (exists ((v_v_1673_3 Int) (v_b_131_4 Int) (v_b_130_4 Int) (v_v_1677_4 Int) (v_b_127_4 Int) (v_v_1679_3 Int) (v_v_1971_2 Int) (v_v_1675_4 Int) (v_b_138_4 Int)) (let ((.cse5 (+ c_ULTIMATE.start_main_p2 1)) (.cse4 (+ v_b_130_4 1)) (.cse3 (+ v_b_138_4 1))) (and (or (<= v_b_131_4 v_idx_359) (= 0 (select |c_#memory_int| v_idx_359)) (< v_idx_359 v_b_130_4)) (or (< v_idx_360 v_b_131_4) (= (select |c_#memory_int| v_idx_360) v_v_1679_3)) (<= .cse3 v_b_127_4) (or (= (select |c_#memory_int| v_idx_354) v_v_1673_3) (<= v_b_138_4 v_idx_354)) (<= .cse4 v_b_131_4) (or (<= v_b_130_4 v_idx_358) (< v_idx_358 .cse5) (= (select |c_#memory_int| v_idx_358) v_v_1677_4)) (<= 0 v_v_1971_2) (<= (+ v_b_138_4 2) v_b_130_4) (or (= 0 (select |c_#memory_int| v_idx_357)) (<= .cse5 v_idx_357) (< v_idx_357 c_ULTIMATE.start_main_p2)) (<= .cse3 c_ULTIMATE.start_main_p2) (<= (+ v_b_138_4 3) v_b_131_4) (<= (+ v_b_127_4 1) v_b_130_4) (<= (+ v_b_127_4 2) v_b_131_4) (<= .cse5 v_b_130_4) (<= v_b_131_4 .cse4) (<= 0 (* 2 v_v_1971_2)) (or (< v_idx_355 v_b_138_4) (<= v_b_127_4 v_idx_355) (= (select |c_#memory_int| v_idx_355) v_v_1971_2)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_4) (<= v_b_127_4 .cse3) (or (< v_idx_356 v_b_127_4) (<= c_ULTIMATE.start_main_p2 v_idx_356) (= (select |c_#memory_int| v_idx_356) v_v_1675_4)) (<= v_b_127_4 c_ULTIMATE.start_main_p2))))) (forall ((v_idx_347 Int) (v_idx_348 Int) (v_idx_349 Int) (v_idx_350 Int) (v_idx_353 Int) (v_idx_351 Int) (v_idx_352 Int)) (exists ((v_v_1673_3 Int) (v_b_131_4 Int) (v_b_130_4 Int) (v_v_1677_4 Int) (v_v_1679_3 Int) (v_v_1674_4 Int) (v_v_1675_4 Int)) (let ((.cse6 (+ c_ULTIMATE.start_main_p2 1)) (.cse7 (+ v_b_130_4 1)) (.cse8 (+ c_ULTIMATE.start_main_p1 1))) (and (<= 0 v_v_1674_4) (or (= 0 (select |c_#memory_int| v_idx_352)) (< v_idx_352 v_b_130_4) (<= v_b_131_4 v_idx_352)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_4) (or (= 0 (select |c_#memory_int| v_idx_350)) (<= .cse6 v_idx_350) (< v_idx_350 c_ULTIMATE.start_main_p2)) (<= .cse7 v_b_131_4) (or (= (select |c_#memory_int| v_idx_353) v_v_1679_3) (< v_idx_353 v_b_131_4)) (<= .cse6 v_b_130_4) (or (< v_idx_348 c_ULTIMATE.start_main_p1) (<= .cse8 v_idx_348) (= (select |c_#memory_int| v_idx_348) v_v_1674_4)) (or (= (select |c_#memory_int| v_idx_351) v_v_1677_4) (< v_idx_351 .cse6) (<= v_b_130_4 v_idx_351)) (or (= (select |c_#memory_int| v_idx_349) v_v_1675_4) (<= c_ULTIMATE.start_main_p2 v_idx_349) (< v_idx_349 .cse8)) (<= v_b_131_4 .cse7) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_4) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_4) (<= .cse8 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_347) v_v_1673_3) (<= c_ULTIMATE.start_main_p1 v_idx_347)) (<= 0 (* 2 v_v_1674_4))))))) is different from false [2019-01-08 14:35:26,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:35:26,758 INFO L93 Difference]: Finished difference Result 12 states and 22 transitions. [2019-01-08 14:35:26,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-08 14:35:26,758 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-08 14:35:26,759 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:35:26,759 INFO L225 Difference]: With dead ends: 12 [2019-01-08 14:35:26,759 INFO L226 Difference]: Without dead ends: 11 [2019-01-08 14:35:26,760 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 9.3s TimeCoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-08 14:35:26,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2019-01-08 14:35:26,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2019-01-08 14:35:26,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11 states. [2019-01-08 14:35:26,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 21 transitions. [2019-01-08 14:35:26,769 INFO L78 Accepts]: Start accepts. Automaton has 11 states and 21 transitions. Word has length 4 [2019-01-08 14:35:26,769 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:35:26,770 INFO L480 AbstractCegarLoop]: Abstraction has 11 states and 21 transitions. [2019-01-08 14:35:26,770 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-08 14:35:26,770 INFO L276 IsEmpty]: Start isEmpty. Operand 11 states and 21 transitions. [2019-01-08 14:35:26,770 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-08 14:35:26,770 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:35:26,771 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1] [2019-01-08 14:35:26,771 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:35:26,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:35:26,771 INFO L82 PathProgramCache]: Analyzing trace with hash 929488, now seen corresponding path program 2 times [2019-01-08 14:35:26,771 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:35:26,772 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:26,772 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:35:26,772 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:26,773 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:35:26,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:35:26,832 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:35:26,832 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:35:26,832 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:35:26,833 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-08 14:35:26,834 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-08 14:35:26,834 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:35:26,834 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-08 14:35:26,844 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-08 14:35:26,845 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-08 14:35:26,868 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-08 14:35:26,869 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-08 14:35:26,874 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-08 14:35:26,921 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-08 14:35:26,962 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:26,963 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-08 14:35:26,991 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:26,993 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:26,994 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-08 14:35:26,995 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-08 14:35:27,019 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:35:27,026 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:35:27,040 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:35:27,041 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:19, output treesize:22 [2019-01-08 14:35:27,093 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:27,104 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:27,105 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:27,106 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:27,107 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 28 [2019-01-08 14:35:27,109 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:35:27,137 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:35:27,137 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-08 14:35:27,185 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:27,187 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:27,189 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:27,191 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:27,193 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:27,194 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:27,196 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 40 [2019-01-08 14:35:27,197 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:35:27,222 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:35:27,223 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-08 14:35:27,243 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:35:27,243 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-08 14:35:27,256 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:35:27,276 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-01-08 14:35:27,277 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 7 [2019-01-08 14:35:27,277 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:35:27,277 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-08 14:35:27,277 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-08 14:35:27,278 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=41, Unknown=0, NotChecked=0, Total=72 [2019-01-08 14:35:27,278 INFO L87 Difference]: Start difference. First operand 11 states and 21 transitions. Second operand 5 states. [2019-01-08 14:35:27,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:35:27,651 INFO L93 Difference]: Finished difference Result 18 states and 40 transitions. [2019-01-08 14:35:27,651 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-08 14:35:27,651 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-08 14:35:27,652 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:35:27,652 INFO L225 Difference]: With dead ends: 18 [2019-01-08 14:35:27,652 INFO L226 Difference]: Without dead ends: 17 [2019-01-08 14:35:27,653 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=41, Unknown=0, NotChecked=0, Total=72 [2019-01-08 14:35:27,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2019-01-08 14:35:27,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 14. [2019-01-08 14:35:27,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2019-01-08 14:35:27,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 35 transitions. [2019-01-08 14:35:27,664 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 35 transitions. Word has length 4 [2019-01-08 14:35:27,664 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:35:27,664 INFO L480 AbstractCegarLoop]: Abstraction has 14 states and 35 transitions. [2019-01-08 14:35:27,665 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-08 14:35:27,665 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 35 transitions. [2019-01-08 14:35:27,665 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-08 14:35:27,665 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:35:27,665 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-08 14:35:27,666 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:35:27,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:35:27,666 INFO L82 PathProgramCache]: Analyzing trace with hash 929612, now seen corresponding path program 1 times [2019-01-08 14:35:27,666 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:35:27,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:27,667 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-08 14:35:27,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:27,667 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:35:27,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:35:27,847 WARN L181 SmtUtils]: Spent 133.00 ms on a formula simplification. DAG size of input: 17 DAG size of output: 9 [2019-01-08 14:35:27,983 WARN L181 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 20 DAG size of output: 13 [2019-01-08 14:35:27,987 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:35:27,988 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:35:27,988 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:35:27,988 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-08 14:35:27,988 INFO L207 CegarAbsIntRunner]: [0], [6], [10], [15] [2019-01-08 14:35:27,990 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:35:27,990 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:35:39,787 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:35:39,787 INFO L272 AbstractInterpreter]: Visited 4 different actions 34 times. Merged at 2 different actions 10 times. Widened at 2 different actions 6 times. Found 12 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-08 14:35:39,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:35:39,788 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:35:40,103 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 61.9% of their original sizes. [2019-01-08 14:35:40,104 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:35:42,617 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_465 Int) (v_idx_466 Int) (v_idx_460 Int) (v_idx_463 Int) (v_idx_464 Int) (v_idx_461 Int) (v_idx_462 Int)) (exists ((v_v_3906_1 Int) (v_v_3902_1 Int) (v_v_3903_1 Int) (v_b_329_1 Int) (v_b_328_1 Int) (v_v_3904_1 Int) (v_v_3900_1 Int) (v_v_3901_1 Int)) (let ((.cse2 (+ v_b_328_1 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (or (< v_idx_463 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_463) (= (select |c_#memory_int| v_idx_463) v_v_3903_1)) (or (< v_idx_461 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_461) (= (select |c_#memory_int| v_idx_461) v_v_3901_1)) (<= .cse2 v_b_329_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_460) (= (select |c_#memory_int| v_idx_460) v_v_3900_1)) (<= .cse0 v_b_328_1) (<= v_b_329_1 .cse2) (<= 0 v_v_3901_1) (or (<= c_ULTIMATE.start_main_p2 v_idx_462) (< v_idx_462 .cse1) (= (select |c_#memory_int| v_idx_462) v_v_3902_1)) (or (= (select |c_#memory_int| v_idx_465) 0) (<= v_b_329_1 v_idx_465) (< v_idx_465 v_b_328_1)) (<= v_v_3903_1 0) (<= 0 (* 2 v_v_3901_1)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_329_1) (<= v_v_3903_1 v_v_3901_1) (<= (* 2 v_v_3903_1) 0) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_328_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_329_1) (<= .cse1 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_466) v_v_3906_1) (< v_idx_466 v_b_329_1)) (or (< v_idx_464 .cse0) (= (select |c_#memory_int| v_idx_464) v_v_3904_1) (<= v_b_328_1 v_idx_464)))))) is different from false [2019-01-08 14:35:45,257 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_467 Int) (v_idx_468 Int) (v_idx_469 Int) (v_idx_470 Int) (v_idx_471 Int) (v_idx_472 Int) (v_idx_473 Int)) (exists ((v_v_3906_1 Int) (v_v_3902_1 Int) (v_b_329_1 Int) (v_v_3903_1 Int) (v_v_3904_1 Int) (v_b_328_1 Int) (v_v_3900_1 Int) (v_v_3901_1 Int)) (let ((.cse2 (+ v_b_328_1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= v_b_328_1 v_idx_471) (= (select |c_#memory_int| v_idx_471) v_v_3904_1) (< v_idx_471 .cse0)) (or (= (select |c_#memory_int| v_idx_469) v_v_3902_1) (<= c_ULTIMATE.start_main_p2 v_idx_469) (< v_idx_469 .cse1)) (or (= (select |c_#memory_int| v_idx_468) v_v_3901_1) (< v_idx_468 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_468)) (<= .cse2 v_b_329_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_467) (= (select |c_#memory_int| v_idx_467) v_v_3900_1)) (<= .cse0 v_b_328_1) (<= v_b_329_1 .cse2) (<= 0 v_v_3901_1) (<= v_v_3903_1 0) (or (= (select |c_#memory_int| v_idx_473) v_v_3906_1) (< v_idx_473 v_b_329_1)) (or (<= v_b_329_1 v_idx_472) (< v_idx_472 v_b_328_1) (= (select |c_#memory_int| v_idx_472) 0)) (<= 0 (* 2 v_v_3901_1)) (or (< v_idx_470 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_470) v_v_3903_1) (<= .cse0 v_idx_470)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_329_1) (<= v_v_3903_1 v_v_3901_1) (<= (* 2 v_v_3903_1) 0) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_328_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_329_1) (<= .cse1 c_ULTIMATE.start_main_p2))))) is different from false [2019-01-08 14:35:48,143 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_478 Int) (v_idx_479 Int) (v_idx_476 Int) (v_idx_477 Int) (v_idx_480 Int) (v_idx_474 Int) (v_idx_475 Int)) (exists ((v_v_3906_1 Int) (v_v_3903_1 Int) (v_b_329_1 Int) (v_v_3902_1 Int) (v_b_327_1 Int) (v_b_328_1 Int) (v_v_3904_1 Int) (v_b_326_1 Int) (v_v_3900_1 Int) (v_v_3901_1 Int)) (let ((.cse1 (+ v_b_328_1 1)) (.cse0 (+ v_b_326_1 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2))) (and (or (= (select |c_#memory_int| v_idx_479) 0) (<= v_b_329_1 v_idx_479) (< v_idx_479 v_b_328_1)) (<= v_b_327_1 .cse0) (<= .cse1 v_b_329_1) (or (= (select |c_#memory_int| v_idx_475) v_v_3901_1) (<= .cse2 v_idx_475) (< v_idx_475 c_ULTIMATE.start_main_p1)) (<= (+ v_b_327_1 1) v_b_329_1) (<= .cse3 v_b_327_1) (<= v_b_327_1 v_b_328_1) (<= v_b_329_1 .cse1) (<= 0 v_v_3901_1) (<= v_v_3903_1 0) (or (= (select |c_#memory_int| v_idx_477) v_v_3903_1) (<= v_b_327_1 v_idx_477) (< v_idx_477 v_b_326_1)) (<= 0 (* 2 v_v_3901_1)) (<= .cse0 v_b_327_1) (<= .cse0 v_b_328_1) (or (< v_idx_476 .cse2) (<= v_b_326_1 v_idx_476) (= (select |c_#memory_int| v_idx_476) v_v_3902_1)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_329_1) (<= v_v_3903_1 v_v_3901_1) (<= .cse2 v_b_326_1) (<= (* 2 v_v_3903_1) 0) (<= .cse3 v_b_328_1) (<= (+ v_b_326_1 2) v_b_329_1) (or (= (select |c_#memory_int| v_idx_480) v_v_3906_1) (< v_idx_480 v_b_329_1)) (or (= (select |c_#memory_int| v_idx_474) v_v_3900_1) (<= c_ULTIMATE.start_main_p1 v_idx_474)) (or (= (select |c_#memory_int| v_idx_478) v_v_3904_1) (< v_idx_478 v_b_327_1) (<= v_b_328_1 v_idx_478)))))) is different from false [2019-01-08 14:35:48,221 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-08 14:35:48,222 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:35:48,222 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:35:48,222 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 6 [2019-01-08 14:35:48,222 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:35:48,222 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-08 14:35:48,223 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-08 14:35:48,223 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:35:48,223 INFO L87 Difference]: Start difference. First operand 14 states and 35 transitions. Second operand 5 states. [2019-01-08 14:35:50,819 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_467 Int) (v_idx_468 Int) (v_idx_469 Int) (v_idx_470 Int) (v_idx_471 Int) (v_idx_472 Int) (v_idx_473 Int)) (exists ((v_v_3906_1 Int) (v_v_3902_1 Int) (v_b_329_1 Int) (v_v_3903_1 Int) (v_v_3904_1 Int) (v_b_328_1 Int) (v_v_3900_1 Int) (v_v_3901_1 Int)) (let ((.cse2 (+ v_b_328_1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= v_b_328_1 v_idx_471) (= (select |c_#memory_int| v_idx_471) v_v_3904_1) (< v_idx_471 .cse0)) (or (= (select |c_#memory_int| v_idx_469) v_v_3902_1) (<= c_ULTIMATE.start_main_p2 v_idx_469) (< v_idx_469 .cse1)) (or (= (select |c_#memory_int| v_idx_468) v_v_3901_1) (< v_idx_468 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_468)) (<= .cse2 v_b_329_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_467) (= (select |c_#memory_int| v_idx_467) v_v_3900_1)) (<= .cse0 v_b_328_1) (<= v_b_329_1 .cse2) (<= 0 v_v_3901_1) (<= v_v_3903_1 0) (or (= (select |c_#memory_int| v_idx_473) v_v_3906_1) (< v_idx_473 v_b_329_1)) (or (<= v_b_329_1 v_idx_472) (< v_idx_472 v_b_328_1) (= (select |c_#memory_int| v_idx_472) 0)) (<= 0 (* 2 v_v_3901_1)) (or (< v_idx_470 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_470) v_v_3903_1) (<= .cse0 v_idx_470)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_329_1) (<= v_v_3903_1 v_v_3901_1) (<= (* 2 v_v_3903_1) 0) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_328_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_329_1) (<= .cse1 c_ULTIMATE.start_main_p2))))) (forall ((v_idx_465 Int) (v_idx_466 Int) (v_idx_460 Int) (v_idx_463 Int) (v_idx_464 Int) (v_idx_461 Int) (v_idx_462 Int)) (exists ((v_v_3906_1 Int) (v_v_3902_1 Int) (v_v_3903_1 Int) (v_b_329_1 Int) (v_b_328_1 Int) (v_v_3904_1 Int) (v_v_3900_1 Int) (v_v_3901_1 Int)) (let ((.cse5 (+ v_b_328_1 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ c_ULTIMATE.start_main_p2 1))) (and (or (< v_idx_463 c_ULTIMATE.start_main_p2) (<= .cse3 v_idx_463) (= (select |c_#memory_int| v_idx_463) v_v_3903_1)) (or (< v_idx_461 c_ULTIMATE.start_main_p1) (<= .cse4 v_idx_461) (= (select |c_#memory_int| v_idx_461) v_v_3901_1)) (<= .cse5 v_b_329_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_460) (= (select |c_#memory_int| v_idx_460) v_v_3900_1)) (<= .cse3 v_b_328_1) (<= v_b_329_1 .cse5) (<= 0 v_v_3901_1) (or (<= c_ULTIMATE.start_main_p2 v_idx_462) (< v_idx_462 .cse4) (= (select |c_#memory_int| v_idx_462) v_v_3902_1)) (or (= (select |c_#memory_int| v_idx_465) 0) (<= v_b_329_1 v_idx_465) (< v_idx_465 v_b_328_1)) (<= v_v_3903_1 0) (<= 0 (* 2 v_v_3901_1)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_329_1) (<= v_v_3903_1 v_v_3901_1) (<= (* 2 v_v_3903_1) 0) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_328_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_329_1) (<= .cse4 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_466) v_v_3906_1) (< v_idx_466 v_b_329_1)) (or (< v_idx_464 .cse3) (= (select |c_#memory_int| v_idx_464) v_v_3904_1) (<= v_b_328_1 v_idx_464)))))) (forall ((v_idx_478 Int) (v_idx_479 Int) (v_idx_476 Int) (v_idx_477 Int) (v_idx_480 Int) (v_idx_474 Int) (v_idx_475 Int)) (exists ((v_v_3906_1 Int) (v_v_3903_1 Int) (v_b_329_1 Int) (v_v_3902_1 Int) (v_b_327_1 Int) (v_b_328_1 Int) (v_v_3904_1 Int) (v_b_326_1 Int) (v_v_3900_1 Int) (v_v_3901_1 Int)) (let ((.cse7 (+ v_b_328_1 1)) (.cse6 (+ v_b_326_1 1)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 2))) (and (or (= (select |c_#memory_int| v_idx_479) 0) (<= v_b_329_1 v_idx_479) (< v_idx_479 v_b_328_1)) (<= v_b_327_1 .cse6) (<= .cse7 v_b_329_1) (or (= (select |c_#memory_int| v_idx_475) v_v_3901_1) (<= .cse8 v_idx_475) (< v_idx_475 c_ULTIMATE.start_main_p1)) (<= (+ v_b_327_1 1) v_b_329_1) (<= .cse9 v_b_327_1) (<= v_b_327_1 v_b_328_1) (<= v_b_329_1 .cse7) (<= 0 v_v_3901_1) (<= v_v_3903_1 0) (or (= (select |c_#memory_int| v_idx_477) v_v_3903_1) (<= v_b_327_1 v_idx_477) (< v_idx_477 v_b_326_1)) (<= 0 (* 2 v_v_3901_1)) (<= .cse6 v_b_327_1) (<= .cse6 v_b_328_1) (or (< v_idx_476 .cse8) (<= v_b_326_1 v_idx_476) (= (select |c_#memory_int| v_idx_476) v_v_3902_1)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_329_1) (<= v_v_3903_1 v_v_3901_1) (<= .cse8 v_b_326_1) (<= (* 2 v_v_3903_1) 0) (<= .cse9 v_b_328_1) (<= (+ v_b_326_1 2) v_b_329_1) (or (= (select |c_#memory_int| v_idx_480) v_v_3906_1) (< v_idx_480 v_b_329_1)) (or (= (select |c_#memory_int| v_idx_474) v_v_3900_1) (<= c_ULTIMATE.start_main_p1 v_idx_474)) (or (= (select |c_#memory_int| v_idx_478) v_v_3904_1) (< v_idx_478 v_b_327_1) (<= v_b_328_1 v_idx_478))))))) is different from false [2019-01-08 14:36:20,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:36:20,356 INFO L93 Difference]: Finished difference Result 16 states and 40 transitions. [2019-01-08 14:36:20,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-08 14:36:20,356 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-08 14:36:20,356 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:36:20,357 INFO L225 Difference]: With dead ends: 16 [2019-01-08 14:36:20,357 INFO L226 Difference]: Without dead ends: 15 [2019-01-08 14:36:20,358 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 10.6s TimeCoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-08 14:36:20,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states. [2019-01-08 14:36:20,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 14. [2019-01-08 14:36:20,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2019-01-08 14:36:20,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 35 transitions. [2019-01-08 14:36:20,369 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 35 transitions. Word has length 4 [2019-01-08 14:36:20,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:36:20,369 INFO L480 AbstractCegarLoop]: Abstraction has 14 states and 35 transitions. [2019-01-08 14:36:20,369 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-08 14:36:20,369 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 35 transitions. [2019-01-08 14:36:20,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-08 14:36:20,370 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:36:20,370 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-08 14:36:20,371 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:36:20,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:36:20,371 INFO L82 PathProgramCache]: Analyzing trace with hash 933644, now seen corresponding path program 1 times [2019-01-08 14:36:20,371 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:36:20,372 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:36:20,372 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:36:20,372 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:36:20,372 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:36:20,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:36:20,413 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:36:20,413 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:36:20,413 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:36:20,413 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-08 14:36:20,414 INFO L207 CegarAbsIntRunner]: [0], [10], [16], [17] [2019-01-08 14:36:20,414 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:36:20,415 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:36:26,462 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:36:26,463 INFO L272 AbstractInterpreter]: Visited 4 different actions 16 times. Merged at 2 different actions 8 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:36:26,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:36:26,463 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:36:26,728 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 61.9% of their original sizes. [2019-01-08 14:36:26,729 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:36:29,153 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_586 Int) (v_idx_580 Int) (v_idx_581 Int) (v_idx_584 Int) (v_idx_585 Int) (v_idx_582 Int) (v_idx_583 Int)) (exists ((v_b_140_6 Int) (v_b_141_6 Int) (v_v_1658_6 Int) (v_v_1664_6 Int) (v_v_1662_6 Int) (v_v_1661_6 Int) (v_v_1660_6 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_140_6 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 3) v_b_141_6) (<= .cse0 v_b_141_6) (<= .cse1 v_b_140_6) (or (< v_idx_581 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_581) (= (select |c_#memory_int| v_idx_581) 0)) (or (< v_idx_583 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_583) v_v_1661_6) (<= .cse1 v_idx_583)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_140_6) (or (< v_idx_585 v_b_140_6) (<= v_b_141_6 v_idx_585) (= (select |c_#memory_int| v_idx_585) 0)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_141_6) (or (<= v_b_140_6 v_idx_584) (< v_idx_584 .cse1) (= (select |c_#memory_int| v_idx_584) v_v_1662_6)) (<= v_b_141_6 .cse0) (or (<= c_ULTIMATE.start_main_p1 v_idx_580) (= (select |c_#memory_int| v_idx_580) v_v_1658_6)) (<= v_v_1661_6 0) (or (< v_idx_586 v_b_141_6) (= (select |c_#memory_int| v_idx_586) v_v_1664_6)) (<= (* 2 v_v_1661_6) 0) (<= .cse2 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_582) v_v_1660_6) (< v_idx_582 .cse2) (<= c_ULTIMATE.start_main_p2 v_idx_582)))))) is different from false [2019-01-08 14:36:31,737 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_588 Int) (v_idx_589 Int) (v_idx_587 Int) (v_idx_591 Int) (v_idx_592 Int) (v_idx_590 Int) (v_idx_593 Int)) (exists ((v_b_140_6 Int) (v_b_141_6 Int) (v_v_1658_6 Int) (v_v_1664_6 Int) (v_v_1662_6 Int) (v_v_1661_6 Int) (v_v_1660_6 Int)) (let ((.cse0 (+ v_b_140_6 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 3) v_b_141_6) (<= .cse0 v_b_141_6) (<= .cse1 v_b_140_6) (or (= (select |c_#memory_int| v_idx_587) v_v_1658_6) (<= c_ULTIMATE.start_main_p1 v_idx_587)) (or (< v_idx_588 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_588) (= (select |c_#memory_int| v_idx_588) 0)) (or (<= v_b_141_6 v_idx_592) (= 0 (select |c_#memory_int| v_idx_592)) (< v_idx_592 v_b_140_6)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_140_6) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_141_6) (<= v_b_141_6 .cse0) (or (< v_idx_591 .cse1) (= (select |c_#memory_int| v_idx_591) v_v_1662_6) (<= v_b_140_6 v_idx_591)) (<= v_v_1661_6 0) (<= (* 2 v_v_1661_6) 0) (or (< v_idx_589 .cse2) (= (select |c_#memory_int| v_idx_589) v_v_1660_6) (<= c_ULTIMATE.start_main_p2 v_idx_589)) (<= .cse2 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_593) v_v_1664_6) (< v_idx_593 v_b_141_6)) (or (< v_idx_590 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_590) (= (select |c_#memory_int| v_idx_590) v_v_1661_6)))))) is different from false [2019-01-08 14:36:34,025 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_599 Int) (v_idx_600 Int) (v_idx_597 Int) (v_idx_598 Int) (v_idx_595 Int) (v_idx_596 Int) (v_idx_594 Int)) (exists ((v_b_140_6 Int) (v_b_141_6 Int) (v_v_1658_6 Int) (v_v_1664_6 Int) (v_b_137_6 Int) (v_b_148_6 Int) (v_v_1662_6 Int) (v_v_1661_6 Int) (v_v_1660_6 Int)) (let ((.cse0 (+ v_b_148_6 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_140_6 1))) (and (<= .cse0 v_b_137_6) (<= (+ v_b_148_6 2) v_b_140_6) (<= .cse1 v_b_141_6) (<= v_b_137_6 .cse0) (<= .cse2 v_b_140_6) (<= (+ v_b_137_6 2) v_b_141_6) (or (< v_idx_600 v_b_141_6) (= (select |c_#memory_int| v_idx_600) v_v_1664_6)) (or (< v_idx_596 v_b_137_6) (= (select |c_#memory_int| v_idx_596) v_v_1660_6) (<= c_ULTIMATE.start_main_p2 v_idx_596)) (<= .cse0 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_599) 0) (<= v_b_141_6 v_idx_599) (< v_idx_599 v_b_140_6)) (or (= (select |c_#memory_int| v_idx_594) v_v_1658_6) (<= v_b_148_6 v_idx_594)) (or (<= v_b_137_6 v_idx_595) (= (select |c_#memory_int| v_idx_595) 0) (< v_idx_595 v_b_148_6)) (<= (+ v_b_148_6 3) v_b_141_6) (or (= (select |c_#memory_int| v_idx_597) v_v_1661_6) (< v_idx_597 c_ULTIMATE.start_main_p2) (<= .cse2 v_idx_597)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_141_6) (<= (+ v_b_137_6 1) v_b_140_6) (<= v_b_137_6 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_598) v_v_1662_6) (<= v_b_140_6 v_idx_598) (< v_idx_598 .cse2)) (<= v_b_141_6 .cse1) (<= v_v_1661_6 0) (<= (* 2 v_v_1661_6) 0))))) is different from false [2019-01-08 14:36:34,078 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-08 14:36:34,078 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:36:34,079 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:36:34,079 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [2] total 5 [2019-01-08 14:36:34,079 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:36:34,079 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-08 14:36:34,079 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-08 14:36:34,079 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:36:34,080 INFO L87 Difference]: Start difference. First operand 14 states and 35 transitions. Second operand 5 states. [2019-01-08 14:36:36,592 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_599 Int) (v_idx_600 Int) (v_idx_597 Int) (v_idx_598 Int) (v_idx_595 Int) (v_idx_596 Int) (v_idx_594 Int)) (exists ((v_b_140_6 Int) (v_b_141_6 Int) (v_v_1658_6 Int) (v_v_1664_6 Int) (v_b_137_6 Int) (v_b_148_6 Int) (v_v_1662_6 Int) (v_v_1661_6 Int) (v_v_1660_6 Int)) (let ((.cse0 (+ v_b_148_6 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_140_6 1))) (and (<= .cse0 v_b_137_6) (<= (+ v_b_148_6 2) v_b_140_6) (<= .cse1 v_b_141_6) (<= v_b_137_6 .cse0) (<= .cse2 v_b_140_6) (<= (+ v_b_137_6 2) v_b_141_6) (or (< v_idx_600 v_b_141_6) (= (select |c_#memory_int| v_idx_600) v_v_1664_6)) (or (< v_idx_596 v_b_137_6) (= (select |c_#memory_int| v_idx_596) v_v_1660_6) (<= c_ULTIMATE.start_main_p2 v_idx_596)) (<= .cse0 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_599) 0) (<= v_b_141_6 v_idx_599) (< v_idx_599 v_b_140_6)) (or (= (select |c_#memory_int| v_idx_594) v_v_1658_6) (<= v_b_148_6 v_idx_594)) (or (<= v_b_137_6 v_idx_595) (= (select |c_#memory_int| v_idx_595) 0) (< v_idx_595 v_b_148_6)) (<= (+ v_b_148_6 3) v_b_141_6) (or (= (select |c_#memory_int| v_idx_597) v_v_1661_6) (< v_idx_597 c_ULTIMATE.start_main_p2) (<= .cse2 v_idx_597)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_141_6) (<= (+ v_b_137_6 1) v_b_140_6) (<= v_b_137_6 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_598) v_v_1662_6) (<= v_b_140_6 v_idx_598) (< v_idx_598 .cse2)) (<= v_b_141_6 .cse1) (<= v_v_1661_6 0) (<= (* 2 v_v_1661_6) 0))))) (forall ((v_idx_586 Int) (v_idx_580 Int) (v_idx_581 Int) (v_idx_584 Int) (v_idx_585 Int) (v_idx_582 Int) (v_idx_583 Int)) (exists ((v_b_140_6 Int) (v_b_141_6 Int) (v_v_1658_6 Int) (v_v_1664_6 Int) (v_v_1662_6 Int) (v_v_1661_6 Int) (v_v_1660_6 Int)) (let ((.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse3 (+ v_b_140_6 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 3) v_b_141_6) (<= .cse3 v_b_141_6) (<= .cse4 v_b_140_6) (or (< v_idx_581 c_ULTIMATE.start_main_p1) (<= .cse5 v_idx_581) (= (select |c_#memory_int| v_idx_581) 0)) (or (< v_idx_583 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_583) v_v_1661_6) (<= .cse4 v_idx_583)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_140_6) (or (< v_idx_585 v_b_140_6) (<= v_b_141_6 v_idx_585) (= (select |c_#memory_int| v_idx_585) 0)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_141_6) (or (<= v_b_140_6 v_idx_584) (< v_idx_584 .cse4) (= (select |c_#memory_int| v_idx_584) v_v_1662_6)) (<= v_b_141_6 .cse3) (or (<= c_ULTIMATE.start_main_p1 v_idx_580) (= (select |c_#memory_int| v_idx_580) v_v_1658_6)) (<= v_v_1661_6 0) (or (< v_idx_586 v_b_141_6) (= (select |c_#memory_int| v_idx_586) v_v_1664_6)) (<= (* 2 v_v_1661_6) 0) (<= .cse5 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_582) v_v_1660_6) (< v_idx_582 .cse5) (<= c_ULTIMATE.start_main_p2 v_idx_582)))))) (forall ((v_idx_588 Int) (v_idx_589 Int) (v_idx_587 Int) (v_idx_591 Int) (v_idx_592 Int) (v_idx_590 Int) (v_idx_593 Int)) (exists ((v_b_140_6 Int) (v_b_141_6 Int) (v_v_1658_6 Int) (v_v_1664_6 Int) (v_v_1662_6 Int) (v_v_1661_6 Int) (v_v_1660_6 Int)) (let ((.cse6 (+ v_b_140_6 1)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 3) v_b_141_6) (<= .cse6 v_b_141_6) (<= .cse7 v_b_140_6) (or (= (select |c_#memory_int| v_idx_587) v_v_1658_6) (<= c_ULTIMATE.start_main_p1 v_idx_587)) (or (< v_idx_588 c_ULTIMATE.start_main_p1) (<= .cse8 v_idx_588) (= (select |c_#memory_int| v_idx_588) 0)) (or (<= v_b_141_6 v_idx_592) (= 0 (select |c_#memory_int| v_idx_592)) (< v_idx_592 v_b_140_6)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_140_6) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_141_6) (<= v_b_141_6 .cse6) (or (< v_idx_591 .cse7) (= (select |c_#memory_int| v_idx_591) v_v_1662_6) (<= v_b_140_6 v_idx_591)) (<= v_v_1661_6 0) (<= (* 2 v_v_1661_6) 0) (or (< v_idx_589 .cse8) (= (select |c_#memory_int| v_idx_589) v_v_1660_6) (<= c_ULTIMATE.start_main_p2 v_idx_589)) (<= .cse8 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_593) v_v_1664_6) (< v_idx_593 v_b_141_6)) (or (< v_idx_590 c_ULTIMATE.start_main_p2) (<= .cse7 v_idx_590) (= (select |c_#memory_int| v_idx_590) v_v_1661_6))))))) is different from false [2019-01-08 14:36:50,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:36:50,691 INFO L93 Difference]: Finished difference Result 17 states and 41 transitions. [2019-01-08 14:36:50,691 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-08 14:36:50,691 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-08 14:36:50,691 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:36:50,692 INFO L225 Difference]: With dead ends: 17 [2019-01-08 14:36:50,692 INFO L226 Difference]: Without dead ends: 16 [2019-01-08 14:36:50,692 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 9.8s TimeCoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-08 14:36:50,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-08 14:36:50,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2019-01-08 14:36:50,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-08 14:36:50,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 39 transitions. [2019-01-08 14:36:50,706 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 39 transitions. Word has length 4 [2019-01-08 14:36:50,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:36:50,706 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 39 transitions. [2019-01-08 14:36:50,707 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-08 14:36:50,707 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 39 transitions. [2019-01-08 14:36:50,707 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-08 14:36:50,707 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:36:50,707 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1] [2019-01-08 14:36:50,708 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:36:50,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:36:50,708 INFO L82 PathProgramCache]: Analyzing trace with hash 933456, now seen corresponding path program 2 times [2019-01-08 14:36:50,708 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:36:50,708 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:36:50,709 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:36:50,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:36:50,709 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:36:50,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:36:50,785 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-08 14:36:50,786 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:36:50,786 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:36:50,786 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-08 14:36:50,786 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-08 14:36:50,786 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:36:50,787 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-08 14:36:50,804 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-08 14:36:50,804 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-08 14:36:50,811 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-08 14:36:50,811 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-08 14:36:50,812 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-08 14:36:50,817 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-08 14:36:50,820 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:36:50,821 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-08 14:36:50,839 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:36:50,840 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:36:50,841 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-08 14:36:50,841 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-08 14:36:50,861 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:36:50,878 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:36:50,890 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:36:50,891 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:19, output treesize:22 [2019-01-08 14:36:50,914 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:36:50,916 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:36:50,918 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:36:50,920 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:36:50,921 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-08 14:36:50,921 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:36:50,957 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:36:50,957 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-08 14:36:50,979 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:36:50,980 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:36:50,983 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:36:50,984 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:36:50,985 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:36:50,986 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:36:50,987 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 40 [2019-01-08 14:36:50,988 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:36:51,012 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:36:51,012 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:22 [2019-01-08 14:36:51,029 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:36:51,030 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-08 14:36:51,096 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:36:51,117 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-08 14:36:51,117 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 3, 3] total 8 [2019-01-08 14:36:51,117 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-08 14:36:51,118 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-01-08 14:36:51,118 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-01-08 14:36:51,118 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=53, Unknown=0, NotChecked=0, Total=90 [2019-01-08 14:36:51,118 INFO L87 Difference]: Start difference. First operand 15 states and 39 transitions. Second operand 7 states. [2019-01-08 14:36:51,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:36:51,375 INFO L93 Difference]: Finished difference Result 29 states and 57 transitions. [2019-01-08 14:36:51,375 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-08 14:36:51,375 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 4 [2019-01-08 14:36:51,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:36:51,376 INFO L225 Difference]: With dead ends: 29 [2019-01-08 14:36:51,376 INFO L226 Difference]: Without dead ends: 28 [2019-01-08 14:36:51,377 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-01-08 14:36:51,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2019-01-08 14:36:51,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 17. [2019-01-08 14:36:51,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2019-01-08 14:36:51,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 47 transitions. [2019-01-08 14:36:51,392 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 47 transitions. Word has length 4 [2019-01-08 14:36:51,393 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:36:51,393 INFO L480 AbstractCegarLoop]: Abstraction has 17 states and 47 transitions. [2019-01-08 14:36:51,393 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-01-08 14:36:51,393 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 47 transitions. [2019-01-08 14:36:51,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-08 14:36:51,393 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:36:51,393 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-08 14:36:51,394 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:36:51,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:36:51,394 INFO L82 PathProgramCache]: Analyzing trace with hash 933518, now seen corresponding path program 1 times [2019-01-08 14:36:51,394 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:36:51,395 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:36:51,395 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-08 14:36:51,395 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:36:51,395 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:36:51,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:36:51,525 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:36:51,526 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:36:51,526 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:36:51,526 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-08 14:36:51,526 INFO L207 CegarAbsIntRunner]: [0], [10], [12], [15] [2019-01-08 14:36:51,528 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:36:51,528 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:37:00,928 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:37:00,928 INFO L272 AbstractInterpreter]: Visited 4 different actions 28 times. Merged at 2 different actions 8 times. Widened at 2 different actions 4 times. Found 10 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-08 14:37:00,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:37:00,928 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:37:01,270 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 57.14% of their original sizes. [2019-01-08 14:37:01,270 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:37:03,706 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_702 Int) (v_idx_703 Int) (v_idx_700 Int) (v_idx_701 Int) (v_idx_706 Int) (v_idx_704 Int) (v_idx_705 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_v_3066_2 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_v_3062_2 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_3067_2)) (or (<= .cse0 v_idx_703) (= (select |c_#memory_int| v_idx_703) v_v_3065_2) (< v_idx_703 c_ULTIMATE.start_main_p2)) (<= (* 2 v_v_3065_2) 0) (<= v_v_3065_2 v_v_3067_2) (<= 0 v_v_3067_2) (<= .cse0 c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p3 v_idx_704) (= (select |c_#memory_int| v_idx_704) v_v_3066_2) (< v_idx_704 .cse0)) (or (<= c_ULTIMATE.start_main_p1 v_idx_700) (= (select |c_#memory_int| v_idx_700) v_v_3062_2)) (or (= (select |c_#memory_int| v_idx_701) 0) (<= .cse1 v_idx_701) (< v_idx_701 c_ULTIMATE.start_main_p1)) (or (= (select |c_#memory_int| v_idx_706) v_v_3068_2) (< v_idx_706 .cse2)) (<= .cse1 c_ULTIMATE.start_main_p2) (or (< v_idx_702 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_702) (= (select |c_#memory_int| v_idx_702) v_v_3064_2)) (or (< v_idx_705 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_705) v_v_3067_2) (<= .cse2 v_idx_705)) (<= v_v_3065_2 0))))) is different from false [2019-01-08 14:37:06,360 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_710 Int) (v_idx_713 Int) (v_idx_711 Int) (v_idx_712 Int) (v_idx_707 Int) (v_idx_708 Int) (v_idx_709 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_v_3066_2 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_b_255_4 Int) (v_b_254_4 Int) (v_v_3062_2 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ v_b_254_4 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 2))) (and (<= .cse0 v_b_254_4) (<= .cse1 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_3067_2)) (or (= (select |c_#memory_int| v_idx_712) v_v_3067_2) (<= .cse2 v_idx_712) (< v_idx_712 c_ULTIMATE.start_main_p3)) (<= v_b_255_4 .cse3) (or (= (select |c_#memory_int| v_idx_713) v_v_3068_2) (< v_idx_713 .cse2)) (<= v_b_255_4 c_ULTIMATE.start_main_p3) (<= (* 2 v_v_3065_2) 0) (<= v_v_3065_2 v_v_3067_2) (<= .cse3 v_b_255_4) (or (= (select |c_#memory_int| v_idx_708) 0) (<= .cse0 v_idx_708) (< v_idx_708 c_ULTIMATE.start_main_p1)) (<= 0 v_v_3067_2) (or (= (select |c_#memory_int| v_idx_707) v_v_3062_2) (<= c_ULTIMATE.start_main_p1 v_idx_707)) (or (<= v_b_254_4 v_idx_709) (= (select |c_#memory_int| v_idx_709) v_v_3064_2) (< v_idx_709 .cse0)) (<= .cse3 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_711) v_v_3066_2) (<= c_ULTIMATE.start_main_p3 v_idx_711) (< v_idx_711 v_b_255_4)) (<= .cse1 v_b_255_4) (or (<= v_b_255_4 v_idx_710) (< v_idx_710 v_b_254_4) (= (select |c_#memory_int| v_idx_710) v_v_3065_2)) (<= v_v_3065_2 0))))) is different from false [2019-01-08 14:37:08,746 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_720 Int) (v_idx_714 Int) (v_idx_717 Int) (v_idx_718 Int) (v_idx_715 Int) (v_idx_716 Int) (v_idx_719 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_v_3066_2 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_b_255_4 Int) (v_b_254_4 Int) (v_v_3062_2 Int) (v_b_257_4 Int) (v_b_256_4 Int)) (let ((.cse1 (+ v_b_254_4 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ v_b_256_4 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_714) (= (select |c_#memory_int| v_idx_714) v_v_3062_2)) (<= .cse0 v_b_254_4) (or (< v_idx_720 v_b_257_4) (= (select |c_#memory_int| v_idx_720) v_v_3068_2)) (<= 0 (* 2 v_v_3067_2)) (<= v_b_255_4 .cse1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_257_4) (<= .cse2 v_b_257_4) (or (<= .cse0 v_idx_715) (< v_idx_715 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_715) 0)) (<= (* 2 v_v_3065_2) 0) (<= v_b_255_4 v_b_256_4) (<= v_v_3065_2 v_v_3067_2) (<= .cse1 v_b_255_4) (or (< v_idx_718 v_b_255_4) (<= v_b_256_4 v_idx_718) (= (select |c_#memory_int| v_idx_718) v_v_3066_2)) (<= .cse1 v_b_256_4) (<= 0 v_v_3067_2) (or (= (select |c_#memory_int| v_idx_719) v_v_3067_2) (< v_idx_719 v_b_256_4) (<= v_b_257_4 v_idx_719)) (or (< v_idx_716 .cse0) (= (select |c_#memory_int| v_idx_716) v_v_3064_2) (<= v_b_254_4 v_idx_716)) (<= (+ v_b_254_4 2) v_b_257_4) (or (<= v_b_255_4 v_idx_717) (= (select |c_#memory_int| v_idx_717) v_v_3065_2) (< v_idx_717 v_b_254_4)) (<= v_b_257_4 .cse2) (<= (+ v_b_255_4 1) v_b_257_4) (<= .cse3 v_b_255_4) (<= v_v_3065_2 0) (<= .cse3 v_b_256_4))))) is different from false [2019-01-08 14:37:08,819 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-08 14:37:08,819 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:37:08,819 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:37:08,819 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 6 [2019-01-08 14:37:08,819 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:37:08,819 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-08 14:37:08,820 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-08 14:37:08,820 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:37:08,820 INFO L87 Difference]: Start difference. First operand 17 states and 47 transitions. Second operand 5 states. [2019-01-08 14:37:11,384 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_720 Int) (v_idx_714 Int) (v_idx_717 Int) (v_idx_718 Int) (v_idx_715 Int) (v_idx_716 Int) (v_idx_719 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_v_3066_2 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_b_255_4 Int) (v_b_254_4 Int) (v_v_3062_2 Int) (v_b_257_4 Int) (v_b_256_4 Int)) (let ((.cse1 (+ v_b_254_4 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ v_b_256_4 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_714) (= (select |c_#memory_int| v_idx_714) v_v_3062_2)) (<= .cse0 v_b_254_4) (or (< v_idx_720 v_b_257_4) (= (select |c_#memory_int| v_idx_720) v_v_3068_2)) (<= 0 (* 2 v_v_3067_2)) (<= v_b_255_4 .cse1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_257_4) (<= .cse2 v_b_257_4) (or (<= .cse0 v_idx_715) (< v_idx_715 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_715) 0)) (<= (* 2 v_v_3065_2) 0) (<= v_b_255_4 v_b_256_4) (<= v_v_3065_2 v_v_3067_2) (<= .cse1 v_b_255_4) (or (< v_idx_718 v_b_255_4) (<= v_b_256_4 v_idx_718) (= (select |c_#memory_int| v_idx_718) v_v_3066_2)) (<= .cse1 v_b_256_4) (<= 0 v_v_3067_2) (or (= (select |c_#memory_int| v_idx_719) v_v_3067_2) (< v_idx_719 v_b_256_4) (<= v_b_257_4 v_idx_719)) (or (< v_idx_716 .cse0) (= (select |c_#memory_int| v_idx_716) v_v_3064_2) (<= v_b_254_4 v_idx_716)) (<= (+ v_b_254_4 2) v_b_257_4) (or (<= v_b_255_4 v_idx_717) (= (select |c_#memory_int| v_idx_717) v_v_3065_2) (< v_idx_717 v_b_254_4)) (<= v_b_257_4 .cse2) (<= (+ v_b_255_4 1) v_b_257_4) (<= .cse3 v_b_255_4) (<= v_v_3065_2 0) (<= .cse3 v_b_256_4))))) (forall ((v_idx_710 Int) (v_idx_713 Int) (v_idx_711 Int) (v_idx_712 Int) (v_idx_707 Int) (v_idx_708 Int) (v_idx_709 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_v_3066_2 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_b_255_4 Int) (v_b_254_4 Int) (v_v_3062_2 Int)) (let ((.cse6 (+ c_ULTIMATE.start_main_p3 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ v_b_254_4 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 2))) (and (<= .cse4 v_b_254_4) (<= .cse5 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_3067_2)) (or (= (select |c_#memory_int| v_idx_712) v_v_3067_2) (<= .cse6 v_idx_712) (< v_idx_712 c_ULTIMATE.start_main_p3)) (<= v_b_255_4 .cse7) (or (= (select |c_#memory_int| v_idx_713) v_v_3068_2) (< v_idx_713 .cse6)) (<= v_b_255_4 c_ULTIMATE.start_main_p3) (<= (* 2 v_v_3065_2) 0) (<= v_v_3065_2 v_v_3067_2) (<= .cse7 v_b_255_4) (or (= (select |c_#memory_int| v_idx_708) 0) (<= .cse4 v_idx_708) (< v_idx_708 c_ULTIMATE.start_main_p1)) (<= 0 v_v_3067_2) (or (= (select |c_#memory_int| v_idx_707) v_v_3062_2) (<= c_ULTIMATE.start_main_p1 v_idx_707)) (or (<= v_b_254_4 v_idx_709) (= (select |c_#memory_int| v_idx_709) v_v_3064_2) (< v_idx_709 .cse4)) (<= .cse7 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_711) v_v_3066_2) (<= c_ULTIMATE.start_main_p3 v_idx_711) (< v_idx_711 v_b_255_4)) (<= .cse5 v_b_255_4) (or (<= v_b_255_4 v_idx_710) (< v_idx_710 v_b_254_4) (= (select |c_#memory_int| v_idx_710) v_v_3065_2)) (<= v_v_3065_2 0))))) (forall ((v_idx_702 Int) (v_idx_703 Int) (v_idx_700 Int) (v_idx_701 Int) (v_idx_706 Int) (v_idx_704 Int) (v_idx_705 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_v_3066_2 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_v_3062_2 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p2 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 1)) (.cse10 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_3067_2)) (or (<= .cse8 v_idx_703) (= (select |c_#memory_int| v_idx_703) v_v_3065_2) (< v_idx_703 c_ULTIMATE.start_main_p2)) (<= (* 2 v_v_3065_2) 0) (<= v_v_3065_2 v_v_3067_2) (<= 0 v_v_3067_2) (<= .cse8 c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p3 v_idx_704) (= (select |c_#memory_int| v_idx_704) v_v_3066_2) (< v_idx_704 .cse8)) (or (<= c_ULTIMATE.start_main_p1 v_idx_700) (= (select |c_#memory_int| v_idx_700) v_v_3062_2)) (or (= (select |c_#memory_int| v_idx_701) 0) (<= .cse9 v_idx_701) (< v_idx_701 c_ULTIMATE.start_main_p1)) (or (= (select |c_#memory_int| v_idx_706) v_v_3068_2) (< v_idx_706 .cse10)) (<= .cse9 c_ULTIMATE.start_main_p2) (or (< v_idx_702 .cse9) (<= c_ULTIMATE.start_main_p2 v_idx_702) (= (select |c_#memory_int| v_idx_702) v_v_3064_2)) (or (< v_idx_705 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_705) v_v_3067_2) (<= .cse10 v_idx_705)) (<= v_v_3065_2 0)))))) is different from false [2019-01-08 14:37:26,051 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_720 Int) (v_idx_714 Int) (v_idx_717 Int) (v_idx_718 Int) (v_idx_715 Int) (v_idx_716 Int) (v_idx_719 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_v_3066_2 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_b_255_4 Int) (v_b_254_4 Int) (v_v_3062_2 Int) (v_b_257_4 Int) (v_b_256_4 Int)) (let ((.cse1 (+ v_b_254_4 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ v_b_256_4 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_714) (= (select |c_#memory_int| v_idx_714) v_v_3062_2)) (<= .cse0 v_b_254_4) (or (< v_idx_720 v_b_257_4) (= (select |c_#memory_int| v_idx_720) v_v_3068_2)) (<= 0 (* 2 v_v_3067_2)) (<= v_b_255_4 .cse1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_257_4) (<= .cse2 v_b_257_4) (or (<= .cse0 v_idx_715) (< v_idx_715 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_715) 0)) (<= (* 2 v_v_3065_2) 0) (<= v_b_255_4 v_b_256_4) (<= v_v_3065_2 v_v_3067_2) (<= .cse1 v_b_255_4) (or (< v_idx_718 v_b_255_4) (<= v_b_256_4 v_idx_718) (= (select |c_#memory_int| v_idx_718) v_v_3066_2)) (<= .cse1 v_b_256_4) (<= 0 v_v_3067_2) (or (= (select |c_#memory_int| v_idx_719) v_v_3067_2) (< v_idx_719 v_b_256_4) (<= v_b_257_4 v_idx_719)) (or (< v_idx_716 .cse0) (= (select |c_#memory_int| v_idx_716) v_v_3064_2) (<= v_b_254_4 v_idx_716)) (<= (+ v_b_254_4 2) v_b_257_4) (or (<= v_b_255_4 v_idx_717) (= (select |c_#memory_int| v_idx_717) v_v_3065_2) (< v_idx_717 v_b_254_4)) (<= v_b_257_4 .cse2) (<= (+ v_b_255_4 1) v_b_257_4) (<= .cse3 v_b_255_4) (<= v_v_3065_2 0) (<= .cse3 v_b_256_4))))) (forall ((v_idx_710 Int) (v_idx_713 Int) (v_idx_711 Int) (v_idx_712 Int) (v_idx_707 Int) (v_idx_708 Int) (v_idx_709 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_v_3066_2 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_b_255_4 Int) (v_b_254_4 Int) (v_v_3062_2 Int)) (let ((.cse6 (+ c_ULTIMATE.start_main_p3 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ v_b_254_4 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 2))) (and (<= .cse4 v_b_254_4) (<= .cse5 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_3067_2)) (or (= (select |c_#memory_int| v_idx_712) v_v_3067_2) (<= .cse6 v_idx_712) (< v_idx_712 c_ULTIMATE.start_main_p3)) (<= v_b_255_4 .cse7) (or (= (select |c_#memory_int| v_idx_713) v_v_3068_2) (< v_idx_713 .cse6)) (<= v_b_255_4 c_ULTIMATE.start_main_p3) (<= (* 2 v_v_3065_2) 0) (<= v_v_3065_2 v_v_3067_2) (<= .cse7 v_b_255_4) (or (= (select |c_#memory_int| v_idx_708) 0) (<= .cse4 v_idx_708) (< v_idx_708 c_ULTIMATE.start_main_p1)) (<= 0 v_v_3067_2) (or (= (select |c_#memory_int| v_idx_707) v_v_3062_2) (<= c_ULTIMATE.start_main_p1 v_idx_707)) (or (<= v_b_254_4 v_idx_709) (= (select |c_#memory_int| v_idx_709) v_v_3064_2) (< v_idx_709 .cse4)) (<= .cse7 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_711) v_v_3066_2) (<= c_ULTIMATE.start_main_p3 v_idx_711) (< v_idx_711 v_b_255_4)) (<= .cse5 v_b_255_4) (or (<= v_b_255_4 v_idx_710) (< v_idx_710 v_b_254_4) (= (select |c_#memory_int| v_idx_710) v_v_3065_2)) (<= v_v_3065_2 0)))))) is different from false [2019-01-08 14:37:31,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:37:31,443 INFO L93 Difference]: Finished difference Result 21 states and 57 transitions. [2019-01-08 14:37:31,443 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-08 14:37:31,444 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-08 14:37:31,444 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:37:31,444 INFO L225 Difference]: With dead ends: 21 [2019-01-08 14:37:31,444 INFO L226 Difference]: Without dead ends: 20 [2019-01-08 14:37:31,445 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.7s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-08 14:37:31,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-01-08 14:37:31,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 17. [2019-01-08 14:37:31,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2019-01-08 14:37:31,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 47 transitions. [2019-01-08 14:37:31,459 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 47 transitions. Word has length 4 [2019-01-08 14:37:31,459 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:37:31,460 INFO L480 AbstractCegarLoop]: Abstraction has 17 states and 47 transitions. [2019-01-08 14:37:31,460 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-08 14:37:31,460 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 47 transitions. [2019-01-08 14:37:31,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-08 14:37:31,460 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:37:31,460 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-08 14:37:31,460 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:37:31,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:37:31,461 INFO L82 PathProgramCache]: Analyzing trace with hash 935566, now seen corresponding path program 1 times [2019-01-08 14:37:31,461 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:37:31,461 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:37:31,462 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:37:31,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:37:31,462 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:37:31,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:37:31,517 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:37:31,518 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:37:31,518 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:37:31,518 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-08 14:37:31,518 INFO L207 CegarAbsIntRunner]: [0], [12], [16], [17] [2019-01-08 14:37:31,519 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:37:31,519 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:37:36,743 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:37:36,743 INFO L272 AbstractInterpreter]: Visited 4 different actions 16 times. Merged at 2 different actions 8 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:37:36,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:37:36,744 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:37:37,019 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 57.14% of their original sizes. [2019-01-08 14:37:37,019 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:37:39,392 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_820 Int) (v_idx_823 Int) (v_idx_824 Int) (v_idx_821 Int) (v_idx_822 Int) (v_idx_825 Int) (v_idx_826 Int)) (exists ((v_v_1678_7 Int) (v_v_1677_8 Int) (v_v_1679_7 Int) (v_v_1675_8 Int) (v_v_1673_7 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 v_v_1678_7) (or (= (select |c_#memory_int| v_idx_823) 0) (<= .cse0 v_idx_823) (< v_idx_823 c_ULTIMATE.start_main_p2)) (or (= (select |c_#memory_int| v_idx_826) v_v_1679_7) (< v_idx_826 .cse1)) (<= 0 (* 2 v_v_1678_7)) (or (<= c_ULTIMATE.start_main_p2 v_idx_822) (< v_idx_822 .cse2) (= (select |c_#memory_int| v_idx_822) v_v_1675_8)) (or (< v_idx_821 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_821) (= (select |c_#memory_int| v_idx_821) 0)) (or (= (select |c_#memory_int| v_idx_824) v_v_1677_8) (<= c_ULTIMATE.start_main_p3 v_idx_824) (< v_idx_824 .cse0)) (<= .cse2 c_ULTIMATE.start_main_p2) (or (<= .cse1 v_idx_825) (= (select |c_#memory_int| v_idx_825) v_v_1678_7) (< v_idx_825 c_ULTIMATE.start_main_p3)) (<= .cse0 c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p1 v_idx_820) (= (select |c_#memory_int| v_idx_820) v_v_1673_7)))))) is different from false [2019-01-08 14:37:41,874 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_830 Int) (v_idx_831 Int) (v_idx_832 Int) (v_idx_833 Int) (v_idx_827 Int) (v_idx_828 Int) (v_idx_829 Int)) (exists ((v_v_1678_7 Int) (v_v_1677_8 Int) (v_v_1679_7 Int) (v_b_131_8 Int) (v_v_1675_8 Int) (v_b_130_8 Int) (v_v_1673_7 Int)) (let ((.cse1 (+ v_b_130_8 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= 0 v_v_1678_7) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_8) (or (< v_idx_833 v_b_131_8) (= (select |c_#memory_int| v_idx_833) v_v_1679_7)) (or (<= .cse0 v_idx_830) (= (select |c_#memory_int| v_idx_830) 0) (< v_idx_830 c_ULTIMATE.start_main_p2)) (or (<= v_b_131_8 v_idx_832) (< v_idx_832 v_b_130_8) (= (select |c_#memory_int| v_idx_832) v_v_1678_7)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_8) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_8) (<= v_b_131_8 .cse1) (or (< v_idx_831 .cse0) (<= v_b_130_8 v_idx_831) (= (select |c_#memory_int| v_idx_831) v_v_1677_8)) (<= 0 (* 2 v_v_1678_7)) (or (< v_idx_828 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_828) (= (select |c_#memory_int| v_idx_828) 0)) (<= .cse1 v_b_131_8) (<= .cse0 v_b_130_8) (or (= (select |c_#memory_int| v_idx_827) v_v_1673_7) (<= c_ULTIMATE.start_main_p1 v_idx_827)) (<= .cse2 c_ULTIMATE.start_main_p2) (or (<= c_ULTIMATE.start_main_p2 v_idx_829) (= (select |c_#memory_int| v_idx_829) v_v_1675_8) (< v_idx_829 .cse2)))))) is different from false [2019-01-08 14:37:44,216 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_840 Int) (v_idx_834 Int) (v_idx_835 Int) (v_idx_838 Int) (v_idx_839 Int) (v_idx_836 Int) (v_idx_837 Int)) (exists ((v_v_1677_8 Int) (v_v_1678_7 Int) (v_b_127_8 Int) (v_v_1679_7 Int) (v_b_131_8 Int) (v_v_1675_8 Int) (v_b_130_8 Int) (v_b_136_8 Int) (v_v_1673_7 Int)) (let ((.cse1 (+ v_b_136_8 1)) (.cse2 (+ v_b_130_8 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (<= 0 v_v_1678_7) (or (<= v_b_130_8 v_idx_838) (< v_idx_838 .cse0) (= (select |c_#memory_int| v_idx_838) v_v_1677_8)) (<= v_b_127_8 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_837) 0) (<= .cse0 v_idx_837) (< v_idx_837 c_ULTIMATE.start_main_p2)) (<= .cse1 v_b_127_8) (<= .cse1 c_ULTIMATE.start_main_p2) (or (< v_idx_835 v_b_136_8) (<= v_b_127_8 v_idx_835) (= (select |c_#memory_int| v_idx_835) 0)) (<= (+ v_b_136_8 2) v_b_130_8) (or (<= c_ULTIMATE.start_main_p2 v_idx_836) (< v_idx_836 v_b_127_8) (= (select |c_#memory_int| v_idx_836) v_v_1675_8)) (<= v_b_127_8 .cse1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_8) (<= v_b_131_8 .cse2) (or (= (select |c_#memory_int| v_idx_840) v_v_1679_7) (< v_idx_840 v_b_131_8)) (<= 0 (* 2 v_v_1678_7)) (or (< v_idx_839 v_b_130_8) (= (select |c_#memory_int| v_idx_839) v_v_1678_7) (<= v_b_131_8 v_idx_839)) (<= .cse2 v_b_131_8) (<= .cse0 v_b_130_8) (<= (+ v_b_127_8 2) v_b_131_8) (<= (+ v_b_127_8 1) v_b_130_8) (or (<= v_b_136_8 v_idx_834) (= (select |c_#memory_int| v_idx_834) v_v_1673_7)) (<= (+ v_b_136_8 3) v_b_131_8))))) is different from false [2019-01-08 14:37:44,279 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-08 14:37:44,279 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:37:44,280 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:37:44,280 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [2] total 5 [2019-01-08 14:37:44,280 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:37:44,280 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-08 14:37:44,280 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-08 14:37:44,280 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:37:44,281 INFO L87 Difference]: Start difference. First operand 17 states and 47 transitions. Second operand 5 states. [2019-01-08 14:37:46,723 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_840 Int) (v_idx_834 Int) (v_idx_835 Int) (v_idx_838 Int) (v_idx_839 Int) (v_idx_836 Int) (v_idx_837 Int)) (exists ((v_v_1677_8 Int) (v_v_1678_7 Int) (v_b_127_8 Int) (v_v_1679_7 Int) (v_b_131_8 Int) (v_v_1675_8 Int) (v_b_130_8 Int) (v_b_136_8 Int) (v_v_1673_7 Int)) (let ((.cse1 (+ v_b_136_8 1)) (.cse2 (+ v_b_130_8 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (<= 0 v_v_1678_7) (or (<= v_b_130_8 v_idx_838) (< v_idx_838 .cse0) (= (select |c_#memory_int| v_idx_838) v_v_1677_8)) (<= v_b_127_8 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_837) 0) (<= .cse0 v_idx_837) (< v_idx_837 c_ULTIMATE.start_main_p2)) (<= .cse1 v_b_127_8) (<= .cse1 c_ULTIMATE.start_main_p2) (or (< v_idx_835 v_b_136_8) (<= v_b_127_8 v_idx_835) (= (select |c_#memory_int| v_idx_835) 0)) (<= (+ v_b_136_8 2) v_b_130_8) (or (<= c_ULTIMATE.start_main_p2 v_idx_836) (< v_idx_836 v_b_127_8) (= (select |c_#memory_int| v_idx_836) v_v_1675_8)) (<= v_b_127_8 .cse1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_8) (<= v_b_131_8 .cse2) (or (= (select |c_#memory_int| v_idx_840) v_v_1679_7) (< v_idx_840 v_b_131_8)) (<= 0 (* 2 v_v_1678_7)) (or (< v_idx_839 v_b_130_8) (= (select |c_#memory_int| v_idx_839) v_v_1678_7) (<= v_b_131_8 v_idx_839)) (<= .cse2 v_b_131_8) (<= .cse0 v_b_130_8) (<= (+ v_b_127_8 2) v_b_131_8) (<= (+ v_b_127_8 1) v_b_130_8) (or (<= v_b_136_8 v_idx_834) (= (select |c_#memory_int| v_idx_834) v_v_1673_7)) (<= (+ v_b_136_8 3) v_b_131_8))))) (forall ((v_idx_830 Int) (v_idx_831 Int) (v_idx_832 Int) (v_idx_833 Int) (v_idx_827 Int) (v_idx_828 Int) (v_idx_829 Int)) (exists ((v_v_1678_7 Int) (v_v_1677_8 Int) (v_v_1679_7 Int) (v_b_131_8 Int) (v_v_1675_8 Int) (v_b_130_8 Int) (v_v_1673_7 Int)) (let ((.cse4 (+ v_b_130_8 1)) (.cse3 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1))) (and (<= 0 v_v_1678_7) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_8) (or (< v_idx_833 v_b_131_8) (= (select |c_#memory_int| v_idx_833) v_v_1679_7)) (or (<= .cse3 v_idx_830) (= (select |c_#memory_int| v_idx_830) 0) (< v_idx_830 c_ULTIMATE.start_main_p2)) (or (<= v_b_131_8 v_idx_832) (< v_idx_832 v_b_130_8) (= (select |c_#memory_int| v_idx_832) v_v_1678_7)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_8) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_8) (<= v_b_131_8 .cse4) (or (< v_idx_831 .cse3) (<= v_b_130_8 v_idx_831) (= (select |c_#memory_int| v_idx_831) v_v_1677_8)) (<= 0 (* 2 v_v_1678_7)) (or (< v_idx_828 c_ULTIMATE.start_main_p1) (<= .cse5 v_idx_828) (= (select |c_#memory_int| v_idx_828) 0)) (<= .cse4 v_b_131_8) (<= .cse3 v_b_130_8) (or (= (select |c_#memory_int| v_idx_827) v_v_1673_7) (<= c_ULTIMATE.start_main_p1 v_idx_827)) (<= .cse5 c_ULTIMATE.start_main_p2) (or (<= c_ULTIMATE.start_main_p2 v_idx_829) (= (select |c_#memory_int| v_idx_829) v_v_1675_8) (< v_idx_829 .cse5)))))) (forall ((v_idx_820 Int) (v_idx_823 Int) (v_idx_824 Int) (v_idx_821 Int) (v_idx_822 Int) (v_idx_825 Int) (v_idx_826 Int)) (exists ((v_v_1678_7 Int) (v_v_1677_8 Int) (v_v_1679_7 Int) (v_v_1675_8 Int) (v_v_1673_7 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ c_ULTIMATE.start_main_p3 1)) (.cse6 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 v_v_1678_7) (or (= (select |c_#memory_int| v_idx_823) 0) (<= .cse6 v_idx_823) (< v_idx_823 c_ULTIMATE.start_main_p2)) (or (= (select |c_#memory_int| v_idx_826) v_v_1679_7) (< v_idx_826 .cse7)) (<= 0 (* 2 v_v_1678_7)) (or (<= c_ULTIMATE.start_main_p2 v_idx_822) (< v_idx_822 .cse8) (= (select |c_#memory_int| v_idx_822) v_v_1675_8)) (or (< v_idx_821 c_ULTIMATE.start_main_p1) (<= .cse8 v_idx_821) (= (select |c_#memory_int| v_idx_821) 0)) (or (= (select |c_#memory_int| v_idx_824) v_v_1677_8) (<= c_ULTIMATE.start_main_p3 v_idx_824) (< v_idx_824 .cse6)) (<= .cse8 c_ULTIMATE.start_main_p2) (or (<= .cse7 v_idx_825) (= (select |c_#memory_int| v_idx_825) v_v_1678_7) (< v_idx_825 c_ULTIMATE.start_main_p3)) (<= .cse6 c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p1 v_idx_820) (= (select |c_#memory_int| v_idx_820) v_v_1673_7))))))) is different from false [2019-01-08 14:38:01,203 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_840 Int) (v_idx_834 Int) (v_idx_835 Int) (v_idx_838 Int) (v_idx_839 Int) (v_idx_836 Int) (v_idx_837 Int)) (exists ((v_v_1677_8 Int) (v_v_1678_7 Int) (v_b_127_8 Int) (v_v_1679_7 Int) (v_b_131_8 Int) (v_v_1675_8 Int) (v_b_130_8 Int) (v_b_136_8 Int) (v_v_1673_7 Int)) (let ((.cse1 (+ v_b_136_8 1)) (.cse2 (+ v_b_130_8 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (<= 0 v_v_1678_7) (or (<= v_b_130_8 v_idx_838) (< v_idx_838 .cse0) (= (select |c_#memory_int| v_idx_838) v_v_1677_8)) (<= v_b_127_8 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_837) 0) (<= .cse0 v_idx_837) (< v_idx_837 c_ULTIMATE.start_main_p2)) (<= .cse1 v_b_127_8) (<= .cse1 c_ULTIMATE.start_main_p2) (or (< v_idx_835 v_b_136_8) (<= v_b_127_8 v_idx_835) (= (select |c_#memory_int| v_idx_835) 0)) (<= (+ v_b_136_8 2) v_b_130_8) (or (<= c_ULTIMATE.start_main_p2 v_idx_836) (< v_idx_836 v_b_127_8) (= (select |c_#memory_int| v_idx_836) v_v_1675_8)) (<= v_b_127_8 .cse1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_8) (<= v_b_131_8 .cse2) (or (= (select |c_#memory_int| v_idx_840) v_v_1679_7) (< v_idx_840 v_b_131_8)) (<= 0 (* 2 v_v_1678_7)) (or (< v_idx_839 v_b_130_8) (= (select |c_#memory_int| v_idx_839) v_v_1678_7) (<= v_b_131_8 v_idx_839)) (<= .cse2 v_b_131_8) (<= .cse0 v_b_130_8) (<= (+ v_b_127_8 2) v_b_131_8) (<= (+ v_b_127_8 1) v_b_130_8) (or (<= v_b_136_8 v_idx_834) (= (select |c_#memory_int| v_idx_834) v_v_1673_7)) (<= (+ v_b_136_8 3) v_b_131_8))))) (forall ((v_idx_830 Int) (v_idx_831 Int) (v_idx_832 Int) (v_idx_833 Int) (v_idx_827 Int) (v_idx_828 Int) (v_idx_829 Int)) (exists ((v_v_1678_7 Int) (v_v_1677_8 Int) (v_v_1679_7 Int) (v_b_131_8 Int) (v_v_1675_8 Int) (v_b_130_8 Int) (v_v_1673_7 Int)) (let ((.cse4 (+ v_b_130_8 1)) (.cse3 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1))) (and (<= 0 v_v_1678_7) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_8) (or (< v_idx_833 v_b_131_8) (= (select |c_#memory_int| v_idx_833) v_v_1679_7)) (or (<= .cse3 v_idx_830) (= (select |c_#memory_int| v_idx_830) 0) (< v_idx_830 c_ULTIMATE.start_main_p2)) (or (<= v_b_131_8 v_idx_832) (< v_idx_832 v_b_130_8) (= (select |c_#memory_int| v_idx_832) v_v_1678_7)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_8) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_8) (<= v_b_131_8 .cse4) (or (< v_idx_831 .cse3) (<= v_b_130_8 v_idx_831) (= (select |c_#memory_int| v_idx_831) v_v_1677_8)) (<= 0 (* 2 v_v_1678_7)) (or (< v_idx_828 c_ULTIMATE.start_main_p1) (<= .cse5 v_idx_828) (= (select |c_#memory_int| v_idx_828) 0)) (<= .cse4 v_b_131_8) (<= .cse3 v_b_130_8) (or (= (select |c_#memory_int| v_idx_827) v_v_1673_7) (<= c_ULTIMATE.start_main_p1 v_idx_827)) (<= .cse5 c_ULTIMATE.start_main_p2) (or (<= c_ULTIMATE.start_main_p2 v_idx_829) (= (select |c_#memory_int| v_idx_829) v_v_1675_8) (< v_idx_829 .cse5))))))) is different from false [2019-01-08 14:38:03,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:38:03,861 INFO L93 Difference]: Finished difference Result 20 states and 53 transitions. [2019-01-08 14:38:03,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-08 14:38:03,861 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-08 14:38:03,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:38:03,861 INFO L225 Difference]: With dead ends: 20 [2019-01-08 14:38:03,861 INFO L226 Difference]: Without dead ends: 19 [2019-01-08 14:38:03,862 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.2s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-08 14:38:03,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2019-01-08 14:38:03,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 18. [2019-01-08 14:38:03,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2019-01-08 14:38:03,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 51 transitions. [2019-01-08 14:38:03,881 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 51 transitions. Word has length 4 [2019-01-08 14:38:03,881 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:38:03,881 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 51 transitions. [2019-01-08 14:38:03,881 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-08 14:38:03,881 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 51 transitions. [2019-01-08 14:38:03,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-08 14:38:03,882 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:38:03,882 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-08 14:38:03,882 INFO L423 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:38:03,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:38:03,882 INFO L82 PathProgramCache]: Analyzing trace with hash 935378, now seen corresponding path program 2 times [2019-01-08 14:38:03,883 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:38:03,883 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:03,883 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:38:03,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:03,884 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:38:03,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:38:04,038 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:38:04,038 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:38:04,038 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:38:04,039 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-08 14:38:04,039 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-08 14:38:04,039 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:38:04,039 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-08 14:38:04,047 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-08 14:38:04,047 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-08 14:38:04,054 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-08 14:38:04,055 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-08 14:38:04,055 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-08 14:38:04,058 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-08 14:38:04,067 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:04,067 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-08 14:38:04,070 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:04,072 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:04,073 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-08 14:38:04,074 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-08 14:38:04,088 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:38:04,094 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:38:04,105 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:38:04,105 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:19, output treesize:22 [2019-01-08 14:38:04,124 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:04,125 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:04,126 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:04,127 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:04,128 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-08 14:38:04,129 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:38:04,158 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:38:04,159 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-08 14:38:04,182 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:04,183 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:04,184 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:04,191 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:04,192 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:04,193 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:04,193 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 48 [2019-01-08 14:38:04,194 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:38:04,240 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:38:04,241 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-08 14:38:04,262 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:38:04,262 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-08 14:38:04,294 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:38:04,315 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-08 14:38:04,315 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 9 [2019-01-08 14:38:04,315 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-08 14:38:04,315 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-01-08 14:38:04,316 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-01-08 14:38:04,316 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=66, Unknown=0, NotChecked=0, Total=110 [2019-01-08 14:38:04,316 INFO L87 Difference]: Start difference. First operand 18 states and 51 transitions. Second operand 8 states. [2019-01-08 14:38:04,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:38:04,625 INFO L93 Difference]: Finished difference Result 37 states and 88 transitions. [2019-01-08 14:38:04,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-08 14:38:04,626 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 4 [2019-01-08 14:38:04,626 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:38:04,627 INFO L225 Difference]: With dead ends: 37 [2019-01-08 14:38:04,627 INFO L226 Difference]: Without dead ends: 36 [2019-01-08 14:38:04,628 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=62, Invalid=94, Unknown=0, NotChecked=0, Total=156 [2019-01-08 14:38:04,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-01-08 14:38:04,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 20. [2019-01-08 14:38:04,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-01-08 14:38:04,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 59 transitions. [2019-01-08 14:38:04,652 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 59 transitions. Word has length 4 [2019-01-08 14:38:04,652 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:38:04,652 INFO L480 AbstractCegarLoop]: Abstraction has 20 states and 59 transitions. [2019-01-08 14:38:04,652 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-01-08 14:38:04,652 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 59 transitions. [2019-01-08 14:38:04,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-08 14:38:04,653 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:38:04,653 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-08 14:38:04,653 INFO L423 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:38:04,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:38:04,653 INFO L82 PathProgramCache]: Analyzing trace with hash 28823850, now seen corresponding path program 1 times [2019-01-08 14:38:04,654 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:38:04,654 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:04,654 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-08 14:38:04,655 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:04,655 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:38:04,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:38:04,733 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:38:04,734 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:38:04,734 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:38:04,734 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-08 14:38:04,735 INFO L207 CegarAbsIntRunner]: [0], [6], [16], [18], [19] [2019-01-08 14:38:04,736 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:38:04,736 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:38:11,435 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:38:11,436 INFO L272 AbstractInterpreter]: Visited 5 different actions 21 times. Merged at 3 different actions 12 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:38:11,436 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:38:11,436 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:38:11,790 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 53.57% of their original sizes. [2019-01-08 14:38:11,790 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:38:14,179 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_973 Int) (v_idx_974 Int) (v_idx_977 Int) (v_idx_978 Int) (v_idx_975 Int) (v_idx_976 Int) (v_idx_979 Int)) (exists ((v_v_1852_8 Int) (v_v_1853_7 Int) (v_v_1856_8 Int) (v_v_1854_7 Int) (v_v_1858_8 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_975 .cse0) (<= c_ULTIMATE.start_main_p2 v_idx_975) (= (select |c_#memory_int| v_idx_975) v_v_1854_7)) (or (<= c_ULTIMATE.start_main_p1 v_idx_973) (= (select |c_#memory_int| v_idx_973) v_v_1852_8)) (or (< v_idx_976 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_976) (= (select |c_#memory_int| v_idx_976) 0)) (<= 0 v_v_1853_7) (or (< v_idx_979 .cse2) (= (select |c_#memory_int| v_idx_979) v_v_1858_8)) (or (= (select |c_#memory_int| v_idx_977) v_v_1856_8) (<= c_ULTIMATE.start_main_p3 v_idx_977) (< v_idx_977 .cse1)) (<= .cse0 c_ULTIMATE.start_main_p2) (or (= 0 (select |c_#memory_int| v_idx_978)) (<= .cse2 v_idx_978) (< v_idx_978 c_ULTIMATE.start_main_p3)) (or (= (select |c_#memory_int| v_idx_974) v_v_1853_7) (<= .cse0 v_idx_974) (< v_idx_974 c_ULTIMATE.start_main_p1)) (<= .cse1 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_1853_7)))))) is different from false [2019-01-08 14:38:16,720 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_984 Int) (v_idx_985 Int) (v_idx_982 Int) (v_idx_983 Int) (v_idx_986 Int) (v_idx_980 Int) (v_idx_981 Int)) (exists ((v_v_1852_8 Int) (v_v_1853_7 Int) (v_v_1856_8 Int) (v_v_1854_7 Int) (v_v_1858_8 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p1 v_idx_980) (= (select |c_#memory_int| v_idx_980) v_v_1852_8)) (or (< v_idx_982 .cse0) (= (select |c_#memory_int| v_idx_982) v_v_1854_7) (<= c_ULTIMATE.start_main_p2 v_idx_982)) (or (= (select |c_#memory_int| v_idx_983) 0) (< v_idx_983 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_983)) (or (<= c_ULTIMATE.start_main_p3 v_idx_984) (< v_idx_984 .cse1) (= (select |c_#memory_int| v_idx_984) v_v_1856_8)) (or (= (select |c_#memory_int| v_idx_981) v_v_1853_7) (<= .cse0 v_idx_981) (< v_idx_981 c_ULTIMATE.start_main_p1)) (<= 0 v_v_1853_7) (or (< v_idx_986 .cse2) (= (select |c_#memory_int| v_idx_986) v_v_1858_8)) (<= .cse0 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_985) 0) (<= .cse2 v_idx_985) (< v_idx_985 c_ULTIMATE.start_main_p3)) (<= .cse1 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_1853_7)))))) is different from false [2019-01-08 14:38:19,431 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_993 Int) (v_idx_988 Int) (v_idx_989 Int) (v_idx_987 Int) (v_idx_991 Int) (v_idx_992 Int) (v_idx_990 Int)) (exists ((v_v_2333_4 Int) (v_v_1852_8 Int) (v_v_1856_8 Int) (v_v_1854_7 Int) (v_b_156_9 Int) (v_b_143_9 Int) (v_v_1858_8 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_156_9 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse0 v_b_143_9) (<= 0 (* 2 v_v_2333_4)) (<= (+ v_b_156_9 2) c_ULTIMATE.start_main_p3) (<= v_b_143_9 .cse0) (<= 0 v_v_2333_4) (or (= (select |c_#memory_int| v_idx_990) 0) (<= .cse1 v_idx_990) (< v_idx_990 c_ULTIMATE.start_main_p2)) (or (< v_idx_991 .cse1) (<= c_ULTIMATE.start_main_p3 v_idx_991) (= (select |c_#memory_int| v_idx_991) v_v_1856_8)) (<= .cse1 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_993) v_v_1858_8) (< v_idx_993 .cse2)) (<= (+ v_b_143_9 1) c_ULTIMATE.start_main_p3) (or (< v_idx_988 v_b_156_9) (<= v_b_143_9 v_idx_988) (= (select |c_#memory_int| v_idx_988) v_v_2333_4)) (<= v_b_143_9 c_ULTIMATE.start_main_p2) (<= .cse0 c_ULTIMATE.start_main_p2) (or (< v_idx_989 v_b_143_9) (= (select |c_#memory_int| v_idx_989) v_v_1854_7) (<= c_ULTIMATE.start_main_p2 v_idx_989)) (or (<= v_b_156_9 v_idx_987) (= (select |c_#memory_int| v_idx_987) v_v_1852_8)) (or (<= .cse2 v_idx_992) (= (select |c_#memory_int| v_idx_992) 0) (< v_idx_992 c_ULTIMATE.start_main_p3)))))) is different from false [2019-01-08 14:38:21,804 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_995 Int) (v_idx_996 Int) (v_idx_994 Int) (v_idx_999 Int) (v_idx_1000 Int) (v_idx_997 Int) (v_idx_998 Int)) (exists ((v_v_2333_4 Int) (v_v_1852_8 Int) (v_b_170_9 Int) (v_v_1856_8 Int) (v_v_1854_7 Int) (v_b_145_9 Int) (v_b_156_9 Int) (v_b_143_9 Int) (v_v_1858_8 Int)) (let ((.cse1 (+ v_b_156_9 2)) (.cse0 (+ v_b_156_9 1)) (.cse3 (+ v_b_143_9 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse4 (+ v_b_170_9 1))) (and (<= .cse0 v_b_143_9) (<= 0 (* 2 v_v_2333_4)) (or (<= v_b_156_9 v_idx_994) (= (select |c_#memory_int| v_idx_994) v_v_1852_8)) (<= .cse1 c_ULTIMATE.start_main_p3) (<= v_b_143_9 .cse0) (or (= 0 (select |c_#memory_int| v_idx_999)) (<= .cse2 v_idx_999) (< v_idx_999 c_ULTIMATE.start_main_p3)) (<= .cse1 v_b_145_9) (<= .cse0 v_b_170_9) (<= v_b_143_9 v_b_170_9) (<= 0 v_v_2333_4) (or (= (select |c_#memory_int| v_idx_997) 0) (< v_idx_997 v_b_170_9) (<= v_b_145_9 v_idx_997)) (<= .cse3 c_ULTIMATE.start_main_p3) (<= .cse4 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_995) v_v_2333_4) (<= v_b_143_9 v_idx_995) (< v_idx_995 v_b_156_9)) (<= .cse3 v_b_145_9) (or (<= c_ULTIMATE.start_main_p3 v_idx_998) (= (select |c_#memory_int| v_idx_998) v_v_1856_8) (< v_idx_998 v_b_145_9)) (or (= (select |c_#memory_int| v_idx_1000) v_v_1858_8) (< v_idx_1000 .cse2)) (<= v_b_145_9 c_ULTIMATE.start_main_p3) (<= .cse4 v_b_145_9) (<= v_b_145_9 .cse4) (or (<= v_b_170_9 v_idx_996) (< v_idx_996 v_b_143_9) (= (select |c_#memory_int| v_idx_996) v_v_1854_7)))))) is different from false [2019-01-08 14:38:21,857 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-08 14:38:21,857 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:38:21,857 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:38:21,858 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [2] total 6 [2019-01-08 14:38:21,858 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:38:21,858 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-08 14:38:21,858 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-08 14:38:21,858 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-08 14:38:21,858 INFO L87 Difference]: Start difference. First operand 20 states and 59 transitions. Second operand 6 states. [2019-01-08 14:38:24,341 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_995 Int) (v_idx_996 Int) (v_idx_994 Int) (v_idx_999 Int) (v_idx_1000 Int) (v_idx_997 Int) (v_idx_998 Int)) (exists ((v_v_2333_4 Int) (v_v_1852_8 Int) (v_b_170_9 Int) (v_v_1856_8 Int) (v_v_1854_7 Int) (v_b_145_9 Int) (v_b_156_9 Int) (v_b_143_9 Int) (v_v_1858_8 Int)) (let ((.cse1 (+ v_b_156_9 2)) (.cse0 (+ v_b_156_9 1)) (.cse3 (+ v_b_143_9 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse4 (+ v_b_170_9 1))) (and (<= .cse0 v_b_143_9) (<= 0 (* 2 v_v_2333_4)) (or (<= v_b_156_9 v_idx_994) (= (select |c_#memory_int| v_idx_994) v_v_1852_8)) (<= .cse1 c_ULTIMATE.start_main_p3) (<= v_b_143_9 .cse0) (or (= 0 (select |c_#memory_int| v_idx_999)) (<= .cse2 v_idx_999) (< v_idx_999 c_ULTIMATE.start_main_p3)) (<= .cse1 v_b_145_9) (<= .cse0 v_b_170_9) (<= v_b_143_9 v_b_170_9) (<= 0 v_v_2333_4) (or (= (select |c_#memory_int| v_idx_997) 0) (< v_idx_997 v_b_170_9) (<= v_b_145_9 v_idx_997)) (<= .cse3 c_ULTIMATE.start_main_p3) (<= .cse4 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_995) v_v_2333_4) (<= v_b_143_9 v_idx_995) (< v_idx_995 v_b_156_9)) (<= .cse3 v_b_145_9) (or (<= c_ULTIMATE.start_main_p3 v_idx_998) (= (select |c_#memory_int| v_idx_998) v_v_1856_8) (< v_idx_998 v_b_145_9)) (or (= (select |c_#memory_int| v_idx_1000) v_v_1858_8) (< v_idx_1000 .cse2)) (<= v_b_145_9 c_ULTIMATE.start_main_p3) (<= .cse4 v_b_145_9) (<= v_b_145_9 .cse4) (or (<= v_b_170_9 v_idx_996) (< v_idx_996 v_b_143_9) (= (select |c_#memory_int| v_idx_996) v_v_1854_7)))))) (forall ((v_idx_984 Int) (v_idx_985 Int) (v_idx_982 Int) (v_idx_983 Int) (v_idx_986 Int) (v_idx_980 Int) (v_idx_981 Int)) (exists ((v_v_1852_8 Int) (v_v_1853_7 Int) (v_v_1856_8 Int) (v_v_1854_7 Int) (v_v_1858_8 Int)) (let ((.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ c_ULTIMATE.start_main_p3 1)) (.cse6 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p1 v_idx_980) (= (select |c_#memory_int| v_idx_980) v_v_1852_8)) (or (< v_idx_982 .cse5) (= (select |c_#memory_int| v_idx_982) v_v_1854_7) (<= c_ULTIMATE.start_main_p2 v_idx_982)) (or (= (select |c_#memory_int| v_idx_983) 0) (< v_idx_983 c_ULTIMATE.start_main_p2) (<= .cse6 v_idx_983)) (or (<= c_ULTIMATE.start_main_p3 v_idx_984) (< v_idx_984 .cse6) (= (select |c_#memory_int| v_idx_984) v_v_1856_8)) (or (= (select |c_#memory_int| v_idx_981) v_v_1853_7) (<= .cse5 v_idx_981) (< v_idx_981 c_ULTIMATE.start_main_p1)) (<= 0 v_v_1853_7) (or (< v_idx_986 .cse7) (= (select |c_#memory_int| v_idx_986) v_v_1858_8)) (<= .cse5 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_985) 0) (<= .cse7 v_idx_985) (< v_idx_985 c_ULTIMATE.start_main_p3)) (<= .cse6 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_1853_7)))))) (forall ((v_idx_993 Int) (v_idx_988 Int) (v_idx_989 Int) (v_idx_987 Int) (v_idx_991 Int) (v_idx_992 Int) (v_idx_990 Int)) (exists ((v_v_2333_4 Int) (v_v_1852_8 Int) (v_v_1856_8 Int) (v_v_1854_7 Int) (v_b_156_9 Int) (v_b_143_9 Int) (v_v_1858_8 Int)) (let ((.cse9 (+ c_ULTIMATE.start_main_p2 1)) (.cse8 (+ v_b_156_9 1)) (.cse10 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse8 v_b_143_9) (<= 0 (* 2 v_v_2333_4)) (<= (+ v_b_156_9 2) c_ULTIMATE.start_main_p3) (<= v_b_143_9 .cse8) (<= 0 v_v_2333_4) (or (= (select |c_#memory_int| v_idx_990) 0) (<= .cse9 v_idx_990) (< v_idx_990 c_ULTIMATE.start_main_p2)) (or (< v_idx_991 .cse9) (<= c_ULTIMATE.start_main_p3 v_idx_991) (= (select |c_#memory_int| v_idx_991) v_v_1856_8)) (<= .cse9 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_993) v_v_1858_8) (< v_idx_993 .cse10)) (<= (+ v_b_143_9 1) c_ULTIMATE.start_main_p3) (or (< v_idx_988 v_b_156_9) (<= v_b_143_9 v_idx_988) (= (select |c_#memory_int| v_idx_988) v_v_2333_4)) (<= v_b_143_9 c_ULTIMATE.start_main_p2) (<= .cse8 c_ULTIMATE.start_main_p2) (or (< v_idx_989 v_b_143_9) (= (select |c_#memory_int| v_idx_989) v_v_1854_7) (<= c_ULTIMATE.start_main_p2 v_idx_989)) (or (<= v_b_156_9 v_idx_987) (= (select |c_#memory_int| v_idx_987) v_v_1852_8)) (or (<= .cse10 v_idx_992) (= (select |c_#memory_int| v_idx_992) 0) (< v_idx_992 c_ULTIMATE.start_main_p3)))))) (forall ((v_idx_973 Int) (v_idx_974 Int) (v_idx_977 Int) (v_idx_978 Int) (v_idx_975 Int) (v_idx_976 Int) (v_idx_979 Int)) (exists ((v_v_1852_8 Int) (v_v_1853_7 Int) (v_v_1856_8 Int) (v_v_1854_7 Int) (v_v_1858_8 Int)) (let ((.cse13 (+ c_ULTIMATE.start_main_p3 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 1)) (.cse12 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_975 .cse11) (<= c_ULTIMATE.start_main_p2 v_idx_975) (= (select |c_#memory_int| v_idx_975) v_v_1854_7)) (or (<= c_ULTIMATE.start_main_p1 v_idx_973) (= (select |c_#memory_int| v_idx_973) v_v_1852_8)) (or (< v_idx_976 c_ULTIMATE.start_main_p2) (<= .cse12 v_idx_976) (= (select |c_#memory_int| v_idx_976) 0)) (<= 0 v_v_1853_7) (or (< v_idx_979 .cse13) (= (select |c_#memory_int| v_idx_979) v_v_1858_8)) (or (= (select |c_#memory_int| v_idx_977) v_v_1856_8) (<= c_ULTIMATE.start_main_p3 v_idx_977) (< v_idx_977 .cse12)) (<= .cse11 c_ULTIMATE.start_main_p2) (or (= 0 (select |c_#memory_int| v_idx_978)) (<= .cse13 v_idx_978) (< v_idx_978 c_ULTIMATE.start_main_p3)) (or (= (select |c_#memory_int| v_idx_974) v_v_1853_7) (<= .cse11 v_idx_974) (< v_idx_974 c_ULTIMATE.start_main_p1)) (<= .cse12 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_1853_7))))))) is different from false [2019-01-08 14:38:43,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:38:43,099 INFO L93 Difference]: Finished difference Result 23 states and 61 transitions. [2019-01-08 14:38:43,099 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-08 14:38:43,099 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2019-01-08 14:38:43,099 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:38:43,099 INFO L225 Difference]: With dead ends: 23 [2019-01-08 14:38:43,100 INFO L226 Difference]: Without dead ends: 20 [2019-01-08 14:38:43,100 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.4s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-08 14:38:43,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-01-08 14:38:43,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-01-08 14:38:43,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-01-08 14:38:43,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 58 transitions. [2019-01-08 14:38:43,120 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 58 transitions. Word has length 5 [2019-01-08 14:38:43,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:38:43,120 INFO L480 AbstractCegarLoop]: Abstraction has 20 states and 58 transitions. [2019-01-08 14:38:43,121 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-01-08 14:38:43,121 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 58 transitions. [2019-01-08 14:38:43,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-08 14:38:43,121 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:38:43,121 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1] [2019-01-08 14:38:43,122 INFO L423 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:38:43,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:38:43,122 INFO L82 PathProgramCache]: Analyzing trace with hash 28814176, now seen corresponding path program 2 times [2019-01-08 14:38:43,122 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:38:43,123 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:43,123 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:38:43,123 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:43,123 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:38:43,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:38:43,196 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2019-01-08 14:38:43,197 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-08 14:38:43,197 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-01-08 14:38:43,197 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:38:43,197 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:38:43,197 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:38:43,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-01-08 14:38:43,198 INFO L87 Difference]: Start difference. First operand 20 states and 58 transitions. Second operand 4 states. [2019-01-08 14:38:43,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:38:43,259 INFO L93 Difference]: Finished difference Result 25 states and 65 transitions. [2019-01-08 14:38:43,260 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-08 14:38:43,260 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 5 [2019-01-08 14:38:43,260 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:38:43,261 INFO L225 Difference]: With dead ends: 25 [2019-01-08 14:38:43,261 INFO L226 Difference]: Without dead ends: 24 [2019-01-08 14:38:43,262 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-01-08 14:38:43,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2019-01-08 14:38:43,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 21. [2019-01-08 14:38:43,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-01-08 14:38:43,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 62 transitions. [2019-01-08 14:38:43,283 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 62 transitions. Word has length 5 [2019-01-08 14:38:43,283 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:38:43,283 INFO L480 AbstractCegarLoop]: Abstraction has 21 states and 62 transitions. [2019-01-08 14:38:43,283 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:38:43,283 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 62 transitions. [2019-01-08 14:38:43,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-08 14:38:43,284 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:38:43,284 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1] [2019-01-08 14:38:43,284 INFO L423 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:38:43,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:38:43,284 INFO L82 PathProgramCache]: Analyzing trace with hash 28813988, now seen corresponding path program 2 times [2019-01-08 14:38:43,284 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:38:43,285 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:43,285 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-08 14:38:43,285 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:43,285 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:38:43,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:38:43,395 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:38:43,395 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:38:43,396 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:38:43,396 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-08 14:38:43,396 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-08 14:38:43,396 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:38:43,396 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-08 14:38:43,406 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-08 14:38:43,407 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-08 14:38:43,413 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-01-08 14:38:43,413 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-08 14:38:43,414 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-08 14:38:43,426 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-08 14:38:43,434 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,435 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-08 14:38:43,474 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,475 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,476 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-08 14:38:43,477 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-08 14:38:43,487 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:38:43,495 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:38:43,505 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:38:43,506 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:19, output treesize:22 [2019-01-08 14:38:43,529 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,530 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,532 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,533 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,534 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 28 [2019-01-08 14:38:43,535 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:38:43,551 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:38:43,552 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-08 14:38:43,574 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,575 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,575 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,577 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,578 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,579 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,580 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 40 [2019-01-08 14:38:43,581 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:38:43,600 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:38:43,601 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-08 14:38:43,626 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,627 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,627 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,628 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,630 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,631 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:38:43,632 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 40 [2019-01-08 14:38:43,633 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:38:43,711 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:38:43,712 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-08 14:38:43,727 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:38:43,728 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-08 14:38:43,758 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 5 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:38:43,778 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-08 14:38:43,778 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 12 [2019-01-08 14:38:43,778 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-08 14:38:43,778 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-01-08 14:38:43,778 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-01-08 14:38:43,779 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=111, Unknown=0, NotChecked=0, Total=182 [2019-01-08 14:38:43,779 INFO L87 Difference]: Start difference. First operand 21 states and 62 transitions. Second operand 10 states. [2019-01-08 14:38:44,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:38:44,191 INFO L93 Difference]: Finished difference Result 55 states and 133 transitions. [2019-01-08 14:38:44,202 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-01-08 14:38:44,202 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 5 [2019-01-08 14:38:44,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:38:44,203 INFO L225 Difference]: With dead ends: 55 [2019-01-08 14:38:44,203 INFO L226 Difference]: Without dead ends: 54 [2019-01-08 14:38:44,203 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 58 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=81, Invalid=129, Unknown=0, NotChecked=0, Total=210 [2019-01-08 14:38:44,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-01-08 14:38:44,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 23. [2019-01-08 14:38:44,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23 states. [2019-01-08 14:38:44,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 70 transitions. [2019-01-08 14:38:44,230 INFO L78 Accepts]: Start accepts. Automaton has 23 states and 70 transitions. Word has length 5 [2019-01-08 14:38:44,230 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:38:44,230 INFO L480 AbstractCegarLoop]: Abstraction has 23 states and 70 transitions. [2019-01-08 14:38:44,231 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-01-08 14:38:44,231 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 70 transitions. [2019-01-08 14:38:44,231 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-08 14:38:44,231 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:38:44,231 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-08 14:38:44,232 INFO L423 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:38:44,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:38:44,232 INFO L82 PathProgramCache]: Analyzing trace with hash 28818020, now seen corresponding path program 1 times [2019-01-08 14:38:44,232 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:38:44,233 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:44,233 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-08 14:38:44,233 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:44,233 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:38:44,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:38:44,303 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:38:44,303 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:38:44,303 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:38:44,303 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-08 14:38:44,304 INFO L207 CegarAbsIntRunner]: [0], [6], [10], [16], [17] [2019-01-08 14:38:44,305 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:38:44,305 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:38:59,006 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:38:59,006 INFO L272 AbstractInterpreter]: Visited 5 different actions 37 times. Merged at 3 different actions 16 times. Widened at 2 different actions 6 times. Found 10 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-08 14:38:59,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:38:59,007 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:38:59,433 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 60.71% of their original sizes. [2019-01-08 14:38:59,434 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:39:04,779 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1137 Int) (v_idx_1136 Int) (v_idx_1135 Int) (v_idx_1134 Int) (v_idx_1133 Int) (v_idx_1139 Int) (v_idx_1138 Int)) (exists ((v_v_4531_2 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_v_4525_1 Int) (v_v_4526_1 Int)) (let ((.cse2 (+ v_b_338_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_1139 v_b_339_3) (= (select |c_#memory_int| v_idx_1139) v_v_4531_2)) (or (<= c_ULTIMATE.start_main_p2 v_idx_1135) (= (select |c_#memory_int| v_idx_1135) v_v_4527_1) (< v_idx_1135 .cse0)) (<= .cse1 v_b_338_3) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_338_3) (<= .cse2 v_b_339_3) (or (< v_idx_1138 v_b_338_3) (<= v_b_339_3 v_idx_1138) (= 0 (select |c_#memory_int| v_idx_1138))) (<= v_v_4528_2 0) (<= (* 2 v_v_4528_2) 0) (or (= (select |c_#memory_int| v_idx_1133) v_v_4525_1) (<= c_ULTIMATE.start_main_p1 v_idx_1133)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= v_b_339_3 .cse2) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_339_3) (or (= (select |c_#memory_int| v_idx_1137) v_v_4529_2) (< v_idx_1137 .cse1) (<= v_b_338_3 v_idx_1137)) (or (<= .cse0 v_idx_1134) (< v_idx_1134 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1134) v_v_4526_1)) (or (= (select |c_#memory_int| v_idx_1136) v_v_4528_2) (< v_idx_1136 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_1136)) (<= 0 v_v_4526_1) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_v_4528_2 v_v_4526_1) (<= 0 (* 2 v_v_4526_1)))))) is different from false [2019-01-08 14:39:07,150 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1146 Int) (v_idx_1145 Int) (v_idx_1144 Int) (v_idx_1143 Int) (v_idx_1142 Int) (v_idx_1141 Int) (v_idx_1140 Int)) (exists ((v_v_4531_2 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_v_4525_1 Int) (v_v_4526_1 Int)) (let ((.cse2 (+ v_b_338_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_1141 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1141) v_v_4526_1) (<= .cse0 v_idx_1141)) (<= .cse1 v_b_338_3) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_338_3) (<= .cse2 v_b_339_3) (<= v_v_4528_2 0) (<= (* 2 v_v_4528_2) 0) (or (< v_idx_1145 v_b_338_3) (= 0 (select |c_#memory_int| v_idx_1145)) (<= v_b_339_3 v_idx_1145)) (or (<= c_ULTIMATE.start_main_p1 v_idx_1140) (= (select |c_#memory_int| v_idx_1140) v_v_4525_1)) (or (< v_idx_1143 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_1143) (= (select |c_#memory_int| v_idx_1143) v_v_4528_2)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= v_b_339_3 .cse2) (or (<= c_ULTIMATE.start_main_p2 v_idx_1142) (= (select |c_#memory_int| v_idx_1142) v_v_4527_1) (< v_idx_1142 .cse0)) (or (= (select |c_#memory_int| v_idx_1146) v_v_4531_2) (< v_idx_1146 v_b_339_3)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_339_3) (or (<= v_b_338_3 v_idx_1144) (< v_idx_1144 .cse1) (= (select |c_#memory_int| v_idx_1144) v_v_4529_2)) (<= 0 v_v_4526_1) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_v_4528_2 v_v_4526_1) (<= 0 (* 2 v_v_4526_1)))))) is different from false [2019-01-08 14:39:09,322 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1148 Int) (v_idx_1147 Int) (v_idx_1153 Int) (v_idx_1152 Int) (v_idx_1151 Int) (v_idx_1150 Int) (v_idx_1149 Int)) (exists ((v_v_4531_2 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_v_4525_1 Int) (v_v_4526_1 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_338_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= (select |c_#memory_int| v_idx_1150) v_v_4528_2) (<= .cse0 v_idx_1150) (< v_idx_1150 c_ULTIMATE.start_main_p2)) (<= .cse0 v_b_338_3) (or (< v_idx_1149 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_1149) (= (select |c_#memory_int| v_idx_1149) v_v_4527_1)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_338_3) (<= .cse2 v_b_339_3) (<= v_v_4528_2 0) (or (<= v_b_338_3 v_idx_1151) (= (select |c_#memory_int| v_idx_1151) v_v_4529_2) (< v_idx_1151 .cse0)) (<= (* 2 v_v_4528_2) 0) (or (<= .cse1 v_idx_1148) (= (select |c_#memory_int| v_idx_1148) v_v_4526_1) (< v_idx_1148 c_ULTIMATE.start_main_p1)) (or (< v_idx_1153 v_b_339_3) (= (select |c_#memory_int| v_idx_1153) v_v_4531_2)) (or (<= v_b_339_3 v_idx_1152) (< v_idx_1152 v_b_338_3) (= (select |c_#memory_int| v_idx_1152) 0)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= v_b_339_3 .cse2) (or (= (select |c_#memory_int| v_idx_1147) v_v_4525_1) (<= c_ULTIMATE.start_main_p1 v_idx_1147)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_339_3) (<= 0 v_v_4526_1) (<= .cse1 c_ULTIMATE.start_main_p2) (<= v_v_4528_2 v_v_4526_1) (<= 0 (* 2 v_v_4526_1)))))) is different from false [2019-01-08 14:39:11,494 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1159 Int) (v_idx_1158 Int) (v_idx_1157 Int) (v_idx_1156 Int) (v_idx_1155 Int) (v_idx_1154 Int) (v_idx_1160 Int)) (exists ((v_v_4531_2 Int) (v_b_362_3 Int) (v_v_4887_2 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_b_335_3 Int) (v_v_4525_1 Int)) (let ((.cse1 (+ v_b_338_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_362_3 1))) (and (or (< v_idx_1156 v_b_335_3) (<= c_ULTIMATE.start_main_p2 v_idx_1156) (= (select |c_#memory_int| v_idx_1156) v_v_4527_1)) (or (= (select |c_#memory_int| v_idx_1160) v_v_4531_2) (< v_idx_1160 v_b_339_3)) (<= .cse0 v_b_338_3) (<= (+ v_b_335_3 2) v_b_339_3) (<= .cse1 v_b_339_3) (<= v_v_4528_2 0) (<= (* 2 v_v_4528_2) 0) (or (<= v_b_335_3 v_idx_1155) (= (select |c_#memory_int| v_idx_1155) v_v_4887_2) (< v_idx_1155 v_b_362_3)) (<= (+ v_b_362_3 3) v_b_339_3) (or (= (select |c_#memory_int| v_idx_1158) v_v_4529_2) (< v_idx_1158 .cse0) (<= v_b_338_3 v_idx_1158)) (or (<= v_b_362_3 v_idx_1154) (= (select |c_#memory_int| v_idx_1154) v_v_4525_1)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= .cse2 v_b_335_3) (<= v_b_335_3 c_ULTIMATE.start_main_p2) (<= v_b_339_3 .cse1) (<= (+ v_b_362_3 2) v_b_338_3) (<= .cse2 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_1157) v_v_4528_2) (< v_idx_1157 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_1157)) (<= v_v_4528_2 v_v_4887_2) (or (= 0 (select |c_#memory_int| v_idx_1159)) (< v_idx_1159 v_b_338_3) (<= v_b_339_3 v_idx_1159)) (<= 0 v_v_4887_2) (<= 0 (* 2 v_v_4887_2)) (<= (+ v_b_335_3 1) v_b_338_3) (<= v_b_335_3 .cse2))))) is different from false [2019-01-08 14:39:11,607 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-08 14:39:11,608 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:39:11,608 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:39:11,608 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [3] total 7 [2019-01-08 14:39:11,608 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:39:11,608 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-08 14:39:11,608 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-08 14:39:11,609 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-08 14:39:11,609 INFO L87 Difference]: Start difference. First operand 23 states and 70 transitions. Second operand 6 states. [2019-01-08 14:39:14,482 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_1159 Int) (v_idx_1158 Int) (v_idx_1157 Int) (v_idx_1156 Int) (v_idx_1155 Int) (v_idx_1154 Int) (v_idx_1160 Int)) (exists ((v_v_4531_2 Int) (v_b_362_3 Int) (v_v_4887_2 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_b_335_3 Int) (v_v_4525_1 Int)) (let ((.cse1 (+ v_b_338_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_362_3 1))) (and (or (< v_idx_1156 v_b_335_3) (<= c_ULTIMATE.start_main_p2 v_idx_1156) (= (select |c_#memory_int| v_idx_1156) v_v_4527_1)) (or (= (select |c_#memory_int| v_idx_1160) v_v_4531_2) (< v_idx_1160 v_b_339_3)) (<= .cse0 v_b_338_3) (<= (+ v_b_335_3 2) v_b_339_3) (<= .cse1 v_b_339_3) (<= v_v_4528_2 0) (<= (* 2 v_v_4528_2) 0) (or (<= v_b_335_3 v_idx_1155) (= (select |c_#memory_int| v_idx_1155) v_v_4887_2) (< v_idx_1155 v_b_362_3)) (<= (+ v_b_362_3 3) v_b_339_3) (or (= (select |c_#memory_int| v_idx_1158) v_v_4529_2) (< v_idx_1158 .cse0) (<= v_b_338_3 v_idx_1158)) (or (<= v_b_362_3 v_idx_1154) (= (select |c_#memory_int| v_idx_1154) v_v_4525_1)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= .cse2 v_b_335_3) (<= v_b_335_3 c_ULTIMATE.start_main_p2) (<= v_b_339_3 .cse1) (<= (+ v_b_362_3 2) v_b_338_3) (<= .cse2 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_1157) v_v_4528_2) (< v_idx_1157 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_1157)) (<= v_v_4528_2 v_v_4887_2) (or (= 0 (select |c_#memory_int| v_idx_1159)) (< v_idx_1159 v_b_338_3) (<= v_b_339_3 v_idx_1159)) (<= 0 v_v_4887_2) (<= 0 (* 2 v_v_4887_2)) (<= (+ v_b_335_3 1) v_b_338_3) (<= v_b_335_3 .cse2))))) (forall ((v_idx_1137 Int) (v_idx_1136 Int) (v_idx_1135 Int) (v_idx_1134 Int) (v_idx_1133 Int) (v_idx_1139 Int) (v_idx_1138 Int)) (exists ((v_v_4531_2 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_v_4525_1 Int) (v_v_4526_1 Int)) (let ((.cse5 (+ v_b_338_3 1)) (.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_1139 v_b_339_3) (= (select |c_#memory_int| v_idx_1139) v_v_4531_2)) (or (<= c_ULTIMATE.start_main_p2 v_idx_1135) (= (select |c_#memory_int| v_idx_1135) v_v_4527_1) (< v_idx_1135 .cse3)) (<= .cse4 v_b_338_3) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_338_3) (<= .cse5 v_b_339_3) (or (< v_idx_1138 v_b_338_3) (<= v_b_339_3 v_idx_1138) (= 0 (select |c_#memory_int| v_idx_1138))) (<= v_v_4528_2 0) (<= (* 2 v_v_4528_2) 0) (or (= (select |c_#memory_int| v_idx_1133) v_v_4525_1) (<= c_ULTIMATE.start_main_p1 v_idx_1133)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= v_b_339_3 .cse5) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_339_3) (or (= (select |c_#memory_int| v_idx_1137) v_v_4529_2) (< v_idx_1137 .cse4) (<= v_b_338_3 v_idx_1137)) (or (<= .cse3 v_idx_1134) (< v_idx_1134 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1134) v_v_4526_1)) (or (= (select |c_#memory_int| v_idx_1136) v_v_4528_2) (< v_idx_1136 c_ULTIMATE.start_main_p2) (<= .cse4 v_idx_1136)) (<= 0 v_v_4526_1) (<= .cse3 c_ULTIMATE.start_main_p2) (<= v_v_4528_2 v_v_4526_1) (<= 0 (* 2 v_v_4526_1)))))) (forall ((v_idx_1148 Int) (v_idx_1147 Int) (v_idx_1153 Int) (v_idx_1152 Int) (v_idx_1151 Int) (v_idx_1150 Int) (v_idx_1149 Int)) (exists ((v_v_4531_2 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_v_4525_1 Int) (v_v_4526_1 Int)) (let ((.cse6 (+ c_ULTIMATE.start_main_p2 1)) (.cse8 (+ v_b_338_3 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= (select |c_#memory_int| v_idx_1150) v_v_4528_2) (<= .cse6 v_idx_1150) (< v_idx_1150 c_ULTIMATE.start_main_p2)) (<= .cse6 v_b_338_3) (or (< v_idx_1149 .cse7) (<= c_ULTIMATE.start_main_p2 v_idx_1149) (= (select |c_#memory_int| v_idx_1149) v_v_4527_1)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_338_3) (<= .cse8 v_b_339_3) (<= v_v_4528_2 0) (or (<= v_b_338_3 v_idx_1151) (= (select |c_#memory_int| v_idx_1151) v_v_4529_2) (< v_idx_1151 .cse6)) (<= (* 2 v_v_4528_2) 0) (or (<= .cse7 v_idx_1148) (= (select |c_#memory_int| v_idx_1148) v_v_4526_1) (< v_idx_1148 c_ULTIMATE.start_main_p1)) (or (< v_idx_1153 v_b_339_3) (= (select |c_#memory_int| v_idx_1153) v_v_4531_2)) (or (<= v_b_339_3 v_idx_1152) (< v_idx_1152 v_b_338_3) (= (select |c_#memory_int| v_idx_1152) 0)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= v_b_339_3 .cse8) (or (= (select |c_#memory_int| v_idx_1147) v_v_4525_1) (<= c_ULTIMATE.start_main_p1 v_idx_1147)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_339_3) (<= 0 v_v_4526_1) (<= .cse7 c_ULTIMATE.start_main_p2) (<= v_v_4528_2 v_v_4526_1) (<= 0 (* 2 v_v_4526_1)))))) (forall ((v_idx_1146 Int) (v_idx_1145 Int) (v_idx_1144 Int) (v_idx_1143 Int) (v_idx_1142 Int) (v_idx_1141 Int) (v_idx_1140 Int)) (exists ((v_v_4531_2 Int) (v_b_338_3 Int) (v_b_339_3 Int) (v_v_4528_2 Int) (v_v_4529_2 Int) (v_v_4527_1 Int) (v_v_4525_1 Int) (v_v_4526_1 Int)) (let ((.cse11 (+ v_b_338_3 1)) (.cse10 (+ c_ULTIMATE.start_main_p2 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_1141 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1141) v_v_4526_1) (<= .cse9 v_idx_1141)) (<= .cse10 v_b_338_3) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_338_3) (<= .cse11 v_b_339_3) (<= v_v_4528_2 0) (<= (* 2 v_v_4528_2) 0) (or (< v_idx_1145 v_b_338_3) (= 0 (select |c_#memory_int| v_idx_1145)) (<= v_b_339_3 v_idx_1145)) (or (<= c_ULTIMATE.start_main_p1 v_idx_1140) (= (select |c_#memory_int| v_idx_1140) v_v_4525_1)) (or (< v_idx_1143 c_ULTIMATE.start_main_p2) (<= .cse10 v_idx_1143) (= (select |c_#memory_int| v_idx_1143) v_v_4528_2)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_3) (<= v_b_339_3 .cse11) (or (<= c_ULTIMATE.start_main_p2 v_idx_1142) (= (select |c_#memory_int| v_idx_1142) v_v_4527_1) (< v_idx_1142 .cse9)) (or (= (select |c_#memory_int| v_idx_1146) v_v_4531_2) (< v_idx_1146 v_b_339_3)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_339_3) (or (<= v_b_338_3 v_idx_1144) (< v_idx_1144 .cse10) (= (select |c_#memory_int| v_idx_1144) v_v_4529_2)) (<= 0 v_v_4526_1) (<= .cse9 c_ULTIMATE.start_main_p2) (<= v_v_4528_2 v_v_4526_1) (<= 0 (* 2 v_v_4526_1))))))) is different from false [2019-01-08 14:39:47,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:39:47,145 INFO L93 Difference]: Finished difference Result 27 states and 77 transitions. [2019-01-08 14:39:47,145 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-08 14:39:47,145 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2019-01-08 14:39:47,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:39:47,146 INFO L225 Difference]: With dead ends: 27 [2019-01-08 14:39:47,146 INFO L226 Difference]: Without dead ends: 26 [2019-01-08 14:39:47,146 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 14.8s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-08 14:39:47,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2019-01-08 14:39:47,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 24. [2019-01-08 14:39:47,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2019-01-08 14:39:47,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 74 transitions. [2019-01-08 14:39:47,178 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 74 transitions. Word has length 5 [2019-01-08 14:39:47,178 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:39:47,178 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 74 transitions. [2019-01-08 14:39:47,178 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-01-08 14:39:47,178 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 74 transitions. [2019-01-08 14:39:47,179 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-08 14:39:47,179 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:39:47,179 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-08 14:39:47,179 INFO L423 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:39:47,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:39:47,179 INFO L82 PathProgramCache]: Analyzing trace with hash 28819942, now seen corresponding path program 1 times [2019-01-08 14:39:47,179 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:39:47,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:39:47,180 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:39:47,180 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:39:47,180 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:39:47,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:39:47,301 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-08 14:39:47,301 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:39:47,301 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:39:47,301 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-08 14:39:47,302 INFO L207 CegarAbsIntRunner]: [0], [6], [12], [16], [17] [2019-01-08 14:39:47,303 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:39:47,303 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:40:00,987 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:40:00,987 INFO L272 AbstractInterpreter]: Visited 5 different actions 37 times. Merged at 3 different actions 16 times. Widened at 2 different actions 6 times. Found 10 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-08 14:40:00,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:40:00,988 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:40:01,406 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 53.57% of their original sizes. [2019-01-08 14:40:01,406 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:40:03,888 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1299 Int) (v_idx_1298 Int) (v_idx_1297 Int) (v_idx_1296 Int) (v_idx_1295 Int) (v_idx_1294 Int) (v_idx_1293 Int)) (exists ((v_v_4485_3 Int) (v_v_4484_3 Int) (v_v_4482_3 Int) (v_v_4486_3 Int) (v_v_4480_3 Int) (v_v_4481_3 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_1293) v_v_4480_3) (<= c_ULTIMATE.start_main_p1 v_idx_1293)) (<= 0 v_v_4481_3) (or (= (select |c_#memory_int| v_idx_1298) v_v_4485_3) (<= .cse0 v_idx_1298) (< v_idx_1298 c_ULTIMATE.start_main_p3)) (or (< v_idx_1294 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_1294) (= (select |c_#memory_int| v_idx_1294) v_v_4481_3)) (or (< v_idx_1297 .cse2) (<= c_ULTIMATE.start_main_p3 v_idx_1297) (= (select |c_#memory_int| v_idx_1297) v_v_4484_3)) (<= .cse2 c_ULTIMATE.start_main_p3) (or (<= .cse2 v_idx_1296) (= 0 (select |c_#memory_int| v_idx_1296)) (< v_idx_1296 c_ULTIMATE.start_main_p2)) (<= 0 (* 2 v_v_4485_3)) (<= 0 (* 2 v_v_4481_3)) (or (< v_idx_1295 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_1295) (= (select |c_#memory_int| v_idx_1295) v_v_4482_3)) (<= 0 v_v_4485_3) (<= .cse1 c_ULTIMATE.start_main_p2) (or (< v_idx_1299 .cse0) (= (select |c_#memory_int| v_idx_1299) v_v_4486_3)) (<= 0 (+ v_v_4485_3 v_v_4481_3)))))) is different from false [2019-01-08 14:40:06,444 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1302 Int) (v_idx_1301 Int) (v_idx_1300 Int) (v_idx_1306 Int) (v_idx_1305 Int) (v_idx_1304 Int) (v_idx_1303 Int)) (exists ((v_v_4485_3 Int) (v_v_4484_3 Int) (v_v_4482_3 Int) (v_v_4486_3 Int) (v_v_4481_3 Int) (v_v_4480_3 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 v_v_4481_3) (or (<= c_ULTIMATE.start_main_p2 v_idx_1302) (= (select |c_#memory_int| v_idx_1302) v_v_4482_3) (< v_idx_1302 .cse0)) (or (<= c_ULTIMATE.start_main_p3 v_idx_1304) (< v_idx_1304 .cse1) (= (select |c_#memory_int| v_idx_1304) v_v_4484_3)) (<= .cse1 c_ULTIMATE.start_main_p3) (or (<= .cse0 v_idx_1301) (= (select |c_#memory_int| v_idx_1301) v_v_4481_3) (< v_idx_1301 c_ULTIMATE.start_main_p1)) (<= 0 (* 2 v_v_4485_3)) (or (= (select |c_#memory_int| v_idx_1305) v_v_4485_3) (<= .cse2 v_idx_1305) (< v_idx_1305 c_ULTIMATE.start_main_p3)) (or (= (select |c_#memory_int| v_idx_1306) v_v_4486_3) (< v_idx_1306 .cse2)) (<= 0 (* 2 v_v_4481_3)) (or (= (select |c_#memory_int| v_idx_1300) v_v_4480_3) (<= c_ULTIMATE.start_main_p1 v_idx_1300)) (<= 0 v_v_4485_3) (or (< v_idx_1303 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1303)) (<= .cse1 v_idx_1303)) (<= .cse0 c_ULTIMATE.start_main_p2) (<= 0 (+ v_v_4485_3 v_v_4481_3)))))) is different from false [2019-01-08 14:40:09,063 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1313 Int) (v_idx_1312 Int) (v_idx_1311 Int) (v_idx_1310 Int) (v_idx_1309 Int) (v_idx_1308 Int) (v_idx_1307 Int)) (exists ((v_v_4485_3 Int) (v_v_4484_3 Int) (v_v_4482_3 Int) (v_v_4486_3 Int) (v_b_349_4 Int) (v_b_348_4 Int) (v_v_4481_3 Int) (v_v_4480_3 Int)) (let ((.cse1 (+ v_b_348_4 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (or (= 0 (select |c_#memory_int| v_idx_1310)) (< v_idx_1310 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_1310)) (<= 0 v_v_4481_3) (<= v_b_349_4 .cse1) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_348_4) (or (= (select |c_#memory_int| v_idx_1308) v_v_4481_3) (< v_idx_1308 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_1308)) (or (< v_idx_1309 .cse2) (<= c_ULTIMATE.start_main_p2 v_idx_1309) (= (select |c_#memory_int| v_idx_1309) v_v_4482_3)) (or (< v_idx_1311 .cse0) (<= v_b_348_4 v_idx_1311) (= (select |c_#memory_int| v_idx_1311) v_v_4484_3)) (or (<= v_b_349_4 v_idx_1312) (= (select |c_#memory_int| v_idx_1312) v_v_4485_3) (< v_idx_1312 v_b_348_4)) (<= 0 (* 2 v_v_4485_3)) (<= .cse1 v_b_349_4) (<= 0 (* 2 v_v_4481_3)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_349_4) (<= 0 v_v_4485_3) (<= .cse2 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_1313) v_v_4486_3) (< v_idx_1313 v_b_349_4)) (<= .cse0 v_b_348_4) (<= 0 (+ v_v_4485_3 v_v_4481_3)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_349_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_1307) (= (select |c_#memory_int| v_idx_1307) v_v_4480_3)))))) is different from false [2019-01-08 14:40:11,407 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1320 Int) (v_idx_1319 Int) (v_idx_1318 Int) (v_idx_1317 Int) (v_idx_1316 Int) (v_idx_1315 Int) (v_idx_1314 Int)) (exists ((v_v_4485_3 Int) (v_b_372_4 Int) (v_v_4484_3 Int) (v_v_4482_3 Int) (v_v_4842_3 Int) (v_v_4486_3 Int) (v_b_349_4 Int) (v_b_348_4 Int) (v_b_345_4 Int) (v_v_4480_3 Int)) (let ((.cse1 (+ v_b_372_4 1)) (.cse0 (+ v_b_348_4 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1))) (and (<= 0 (* 2 v_v_4842_3)) (<= (+ v_b_345_4 2) v_b_349_4) (or (< v_idx_1315 v_b_372_4) (<= v_b_345_4 v_idx_1315) (= (select |c_#memory_int| v_idx_1315) v_v_4842_3)) (<= 0 v_v_4842_3) (or (< v_idx_1320 v_b_349_4) (= (select |c_#memory_int| v_idx_1320) v_v_4486_3)) (<= v_b_349_4 .cse0) (<= (+ v_b_372_4 3) v_b_349_4) (<= v_b_345_4 c_ULTIMATE.start_main_p2) (<= v_b_345_4 .cse1) (<= 0 (+ v_v_4485_3 v_v_4842_3)) (<= .cse1 v_b_345_4) (or (< v_idx_1318 .cse2) (<= v_b_348_4 v_idx_1318) (= (select |c_#memory_int| v_idx_1318) v_v_4484_3)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= (+ v_b_372_4 2) v_b_348_4) (<= 0 (* 2 v_v_4485_3)) (<= (+ v_b_345_4 1) v_b_348_4) (<= .cse0 v_b_349_4) (or (<= v_b_349_4 v_idx_1319) (= (select |c_#memory_int| v_idx_1319) v_v_4485_3) (< v_idx_1319 v_b_348_4)) (or (< v_idx_1316 v_b_345_4) (= (select |c_#memory_int| v_idx_1316) v_v_4482_3) (<= c_ULTIMATE.start_main_p2 v_idx_1316)) (<= 0 v_v_4485_3) (or (<= .cse2 v_idx_1317) (< v_idx_1317 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1317))) (<= .cse2 v_b_348_4) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_349_4) (or (<= v_b_372_4 v_idx_1314) (= (select |c_#memory_int| v_idx_1314) v_v_4480_3)))))) is different from false [2019-01-08 14:40:11,465 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-08 14:40:11,465 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:40:11,466 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:40:11,466 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [3] total 7 [2019-01-08 14:40:11,466 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:40:11,466 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-08 14:40:11,466 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-08 14:40:11,466 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-08 14:40:11,467 INFO L87 Difference]: Start difference. First operand 24 states and 74 transitions. Second operand 6 states. [2019-01-08 14:40:14,225 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_1299 Int) (v_idx_1298 Int) (v_idx_1297 Int) (v_idx_1296 Int) (v_idx_1295 Int) (v_idx_1294 Int) (v_idx_1293 Int)) (exists ((v_v_4485_3 Int) (v_v_4484_3 Int) (v_v_4482_3 Int) (v_v_4486_3 Int) (v_v_4480_3 Int) (v_v_4481_3 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_1293) v_v_4480_3) (<= c_ULTIMATE.start_main_p1 v_idx_1293)) (<= 0 v_v_4481_3) (or (= (select |c_#memory_int| v_idx_1298) v_v_4485_3) (<= .cse0 v_idx_1298) (< v_idx_1298 c_ULTIMATE.start_main_p3)) (or (< v_idx_1294 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_1294) (= (select |c_#memory_int| v_idx_1294) v_v_4481_3)) (or (< v_idx_1297 .cse2) (<= c_ULTIMATE.start_main_p3 v_idx_1297) (= (select |c_#memory_int| v_idx_1297) v_v_4484_3)) (<= .cse2 c_ULTIMATE.start_main_p3) (or (<= .cse2 v_idx_1296) (= 0 (select |c_#memory_int| v_idx_1296)) (< v_idx_1296 c_ULTIMATE.start_main_p2)) (<= 0 (* 2 v_v_4485_3)) (<= 0 (* 2 v_v_4481_3)) (or (< v_idx_1295 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_1295) (= (select |c_#memory_int| v_idx_1295) v_v_4482_3)) (<= 0 v_v_4485_3) (<= .cse1 c_ULTIMATE.start_main_p2) (or (< v_idx_1299 .cse0) (= (select |c_#memory_int| v_idx_1299) v_v_4486_3)) (<= 0 (+ v_v_4485_3 v_v_4481_3)))))) (forall ((v_idx_1302 Int) (v_idx_1301 Int) (v_idx_1300 Int) (v_idx_1306 Int) (v_idx_1305 Int) (v_idx_1304 Int) (v_idx_1303 Int)) (exists ((v_v_4485_3 Int) (v_v_4484_3 Int) (v_v_4482_3 Int) (v_v_4486_3 Int) (v_v_4481_3 Int) (v_v_4480_3 Int)) (let ((.cse5 (+ c_ULTIMATE.start_main_p3 1)) (.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 v_v_4481_3) (or (<= c_ULTIMATE.start_main_p2 v_idx_1302) (= (select |c_#memory_int| v_idx_1302) v_v_4482_3) (< v_idx_1302 .cse3)) (or (<= c_ULTIMATE.start_main_p3 v_idx_1304) (< v_idx_1304 .cse4) (= (select |c_#memory_int| v_idx_1304) v_v_4484_3)) (<= .cse4 c_ULTIMATE.start_main_p3) (or (<= .cse3 v_idx_1301) (= (select |c_#memory_int| v_idx_1301) v_v_4481_3) (< v_idx_1301 c_ULTIMATE.start_main_p1)) (<= 0 (* 2 v_v_4485_3)) (or (= (select |c_#memory_int| v_idx_1305) v_v_4485_3) (<= .cse5 v_idx_1305) (< v_idx_1305 c_ULTIMATE.start_main_p3)) (or (= (select |c_#memory_int| v_idx_1306) v_v_4486_3) (< v_idx_1306 .cse5)) (<= 0 (* 2 v_v_4481_3)) (or (= (select |c_#memory_int| v_idx_1300) v_v_4480_3) (<= c_ULTIMATE.start_main_p1 v_idx_1300)) (<= 0 v_v_4485_3) (or (< v_idx_1303 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1303)) (<= .cse4 v_idx_1303)) (<= .cse3 c_ULTIMATE.start_main_p2) (<= 0 (+ v_v_4485_3 v_v_4481_3)))))) (forall ((v_idx_1320 Int) (v_idx_1319 Int) (v_idx_1318 Int) (v_idx_1317 Int) (v_idx_1316 Int) (v_idx_1315 Int) (v_idx_1314 Int)) (exists ((v_v_4485_3 Int) (v_b_372_4 Int) (v_v_4484_3 Int) (v_v_4482_3 Int) (v_v_4842_3 Int) (v_v_4486_3 Int) (v_b_349_4 Int) (v_b_348_4 Int) (v_b_345_4 Int) (v_v_4480_3 Int)) (let ((.cse7 (+ v_b_372_4 1)) (.cse6 (+ v_b_348_4 1)) (.cse8 (+ c_ULTIMATE.start_main_p2 1))) (and (<= 0 (* 2 v_v_4842_3)) (<= (+ v_b_345_4 2) v_b_349_4) (or (< v_idx_1315 v_b_372_4) (<= v_b_345_4 v_idx_1315) (= (select |c_#memory_int| v_idx_1315) v_v_4842_3)) (<= 0 v_v_4842_3) (or (< v_idx_1320 v_b_349_4) (= (select |c_#memory_int| v_idx_1320) v_v_4486_3)) (<= v_b_349_4 .cse6) (<= (+ v_b_372_4 3) v_b_349_4) (<= v_b_345_4 c_ULTIMATE.start_main_p2) (<= v_b_345_4 .cse7) (<= 0 (+ v_v_4485_3 v_v_4842_3)) (<= .cse7 v_b_345_4) (or (< v_idx_1318 .cse8) (<= v_b_348_4 v_idx_1318) (= (select |c_#memory_int| v_idx_1318) v_v_4484_3)) (<= .cse7 c_ULTIMATE.start_main_p2) (<= (+ v_b_372_4 2) v_b_348_4) (<= 0 (* 2 v_v_4485_3)) (<= (+ v_b_345_4 1) v_b_348_4) (<= .cse6 v_b_349_4) (or (<= v_b_349_4 v_idx_1319) (= (select |c_#memory_int| v_idx_1319) v_v_4485_3) (< v_idx_1319 v_b_348_4)) (or (< v_idx_1316 v_b_345_4) (= (select |c_#memory_int| v_idx_1316) v_v_4482_3) (<= c_ULTIMATE.start_main_p2 v_idx_1316)) (<= 0 v_v_4485_3) (or (<= .cse8 v_idx_1317) (< v_idx_1317 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1317))) (<= .cse8 v_b_348_4) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_349_4) (or (<= v_b_372_4 v_idx_1314) (= (select |c_#memory_int| v_idx_1314) v_v_4480_3)))))) (forall ((v_idx_1313 Int) (v_idx_1312 Int) (v_idx_1311 Int) (v_idx_1310 Int) (v_idx_1309 Int) (v_idx_1308 Int) (v_idx_1307 Int)) (exists ((v_v_4485_3 Int) (v_v_4484_3 Int) (v_v_4482_3 Int) (v_v_4486_3 Int) (v_b_349_4 Int) (v_b_348_4 Int) (v_v_4481_3 Int) (v_v_4480_3 Int)) (let ((.cse10 (+ v_b_348_4 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 1)) (.cse9 (+ c_ULTIMATE.start_main_p2 1))) (and (or (= 0 (select |c_#memory_int| v_idx_1310)) (< v_idx_1310 c_ULTIMATE.start_main_p2) (<= .cse9 v_idx_1310)) (<= 0 v_v_4481_3) (<= v_b_349_4 .cse10) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_348_4) (or (= (select |c_#memory_int| v_idx_1308) v_v_4481_3) (< v_idx_1308 c_ULTIMATE.start_main_p1) (<= .cse11 v_idx_1308)) (or (< v_idx_1309 .cse11) (<= c_ULTIMATE.start_main_p2 v_idx_1309) (= (select |c_#memory_int| v_idx_1309) v_v_4482_3)) (or (< v_idx_1311 .cse9) (<= v_b_348_4 v_idx_1311) (= (select |c_#memory_int| v_idx_1311) v_v_4484_3)) (or (<= v_b_349_4 v_idx_1312) (= (select |c_#memory_int| v_idx_1312) v_v_4485_3) (< v_idx_1312 v_b_348_4)) (<= 0 (* 2 v_v_4485_3)) (<= .cse10 v_b_349_4) (<= 0 (* 2 v_v_4481_3)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_349_4) (<= 0 v_v_4485_3) (<= .cse11 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_1313) v_v_4486_3) (< v_idx_1313 v_b_349_4)) (<= .cse9 v_b_348_4) (<= 0 (+ v_v_4485_3 v_v_4481_3)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_349_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_1307) (= (select |c_#memory_int| v_idx_1307) v_v_4480_3))))))) is different from false [2019-01-08 14:40:52,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:40:52,572 INFO L93 Difference]: Finished difference Result 28 states and 81 transitions. [2019-01-08 14:40:52,573 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-08 14:40:52,573 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2019-01-08 14:40:52,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:40:52,573 INFO L225 Difference]: With dead ends: 28 [2019-01-08 14:40:52,573 INFO L226 Difference]: Without dead ends: 27 [2019-01-08 14:40:52,574 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.5s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-08 14:40:52,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2019-01-08 14:40:52,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 24. [2019-01-08 14:40:52,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2019-01-08 14:40:52,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 74 transitions. [2019-01-08 14:40:52,602 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 74 transitions. Word has length 5 [2019-01-08 14:40:52,603 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:40:52,603 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 74 transitions. [2019-01-08 14:40:52,603 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-01-08 14:40:52,603 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 74 transitions. [2019-01-08 14:40:52,603 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-08 14:40:52,603 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:40:52,603 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-08 14:40:52,604 INFO L423 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:40:52,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:40:52,604 INFO L82 PathProgramCache]: Analyzing trace with hash 28943014, now seen corresponding path program 1 times [2019-01-08 14:40:52,604 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:40:52,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:40:52,605 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:40:52,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:40:52,605 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:40:52,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:40:52,829 WARN L181 SmtUtils]: Spent 186.00 ms on a formula simplification. DAG size of input: 21 DAG size of output: 13 [2019-01-08 14:40:52,837 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-08 14:40:52,838 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-08 14:40:52,838 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-01-08 14:40:52,838 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:40:52,838 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:40:52,838 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:40:52,839 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-01-08 14:40:52,839 INFO L87 Difference]: Start difference. First operand 24 states and 74 transitions. Second operand 4 states. [2019-01-08 14:40:52,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:40:52,885 INFO L93 Difference]: Finished difference Result 29 states and 78 transitions. [2019-01-08 14:40:52,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-08 14:40:52,886 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 5 [2019-01-08 14:40:52,886 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:40:52,887 INFO L225 Difference]: With dead ends: 29 [2019-01-08 14:40:52,887 INFO L226 Difference]: Without dead ends: 26 [2019-01-08 14:40:52,887 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-01-08 14:40:52,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2019-01-08 14:40:52,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 25. [2019-01-08 14:40:52,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-01-08 14:40:52,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 74 transitions. [2019-01-08 14:40:52,917 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 74 transitions. Word has length 5 [2019-01-08 14:40:52,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:40:52,917 INFO L480 AbstractCegarLoop]: Abstraction has 25 states and 74 transitions. [2019-01-08 14:40:52,917 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:40:52,917 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 74 transitions. [2019-01-08 14:40:52,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-08 14:40:52,918 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:40:52,918 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-08 14:40:52,918 INFO L423 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:40:52,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:40:52,918 INFO L82 PathProgramCache]: Analyzing trace with hash 28933340, now seen corresponding path program 2 times [2019-01-08 14:40:52,919 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:40:52,919 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:40:52,919 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:40:52,919 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:40:52,920 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:40:52,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:40:53,003 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:40:53,004 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:40:53,004 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:40:53,004 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-08 14:40:53,005 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-08 14:40:53,005 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:40:53,005 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-08 14:40:53,022 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-08 14:40:53,022 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-08 14:40:53,027 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-08 14:40:53,027 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-08 14:40:53,028 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-08 14:40:53,032 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-08 14:40:53,034 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:40:53,035 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-08 14:40:53,060 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:40:53,085 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:40:53,086 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-08 14:40:53,086 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-08 14:40:53,146 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:40:53,152 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:40:53,167 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:40:53,168 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:19, output treesize:22 [2019-01-08 14:40:53,191 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:40:53,192 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:40:53,193 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:40:53,194 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:40:53,195 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-08 14:40:53,196 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:40:53,213 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:40:53,214 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-08 14:40:53,233 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:40:53,234 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:40:53,235 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:40:53,236 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:40:53,237 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:40:53,238 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:40:53,239 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 42 [2019-01-08 14:40:53,239 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:40:53,265 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:40:53,265 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:24 [2019-01-08 14:40:53,316 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:40:53,317 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-08 14:40:53,339 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:40:53,359 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-08 14:40:53,359 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 9 [2019-01-08 14:40:53,359 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-08 14:40:53,360 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-01-08 14:40:53,360 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-01-08 14:40:53,360 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-01-08 14:40:53,360 INFO L87 Difference]: Start difference. First operand 25 states and 74 transitions. Second operand 8 states. [2019-01-08 14:40:53,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:40:53,657 INFO L93 Difference]: Finished difference Result 39 states and 95 transitions. [2019-01-08 14:40:53,657 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-01-08 14:40:53,657 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 5 [2019-01-08 14:40:53,658 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:40:53,658 INFO L225 Difference]: With dead ends: 39 [2019-01-08 14:40:53,658 INFO L226 Difference]: Without dead ends: 37 [2019-01-08 14:40:53,659 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=53, Invalid=79, Unknown=0, NotChecked=0, Total=132 [2019-01-08 14:40:53,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2019-01-08 14:40:53,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 24. [2019-01-08 14:40:53,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2019-01-08 14:40:53,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 71 transitions. [2019-01-08 14:40:53,688 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 71 transitions. Word has length 5 [2019-01-08 14:40:53,688 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:40:53,688 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 71 transitions. [2019-01-08 14:40:53,688 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-01-08 14:40:53,688 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 71 transitions. [2019-01-08 14:40:53,688 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-08 14:40:53,689 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:40:53,689 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-08 14:40:53,689 INFO L423 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:40:53,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:40:53,689 INFO L82 PathProgramCache]: Analyzing trace with hash 28939106, now seen corresponding path program 1 times [2019-01-08 14:40:53,689 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:40:53,690 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:40:53,690 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-08 14:40:53,690 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:40:53,690 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:40:53,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:40:53,761 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:40:53,761 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:40:53,761 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:40:53,762 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-08 14:40:53,762 INFO L207 CegarAbsIntRunner]: [0], [10], [12], [16], [17] [2019-01-08 14:40:53,763 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:40:53,763 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:41:06,478 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:41:06,478 INFO L272 AbstractInterpreter]: Visited 5 different actions 37 times. Merged at 3 different actions 16 times. Widened at 2 different actions 6 times. Found 10 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-08 14:41:06,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:41:06,478 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:41:06,909 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 53.57% of their original sizes. [2019-01-08 14:41:06,909 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:41:09,316 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1456 Int) (v_idx_1455 Int) (v_idx_1454 Int) (v_idx_1453 Int) (v_idx_1459 Int) (v_idx_1458 Int) (v_idx_1457 Int)) (exists ((v_v_4470_4 Int) (v_v_4471_4 Int) (v_v_4465_4 Int) (v_v_4469_4 Int) (v_v_4467_4 Int) (v_v_4468_4 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= .cse0 v_idx_1456) (= (select |c_#memory_int| v_idx_1456) v_v_4468_4) (< v_idx_1456 c_ULTIMATE.start_main_p2)) (or (< v_idx_1454 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_1454) (= (select |c_#memory_int| v_idx_1454) 0)) (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_1458 c_ULTIMATE.start_main_p3) (<= .cse2 v_idx_1458) (= (select |c_#memory_int| v_idx_1458) v_v_4470_4)) (<= v_v_4468_4 0) (or (= (select |c_#memory_int| v_idx_1459) v_v_4471_4) (< v_idx_1459 .cse2)) (<= 0 (* 2 v_v_4470_4)) (<= .cse0 c_ULTIMATE.start_main_p3) (<= v_v_4468_4 v_v_4470_4) (or (<= c_ULTIMATE.start_main_p3 v_idx_1457) (= (select |c_#memory_int| v_idx_1457) v_v_4469_4) (< v_idx_1457 .cse0)) (<= (* 2 v_v_4468_4) 0) (or (= (select |c_#memory_int| v_idx_1453) v_v_4465_4) (<= c_ULTIMATE.start_main_p1 v_idx_1453)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= 0 v_v_4470_4) (or (<= c_ULTIMATE.start_main_p2 v_idx_1455) (= (select |c_#memory_int| v_idx_1455) v_v_4467_4) (< v_idx_1455 .cse1)))))) is different from false [2019-01-08 14:41:11,960 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1466 Int) (v_idx_1465 Int) (v_idx_1464 Int) (v_idx_1463 Int) (v_idx_1462 Int) (v_idx_1461 Int) (v_idx_1460 Int)) (exists ((v_v_4470_4 Int) (v_v_4471_4 Int) (v_v_4465_4 Int) (v_v_4469_4 Int) (v_v_4467_4 Int) (v_v_4468_4 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_1461 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_1461)) (<= .cse0 v_idx_1461)) (<= v_v_4468_4 0) (or (= (select |c_#memory_int| v_idx_1462) v_v_4467_4) (<= c_ULTIMATE.start_main_p2 v_idx_1462) (< v_idx_1462 .cse0)) (or (= (select |c_#memory_int| v_idx_1463) v_v_4468_4) (< v_idx_1463 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_1463)) (<= 0 (* 2 v_v_4470_4)) (<= .cse1 c_ULTIMATE.start_main_p3) (<= v_v_4468_4 v_v_4470_4) (or (<= .cse2 v_idx_1465) (= (select |c_#memory_int| v_idx_1465) v_v_4470_4) (< v_idx_1465 c_ULTIMATE.start_main_p3)) (<= (* 2 v_v_4468_4) 0) (or (<= c_ULTIMATE.start_main_p3 v_idx_1464) (= (select |c_#memory_int| v_idx_1464) v_v_4469_4) (< v_idx_1464 .cse1)) (or (= (select |c_#memory_int| v_idx_1466) v_v_4471_4) (< v_idx_1466 .cse2)) (<= .cse0 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_1460) v_v_4465_4) (<= c_ULTIMATE.start_main_p1 v_idx_1460)) (<= 0 v_v_4470_4))))) is different from false [2019-01-08 14:41:16,135 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1467 Int) (v_idx_1473 Int) (v_idx_1472 Int) (v_idx_1471 Int) (v_idx_1470 Int) (v_idx_1469 Int) (v_idx_1468 Int)) (exists ((v_v_4470_4 Int) (v_v_4471_4 Int) (v_v_4465_4 Int) (v_b_338_5 Int) (v_b_339_5 Int) (v_v_4469_4 Int) (v_v_4467_4 Int) (v_v_4468_4 Int)) (let ((.cse0 (+ v_b_338_5 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_1472 v_b_338_5) (<= v_b_339_5 v_idx_1472) (= (select |c_#memory_int| v_idx_1472) v_v_4470_4)) (<= .cse0 v_b_339_5) (or (= (select |c_#memory_int| v_idx_1473) v_v_4471_4) (< v_idx_1473 v_b_339_5)) (<= v_b_339_5 .cse0) (<= v_v_4468_4 0) (or (<= c_ULTIMATE.start_main_p1 v_idx_1467) (= (select |c_#memory_int| v_idx_1467) v_v_4465_4)) (or (= (select |c_#memory_int| v_idx_1469) v_v_4467_4) (<= c_ULTIMATE.start_main_p2 v_idx_1469) (< v_idx_1469 .cse1)) (or (= 0 (select |c_#memory_int| v_idx_1468)) (<= .cse1 v_idx_1468) (< v_idx_1468 c_ULTIMATE.start_main_p1)) (<= 0 (* 2 v_v_4470_4)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_5) (<= v_v_4468_4 v_v_4470_4) (or (= (select |c_#memory_int| v_idx_1471) v_v_4469_4) (< v_idx_1471 .cse2) (<= v_b_338_5 v_idx_1471)) (<= .cse2 v_b_338_5) (<= (* 2 v_v_4468_4) 0) (or (< v_idx_1470 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1470) v_v_4468_4) (<= .cse2 v_idx_1470)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_338_5) (<= 0 v_v_4470_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_339_5))))) is different from false [2019-01-08 14:41:18,304 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1478 Int) (v_idx_1477 Int) (v_idx_1476 Int) (v_idx_1475 Int) (v_idx_1474 Int) (v_idx_1480 Int) (v_idx_1479 Int)) (exists ((v_b_362_5 Int) (v_v_4470_4 Int) (v_v_4471_4 Int) (v_v_4465_4 Int) (v_b_338_5 Int) (v_b_339_5 Int) (v_v_4469_4 Int) (v_v_4467_4 Int) (v_b_335_5 Int) (v_v_4468_4 Int)) (let ((.cse0 (+ v_b_338_5 1)) (.cse1 (+ v_b_362_5 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1))) (and (<= v_b_335_5 c_ULTIMATE.start_main_p2) (<= .cse0 v_b_339_5) (or (< v_idx_1475 v_b_362_5) (<= v_b_335_5 v_idx_1475) (= 0 (select |c_#memory_int| v_idx_1475))) (or (<= v_b_362_5 v_idx_1474) (= (select |c_#memory_int| v_idx_1474) v_v_4465_4)) (<= v_b_339_5 .cse0) (<= v_v_4468_4 0) (or (= (select |c_#memory_int| v_idx_1476) v_v_4467_4) (<= c_ULTIMATE.start_main_p2 v_idx_1476) (< v_idx_1476 v_b_335_5)) (<= (+ v_b_362_5 3) v_b_339_5) (<= .cse1 v_b_335_5) (or (= (select |c_#memory_int| v_idx_1479) v_v_4470_4) (<= v_b_339_5 v_idx_1479) (< v_idx_1479 v_b_338_5)) (<= 0 (* 2 v_v_4470_4)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_5) (<= v_v_4468_4 v_v_4470_4) (<= (+ v_b_335_5 1) v_b_338_5) (<= .cse2 v_b_338_5) (<= v_b_335_5 .cse1) (<= (* 2 v_v_4468_4) 0) (<= (+ v_b_362_5 2) v_b_338_5) (or (= (select |c_#memory_int| v_idx_1477) v_v_4468_4) (<= .cse2 v_idx_1477) (< v_idx_1477 c_ULTIMATE.start_main_p2)) (or (< v_idx_1480 v_b_339_5) (= (select |c_#memory_int| v_idx_1480) v_v_4471_4)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= 0 v_v_4470_4) (<= (+ v_b_335_5 2) v_b_339_5) (or (< v_idx_1478 .cse2) (<= v_b_338_5 v_idx_1478) (= (select |c_#memory_int| v_idx_1478) v_v_4469_4)))))) is different from false [2019-01-08 14:41:18,345 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-08 14:41:18,345 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:41:18,345 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:41:18,345 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [3] total 7 [2019-01-08 14:41:18,346 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:41:18,346 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-08 14:41:18,346 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-08 14:41:18,346 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-08 14:41:18,346 INFO L87 Difference]: Start difference. First operand 24 states and 71 transitions. Second operand 6 states. [2019-01-08 14:41:20,971 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_1456 Int) (v_idx_1455 Int) (v_idx_1454 Int) (v_idx_1453 Int) (v_idx_1459 Int) (v_idx_1458 Int) (v_idx_1457 Int)) (exists ((v_v_4470_4 Int) (v_v_4471_4 Int) (v_v_4465_4 Int) (v_v_4469_4 Int) (v_v_4467_4 Int) (v_v_4468_4 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= .cse0 v_idx_1456) (= (select |c_#memory_int| v_idx_1456) v_v_4468_4) (< v_idx_1456 c_ULTIMATE.start_main_p2)) (or (< v_idx_1454 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_1454) (= (select |c_#memory_int| v_idx_1454) 0)) (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_1458 c_ULTIMATE.start_main_p3) (<= .cse2 v_idx_1458) (= (select |c_#memory_int| v_idx_1458) v_v_4470_4)) (<= v_v_4468_4 0) (or (= (select |c_#memory_int| v_idx_1459) v_v_4471_4) (< v_idx_1459 .cse2)) (<= 0 (* 2 v_v_4470_4)) (<= .cse0 c_ULTIMATE.start_main_p3) (<= v_v_4468_4 v_v_4470_4) (or (<= c_ULTIMATE.start_main_p3 v_idx_1457) (= (select |c_#memory_int| v_idx_1457) v_v_4469_4) (< v_idx_1457 .cse0)) (<= (* 2 v_v_4468_4) 0) (or (= (select |c_#memory_int| v_idx_1453) v_v_4465_4) (<= c_ULTIMATE.start_main_p1 v_idx_1453)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= 0 v_v_4470_4) (or (<= c_ULTIMATE.start_main_p2 v_idx_1455) (= (select |c_#memory_int| v_idx_1455) v_v_4467_4) (< v_idx_1455 .cse1)))))) (forall ((v_idx_1478 Int) (v_idx_1477 Int) (v_idx_1476 Int) (v_idx_1475 Int) (v_idx_1474 Int) (v_idx_1480 Int) (v_idx_1479 Int)) (exists ((v_b_362_5 Int) (v_v_4470_4 Int) (v_v_4471_4 Int) (v_v_4465_4 Int) (v_b_338_5 Int) (v_b_339_5 Int) (v_v_4469_4 Int) (v_v_4467_4 Int) (v_b_335_5 Int) (v_v_4468_4 Int)) (let ((.cse3 (+ v_b_338_5 1)) (.cse4 (+ v_b_362_5 1)) (.cse5 (+ c_ULTIMATE.start_main_p2 1))) (and (<= v_b_335_5 c_ULTIMATE.start_main_p2) (<= .cse3 v_b_339_5) (or (< v_idx_1475 v_b_362_5) (<= v_b_335_5 v_idx_1475) (= 0 (select |c_#memory_int| v_idx_1475))) (or (<= v_b_362_5 v_idx_1474) (= (select |c_#memory_int| v_idx_1474) v_v_4465_4)) (<= v_b_339_5 .cse3) (<= v_v_4468_4 0) (or (= (select |c_#memory_int| v_idx_1476) v_v_4467_4) (<= c_ULTIMATE.start_main_p2 v_idx_1476) (< v_idx_1476 v_b_335_5)) (<= (+ v_b_362_5 3) v_b_339_5) (<= .cse4 v_b_335_5) (or (= (select |c_#memory_int| v_idx_1479) v_v_4470_4) (<= v_b_339_5 v_idx_1479) (< v_idx_1479 v_b_338_5)) (<= 0 (* 2 v_v_4470_4)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_5) (<= v_v_4468_4 v_v_4470_4) (<= (+ v_b_335_5 1) v_b_338_5) (<= .cse5 v_b_338_5) (<= v_b_335_5 .cse4) (<= (* 2 v_v_4468_4) 0) (<= (+ v_b_362_5 2) v_b_338_5) (or (= (select |c_#memory_int| v_idx_1477) v_v_4468_4) (<= .cse5 v_idx_1477) (< v_idx_1477 c_ULTIMATE.start_main_p2)) (or (< v_idx_1480 v_b_339_5) (= (select |c_#memory_int| v_idx_1480) v_v_4471_4)) (<= .cse4 c_ULTIMATE.start_main_p2) (<= 0 v_v_4470_4) (<= (+ v_b_335_5 2) v_b_339_5) (or (< v_idx_1478 .cse5) (<= v_b_338_5 v_idx_1478) (= (select |c_#memory_int| v_idx_1478) v_v_4469_4)))))) (forall ((v_idx_1466 Int) (v_idx_1465 Int) (v_idx_1464 Int) (v_idx_1463 Int) (v_idx_1462 Int) (v_idx_1461 Int) (v_idx_1460 Int)) (exists ((v_v_4470_4 Int) (v_v_4471_4 Int) (v_v_4465_4 Int) (v_v_4469_4 Int) (v_v_4467_4 Int) (v_v_4468_4 Int)) (let ((.cse7 (+ c_ULTIMATE.start_main_p2 1)) (.cse8 (+ c_ULTIMATE.start_main_p3 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_1461 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_1461)) (<= .cse6 v_idx_1461)) (<= v_v_4468_4 0) (or (= (select |c_#memory_int| v_idx_1462) v_v_4467_4) (<= c_ULTIMATE.start_main_p2 v_idx_1462) (< v_idx_1462 .cse6)) (or (= (select |c_#memory_int| v_idx_1463) v_v_4468_4) (< v_idx_1463 c_ULTIMATE.start_main_p2) (<= .cse7 v_idx_1463)) (<= 0 (* 2 v_v_4470_4)) (<= .cse7 c_ULTIMATE.start_main_p3) (<= v_v_4468_4 v_v_4470_4) (or (<= .cse8 v_idx_1465) (= (select |c_#memory_int| v_idx_1465) v_v_4470_4) (< v_idx_1465 c_ULTIMATE.start_main_p3)) (<= (* 2 v_v_4468_4) 0) (or (<= c_ULTIMATE.start_main_p3 v_idx_1464) (= (select |c_#memory_int| v_idx_1464) v_v_4469_4) (< v_idx_1464 .cse7)) (or (= (select |c_#memory_int| v_idx_1466) v_v_4471_4) (< v_idx_1466 .cse8)) (<= .cse6 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_1460) v_v_4465_4) (<= c_ULTIMATE.start_main_p1 v_idx_1460)) (<= 0 v_v_4470_4))))) (forall ((v_idx_1467 Int) (v_idx_1473 Int) (v_idx_1472 Int) (v_idx_1471 Int) (v_idx_1470 Int) (v_idx_1469 Int) (v_idx_1468 Int)) (exists ((v_v_4470_4 Int) (v_v_4471_4 Int) (v_v_4465_4 Int) (v_b_338_5 Int) (v_b_339_5 Int) (v_v_4469_4 Int) (v_v_4467_4 Int) (v_v_4468_4 Int)) (let ((.cse9 (+ v_b_338_5 1)) (.cse11 (+ c_ULTIMATE.start_main_p2 1)) (.cse10 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_1472 v_b_338_5) (<= v_b_339_5 v_idx_1472) (= (select |c_#memory_int| v_idx_1472) v_v_4470_4)) (<= .cse9 v_b_339_5) (or (= (select |c_#memory_int| v_idx_1473) v_v_4471_4) (< v_idx_1473 v_b_339_5)) (<= v_b_339_5 .cse9) (<= v_v_4468_4 0) (or (<= c_ULTIMATE.start_main_p1 v_idx_1467) (= (select |c_#memory_int| v_idx_1467) v_v_4465_4)) (or (= (select |c_#memory_int| v_idx_1469) v_v_4467_4) (<= c_ULTIMATE.start_main_p2 v_idx_1469) (< v_idx_1469 .cse10)) (or (= 0 (select |c_#memory_int| v_idx_1468)) (<= .cse10 v_idx_1468) (< v_idx_1468 c_ULTIMATE.start_main_p1)) (<= 0 (* 2 v_v_4470_4)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_339_5) (<= v_v_4468_4 v_v_4470_4) (or (= (select |c_#memory_int| v_idx_1471) v_v_4469_4) (< v_idx_1471 .cse11) (<= v_b_338_5 v_idx_1471)) (<= .cse11 v_b_338_5) (<= (* 2 v_v_4468_4) 0) (or (< v_idx_1470 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1470) v_v_4468_4) (<= .cse11 v_idx_1470)) (<= .cse10 c_ULTIMATE.start_main_p2) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_338_5) (<= 0 v_v_4470_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_339_5)))))) is different from false [2019-01-08 14:41:32,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:41:32,957 INFO L93 Difference]: Finished difference Result 28 states and 78 transitions. [2019-01-08 14:41:32,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-08 14:41:32,957 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2019-01-08 14:41:32,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:41:32,957 INFO L225 Difference]: With dead ends: 28 [2019-01-08 14:41:32,958 INFO L226 Difference]: Without dead ends: 27 [2019-01-08 14:41:32,958 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 13.9s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-08 14:41:32,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2019-01-08 14:41:32,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 25. [2019-01-08 14:41:32,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-01-08 14:41:32,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 75 transitions. [2019-01-08 14:41:32,990 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 75 transitions. Word has length 5 [2019-01-08 14:41:32,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:41:32,991 INFO L480 AbstractCegarLoop]: Abstraction has 25 states and 75 transitions. [2019-01-08 14:41:32,991 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-01-08 14:41:32,991 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 75 transitions. [2019-01-08 14:41:32,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-08 14:41:32,991 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:41:32,991 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-08 14:41:32,992 INFO L423 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:41:32,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:41:32,992 INFO L82 PathProgramCache]: Analyzing trace with hash 29002596, now seen corresponding path program 1 times [2019-01-08 14:41:32,992 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:41:32,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:41:32,993 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:41:32,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:41:32,993 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:41:32,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:41:33,021 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:41:33,021 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:41:33,021 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:41:33,021 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-08 14:41:33,021 INFO L207 CegarAbsIntRunner]: [0], [12], [16], [18], [19] [2019-01-08 14:41:33,022 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:41:33,023 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:41:39,021 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:41:39,022 INFO L272 AbstractInterpreter]: Visited 5 different actions 21 times. Merged at 3 different actions 12 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:41:39,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:41:39,022 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:41:39,372 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 53.57% of their original sizes. [2019-01-08 14:41:39,372 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:41:41,749 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1619 Int) (v_idx_1618 Int) (v_idx_1617 Int) (v_idx_1616 Int) (v_idx_1615 Int) (v_idx_1614 Int) (v_idx_1613 Int)) (exists ((v_v_1749_13 Int) (v_v_1753_13 Int) (v_v_1747_13 Int) (v_v_1752_13 Int) (v_v_1751_13 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_1619 .cse0) (= v_v_1753_13 (select |c_#memory_int| v_idx_1619))) (<= 0 (* 2 v_v_1752_13)) (or (= 0 (select |c_#memory_int| v_idx_1614)) (< v_idx_1614 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_1614)) (or (< v_idx_1615 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_1615) (= v_v_1749_13 (select |c_#memory_int| v_idx_1615))) (or (= v_v_1747_13 (select |c_#memory_int| v_idx_1613)) (<= c_ULTIMATE.start_main_p1 v_idx_1613)) (or (< v_idx_1618 c_ULTIMATE.start_main_p3) (= v_v_1752_13 (select |c_#memory_int| v_idx_1618)) (<= .cse0 v_idx_1618)) (or (< v_idx_1617 .cse2) (<= c_ULTIMATE.start_main_p3 v_idx_1617) (= v_v_1751_13 (select |c_#memory_int| v_idx_1617))) (or (< v_idx_1616 c_ULTIMATE.start_main_p2) (<= .cse2 v_idx_1616) (= 0 (select |c_#memory_int| v_idx_1616))) (<= .cse1 c_ULTIMATE.start_main_p2) (<= 0 v_v_1752_13) (<= .cse2 c_ULTIMATE.start_main_p3))))) is different from false [2019-01-08 14:41:44,315 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1621 Int) (v_idx_1620 Int) (v_idx_1626 Int) (v_idx_1625 Int) (v_idx_1624 Int) (v_idx_1623 Int) (v_idx_1622 Int)) (exists ((v_v_1749_13 Int) (v_v_1753_13 Int) (v_v_1747_13 Int) (v_v_1752_13 Int) (v_v_1751_13 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_1752_13)) (or (< v_idx_1625 c_ULTIMATE.start_main_p3) (= v_v_1752_13 (select |c_#memory_int| v_idx_1625)) (<= .cse0 v_idx_1625)) (or (< v_idx_1622 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_1622) (= v_v_1749_13 (select |c_#memory_int| v_idx_1622))) (or (= v_v_1753_13 (select |c_#memory_int| v_idx_1626)) (< v_idx_1626 .cse0)) (or (= v_v_1751_13 (select |c_#memory_int| v_idx_1624)) (<= c_ULTIMATE.start_main_p3 v_idx_1624) (< v_idx_1624 .cse2)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= 0 v_v_1752_13) (or (< v_idx_1621 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1621) 0) (<= .cse1 v_idx_1621)) (or (<= .cse2 v_idx_1623) (< v_idx_1623 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1623))) (or (= v_v_1747_13 (select |c_#memory_int| v_idx_1620)) (<= c_ULTIMATE.start_main_p1 v_idx_1620)) (<= .cse2 c_ULTIMATE.start_main_p3))))) is different from false [2019-01-08 14:41:47,000 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1632 Int) (v_idx_1631 Int) (v_idx_1630 Int) (v_idx_1629 Int) (v_idx_1628 Int) (v_idx_1627 Int) (v_idx_1633 Int)) (exists ((v_v_1753_13 Int) (v_v_1749_13 Int) (v_v_1747_13 Int) (v_v_1751_13 Int) (v_v_1752_13 Int) (v_b_148_13 Int) (v_b_133_13 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_148_13 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1))) (and (or (< v_idx_1630 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_1630) (= 0 (select |c_#memory_int| v_idx_1630))) (<= (+ v_b_148_13 2) c_ULTIMATE.start_main_p3) (or (<= v_b_148_13 v_idx_1627) (= v_v_1747_13 (select |c_#memory_int| v_idx_1627))) (<= 0 v_v_1752_13) (or (= v_v_1751_13 (select |c_#memory_int| v_idx_1631)) (<= c_ULTIMATE.start_main_p3 v_idx_1631) (< v_idx_1631 .cse0)) (<= .cse0 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_1752_13)) (<= .cse1 c_ULTIMATE.start_main_p2) (or (< v_idx_1628 v_b_148_13) (= 0 (select |c_#memory_int| v_idx_1628)) (<= v_b_133_13 v_idx_1628)) (<= v_b_133_13 c_ULTIMATE.start_main_p2) (<= .cse1 v_b_133_13) (<= (+ v_b_133_13 1) c_ULTIMATE.start_main_p3) (<= v_b_133_13 .cse1) (or (< v_idx_1632 c_ULTIMATE.start_main_p3) (<= .cse2 v_idx_1632) (= v_v_1752_13 (select |c_#memory_int| v_idx_1632))) (or (< v_idx_1633 .cse2) (= (select |c_#memory_int| v_idx_1633) v_v_1753_13)) (or (= (select |c_#memory_int| v_idx_1629) v_v_1749_13) (< v_idx_1629 v_b_133_13) (<= c_ULTIMATE.start_main_p2 v_idx_1629)))))) is different from false [2019-01-08 14:41:49,341 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1640 Int) (v_idx_1639 Int) (v_idx_1638 Int) (v_idx_1637 Int) (v_idx_1636 Int) (v_idx_1635 Int) (v_idx_1634 Int)) (exists ((v_v_1749_13 Int) (v_v_1753_13 Int) (v_v_1747_13 Int) (v_b_160_13 Int) (v_b_135_13 Int) (v_v_1752_13 Int) (v_v_1751_13 Int) (v_b_148_13 Int) (v_b_133_13 Int)) (let ((.cse0 (+ v_b_148_13 2)) (.cse2 (+ v_b_160_13 1)) (.cse1 (+ v_b_133_13 1)) (.cse3 (+ v_b_148_13 1)) (.cse4 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse0 v_b_135_13) (<= .cse1 v_b_135_13) (<= .cse2 v_b_135_13) (or (<= v_b_148_13 v_idx_1634) (= v_v_1747_13 (select |c_#memory_int| v_idx_1634))) (or (= 0 (select |c_#memory_int| v_idx_1637)) (< v_idx_1637 v_b_160_13) (<= v_b_135_13 v_idx_1637)) (<= .cse3 v_b_160_13) (<= .cse0 c_ULTIMATE.start_main_p3) (<= .cse2 c_ULTIMATE.start_main_p3) (<= v_b_135_13 .cse2) (or (= 0 (select |c_#memory_int| v_idx_1635)) (< v_idx_1635 v_b_148_13) (<= v_b_133_13 v_idx_1635)) (<= 0 v_v_1752_13) (or (= v_v_1752_13 (select |c_#memory_int| v_idx_1639)) (<= .cse4 v_idx_1639) (< v_idx_1639 c_ULTIMATE.start_main_p3)) (<= v_b_135_13 c_ULTIMATE.start_main_p3) (or (< v_idx_1636 v_b_133_13) (<= v_b_160_13 v_idx_1636) (= v_v_1749_13 (select |c_#memory_int| v_idx_1636))) (<= 0 (* 2 v_v_1752_13)) (<= v_b_133_13 v_b_160_13) (or (= v_v_1751_13 (select |c_#memory_int| v_idx_1638)) (< v_idx_1638 v_b_135_13) (<= c_ULTIMATE.start_main_p3 v_idx_1638)) (<= .cse3 v_b_133_13) (<= .cse1 c_ULTIMATE.start_main_p3) (<= v_b_133_13 .cse3) (or (= v_v_1753_13 (select |c_#memory_int| v_idx_1640)) (< v_idx_1640 .cse4)))))) is different from false [2019-01-08 14:41:49,398 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-08 14:41:49,398 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:41:49,398 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:41:49,399 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [2] total 6 [2019-01-08 14:41:49,399 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:41:49,399 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-08 14:41:49,399 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-08 14:41:49,399 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-08 14:41:49,399 INFO L87 Difference]: Start difference. First operand 25 states and 75 transitions. Second operand 6 states. [2019-01-08 14:41:51,917 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_1632 Int) (v_idx_1631 Int) (v_idx_1630 Int) (v_idx_1629 Int) (v_idx_1628 Int) (v_idx_1627 Int) (v_idx_1633 Int)) (exists ((v_v_1753_13 Int) (v_v_1749_13 Int) (v_v_1747_13 Int) (v_v_1751_13 Int) (v_v_1752_13 Int) (v_b_148_13 Int) (v_b_133_13 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_148_13 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1))) (and (or (< v_idx_1630 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_1630) (= 0 (select |c_#memory_int| v_idx_1630))) (<= (+ v_b_148_13 2) c_ULTIMATE.start_main_p3) (or (<= v_b_148_13 v_idx_1627) (= v_v_1747_13 (select |c_#memory_int| v_idx_1627))) (<= 0 v_v_1752_13) (or (= v_v_1751_13 (select |c_#memory_int| v_idx_1631)) (<= c_ULTIMATE.start_main_p3 v_idx_1631) (< v_idx_1631 .cse0)) (<= .cse0 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_1752_13)) (<= .cse1 c_ULTIMATE.start_main_p2) (or (< v_idx_1628 v_b_148_13) (= 0 (select |c_#memory_int| v_idx_1628)) (<= v_b_133_13 v_idx_1628)) (<= v_b_133_13 c_ULTIMATE.start_main_p2) (<= .cse1 v_b_133_13) (<= (+ v_b_133_13 1) c_ULTIMATE.start_main_p3) (<= v_b_133_13 .cse1) (or (< v_idx_1632 c_ULTIMATE.start_main_p3) (<= .cse2 v_idx_1632) (= v_v_1752_13 (select |c_#memory_int| v_idx_1632))) (or (< v_idx_1633 .cse2) (= (select |c_#memory_int| v_idx_1633) v_v_1753_13)) (or (= (select |c_#memory_int| v_idx_1629) v_v_1749_13) (< v_idx_1629 v_b_133_13) (<= c_ULTIMATE.start_main_p2 v_idx_1629)))))) (forall ((v_idx_1640 Int) (v_idx_1639 Int) (v_idx_1638 Int) (v_idx_1637 Int) (v_idx_1636 Int) (v_idx_1635 Int) (v_idx_1634 Int)) (exists ((v_v_1749_13 Int) (v_v_1753_13 Int) (v_v_1747_13 Int) (v_b_160_13 Int) (v_b_135_13 Int) (v_v_1752_13 Int) (v_v_1751_13 Int) (v_b_148_13 Int) (v_b_133_13 Int)) (let ((.cse3 (+ v_b_148_13 2)) (.cse5 (+ v_b_160_13 1)) (.cse4 (+ v_b_133_13 1)) (.cse6 (+ v_b_148_13 1)) (.cse7 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse3 v_b_135_13) (<= .cse4 v_b_135_13) (<= .cse5 v_b_135_13) (or (<= v_b_148_13 v_idx_1634) (= v_v_1747_13 (select |c_#memory_int| v_idx_1634))) (or (= 0 (select |c_#memory_int| v_idx_1637)) (< v_idx_1637 v_b_160_13) (<= v_b_135_13 v_idx_1637)) (<= .cse6 v_b_160_13) (<= .cse3 c_ULTIMATE.start_main_p3) (<= .cse5 c_ULTIMATE.start_main_p3) (<= v_b_135_13 .cse5) (or (= 0 (select |c_#memory_int| v_idx_1635)) (< v_idx_1635 v_b_148_13) (<= v_b_133_13 v_idx_1635)) (<= 0 v_v_1752_13) (or (= v_v_1752_13 (select |c_#memory_int| v_idx_1639)) (<= .cse7 v_idx_1639) (< v_idx_1639 c_ULTIMATE.start_main_p3)) (<= v_b_135_13 c_ULTIMATE.start_main_p3) (or (< v_idx_1636 v_b_133_13) (<= v_b_160_13 v_idx_1636) (= v_v_1749_13 (select |c_#memory_int| v_idx_1636))) (<= 0 (* 2 v_v_1752_13)) (<= v_b_133_13 v_b_160_13) (or (= v_v_1751_13 (select |c_#memory_int| v_idx_1638)) (< v_idx_1638 v_b_135_13) (<= c_ULTIMATE.start_main_p3 v_idx_1638)) (<= .cse6 v_b_133_13) (<= .cse4 c_ULTIMATE.start_main_p3) (<= v_b_133_13 .cse6) (or (= v_v_1753_13 (select |c_#memory_int| v_idx_1640)) (< v_idx_1640 .cse7)))))) (forall ((v_idx_1619 Int) (v_idx_1618 Int) (v_idx_1617 Int) (v_idx_1616 Int) (v_idx_1615 Int) (v_idx_1614 Int) (v_idx_1613 Int)) (exists ((v_v_1749_13 Int) (v_v_1753_13 Int) (v_v_1747_13 Int) (v_v_1752_13 Int) (v_v_1751_13 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p3 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 1)) (.cse10 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_1619 .cse8) (= v_v_1753_13 (select |c_#memory_int| v_idx_1619))) (<= 0 (* 2 v_v_1752_13)) (or (= 0 (select |c_#memory_int| v_idx_1614)) (< v_idx_1614 c_ULTIMATE.start_main_p1) (<= .cse9 v_idx_1614)) (or (< v_idx_1615 .cse9) (<= c_ULTIMATE.start_main_p2 v_idx_1615) (= v_v_1749_13 (select |c_#memory_int| v_idx_1615))) (or (= v_v_1747_13 (select |c_#memory_int| v_idx_1613)) (<= c_ULTIMATE.start_main_p1 v_idx_1613)) (or (< v_idx_1618 c_ULTIMATE.start_main_p3) (= v_v_1752_13 (select |c_#memory_int| v_idx_1618)) (<= .cse8 v_idx_1618)) (or (< v_idx_1617 .cse10) (<= c_ULTIMATE.start_main_p3 v_idx_1617) (= v_v_1751_13 (select |c_#memory_int| v_idx_1617))) (or (< v_idx_1616 c_ULTIMATE.start_main_p2) (<= .cse10 v_idx_1616) (= 0 (select |c_#memory_int| v_idx_1616))) (<= .cse9 c_ULTIMATE.start_main_p2) (<= 0 v_v_1752_13) (<= .cse10 c_ULTIMATE.start_main_p3))))) (forall ((v_idx_1621 Int) (v_idx_1620 Int) (v_idx_1626 Int) (v_idx_1625 Int) (v_idx_1624 Int) (v_idx_1623 Int) (v_idx_1622 Int)) (exists ((v_v_1749_13 Int) (v_v_1753_13 Int) (v_v_1747_13 Int) (v_v_1752_13 Int) (v_v_1751_13 Int)) (let ((.cse11 (+ c_ULTIMATE.start_main_p3 1)) (.cse12 (+ c_ULTIMATE.start_main_p1 1)) (.cse13 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_1752_13)) (or (< v_idx_1625 c_ULTIMATE.start_main_p3) (= v_v_1752_13 (select |c_#memory_int| v_idx_1625)) (<= .cse11 v_idx_1625)) (or (< v_idx_1622 .cse12) (<= c_ULTIMATE.start_main_p2 v_idx_1622) (= v_v_1749_13 (select |c_#memory_int| v_idx_1622))) (or (= v_v_1753_13 (select |c_#memory_int| v_idx_1626)) (< v_idx_1626 .cse11)) (or (= v_v_1751_13 (select |c_#memory_int| v_idx_1624)) (<= c_ULTIMATE.start_main_p3 v_idx_1624) (< v_idx_1624 .cse13)) (<= .cse12 c_ULTIMATE.start_main_p2) (<= 0 v_v_1752_13) (or (< v_idx_1621 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1621) 0) (<= .cse12 v_idx_1621)) (or (<= .cse13 v_idx_1623) (< v_idx_1623 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1623))) (or (= v_v_1747_13 (select |c_#memory_int| v_idx_1620)) (<= c_ULTIMATE.start_main_p1 v_idx_1620)) (<= .cse13 c_ULTIMATE.start_main_p3)))))) is different from false [2019-01-08 14:42:05,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:42:05,403 INFO L93 Difference]: Finished difference Result 28 states and 77 transitions. [2019-01-08 14:42:05,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-08 14:42:05,404 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2019-01-08 14:42:05,404 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:42:05,404 INFO L225 Difference]: With dead ends: 28 [2019-01-08 14:42:05,404 INFO L226 Difference]: Without dead ends: 25 [2019-01-08 14:42:05,405 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.4s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-08 14:42:05,405 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-01-08 14:42:05,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-01-08 14:42:05,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-01-08 14:42:05,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 74 transitions. [2019-01-08 14:42:05,436 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 74 transitions. Word has length 5 [2019-01-08 14:42:05,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:42:05,436 INFO L480 AbstractCegarLoop]: Abstraction has 25 states and 74 transitions. [2019-01-08 14:42:05,437 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-01-08 14:42:05,437 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 74 transitions. [2019-01-08 14:42:05,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-08 14:42:05,437 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:42:05,437 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-08 14:42:05,437 INFO L423 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:42:05,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:42:05,437 INFO L82 PathProgramCache]: Analyzing trace with hash 28992922, now seen corresponding path program 2 times [2019-01-08 14:42:05,437 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:42:05,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:42:05,438 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:42:05,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:42:05,438 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:42:05,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:42:05,564 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:42:05,564 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:42:05,564 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:42:05,564 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-08 14:42:05,565 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-08 14:42:05,565 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:42:05,565 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-08 14:42:05,576 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-08 14:42:05,577 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-08 14:42:05,585 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-08 14:42:05,585 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-08 14:42:05,585 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-08 14:42:05,588 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-08 14:42:05,596 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:42:05,596 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-08 14:42:05,600 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:42:05,601 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:42:05,601 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-08 14:42:05,602 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-08 14:42:05,620 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:42:05,637 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:42:05,650 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:42:05,651 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:19, output treesize:22 [2019-01-08 14:42:05,709 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:42:05,721 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:42:05,744 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:42:05,767 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:42:05,768 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-08 14:42:05,768 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:42:05,793 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:42:05,793 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-08 14:42:05,813 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:42:05,814 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:42:05,815 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:42:05,815 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:42:05,816 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:42:05,816 INFO L683 Elim1Store]: detected equality via solver [2019-01-08 14:42:05,817 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-08 14:42:05,818 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:42:05,835 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:42:05,836 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-08 14:42:05,853 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:42:05,853 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-08 14:42:05,884 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:42:05,904 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-08 14:42:05,904 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 9 [2019-01-08 14:42:05,904 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-08 14:42:05,904 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-01-08 14:42:05,904 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-01-08 14:42:05,904 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=67, Unknown=0, NotChecked=0, Total=110 [2019-01-08 14:42:05,905 INFO L87 Difference]: Start difference. First operand 25 states and 74 transitions. Second operand 8 states. [2019-01-08 14:42:06,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:42:06,142 INFO L93 Difference]: Finished difference Result 37 states and 97 transitions. [2019-01-08 14:42:06,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-08 14:42:06,142 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 5 [2019-01-08 14:42:06,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:42:06,143 INFO L225 Difference]: With dead ends: 37 [2019-01-08 14:42:06,143 INFO L226 Difference]: Without dead ends: 36 [2019-01-08 14:42:06,144 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=61, Invalid=95, Unknown=0, NotChecked=0, Total=156 [2019-01-08 14:42:06,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-01-08 14:42:06,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 27. [2019-01-08 14:42:06,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2019-01-08 14:42:06,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 82 transitions. [2019-01-08 14:42:06,180 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 82 transitions. Word has length 5 [2019-01-08 14:42:06,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:42:06,180 INFO L480 AbstractCegarLoop]: Abstraction has 27 states and 82 transitions. [2019-01-08 14:42:06,180 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-01-08 14:42:06,180 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 82 transitions. [2019-01-08 14:42:06,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-08 14:42:06,181 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:42:06,181 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-08 14:42:06,181 INFO L423 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:42:06,181 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:42:06,181 INFO L82 PathProgramCache]: Analyzing trace with hash 28992734, now seen corresponding path program 1 times [2019-01-08 14:42:06,182 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:42:06,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:42:06,182 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-08 14:42:06,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:42:06,182 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:42:06,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:42:06,398 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:42:06,399 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:42:06,399 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:42:06,399 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-08 14:42:06,399 INFO L207 CegarAbsIntRunner]: [0], [6], [10], [12], [15] [2019-01-08 14:42:06,400 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:42:06,401 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:42:24,540 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:42:24,541 INFO L272 AbstractInterpreter]: Visited 5 different actions 57 times. Merged at 3 different actions 13 times. Widened at 3 different actions 9 times. Found 29 fixpoints after 3 different actions. Largest state had 0 variables. [2019-01-08 14:42:24,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:42:24,541 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:42:24,993 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 57.14% of their original sizes. [2019-01-08 14:42:24,994 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:42:27,509 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1775 Int) (v_idx_1774 Int) (v_idx_1773 Int) (v_idx_1779 Int) (v_idx_1778 Int) (v_idx_1777 Int) (v_idx_1776 Int)) (exists ((v_v_6178_1 Int) (v_v_6179_1 Int) (v_v_6180_1 Int) (v_v_6183_1 Int) (v_v_6181_1 Int) (v_v_6182_1 Int) (v_v_6177_1 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (+ v_v_6178_1 v_v_6182_1)) (or (< v_idx_1778 c_ULTIMATE.start_main_p3) (<= .cse0 v_idx_1778) (= v_v_6182_1 (select |c_#memory_int| v_idx_1778))) (or (< v_idx_1777 .cse1) (= v_v_6181_1 (select |c_#memory_int| v_idx_1777)) (<= c_ULTIMATE.start_main_p3 v_idx_1777)) (or (< v_idx_1775 .cse2) (<= c_ULTIMATE.start_main_p2 v_idx_1775) (= v_v_6179_1 (select |c_#memory_int| v_idx_1775))) (<= v_v_6180_1 v_v_6178_1) (<= .cse1 c_ULTIMATE.start_main_p3) (or (= v_v_6177_1 (select |c_#memory_int| v_idx_1773)) (<= c_ULTIMATE.start_main_p1 v_idx_1773)) (<= 0 (* 2 v_v_6178_1)) (<= 0 (* 2 v_v_6182_1)) (or (<= .cse1 v_idx_1776) (< v_idx_1776 c_ULTIMATE.start_main_p2) (= v_v_6180_1 (select |c_#memory_int| v_idx_1776))) (<= (* 2 v_v_6180_1) 0) (or (< v_idx_1779 .cse0) (= v_v_6183_1 (select |c_#memory_int| v_idx_1779))) (<= .cse2 c_ULTIMATE.start_main_p2) (<= v_v_6180_1 v_v_6182_1) (or (= v_v_6178_1 (select |c_#memory_int| v_idx_1774)) (<= .cse2 v_idx_1774) (< v_idx_1774 c_ULTIMATE.start_main_p1)))))) is different from false [2019-01-08 14:42:29,856 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1786 Int) (v_idx_1785 Int) (v_idx_1784 Int) (v_idx_1783 Int) (v_idx_1782 Int) (v_idx_1781 Int) (v_idx_1780 Int)) (exists ((v_v_6178_1 Int) (v_v_6179_1 Int) (v_v_6180_1 Int) (v_v_6183_1 Int) (v_v_6181_1 Int) (v_v_6182_1 Int) (v_v_6177_1 Int) (v_b_507_4 Int) (v_b_506_4 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_506_4 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= 0 (+ v_v_6178_1 v_v_6182_1)) (or (< v_idx_1786 v_b_507_4) (= v_v_6183_1 (select |c_#memory_int| v_idx_1786))) (<= v_v_6180_1 v_v_6178_1) (or (= v_v_6177_1 (select |c_#memory_int| v_idx_1780)) (<= c_ULTIMATE.start_main_p1 v_idx_1780)) (or (< v_idx_1782 .cse0) (= v_v_6179_1 (select |c_#memory_int| v_idx_1782)) (<= c_ULTIMATE.start_main_p2 v_idx_1782)) (<= 0 (* 2 v_v_6178_1)) (<= 0 (* 2 v_v_6182_1)) (<= .cse1 v_b_506_4) (or (<= v_b_506_4 v_idx_1784) (= v_v_6181_1 (select |c_#memory_int| v_idx_1784)) (< v_idx_1784 .cse1)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_507_4) (<= v_b_507_4 .cse2) (or (= v_v_6178_1 (select |c_#memory_int| v_idx_1781)) (<= .cse0 v_idx_1781) (< v_idx_1781 c_ULTIMATE.start_main_p1)) (<= (* 2 v_v_6180_1) 0) (or (= v_v_6182_1 (select |c_#memory_int| v_idx_1785)) (< v_idx_1785 v_b_506_4) (<= v_b_507_4 v_idx_1785)) (or (<= .cse1 v_idx_1783) (< v_idx_1783 c_ULTIMATE.start_main_p2) (= v_v_6180_1 (select |c_#memory_int| v_idx_1783))) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_506_4) (<= .cse2 v_b_507_4) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_v_6180_1 v_v_6182_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_507_4))))) is different from false [2019-01-08 14:42:32,019 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1793 Int) (v_idx_1792 Int) (v_idx_1791 Int) (v_idx_1790 Int) (v_idx_1789 Int) (v_idx_1788 Int) (v_idx_1787 Int)) (exists ((v_v_6178_1 Int) (v_v_6179_1 Int) (v_v_6180_1 Int) (v_v_6183_1 Int) (v_v_6181_1 Int) (v_v_6182_1 Int) (v_v_6177_1 Int) (v_b_507_4 Int) (v_b_506_4 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_506_4 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_1787) (= v_v_6177_1 (select |c_#memory_int| v_idx_1787))) (<= 0 (+ v_v_6178_1 v_v_6182_1)) (or (= v_v_6180_1 (select |c_#memory_int| v_idx_1790)) (<= .cse0 v_idx_1790) (< v_idx_1790 c_ULTIMATE.start_main_p2)) (or (= v_v_6183_1 (select |c_#memory_int| v_idx_1793)) (< v_idx_1793 v_b_507_4)) (or (< v_idx_1791 .cse0) (<= v_b_506_4 v_idx_1791) (= v_v_6181_1 (select |c_#memory_int| v_idx_1791))) (or (< v_idx_1788 c_ULTIMATE.start_main_p1) (= v_v_6178_1 (select |c_#memory_int| v_idx_1788)) (<= .cse1 v_idx_1788)) (<= v_v_6180_1 v_v_6178_1) (<= 0 (* 2 v_v_6178_1)) (<= 0 (* 2 v_v_6182_1)) (<= .cse0 v_b_506_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_507_4) (<= v_b_507_4 .cse2) (<= (* 2 v_v_6180_1) 0) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_506_4) (<= .cse2 v_b_507_4) (<= .cse1 c_ULTIMATE.start_main_p2) (<= v_v_6180_1 v_v_6182_1) (or (< v_idx_1789 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_1789) (= v_v_6179_1 (select |c_#memory_int| v_idx_1789))) (or (= v_v_6182_1 (select |c_#memory_int| v_idx_1792)) (< v_idx_1792 v_b_506_4) (<= v_b_507_4 v_idx_1792)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_507_4))))) is different from false [2019-01-08 14:42:35,656 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1797 Int) (v_idx_1796 Int) (v_idx_1795 Int) (v_idx_1794 Int) (v_idx_1800 Int) (v_idx_1799 Int) (v_idx_1798 Int)) (exists ((v_v_6178_1 Int) (v_v_6179_1 Int) (v_v_6180_1 Int) (v_v_6183_1 Int) (v_v_6181_1 Int) (v_v_6182_1 Int) (v_b_505_4 Int) (v_b_504_4 Int) (v_v_6177_1 Int) (v_b_507_4 Int) (v_b_506_4 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 2)) (.cse1 (+ v_b_504_4 1)) (.cse2 (+ v_b_506_4 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= 0 (+ v_v_6178_1 v_v_6182_1)) (<= (+ v_b_505_4 1) v_b_507_4) (<= .cse0 v_b_504_4) (<= v_b_505_4 .cse1) (or (<= c_ULTIMATE.start_main_p1 v_idx_1794) (= v_v_6177_1 (select |c_#memory_int| v_idx_1794))) (or (< v_idx_1798 v_b_505_4) (<= v_b_506_4 v_idx_1798) (= v_v_6181_1 (select |c_#memory_int| v_idx_1798))) (or (<= .cse0 v_idx_1795) (< v_idx_1795 c_ULTIMATE.start_main_p1) (= v_v_6178_1 (select |c_#memory_int| v_idx_1795))) (<= 0 (* 2 v_v_6178_1)) (or (< v_idx_1797 v_b_504_4) (= v_v_6180_1 (select |c_#memory_int| v_idx_1797)) (<= v_b_505_4 v_idx_1797)) (<= v_b_507_4 .cse2) (<= .cse3 v_b_506_4) (or (= v_v_6183_1 (select |c_#memory_int| v_idx_1800)) (< v_idx_1800 v_b_507_4)) (<= v_v_6180_1 v_v_6178_1) (<= (+ v_b_504_4 2) v_b_507_4) (<= .cse3 v_b_505_4) (<= .cse1 v_b_505_4) (<= 0 (* 2 v_v_6182_1)) (or (<= v_b_507_4 v_idx_1799) (= v_v_6182_1 (select |c_#memory_int| v_idx_1799)) (< v_idx_1799 v_b_506_4)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_507_4) (<= v_b_505_4 v_b_506_4) (<= (* 2 v_v_6180_1) 0) (<= .cse1 v_b_506_4) (<= .cse2 v_b_507_4) (<= v_v_6180_1 v_v_6182_1) (or (< v_idx_1796 .cse0) (<= v_b_504_4 v_idx_1796) (= v_v_6179_1 (select |c_#memory_int| v_idx_1796))))))) is different from false [2019-01-08 14:42:35,747 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-08 14:42:35,747 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:42:35,747 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:42:35,747 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 8 [2019-01-08 14:42:35,747 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:42:35,747 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-08 14:42:35,748 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-08 14:42:35,748 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-08 14:42:35,748 INFO L87 Difference]: Start difference. First operand 27 states and 82 transitions. Second operand 6 states. [2019-01-08 14:42:38,604 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_1786 Int) (v_idx_1785 Int) (v_idx_1784 Int) (v_idx_1783 Int) (v_idx_1782 Int) (v_idx_1781 Int) (v_idx_1780 Int)) (exists ((v_v_6178_1 Int) (v_v_6179_1 Int) (v_v_6180_1 Int) (v_v_6183_1 Int) (v_v_6181_1 Int) (v_v_6182_1 Int) (v_v_6177_1 Int) (v_b_507_4 Int) (v_b_506_4 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_506_4 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= 0 (+ v_v_6178_1 v_v_6182_1)) (or (< v_idx_1786 v_b_507_4) (= v_v_6183_1 (select |c_#memory_int| v_idx_1786))) (<= v_v_6180_1 v_v_6178_1) (or (= v_v_6177_1 (select |c_#memory_int| v_idx_1780)) (<= c_ULTIMATE.start_main_p1 v_idx_1780)) (or (< v_idx_1782 .cse0) (= v_v_6179_1 (select |c_#memory_int| v_idx_1782)) (<= c_ULTIMATE.start_main_p2 v_idx_1782)) (<= 0 (* 2 v_v_6178_1)) (<= 0 (* 2 v_v_6182_1)) (<= .cse1 v_b_506_4) (or (<= v_b_506_4 v_idx_1784) (= v_v_6181_1 (select |c_#memory_int| v_idx_1784)) (< v_idx_1784 .cse1)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_507_4) (<= v_b_507_4 .cse2) (or (= v_v_6178_1 (select |c_#memory_int| v_idx_1781)) (<= .cse0 v_idx_1781) (< v_idx_1781 c_ULTIMATE.start_main_p1)) (<= (* 2 v_v_6180_1) 0) (or (= v_v_6182_1 (select |c_#memory_int| v_idx_1785)) (< v_idx_1785 v_b_506_4) (<= v_b_507_4 v_idx_1785)) (or (<= .cse1 v_idx_1783) (< v_idx_1783 c_ULTIMATE.start_main_p2) (= v_v_6180_1 (select |c_#memory_int| v_idx_1783))) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_506_4) (<= .cse2 v_b_507_4) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_v_6180_1 v_v_6182_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_507_4))))) (forall ((v_idx_1793 Int) (v_idx_1792 Int) (v_idx_1791 Int) (v_idx_1790 Int) (v_idx_1789 Int) (v_idx_1788 Int) (v_idx_1787 Int)) (exists ((v_v_6178_1 Int) (v_v_6179_1 Int) (v_v_6180_1 Int) (v_v_6183_1 Int) (v_v_6181_1 Int) (v_v_6182_1 Int) (v_v_6177_1 Int) (v_b_507_4 Int) (v_b_506_4 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ v_b_506_4 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_1787) (= v_v_6177_1 (select |c_#memory_int| v_idx_1787))) (<= 0 (+ v_v_6178_1 v_v_6182_1)) (or (= v_v_6180_1 (select |c_#memory_int| v_idx_1790)) (<= .cse3 v_idx_1790) (< v_idx_1790 c_ULTIMATE.start_main_p2)) (or (= v_v_6183_1 (select |c_#memory_int| v_idx_1793)) (< v_idx_1793 v_b_507_4)) (or (< v_idx_1791 .cse3) (<= v_b_506_4 v_idx_1791) (= v_v_6181_1 (select |c_#memory_int| v_idx_1791))) (or (< v_idx_1788 c_ULTIMATE.start_main_p1) (= v_v_6178_1 (select |c_#memory_int| v_idx_1788)) (<= .cse4 v_idx_1788)) (<= v_v_6180_1 v_v_6178_1) (<= 0 (* 2 v_v_6178_1)) (<= 0 (* 2 v_v_6182_1)) (<= .cse3 v_b_506_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_507_4) (<= v_b_507_4 .cse5) (<= (* 2 v_v_6180_1) 0) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_506_4) (<= .cse5 v_b_507_4) (<= .cse4 c_ULTIMATE.start_main_p2) (<= v_v_6180_1 v_v_6182_1) (or (< v_idx_1789 .cse4) (<= c_ULTIMATE.start_main_p2 v_idx_1789) (= v_v_6179_1 (select |c_#memory_int| v_idx_1789))) (or (= v_v_6182_1 (select |c_#memory_int| v_idx_1792)) (< v_idx_1792 v_b_506_4) (<= v_b_507_4 v_idx_1792)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_507_4))))) (forall ((v_idx_1775 Int) (v_idx_1774 Int) (v_idx_1773 Int) (v_idx_1779 Int) (v_idx_1778 Int) (v_idx_1777 Int) (v_idx_1776 Int)) (exists ((v_v_6178_1 Int) (v_v_6179_1 Int) (v_v_6180_1 Int) (v_v_6183_1 Int) (v_v_6181_1 Int) (v_v_6182_1 Int) (v_v_6177_1 Int)) (let ((.cse7 (+ c_ULTIMATE.start_main_p2 1)) (.cse6 (+ c_ULTIMATE.start_main_p3 1)) (.cse8 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (+ v_v_6178_1 v_v_6182_1)) (or (< v_idx_1778 c_ULTIMATE.start_main_p3) (<= .cse6 v_idx_1778) (= v_v_6182_1 (select |c_#memory_int| v_idx_1778))) (or (< v_idx_1777 .cse7) (= v_v_6181_1 (select |c_#memory_int| v_idx_1777)) (<= c_ULTIMATE.start_main_p3 v_idx_1777)) (or (< v_idx_1775 .cse8) (<= c_ULTIMATE.start_main_p2 v_idx_1775) (= v_v_6179_1 (select |c_#memory_int| v_idx_1775))) (<= v_v_6180_1 v_v_6178_1) (<= .cse7 c_ULTIMATE.start_main_p3) (or (= v_v_6177_1 (select |c_#memory_int| v_idx_1773)) (<= c_ULTIMATE.start_main_p1 v_idx_1773)) (<= 0 (* 2 v_v_6178_1)) (<= 0 (* 2 v_v_6182_1)) (or (<= .cse7 v_idx_1776) (< v_idx_1776 c_ULTIMATE.start_main_p2) (= v_v_6180_1 (select |c_#memory_int| v_idx_1776))) (<= (* 2 v_v_6180_1) 0) (or (< v_idx_1779 .cse6) (= v_v_6183_1 (select |c_#memory_int| v_idx_1779))) (<= .cse8 c_ULTIMATE.start_main_p2) (<= v_v_6180_1 v_v_6182_1) (or (= v_v_6178_1 (select |c_#memory_int| v_idx_1774)) (<= .cse8 v_idx_1774) (< v_idx_1774 c_ULTIMATE.start_main_p1)))))) (forall ((v_idx_1797 Int) (v_idx_1796 Int) (v_idx_1795 Int) (v_idx_1794 Int) (v_idx_1800 Int) (v_idx_1799 Int) (v_idx_1798 Int)) (exists ((v_v_6178_1 Int) (v_v_6179_1 Int) (v_v_6180_1 Int) (v_v_6183_1 Int) (v_v_6181_1 Int) (v_v_6182_1 Int) (v_b_505_4 Int) (v_b_504_4 Int) (v_v_6177_1 Int) (v_b_507_4 Int) (v_b_506_4 Int)) (let ((.cse12 (+ c_ULTIMATE.start_main_p1 2)) (.cse10 (+ v_b_504_4 1)) (.cse11 (+ v_b_506_4 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 1))) (and (<= 0 (+ v_v_6178_1 v_v_6182_1)) (<= (+ v_b_505_4 1) v_b_507_4) (<= .cse9 v_b_504_4) (<= v_b_505_4 .cse10) (or (<= c_ULTIMATE.start_main_p1 v_idx_1794) (= v_v_6177_1 (select |c_#memory_int| v_idx_1794))) (or (< v_idx_1798 v_b_505_4) (<= v_b_506_4 v_idx_1798) (= v_v_6181_1 (select |c_#memory_int| v_idx_1798))) (or (<= .cse9 v_idx_1795) (< v_idx_1795 c_ULTIMATE.start_main_p1) (= v_v_6178_1 (select |c_#memory_int| v_idx_1795))) (<= 0 (* 2 v_v_6178_1)) (or (< v_idx_1797 v_b_504_4) (= v_v_6180_1 (select |c_#memory_int| v_idx_1797)) (<= v_b_505_4 v_idx_1797)) (<= v_b_507_4 .cse11) (<= .cse12 v_b_506_4) (or (= v_v_6183_1 (select |c_#memory_int| v_idx_1800)) (< v_idx_1800 v_b_507_4)) (<= v_v_6180_1 v_v_6178_1) (<= (+ v_b_504_4 2) v_b_507_4) (<= .cse12 v_b_505_4) (<= .cse10 v_b_505_4) (<= 0 (* 2 v_v_6182_1)) (or (<= v_b_507_4 v_idx_1799) (= v_v_6182_1 (select |c_#memory_int| v_idx_1799)) (< v_idx_1799 v_b_506_4)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_507_4) (<= v_b_505_4 v_b_506_4) (<= (* 2 v_v_6180_1) 0) (<= .cse10 v_b_506_4) (<= .cse11 v_b_507_4) (<= v_v_6180_1 v_v_6182_1) (or (< v_idx_1796 .cse9) (<= v_b_504_4 v_idx_1796) (= v_v_6179_1 (select |c_#memory_int| v_idx_1796)))))))) is different from false [2019-01-08 14:43:21,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:43:21,560 INFO L93 Difference]: Finished difference Result 31 states and 95 transitions. [2019-01-08 14:43:21,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-08 14:43:21,560 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2019-01-08 14:43:21,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:43:21,560 INFO L225 Difference]: With dead ends: 31 [2019-01-08 14:43:21,560 INFO L226 Difference]: Without dead ends: 30 [2019-01-08 14:43:21,561 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 13.2s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-08 14:43:21,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2019-01-08 14:43:21,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 29. [2019-01-08 14:43:21,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-01-08 14:43:21,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 90 transitions. [2019-01-08 14:43:21,602 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 90 transitions. Word has length 5 [2019-01-08 14:43:21,603 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:43:21,603 INFO L480 AbstractCegarLoop]: Abstraction has 29 states and 90 transitions. [2019-01-08 14:43:21,603 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-01-08 14:43:21,603 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 90 transitions. [2019-01-08 14:43:21,603 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-08 14:43:21,603 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:43:21,603 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-08 14:43:21,604 INFO L423 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:43:21,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:43:21,604 INFO L82 PathProgramCache]: Analyzing trace with hash 28996766, now seen corresponding path program 2 times [2019-01-08 14:43:21,604 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:43:21,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:43:21,605 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:43:21,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:43:21,605 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:43:21,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:43:21,694 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:43:21,694 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:43:21,695 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:43:21,695 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-08 14:43:21,695 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-08 14:43:21,695 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:43:21,695 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-08 14:43:21,705 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-08 14:43:21,705 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-08 14:43:21,727 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-08 14:43:21,727 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-08 14:43:21,728 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-08 14:43:21,730 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-08 14:43:21,733 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 17 [2019-01-08 14:43:21,738 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:21,739 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 20 [2019-01-08 14:43:21,740 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-08 14:43:21,752 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:43:21,757 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:43:21,766 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:43:21,766 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:16, output treesize:19 [2019-01-08 14:43:21,789 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:21,822 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:21,823 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 21 [2019-01-08 14:43:21,823 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:43:21,835 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:43:21,835 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:24, output treesize:14 [2019-01-08 14:43:21,874 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:21,875 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:21,877 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:21,878 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:21,878 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 27 [2019-01-08 14:43:21,879 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:43:21,888 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:43:21,889 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:24, output treesize:14 [2019-01-08 14:43:21,902 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:43:21,902 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-08 14:43:21,932 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:43:21,952 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-08 14:43:21,952 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 8 [2019-01-08 14:43:21,952 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-08 14:43:21,952 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-01-08 14:43:21,952 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-01-08 14:43:21,953 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=51, Unknown=0, NotChecked=0, Total=90 [2019-01-08 14:43:21,953 INFO L87 Difference]: Start difference. First operand 29 states and 90 transitions. Second operand 8 states. [2019-01-08 14:43:22,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:43:22,127 INFO L93 Difference]: Finished difference Result 46 states and 132 transitions. [2019-01-08 14:43:22,127 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-01-08 14:43:22,127 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 5 [2019-01-08 14:43:22,127 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:43:22,128 INFO L225 Difference]: With dead ends: 46 [2019-01-08 14:43:22,128 INFO L226 Difference]: Without dead ends: 45 [2019-01-08 14:43:22,129 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=63, Unknown=0, NotChecked=0, Total=110 [2019-01-08 14:43:22,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2019-01-08 14:43:22,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 37. [2019-01-08 14:43:22,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2019-01-08 14:43:22,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 125 transitions. [2019-01-08 14:43:22,179 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 125 transitions. Word has length 5 [2019-01-08 14:43:22,179 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:43:22,179 INFO L480 AbstractCegarLoop]: Abstraction has 37 states and 125 transitions. [2019-01-08 14:43:22,179 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-01-08 14:43:22,179 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 125 transitions. [2019-01-08 14:43:22,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-08 14:43:22,180 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:43:22,180 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1] [2019-01-08 14:43:22,180 INFO L423 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:43:22,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:43:22,180 INFO L82 PathProgramCache]: Analyzing trace with hash 893239506, now seen corresponding path program 2 times [2019-01-08 14:43:22,181 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:43:22,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:43:22,181 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-08 14:43:22,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:43:22,181 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:43:22,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:43:22,235 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-08 14:43:22,236 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:43:22,236 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:43:22,236 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-08 14:43:22,236 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-08 14:43:22,236 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:43:22,237 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-08 14:43:22,246 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-08 14:43:22,246 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-08 14:43:22,250 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-08 14:43:22,250 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-08 14:43:22,252 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-08 14:43:22,254 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-08 14:43:22,260 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:22,261 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-08 14:43:22,292 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:22,293 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:22,293 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-08 14:43:22,294 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-08 14:43:22,305 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:43:22,312 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:43:22,322 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:43:22,323 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:19, output treesize:22 [2019-01-08 14:43:22,336 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:22,337 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:22,338 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:22,339 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:22,340 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 28 [2019-01-08 14:43:22,341 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:43:22,359 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:43:22,359 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-08 14:43:22,374 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:22,375 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:22,376 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:22,377 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:22,378 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:22,379 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:43:22,380 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 40 [2019-01-08 14:43:22,381 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:43:22,399 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:43:22,399 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-08 14:43:22,414 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:43:22,414 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-08 14:43:22,431 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:43:22,451 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-01-08 14:43:22,451 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [2, 3] total 8 [2019-01-08 14:43:22,451 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:43:22,451 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-08 14:43:22,451 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-08 14:43:22,452 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=49, Unknown=0, NotChecked=0, Total=90 [2019-01-08 14:43:22,452 INFO L87 Difference]: Start difference. First operand 37 states and 125 transitions. Second operand 5 states. [2019-01-08 14:43:22,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:43:22,531 INFO L93 Difference]: Finished difference Result 40 states and 127 transitions. [2019-01-08 14:43:22,533 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-08 14:43:22,533 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 6 [2019-01-08 14:43:22,533 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:43:22,534 INFO L225 Difference]: With dead ends: 40 [2019-01-08 14:43:22,534 INFO L226 Difference]: Without dead ends: 37 [2019-01-08 14:43:22,534 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=49, Unknown=0, NotChecked=0, Total=90 [2019-01-08 14:43:22,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2019-01-08 14:43:22,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 36. [2019-01-08 14:43:22,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-01-08 14:43:22,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 117 transitions. [2019-01-08 14:43:22,579 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 117 transitions. Word has length 6 [2019-01-08 14:43:22,579 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:43:22,579 INFO L480 AbstractCegarLoop]: Abstraction has 36 states and 117 transitions. [2019-01-08 14:43:22,579 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-08 14:43:22,579 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 117 transitions. [2019-01-08 14:43:22,580 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-08 14:43:22,580 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:43:22,580 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2019-01-08 14:43:22,580 INFO L423 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:43:22,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:43:22,581 INFO L82 PathProgramCache]: Analyzing trace with hash 893358670, now seen corresponding path program 1 times [2019-01-08 14:43:22,581 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:43:22,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:43:22,581 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-08 14:43:22,582 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:43:22,582 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:43:22,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:43:22,683 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-08 14:43:22,683 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:43:22,683 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:43:22,683 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 7 with the following transitions: [2019-01-08 14:43:22,684 INFO L207 CegarAbsIntRunner]: [0], [6], [10], [16], [18], [19] [2019-01-08 14:43:22,685 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:43:22,685 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:43:42,348 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:43:42,348 INFO L272 AbstractInterpreter]: Visited 6 different actions 49 times. Merged at 4 different actions 25 times. Widened at 2 different actions 7 times. Found 12 fixpoints after 3 different actions. Largest state had 0 variables. [2019-01-08 14:43:42,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:43:42,349 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:43:42,926 INFO L227 lantSequenceWeakener]: Weakened 5 states. On average, predicates are now at 51.43% of their original sizes. [2019-01-08 14:43:42,926 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:43:45,377 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1972 Int) (v_idx_1971 Int) (v_idx_1970 Int) (v_idx_1969 Int) (v_idx_1968 Int) (v_idx_1967 Int) (v_idx_1966 Int)) (exists ((v_v_5814_4 Int) (v_v_5813_5 Int) (v_v_5816_4 Int) (v_v_5815_4 Int) (v_v_5817_5 Int) (v_v_5819_5 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= .cse0 v_idx_1967) (< v_idx_1967 c_ULTIMATE.start_main_p1) (= v_v_5814_4 (select |c_#memory_int| v_idx_1967))) (<= 0 (* 2 v_v_5814_4)) (or (= v_v_5817_5 (select |c_#memory_int| v_idx_1970)) (<= c_ULTIMATE.start_main_p3 v_idx_1970) (< v_idx_1970 .cse1)) (or (<= .cse2 v_idx_1971) (= 0 (select |c_#memory_int| v_idx_1971)) (< v_idx_1971 c_ULTIMATE.start_main_p3)) (<= v_v_5816_4 v_v_5814_4) (<= v_v_5816_4 0) (<= .cse1 c_ULTIMATE.start_main_p3) (<= (* 2 v_v_5816_4) 0) (or (= v_v_5815_4 (select |c_#memory_int| v_idx_1968)) (<= c_ULTIMATE.start_main_p2 v_idx_1968) (< v_idx_1968 .cse0)) (or (= v_v_5813_5 (select |c_#memory_int| v_idx_1966)) (<= c_ULTIMATE.start_main_p1 v_idx_1966)) (<= 0 v_v_5814_4) (<= .cse0 c_ULTIMATE.start_main_p2) (or (<= .cse1 v_idx_1969) (< v_idx_1969 c_ULTIMATE.start_main_p2) (= v_v_5816_4 (select |c_#memory_int| v_idx_1969))) (or (< v_idx_1972 .cse2) (= v_v_5819_5 (select |c_#memory_int| v_idx_1972))))))) is different from false [2019-01-08 14:43:48,011 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1973 Int) (v_idx_1979 Int) (v_idx_1978 Int) (v_idx_1977 Int) (v_idx_1976 Int) (v_idx_1975 Int) (v_idx_1974 Int)) (exists ((v_v_5814_4 Int) (v_v_5813_5 Int) (v_v_5816_4 Int) (v_v_5815_4 Int) (v_v_5817_5 Int) (v_v_5819_5 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_1978) 0) (<= .cse0 v_idx_1978) (< v_idx_1978 c_ULTIMATE.start_main_p3)) (<= 0 (* 2 v_v_5814_4)) (or (= v_v_5817_5 (select |c_#memory_int| v_idx_1977)) (<= c_ULTIMATE.start_main_p3 v_idx_1977) (< v_idx_1977 .cse1)) (or (= v_v_5819_5 (select |c_#memory_int| v_idx_1979)) (< v_idx_1979 .cse0)) (<= v_v_5816_4 v_v_5814_4) (<= v_v_5816_4 0) (<= .cse1 c_ULTIMATE.start_main_p3) (<= (* 2 v_v_5816_4) 0) (<= 0 v_v_5814_4) (or (= v_v_5813_5 (select |c_#memory_int| v_idx_1973)) (<= c_ULTIMATE.start_main_p1 v_idx_1973)) (or (< v_idx_1976 c_ULTIMATE.start_main_p2) (= v_v_5816_4 (select |c_#memory_int| v_idx_1976)) (<= .cse1 v_idx_1976)) (or (< v_idx_1975 .cse2) (= v_v_5815_4 (select |c_#memory_int| v_idx_1975)) (<= c_ULTIMATE.start_main_p2 v_idx_1975)) (<= .cse2 c_ULTIMATE.start_main_p2) (or (= v_v_5814_4 (select |c_#memory_int| v_idx_1974)) (< v_idx_1974 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_1974)))))) is different from false [2019-01-08 14:43:50,629 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1984 Int) (v_idx_1983 Int) (v_idx_1982 Int) (v_idx_1981 Int) (v_idx_1980 Int) (v_idx_1986 Int) (v_idx_1985 Int)) (exists ((v_v_5813_5 Int) (v_v_5814_4 Int) (v_v_5816_4 Int) (v_v_5815_4 Int) (v_v_5817_5 Int) (v_v_5819_5 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_1984 .cse0) (<= c_ULTIMATE.start_main_p3 v_idx_1984) (= v_v_5817_5 (select |c_#memory_int| v_idx_1984))) (or (= v_v_5813_5 (select |c_#memory_int| v_idx_1980)) (<= c_ULTIMATE.start_main_p1 v_idx_1980)) (<= 0 (* 2 v_v_5814_4)) (or (< v_idx_1981 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_1981) (= v_v_5814_4 (select |c_#memory_int| v_idx_1981))) (or (< v_idx_1986 .cse2) (= v_v_5819_5 (select |c_#memory_int| v_idx_1986))) (<= v_v_5816_4 v_v_5814_4) (<= v_v_5816_4 0) (<= .cse0 c_ULTIMATE.start_main_p3) (<= (* 2 v_v_5816_4) 0) (<= 0 v_v_5814_4) (or (= v_v_5816_4 (select |c_#memory_int| v_idx_1983)) (<= .cse0 v_idx_1983) (< v_idx_1983 c_ULTIMATE.start_main_p2)) (or (= (select |c_#memory_int| v_idx_1985) 0) (< v_idx_1985 c_ULTIMATE.start_main_p3) (<= .cse2 v_idx_1985)) (<= .cse1 c_ULTIMATE.start_main_p2) (or (= v_v_5815_4 (select |c_#memory_int| v_idx_1982)) (<= c_ULTIMATE.start_main_p2 v_idx_1982) (< v_idx_1982 .cse1)))))) is different from false [2019-01-08 14:43:53,292 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1993 Int) (v_idx_1992 Int) (v_idx_1991 Int) (v_idx_1990 Int) (v_idx_1989 Int) (v_idx_1988 Int) (v_idx_1987 Int)) (exists ((v_b_432_6 Int) (v_v_5813_5 Int) (v_v_5816_4 Int) (v_v_5815_4 Int) (v_v_5817_5 Int) (v_v_6547_2 Int) (v_v_5819_5 Int) (v_b_397_7 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ v_b_432_6 1))) (and (<= 0 v_v_6547_2) (<= (+ v_b_432_6 2) c_ULTIMATE.start_main_p3) (<= v_v_5816_4 0) (<= .cse0 c_ULTIMATE.start_main_p3) (or (= v_v_5815_4 (select |c_#memory_int| v_idx_1989)) (<= c_ULTIMATE.start_main_p2 v_idx_1989) (< v_idx_1989 v_b_397_7)) (or (= v_v_5817_5 (select |c_#memory_int| v_idx_1991)) (< v_idx_1991 .cse0) (<= c_ULTIMATE.start_main_p3 v_idx_1991)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= v_b_397_7 .cse1) (or (<= v_b_397_7 v_idx_1988) (< v_idx_1988 v_b_432_6) (= v_v_6547_2 (select |c_#memory_int| v_idx_1988))) (<= (+ v_b_397_7 1) c_ULTIMATE.start_main_p3) (<= (* 2 v_v_5816_4) 0) (or (<= v_b_432_6 v_idx_1987) (= v_v_5813_5 (select |c_#memory_int| v_idx_1987))) (<= v_b_397_7 c_ULTIMATE.start_main_p2) (or (<= .cse2 v_idx_1992) (= 0 (select |c_#memory_int| v_idx_1992)) (< v_idx_1992 c_ULTIMATE.start_main_p3)) (<= 0 (* 2 v_v_6547_2)) (or (< v_idx_1990 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_1990) (= v_v_5816_4 (select |c_#memory_int| v_idx_1990))) (or (= v_v_5819_5 (select |c_#memory_int| v_idx_1993)) (< v_idx_1993 .cse2)) (<= v_v_5816_4 v_v_6547_2) (<= .cse1 v_b_397_7))))) is different from false [2019-01-08 14:43:55,638 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1995 Int) (v_idx_1994 Int) (v_idx_2000 Int) (v_idx_1999 Int) (v_idx_1998 Int) (v_idx_1997 Int) (v_idx_1996 Int)) (exists ((v_b_432_6 Int) (v_v_7083_2 Int) (v_v_5813_5 Int) (v_b_456_6 Int) (v_v_5815_4 Int) (v_b_399_7 Int) (v_v_5817_5 Int) (v_v_6547_2 Int) (v_v_5819_5 Int) (v_b_397_7 Int)) (let ((.cse2 (+ v_b_432_6 2)) (.cse0 (+ v_b_456_6 1)) (.cse4 (+ v_b_397_7 1)) (.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse3 (+ v_b_432_6 1))) (and (<= .cse0 c_ULTIMATE.start_main_p3) (or (= v_v_5819_5 (select |c_#memory_int| v_idx_2000)) (< v_idx_2000 .cse1)) (<= v_v_7083_2 v_v_6547_2) (<= v_v_7083_2 0) (<= 0 v_v_6547_2) (<= .cse2 c_ULTIMATE.start_main_p3) (<= .cse2 v_b_399_7) (<= v_b_397_7 v_b_456_6) (<= .cse0 v_b_399_7) (<= v_b_399_7 .cse0) (<= v_b_397_7 .cse3) (<= .cse3 v_b_456_6) (<= .cse4 c_ULTIMATE.start_main_p3) (or (<= v_b_432_6 v_idx_1994) (= v_v_5813_5 (select |c_#memory_int| v_idx_1994))) (or (<= v_b_397_7 v_idx_1995) (< v_idx_1995 v_b_432_6) (= v_v_6547_2 (select |c_#memory_int| v_idx_1995))) (<= .cse4 v_b_399_7) (or (< v_idx_1998 v_b_399_7) (<= c_ULTIMATE.start_main_p3 v_idx_1998) (= v_v_5817_5 (select |c_#memory_int| v_idx_1998))) (<= 0 (* 2 v_v_6547_2)) (or (< v_idx_1999 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_1999) 0) (<= .cse1 v_idx_1999)) (or (<= v_b_456_6 v_idx_1996) (= v_v_5815_4 (select |c_#memory_int| v_idx_1996)) (< v_idx_1996 v_b_397_7)) (<= (* 2 v_v_7083_2) 0) (<= v_b_399_7 c_ULTIMATE.start_main_p3) (or (< v_idx_1997 v_b_456_6) (<= v_b_399_7 v_idx_1997) (= v_v_7083_2 (select |c_#memory_int| v_idx_1997))) (<= .cse3 v_b_397_7))))) is different from false [2019-01-08 14:43:55,695 INFO L420 sIntCurrentIteration]: We unified 5 AI predicates to 5 [2019-01-08 14:43:55,696 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:43:55,696 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:43:55,696 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [3] total 8 [2019-01-08 14:43:55,696 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:43:55,696 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-01-08 14:43:55,696 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-01-08 14:43:55,696 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-08 14:43:55,697 INFO L87 Difference]: Start difference. First operand 36 states and 117 transitions. Second operand 7 states. [2019-01-08 14:43:58,614 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_1993 Int) (v_idx_1992 Int) (v_idx_1991 Int) (v_idx_1990 Int) (v_idx_1989 Int) (v_idx_1988 Int) (v_idx_1987 Int)) (exists ((v_b_432_6 Int) (v_v_5813_5 Int) (v_v_5816_4 Int) (v_v_5815_4 Int) (v_v_5817_5 Int) (v_v_6547_2 Int) (v_v_5819_5 Int) (v_b_397_7 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ v_b_432_6 1))) (and (<= 0 v_v_6547_2) (<= (+ v_b_432_6 2) c_ULTIMATE.start_main_p3) (<= v_v_5816_4 0) (<= .cse0 c_ULTIMATE.start_main_p3) (or (= v_v_5815_4 (select |c_#memory_int| v_idx_1989)) (<= c_ULTIMATE.start_main_p2 v_idx_1989) (< v_idx_1989 v_b_397_7)) (or (= v_v_5817_5 (select |c_#memory_int| v_idx_1991)) (< v_idx_1991 .cse0) (<= c_ULTIMATE.start_main_p3 v_idx_1991)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= v_b_397_7 .cse1) (or (<= v_b_397_7 v_idx_1988) (< v_idx_1988 v_b_432_6) (= v_v_6547_2 (select |c_#memory_int| v_idx_1988))) (<= (+ v_b_397_7 1) c_ULTIMATE.start_main_p3) (<= (* 2 v_v_5816_4) 0) (or (<= v_b_432_6 v_idx_1987) (= v_v_5813_5 (select |c_#memory_int| v_idx_1987))) (<= v_b_397_7 c_ULTIMATE.start_main_p2) (or (<= .cse2 v_idx_1992) (= 0 (select |c_#memory_int| v_idx_1992)) (< v_idx_1992 c_ULTIMATE.start_main_p3)) (<= 0 (* 2 v_v_6547_2)) (or (< v_idx_1990 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_1990) (= v_v_5816_4 (select |c_#memory_int| v_idx_1990))) (or (= v_v_5819_5 (select |c_#memory_int| v_idx_1993)) (< v_idx_1993 .cse2)) (<= v_v_5816_4 v_v_6547_2) (<= .cse1 v_b_397_7))))) (forall ((v_idx_1984 Int) (v_idx_1983 Int) (v_idx_1982 Int) (v_idx_1981 Int) (v_idx_1980 Int) (v_idx_1986 Int) (v_idx_1985 Int)) (exists ((v_v_5813_5 Int) (v_v_5814_4 Int) (v_v_5816_4 Int) (v_v_5815_4 Int) (v_v_5817_5 Int) (v_v_5819_5 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ c_ULTIMATE.start_main_p3 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_1984 .cse3) (<= c_ULTIMATE.start_main_p3 v_idx_1984) (= v_v_5817_5 (select |c_#memory_int| v_idx_1984))) (or (= v_v_5813_5 (select |c_#memory_int| v_idx_1980)) (<= c_ULTIMATE.start_main_p1 v_idx_1980)) (<= 0 (* 2 v_v_5814_4)) (or (< v_idx_1981 c_ULTIMATE.start_main_p1) (<= .cse4 v_idx_1981) (= v_v_5814_4 (select |c_#memory_int| v_idx_1981))) (or (< v_idx_1986 .cse5) (= v_v_5819_5 (select |c_#memory_int| v_idx_1986))) (<= v_v_5816_4 v_v_5814_4) (<= v_v_5816_4 0) (<= .cse3 c_ULTIMATE.start_main_p3) (<= (* 2 v_v_5816_4) 0) (<= 0 v_v_5814_4) (or (= v_v_5816_4 (select |c_#memory_int| v_idx_1983)) (<= .cse3 v_idx_1983) (< v_idx_1983 c_ULTIMATE.start_main_p2)) (or (= (select |c_#memory_int| v_idx_1985) 0) (< v_idx_1985 c_ULTIMATE.start_main_p3) (<= .cse5 v_idx_1985)) (<= .cse4 c_ULTIMATE.start_main_p2) (or (= v_v_5815_4 (select |c_#memory_int| v_idx_1982)) (<= c_ULTIMATE.start_main_p2 v_idx_1982) (< v_idx_1982 .cse4)))))) (forall ((v_idx_1973 Int) (v_idx_1979 Int) (v_idx_1978 Int) (v_idx_1977 Int) (v_idx_1976 Int) (v_idx_1975 Int) (v_idx_1974 Int)) (exists ((v_v_5814_4 Int) (v_v_5813_5 Int) (v_v_5816_4 Int) (v_v_5815_4 Int) (v_v_5817_5 Int) (v_v_5819_5 Int)) (let ((.cse6 (+ c_ULTIMATE.start_main_p3 1)) (.cse7 (+ c_ULTIMATE.start_main_p2 1)) (.cse8 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_1978) 0) (<= .cse6 v_idx_1978) (< v_idx_1978 c_ULTIMATE.start_main_p3)) (<= 0 (* 2 v_v_5814_4)) (or (= v_v_5817_5 (select |c_#memory_int| v_idx_1977)) (<= c_ULTIMATE.start_main_p3 v_idx_1977) (< v_idx_1977 .cse7)) (or (= v_v_5819_5 (select |c_#memory_int| v_idx_1979)) (< v_idx_1979 .cse6)) (<= v_v_5816_4 v_v_5814_4) (<= v_v_5816_4 0) (<= .cse7 c_ULTIMATE.start_main_p3) (<= (* 2 v_v_5816_4) 0) (<= 0 v_v_5814_4) (or (= v_v_5813_5 (select |c_#memory_int| v_idx_1973)) (<= c_ULTIMATE.start_main_p1 v_idx_1973)) (or (< v_idx_1976 c_ULTIMATE.start_main_p2) (= v_v_5816_4 (select |c_#memory_int| v_idx_1976)) (<= .cse7 v_idx_1976)) (or (< v_idx_1975 .cse8) (= v_v_5815_4 (select |c_#memory_int| v_idx_1975)) (<= c_ULTIMATE.start_main_p2 v_idx_1975)) (<= .cse8 c_ULTIMATE.start_main_p2) (or (= v_v_5814_4 (select |c_#memory_int| v_idx_1974)) (< v_idx_1974 c_ULTIMATE.start_main_p1) (<= .cse8 v_idx_1974)))))) (forall ((v_idx_1995 Int) (v_idx_1994 Int) (v_idx_2000 Int) (v_idx_1999 Int) (v_idx_1998 Int) (v_idx_1997 Int) (v_idx_1996 Int)) (exists ((v_b_432_6 Int) (v_v_7083_2 Int) (v_v_5813_5 Int) (v_b_456_6 Int) (v_v_5815_4 Int) (v_b_399_7 Int) (v_v_5817_5 Int) (v_v_6547_2 Int) (v_v_5819_5 Int) (v_b_397_7 Int)) (let ((.cse11 (+ v_b_432_6 2)) (.cse9 (+ v_b_456_6 1)) (.cse13 (+ v_b_397_7 1)) (.cse10 (+ c_ULTIMATE.start_main_p3 1)) (.cse12 (+ v_b_432_6 1))) (and (<= .cse9 c_ULTIMATE.start_main_p3) (or (= v_v_5819_5 (select |c_#memory_int| v_idx_2000)) (< v_idx_2000 .cse10)) (<= v_v_7083_2 v_v_6547_2) (<= v_v_7083_2 0) (<= 0 v_v_6547_2) (<= .cse11 c_ULTIMATE.start_main_p3) (<= .cse11 v_b_399_7) (<= v_b_397_7 v_b_456_6) (<= .cse9 v_b_399_7) (<= v_b_399_7 .cse9) (<= v_b_397_7 .cse12) (<= .cse12 v_b_456_6) (<= .cse13 c_ULTIMATE.start_main_p3) (or (<= v_b_432_6 v_idx_1994) (= v_v_5813_5 (select |c_#memory_int| v_idx_1994))) (or (<= v_b_397_7 v_idx_1995) (< v_idx_1995 v_b_432_6) (= v_v_6547_2 (select |c_#memory_int| v_idx_1995))) (<= .cse13 v_b_399_7) (or (< v_idx_1998 v_b_399_7) (<= c_ULTIMATE.start_main_p3 v_idx_1998) (= v_v_5817_5 (select |c_#memory_int| v_idx_1998))) (<= 0 (* 2 v_v_6547_2)) (or (< v_idx_1999 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_1999) 0) (<= .cse10 v_idx_1999)) (or (<= v_b_456_6 v_idx_1996) (= v_v_5815_4 (select |c_#memory_int| v_idx_1996)) (< v_idx_1996 v_b_397_7)) (<= (* 2 v_v_7083_2) 0) (<= v_b_399_7 c_ULTIMATE.start_main_p3) (or (< v_idx_1997 v_b_456_6) (<= v_b_399_7 v_idx_1997) (= v_v_7083_2 (select |c_#memory_int| v_idx_1997))) (<= .cse12 v_b_397_7))))) (forall ((v_idx_1972 Int) (v_idx_1971 Int) (v_idx_1970 Int) (v_idx_1969 Int) (v_idx_1968 Int) (v_idx_1967 Int) (v_idx_1966 Int)) (exists ((v_v_5814_4 Int) (v_v_5813_5 Int) (v_v_5816_4 Int) (v_v_5815_4 Int) (v_v_5817_5 Int) (v_v_5819_5 Int)) (let ((.cse14 (+ c_ULTIMATE.start_main_p1 1)) (.cse15 (+ c_ULTIMATE.start_main_p2 1)) (.cse16 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= .cse14 v_idx_1967) (< v_idx_1967 c_ULTIMATE.start_main_p1) (= v_v_5814_4 (select |c_#memory_int| v_idx_1967))) (<= 0 (* 2 v_v_5814_4)) (or (= v_v_5817_5 (select |c_#memory_int| v_idx_1970)) (<= c_ULTIMATE.start_main_p3 v_idx_1970) (< v_idx_1970 .cse15)) (or (<= .cse16 v_idx_1971) (= 0 (select |c_#memory_int| v_idx_1971)) (< v_idx_1971 c_ULTIMATE.start_main_p3)) (<= v_v_5816_4 v_v_5814_4) (<= v_v_5816_4 0) (<= .cse15 c_ULTIMATE.start_main_p3) (<= (* 2 v_v_5816_4) 0) (or (= v_v_5815_4 (select |c_#memory_int| v_idx_1968)) (<= c_ULTIMATE.start_main_p2 v_idx_1968) (< v_idx_1968 .cse14)) (or (= v_v_5813_5 (select |c_#memory_int| v_idx_1966)) (<= c_ULTIMATE.start_main_p1 v_idx_1966)) (<= 0 v_v_5814_4) (<= .cse14 c_ULTIMATE.start_main_p2) (or (<= .cse15 v_idx_1969) (< v_idx_1969 c_ULTIMATE.start_main_p2) (= v_v_5816_4 (select |c_#memory_int| v_idx_1969))) (or (< v_idx_1972 .cse16) (= v_v_5819_5 (select |c_#memory_int| v_idx_1972)))))))) is different from false [2019-01-08 14:44:26,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:44:26,112 INFO L93 Difference]: Finished difference Result 41 states and 126 transitions. [2019-01-08 14:44:26,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-01-08 14:44:26,112 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 6 [2019-01-08 14:44:26,113 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:44:26,113 INFO L225 Difference]: With dead ends: 41 [2019-01-08 14:44:26,113 INFO L226 Difference]: Without dead ends: 38 [2019-01-08 14:44:26,114 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 15.2s TimeCoverageRelationStatistics Valid=13, Invalid=7, Unknown=6, NotChecked=30, Total=56 [2019-01-08 14:44:26,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2019-01-08 14:44:26,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 38. [2019-01-08 14:44:26,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2019-01-08 14:44:26,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 123 transitions. [2019-01-08 14:44:26,168 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 123 transitions. Word has length 6 [2019-01-08 14:44:26,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:44:26,168 INFO L480 AbstractCegarLoop]: Abstraction has 38 states and 123 transitions. [2019-01-08 14:44:26,168 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-01-08 14:44:26,168 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 123 transitions. [2019-01-08 14:44:26,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-08 14:44:26,169 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:44:26,169 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2019-01-08 14:44:26,169 INFO L423 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:44:26,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:44:26,169 INFO L82 PathProgramCache]: Analyzing trace with hash 893354762, now seen corresponding path program 1 times [2019-01-08 14:44:26,169 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:44:26,170 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:44:26,170 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:44:26,170 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:44:26,170 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:44:26,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:44:26,347 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-08 14:44:26,347 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:44:26,347 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:44:26,347 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 7 with the following transitions: [2019-01-08 14:44:26,348 INFO L207 CegarAbsIntRunner]: [0], [6], [10], [12], [16], [17] [2019-01-08 14:44:26,349 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:44:26,349 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:44:58,289 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:44:58,289 INFO L272 AbstractInterpreter]: Visited 6 different actions 74 times. Merged at 4 different actions 26 times. Widened at 3 different actions 11 times. Found 33 fixpoints after 4 different actions. Largest state had 0 variables. [2019-01-08 14:44:58,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:44:58,290 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:44:59,049 INFO L227 lantSequenceWeakener]: Weakened 5 states. On average, predicates are now at 51.43% of their original sizes. [2019-01-08 14:44:59,049 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:45:01,498 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2169 Int) (v_idx_2168 Int) (v_idx_2167 Int) (v_idx_2166 Int) (v_idx_2172 Int) (v_idx_2171 Int) (v_idx_2170 Int)) (exists ((v_v_9072_1 Int) (v_v_9070_1 Int) (v_v_9071_1 Int) (v_v_9066_1 Int) (v_v_9069_1 Int) (v_v_9067_1 Int) (v_v_9068_1 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_2168 .cse0) (= (select |c_#memory_int| v_idx_2168) v_v_9068_1) (<= c_ULTIMATE.start_main_p2 v_idx_2168)) (or (= v_v_9066_1 (select |c_#memory_int| v_idx_2166)) (<= c_ULTIMATE.start_main_p1 v_idx_2166)) (<= 0 (+ v_v_9071_1 v_v_9067_1)) (or (= v_v_9069_1 (select |c_#memory_int| v_idx_2169)) (<= .cse1 v_idx_2169) (< v_idx_2169 c_ULTIMATE.start_main_p2)) (or (< v_idx_2172 .cse2) (= v_v_9072_1 (select |c_#memory_int| v_idx_2172))) (or (= v_v_9067_1 (select |c_#memory_int| v_idx_2167)) (<= .cse0 v_idx_2167) (< v_idx_2167 c_ULTIMATE.start_main_p1)) (<= .cse1 c_ULTIMATE.start_main_p3) (or (<= .cse2 v_idx_2171) (< v_idx_2171 c_ULTIMATE.start_main_p3) (= v_v_9071_1 (select |c_#memory_int| v_idx_2171))) (or (<= c_ULTIMATE.start_main_p3 v_idx_2170) (< v_idx_2170 .cse1) (= v_v_9070_1 (select |c_#memory_int| v_idx_2170))) (<= 0 (* 2 v_v_9071_1)) (<= 0 (* 2 v_v_9067_1)) (<= (* 2 v_v_9069_1) 0) (<= v_v_9069_1 v_v_9067_1) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_v_9069_1 v_v_9071_1))))) is different from false [2019-01-08 14:45:04,077 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2179 Int) (v_idx_2178 Int) (v_idx_2177 Int) (v_idx_2176 Int) (v_idx_2175 Int) (v_idx_2174 Int) (v_idx_2173 Int)) (exists ((v_v_9072_1 Int) (v_v_9070_1 Int) (v_v_9071_1 Int) (v_v_9066_1 Int) (v_v_9069_1 Int) (v_v_9067_1 Int) (v_v_9068_1 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p1 v_idx_2173) (= v_v_9066_1 (select |c_#memory_int| v_idx_2173))) (or (<= c_ULTIMATE.start_main_p3 v_idx_2177) (< v_idx_2177 .cse0) (= v_v_9070_1 (select |c_#memory_int| v_idx_2177))) (or (< v_idx_2175 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_2175) (= v_v_9068_1 (select |c_#memory_int| v_idx_2175))) (or (<= .cse2 v_idx_2178) (< v_idx_2178 c_ULTIMATE.start_main_p3) (= v_v_9071_1 (select |c_#memory_int| v_idx_2178))) (<= 0 (+ v_v_9071_1 v_v_9067_1)) (or (< v_idx_2174 c_ULTIMATE.start_main_p1) (= v_v_9067_1 (select |c_#memory_int| v_idx_2174)) (<= .cse1 v_idx_2174)) (<= .cse0 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_9071_1)) (or (= v_v_9069_1 (select |c_#memory_int| v_idx_2176)) (<= .cse0 v_idx_2176) (< v_idx_2176 c_ULTIMATE.start_main_p2)) (<= 0 (* 2 v_v_9067_1)) (<= (* 2 v_v_9069_1) 0) (<= v_v_9069_1 v_v_9067_1) (<= .cse1 c_ULTIMATE.start_main_p2) (or (= v_v_9072_1 (select |c_#memory_int| v_idx_2179)) (< v_idx_2179 .cse2)) (<= v_v_9069_1 v_v_9071_1))))) is different from false [2019-01-08 14:45:06,700 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2186 Int) (v_idx_2185 Int) (v_idx_2184 Int) (v_idx_2183 Int) (v_idx_2182 Int) (v_idx_2181 Int) (v_idx_2180 Int)) (exists ((v_v_9072_1 Int) (v_v_9070_1 Int) (v_v_9071_1 Int) (v_v_9066_1 Int) (v_v_9069_1 Int) (v_v_9067_1 Int) (v_v_9068_1 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= v_v_9072_1 (select |c_#memory_int| v_idx_2186)) (< v_idx_2186 .cse0)) (or (<= .cse0 v_idx_2185) (= v_v_9071_1 (select |c_#memory_int| v_idx_2185)) (< v_idx_2185 c_ULTIMATE.start_main_p3)) (<= 0 (+ v_v_9071_1 v_v_9067_1)) (or (<= c_ULTIMATE.start_main_p2 v_idx_2182) (= v_v_9068_1 (select |c_#memory_int| v_idx_2182)) (< v_idx_2182 .cse1)) (<= .cse2 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_9071_1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_2180) (= v_v_9066_1 (select |c_#memory_int| v_idx_2180))) (<= 0 (* 2 v_v_9067_1)) (or (<= .cse1 v_idx_2181) (= v_v_9067_1 (select |c_#memory_int| v_idx_2181)) (< v_idx_2181 c_ULTIMATE.start_main_p1)) (<= (* 2 v_v_9069_1) 0) (or (= v_v_9069_1 (select |c_#memory_int| v_idx_2183)) (<= .cse2 v_idx_2183) (< v_idx_2183 c_ULTIMATE.start_main_p2)) (<= v_v_9069_1 v_v_9067_1) (<= .cse1 c_ULTIMATE.start_main_p2) (or (<= c_ULTIMATE.start_main_p3 v_idx_2184) (= v_v_9070_1 (select |c_#memory_int| v_idx_2184)) (< v_idx_2184 .cse2)) (<= v_v_9069_1 v_v_9071_1))))) is different from false [2019-01-08 14:45:09,059 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2189 Int) (v_idx_2188 Int) (v_idx_2187 Int) (v_idx_2193 Int) (v_idx_2192 Int) (v_idx_2191 Int) (v_idx_2190 Int)) (exists ((v_b_652_3 Int) (v_v_9072_1 Int) (v_v_9070_1 Int) (v_b_653_3 Int) (v_v_9071_1 Int) (v_v_9066_1 Int) (v_v_9069_1 Int) (v_v_9067_1 Int) (v_v_9068_1 Int)) (let ((.cse0 (+ v_b_652_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) v_b_652_3) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_653_3) (<= v_b_653_3 .cse0) (<= 0 (+ v_v_9071_1 v_v_9067_1)) (or (<= .cse1 v_idx_2190) (< v_idx_2190 c_ULTIMATE.start_main_p2) (= v_v_9069_1 (select |c_#memory_int| v_idx_2190))) (<= .cse1 v_b_652_3) (or (< v_idx_2193 v_b_653_3) (= v_v_9072_1 (select |c_#memory_int| v_idx_2193))) (<= 0 (* 2 v_v_9071_1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_2187) (= v_v_9066_1 (select |c_#memory_int| v_idx_2187))) (<= 0 (* 2 v_v_9067_1)) (<= (* 2 v_v_9069_1) 0) (or (= v_v_9068_1 (select |c_#memory_int| v_idx_2189)) (< v_idx_2189 .cse2) (<= c_ULTIMATE.start_main_p2 v_idx_2189)) (<= v_v_9069_1 v_v_9067_1) (<= .cse2 c_ULTIMATE.start_main_p2) (<= .cse0 v_b_653_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_653_3) (or (< v_idx_2192 v_b_652_3) (<= v_b_653_3 v_idx_2192) (= v_v_9071_1 (select |c_#memory_int| v_idx_2192))) (or (< v_idx_2191 .cse1) (= v_v_9070_1 (select |c_#memory_int| v_idx_2191)) (<= v_b_652_3 v_idx_2191)) (or (<= .cse2 v_idx_2188) (= v_v_9067_1 (select |c_#memory_int| v_idx_2188)) (< v_idx_2188 c_ULTIMATE.start_main_p1)) (<= v_v_9069_1 v_v_9071_1))))) is different from false [2019-01-08 14:45:11,436 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2200 Int) (v_idx_2199 Int) (v_idx_2198 Int) (v_idx_2197 Int) (v_idx_2196 Int) (v_idx_2195 Int) (v_idx_2194 Int)) (exists ((v_b_652_3 Int) (v_v_9072_1 Int) (v_v_9070_1 Int) (v_b_653_3 Int) (v_v_9071_1 Int) (v_v_9066_1 Int) (v_b_649_3 Int) (v_v_9069_1 Int) (v_b_700_2 Int) (v_v_9894_1 Int) (v_v_9068_1 Int)) (let ((.cse1 (+ v_b_700_2 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_652_3 1))) (and (<= (+ c_ULTIMATE.start_main_p2 2) v_b_653_3) (or (< v_idx_2196 v_b_649_3) (<= c_ULTIMATE.start_main_p2 v_idx_2196) (= v_v_9068_1 (select |c_#memory_int| v_idx_2196))) (<= (+ v_b_649_3 1) v_b_652_3) (or (= v_v_9069_1 (select |c_#memory_int| v_idx_2197)) (< v_idx_2197 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_2197)) (<= v_v_9069_1 v_v_9894_1) (<= 0 (* 2 v_v_9071_1)) (<= 0 (* 2 v_v_9894_1)) (<= (* 2 v_v_9069_1) 0) (<= v_b_649_3 .cse1) (or (= v_v_9070_1 (select |c_#memory_int| v_idx_2198)) (< v_idx_2198 .cse0) (<= v_b_652_3 v_idx_2198)) (<= (+ v_b_700_2 3) v_b_653_3) (or (<= v_b_653_3 v_idx_2199) (= v_v_9071_1 (select |c_#memory_int| v_idx_2199)) (< v_idx_2199 v_b_652_3)) (<= .cse1 v_b_649_3) (<= v_b_653_3 .cse2) (<= 0 (+ v_v_9071_1 v_v_9894_1)) (<= .cse1 c_ULTIMATE.start_main_p2) (or (= v_v_9072_1 (select |c_#memory_int| v_idx_2200)) (< v_idx_2200 v_b_653_3)) (<= .cse0 v_b_652_3) (<= (+ v_b_649_3 2) v_b_653_3) (or (<= v_b_700_2 v_idx_2194) (= v_v_9066_1 (select |c_#memory_int| v_idx_2194))) (<= v_b_649_3 c_ULTIMATE.start_main_p2) (<= (+ v_b_700_2 2) v_b_652_3) (<= .cse2 v_b_653_3) (or (< v_idx_2195 v_b_700_2) (= v_v_9894_1 (select |c_#memory_int| v_idx_2195)) (<= v_b_649_3 v_idx_2195)) (<= v_v_9069_1 v_v_9071_1))))) is different from false [2019-01-08 14:45:11,527 INFO L420 sIntCurrentIteration]: We unified 5 AI predicates to 5 [2019-01-08 14:45:11,527 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:45:11,528 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:45:11,528 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [4] total 9 [2019-01-08 14:45:11,528 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:45:11,528 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-01-08 14:45:11,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-01-08 14:45:11,528 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-08 14:45:11,528 INFO L87 Difference]: Start difference. First operand 38 states and 123 transitions. Second operand 7 states. [2019-01-08 14:45:14,751 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_2186 Int) (v_idx_2185 Int) (v_idx_2184 Int) (v_idx_2183 Int) (v_idx_2182 Int) (v_idx_2181 Int) (v_idx_2180 Int)) (exists ((v_v_9072_1 Int) (v_v_9070_1 Int) (v_v_9071_1 Int) (v_v_9066_1 Int) (v_v_9069_1 Int) (v_v_9067_1 Int) (v_v_9068_1 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= v_v_9072_1 (select |c_#memory_int| v_idx_2186)) (< v_idx_2186 .cse0)) (or (<= .cse0 v_idx_2185) (= v_v_9071_1 (select |c_#memory_int| v_idx_2185)) (< v_idx_2185 c_ULTIMATE.start_main_p3)) (<= 0 (+ v_v_9071_1 v_v_9067_1)) (or (<= c_ULTIMATE.start_main_p2 v_idx_2182) (= v_v_9068_1 (select |c_#memory_int| v_idx_2182)) (< v_idx_2182 .cse1)) (<= .cse2 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_9071_1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_2180) (= v_v_9066_1 (select |c_#memory_int| v_idx_2180))) (<= 0 (* 2 v_v_9067_1)) (or (<= .cse1 v_idx_2181) (= v_v_9067_1 (select |c_#memory_int| v_idx_2181)) (< v_idx_2181 c_ULTIMATE.start_main_p1)) (<= (* 2 v_v_9069_1) 0) (or (= v_v_9069_1 (select |c_#memory_int| v_idx_2183)) (<= .cse2 v_idx_2183) (< v_idx_2183 c_ULTIMATE.start_main_p2)) (<= v_v_9069_1 v_v_9067_1) (<= .cse1 c_ULTIMATE.start_main_p2) (or (<= c_ULTIMATE.start_main_p3 v_idx_2184) (= v_v_9070_1 (select |c_#memory_int| v_idx_2184)) (< v_idx_2184 .cse2)) (<= v_v_9069_1 v_v_9071_1))))) (forall ((v_idx_2189 Int) (v_idx_2188 Int) (v_idx_2187 Int) (v_idx_2193 Int) (v_idx_2192 Int) (v_idx_2191 Int) (v_idx_2190 Int)) (exists ((v_b_652_3 Int) (v_v_9072_1 Int) (v_v_9070_1 Int) (v_b_653_3 Int) (v_v_9071_1 Int) (v_v_9066_1 Int) (v_v_9069_1 Int) (v_v_9067_1 Int) (v_v_9068_1 Int)) (let ((.cse3 (+ v_b_652_3 1)) (.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) v_b_652_3) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_653_3) (<= v_b_653_3 .cse3) (<= 0 (+ v_v_9071_1 v_v_9067_1)) (or (<= .cse4 v_idx_2190) (< v_idx_2190 c_ULTIMATE.start_main_p2) (= v_v_9069_1 (select |c_#memory_int| v_idx_2190))) (<= .cse4 v_b_652_3) (or (< v_idx_2193 v_b_653_3) (= v_v_9072_1 (select |c_#memory_int| v_idx_2193))) (<= 0 (* 2 v_v_9071_1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_2187) (= v_v_9066_1 (select |c_#memory_int| v_idx_2187))) (<= 0 (* 2 v_v_9067_1)) (<= (* 2 v_v_9069_1) 0) (or (= v_v_9068_1 (select |c_#memory_int| v_idx_2189)) (< v_idx_2189 .cse5) (<= c_ULTIMATE.start_main_p2 v_idx_2189)) (<= v_v_9069_1 v_v_9067_1) (<= .cse5 c_ULTIMATE.start_main_p2) (<= .cse3 v_b_653_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_653_3) (or (< v_idx_2192 v_b_652_3) (<= v_b_653_3 v_idx_2192) (= v_v_9071_1 (select |c_#memory_int| v_idx_2192))) (or (< v_idx_2191 .cse4) (= v_v_9070_1 (select |c_#memory_int| v_idx_2191)) (<= v_b_652_3 v_idx_2191)) (or (<= .cse5 v_idx_2188) (= v_v_9067_1 (select |c_#memory_int| v_idx_2188)) (< v_idx_2188 c_ULTIMATE.start_main_p1)) (<= v_v_9069_1 v_v_9071_1))))) (forall ((v_idx_2169 Int) (v_idx_2168 Int) (v_idx_2167 Int) (v_idx_2166 Int) (v_idx_2172 Int) (v_idx_2171 Int) (v_idx_2170 Int)) (exists ((v_v_9072_1 Int) (v_v_9070_1 Int) (v_v_9071_1 Int) (v_v_9066_1 Int) (v_v_9069_1 Int) (v_v_9067_1 Int) (v_v_9068_1 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p3 1)) (.cse7 (+ c_ULTIMATE.start_main_p2 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_2168 .cse6) (= (select |c_#memory_int| v_idx_2168) v_v_9068_1) (<= c_ULTIMATE.start_main_p2 v_idx_2168)) (or (= v_v_9066_1 (select |c_#memory_int| v_idx_2166)) (<= c_ULTIMATE.start_main_p1 v_idx_2166)) (<= 0 (+ v_v_9071_1 v_v_9067_1)) (or (= v_v_9069_1 (select |c_#memory_int| v_idx_2169)) (<= .cse7 v_idx_2169) (< v_idx_2169 c_ULTIMATE.start_main_p2)) (or (< v_idx_2172 .cse8) (= v_v_9072_1 (select |c_#memory_int| v_idx_2172))) (or (= v_v_9067_1 (select |c_#memory_int| v_idx_2167)) (<= .cse6 v_idx_2167) (< v_idx_2167 c_ULTIMATE.start_main_p1)) (<= .cse7 c_ULTIMATE.start_main_p3) (or (<= .cse8 v_idx_2171) (< v_idx_2171 c_ULTIMATE.start_main_p3) (= v_v_9071_1 (select |c_#memory_int| v_idx_2171))) (or (<= c_ULTIMATE.start_main_p3 v_idx_2170) (< v_idx_2170 .cse7) (= v_v_9070_1 (select |c_#memory_int| v_idx_2170))) (<= 0 (* 2 v_v_9071_1)) (<= 0 (* 2 v_v_9067_1)) (<= (* 2 v_v_9069_1) 0) (<= v_v_9069_1 v_v_9067_1) (<= .cse6 c_ULTIMATE.start_main_p2) (<= v_v_9069_1 v_v_9071_1))))) (forall ((v_idx_2200 Int) (v_idx_2199 Int) (v_idx_2198 Int) (v_idx_2197 Int) (v_idx_2196 Int) (v_idx_2195 Int) (v_idx_2194 Int)) (exists ((v_b_652_3 Int) (v_v_9072_1 Int) (v_v_9070_1 Int) (v_b_653_3 Int) (v_v_9071_1 Int) (v_v_9066_1 Int) (v_b_649_3 Int) (v_v_9069_1 Int) (v_b_700_2 Int) (v_v_9894_1 Int) (v_v_9068_1 Int)) (let ((.cse10 (+ v_b_700_2 1)) (.cse9 (+ c_ULTIMATE.start_main_p2 1)) (.cse11 (+ v_b_652_3 1))) (and (<= (+ c_ULTIMATE.start_main_p2 2) v_b_653_3) (or (< v_idx_2196 v_b_649_3) (<= c_ULTIMATE.start_main_p2 v_idx_2196) (= v_v_9068_1 (select |c_#memory_int| v_idx_2196))) (<= (+ v_b_649_3 1) v_b_652_3) (or (= v_v_9069_1 (select |c_#memory_int| v_idx_2197)) (< v_idx_2197 c_ULTIMATE.start_main_p2) (<= .cse9 v_idx_2197)) (<= v_v_9069_1 v_v_9894_1) (<= 0 (* 2 v_v_9071_1)) (<= 0 (* 2 v_v_9894_1)) (<= (* 2 v_v_9069_1) 0) (<= v_b_649_3 .cse10) (or (= v_v_9070_1 (select |c_#memory_int| v_idx_2198)) (< v_idx_2198 .cse9) (<= v_b_652_3 v_idx_2198)) (<= (+ v_b_700_2 3) v_b_653_3) (or (<= v_b_653_3 v_idx_2199) (= v_v_9071_1 (select |c_#memory_int| v_idx_2199)) (< v_idx_2199 v_b_652_3)) (<= .cse10 v_b_649_3) (<= v_b_653_3 .cse11) (<= 0 (+ v_v_9071_1 v_v_9894_1)) (<= .cse10 c_ULTIMATE.start_main_p2) (or (= v_v_9072_1 (select |c_#memory_int| v_idx_2200)) (< v_idx_2200 v_b_653_3)) (<= .cse9 v_b_652_3) (<= (+ v_b_649_3 2) v_b_653_3) (or (<= v_b_700_2 v_idx_2194) (= v_v_9066_1 (select |c_#memory_int| v_idx_2194))) (<= v_b_649_3 c_ULTIMATE.start_main_p2) (<= (+ v_b_700_2 2) v_b_652_3) (<= .cse11 v_b_653_3) (or (< v_idx_2195 v_b_700_2) (= v_v_9894_1 (select |c_#memory_int| v_idx_2195)) (<= v_b_649_3 v_idx_2195)) (<= v_v_9069_1 v_v_9071_1))))) (forall ((v_idx_2179 Int) (v_idx_2178 Int) (v_idx_2177 Int) (v_idx_2176 Int) (v_idx_2175 Int) (v_idx_2174 Int) (v_idx_2173 Int)) (exists ((v_v_9072_1 Int) (v_v_9070_1 Int) (v_v_9071_1 Int) (v_v_9066_1 Int) (v_v_9069_1 Int) (v_v_9067_1 Int) (v_v_9068_1 Int)) (let ((.cse12 (+ c_ULTIMATE.start_main_p2 1)) (.cse13 (+ c_ULTIMATE.start_main_p1 1)) (.cse14 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p1 v_idx_2173) (= v_v_9066_1 (select |c_#memory_int| v_idx_2173))) (or (<= c_ULTIMATE.start_main_p3 v_idx_2177) (< v_idx_2177 .cse12) (= v_v_9070_1 (select |c_#memory_int| v_idx_2177))) (or (< v_idx_2175 .cse13) (<= c_ULTIMATE.start_main_p2 v_idx_2175) (= v_v_9068_1 (select |c_#memory_int| v_idx_2175))) (or (<= .cse14 v_idx_2178) (< v_idx_2178 c_ULTIMATE.start_main_p3) (= v_v_9071_1 (select |c_#memory_int| v_idx_2178))) (<= 0 (+ v_v_9071_1 v_v_9067_1)) (or (< v_idx_2174 c_ULTIMATE.start_main_p1) (= v_v_9067_1 (select |c_#memory_int| v_idx_2174)) (<= .cse13 v_idx_2174)) (<= .cse12 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_9071_1)) (or (= v_v_9069_1 (select |c_#memory_int| v_idx_2176)) (<= .cse12 v_idx_2176) (< v_idx_2176 c_ULTIMATE.start_main_p2)) (<= 0 (* 2 v_v_9067_1)) (<= (* 2 v_v_9069_1) 0) (<= v_v_9069_1 v_v_9067_1) (<= .cse13 c_ULTIMATE.start_main_p2) (or (= v_v_9072_1 (select |c_#memory_int| v_idx_2179)) (< v_idx_2179 .cse14)) (<= v_v_9069_1 v_v_9071_1)))))) is different from false [2019-01-08 14:45:54,529 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_2189 Int) (v_idx_2188 Int) (v_idx_2187 Int) (v_idx_2193 Int) (v_idx_2192 Int) (v_idx_2191 Int) (v_idx_2190 Int)) (exists ((v_b_652_3 Int) (v_v_9072_1 Int) (v_v_9070_1 Int) (v_b_653_3 Int) (v_v_9071_1 Int) (v_v_9066_1 Int) (v_v_9069_1 Int) (v_v_9067_1 Int) (v_v_9068_1 Int)) (let ((.cse0 (+ v_b_652_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) v_b_652_3) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_653_3) (<= v_b_653_3 .cse0) (<= 0 (+ v_v_9071_1 v_v_9067_1)) (or (<= .cse1 v_idx_2190) (< v_idx_2190 c_ULTIMATE.start_main_p2) (= v_v_9069_1 (select |c_#memory_int| v_idx_2190))) (<= .cse1 v_b_652_3) (or (< v_idx_2193 v_b_653_3) (= v_v_9072_1 (select |c_#memory_int| v_idx_2193))) (<= 0 (* 2 v_v_9071_1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_2187) (= v_v_9066_1 (select |c_#memory_int| v_idx_2187))) (<= 0 (* 2 v_v_9067_1)) (<= (* 2 v_v_9069_1) 0) (or (= v_v_9068_1 (select |c_#memory_int| v_idx_2189)) (< v_idx_2189 .cse2) (<= c_ULTIMATE.start_main_p2 v_idx_2189)) (<= v_v_9069_1 v_v_9067_1) (<= .cse2 c_ULTIMATE.start_main_p2) (<= .cse0 v_b_653_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_653_3) (or (< v_idx_2192 v_b_652_3) (<= v_b_653_3 v_idx_2192) (= v_v_9071_1 (select |c_#memory_int| v_idx_2192))) (or (< v_idx_2191 .cse1) (= v_v_9070_1 (select |c_#memory_int| v_idx_2191)) (<= v_b_652_3 v_idx_2191)) (or (<= .cse2 v_idx_2188) (= v_v_9067_1 (select |c_#memory_int| v_idx_2188)) (< v_idx_2188 c_ULTIMATE.start_main_p1)) (<= v_v_9069_1 v_v_9071_1))))) (forall ((v_idx_2200 Int) (v_idx_2199 Int) (v_idx_2198 Int) (v_idx_2197 Int) (v_idx_2196 Int) (v_idx_2195 Int) (v_idx_2194 Int)) (exists ((v_b_652_3 Int) (v_v_9072_1 Int) (v_v_9070_1 Int) (v_b_653_3 Int) (v_v_9071_1 Int) (v_v_9066_1 Int) (v_b_649_3 Int) (v_v_9069_1 Int) (v_b_700_2 Int) (v_v_9894_1 Int) (v_v_9068_1 Int)) (let ((.cse4 (+ v_b_700_2 1)) (.cse3 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ v_b_652_3 1))) (and (<= (+ c_ULTIMATE.start_main_p2 2) v_b_653_3) (or (< v_idx_2196 v_b_649_3) (<= c_ULTIMATE.start_main_p2 v_idx_2196) (= v_v_9068_1 (select |c_#memory_int| v_idx_2196))) (<= (+ v_b_649_3 1) v_b_652_3) (or (= v_v_9069_1 (select |c_#memory_int| v_idx_2197)) (< v_idx_2197 c_ULTIMATE.start_main_p2) (<= .cse3 v_idx_2197)) (<= v_v_9069_1 v_v_9894_1) (<= 0 (* 2 v_v_9071_1)) (<= 0 (* 2 v_v_9894_1)) (<= (* 2 v_v_9069_1) 0) (<= v_b_649_3 .cse4) (or (= v_v_9070_1 (select |c_#memory_int| v_idx_2198)) (< v_idx_2198 .cse3) (<= v_b_652_3 v_idx_2198)) (<= (+ v_b_700_2 3) v_b_653_3) (or (<= v_b_653_3 v_idx_2199) (= v_v_9071_1 (select |c_#memory_int| v_idx_2199)) (< v_idx_2199 v_b_652_3)) (<= .cse4 v_b_649_3) (<= v_b_653_3 .cse5) (<= 0 (+ v_v_9071_1 v_v_9894_1)) (<= .cse4 c_ULTIMATE.start_main_p2) (or (= v_v_9072_1 (select |c_#memory_int| v_idx_2200)) (< v_idx_2200 v_b_653_3)) (<= .cse3 v_b_652_3) (<= (+ v_b_649_3 2) v_b_653_3) (or (<= v_b_700_2 v_idx_2194) (= v_v_9066_1 (select |c_#memory_int| v_idx_2194))) (<= v_b_649_3 c_ULTIMATE.start_main_p2) (<= (+ v_b_700_2 2) v_b_652_3) (<= .cse5 v_b_653_3) (or (< v_idx_2195 v_b_700_2) (= v_v_9894_1 (select |c_#memory_int| v_idx_2195)) (<= v_b_649_3 v_idx_2195)) (<= v_v_9069_1 v_v_9071_1)))))) is different from false [2019-01-08 14:46:00,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:46:00,536 INFO L93 Difference]: Finished difference Result 42 states and 130 transitions. [2019-01-08 14:46:00,536 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-01-08 14:46:00,536 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 6 [2019-01-08 14:46:00,537 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:46:00,537 INFO L225 Difference]: With dead ends: 42 [2019-01-08 14:46:00,537 INFO L226 Difference]: Without dead ends: 41 [2019-01-08 14:46:00,537 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 7 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 17.3s TimeCoverageRelationStatistics Valid=15, Invalid=8, Unknown=7, NotChecked=42, Total=72 [2019-01-08 14:46:00,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2019-01-08 14:46:00,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 39. [2019-01-08 14:46:00,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2019-01-08 14:46:00,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 127 transitions. [2019-01-08 14:46:00,592 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 127 transitions. Word has length 6 [2019-01-08 14:46:00,593 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:46:00,593 INFO L480 AbstractCegarLoop]: Abstraction has 39 states and 127 transitions. [2019-01-08 14:46:00,593 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-01-08 14:46:00,593 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 127 transitions. [2019-01-08 14:46:00,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-08 14:46:00,593 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:46:00,594 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2019-01-08 14:46:00,594 INFO L423 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:46:00,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:46:00,594 INFO L82 PathProgramCache]: Analyzing trace with hash 893412422, now seen corresponding path program 2 times [2019-01-08 14:46:00,594 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:46:00,595 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:46:00,595 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:46:00,595 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:46:00,595 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:46:00,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:46:00,712 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-08 14:46:00,712 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:46:00,712 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:46:00,712 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-08 14:46:00,712 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-08 14:46:00,712 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:46:00,712 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-08 14:46:00,723 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-08 14:46:00,723 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-08 14:46:00,730 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-01-08 14:46:00,730 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-08 14:46:00,731 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-08 14:46:00,734 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-08 14:46:00,741 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,741 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-08 14:46:00,747 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,748 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,748 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-08 14:46:00,749 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:00,760 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:46:00,767 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:46:00,777 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:46:00,778 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:19, output treesize:22 [2019-01-08 14:46:00,794 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,795 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,796 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,797 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,798 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 28 [2019-01-08 14:46:00,798 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:00,814 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:46:00,814 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-08 14:46:00,835 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,837 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,838 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,839 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,840 INFO L683 Elim1Store]: detected equality via solver [2019-01-08 14:46:00,841 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 36 [2019-01-08 14:46:00,841 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:00,856 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:46:00,856 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-08 14:46:00,876 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,877 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,879 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,880 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,881 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,882 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:00,883 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 40 [2019-01-08 14:46:00,883 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:00,902 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:46:00,902 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-08 14:46:00,921 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:46:00,921 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-08 14:46:00,953 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:46:00,971 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-08 14:46:00,971 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 11 [2019-01-08 14:46:00,971 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-08 14:46:00,972 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-01-08 14:46:00,972 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-01-08 14:46:00,972 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=95, Unknown=0, NotChecked=0, Total=156 [2019-01-08 14:46:00,972 INFO L87 Difference]: Start difference. First operand 39 states and 127 transitions. Second operand 10 states. [2019-01-08 14:46:01,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:46:01,286 INFO L93 Difference]: Finished difference Result 58 states and 176 transitions. [2019-01-08 14:46:01,286 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-01-08 14:46:01,286 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 6 [2019-01-08 14:46:01,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:46:01,287 INFO L225 Difference]: With dead ends: 58 [2019-01-08 14:46:01,287 INFO L226 Difference]: Without dead ends: 57 [2019-01-08 14:46:01,288 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=89, Invalid=151, Unknown=0, NotChecked=0, Total=240 [2019-01-08 14:46:01,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2019-01-08 14:46:01,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 43. [2019-01-08 14:46:01,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2019-01-08 14:46:01,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 143 transitions. [2019-01-08 14:46:01,347 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 143 transitions. Word has length 6 [2019-01-08 14:46:01,347 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:46:01,347 INFO L480 AbstractCegarLoop]: Abstraction has 43 states and 143 transitions. [2019-01-08 14:46:01,347 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-01-08 14:46:01,347 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 143 transitions. [2019-01-08 14:46:01,348 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-08 14:46:01,348 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:46:01,348 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2019-01-08 14:46:01,348 INFO L423 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:46:01,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:46:01,348 INFO L82 PathProgramCache]: Analyzing trace with hash 896933590, now seen corresponding path program 2 times [2019-01-08 14:46:01,349 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:46:01,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:46:01,349 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-08 14:46:01,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:46:01,349 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:46:01,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:46:01,536 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-08 14:46:01,536 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:46:01,536 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:46:01,537 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-08 14:46:01,537 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-08 14:46:01,537 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:46:01,537 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-08 14:46:01,583 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-08 14:46:01,583 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-08 14:46:01,589 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-08 14:46:01,589 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-08 14:46:01,590 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-08 14:46:01,593 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-08 14:46:01,597 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:01,598 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-08 14:46:01,601 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:01,601 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:01,602 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-08 14:46:01,602 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:01,613 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:46:01,620 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:46:01,634 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:46:01,634 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:19, output treesize:22 [2019-01-08 14:46:01,653 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:01,654 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:01,655 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:01,656 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:01,657 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-08 14:46:01,657 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:01,677 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:46:01,677 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-08 14:46:01,696 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:01,697 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:01,698 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:01,699 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:01,700 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:01,701 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:01,702 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 42 [2019-01-08 14:46:01,702 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:01,723 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:46:01,723 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:24 [2019-01-08 14:46:01,742 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:46:01,743 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-08 14:46:01,804 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:46:01,823 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-08 14:46:01,823 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 9 [2019-01-08 14:46:01,823 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-08 14:46:01,823 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-01-08 14:46:01,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-01-08 14:46:01,824 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=66, Unknown=0, NotChecked=0, Total=110 [2019-01-08 14:46:01,824 INFO L87 Difference]: Start difference. First operand 43 states and 143 transitions. Second operand 8 states. [2019-01-08 14:46:02,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:46:02,037 INFO L93 Difference]: Finished difference Result 51 states and 158 transitions. [2019-01-08 14:46:02,038 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-08 14:46:02,038 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 6 [2019-01-08 14:46:02,038 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:46:02,039 INFO L225 Difference]: With dead ends: 51 [2019-01-08 14:46:02,039 INFO L226 Difference]: Without dead ends: 46 [2019-01-08 14:46:02,040 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=62, Invalid=94, Unknown=0, NotChecked=0, Total=156 [2019-01-08 14:46:02,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2019-01-08 14:46:02,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 45. [2019-01-08 14:46:02,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2019-01-08 14:46:02,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 149 transitions. [2019-01-08 14:46:02,103 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 149 transitions. Word has length 6 [2019-01-08 14:46:02,103 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:46:02,103 INFO L480 AbstractCegarLoop]: Abstraction has 45 states and 149 transitions. [2019-01-08 14:46:02,103 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-01-08 14:46:02,103 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 149 transitions. [2019-01-08 14:46:02,103 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-08 14:46:02,103 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:46:02,103 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2019-01-08 14:46:02,104 INFO L423 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:46:02,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:46:02,104 INFO L82 PathProgramCache]: Analyzing trace with hash 896929682, now seen corresponding path program 3 times [2019-01-08 14:46:02,104 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:46:02,104 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:46:02,105 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-08 14:46:02,105 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:46:02,105 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:46:02,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:46:02,301 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-08 14:46:02,302 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:46:02,302 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:46:02,302 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-08 14:46:02,302 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-08 14:46:02,303 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:46:02,303 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-08 14:46:02,312 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2019-01-08 14:46:02,313 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2019-01-08 14:46:02,316 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-01-08 14:46:02,317 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-08 14:46:02,318 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-08 14:46:02,321 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-08 14:46:02,323 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,323 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-08 14:46:02,327 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,328 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,329 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-08 14:46:02,329 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:02,351 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:46:02,358 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:46:02,367 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:46:02,367 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:19, output treesize:22 [2019-01-08 14:46:02,387 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,388 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,389 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,391 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,391 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-08 14:46:02,392 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:02,410 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:46:02,411 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:32, output treesize:22 [2019-01-08 14:46:02,428 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,429 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,430 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,431 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,432 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,433 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,434 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 42 [2019-01-08 14:46:02,434 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:02,454 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:46:02,454 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:34, output treesize:24 [2019-01-08 14:46:02,476 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,477 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,478 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,479 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,480 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,480 INFO L683 Elim1Store]: detected equality via solver [2019-01-08 14:46:02,481 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:02,482 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 50 [2019-01-08 14:46:02,483 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:02,503 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:46:02,504 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:24 [2019-01-08 14:46:02,522 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:46:02,523 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-08 14:46:02,584 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:46:02,604 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-08 14:46:02,604 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 11 [2019-01-08 14:46:02,604 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-08 14:46:02,604 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-01-08 14:46:02,605 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-01-08 14:46:02,605 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=97, Unknown=0, NotChecked=0, Total=156 [2019-01-08 14:46:02,605 INFO L87 Difference]: Start difference. First operand 45 states and 149 transitions. Second operand 10 states. [2019-01-08 14:46:02,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:46:02,961 INFO L93 Difference]: Finished difference Result 50 states and 159 transitions. [2019-01-08 14:46:02,962 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-01-08 14:46:02,962 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 6 [2019-01-08 14:46:02,962 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:46:02,963 INFO L225 Difference]: With dead ends: 50 [2019-01-08 14:46:02,963 INFO L226 Difference]: Without dead ends: 49 [2019-01-08 14:46:02,964 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=77, Invalid=133, Unknown=0, NotChecked=0, Total=210 [2019-01-08 14:46:02,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2019-01-08 14:46:03,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 25. [2019-01-08 14:46:03,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-01-08 14:46:03,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 75 transitions. [2019-01-08 14:46:03,008 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 75 transitions. Word has length 6 [2019-01-08 14:46:03,008 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:46:03,008 INFO L480 AbstractCegarLoop]: Abstraction has 25 states and 75 transitions. [2019-01-08 14:46:03,008 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-01-08 14:46:03,009 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 75 transitions. [2019-01-08 14:46:03,009 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-08 14:46:03,009 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:46:03,009 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1] [2019-01-08 14:46:03,009 INFO L423 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:46:03,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:46:03,010 INFO L82 PathProgramCache]: Analyzing trace with hash 897048534, now seen corresponding path program 2 times [2019-01-08 14:46:03,010 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:46:03,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:46:03,010 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-08 14:46:03,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:46:03,010 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:46:03,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:46:03,107 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-08 14:46:03,107 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:46:03,107 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:46:03,108 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-08 14:46:03,108 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-08 14:46:03,108 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:46:03,108 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-08 14:46:03,116 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-08 14:46:03,116 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-08 14:46:03,121 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-01-08 14:46:03,121 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-08 14:46:03,122 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-08 14:46:03,125 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-08 14:46:03,127 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,128 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-08 14:46:03,133 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,134 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,134 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-08 14:46:03,135 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:03,144 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:46:03,151 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:46:03,161 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:46:03,161 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:19, output treesize:22 [2019-01-08 14:46:03,178 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,181 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,182 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,204 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,205 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-08 14:46:03,205 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:03,222 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:46:03,222 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:32, output treesize:22 [2019-01-08 14:46:03,241 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,242 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,243 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,243 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,244 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,245 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,246 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 40 [2019-01-08 14:46:03,246 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:03,262 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:46:03,263 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:34, output treesize:22 [2019-01-08 14:46:03,284 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,285 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,286 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,287 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,288 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,289 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,290 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 50 [2019-01-08 14:46:03,291 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:03,311 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:46:03,311 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:24 [2019-01-08 14:46:03,330 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,331 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,332 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,333 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,334 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,335 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,336 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,337 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:46:03,337 INFO L683 Elim1Store]: detected equality via solver [2019-01-08 14:46:03,338 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 56 [2019-01-08 14:46:03,339 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:46:03,358 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:46:03,358 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:24 [2019-01-08 14:46:03,372 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:46:03,372 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-08 14:46:03,410 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:46:03,430 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-08 14:46:03,430 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5, 5] total 13 [2019-01-08 14:46:03,430 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-08 14:46:03,430 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-01-08 14:46:03,431 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-01-08 14:46:03,431 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=128, Unknown=0, NotChecked=0, Total=210 [2019-01-08 14:46:03,431 INFO L87 Difference]: Start difference. First operand 25 states and 75 transitions. Second operand 11 states. [2019-01-08 14:46:03,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:46:03,863 INFO L93 Difference]: Finished difference Result 43 states and 116 transitions. [2019-01-08 14:46:03,864 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-01-08 14:46:03,864 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 6 [2019-01-08 14:46:03,864 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:46:03,865 INFO L225 Difference]: With dead ends: 43 [2019-01-08 14:46:03,865 INFO L226 Difference]: Without dead ends: 42 [2019-01-08 14:46:03,865 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 77 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=104, Invalid=168, Unknown=0, NotChecked=0, Total=272 [2019-01-08 14:46:03,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2019-01-08 14:46:03,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 30. [2019-01-08 14:46:03,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2019-01-08 14:46:03,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 95 transitions. [2019-01-08 14:46:03,909 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 95 transitions. Word has length 6 [2019-01-08 14:46:03,910 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:46:03,910 INFO L480 AbstractCegarLoop]: Abstraction has 30 states and 95 transitions. [2019-01-08 14:46:03,910 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-01-08 14:46:03,910 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 95 transitions. [2019-01-08 14:46:03,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-08 14:46:03,910 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:46:03,910 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2019-01-08 14:46:03,911 INFO L423 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:46:03,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:46:03,911 INFO L82 PathProgramCache]: Analyzing trace with hash 897112336, now seen corresponding path program 1 times [2019-01-08 14:46:03,911 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:46:03,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:46:03,911 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-08 14:46:03,912 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:46:03,912 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:46:03,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:46:04,269 WARN L181 SmtUtils]: Spent 311.00 ms on a formula simplification. DAG size of input: 21 DAG size of output: 13 [2019-01-08 14:46:04,496 WARN L181 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 17 DAG size of output: 9 [2019-01-08 14:46:04,503 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-08 14:46:04,503 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:46:04,503 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:46:04,504 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 7 with the following transitions: [2019-01-08 14:46:04,504 INFO L207 CegarAbsIntRunner]: [0], [10], [12], [16], [18], [19] [2019-01-08 14:46:04,507 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:46:04,507 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:46:21,431 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:46:21,432 INFO L272 AbstractInterpreter]: Visited 6 different actions 46 times. Merged at 4 different actions 24 times. Widened at 2 different actions 6 times. Found 10 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-08 14:46:21,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:46:21,432 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:46:22,011 INFO L227 lantSequenceWeakener]: Weakened 5 states. On average, predicates are now at 51.43% of their original sizes. [2019-01-08 14:46:22,012 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:46:24,455 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2369 Int) (v_idx_2368 Int) (v_idx_2367 Int) (v_idx_2366 Int) (v_idx_2372 Int) (v_idx_2371 Int) (v_idx_2370 Int)) (exists ((v_v_5065_7 Int) (v_v_5066_7 Int) (v_v_5063_7 Int) (v_v_5064_7 Int) (v_v_5062_7 Int) (v_v_5060_7 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_5065_7)) (or (< v_idx_2369 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_2369) v_v_5063_7) (<= .cse0 v_idx_2369)) (<= (* 2 v_v_5063_7) 0) (or (= (select |c_#memory_int| v_idx_2371) v_v_5065_7) (<= .cse1 v_idx_2371) (< v_idx_2371 c_ULTIMATE.start_main_p3)) (or (< v_idx_2367 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_2367) 0) (<= .cse2 v_idx_2367)) (or (< v_idx_2370 .cse0) (= (select |c_#memory_int| v_idx_2370) v_v_5064_7) (<= c_ULTIMATE.start_main_p3 v_idx_2370)) (<= .cse0 c_ULTIMATE.start_main_p3) (<= v_v_5063_7 0) (or (= (select |c_#memory_int| v_idx_2372) v_v_5066_7) (< v_idx_2372 .cse1)) (<= v_v_5063_7 v_v_5065_7) (<= 0 v_v_5065_7) (<= .cse2 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_2368) v_v_5062_7) (< v_idx_2368 .cse2) (<= c_ULTIMATE.start_main_p2 v_idx_2368)) (or (<= c_ULTIMATE.start_main_p1 v_idx_2366) (= (select |c_#memory_int| v_idx_2366) v_v_5060_7)))))) is different from false [2019-01-08 14:46:27,019 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2379 Int) (v_idx_2378 Int) (v_idx_2377 Int) (v_idx_2376 Int) (v_idx_2375 Int) (v_idx_2374 Int) (v_idx_2373 Int)) (exists ((v_v_5065_7 Int) (v_v_5066_7 Int) (v_v_5063_7 Int) (v_v_5064_7 Int) (v_v_5062_7 Int) (v_v_5060_7 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_2379 .cse0) (= (select |c_#memory_int| v_idx_2379) v_v_5066_7)) (<= 0 (* 2 v_v_5065_7)) (<= (* 2 v_v_5063_7) 0) (or (= (select |c_#memory_int| v_idx_2376) v_v_5063_7) (< v_idx_2376 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_2376)) (or (= (select |c_#memory_int| v_idx_2373) v_v_5060_7) (<= c_ULTIMATE.start_main_p1 v_idx_2373)) (<= .cse1 c_ULTIMATE.start_main_p3) (<= v_v_5063_7 0) (or (<= .cse0 v_idx_2378) (< v_idx_2378 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_2378) v_v_5065_7)) (or (= (select |c_#memory_int| v_idx_2377) v_v_5064_7) (<= c_ULTIMATE.start_main_p3 v_idx_2377) (< v_idx_2377 .cse1)) (or (< v_idx_2375 .cse2) (<= c_ULTIMATE.start_main_p2 v_idx_2375) (= (select |c_#memory_int| v_idx_2375) v_v_5062_7)) (<= v_v_5063_7 v_v_5065_7) (<= 0 v_v_5065_7) (<= .cse2 c_ULTIMATE.start_main_p2) (or (< v_idx_2374 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_2374) 0) (<= .cse2 v_idx_2374)))))) is different from false [2019-01-08 14:46:29,626 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2386 Int) (v_idx_2385 Int) (v_idx_2384 Int) (v_idx_2383 Int) (v_idx_2382 Int) (v_idx_2381 Int) (v_idx_2380 Int)) (exists ((v_v_5065_7 Int) (v_v_5066_7 Int) (v_v_5063_7 Int) (v_v_5064_7 Int) (v_v_5062_7 Int) (v_v_5060_7 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_2380) v_v_5060_7) (<= c_ULTIMATE.start_main_p1 v_idx_2380)) (or (<= .cse0 v_idx_2381) (< v_idx_2381 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_2381) 0)) (<= 0 (* 2 v_v_5065_7)) (<= (* 2 v_v_5063_7) 0) (<= .cse1 c_ULTIMATE.start_main_p3) (<= v_v_5063_7 0) (or (< v_idx_2384 .cse1) (= (select |c_#memory_int| v_idx_2384) v_v_5064_7) (<= c_ULTIMATE.start_main_p3 v_idx_2384)) (or (< v_idx_2382 .cse0) (<= c_ULTIMATE.start_main_p2 v_idx_2382) (= (select |c_#memory_int| v_idx_2382) v_v_5062_7)) (<= v_v_5063_7 v_v_5065_7) (or (= (select |c_#memory_int| v_idx_2385) v_v_5065_7) (< v_idx_2385 c_ULTIMATE.start_main_p3) (<= .cse2 v_idx_2385)) (<= 0 v_v_5065_7) (<= .cse0 c_ULTIMATE.start_main_p2) (or (<= .cse1 v_idx_2383) (= (select |c_#memory_int| v_idx_2383) v_v_5063_7) (< v_idx_2383 c_ULTIMATE.start_main_p2)) (or (= (select |c_#memory_int| v_idx_2386) v_v_5066_7) (< v_idx_2386 .cse2)))))) is different from false [2019-01-08 14:46:32,342 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2389 Int) (v_idx_2388 Int) (v_idx_2387 Int) (v_idx_2393 Int) (v_idx_2392 Int) (v_idx_2391 Int) (v_idx_2390 Int)) (exists ((v_v_5065_7 Int) (v_b_390_9 Int) (v_v_5066_7 Int) (v_v_5063_7 Int) (v_v_5064_7 Int) (v_v_5062_7 Int) (v_b_355_9 Int) (v_v_5060_7 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_390_9 1))) (and (<= v_b_355_9 .cse0) (<= .cse0 v_b_355_9) (or (= (select |c_#memory_int| v_idx_2393) v_v_5066_7) (< v_idx_2393 .cse1)) (or (<= v_b_355_9 v_idx_2388) (= (select |c_#memory_int| v_idx_2388) 0) (< v_idx_2388 v_b_390_9)) (<= (+ v_b_390_9 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_5065_7)) (<= (+ v_b_355_9 1) c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p2 v_idx_2389) (= (select |c_#memory_int| v_idx_2389) v_v_5062_7) (< v_idx_2389 v_b_355_9)) (or (= (select |c_#memory_int| v_idx_2391) v_v_5064_7) (<= c_ULTIMATE.start_main_p3 v_idx_2391) (< v_idx_2391 .cse2)) (<= (* 2 v_v_5063_7) 0) (or (= (select |c_#memory_int| v_idx_2392) v_v_5065_7) (<= .cse1 v_idx_2392) (< v_idx_2392 c_ULTIMATE.start_main_p3)) (<= .cse2 c_ULTIMATE.start_main_p3) (<= v_v_5063_7 0) (<= v_b_355_9 c_ULTIMATE.start_main_p2) (or (<= .cse2 v_idx_2390) (< v_idx_2390 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_2390) v_v_5063_7)) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_v_5063_7 v_v_5065_7) (or (= (select |c_#memory_int| v_idx_2387) v_v_5060_7) (<= v_b_390_9 v_idx_2387)) (<= 0 v_v_5065_7))))) is different from false [2019-01-08 14:46:34,686 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2400 Int) (v_idx_2399 Int) (v_idx_2398 Int) (v_idx_2397 Int) (v_idx_2396 Int) (v_idx_2395 Int) (v_idx_2394 Int)) (exists ((v_v_5065_7 Int) (v_b_390_9 Int) (v_v_5066_7 Int) (v_v_5064_7 Int) (v_b_357_9 Int) (v_v_5062_7 Int) (v_b_414_9 Int) (v_b_355_9 Int) (v_v_6330_4 Int) (v_v_5060_7 Int)) (let ((.cse0 (+ v_b_390_9 1)) (.cse1 (+ v_b_414_9 1)) (.cse2 (+ v_b_390_9 2)) (.cse3 (+ v_b_355_9 1)) (.cse4 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse0 v_b_414_9) (<= (* 2 v_v_6330_4) 0) (<= v_b_355_9 .cse0) (<= v_b_357_9 .cse1) (<= .cse1 c_ULTIMATE.start_main_p3) (or (<= v_b_414_9 v_idx_2396) (< v_idx_2396 v_b_355_9) (= (select |c_#memory_int| v_idx_2396) v_v_5062_7)) (or (= (select |c_#memory_int| v_idx_2394) v_v_5060_7) (<= v_b_390_9 v_idx_2394)) (<= .cse0 v_b_355_9) (<= v_v_6330_4 v_v_5065_7) (<= .cse2 c_ULTIMATE.start_main_p3) (or (< v_idx_2397 v_b_414_9) (= v_v_6330_4 (select |c_#memory_int| v_idx_2397)) (<= v_b_357_9 v_idx_2397)) (<= v_b_355_9 v_b_414_9) (<= 0 (* 2 v_v_5065_7)) (<= .cse3 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_2399) v_v_5065_7) (<= .cse4 v_idx_2399) (< v_idx_2399 c_ULTIMATE.start_main_p3)) (<= v_v_6330_4 0) (<= .cse1 v_b_357_9) (<= v_b_357_9 c_ULTIMATE.start_main_p3) (<= .cse2 v_b_357_9) (or (= (select |c_#memory_int| v_idx_2398) v_v_5064_7) (<= c_ULTIMATE.start_main_p3 v_idx_2398) (< v_idx_2398 v_b_357_9)) (<= .cse3 v_b_357_9) (<= 0 v_v_5065_7) (or (= (select |c_#memory_int| v_idx_2400) v_v_5066_7) (< v_idx_2400 .cse4)) (or (= 0 (select |c_#memory_int| v_idx_2395)) (<= v_b_355_9 v_idx_2395) (< v_idx_2395 v_b_390_9)))))) is different from false [2019-01-08 14:46:34,740 INFO L420 sIntCurrentIteration]: We unified 5 AI predicates to 5 [2019-01-08 14:46:34,740 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:46:34,740 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:46:34,740 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [3] total 8 [2019-01-08 14:46:34,741 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:46:34,741 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-01-08 14:46:34,741 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-01-08 14:46:34,741 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-08 14:46:34,741 INFO L87 Difference]: Start difference. First operand 30 states and 95 transitions. Second operand 7 states. [2019-01-08 14:46:37,560 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_2389 Int) (v_idx_2388 Int) (v_idx_2387 Int) (v_idx_2393 Int) (v_idx_2392 Int) (v_idx_2391 Int) (v_idx_2390 Int)) (exists ((v_v_5065_7 Int) (v_b_390_9 Int) (v_v_5066_7 Int) (v_v_5063_7 Int) (v_v_5064_7 Int) (v_v_5062_7 Int) (v_b_355_9 Int) (v_v_5060_7 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_390_9 1))) (and (<= v_b_355_9 .cse0) (<= .cse0 v_b_355_9) (or (= (select |c_#memory_int| v_idx_2393) v_v_5066_7) (< v_idx_2393 .cse1)) (or (<= v_b_355_9 v_idx_2388) (= (select |c_#memory_int| v_idx_2388) 0) (< v_idx_2388 v_b_390_9)) (<= (+ v_b_390_9 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_5065_7)) (<= (+ v_b_355_9 1) c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p2 v_idx_2389) (= (select |c_#memory_int| v_idx_2389) v_v_5062_7) (< v_idx_2389 v_b_355_9)) (or (= (select |c_#memory_int| v_idx_2391) v_v_5064_7) (<= c_ULTIMATE.start_main_p3 v_idx_2391) (< v_idx_2391 .cse2)) (<= (* 2 v_v_5063_7) 0) (or (= (select |c_#memory_int| v_idx_2392) v_v_5065_7) (<= .cse1 v_idx_2392) (< v_idx_2392 c_ULTIMATE.start_main_p3)) (<= .cse2 c_ULTIMATE.start_main_p3) (<= v_v_5063_7 0) (<= v_b_355_9 c_ULTIMATE.start_main_p2) (or (<= .cse2 v_idx_2390) (< v_idx_2390 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_2390) v_v_5063_7)) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_v_5063_7 v_v_5065_7) (or (= (select |c_#memory_int| v_idx_2387) v_v_5060_7) (<= v_b_390_9 v_idx_2387)) (<= 0 v_v_5065_7))))) (forall ((v_idx_2400 Int) (v_idx_2399 Int) (v_idx_2398 Int) (v_idx_2397 Int) (v_idx_2396 Int) (v_idx_2395 Int) (v_idx_2394 Int)) (exists ((v_v_5065_7 Int) (v_b_390_9 Int) (v_v_5066_7 Int) (v_v_5064_7 Int) (v_b_357_9 Int) (v_v_5062_7 Int) (v_b_414_9 Int) (v_b_355_9 Int) (v_v_6330_4 Int) (v_v_5060_7 Int)) (let ((.cse3 (+ v_b_390_9 1)) (.cse4 (+ v_b_414_9 1)) (.cse5 (+ v_b_390_9 2)) (.cse6 (+ v_b_355_9 1)) (.cse7 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse3 v_b_414_9) (<= (* 2 v_v_6330_4) 0) (<= v_b_355_9 .cse3) (<= v_b_357_9 .cse4) (<= .cse4 c_ULTIMATE.start_main_p3) (or (<= v_b_414_9 v_idx_2396) (< v_idx_2396 v_b_355_9) (= (select |c_#memory_int| v_idx_2396) v_v_5062_7)) (or (= (select |c_#memory_int| v_idx_2394) v_v_5060_7) (<= v_b_390_9 v_idx_2394)) (<= .cse3 v_b_355_9) (<= v_v_6330_4 v_v_5065_7) (<= .cse5 c_ULTIMATE.start_main_p3) (or (< v_idx_2397 v_b_414_9) (= v_v_6330_4 (select |c_#memory_int| v_idx_2397)) (<= v_b_357_9 v_idx_2397)) (<= v_b_355_9 v_b_414_9) (<= 0 (* 2 v_v_5065_7)) (<= .cse6 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_2399) v_v_5065_7) (<= .cse7 v_idx_2399) (< v_idx_2399 c_ULTIMATE.start_main_p3)) (<= v_v_6330_4 0) (<= .cse4 v_b_357_9) (<= v_b_357_9 c_ULTIMATE.start_main_p3) (<= .cse5 v_b_357_9) (or (= (select |c_#memory_int| v_idx_2398) v_v_5064_7) (<= c_ULTIMATE.start_main_p3 v_idx_2398) (< v_idx_2398 v_b_357_9)) (<= .cse6 v_b_357_9) (<= 0 v_v_5065_7) (or (= (select |c_#memory_int| v_idx_2400) v_v_5066_7) (< v_idx_2400 .cse7)) (or (= 0 (select |c_#memory_int| v_idx_2395)) (<= v_b_355_9 v_idx_2395) (< v_idx_2395 v_b_390_9)))))) (forall ((v_idx_2386 Int) (v_idx_2385 Int) (v_idx_2384 Int) (v_idx_2383 Int) (v_idx_2382 Int) (v_idx_2381 Int) (v_idx_2380 Int)) (exists ((v_v_5065_7 Int) (v_v_5066_7 Int) (v_v_5063_7 Int) (v_v_5064_7 Int) (v_v_5062_7 Int) (v_v_5060_7 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse9 (+ c_ULTIMATE.start_main_p2 1)) (.cse10 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_2380) v_v_5060_7) (<= c_ULTIMATE.start_main_p1 v_idx_2380)) (or (<= .cse8 v_idx_2381) (< v_idx_2381 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_2381) 0)) (<= 0 (* 2 v_v_5065_7)) (<= (* 2 v_v_5063_7) 0) (<= .cse9 c_ULTIMATE.start_main_p3) (<= v_v_5063_7 0) (or (< v_idx_2384 .cse9) (= (select |c_#memory_int| v_idx_2384) v_v_5064_7) (<= c_ULTIMATE.start_main_p3 v_idx_2384)) (or (< v_idx_2382 .cse8) (<= c_ULTIMATE.start_main_p2 v_idx_2382) (= (select |c_#memory_int| v_idx_2382) v_v_5062_7)) (<= v_v_5063_7 v_v_5065_7) (or (= (select |c_#memory_int| v_idx_2385) v_v_5065_7) (< v_idx_2385 c_ULTIMATE.start_main_p3) (<= .cse10 v_idx_2385)) (<= 0 v_v_5065_7) (<= .cse8 c_ULTIMATE.start_main_p2) (or (<= .cse9 v_idx_2383) (= (select |c_#memory_int| v_idx_2383) v_v_5063_7) (< v_idx_2383 c_ULTIMATE.start_main_p2)) (or (= (select |c_#memory_int| v_idx_2386) v_v_5066_7) (< v_idx_2386 .cse10)))))) (forall ((v_idx_2369 Int) (v_idx_2368 Int) (v_idx_2367 Int) (v_idx_2366 Int) (v_idx_2372 Int) (v_idx_2371 Int) (v_idx_2370 Int)) (exists ((v_v_5065_7 Int) (v_v_5066_7 Int) (v_v_5063_7 Int) (v_v_5064_7 Int) (v_v_5062_7 Int) (v_v_5060_7 Int)) (let ((.cse11 (+ c_ULTIMATE.start_main_p2 1)) (.cse12 (+ c_ULTIMATE.start_main_p3 1)) (.cse13 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_5065_7)) (or (< v_idx_2369 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_2369) v_v_5063_7) (<= .cse11 v_idx_2369)) (<= (* 2 v_v_5063_7) 0) (or (= (select |c_#memory_int| v_idx_2371) v_v_5065_7) (<= .cse12 v_idx_2371) (< v_idx_2371 c_ULTIMATE.start_main_p3)) (or (< v_idx_2367 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_2367) 0) (<= .cse13 v_idx_2367)) (or (< v_idx_2370 .cse11) (= (select |c_#memory_int| v_idx_2370) v_v_5064_7) (<= c_ULTIMATE.start_main_p3 v_idx_2370)) (<= .cse11 c_ULTIMATE.start_main_p3) (<= v_v_5063_7 0) (or (= (select |c_#memory_int| v_idx_2372) v_v_5066_7) (< v_idx_2372 .cse12)) (<= v_v_5063_7 v_v_5065_7) (<= 0 v_v_5065_7) (<= .cse13 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_2368) v_v_5062_7) (< v_idx_2368 .cse13) (<= c_ULTIMATE.start_main_p2 v_idx_2368)) (or (<= c_ULTIMATE.start_main_p1 v_idx_2366) (= (select |c_#memory_int| v_idx_2366) v_v_5060_7)))))) (forall ((v_idx_2379 Int) (v_idx_2378 Int) (v_idx_2377 Int) (v_idx_2376 Int) (v_idx_2375 Int) (v_idx_2374 Int) (v_idx_2373 Int)) (exists ((v_v_5065_7 Int) (v_v_5066_7 Int) (v_v_5063_7 Int) (v_v_5064_7 Int) (v_v_5062_7 Int) (v_v_5060_7 Int)) (let ((.cse14 (+ c_ULTIMATE.start_main_p3 1)) (.cse15 (+ c_ULTIMATE.start_main_p2 1)) (.cse16 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_2379 .cse14) (= (select |c_#memory_int| v_idx_2379) v_v_5066_7)) (<= 0 (* 2 v_v_5065_7)) (<= (* 2 v_v_5063_7) 0) (or (= (select |c_#memory_int| v_idx_2376) v_v_5063_7) (< v_idx_2376 c_ULTIMATE.start_main_p2) (<= .cse15 v_idx_2376)) (or (= (select |c_#memory_int| v_idx_2373) v_v_5060_7) (<= c_ULTIMATE.start_main_p1 v_idx_2373)) (<= .cse15 c_ULTIMATE.start_main_p3) (<= v_v_5063_7 0) (or (<= .cse14 v_idx_2378) (< v_idx_2378 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_2378) v_v_5065_7)) (or (= (select |c_#memory_int| v_idx_2377) v_v_5064_7) (<= c_ULTIMATE.start_main_p3 v_idx_2377) (< v_idx_2377 .cse15)) (or (< v_idx_2375 .cse16) (<= c_ULTIMATE.start_main_p2 v_idx_2375) (= (select |c_#memory_int| v_idx_2375) v_v_5062_7)) (<= v_v_5063_7 v_v_5065_7) (<= 0 v_v_5065_7) (<= .cse16 c_ULTIMATE.start_main_p2) (or (< v_idx_2374 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_2374) 0) (<= .cse16 v_idx_2374))))))) is different from false [2019-01-08 14:47:10,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:47:10,915 INFO L93 Difference]: Finished difference Result 34 states and 101 transitions. [2019-01-08 14:47:10,915 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-01-08 14:47:10,915 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 6 [2019-01-08 14:47:10,915 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:47:10,915 INFO L225 Difference]: With dead ends: 34 [2019-01-08 14:47:10,915 INFO L226 Difference]: Without dead ends: 31 [2019-01-08 14:47:10,916 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 15.1s TimeCoverageRelationStatistics Valid=13, Invalid=7, Unknown=6, NotChecked=30, Total=56 [2019-01-08 14:47:10,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2019-01-08 14:47:10,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 31. [2019-01-08 14:47:10,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2019-01-08 14:47:10,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 98 transitions. [2019-01-08 14:47:10,962 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 98 transitions. Word has length 6 [2019-01-08 14:47:10,962 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:47:10,962 INFO L480 AbstractCegarLoop]: Abstraction has 31 states and 98 transitions. [2019-01-08 14:47:10,962 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-01-08 14:47:10,962 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 98 transitions. [2019-01-08 14:47:10,963 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-08 14:47:10,963 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:47:10,963 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1] [2019-01-08 14:47:10,963 INFO L423 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:47:10,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:47:10,963 INFO L82 PathProgramCache]: Analyzing trace with hash 897102474, now seen corresponding path program 3 times [2019-01-08 14:47:10,963 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:47:10,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:47:10,964 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:47:10,964 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:47:10,964 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:47:10,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:47:11,068 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-08 14:47:11,068 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:47:11,068 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:47:11,068 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-08 14:47:11,068 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-08 14:47:11,068 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:47:11,068 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-08 14:47:11,078 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2019-01-08 14:47:11,078 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2019-01-08 14:47:11,082 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-01-08 14:47:11,083 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-08 14:47:11,083 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-08 14:47:11,085 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-08 14:47:11,087 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,088 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-08 14:47:11,093 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,094 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,094 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-08 14:47:11,095 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-08 14:47:11,105 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:47:11,112 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:47:11,122 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:47:11,123 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:19, output treesize:22 [2019-01-08 14:47:11,139 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,140 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,141 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,141 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,142 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-08 14:47:11,142 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:47:11,159 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:47:11,160 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:32, output treesize:22 [2019-01-08 14:47:11,179 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,180 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,180 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,181 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,182 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,183 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,184 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 50 [2019-01-08 14:47:11,185 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:47:11,204 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:47:11,205 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:34, output treesize:24 [2019-01-08 14:47:11,223 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,225 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,226 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,227 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,228 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,229 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,230 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,231 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,232 INFO L683 Elim1Store]: detected equality via solver [2019-01-08 14:47:11,233 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 56 [2019-01-08 14:47:11,233 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:47:11,253 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:47:11,253 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:34, output treesize:24 [2019-01-08 14:47:11,284 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,285 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,286 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,286 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,287 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,288 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:11,289 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 40 [2019-01-08 14:47:11,290 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:47:11,306 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:47:11,307 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:22 [2019-01-08 14:47:11,324 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:47:11,324 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-08 14:47:11,374 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:47:11,393 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-08 14:47:11,393 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5, 5] total 14 [2019-01-08 14:47:11,393 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-08 14:47:11,393 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-01-08 14:47:11,393 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-01-08 14:47:11,394 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=148, Unknown=0, NotChecked=0, Total=240 [2019-01-08 14:47:11,394 INFO L87 Difference]: Start difference. First operand 31 states and 98 transitions. Second operand 11 states. [2019-01-08 14:47:11,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:47:11,743 INFO L93 Difference]: Finished difference Result 42 states and 113 transitions. [2019-01-08 14:47:11,743 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-01-08 14:47:11,743 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 6 [2019-01-08 14:47:11,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:47:11,744 INFO L225 Difference]: With dead ends: 42 [2019-01-08 14:47:11,744 INFO L226 Difference]: Without dead ends: 41 [2019-01-08 14:47:11,745 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 87 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=112, Invalid=194, Unknown=0, NotChecked=0, Total=306 [2019-01-08 14:47:11,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2019-01-08 14:47:11,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 11. [2019-01-08 14:47:11,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11 states. [2019-01-08 14:47:11,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 25 transitions. [2019-01-08 14:47:11,784 INFO L78 Accepts]: Start accepts. Automaton has 11 states and 25 transitions. Word has length 6 [2019-01-08 14:47:11,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:47:11,784 INFO L480 AbstractCegarLoop]: Abstraction has 11 states and 25 transitions. [2019-01-08 14:47:11,784 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-01-08 14:47:11,784 INFO L276 IsEmpty]: Start isEmpty. Operand 11 states and 25 transitions. [2019-01-08 14:47:11,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-08 14:47:11,784 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:47:11,784 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2019-01-08 14:47:11,785 INFO L423 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:47:11,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:47:11,785 INFO L82 PathProgramCache]: Analyzing trace with hash 898899796, now seen corresponding path program 2 times [2019-01-08 14:47:11,785 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:47:11,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:47:11,786 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-08 14:47:11,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:47:11,786 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:47:11,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:47:11,975 WARN L181 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 17 DAG size of output: 9 [2019-01-08 14:47:12,022 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:47:12,022 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:47:12,022 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:47:12,022 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-08 14:47:12,023 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-08 14:47:12,023 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:47:12,023 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-08 14:47:12,040 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-08 14:47:12,040 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-08 14:47:12,049 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-08 14:47:12,049 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-08 14:47:12,050 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-08 14:47:12,052 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-08 14:47:12,054 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 17 [2019-01-08 14:47:12,058 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:12,059 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 20 [2019-01-08 14:47:12,059 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-08 14:47:12,066 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:47:12,072 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:47:12,081 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:47:12,081 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:16, output treesize:19 [2019-01-08 14:47:12,100 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:12,101 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:12,101 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 21 [2019-01-08 14:47:12,102 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:47:12,110 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:47:12,110 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:24, output treesize:14 [2019-01-08 14:47:12,124 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:12,125 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:12,125 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:12,126 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:47:12,127 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 27 [2019-01-08 14:47:12,128 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:47:12,139 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-08 14:47:12,139 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:24, output treesize:14 [2019-01-08 14:47:12,153 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:47:12,153 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-08 14:47:12,171 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:47:12,190 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-08 14:47:12,190 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 3, 3] total 9 [2019-01-08 14:47:12,190 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-08 14:47:12,190 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-01-08 14:47:12,191 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-01-08 14:47:12,191 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=64, Unknown=0, NotChecked=0, Total=110 [2019-01-08 14:47:12,191 INFO L87 Difference]: Start difference. First operand 11 states and 25 transitions. Second operand 9 states. [2019-01-08 14:47:12,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:47:12,341 INFO L93 Difference]: Finished difference Result 16 states and 37 transitions. [2019-01-08 14:47:12,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-01-08 14:47:12,341 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 6 [2019-01-08 14:47:12,342 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:47:12,342 INFO L225 Difference]: With dead ends: 16 [2019-01-08 14:47:12,342 INFO L226 Difference]: Without dead ends: 0 [2019-01-08 14:47:12,342 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=54, Invalid=78, Unknown=0, NotChecked=0, Total=132 [2019-01-08 14:47:12,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2019-01-08 14:47:12,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2019-01-08 14:47:12,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 0 states. [2019-01-08 14:47:12,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2019-01-08 14:47:12,344 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 6 [2019-01-08 14:47:12,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:47:12,344 INFO L480 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2019-01-08 14:47:12,344 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-01-08 14:47:12,344 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2019-01-08 14:47:12,344 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2019-01-08 14:47:12,348 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 0 states and 0 transitions. [2019-01-08 14:47:12,539 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2019-01-08 14:47:12,563 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2019-01-08 14:47:12,563 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2019-01-08 14:47:12,566 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2019-01-08 14:47:12,570 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2019-01-08 14:47:12,585 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2019-01-08 14:47:12,687 WARN L181 SmtUtils]: Spent 328.00 ms on a formula simplification. DAG size of input: 3441 DAG size of output: 3380