java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml -s ../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf -i ../../../trunk/examples/programs/heapseparator/speedup-poc-dd-4-limited.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.24-f57a05f [2019-01-08 14:33:23,261 INFO L170 SettingsManager]: Resetting all preferences to default values... [2019-01-08 14:33:23,263 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2019-01-08 14:33:23,275 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2019-01-08 14:33:23,307 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf [2019-01-08 14:33:23,326 INFO L110 SettingsManager]: Loading preferences was successful [2019-01-08 14:33:23,327 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2019-01-08 14:33:23,328 INFO L131 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2019-01-08 14:33:23,328 INFO L133 SettingsManager]: * Show backtranslation warnings=false [2019-01-08 14:33:23,328 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-01-08 14:33:23,328 INFO L133 SettingsManager]: * User list type=DISABLED [2019-01-08 14:33:23,328 INFO L133 SettingsManager]: * Inline calls to unimplemented procedures=true [2019-01-08 14:33:23,329 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-01-08 14:33:23,329 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-01-08 14:33:23,329 INFO L133 SettingsManager]: * Underlying domain=OctagonDomain [2019-01-08 14:33:23,329 INFO L133 SettingsManager]: * Abstract domain=ArrayDomain [2019-01-08 14:33:23,329 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-01-08 14:33:23,329 INFO L133 SettingsManager]: * Interval Domain=false [2019-01-08 14:33:23,330 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-01-08 14:33:23,330 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2019-01-08 14:33:23,330 INFO L133 SettingsManager]: * Use SBE=true [2019-01-08 14:33:23,331 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-01-08 14:33:23,331 INFO L133 SettingsManager]: * sizeof long=4 [2019-01-08 14:33:23,331 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2019-01-08 14:33:23,331 INFO L133 SettingsManager]: * sizeof POINTER=4 [2019-01-08 14:33:23,331 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2019-01-08 14:33:23,332 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-01-08 14:33:23,332 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-01-08 14:33:23,332 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-01-08 14:33:23,332 INFO L133 SettingsManager]: * sizeof long double=12 [2019-01-08 14:33:23,332 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2019-01-08 14:33:23,333 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-01-08 14:33:23,333 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-01-08 14:33:23,333 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-01-08 14:33:23,333 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2019-01-08 14:33:23,333 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-08 14:33:23,334 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-01-08 14:33:23,334 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-01-08 14:33:23,334 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-01-08 14:33:23,334 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2019-01-08 14:33:23,334 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-01-08 14:33:23,335 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in [2019-01-08 14:33:23,335 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-01-08 14:33:23,335 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2019-01-08 14:33:23,368 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-01-08 14:33:23,382 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-01-08 14:33:23,386 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-01-08 14:33:23,387 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2019-01-08 14:33:23,388 INFO L276 PluginConnector]: Boogie PL CUP Parser initialized [2019-01-08 14:33:23,389 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-4-limited.bpl [2019-01-08 14:33:23,389 INFO L111 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-4-limited.bpl' [2019-01-08 14:33:23,429 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-01-08 14:33:23,432 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-01-08 14:33:23,432 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-01-08 14:33:23,433 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-01-08 14:33:23,435 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2019-01-08 14:33:23,452 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:23" (1/1) ... [2019-01-08 14:33:23,471 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:23" (1/1) ... [2019-01-08 14:33:23,505 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-01-08 14:33:23,506 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-01-08 14:33:23,506 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-01-08 14:33:23,507 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2019-01-08 14:33:23,520 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:23" (1/1) ... [2019-01-08 14:33:23,521 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:23" (1/1) ... [2019-01-08 14:33:23,523 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:23" (1/1) ... [2019-01-08 14:33:23,523 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:23" (1/1) ... [2019-01-08 14:33:23,527 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:23" (1/1) ... [2019-01-08 14:33:23,533 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:23" (1/1) ... [2019-01-08 14:33:23,534 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:23" (1/1) ... [2019-01-08 14:33:23,537 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-01-08 14:33:23,541 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-01-08 14:33:23,541 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-01-08 14:33:23,541 INFO L276 PluginConnector]: RCFGBuilder initialized [2019-01-08 14:33:23,543 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:23" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-08 14:33:23,626 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-01-08 14:33:23,626 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-01-08 14:33:23,937 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-01-08 14:33:23,938 INFO L286 CfgBuilder]: Removed 11 assue(true) statements. [2019-01-08 14:33:23,939 INFO L202 PluginConnector]: Adding new model speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.01 02:33:23 BoogieIcfgContainer [2019-01-08 14:33:23,939 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-01-08 14:33:23,940 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-01-08 14:33:23,940 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-01-08 14:33:23,943 INFO L276 PluginConnector]: TraceAbstraction initialized [2019-01-08 14:33:23,944 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:33:23" (1/2) ... [2019-01-08 14:33:23,945 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7bfcab0a and model type speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.01 02:33:23, skipping insertion in model container [2019-01-08 14:33:23,946 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.01 02:33:23" (2/2) ... [2019-01-08 14:33:23,948 INFO L112 eAbstractionObserver]: Analyzing ICFG speedup-poc-dd-4-limited.bpl [2019-01-08 14:33:23,958 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-01-08 14:33:23,968 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 4 error locations. [2019-01-08 14:33:23,989 INFO L257 AbstractCegarLoop]: Starting to check reachability of 4 error locations. [2019-01-08 14:33:24,028 INFO L382 AbstractCegarLoop]: Interprodecural is true [2019-01-08 14:33:24,028 INFO L383 AbstractCegarLoop]: Hoare is true [2019-01-08 14:33:24,028 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-01-08 14:33:24,029 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-01-08 14:33:24,029 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-01-08 14:33:24,029 INFO L387 AbstractCegarLoop]: Difference is false [2019-01-08 14:33:24,029 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-01-08 14:33:24,029 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-01-08 14:33:24,049 INFO L276 IsEmpty]: Start isEmpty. Operand 11 states. [2019-01-08 14:33:24,060 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3 [2019-01-08 14:33:24,060 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:33:24,063 INFO L402 BasicCegarLoop]: trace histogram [1, 1] [2019-01-08 14:33:24,068 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:33:24,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:33:24,077 INFO L82 PathProgramCache]: Analyzing trace with hash 980, now seen corresponding path program 1 times [2019-01-08 14:33:24,079 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:33:24,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:33:24,139 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:33:24,139 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:33:24,139 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:33:24,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:33:24,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:33:24,367 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-08 14:33:24,367 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-08 14:33:24,367 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:33:24,379 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-08 14:33:24,409 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-08 14:33:24,410 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:33:24,417 INFO L87 Difference]: Start difference. First operand 11 states. Second operand 3 states. [2019-01-08 14:33:24,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:33:24,616 INFO L93 Difference]: Finished difference Result 21 states and 27 transitions. [2019-01-08 14:33:24,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-08 14:33:24,618 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 2 [2019-01-08 14:33:24,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:33:24,633 INFO L225 Difference]: With dead ends: 21 [2019-01-08 14:33:24,634 INFO L226 Difference]: Without dead ends: 16 [2019-01-08 14:33:24,638 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:33:24,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-08 14:33:24,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 10. [2019-01-08 14:33:24,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2019-01-08 14:33:24,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 17 transitions. [2019-01-08 14:33:24,677 INFO L78 Accepts]: Start accepts. Automaton has 10 states and 17 transitions. Word has length 2 [2019-01-08 14:33:24,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:33:24,679 INFO L480 AbstractCegarLoop]: Abstraction has 10 states and 17 transitions. [2019-01-08 14:33:24,679 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-08 14:33:24,680 INFO L276 IsEmpty]: Start isEmpty. Operand 10 states and 17 transitions. [2019-01-08 14:33:24,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:33:24,680 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:33:24,680 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:33:24,681 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:33:24,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:33:24,681 INFO L82 PathProgramCache]: Analyzing trace with hash 30306, now seen corresponding path program 1 times [2019-01-08 14:33:24,682 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:33:24,683 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:33:24,683 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:33:24,683 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:33:24,683 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:33:24,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:33:24,866 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:33:24,867 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:33:24,867 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:33:24,868 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:33:24,870 INFO L207 CegarAbsIntRunner]: [0], [16], [19] [2019-01-08 14:33:24,925 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:33:24,925 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:33:34,708 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:33:34,710 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:33:34,715 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:33:34,716 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:33:35,111 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 68.75% of their original sizes. [2019-01-08 14:33:35,111 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:33:37,347 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_79 Int) (v_idx_87 Int) (v_idx_85 Int) (v_idx_86 Int) (v_idx_83 Int) (v_idx_84 Int) (v_idx_81 Int) (v_idx_82 Int) (v_idx_80 Int)) (exists ((v_v_1521_1 Int) (v_b_121_1 Int) (v_b_120_1 Int) (v_v_1519_1 Int) (v_b_119_1 Int) (v_b_118_1 Int) (v_v_1527_1 Int) (v_v_1526_1 Int) (v_v_1525_1 Int) (v_v_1523_1 Int)) (let ((.cse0 (+ v_b_120_1 1)) (.cse3 (+ v_b_118_1 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ v_b_119_1 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 3)) (.cse5 (+ c_ULTIMATE.start_main_p4 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ v_b_118_1 2))) (and (<= .cse0 v_b_121_1) (<= v_b_121_1 .cse0) (<= .cse1 v_b_120_1) (<= .cse2 c_ULTIMATE.start_main_p4) (<= .cse3 v_b_120_1) (<= .cse4 v_b_118_1) (or (= (select |c_#memory_int| v_idx_87) v_v_1527_1) (< v_idx_87 .cse5)) (<= .cse3 v_b_119_1) (or (= (select |c_#memory_int| v_idx_81) v_v_1521_1) (< v_idx_81 .cse4) (<= v_b_118_1 v_idx_81)) (<= v_b_119_1 v_b_120_1) (<= .cse0 c_ULTIMATE.start_main_p4) (<= .cse6 c_ULTIMATE.start_main_p4) (<= (* 2 v_v_1526_1) 0) (<= v_b_119_1 .cse3) (or (< v_idx_82 v_b_118_1) (= 0 (select |c_#memory_int| v_idx_82)) (<= v_b_119_1 v_idx_82)) (<= .cse7 v_b_121_1) (or (<= .cse4 v_idx_80) (= 0 (select |c_#memory_int| v_idx_80)) (< v_idx_80 c_ULTIMATE.start_main_p1)) (<= .cse2 v_b_121_1) (<= v_b_121_1 c_ULTIMATE.start_main_p4) (<= .cse6 v_b_121_1) (or (<= .cse5 v_idx_86) (= (select |c_#memory_int| v_idx_86) v_v_1526_1) (< v_idx_86 c_ULTIMATE.start_main_p4)) (or (= (select |c_#memory_int| v_idx_83) v_v_1523_1) (<= v_b_120_1 v_idx_83) (< v_idx_83 v_b_119_1)) (<= .cse1 v_b_119_1) (<= v_v_1526_1 0) (or (< v_idx_85 v_b_121_1) (<= c_ULTIMATE.start_main_p4 v_idx_85) (= (select |c_#memory_int| v_idx_85) v_v_1525_1)) (or (< v_idx_84 v_b_120_1) (= 0 (select |c_#memory_int| v_idx_84)) (<= v_b_121_1 v_idx_84)) (or (<= c_ULTIMATE.start_main_p1 v_idx_79) (= (select |c_#memory_int| v_idx_79) v_v_1519_1)) (<= .cse7 c_ULTIMATE.start_main_p4))))) is different from false [2019-01-08 14:33:39,800 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_89 Int) (v_idx_88 Int) (v_idx_96 Int) (v_idx_94 Int) (v_idx_95 Int) (v_idx_92 Int) (v_idx_93 Int) (v_idx_90 Int) (v_idx_91 Int)) (exists ((v_v_1521_1 Int) (v_b_122_1 Int) (v_b_121_1 Int) (v_b_123_1 Int) (v_b_120_1 Int) (v_v_1519_1 Int) (v_b_119_1 Int) (v_b_118_1 Int) (v_v_1527_1 Int) (v_v_1526_1 Int) (v_v_1525_1 Int) (v_v_1523_1 Int)) (let ((.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_120_1 1)) (.cse4 (+ v_b_118_1 1)) (.cse0 (+ v_b_118_1 2)) (.cse6 (+ v_b_119_1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 3)) (.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ v_b_122_1 1))) (and (<= .cse0 v_b_122_1) (<= .cse1 v_b_121_1) (<= v_b_121_1 .cse1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_123_1) (<= .cse2 v_b_120_1) (<= .cse3 v_b_122_1) (<= .cse4 v_b_120_1) (or (= (select |c_#memory_int| v_idx_88) v_v_1519_1) (<= c_ULTIMATE.start_main_p1 v_idx_88)) (or (< v_idx_90 .cse5) (<= v_b_118_1 v_idx_90) (= (select |c_#memory_int| v_idx_90) v_v_1521_1)) (<= .cse5 v_b_118_1) (<= .cse4 v_b_119_1) (<= (+ v_b_119_1 2) v_b_123_1) (or (= (select |c_#memory_int| v_idx_96) v_v_1527_1) (< v_idx_96 v_b_123_1)) (or (< v_idx_91 v_b_118_1) (<= v_b_119_1 v_idx_91) (= 0 (select |c_#memory_int| v_idx_91))) (or (< v_idx_95 v_b_122_1) (= (select |c_#memory_int| v_idx_95) v_v_1526_1) (<= v_b_123_1 v_idx_95)) (or (< v_idx_89 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_89)) (<= .cse5 v_idx_89)) (<= v_b_119_1 v_b_120_1) (<= .cse1 v_b_122_1) (<= v_b_121_1 v_b_122_1) (<= (* 2 v_v_1526_1) 0) (<= .cse6 v_b_122_1) (<= v_b_119_1 .cse4) (or (= (select |c_#memory_int| v_idx_92) v_v_1523_1) (< v_idx_92 v_b_119_1) (<= v_b_120_1 v_idx_92)) (<= .cse0 v_b_121_1) (or (<= v_b_121_1 v_idx_93) (< v_idx_93 v_b_120_1) (= 0 (select |c_#memory_int| v_idx_93))) (<= .cse6 v_b_121_1) (<= (+ v_b_121_1 1) v_b_123_1) (<= .cse3 v_b_121_1) (<= .cse7 v_b_123_1) (<= .cse2 v_b_119_1) (<= v_v_1526_1 0) (<= v_b_123_1 .cse7) (<= (+ v_b_120_1 2) v_b_123_1) (or (= (select |c_#memory_int| v_idx_94) v_v_1525_1) (< v_idx_94 v_b_121_1) (<= v_b_122_1 v_idx_94)) (<= (+ v_b_118_1 3) v_b_123_1))))) is different from false [2019-01-08 14:33:41,329 WARN L860 $PredicateComparison]: unable to prove that (forall ((v_idx_89 Int) (v_idx_88 Int) (v_idx_96 Int) (v_idx_94 Int) (v_idx_95 Int) (v_idx_92 Int) (v_idx_93 Int) (v_idx_90 Int) (v_idx_91 Int)) (exists ((v_v_1521_1 Int) (v_b_122_1 Int) (v_b_121_1 Int) (v_b_123_1 Int) (v_b_120_1 Int) (v_v_1519_1 Int) (v_b_119_1 Int) (v_b_118_1 Int) (v_v_1527_1 Int) (v_v_1526_1 Int) (v_v_1525_1 Int) (v_v_1523_1 Int)) (let ((.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_120_1 1)) (.cse4 (+ v_b_118_1 1)) (.cse0 (+ v_b_118_1 2)) (.cse6 (+ v_b_119_1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 3)) (.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ v_b_122_1 1))) (and (<= .cse0 v_b_122_1) (<= .cse1 v_b_121_1) (<= v_b_121_1 .cse1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_123_1) (<= .cse2 v_b_120_1) (<= .cse3 v_b_122_1) (<= .cse4 v_b_120_1) (or (= (select |c_#memory_int| v_idx_88) v_v_1519_1) (<= c_ULTIMATE.start_main_p1 v_idx_88)) (or (< v_idx_90 .cse5) (<= v_b_118_1 v_idx_90) (= (select |c_#memory_int| v_idx_90) v_v_1521_1)) (<= .cse5 v_b_118_1) (<= .cse4 v_b_119_1) (<= (+ v_b_119_1 2) v_b_123_1) (or (= (select |c_#memory_int| v_idx_96) v_v_1527_1) (< v_idx_96 v_b_123_1)) (or (< v_idx_91 v_b_118_1) (<= v_b_119_1 v_idx_91) (= 0 (select |c_#memory_int| v_idx_91))) (or (< v_idx_95 v_b_122_1) (= (select |c_#memory_int| v_idx_95) v_v_1526_1) (<= v_b_123_1 v_idx_95)) (or (< v_idx_89 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_89)) (<= .cse5 v_idx_89)) (<= v_b_119_1 v_b_120_1) (<= .cse1 v_b_122_1) (<= v_b_121_1 v_b_122_1) (<= (* 2 v_v_1526_1) 0) (<= .cse6 v_b_122_1) (<= v_b_119_1 .cse4) (or (= (select |c_#memory_int| v_idx_92) v_v_1523_1) (< v_idx_92 v_b_119_1) (<= v_b_120_1 v_idx_92)) (<= .cse0 v_b_121_1) (or (<= v_b_121_1 v_idx_93) (< v_idx_93 v_b_120_1) (= 0 (select |c_#memory_int| v_idx_93))) (<= .cse6 v_b_121_1) (<= (+ v_b_121_1 1) v_b_123_1) (<= .cse3 v_b_121_1) (<= .cse7 v_b_123_1) (<= .cse2 v_b_119_1) (<= v_v_1526_1 0) (<= v_b_123_1 .cse7) (<= (+ v_b_120_1 2) v_b_123_1) (or (= (select |c_#memory_int| v_idx_94) v_v_1525_1) (< v_idx_94 v_b_121_1) (<= v_b_122_1 v_idx_94)) (<= (+ v_b_118_1 3) v_b_123_1))))) is different from true [2019-01-08 14:33:41,330 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:33:41,330 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:33:41,331 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:33:41,331 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:33:41,331 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:33:41,332 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:33:41,333 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:33:41,333 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=2, Unknown=3, NotChecked=2, Total=12 [2019-01-08 14:33:41,333 INFO L87 Difference]: Start difference. First operand 10 states and 17 transitions. Second operand 4 states. [2019-01-08 14:33:43,641 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_89 Int) (v_idx_88 Int) (v_idx_96 Int) (v_idx_94 Int) (v_idx_95 Int) (v_idx_92 Int) (v_idx_93 Int) (v_idx_90 Int) (v_idx_91 Int)) (exists ((v_v_1521_1 Int) (v_b_122_1 Int) (v_b_121_1 Int) (v_b_123_1 Int) (v_b_120_1 Int) (v_v_1519_1 Int) (v_b_119_1 Int) (v_b_118_1 Int) (v_v_1527_1 Int) (v_v_1526_1 Int) (v_v_1525_1 Int) (v_v_1523_1 Int)) (let ((.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_120_1 1)) (.cse4 (+ v_b_118_1 1)) (.cse0 (+ v_b_118_1 2)) (.cse6 (+ v_b_119_1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 3)) (.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ v_b_122_1 1))) (and (<= .cse0 v_b_122_1) (<= .cse1 v_b_121_1) (<= v_b_121_1 .cse1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_123_1) (<= .cse2 v_b_120_1) (<= .cse3 v_b_122_1) (<= .cse4 v_b_120_1) (or (= (select |c_#memory_int| v_idx_88) v_v_1519_1) (<= c_ULTIMATE.start_main_p1 v_idx_88)) (or (< v_idx_90 .cse5) (<= v_b_118_1 v_idx_90) (= (select |c_#memory_int| v_idx_90) v_v_1521_1)) (<= .cse5 v_b_118_1) (<= .cse4 v_b_119_1) (<= (+ v_b_119_1 2) v_b_123_1) (or (= (select |c_#memory_int| v_idx_96) v_v_1527_1) (< v_idx_96 v_b_123_1)) (or (< v_idx_91 v_b_118_1) (<= v_b_119_1 v_idx_91) (= 0 (select |c_#memory_int| v_idx_91))) (or (< v_idx_95 v_b_122_1) (= (select |c_#memory_int| v_idx_95) v_v_1526_1) (<= v_b_123_1 v_idx_95)) (or (< v_idx_89 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_89)) (<= .cse5 v_idx_89)) (<= v_b_119_1 v_b_120_1) (<= .cse1 v_b_122_1) (<= v_b_121_1 v_b_122_1) (<= (* 2 v_v_1526_1) 0) (<= .cse6 v_b_122_1) (<= v_b_119_1 .cse4) (or (= (select |c_#memory_int| v_idx_92) v_v_1523_1) (< v_idx_92 v_b_119_1) (<= v_b_120_1 v_idx_92)) (<= .cse0 v_b_121_1) (or (<= v_b_121_1 v_idx_93) (< v_idx_93 v_b_120_1) (= 0 (select |c_#memory_int| v_idx_93))) (<= .cse6 v_b_121_1) (<= (+ v_b_121_1 1) v_b_123_1) (<= .cse3 v_b_121_1) (<= .cse7 v_b_123_1) (<= .cse2 v_b_119_1) (<= v_v_1526_1 0) (<= v_b_123_1 .cse7) (<= (+ v_b_120_1 2) v_b_123_1) (or (= (select |c_#memory_int| v_idx_94) v_v_1525_1) (< v_idx_94 v_b_121_1) (<= v_b_122_1 v_idx_94)) (<= (+ v_b_118_1 3) v_b_123_1))))) (forall ((v_idx_79 Int) (v_idx_87 Int) (v_idx_85 Int) (v_idx_86 Int) (v_idx_83 Int) (v_idx_84 Int) (v_idx_81 Int) (v_idx_82 Int) (v_idx_80 Int)) (exists ((v_v_1521_1 Int) (v_b_121_1 Int) (v_b_120_1 Int) (v_v_1519_1 Int) (v_b_119_1 Int) (v_b_118_1 Int) (v_v_1527_1 Int) (v_v_1526_1 Int) (v_v_1525_1 Int) (v_v_1523_1 Int)) (let ((.cse8 (+ v_b_120_1 1)) (.cse11 (+ v_b_118_1 1)) (.cse12 (+ c_ULTIMATE.start_main_p1 1)) (.cse10 (+ v_b_119_1 1)) (.cse14 (+ c_ULTIMATE.start_main_p1 3)) (.cse13 (+ c_ULTIMATE.start_main_p4 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 2)) (.cse15 (+ v_b_118_1 2))) (and (<= .cse8 v_b_121_1) (<= v_b_121_1 .cse8) (<= .cse9 v_b_120_1) (<= .cse10 c_ULTIMATE.start_main_p4) (<= .cse11 v_b_120_1) (<= .cse12 v_b_118_1) (or (= (select |c_#memory_int| v_idx_87) v_v_1527_1) (< v_idx_87 .cse13)) (<= .cse11 v_b_119_1) (or (= (select |c_#memory_int| v_idx_81) v_v_1521_1) (< v_idx_81 .cse12) (<= v_b_118_1 v_idx_81)) (<= v_b_119_1 v_b_120_1) (<= .cse8 c_ULTIMATE.start_main_p4) (<= .cse14 c_ULTIMATE.start_main_p4) (<= (* 2 v_v_1526_1) 0) (<= v_b_119_1 .cse11) (or (< v_idx_82 v_b_118_1) (= 0 (select |c_#memory_int| v_idx_82)) (<= v_b_119_1 v_idx_82)) (<= .cse15 v_b_121_1) (or (<= .cse12 v_idx_80) (= 0 (select |c_#memory_int| v_idx_80)) (< v_idx_80 c_ULTIMATE.start_main_p1)) (<= .cse10 v_b_121_1) (<= v_b_121_1 c_ULTIMATE.start_main_p4) (<= .cse14 v_b_121_1) (or (<= .cse13 v_idx_86) (= (select |c_#memory_int| v_idx_86) v_v_1526_1) (< v_idx_86 c_ULTIMATE.start_main_p4)) (or (= (select |c_#memory_int| v_idx_83) v_v_1523_1) (<= v_b_120_1 v_idx_83) (< v_idx_83 v_b_119_1)) (<= .cse9 v_b_119_1) (<= v_v_1526_1 0) (or (< v_idx_85 v_b_121_1) (<= c_ULTIMATE.start_main_p4 v_idx_85) (= (select |c_#memory_int| v_idx_85) v_v_1525_1)) (or (< v_idx_84 v_b_120_1) (= 0 (select |c_#memory_int| v_idx_84)) (<= v_b_121_1 v_idx_84)) (or (<= c_ULTIMATE.start_main_p1 v_idx_79) (= (select |c_#memory_int| v_idx_79) v_v_1519_1)) (<= .cse15 c_ULTIMATE.start_main_p4)))))) is different from false [2019-01-08 14:34:07,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:34:07,976 INFO L93 Difference]: Finished difference Result 12 states and 23 transitions. [2019-01-08 14:34:07,976 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-08 14:34:07,976 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-08 14:34:07,976 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:34:07,977 INFO L225 Difference]: With dead ends: 12 [2019-01-08 14:34:07,977 INFO L226 Difference]: Without dead ends: 11 [2019-01-08 14:34:07,978 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 8.4s TimeCoverageRelationStatistics Valid=7, Invalid=3, Unknown=4, NotChecked=6, Total=20 [2019-01-08 14:34:07,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2019-01-08 14:34:07,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2019-01-08 14:34:07,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11 states. [2019-01-08 14:34:07,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 22 transitions. [2019-01-08 14:34:07,985 INFO L78 Accepts]: Start accepts. Automaton has 11 states and 22 transitions. Word has length 3 [2019-01-08 14:34:07,986 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:34:07,986 INFO L480 AbstractCegarLoop]: Abstraction has 11 states and 22 transitions. [2019-01-08 14:34:07,986 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:34:07,986 INFO L276 IsEmpty]: Start isEmpty. Operand 11 states and 22 transitions. [2019-01-08 14:34:07,987 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:34:07,987 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:34:07,987 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:34:07,988 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:34:07,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:34:07,990 INFO L82 PathProgramCache]: Analyzing trace with hash 30432, now seen corresponding path program 1 times [2019-01-08 14:34:07,990 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:34:07,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:34:07,991 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:34:07,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:34:07,991 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:34:08,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:34:08,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:34:08,082 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-08 14:34:08,082 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-08 14:34:08,083 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:34:08,084 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-08 14:34:08,084 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-08 14:34:08,085 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:34:08,085 INFO L87 Difference]: Start difference. First operand 11 states and 22 transitions. Second operand 3 states. [2019-01-08 14:34:08,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:34:08,360 INFO L93 Difference]: Finished difference Result 17 states and 27 transitions. [2019-01-08 14:34:08,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-08 14:34:08,361 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-01-08 14:34:08,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:34:08,362 INFO L225 Difference]: With dead ends: 17 [2019-01-08 14:34:08,362 INFO L226 Difference]: Without dead ends: 16 [2019-01-08 14:34:08,362 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:34:08,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-08 14:34:08,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 12. [2019-01-08 14:34:08,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2019-01-08 14:34:08,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 23 transitions. [2019-01-08 14:34:08,370 INFO L78 Accepts]: Start accepts. Automaton has 12 states and 23 transitions. Word has length 3 [2019-01-08 14:34:08,370 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:34:08,371 INFO L480 AbstractCegarLoop]: Abstraction has 12 states and 23 transitions. [2019-01-08 14:34:08,371 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-08 14:34:08,371 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 23 transitions. [2019-01-08 14:34:08,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:34:08,371 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:34:08,371 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:34:08,373 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:34:08,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:34:08,373 INFO L82 PathProgramCache]: Analyzing trace with hash 29996, now seen corresponding path program 1 times [2019-01-08 14:34:08,373 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:34:08,374 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:34:08,374 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:34:08,375 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:34:08,375 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:34:08,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:34:08,530 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:34:08,530 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:34:08,530 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:34:08,531 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:34:08,531 INFO L207 CegarAbsIntRunner]: [0], [6], [19] [2019-01-08 14:34:08,534 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:34:08,534 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:34:14,614 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:34:14,614 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:34:14,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:34:14,615 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:34:14,858 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 75% of their original sizes. [2019-01-08 14:34:14,858 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:34:17,411 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_179 Int) (v_idx_180 Int) (v_idx_181 Int) (v_idx_182 Int) (v_idx_183 Int) (v_idx_177 Int) (v_idx_178 Int) (v_idx_175 Int) (v_idx_176 Int)) (exists ((v_v_1450_2 Int) (v_v_1454_2 Int) (v_b_134_2 Int) (v_v_1452_2 Int) (v_v_1451_2 Int) (v_b_137_2 Int) (v_v_1458_2 Int) (v_b_138_2 Int) (v_b_135_2 Int) (v_v_1456_2 Int) (v_b_136_2 Int) (v_b_139_2 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p1 2)) (.cse6 (+ v_b_134_2 2)) (.cse5 (+ v_b_135_2 1)) (.cse4 (+ v_b_136_2 1)) (.cse3 (+ v_b_134_2 1)) (.cse7 (+ v_b_138_2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 3)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_2) (<= .cse0 v_b_135_2) (or (< v_idx_177 .cse1) (= (select |c_#memory_int| v_idx_177) v_v_1452_2) (<= v_b_134_2 v_idx_177)) (<= (+ v_b_136_2 2) v_b_139_2) (<= .cse2 v_b_137_2) (<= .cse3 v_b_135_2) (or (<= v_b_139_2 v_idx_182) (= 0 (select |c_#memory_int| v_idx_182)) (< v_idx_182 v_b_138_2)) (or (= (select |c_#memory_int| v_idx_178) 0) (< v_idx_178 v_b_134_2) (<= v_b_135_2 v_idx_178)) (<= v_b_135_2 v_b_136_2) (<= v_b_137_2 .cse4) (or (= (select |c_#memory_int| v_idx_179) v_v_1454_2) (<= v_b_136_2 v_idx_179) (< v_idx_179 v_b_135_2)) (<= .cse5 v_b_138_2) (or (< v_idx_181 v_b_137_2) (<= v_b_138_2 v_idx_181) (= (select |c_#memory_int| v_idx_181) v_v_1456_2)) (<= 0 (* 2 v_v_1451_2)) (<= (+ v_b_137_2 1) v_b_139_2) (<= (+ v_b_135_2 2) v_b_139_2) (<= (+ v_b_134_2 3) v_b_139_2) (<= .cse0 v_b_136_2) (<= v_b_135_2 .cse3) (<= .cse6 v_b_137_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_175) (= (select |c_#memory_int| v_idx_175) v_v_1450_2)) (or (< v_idx_176 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_176) v_v_1451_2) (<= .cse1 v_idx_176)) (<= .cse6 v_b_138_2) (<= .cse5 v_b_137_2) (<= v_b_137_2 v_b_138_2) (or (< v_idx_183 v_b_139_2) (= (select |c_#memory_int| v_idx_183) v_v_1458_2)) (<= .cse4 v_b_137_2) (<= .cse4 v_b_138_2) (<= v_b_139_2 .cse7) (<= .cse3 v_b_136_2) (<= 0 v_v_1451_2) (<= .cse7 v_b_139_2) (or (< v_idx_180 v_b_136_2) (<= v_b_137_2 v_idx_180) (= (select |c_#memory_int| v_idx_180) 0)) (<= .cse2 v_b_138_2) (<= .cse1 v_b_134_2))))) is different from false [2019-01-08 14:34:20,095 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_191 Int) (v_idx_192 Int) (v_idx_190 Int) (v_idx_184 Int) (v_idx_185 Int) (v_idx_188 Int) (v_idx_189 Int) (v_idx_186 Int) (v_idx_187 Int)) (exists ((v_v_1450_2 Int) (v_v_1454_2 Int) (v_b_134_2 Int) (v_v_1452_2 Int) (v_v_1451_2 Int) (v_b_137_2 Int) (v_v_1458_2 Int) (v_b_138_2 Int) (v_v_1456_2 Int) (v_b_135_2 Int) (v_b_136_2 Int) (v_b_139_2 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse6 (+ v_b_134_2 2)) (.cse5 (+ v_b_135_2 1)) (.cse4 (+ v_b_136_2 1)) (.cse3 (+ v_b_134_2 1)) (.cse7 (+ v_b_138_2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 3)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= (select |c_#memory_int| v_idx_185) v_v_1451_2) (< v_idx_185 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_185)) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_2) (<= .cse1 v_b_135_2) (<= (+ v_b_136_2 2) v_b_139_2) (<= .cse2 v_b_137_2) (<= .cse3 v_b_135_2) (or (= (select |c_#memory_int| v_idx_190) v_v_1456_2) (<= v_b_138_2 v_idx_190) (< v_idx_190 v_b_137_2)) (<= v_b_135_2 v_b_136_2) (<= v_b_137_2 .cse4) (<= .cse5 v_b_138_2) (<= 0 (* 2 v_v_1451_2)) (or (< v_idx_186 .cse0) (<= v_b_134_2 v_idx_186) (= (select |c_#memory_int| v_idx_186) v_v_1452_2)) (<= (+ v_b_137_2 1) v_b_139_2) (<= (+ v_b_135_2 2) v_b_139_2) (<= (+ v_b_134_2 3) v_b_139_2) (<= .cse1 v_b_136_2) (<= v_b_135_2 .cse3) (<= .cse6 v_b_137_2) (or (< v_idx_192 v_b_139_2) (= (select |c_#memory_int| v_idx_192) v_v_1458_2)) (<= .cse6 v_b_138_2) (<= .cse5 v_b_137_2) (or (< v_idx_187 v_b_134_2) (= 0 (select |c_#memory_int| v_idx_187)) (<= v_b_135_2 v_idx_187)) (<= v_b_137_2 v_b_138_2) (or (= (select |c_#memory_int| v_idx_188) v_v_1454_2) (<= v_b_136_2 v_idx_188) (< v_idx_188 v_b_135_2)) (<= .cse4 v_b_137_2) (<= .cse4 v_b_138_2) (<= v_b_139_2 .cse7) (or (<= v_b_139_2 v_idx_191) (< v_idx_191 v_b_138_2) (= (select |c_#memory_int| v_idx_191) 0)) (or (= (select |c_#memory_int| v_idx_189) 0) (< v_idx_189 v_b_136_2) (<= v_b_137_2 v_idx_189)) (<= .cse3 v_b_136_2) (<= 0 v_v_1451_2) (<= .cse7 v_b_139_2) (<= .cse2 v_b_138_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_184) (= (select |c_#memory_int| v_idx_184) v_v_1450_2)) (<= .cse0 v_b_134_2))))) is different from false [2019-01-08 14:34:20,274 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:34:20,274 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:34:20,274 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:34:20,274 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:34:20,274 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:34:20,275 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:34:20,275 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:34:20,275 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-08 14:34:20,276 INFO L87 Difference]: Start difference. First operand 12 states and 23 transitions. Second operand 4 states. [2019-01-08 14:34:22,903 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_191 Int) (v_idx_192 Int) (v_idx_190 Int) (v_idx_184 Int) (v_idx_185 Int) (v_idx_188 Int) (v_idx_189 Int) (v_idx_186 Int) (v_idx_187 Int)) (exists ((v_v_1450_2 Int) (v_v_1454_2 Int) (v_b_134_2 Int) (v_v_1452_2 Int) (v_v_1451_2 Int) (v_b_137_2 Int) (v_v_1458_2 Int) (v_b_138_2 Int) (v_v_1456_2 Int) (v_b_135_2 Int) (v_b_136_2 Int) (v_b_139_2 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse6 (+ v_b_134_2 2)) (.cse5 (+ v_b_135_2 1)) (.cse4 (+ v_b_136_2 1)) (.cse3 (+ v_b_134_2 1)) (.cse7 (+ v_b_138_2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 3)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= (select |c_#memory_int| v_idx_185) v_v_1451_2) (< v_idx_185 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_185)) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_2) (<= .cse1 v_b_135_2) (<= (+ v_b_136_2 2) v_b_139_2) (<= .cse2 v_b_137_2) (<= .cse3 v_b_135_2) (or (= (select |c_#memory_int| v_idx_190) v_v_1456_2) (<= v_b_138_2 v_idx_190) (< v_idx_190 v_b_137_2)) (<= v_b_135_2 v_b_136_2) (<= v_b_137_2 .cse4) (<= .cse5 v_b_138_2) (<= 0 (* 2 v_v_1451_2)) (or (< v_idx_186 .cse0) (<= v_b_134_2 v_idx_186) (= (select |c_#memory_int| v_idx_186) v_v_1452_2)) (<= (+ v_b_137_2 1) v_b_139_2) (<= (+ v_b_135_2 2) v_b_139_2) (<= (+ v_b_134_2 3) v_b_139_2) (<= .cse1 v_b_136_2) (<= v_b_135_2 .cse3) (<= .cse6 v_b_137_2) (or (< v_idx_192 v_b_139_2) (= (select |c_#memory_int| v_idx_192) v_v_1458_2)) (<= .cse6 v_b_138_2) (<= .cse5 v_b_137_2) (or (< v_idx_187 v_b_134_2) (= 0 (select |c_#memory_int| v_idx_187)) (<= v_b_135_2 v_idx_187)) (<= v_b_137_2 v_b_138_2) (or (= (select |c_#memory_int| v_idx_188) v_v_1454_2) (<= v_b_136_2 v_idx_188) (< v_idx_188 v_b_135_2)) (<= .cse4 v_b_137_2) (<= .cse4 v_b_138_2) (<= v_b_139_2 .cse7) (or (<= v_b_139_2 v_idx_191) (< v_idx_191 v_b_138_2) (= (select |c_#memory_int| v_idx_191) 0)) (or (= (select |c_#memory_int| v_idx_189) 0) (< v_idx_189 v_b_136_2) (<= v_b_137_2 v_idx_189)) (<= .cse3 v_b_136_2) (<= 0 v_v_1451_2) (<= .cse7 v_b_139_2) (<= .cse2 v_b_138_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_184) (= (select |c_#memory_int| v_idx_184) v_v_1450_2)) (<= .cse0 v_b_134_2))))) (forall ((v_idx_179 Int) (v_idx_180 Int) (v_idx_181 Int) (v_idx_182 Int) (v_idx_183 Int) (v_idx_177 Int) (v_idx_178 Int) (v_idx_175 Int) (v_idx_176 Int)) (exists ((v_v_1450_2 Int) (v_v_1454_2 Int) (v_b_134_2 Int) (v_v_1452_2 Int) (v_v_1451_2 Int) (v_b_137_2 Int) (v_v_1458_2 Int) (v_b_138_2 Int) (v_b_135_2 Int) (v_v_1456_2 Int) (v_b_136_2 Int) (v_b_139_2 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p1 2)) (.cse14 (+ v_b_134_2 2)) (.cse13 (+ v_b_135_2 1)) (.cse12 (+ v_b_136_2 1)) (.cse11 (+ v_b_134_2 1)) (.cse15 (+ v_b_138_2 1)) (.cse10 (+ c_ULTIMATE.start_main_p1 3)) (.cse9 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_2) (<= .cse8 v_b_135_2) (or (< v_idx_177 .cse9) (= (select |c_#memory_int| v_idx_177) v_v_1452_2) (<= v_b_134_2 v_idx_177)) (<= (+ v_b_136_2 2) v_b_139_2) (<= .cse10 v_b_137_2) (<= .cse11 v_b_135_2) (or (<= v_b_139_2 v_idx_182) (= 0 (select |c_#memory_int| v_idx_182)) (< v_idx_182 v_b_138_2)) (or (= (select |c_#memory_int| v_idx_178) 0) (< v_idx_178 v_b_134_2) (<= v_b_135_2 v_idx_178)) (<= v_b_135_2 v_b_136_2) (<= v_b_137_2 .cse12) (or (= (select |c_#memory_int| v_idx_179) v_v_1454_2) (<= v_b_136_2 v_idx_179) (< v_idx_179 v_b_135_2)) (<= .cse13 v_b_138_2) (or (< v_idx_181 v_b_137_2) (<= v_b_138_2 v_idx_181) (= (select |c_#memory_int| v_idx_181) v_v_1456_2)) (<= 0 (* 2 v_v_1451_2)) (<= (+ v_b_137_2 1) v_b_139_2) (<= (+ v_b_135_2 2) v_b_139_2) (<= (+ v_b_134_2 3) v_b_139_2) (<= .cse8 v_b_136_2) (<= v_b_135_2 .cse11) (<= .cse14 v_b_137_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_175) (= (select |c_#memory_int| v_idx_175) v_v_1450_2)) (or (< v_idx_176 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_176) v_v_1451_2) (<= .cse9 v_idx_176)) (<= .cse14 v_b_138_2) (<= .cse13 v_b_137_2) (<= v_b_137_2 v_b_138_2) (or (< v_idx_183 v_b_139_2) (= (select |c_#memory_int| v_idx_183) v_v_1458_2)) (<= .cse12 v_b_137_2) (<= .cse12 v_b_138_2) (<= v_b_139_2 .cse15) (<= .cse11 v_b_136_2) (<= 0 v_v_1451_2) (<= .cse15 v_b_139_2) (or (< v_idx_180 v_b_136_2) (<= v_b_137_2 v_idx_180) (= (select |c_#memory_int| v_idx_180) 0)) (<= .cse10 v_b_138_2) (<= .cse9 v_b_134_2)))))) is different from false [2019-01-08 14:34:40,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:34:40,598 INFO L93 Difference]: Finished difference Result 14 states and 29 transitions. [2019-01-08 14:34:40,598 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-08 14:34:40,599 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-08 14:34:40,599 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:34:40,599 INFO L225 Difference]: With dead ends: 14 [2019-01-08 14:34:40,599 INFO L226 Difference]: Without dead ends: 13 [2019-01-08 14:34:40,600 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 8.1s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:34:40,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2019-01-08 14:34:40,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 12. [2019-01-08 14:34:40,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2019-01-08 14:34:40,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 23 transitions. [2019-01-08 14:34:40,607 INFO L78 Accepts]: Start accepts. Automaton has 12 states and 23 transitions. Word has length 3 [2019-01-08 14:34:40,607 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:34:40,607 INFO L480 AbstractCegarLoop]: Abstraction has 12 states and 23 transitions. [2019-01-08 14:34:40,608 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:34:40,608 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 23 transitions. [2019-01-08 14:34:40,608 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:34:40,608 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:34:40,608 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:34:40,609 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:34:40,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:34:40,609 INFO L82 PathProgramCache]: Analyzing trace with hash 30120, now seen corresponding path program 1 times [2019-01-08 14:34:40,609 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:34:40,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:34:40,610 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:34:40,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:34:40,611 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:34:40,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:34:40,778 WARN L181 SmtUtils]: Spent 101.00 ms on a formula simplification. DAG size of input: 21 DAG size of output: 13 [2019-01-08 14:34:40,793 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:34:40,793 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:34:40,794 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:34:40,794 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:34:40,794 INFO L207 CegarAbsIntRunner]: [0], [10], [19] [2019-01-08 14:34:40,795 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:34:40,795 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:34:47,276 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:34:47,277 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:34:47,277 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:34:47,278 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:34:47,524 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 68.75% of their original sizes. [2019-01-08 14:34:47,524 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:34:49,925 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_278 Int) (v_idx_279 Int) (v_idx_272 Int) (v_idx_273 Int) (v_idx_271 Int) (v_idx_276 Int) (v_idx_277 Int) (v_idx_274 Int) (v_idx_275 Int)) (exists ((v_v_1509_3 Int) (v_v_1507_3 Int) (v_v_1504_3 Int) (v_b_127_3 Int) (v_v_1505_3 Int) (v_v_1503_3 Int) (v_b_124_3 Int) (v_v_1501_3 Int) (v_b_126_3 Int) (v_b_125_3 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p1 3)) (.cse3 (+ v_b_126_3 1)) (.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_124_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 2)) (.cse5 (+ c_ULTIMATE.start_main_p1 1))) (and (<= .cse0 v_b_126_3) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_127_3) (or (= (select |c_#memory_int| v_idx_277) v_v_1507_3) (<= v_b_126_3 v_idx_277) (< v_idx_277 v_b_125_3)) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_127_3) (<= v_v_1504_3 0) (or (= 0 (select |c_#memory_int| v_idx_276)) (< v_idx_276 v_b_124_3) (<= v_b_125_3 v_idx_276)) (<= v_b_125_3 v_b_126_3) (or (< v_idx_279 v_b_127_3) (= (select |c_#memory_int| v_idx_279) v_v_1509_3)) (or (<= c_ULTIMATE.start_main_p1 v_idx_271) (= (select |c_#memory_int| v_idx_271) v_v_1501_3)) (<= .cse1 v_b_126_3) (<= .cse2 v_b_126_3) (<= (+ v_b_125_3 1) v_b_127_3) (<= .cse2 v_b_125_3) (<= .cse3 v_b_127_3) (<= (* 2 v_v_1504_3) 0) (or (<= v_b_127_3 v_idx_278) (= 0 (select |c_#memory_int| v_idx_278)) (< v_idx_278 v_b_126_3)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_124_3) (or (= (select |c_#memory_int| v_idx_275) v_v_1505_3) (< v_idx_275 .cse4) (<= v_b_124_3 v_idx_275)) (<= .cse0 v_b_125_3) (<= v_b_127_3 .cse3) (<= (+ v_b_124_3 2) v_b_127_3) (or (< v_idx_274 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_274) v_v_1504_3) (<= .cse4 v_idx_274)) (<= .cse5 c_ULTIMATE.start_main_p2) (<= .cse4 v_b_124_3) (<= v_b_125_3 .cse2) (or (= (select |c_#memory_int| v_idx_272) 0) (<= .cse5 v_idx_272) (< v_idx_272 c_ULTIMATE.start_main_p1)) (<= .cse1 v_b_125_3) (or (< v_idx_273 .cse5) (<= c_ULTIMATE.start_main_p2 v_idx_273) (= (select |c_#memory_int| v_idx_273) v_v_1503_3)))))) is different from false [2019-01-08 14:34:52,597 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_280 Int) (v_idx_283 Int) (v_idx_284 Int) (v_idx_281 Int) (v_idx_282 Int) (v_idx_287 Int) (v_idx_288 Int) (v_idx_285 Int) (v_idx_286 Int)) (exists ((v_b_122_3 Int) (v_v_1509_3 Int) (v_v_1507_3 Int) (v_v_1504_3 Int) (v_b_127_3 Int) (v_v_1505_3 Int) (v_v_1503_3 Int) (v_b_124_3 Int) (v_v_1501_3 Int) (v_b_123_3 Int) (v_b_126_3 Int) (v_b_125_3 Int)) (let ((.cse4 (+ c_ULTIMATE.start_main_p1 2)) (.cse5 (+ v_b_122_3 2)) (.cse0 (+ c_ULTIMATE.start_main_p1 3)) (.cse7 (+ v_b_126_3 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ v_b_123_3 1)) (.cse6 (+ v_b_124_3 1)) (.cse1 (+ v_b_122_3 1))) (and (<= .cse0 v_b_126_3) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_127_3) (<= v_v_1504_3 0) (or (<= c_ULTIMATE.start_main_p1 v_idx_280) (= (select |c_#memory_int| v_idx_280) v_v_1501_3)) (<= (+ v_b_122_3 3) v_b_127_3) (or (= 0 (select |c_#memory_int| v_idx_287)) (< v_idx_287 v_b_126_3) (<= v_b_127_3 v_idx_287)) (<= v_b_125_3 v_b_126_3) (<= .cse1 v_b_124_3) (<= v_b_123_3 .cse1) (<= .cse2 v_b_122_3) (<= .cse3 v_b_125_3) (<= .cse4 v_b_123_3) (<= .cse5 v_b_126_3) (or (<= .cse2 v_idx_281) (< v_idx_281 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_281))) (or (<= v_b_125_3 v_idx_285) (= 0 (select |c_#memory_int| v_idx_285)) (< v_idx_285 v_b_124_3)) (<= .cse6 v_b_126_3) (<= (+ v_b_125_3 1) v_b_127_3) (<= .cse6 v_b_125_3) (<= .cse7 v_b_127_3) (or (= (select |c_#memory_int| v_idx_288) v_v_1509_3) (< v_idx_288 v_b_127_3)) (or (< v_idx_286 v_b_125_3) (<= v_b_126_3 v_idx_286) (= (select |c_#memory_int| v_idx_286) v_v_1507_3)) (<= (* 2 v_v_1504_3) 0) (<= .cse4 v_b_124_3) (or (<= v_b_124_3 v_idx_284) (< v_idx_284 v_b_123_3) (= (select |c_#memory_int| v_idx_284) v_v_1505_3)) (<= (+ v_b_123_3 2) v_b_127_3) (or (= (select |c_#memory_int| v_idx_283) v_v_1504_3) (< v_idx_283 v_b_122_3) (<= v_b_123_3 v_idx_283)) (<= v_b_123_3 v_b_124_3) (<= .cse5 v_b_125_3) (<= .cse0 v_b_125_3) (<= v_b_127_3 .cse7) (<= (+ v_b_124_3 2) v_b_127_3) (or (< v_idx_282 .cse2) (= (select |c_#memory_int| v_idx_282) v_v_1503_3) (<= v_b_122_3 v_idx_282)) (<= .cse3 v_b_126_3) (<= v_b_125_3 .cse6) (<= .cse1 v_b_123_3))))) is different from false [2019-01-08 14:34:52,761 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:34:52,762 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:34:52,762 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:34:52,762 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:34:52,762 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:34:52,762 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:34:52,763 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:34:52,763 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-08 14:34:52,763 INFO L87 Difference]: Start difference. First operand 12 states and 23 transitions. Second operand 4 states. [2019-01-08 14:34:55,245 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_280 Int) (v_idx_283 Int) (v_idx_284 Int) (v_idx_281 Int) (v_idx_282 Int) (v_idx_287 Int) (v_idx_288 Int) (v_idx_285 Int) (v_idx_286 Int)) (exists ((v_b_122_3 Int) (v_v_1509_3 Int) (v_v_1507_3 Int) (v_v_1504_3 Int) (v_b_127_3 Int) (v_v_1505_3 Int) (v_v_1503_3 Int) (v_b_124_3 Int) (v_v_1501_3 Int) (v_b_123_3 Int) (v_b_126_3 Int) (v_b_125_3 Int)) (let ((.cse4 (+ c_ULTIMATE.start_main_p1 2)) (.cse5 (+ v_b_122_3 2)) (.cse0 (+ c_ULTIMATE.start_main_p1 3)) (.cse7 (+ v_b_126_3 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ v_b_123_3 1)) (.cse6 (+ v_b_124_3 1)) (.cse1 (+ v_b_122_3 1))) (and (<= .cse0 v_b_126_3) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_127_3) (<= v_v_1504_3 0) (or (<= c_ULTIMATE.start_main_p1 v_idx_280) (= (select |c_#memory_int| v_idx_280) v_v_1501_3)) (<= (+ v_b_122_3 3) v_b_127_3) (or (= 0 (select |c_#memory_int| v_idx_287)) (< v_idx_287 v_b_126_3) (<= v_b_127_3 v_idx_287)) (<= v_b_125_3 v_b_126_3) (<= .cse1 v_b_124_3) (<= v_b_123_3 .cse1) (<= .cse2 v_b_122_3) (<= .cse3 v_b_125_3) (<= .cse4 v_b_123_3) (<= .cse5 v_b_126_3) (or (<= .cse2 v_idx_281) (< v_idx_281 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_281))) (or (<= v_b_125_3 v_idx_285) (= 0 (select |c_#memory_int| v_idx_285)) (< v_idx_285 v_b_124_3)) (<= .cse6 v_b_126_3) (<= (+ v_b_125_3 1) v_b_127_3) (<= .cse6 v_b_125_3) (<= .cse7 v_b_127_3) (or (= (select |c_#memory_int| v_idx_288) v_v_1509_3) (< v_idx_288 v_b_127_3)) (or (< v_idx_286 v_b_125_3) (<= v_b_126_3 v_idx_286) (= (select |c_#memory_int| v_idx_286) v_v_1507_3)) (<= (* 2 v_v_1504_3) 0) (<= .cse4 v_b_124_3) (or (<= v_b_124_3 v_idx_284) (< v_idx_284 v_b_123_3) (= (select |c_#memory_int| v_idx_284) v_v_1505_3)) (<= (+ v_b_123_3 2) v_b_127_3) (or (= (select |c_#memory_int| v_idx_283) v_v_1504_3) (< v_idx_283 v_b_122_3) (<= v_b_123_3 v_idx_283)) (<= v_b_123_3 v_b_124_3) (<= .cse5 v_b_125_3) (<= .cse0 v_b_125_3) (<= v_b_127_3 .cse7) (<= (+ v_b_124_3 2) v_b_127_3) (or (< v_idx_282 .cse2) (= (select |c_#memory_int| v_idx_282) v_v_1503_3) (<= v_b_122_3 v_idx_282)) (<= .cse3 v_b_126_3) (<= v_b_125_3 .cse6) (<= .cse1 v_b_123_3))))) (forall ((v_idx_278 Int) (v_idx_279 Int) (v_idx_272 Int) (v_idx_273 Int) (v_idx_271 Int) (v_idx_276 Int) (v_idx_277 Int) (v_idx_274 Int) (v_idx_275 Int)) (exists ((v_v_1509_3 Int) (v_v_1507_3 Int) (v_v_1504_3 Int) (v_b_127_3 Int) (v_v_1505_3 Int) (v_v_1503_3 Int) (v_b_124_3 Int) (v_v_1501_3 Int) (v_b_126_3 Int) (v_b_125_3 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p1 3)) (.cse11 (+ v_b_126_3 1)) (.cse12 (+ c_ULTIMATE.start_main_p2 1)) (.cse10 (+ v_b_124_3 1)) (.cse9 (+ c_ULTIMATE.start_main_p2 2)) (.cse13 (+ c_ULTIMATE.start_main_p1 1))) (and (<= .cse8 v_b_126_3) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_127_3) (or (= (select |c_#memory_int| v_idx_277) v_v_1507_3) (<= v_b_126_3 v_idx_277) (< v_idx_277 v_b_125_3)) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_127_3) (<= v_v_1504_3 0) (or (= 0 (select |c_#memory_int| v_idx_276)) (< v_idx_276 v_b_124_3) (<= v_b_125_3 v_idx_276)) (<= v_b_125_3 v_b_126_3) (or (< v_idx_279 v_b_127_3) (= (select |c_#memory_int| v_idx_279) v_v_1509_3)) (or (<= c_ULTIMATE.start_main_p1 v_idx_271) (= (select |c_#memory_int| v_idx_271) v_v_1501_3)) (<= .cse9 v_b_126_3) (<= .cse10 v_b_126_3) (<= (+ v_b_125_3 1) v_b_127_3) (<= .cse10 v_b_125_3) (<= .cse11 v_b_127_3) (<= (* 2 v_v_1504_3) 0) (or (<= v_b_127_3 v_idx_278) (= 0 (select |c_#memory_int| v_idx_278)) (< v_idx_278 v_b_126_3)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_124_3) (or (= (select |c_#memory_int| v_idx_275) v_v_1505_3) (< v_idx_275 .cse12) (<= v_b_124_3 v_idx_275)) (<= .cse8 v_b_125_3) (<= v_b_127_3 .cse11) (<= (+ v_b_124_3 2) v_b_127_3) (or (< v_idx_274 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_274) v_v_1504_3) (<= .cse12 v_idx_274)) (<= .cse13 c_ULTIMATE.start_main_p2) (<= .cse12 v_b_124_3) (<= v_b_125_3 .cse10) (or (= (select |c_#memory_int| v_idx_272) 0) (<= .cse13 v_idx_272) (< v_idx_272 c_ULTIMATE.start_main_p1)) (<= .cse9 v_b_125_3) (or (< v_idx_273 .cse13) (<= c_ULTIMATE.start_main_p2 v_idx_273) (= (select |c_#memory_int| v_idx_273) v_v_1503_3))))))) is different from false [2019-01-08 14:35:08,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:35:08,402 INFO L93 Difference]: Finished difference Result 14 states and 29 transitions. [2019-01-08 14:35:08,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-08 14:35:08,403 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-08 14:35:08,403 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:35:08,403 INFO L225 Difference]: With dead ends: 14 [2019-01-08 14:35:08,404 INFO L226 Difference]: Without dead ends: 13 [2019-01-08 14:35:08,404 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.8s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:35:08,404 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2019-01-08 14:35:08,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 12. [2019-01-08 14:35:08,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2019-01-08 14:35:08,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 23 transitions. [2019-01-08 14:35:08,411 INFO L78 Accepts]: Start accepts. Automaton has 12 states and 23 transitions. Word has length 3 [2019-01-08 14:35:08,412 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:35:08,412 INFO L480 AbstractCegarLoop]: Abstraction has 12 states and 23 transitions. [2019-01-08 14:35:08,412 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:35:08,412 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 23 transitions. [2019-01-08 14:35:08,412 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:35:08,412 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:35:08,413 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:35:08,413 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:35:08,413 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:35:08,413 INFO L82 PathProgramCache]: Analyzing trace with hash 30244, now seen corresponding path program 1 times [2019-01-08 14:35:08,413 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:35:08,414 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:08,414 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:35:08,414 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:08,414 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:35:08,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:35:08,477 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:35:08,477 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:35:08,477 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:35:08,478 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:35:08,478 INFO L207 CegarAbsIntRunner]: [0], [14], [19] [2019-01-08 14:35:08,479 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:35:08,479 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:35:13,466 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:35:13,467 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:35:13,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:35:13,467 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:35:13,741 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 68.75% of their original sizes. [2019-01-08 14:35:13,742 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:35:16,214 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_368 Int) (v_idx_369 Int) (v_idx_367 Int) (v_idx_371 Int) (v_idx_372 Int) (v_idx_370 Int) (v_idx_375 Int) (v_idx_373 Int) (v_idx_374 Int)) (exists ((v_v_1149_4 Int) (v_v_1146_4 Int) (v_v_1148_4 Int) (v_b_135_4 Int) (v_v_1152_4 Int) (v_b_134_4 Int) (v_v_1144_4 Int) (v_b_139_4 Int) (v_v_1150_4 Int) (v_b_138_4 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_138_4 1)) (.cse4 (+ v_b_134_4 1)) (.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2))) (and (or (<= c_ULTIMATE.start_main_p3 v_idx_371) (< v_idx_371 v_b_135_4) (= (select |c_#memory_int| v_idx_371) v_v_1148_4)) (<= (+ c_ULTIMATE.start_main_p3 2) v_b_139_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_138_4) (or (= (select |c_#memory_int| v_idx_372) v_v_1149_4) (< v_idx_372 c_ULTIMATE.start_main_p3) (<= .cse0 v_idx_372)) (<= v_b_135_4 c_ULTIMATE.start_main_p3) (<= .cse1 v_b_139_4) (or (<= v_b_139_4 v_idx_374) (= 0 (select |c_#memory_int| v_idx_374)) (< v_idx_374 v_b_138_4)) (<= (+ v_b_134_4 3) v_b_139_4) (<= 0 v_v_1149_4) (<= .cse2 v_b_134_4) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_4) (or (= (select |c_#memory_int| v_idx_373) v_v_1150_4) (< v_idx_373 .cse0) (<= v_b_138_4 v_idx_373)) (<= .cse3 c_ULTIMATE.start_main_p3) (<= .cse4 v_b_135_4) (<= v_b_135_4 .cse4) (or (<= v_b_135_4 v_idx_370) (< v_idx_370 v_b_134_4) (= 0 (select |c_#memory_int| v_idx_370))) (or (= (select |c_#memory_int| v_idx_369) v_v_1146_4) (< v_idx_369 .cse2) (<= v_b_134_4 v_idx_369)) (or (= 0 (select |c_#memory_int| v_idx_368)) (<= .cse2 v_idx_368) (< v_idx_368 c_ULTIMATE.start_main_p1)) (<= v_b_139_4 .cse1) (<= (+ v_b_135_4 2) v_b_139_4) (<= 0 (* 2 v_v_1149_4)) (<= (+ v_b_134_4 2) v_b_138_4) (<= .cse4 c_ULTIMATE.start_main_p3) (<= (+ v_b_135_4 1) v_b_138_4) (or (= (select |c_#memory_int| v_idx_375) v_v_1152_4) (< v_idx_375 v_b_139_4)) (or (<= c_ULTIMATE.start_main_p1 v_idx_367) (= (select |c_#memory_int| v_idx_367) v_v_1144_4)) (<= .cse0 v_b_138_4) (<= .cse3 v_b_135_4))))) is different from false [2019-01-08 14:35:18,813 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_379 Int) (v_idx_377 Int) (v_idx_378 Int) (v_idx_382 Int) (v_idx_383 Int) (v_idx_380 Int) (v_idx_381 Int) (v_idx_376 Int) (v_idx_384 Int)) (exists ((v_v_1149_4 Int) (v_v_1146_4 Int) (v_v_1148_4 Int) (v_b_135_4 Int) (v_v_1152_4 Int) (v_b_136_4 Int) (v_b_134_4 Int) (v_v_1144_4 Int) (v_b_139_4 Int) (v_b_137_4 Int) (v_v_1150_4 Int) (v_b_138_4 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse4 (+ v_b_134_4 1)) (.cse3 (+ v_b_138_4 1)) (.cse2 (+ v_b_134_4 2)) (.cse6 (+ v_b_136_4 1)) (.cse7 (+ v_b_135_4 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 2))) (and (or (<= v_b_134_4 v_idx_378) (< v_idx_378 .cse0) (= (select |c_#memory_int| v_idx_378) v_v_1146_4)) (or (<= .cse0 v_idx_377) (< v_idx_377 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_377))) (<= (+ v_b_137_4 1) v_b_139_4) (<= .cse1 v_b_138_4) (<= .cse2 v_b_137_4) (or (< v_idx_379 v_b_134_4) (<= v_b_135_4 v_idx_379) (= 0 (select |c_#memory_int| v_idx_379))) (<= .cse1 v_b_137_4) (or (< v_idx_380 v_b_135_4) (= (select |c_#memory_int| v_idx_380) v_v_1148_4) (<= v_b_136_4 v_idx_380)) (or (= 0 (select |c_#memory_int| v_idx_383)) (< v_idx_383 v_b_138_4) (<= v_b_139_4 v_idx_383)) (<= .cse3 v_b_139_4) (<= (+ v_b_134_4 3) v_b_139_4) (<= 0 v_v_1149_4) (or (= (select |c_#memory_int| v_idx_384) v_v_1152_4) (< v_idx_384 v_b_139_4)) (<= .cse0 v_b_134_4) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_4) (<= v_b_135_4 v_b_136_4) (or (= (select |c_#memory_int| v_idx_381) v_v_1149_4) (< v_idx_381 v_b_136_4) (<= v_b_137_4 v_idx_381)) (<= .cse4 v_b_135_4) (<= v_b_135_4 .cse4) (<= .cse4 v_b_136_4) (<= .cse5 v_b_136_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_376) (= (select |c_#memory_int| v_idx_376) v_v_1144_4)) (<= v_b_137_4 .cse6) (<= .cse6 v_b_137_4) (<= v_b_139_4 .cse3) (<= (+ v_b_135_4 2) v_b_139_4) (<= 0 (* 2 v_v_1149_4)) (<= (+ v_b_136_4 2) v_b_139_4) (<= v_b_137_4 v_b_138_4) (<= .cse7 v_b_137_4) (<= .cse2 v_b_138_4) (<= .cse6 v_b_138_4) (<= .cse7 v_b_138_4) (or (= (select |c_#memory_int| v_idx_382) v_v_1150_4) (<= v_b_138_4 v_idx_382) (< v_idx_382 v_b_137_4)) (<= .cse5 v_b_135_4))))) is different from false [2019-01-08 14:35:18,940 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:35:18,940 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:35:18,940 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:35:18,940 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:35:18,940 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:35:18,940 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:35:18,941 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:35:18,941 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-08 14:35:18,941 INFO L87 Difference]: Start difference. First operand 12 states and 23 transitions. Second operand 4 states. [2019-01-08 14:35:21,518 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_379 Int) (v_idx_377 Int) (v_idx_378 Int) (v_idx_382 Int) (v_idx_383 Int) (v_idx_380 Int) (v_idx_381 Int) (v_idx_376 Int) (v_idx_384 Int)) (exists ((v_v_1149_4 Int) (v_v_1146_4 Int) (v_v_1148_4 Int) (v_b_135_4 Int) (v_v_1152_4 Int) (v_b_136_4 Int) (v_b_134_4 Int) (v_v_1144_4 Int) (v_b_139_4 Int) (v_b_137_4 Int) (v_v_1150_4 Int) (v_b_138_4 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse4 (+ v_b_134_4 1)) (.cse3 (+ v_b_138_4 1)) (.cse2 (+ v_b_134_4 2)) (.cse6 (+ v_b_136_4 1)) (.cse7 (+ v_b_135_4 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 2))) (and (or (<= v_b_134_4 v_idx_378) (< v_idx_378 .cse0) (= (select |c_#memory_int| v_idx_378) v_v_1146_4)) (or (<= .cse0 v_idx_377) (< v_idx_377 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_377))) (<= (+ v_b_137_4 1) v_b_139_4) (<= .cse1 v_b_138_4) (<= .cse2 v_b_137_4) (or (< v_idx_379 v_b_134_4) (<= v_b_135_4 v_idx_379) (= 0 (select |c_#memory_int| v_idx_379))) (<= .cse1 v_b_137_4) (or (< v_idx_380 v_b_135_4) (= (select |c_#memory_int| v_idx_380) v_v_1148_4) (<= v_b_136_4 v_idx_380)) (or (= 0 (select |c_#memory_int| v_idx_383)) (< v_idx_383 v_b_138_4) (<= v_b_139_4 v_idx_383)) (<= .cse3 v_b_139_4) (<= (+ v_b_134_4 3) v_b_139_4) (<= 0 v_v_1149_4) (or (= (select |c_#memory_int| v_idx_384) v_v_1152_4) (< v_idx_384 v_b_139_4)) (<= .cse0 v_b_134_4) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_4) (<= v_b_135_4 v_b_136_4) (or (= (select |c_#memory_int| v_idx_381) v_v_1149_4) (< v_idx_381 v_b_136_4) (<= v_b_137_4 v_idx_381)) (<= .cse4 v_b_135_4) (<= v_b_135_4 .cse4) (<= .cse4 v_b_136_4) (<= .cse5 v_b_136_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_376) (= (select |c_#memory_int| v_idx_376) v_v_1144_4)) (<= v_b_137_4 .cse6) (<= .cse6 v_b_137_4) (<= v_b_139_4 .cse3) (<= (+ v_b_135_4 2) v_b_139_4) (<= 0 (* 2 v_v_1149_4)) (<= (+ v_b_136_4 2) v_b_139_4) (<= v_b_137_4 v_b_138_4) (<= .cse7 v_b_137_4) (<= .cse2 v_b_138_4) (<= .cse6 v_b_138_4) (<= .cse7 v_b_138_4) (or (= (select |c_#memory_int| v_idx_382) v_v_1150_4) (<= v_b_138_4 v_idx_382) (< v_idx_382 v_b_137_4)) (<= .cse5 v_b_135_4))))) (forall ((v_idx_368 Int) (v_idx_369 Int) (v_idx_367 Int) (v_idx_371 Int) (v_idx_372 Int) (v_idx_370 Int) (v_idx_375 Int) (v_idx_373 Int) (v_idx_374 Int)) (exists ((v_v_1149_4 Int) (v_v_1146_4 Int) (v_v_1148_4 Int) (v_b_135_4 Int) (v_v_1152_4 Int) (v_b_134_4 Int) (v_v_1144_4 Int) (v_b_139_4 Int) (v_v_1150_4 Int) (v_b_138_4 Int)) (let ((.cse10 (+ c_ULTIMATE.start_main_p1 1)) (.cse9 (+ v_b_138_4 1)) (.cse12 (+ v_b_134_4 1)) (.cse8 (+ c_ULTIMATE.start_main_p3 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 2))) (and (or (<= c_ULTIMATE.start_main_p3 v_idx_371) (< v_idx_371 v_b_135_4) (= (select |c_#memory_int| v_idx_371) v_v_1148_4)) (<= (+ c_ULTIMATE.start_main_p3 2) v_b_139_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_138_4) (or (= (select |c_#memory_int| v_idx_372) v_v_1149_4) (< v_idx_372 c_ULTIMATE.start_main_p3) (<= .cse8 v_idx_372)) (<= v_b_135_4 c_ULTIMATE.start_main_p3) (<= .cse9 v_b_139_4) (or (<= v_b_139_4 v_idx_374) (= 0 (select |c_#memory_int| v_idx_374)) (< v_idx_374 v_b_138_4)) (<= (+ v_b_134_4 3) v_b_139_4) (<= 0 v_v_1149_4) (<= .cse10 v_b_134_4) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_4) (or (= (select |c_#memory_int| v_idx_373) v_v_1150_4) (< v_idx_373 .cse8) (<= v_b_138_4 v_idx_373)) (<= .cse11 c_ULTIMATE.start_main_p3) (<= .cse12 v_b_135_4) (<= v_b_135_4 .cse12) (or (<= v_b_135_4 v_idx_370) (< v_idx_370 v_b_134_4) (= 0 (select |c_#memory_int| v_idx_370))) (or (= (select |c_#memory_int| v_idx_369) v_v_1146_4) (< v_idx_369 .cse10) (<= v_b_134_4 v_idx_369)) (or (= 0 (select |c_#memory_int| v_idx_368)) (<= .cse10 v_idx_368) (< v_idx_368 c_ULTIMATE.start_main_p1)) (<= v_b_139_4 .cse9) (<= (+ v_b_135_4 2) v_b_139_4) (<= 0 (* 2 v_v_1149_4)) (<= (+ v_b_134_4 2) v_b_138_4) (<= .cse12 c_ULTIMATE.start_main_p3) (<= (+ v_b_135_4 1) v_b_138_4) (or (= (select |c_#memory_int| v_idx_375) v_v_1152_4) (< v_idx_375 v_b_139_4)) (or (<= c_ULTIMATE.start_main_p1 v_idx_367) (= (select |c_#memory_int| v_idx_367) v_v_1144_4)) (<= .cse8 v_b_138_4) (<= .cse11 v_b_135_4)))))) is different from false [2019-01-08 14:35:34,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:35:34,164 INFO L93 Difference]: Finished difference Result 14 states and 29 transitions. [2019-01-08 14:35:34,164 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-08 14:35:34,165 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-08 14:35:34,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:35:34,165 INFO L225 Difference]: With dead ends: 14 [2019-01-08 14:35:34,165 INFO L226 Difference]: Without dead ends: 13 [2019-01-08 14:35:34,166 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.8s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:35:34,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2019-01-08 14:35:34,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 12. [2019-01-08 14:35:34,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2019-01-08 14:35:34,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 23 transitions. [2019-01-08 14:35:34,174 INFO L78 Accepts]: Start accepts. Automaton has 12 states and 23 transitions. Word has length 3 [2019-01-08 14:35:34,174 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:35:34,174 INFO L480 AbstractCegarLoop]: Abstraction has 12 states and 23 transitions. [2019-01-08 14:35:34,174 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:35:34,174 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 23 transitions. [2019-01-08 14:35:34,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-08 14:35:34,175 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:35:34,175 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1] [2019-01-08 14:35:34,175 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:35:34,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:35:34,176 INFO L82 PathProgramCache]: Analyzing trace with hash 939412, now seen corresponding path program 2 times [2019-01-08 14:35:34,176 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:35:34,177 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:34,177 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:35:34,177 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:34,177 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:35:34,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:35:34,239 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-08 14:35:34,239 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:35:34,240 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:35:34,240 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-08 14:35:34,241 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-08 14:35:34,241 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:35:34,241 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-08 14:35:34,252 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-08 14:35:34,252 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-08 14:35:34,263 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-08 14:35:34,263 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-08 14:35:34,270 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-08 14:35:34,324 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 18 [2019-01-08 14:35:34,354 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:34,355 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 24 [2019-01-08 14:35:34,374 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:34,380 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:34,381 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 34 [2019-01-08 14:35:34,388 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:34,390 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:34,392 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:34,393 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 45 [2019-01-08 14:35:34,395 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2019-01-08 14:35:34,429 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:35:34,520 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:35:34,655 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-08 14:35:34,762 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:35:34,763 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:25, output treesize:30 [2019-01-08 14:35:34,908 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:34,921 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:34,923 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:34,926 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:34,928 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:34,930 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:34,932 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:34,933 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 45 [2019-01-08 14:35:34,934 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:35:35,030 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-08 14:35:35,031 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:40, output treesize:30 [2019-01-08 14:35:35,226 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:35,254 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:35,275 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:35,290 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:35,298 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:35,300 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:35,302 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:35,304 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:35,305 INFO L701 Elim1Store]: detected not equals via solver [2019-01-08 14:35:35,305 INFO L303 Elim1Store]: Index analysis took 103 ms [2019-01-08 14:35:35,306 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 9 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 57 [2019-01-08 14:35:35,307 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-08 14:35:35,361 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2019-01-08 14:35:35,362 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 4 variables, input treesize:42, output treesize:30 [2019-01-08 14:35:35,379 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:35:35,380 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-08 14:35:35,417 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:35:35,437 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-08 14:35:35,437 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 3, 3] total 8 [2019-01-08 14:35:35,437 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-08 14:35:35,437 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-01-08 14:35:35,438 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-01-08 14:35:35,438 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=53, Unknown=0, NotChecked=0, Total=90 [2019-01-08 14:35:35,438 INFO L87 Difference]: Start difference. First operand 12 states and 23 transitions. Second operand 7 states. [2019-01-08 14:35:35,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:35:35,872 INFO L93 Difference]: Finished difference Result 37 states and 58 transitions. [2019-01-08 14:35:35,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-08 14:35:35,872 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 4 [2019-01-08 14:35:35,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:35:35,873 INFO L225 Difference]: With dead ends: 37 [2019-01-08 14:35:35,873 INFO L226 Difference]: Without dead ends: 33 [2019-01-08 14:35:35,874 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-01-08 14:35:35,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states. [2019-01-08 14:35:35,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 16. [2019-01-08 14:35:35,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2019-01-08 14:35:35,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 36 transitions. [2019-01-08 14:35:35,886 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 36 transitions. Word has length 4 [2019-01-08 14:35:35,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:35:35,886 INFO L480 AbstractCegarLoop]: Abstraction has 16 states and 36 transitions. [2019-01-08 14:35:35,886 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-01-08 14:35:35,886 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 36 transitions. [2019-01-08 14:35:35,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-08 14:35:35,887 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:35:35,887 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-08 14:35:35,887 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:35:35,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:35:35,888 INFO L82 PathProgramCache]: Analyzing trace with hash 939538, now seen corresponding path program 1 times [2019-01-08 14:35:35,888 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:35:35,889 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:35,889 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-08 14:35:35,889 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:35,889 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:35:35,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:35:35,999 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:35:35,999 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:35:35,999 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:35:36,000 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-08 14:35:36,000 INFO L207 CegarAbsIntRunner]: [0], [16], [20], [21] [2019-01-08 14:35:36,001 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:35:36,001 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:35:43,031 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:35:43,031 INFO L272 AbstractInterpreter]: Visited 4 different actions 16 times. Merged at 2 different actions 8 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:35:43,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:35:43,031 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:35:43,400 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 62.5% of their original sizes. [2019-01-08 14:35:43,400 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:35:45,786 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_510 Int) (v_idx_504 Int) (v_idx_505 Int) (v_idx_502 Int) (v_idx_503 Int) (v_idx_508 Int) (v_idx_509 Int) (v_idx_506 Int) (v_idx_507 Int)) (exists ((v_b_142_5 Int) (v_v_1504_5 Int) (v_v_1496_5 Int) (v_v_1502_5 Int) (v_v_1503_5 Int) (v_b_143_5 Int) (v_v_1500_5 Int) (v_v_1498_5 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p4 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ v_b_142_5 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 3)) (.cse4 (+ c_ULTIMATE.start_main_p2 2))) (and (<= .cse0 v_b_143_5) (or (< v_idx_504 .cse1) (= (select |c_#memory_int| v_idx_504) v_v_1498_5) (<= c_ULTIMATE.start_main_p2 v_idx_504)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_142_5) (<= .cse2 v_b_142_5) (<= v_v_1503_5 0) (or (= (select |c_#memory_int| v_idx_509) v_v_1503_5) (< v_idx_509 c_ULTIMATE.start_main_p4) (<= .cse3 v_idx_509)) (<= v_b_143_5 c_ULTIMATE.start_main_p4) (or (= (select |c_#memory_int| v_idx_502) v_v_1496_5) (<= c_ULTIMATE.start_main_p1 v_idx_502)) (or (< v_idx_510 .cse3) (= (select |c_#memory_int| v_idx_510) v_v_1504_5)) (<= .cse4 c_ULTIMATE.start_main_p4) (or (<= .cse1 v_idx_503) (= 0 (select |c_#memory_int| v_idx_503)) (< v_idx_503 c_ULTIMATE.start_main_p1)) (or (< v_idx_506 .cse2) (<= v_b_142_5 v_idx_506) (= (select |c_#memory_int| v_idx_506) v_v_1500_5)) (<= (* 2 v_v_1503_5) 0) (or (<= .cse2 v_idx_505) (= 0 (select |c_#memory_int| v_idx_505)) (< v_idx_505 c_ULTIMATE.start_main_p2)) (<= .cse5 v_b_143_5) (<= .cse0 c_ULTIMATE.start_main_p4) (or (< v_idx_508 v_b_143_5) (<= c_ULTIMATE.start_main_p4 v_idx_508) (= (select |c_#memory_int| v_idx_508) v_v_1502_5)) (or (< v_idx_507 v_b_142_5) (= 0 (select |c_#memory_int| v_idx_507)) (<= v_b_143_5 v_idx_507)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= v_b_143_5 .cse0) (<= .cse5 c_ULTIMATE.start_main_p4) (<= .cse4 v_b_143_5))))) is different from false [2019-01-08 14:35:48,194 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_511 Int) (v_idx_512 Int) (v_idx_515 Int) (v_idx_516 Int) (v_idx_513 Int) (v_idx_514 Int) (v_idx_519 Int) (v_idx_517 Int) (v_idx_518 Int)) (exists ((v_b_142_5 Int) (v_v_1504_5 Int) (v_b_145_5 Int) (v_v_1502_5 Int) (v_v_1496_5 Int) (v_v_1503_5 Int) (v_b_143_5 Int) (v_v_1500_5 Int) (v_b_144_5 Int) (v_v_1498_5 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 3)) (.cse1 (+ c_ULTIMATE.start_main_p2 2)) (.cse2 (+ v_b_144_5 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse4 (+ v_b_142_5 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_514 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_514)) (<= .cse0 v_idx_514)) (or (< v_idx_518 v_b_144_5) (= (select |c_#memory_int| v_idx_518) v_v_1503_5) (<= v_b_145_5 v_idx_518)) (<= .cse1 v_b_144_5) (<= (* 2 v_v_1503_5) 0) (<= v_b_145_5 .cse2) (or (< v_idx_519 v_b_145_5) (= (select |c_#memory_int| v_idx_519) v_v_1504_5)) (<= (+ v_b_142_5 2) v_b_145_5) (<= .cse3 v_b_144_5) (<= .cse3 v_b_143_5) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_145_5) (<= v_b_143_5 .cse4) (<= v_b_143_5 v_b_144_5) (<= .cse1 v_b_143_5) (<= .cse4 v_b_143_5) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_142_5) (<= .cse0 v_b_142_5) (<= v_v_1503_5 0) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_145_5) (<= .cse2 v_b_145_5) (or (< v_idx_517 v_b_143_5) (= (select |c_#memory_int| v_idx_517) v_v_1502_5) (<= v_b_144_5 v_idx_517)) (or (= (select |c_#memory_int| v_idx_515) v_v_1500_5) (< v_idx_515 .cse0) (<= v_b_142_5 v_idx_515)) (or (= (select |c_#memory_int| v_idx_513) v_v_1498_5) (<= c_ULTIMATE.start_main_p2 v_idx_513) (< v_idx_513 .cse5)) (<= .cse4 v_b_144_5) (or (<= c_ULTIMATE.start_main_p1 v_idx_511) (= (select |c_#memory_int| v_idx_511) v_v_1496_5)) (or (<= .cse5 v_idx_512) (< v_idx_512 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_512) 0)) (or (< v_idx_516 v_b_142_5) (= (select |c_#memory_int| v_idx_516) 0) (<= v_b_143_5 v_idx_516)) (<= .cse5 c_ULTIMATE.start_main_p2) (<= (+ v_b_143_5 1) v_b_145_5))))) is different from false [2019-01-08 14:35:50,757 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_522 Int) (v_idx_523 Int) (v_idx_520 Int) (v_idx_521 Int) (v_idx_526 Int) (v_idx_527 Int) (v_idx_524 Int) (v_idx_525 Int) (v_idx_528 Int)) (exists ((v_b_160_5 Int) (v_b_142_5 Int) (v_v_1504_5 Int) (v_v_1502_5 Int) (v_b_145_5 Int) (v_v_1496_5 Int) (v_v_1503_5 Int) (v_v_1500_5 Int) (v_b_143_5 Int) (v_v_1498_5 Int) (v_b_144_5 Int) (v_b_139_5 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p2 2)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_160_5 1)) (.cse4 (+ v_b_144_5 1)) (.cse6 (+ v_b_139_5 2)) (.cse3 (+ v_b_160_5 3)) (.cse5 (+ v_b_142_5 1))) (and (<= .cse0 c_ULTIMATE.start_main_p2) (<= .cse0 v_b_139_5) (<= (+ v_b_160_5 2) v_b_142_5) (or (<= v_b_142_5 v_idx_524) (= (select |c_#memory_int| v_idx_524) v_v_1500_5) (< v_idx_524 .cse1)) (or (< v_idx_522 v_b_139_5) (<= c_ULTIMATE.start_main_p2 v_idx_522) (= (select |c_#memory_int| v_idx_522) v_v_1498_5)) (or (<= v_b_144_5 v_idx_526) (= (select |c_#memory_int| v_idx_526) v_v_1502_5) (< v_idx_526 v_b_143_5)) (<= .cse2 v_b_144_5) (<= (+ v_b_160_5 4) v_b_145_5) (<= (* 2 v_v_1503_5) 0) (<= .cse3 v_b_144_5) (<= v_b_145_5 .cse4) (<= (+ v_b_142_5 2) v_b_145_5) (or (< v_idx_521 v_b_160_5) (<= v_b_139_5 v_idx_521) (= (select |c_#memory_int| v_idx_521) 0)) (or (<= v_b_143_5 v_idx_525) (= (select |c_#memory_int| v_idx_525) 0) (< v_idx_525 v_b_142_5)) (or (<= .cse1 v_idx_523) (< v_idx_523 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_523) 0)) (<= v_b_143_5 .cse5) (<= v_b_143_5 v_b_144_5) (<= .cse2 v_b_143_5) (<= .cse5 v_b_143_5) (<= (+ v_b_139_5 3) v_b_145_5) (<= .cse1 v_b_142_5) (<= v_v_1503_5 0) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_145_5) (or (= (select |c_#memory_int| v_idx_520) v_v_1496_5) (<= v_b_160_5 v_idx_520)) (<= .cse6 v_b_144_5) (<= v_b_139_5 .cse0) (<= .cse4 v_b_145_5) (<= .cse6 v_b_143_5) (<= v_b_139_5 c_ULTIMATE.start_main_p2) (<= .cse3 v_b_143_5) (or (< v_idx_528 v_b_145_5) (= (select |c_#memory_int| v_idx_528) v_v_1504_5)) (or (<= v_b_145_5 v_idx_527) (< v_idx_527 v_b_144_5) (= (select |c_#memory_int| v_idx_527) v_v_1503_5)) (<= .cse5 v_b_144_5) (<= (+ v_b_139_5 1) v_b_142_5) (<= (+ v_b_143_5 1) v_b_145_5))))) is different from false [2019-01-08 14:35:50,871 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-08 14:35:50,871 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:35:50,871 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:35:50,871 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [2] total 5 [2019-01-08 14:35:50,872 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:35:50,872 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-08 14:35:50,872 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-08 14:35:50,872 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:35:50,872 INFO L87 Difference]: Start difference. First operand 16 states and 36 transitions. Second operand 5 states. [2019-01-08 14:35:53,604 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_522 Int) (v_idx_523 Int) (v_idx_520 Int) (v_idx_521 Int) (v_idx_526 Int) (v_idx_527 Int) (v_idx_524 Int) (v_idx_525 Int) (v_idx_528 Int)) (exists ((v_b_160_5 Int) (v_b_142_5 Int) (v_v_1504_5 Int) (v_v_1502_5 Int) (v_b_145_5 Int) (v_v_1496_5 Int) (v_v_1503_5 Int) (v_v_1500_5 Int) (v_b_143_5 Int) (v_v_1498_5 Int) (v_b_144_5 Int) (v_b_139_5 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p2 2)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_160_5 1)) (.cse4 (+ v_b_144_5 1)) (.cse6 (+ v_b_139_5 2)) (.cse3 (+ v_b_160_5 3)) (.cse5 (+ v_b_142_5 1))) (and (<= .cse0 c_ULTIMATE.start_main_p2) (<= .cse0 v_b_139_5) (<= (+ v_b_160_5 2) v_b_142_5) (or (<= v_b_142_5 v_idx_524) (= (select |c_#memory_int| v_idx_524) v_v_1500_5) (< v_idx_524 .cse1)) (or (< v_idx_522 v_b_139_5) (<= c_ULTIMATE.start_main_p2 v_idx_522) (= (select |c_#memory_int| v_idx_522) v_v_1498_5)) (or (<= v_b_144_5 v_idx_526) (= (select |c_#memory_int| v_idx_526) v_v_1502_5) (< v_idx_526 v_b_143_5)) (<= .cse2 v_b_144_5) (<= (+ v_b_160_5 4) v_b_145_5) (<= (* 2 v_v_1503_5) 0) (<= .cse3 v_b_144_5) (<= v_b_145_5 .cse4) (<= (+ v_b_142_5 2) v_b_145_5) (or (< v_idx_521 v_b_160_5) (<= v_b_139_5 v_idx_521) (= (select |c_#memory_int| v_idx_521) 0)) (or (<= v_b_143_5 v_idx_525) (= (select |c_#memory_int| v_idx_525) 0) (< v_idx_525 v_b_142_5)) (or (<= .cse1 v_idx_523) (< v_idx_523 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_523) 0)) (<= v_b_143_5 .cse5) (<= v_b_143_5 v_b_144_5) (<= .cse2 v_b_143_5) (<= .cse5 v_b_143_5) (<= (+ v_b_139_5 3) v_b_145_5) (<= .cse1 v_b_142_5) (<= v_v_1503_5 0) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_145_5) (or (= (select |c_#memory_int| v_idx_520) v_v_1496_5) (<= v_b_160_5 v_idx_520)) (<= .cse6 v_b_144_5) (<= v_b_139_5 .cse0) (<= .cse4 v_b_145_5) (<= .cse6 v_b_143_5) (<= v_b_139_5 c_ULTIMATE.start_main_p2) (<= .cse3 v_b_143_5) (or (< v_idx_528 v_b_145_5) (= (select |c_#memory_int| v_idx_528) v_v_1504_5)) (or (<= v_b_145_5 v_idx_527) (< v_idx_527 v_b_144_5) (= (select |c_#memory_int| v_idx_527) v_v_1503_5)) (<= .cse5 v_b_144_5) (<= (+ v_b_139_5 1) v_b_142_5) (<= (+ v_b_143_5 1) v_b_145_5))))) (forall ((v_idx_510 Int) (v_idx_504 Int) (v_idx_505 Int) (v_idx_502 Int) (v_idx_503 Int) (v_idx_508 Int) (v_idx_509 Int) (v_idx_506 Int) (v_idx_507 Int)) (exists ((v_b_142_5 Int) (v_v_1504_5 Int) (v_v_1496_5 Int) (v_v_1502_5 Int) (v_v_1503_5 Int) (v_b_143_5 Int) (v_v_1500_5 Int) (v_v_1498_5 Int)) (let ((.cse10 (+ c_ULTIMATE.start_main_p4 1)) (.cse9 (+ c_ULTIMATE.start_main_p2 1)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ v_b_142_5 1)) (.cse12 (+ c_ULTIMATE.start_main_p1 3)) (.cse11 (+ c_ULTIMATE.start_main_p2 2))) (and (<= .cse7 v_b_143_5) (or (< v_idx_504 .cse8) (= (select |c_#memory_int| v_idx_504) v_v_1498_5) (<= c_ULTIMATE.start_main_p2 v_idx_504)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_142_5) (<= .cse9 v_b_142_5) (<= v_v_1503_5 0) (or (= (select |c_#memory_int| v_idx_509) v_v_1503_5) (< v_idx_509 c_ULTIMATE.start_main_p4) (<= .cse10 v_idx_509)) (<= v_b_143_5 c_ULTIMATE.start_main_p4) (or (= (select |c_#memory_int| v_idx_502) v_v_1496_5) (<= c_ULTIMATE.start_main_p1 v_idx_502)) (or (< v_idx_510 .cse10) (= (select |c_#memory_int| v_idx_510) v_v_1504_5)) (<= .cse11 c_ULTIMATE.start_main_p4) (or (<= .cse8 v_idx_503) (= 0 (select |c_#memory_int| v_idx_503)) (< v_idx_503 c_ULTIMATE.start_main_p1)) (or (< v_idx_506 .cse9) (<= v_b_142_5 v_idx_506) (= (select |c_#memory_int| v_idx_506) v_v_1500_5)) (<= (* 2 v_v_1503_5) 0) (or (<= .cse9 v_idx_505) (= 0 (select |c_#memory_int| v_idx_505)) (< v_idx_505 c_ULTIMATE.start_main_p2)) (<= .cse12 v_b_143_5) (<= .cse7 c_ULTIMATE.start_main_p4) (or (< v_idx_508 v_b_143_5) (<= c_ULTIMATE.start_main_p4 v_idx_508) (= (select |c_#memory_int| v_idx_508) v_v_1502_5)) (or (< v_idx_507 v_b_142_5) (= 0 (select |c_#memory_int| v_idx_507)) (<= v_b_143_5 v_idx_507)) (<= .cse8 c_ULTIMATE.start_main_p2) (<= v_b_143_5 .cse7) (<= .cse12 c_ULTIMATE.start_main_p4) (<= .cse11 v_b_143_5))))) (forall ((v_idx_511 Int) (v_idx_512 Int) (v_idx_515 Int) (v_idx_516 Int) (v_idx_513 Int) (v_idx_514 Int) (v_idx_519 Int) (v_idx_517 Int) (v_idx_518 Int)) (exists ((v_b_142_5 Int) (v_v_1504_5 Int) (v_b_145_5 Int) (v_v_1502_5 Int) (v_v_1496_5 Int) (v_v_1503_5 Int) (v_b_143_5 Int) (v_v_1500_5 Int) (v_b_144_5 Int) (v_v_1498_5 Int)) (let ((.cse16 (+ c_ULTIMATE.start_main_p1 3)) (.cse14 (+ c_ULTIMATE.start_main_p2 2)) (.cse15 (+ v_b_144_5 1)) (.cse13 (+ c_ULTIMATE.start_main_p2 1)) (.cse17 (+ v_b_142_5 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_514 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_514)) (<= .cse13 v_idx_514)) (or (< v_idx_518 v_b_144_5) (= (select |c_#memory_int| v_idx_518) v_v_1503_5) (<= v_b_145_5 v_idx_518)) (<= .cse14 v_b_144_5) (<= (* 2 v_v_1503_5) 0) (<= v_b_145_5 .cse15) (or (< v_idx_519 v_b_145_5) (= (select |c_#memory_int| v_idx_519) v_v_1504_5)) (<= (+ v_b_142_5 2) v_b_145_5) (<= .cse16 v_b_144_5) (<= .cse16 v_b_143_5) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_145_5) (<= v_b_143_5 .cse17) (<= v_b_143_5 v_b_144_5) (<= .cse14 v_b_143_5) (<= .cse17 v_b_143_5) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_142_5) (<= .cse13 v_b_142_5) (<= v_v_1503_5 0) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_145_5) (<= .cse15 v_b_145_5) (or (< v_idx_517 v_b_143_5) (= (select |c_#memory_int| v_idx_517) v_v_1502_5) (<= v_b_144_5 v_idx_517)) (or (= (select |c_#memory_int| v_idx_515) v_v_1500_5) (< v_idx_515 .cse13) (<= v_b_142_5 v_idx_515)) (or (= (select |c_#memory_int| v_idx_513) v_v_1498_5) (<= c_ULTIMATE.start_main_p2 v_idx_513) (< v_idx_513 .cse18)) (<= .cse17 v_b_144_5) (or (<= c_ULTIMATE.start_main_p1 v_idx_511) (= (select |c_#memory_int| v_idx_511) v_v_1496_5)) (or (<= .cse18 v_idx_512) (< v_idx_512 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_512) 0)) (or (< v_idx_516 v_b_142_5) (= (select |c_#memory_int| v_idx_516) 0) (<= v_b_143_5 v_idx_516)) (<= .cse18 c_ULTIMATE.start_main_p2) (<= (+ v_b_143_5 1) v_b_145_5)))))) is different from false [2019-01-08 14:36:21,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:36:21,116 INFO L93 Difference]: Finished difference Result 17 states and 36 transitions. [2019-01-08 14:36:21,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-08 14:36:21,116 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-08 14:36:21,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:36:21,117 INFO L225 Difference]: With dead ends: 17 [2019-01-08 14:36:21,117 INFO L226 Difference]: Without dead ends: 16 [2019-01-08 14:36:21,117 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 10.0s TimeCoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-08 14:36:21,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-08 14:36:21,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2019-01-08 14:36:21,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-08 14:36:21,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 34 transitions. [2019-01-08 14:36:21,130 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 34 transitions. Word has length 4 [2019-01-08 14:36:21,130 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:36:21,130 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 34 transitions. [2019-01-08 14:36:21,130 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-08 14:36:21,130 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 34 transitions. [2019-01-08 14:36:21,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-08 14:36:21,131 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:36:21,131 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-08 14:36:21,131 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:36:21,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:36:21,132 INFO L82 PathProgramCache]: Analyzing trace with hash 939102, now seen corresponding path program 1 times [2019-01-08 14:36:21,132 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:36:21,132 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:36:21,133 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:36:21,133 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:36:21,133 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:36:21,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:36:21,205 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:36:21,206 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:36:21,206 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:36:21,206 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-08 14:36:21,206 INFO L207 CegarAbsIntRunner]: [0], [6], [16], [19] [2019-01-08 14:36:21,207 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:36:21,207 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:36:36,034 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:36:36,034 INFO L272 AbstractInterpreter]: Visited 4 different actions 31 times. Merged at 2 different actions 9 times. Widened at 2 different actions 5 times. Found 11 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-08 14:36:36,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:36:36,035 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:36:36,439 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 70.83% of their original sizes. [2019-01-08 14:36:36,439 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:36:38,825 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_654 Int) (v_idx_652 Int) (v_idx_653 Int) (v_idx_647 Int) (v_idx_648 Int) (v_idx_646 Int) (v_idx_649 Int) (v_idx_650 Int) (v_idx_651 Int)) (exists ((v_v_4130_1 Int) (v_b_370_1 Int) (v_b_371_1 Int) (v_v_4129_1 Int) (v_v_4128_1 Int) (v_v_4136_1 Int) (v_v_4134_1 Int) (v_b_369_1 Int) (v_v_4135_1 Int) (v_b_368_1 Int) (v_v_4132_1 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse0 (+ v_b_369_1 1)) (.cse5 (+ v_b_368_1 2)) (.cse4 (+ v_b_368_1 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ v_b_370_1 1)) (.cse7 (+ c_ULTIMATE.start_main_p4 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_371_1 c_ULTIMATE.start_main_p4) (<= v_b_369_1 v_b_370_1) (<= 0 v_v_4129_1) (<= .cse0 v_b_371_1) (<= .cse1 v_b_371_1) (<= .cse2 v_b_371_1) (or (< v_idx_648 .cse3) (<= v_b_368_1 v_idx_648) (= (select |c_#memory_int| v_idx_648) v_v_4130_1)) (<= .cse2 c_ULTIMATE.start_main_p4) (or (= (select |c_#memory_int| v_idx_651) 0) (<= v_b_371_1 v_idx_651) (< v_idx_651 v_b_370_1)) (<= .cse4 v_b_369_1) (<= .cse1 c_ULTIMATE.start_main_p4) (<= 0 (* 2 v_v_4129_1)) (or (= (select |c_#memory_int| v_idx_652) v_v_4134_1) (< v_idx_652 v_b_371_1) (<= c_ULTIMATE.start_main_p4 v_idx_652)) (<= .cse4 v_b_370_1) (<= .cse0 c_ULTIMATE.start_main_p4) (<= .cse5 c_ULTIMATE.start_main_p4) (or (= (select |c_#memory_int| v_idx_647) v_v_4129_1) (<= .cse3 v_idx_647) (< v_idx_647 c_ULTIMATE.start_main_p1)) (<= .cse5 v_b_371_1) (or (< v_idx_650 v_b_369_1) (= (select |c_#memory_int| v_idx_650) v_v_4132_1) (<= v_b_370_1 v_idx_650)) (or (= (select |c_#memory_int| v_idx_646) v_v_4128_1) (<= c_ULTIMATE.start_main_p1 v_idx_646)) (<= v_v_4135_1 v_v_4129_1) (<= .cse6 v_b_370_1) (or (<= .cse7 v_idx_653) (< v_idx_653 c_ULTIMATE.start_main_p4) (= (select |c_#memory_int| v_idx_653) v_v_4135_1)) (<= v_b_369_1 .cse4) (<= .cse6 v_b_369_1) (<= v_b_371_1 .cse2) (<= (* 2 v_v_4135_1) 0) (<= v_v_4135_1 0) (or (< v_idx_654 .cse7) (= (select |c_#memory_int| v_idx_654) v_v_4136_1)) (or (< v_idx_649 v_b_368_1) (<= v_b_369_1 v_idx_649) (= (select |c_#memory_int| v_idx_649) 0)) (<= .cse3 v_b_368_1))))) is different from false [2019-01-08 14:36:41,377 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_655 Int) (v_idx_663 Int) (v_idx_658 Int) (v_idx_659 Int) (v_idx_656 Int) (v_idx_657 Int) (v_idx_661 Int) (v_idx_662 Int) (v_idx_660 Int)) (exists ((v_v_4129_1 Int) (v_v_4128_1 Int) (v_v_4136_1 Int) (v_v_4134_1 Int) (v_b_369_1 Int) (v_v_4135_1 Int) (v_v_4132_1 Int) (v_b_368_1 Int) (v_v_4130_1 Int) (v_b_370_1 Int) (v_b_371_1 Int) (v_b_372_1 Int) (v_b_373_1 Int)) (let ((.cse0 (+ v_b_369_1 1)) (.cse6 (+ v_b_372_1 1)) (.cse4 (+ v_b_368_1 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse5 (+ v_b_368_1 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ v_b_370_1 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_369_1 v_b_370_1) (<= 0 v_v_4129_1) (or (= (select |c_#memory_int| v_idx_660) 0) (<= v_b_371_1 v_idx_660) (< v_idx_660 v_b_370_1)) (<= (+ v_b_368_1 3) v_b_373_1) (<= .cse0 v_b_371_1) (or (<= v_b_370_1 v_idx_659) (= (select |c_#memory_int| v_idx_659) v_v_4132_1) (< v_idx_659 v_b_369_1)) (<= .cse1 v_b_371_1) (or (= (select |c_#memory_int| v_idx_656) v_v_4129_1) (<= .cse2 v_idx_656) (< v_idx_656 c_ULTIMATE.start_main_p1)) (<= .cse3 v_b_372_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_373_1) (<= (+ v_b_371_1 1) v_b_373_1) (<= .cse3 v_b_371_1) (<= .cse4 v_b_372_1) (<= .cse5 v_b_369_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_655) (= (select |c_#memory_int| v_idx_655) v_v_4128_1)) (<= (+ v_b_369_1 2) v_b_373_1) (or (< v_idx_662 v_b_372_1) (= (select |c_#memory_int| v_idx_662) v_v_4135_1) (<= v_b_373_1 v_idx_662)) (<= v_b_373_1 .cse6) (<= .cse0 v_b_372_1) (<= 0 (* 2 v_v_4129_1)) (<= .cse5 v_b_370_1) (<= .cse6 v_b_373_1) (or (= (select |c_#memory_int| v_idx_663) v_v_4136_1) (< v_idx_663 v_b_373_1)) (<= .cse4 v_b_371_1) (<= v_v_4135_1 v_v_4129_1) (<= .cse1 v_b_372_1) (<= .cse7 v_b_370_1) (or (<= v_b_372_1 v_idx_661) (= (select |c_#memory_int| v_idx_661) v_v_4134_1) (< v_idx_661 v_b_371_1)) (or (= (select |c_#memory_int| v_idx_657) v_v_4130_1) (<= v_b_368_1 v_idx_657) (< v_idx_657 .cse2)) (<= v_b_369_1 .cse5) (<= .cse7 v_b_369_1) (or (< v_idx_658 v_b_368_1) (= (select |c_#memory_int| v_idx_658) 0) (<= v_b_369_1 v_idx_658)) (<= (+ v_b_370_1 2) v_b_373_1) (<= v_b_371_1 .cse3) (<= (* 2 v_v_4135_1) 0) (<= v_v_4135_1 0) (<= v_b_371_1 v_b_372_1) (<= .cse2 v_b_368_1))))) is different from false [2019-01-08 14:36:43,390 WARN L860 $PredicateComparison]: unable to prove that (forall ((v_idx_655 Int) (v_idx_663 Int) (v_idx_658 Int) (v_idx_659 Int) (v_idx_656 Int) (v_idx_657 Int) (v_idx_661 Int) (v_idx_662 Int) (v_idx_660 Int)) (exists ((v_v_4129_1 Int) (v_v_4128_1 Int) (v_v_4136_1 Int) (v_v_4134_1 Int) (v_b_369_1 Int) (v_v_4135_1 Int) (v_v_4132_1 Int) (v_b_368_1 Int) (v_v_4130_1 Int) (v_b_370_1 Int) (v_b_371_1 Int) (v_b_372_1 Int) (v_b_373_1 Int)) (let ((.cse0 (+ v_b_369_1 1)) (.cse6 (+ v_b_372_1 1)) (.cse4 (+ v_b_368_1 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse5 (+ v_b_368_1 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ v_b_370_1 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_369_1 v_b_370_1) (<= 0 v_v_4129_1) (or (= (select |c_#memory_int| v_idx_660) 0) (<= v_b_371_1 v_idx_660) (< v_idx_660 v_b_370_1)) (<= (+ v_b_368_1 3) v_b_373_1) (<= .cse0 v_b_371_1) (or (<= v_b_370_1 v_idx_659) (= (select |c_#memory_int| v_idx_659) v_v_4132_1) (< v_idx_659 v_b_369_1)) (<= .cse1 v_b_371_1) (or (= (select |c_#memory_int| v_idx_656) v_v_4129_1) (<= .cse2 v_idx_656) (< v_idx_656 c_ULTIMATE.start_main_p1)) (<= .cse3 v_b_372_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_373_1) (<= (+ v_b_371_1 1) v_b_373_1) (<= .cse3 v_b_371_1) (<= .cse4 v_b_372_1) (<= .cse5 v_b_369_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_655) (= (select |c_#memory_int| v_idx_655) v_v_4128_1)) (<= (+ v_b_369_1 2) v_b_373_1) (or (< v_idx_662 v_b_372_1) (= (select |c_#memory_int| v_idx_662) v_v_4135_1) (<= v_b_373_1 v_idx_662)) (<= v_b_373_1 .cse6) (<= .cse0 v_b_372_1) (<= 0 (* 2 v_v_4129_1)) (<= .cse5 v_b_370_1) (<= .cse6 v_b_373_1) (or (= (select |c_#memory_int| v_idx_663) v_v_4136_1) (< v_idx_663 v_b_373_1)) (<= .cse4 v_b_371_1) (<= v_v_4135_1 v_v_4129_1) (<= .cse1 v_b_372_1) (<= .cse7 v_b_370_1) (or (<= v_b_372_1 v_idx_661) (= (select |c_#memory_int| v_idx_661) v_v_4134_1) (< v_idx_661 v_b_371_1)) (or (= (select |c_#memory_int| v_idx_657) v_v_4130_1) (<= v_b_368_1 v_idx_657) (< v_idx_657 .cse2)) (<= v_b_369_1 .cse5) (<= .cse7 v_b_369_1) (or (< v_idx_658 v_b_368_1) (= (select |c_#memory_int| v_idx_658) 0) (<= v_b_369_1 v_idx_658)) (<= (+ v_b_370_1 2) v_b_373_1) (<= v_b_371_1 .cse3) (<= (* 2 v_v_4135_1) 0) (<= v_v_4135_1 0) (<= v_b_371_1 v_b_372_1) (<= .cse2 v_b_368_1))))) is different from true [2019-01-08 14:36:45,719 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_665 Int) (v_idx_666 Int) (v_idx_664 Int) (v_idx_669 Int) (v_idx_667 Int) (v_idx_668 Int) (v_idx_672 Int) (v_idx_670 Int) (v_idx_671 Int)) (exists ((v_v_4129_1 Int) (v_v_4128_1 Int) (v_v_4136_1 Int) (v_v_4134_1 Int) (v_b_369_1 Int) (v_v_4135_1 Int) (v_v_4132_1 Int) (v_b_368_1 Int) (v_v_4130_1 Int) (v_b_370_1 Int) (v_b_371_1 Int) (v_b_372_1 Int) (v_b_373_1 Int)) (let ((.cse0 (+ v_b_369_1 1)) (.cse5 (+ v_b_372_1 1)) (.cse3 (+ v_b_368_1 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse4 (+ v_b_368_1 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ v_b_370_1 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_369_1 v_b_370_1) (<= 0 v_v_4129_1) (<= (+ v_b_368_1 3) v_b_373_1) (<= .cse0 v_b_371_1) (<= .cse1 v_b_371_1) (or (= (select |c_#memory_int| v_idx_672) v_v_4136_1) (< v_idx_672 v_b_373_1)) (<= .cse2 v_b_372_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_373_1) (<= (+ v_b_371_1 1) v_b_373_1) (<= .cse2 v_b_371_1) (or (<= v_b_370_1 v_idx_668) (= (select |c_#memory_int| v_idx_668) v_v_4132_1) (< v_idx_668 v_b_369_1)) (<= .cse3 v_b_372_1) (<= .cse4 v_b_369_1) (<= (+ v_b_369_1 2) v_b_373_1) (or (<= v_b_373_1 v_idx_671) (= (select |c_#memory_int| v_idx_671) v_v_4135_1) (< v_idx_671 v_b_372_1)) (<= v_b_373_1 .cse5) (<= .cse0 v_b_372_1) (or (<= .cse6 v_idx_665) (< v_idx_665 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_665) v_v_4129_1)) (<= 0 (* 2 v_v_4129_1)) (or (< v_idx_666 .cse6) (<= v_b_368_1 v_idx_666) (= (select |c_#memory_int| v_idx_666) v_v_4130_1)) (<= .cse4 v_b_370_1) (<= .cse5 v_b_373_1) (<= .cse3 v_b_371_1) (or (= (select |c_#memory_int| v_idx_667) 0) (<= v_b_369_1 v_idx_667) (< v_idx_667 v_b_368_1)) (<= v_v_4135_1 v_v_4129_1) (<= .cse1 v_b_372_1) (<= .cse7 v_b_370_1) (or (= (select |c_#memory_int| v_idx_664) v_v_4128_1) (<= c_ULTIMATE.start_main_p1 v_idx_664)) (or (< v_idx_670 v_b_371_1) (<= v_b_372_1 v_idx_670) (= (select |c_#memory_int| v_idx_670) v_v_4134_1)) (or (< v_idx_669 v_b_370_1) (= 0 (select |c_#memory_int| v_idx_669)) (<= v_b_371_1 v_idx_669)) (<= v_b_369_1 .cse4) (<= .cse7 v_b_369_1) (<= (+ v_b_370_1 2) v_b_373_1) (<= v_b_371_1 .cse2) (<= (* 2 v_v_4135_1) 0) (<= v_v_4135_1 0) (<= v_b_371_1 v_b_372_1) (<= .cse6 v_b_368_1))))) is different from false [2019-01-08 14:36:47,747 WARN L860 $PredicateComparison]: unable to prove that (forall ((v_idx_665 Int) (v_idx_666 Int) (v_idx_664 Int) (v_idx_669 Int) (v_idx_667 Int) (v_idx_668 Int) (v_idx_672 Int) (v_idx_670 Int) (v_idx_671 Int)) (exists ((v_v_4129_1 Int) (v_v_4128_1 Int) (v_v_4136_1 Int) (v_v_4134_1 Int) (v_b_369_1 Int) (v_v_4135_1 Int) (v_v_4132_1 Int) (v_b_368_1 Int) (v_v_4130_1 Int) (v_b_370_1 Int) (v_b_371_1 Int) (v_b_372_1 Int) (v_b_373_1 Int)) (let ((.cse0 (+ v_b_369_1 1)) (.cse5 (+ v_b_372_1 1)) (.cse3 (+ v_b_368_1 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse4 (+ v_b_368_1 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ v_b_370_1 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_369_1 v_b_370_1) (<= 0 v_v_4129_1) (<= (+ v_b_368_1 3) v_b_373_1) (<= .cse0 v_b_371_1) (<= .cse1 v_b_371_1) (or (= (select |c_#memory_int| v_idx_672) v_v_4136_1) (< v_idx_672 v_b_373_1)) (<= .cse2 v_b_372_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_373_1) (<= (+ v_b_371_1 1) v_b_373_1) (<= .cse2 v_b_371_1) (or (<= v_b_370_1 v_idx_668) (= (select |c_#memory_int| v_idx_668) v_v_4132_1) (< v_idx_668 v_b_369_1)) (<= .cse3 v_b_372_1) (<= .cse4 v_b_369_1) (<= (+ v_b_369_1 2) v_b_373_1) (or (<= v_b_373_1 v_idx_671) (= (select |c_#memory_int| v_idx_671) v_v_4135_1) (< v_idx_671 v_b_372_1)) (<= v_b_373_1 .cse5) (<= .cse0 v_b_372_1) (or (<= .cse6 v_idx_665) (< v_idx_665 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_665) v_v_4129_1)) (<= 0 (* 2 v_v_4129_1)) (or (< v_idx_666 .cse6) (<= v_b_368_1 v_idx_666) (= (select |c_#memory_int| v_idx_666) v_v_4130_1)) (<= .cse4 v_b_370_1) (<= .cse5 v_b_373_1) (<= .cse3 v_b_371_1) (or (= (select |c_#memory_int| v_idx_667) 0) (<= v_b_369_1 v_idx_667) (< v_idx_667 v_b_368_1)) (<= v_v_4135_1 v_v_4129_1) (<= .cse1 v_b_372_1) (<= .cse7 v_b_370_1) (or (= (select |c_#memory_int| v_idx_664) v_v_4128_1) (<= c_ULTIMATE.start_main_p1 v_idx_664)) (or (< v_idx_670 v_b_371_1) (<= v_b_372_1 v_idx_670) (= (select |c_#memory_int| v_idx_670) v_v_4134_1)) (or (< v_idx_669 v_b_370_1) (= 0 (select |c_#memory_int| v_idx_669)) (<= v_b_371_1 v_idx_669)) (<= v_b_369_1 .cse4) (<= .cse7 v_b_369_1) (<= (+ v_b_370_1 2) v_b_373_1) (<= v_b_371_1 .cse2) (<= (* 2 v_v_4135_1) 0) (<= v_v_4135_1 0) (<= v_b_371_1 v_b_372_1) (<= .cse6 v_b_368_1))))) is different from true [2019-01-08 14:36:47,748 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-08 14:36:47,748 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:36:47,748 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:36:47,748 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 6 [2019-01-08 14:36:47,748 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:36:47,748 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-08 14:36:47,749 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-08 14:36:47,749 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=2, Unknown=5, NotChecked=6, Total=20 [2019-01-08 14:36:47,749 INFO L87 Difference]: Start difference. First operand 15 states and 34 transitions. Second operand 5 states. [2019-01-08 14:36:50,257 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_655 Int) (v_idx_663 Int) (v_idx_658 Int) (v_idx_659 Int) (v_idx_656 Int) (v_idx_657 Int) (v_idx_661 Int) (v_idx_662 Int) (v_idx_660 Int)) (exists ((v_v_4129_1 Int) (v_v_4128_1 Int) (v_v_4136_1 Int) (v_v_4134_1 Int) (v_b_369_1 Int) (v_v_4135_1 Int) (v_v_4132_1 Int) (v_b_368_1 Int) (v_v_4130_1 Int) (v_b_370_1 Int) (v_b_371_1 Int) (v_b_372_1 Int) (v_b_373_1 Int)) (let ((.cse0 (+ v_b_369_1 1)) (.cse6 (+ v_b_372_1 1)) (.cse4 (+ v_b_368_1 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse5 (+ v_b_368_1 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ v_b_370_1 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_369_1 v_b_370_1) (<= 0 v_v_4129_1) (or (= (select |c_#memory_int| v_idx_660) 0) (<= v_b_371_1 v_idx_660) (< v_idx_660 v_b_370_1)) (<= (+ v_b_368_1 3) v_b_373_1) (<= .cse0 v_b_371_1) (or (<= v_b_370_1 v_idx_659) (= (select |c_#memory_int| v_idx_659) v_v_4132_1) (< v_idx_659 v_b_369_1)) (<= .cse1 v_b_371_1) (or (= (select |c_#memory_int| v_idx_656) v_v_4129_1) (<= .cse2 v_idx_656) (< v_idx_656 c_ULTIMATE.start_main_p1)) (<= .cse3 v_b_372_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_373_1) (<= (+ v_b_371_1 1) v_b_373_1) (<= .cse3 v_b_371_1) (<= .cse4 v_b_372_1) (<= .cse5 v_b_369_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_655) (= (select |c_#memory_int| v_idx_655) v_v_4128_1)) (<= (+ v_b_369_1 2) v_b_373_1) (or (< v_idx_662 v_b_372_1) (= (select |c_#memory_int| v_idx_662) v_v_4135_1) (<= v_b_373_1 v_idx_662)) (<= v_b_373_1 .cse6) (<= .cse0 v_b_372_1) (<= 0 (* 2 v_v_4129_1)) (<= .cse5 v_b_370_1) (<= .cse6 v_b_373_1) (or (= (select |c_#memory_int| v_idx_663) v_v_4136_1) (< v_idx_663 v_b_373_1)) (<= .cse4 v_b_371_1) (<= v_v_4135_1 v_v_4129_1) (<= .cse1 v_b_372_1) (<= .cse7 v_b_370_1) (or (<= v_b_372_1 v_idx_661) (= (select |c_#memory_int| v_idx_661) v_v_4134_1) (< v_idx_661 v_b_371_1)) (or (= (select |c_#memory_int| v_idx_657) v_v_4130_1) (<= v_b_368_1 v_idx_657) (< v_idx_657 .cse2)) (<= v_b_369_1 .cse5) (<= .cse7 v_b_369_1) (or (< v_idx_658 v_b_368_1) (= (select |c_#memory_int| v_idx_658) 0) (<= v_b_369_1 v_idx_658)) (<= (+ v_b_370_1 2) v_b_373_1) (<= v_b_371_1 .cse3) (<= (* 2 v_v_4135_1) 0) (<= v_v_4135_1 0) (<= v_b_371_1 v_b_372_1) (<= .cse2 v_b_368_1))))) (forall ((v_idx_654 Int) (v_idx_652 Int) (v_idx_653 Int) (v_idx_647 Int) (v_idx_648 Int) (v_idx_646 Int) (v_idx_649 Int) (v_idx_650 Int) (v_idx_651 Int)) (exists ((v_v_4130_1 Int) (v_b_370_1 Int) (v_b_371_1 Int) (v_v_4129_1 Int) (v_v_4128_1 Int) (v_v_4136_1 Int) (v_v_4134_1 Int) (v_b_369_1 Int) (v_v_4135_1 Int) (v_b_368_1 Int) (v_v_4132_1 Int)) (let ((.cse9 (+ c_ULTIMATE.start_main_p1 3)) (.cse8 (+ v_b_369_1 1)) (.cse13 (+ v_b_368_1 2)) (.cse12 (+ v_b_368_1 1)) (.cse14 (+ c_ULTIMATE.start_main_p1 2)) (.cse10 (+ v_b_370_1 1)) (.cse15 (+ c_ULTIMATE.start_main_p4 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_371_1 c_ULTIMATE.start_main_p4) (<= v_b_369_1 v_b_370_1) (<= 0 v_v_4129_1) (<= .cse8 v_b_371_1) (<= .cse9 v_b_371_1) (<= .cse10 v_b_371_1) (or (< v_idx_648 .cse11) (<= v_b_368_1 v_idx_648) (= (select |c_#memory_int| v_idx_648) v_v_4130_1)) (<= .cse10 c_ULTIMATE.start_main_p4) (or (= (select |c_#memory_int| v_idx_651) 0) (<= v_b_371_1 v_idx_651) (< v_idx_651 v_b_370_1)) (<= .cse12 v_b_369_1) (<= .cse9 c_ULTIMATE.start_main_p4) (<= 0 (* 2 v_v_4129_1)) (or (= (select |c_#memory_int| v_idx_652) v_v_4134_1) (< v_idx_652 v_b_371_1) (<= c_ULTIMATE.start_main_p4 v_idx_652)) (<= .cse12 v_b_370_1) (<= .cse8 c_ULTIMATE.start_main_p4) (<= .cse13 c_ULTIMATE.start_main_p4) (or (= (select |c_#memory_int| v_idx_647) v_v_4129_1) (<= .cse11 v_idx_647) (< v_idx_647 c_ULTIMATE.start_main_p1)) (<= .cse13 v_b_371_1) (or (< v_idx_650 v_b_369_1) (= (select |c_#memory_int| v_idx_650) v_v_4132_1) (<= v_b_370_1 v_idx_650)) (or (= (select |c_#memory_int| v_idx_646) v_v_4128_1) (<= c_ULTIMATE.start_main_p1 v_idx_646)) (<= v_v_4135_1 v_v_4129_1) (<= .cse14 v_b_370_1) (or (<= .cse15 v_idx_653) (< v_idx_653 c_ULTIMATE.start_main_p4) (= (select |c_#memory_int| v_idx_653) v_v_4135_1)) (<= v_b_369_1 .cse12) (<= .cse14 v_b_369_1) (<= v_b_371_1 .cse10) (<= (* 2 v_v_4135_1) 0) (<= v_v_4135_1 0) (or (< v_idx_654 .cse15) (= (select |c_#memory_int| v_idx_654) v_v_4136_1)) (or (< v_idx_649 v_b_368_1) (<= v_b_369_1 v_idx_649) (= (select |c_#memory_int| v_idx_649) 0)) (<= .cse11 v_b_368_1))))) (forall ((v_idx_665 Int) (v_idx_666 Int) (v_idx_664 Int) (v_idx_669 Int) (v_idx_667 Int) (v_idx_668 Int) (v_idx_672 Int) (v_idx_670 Int) (v_idx_671 Int)) (exists ((v_v_4129_1 Int) (v_v_4128_1 Int) (v_v_4136_1 Int) (v_v_4134_1 Int) (v_b_369_1 Int) (v_v_4135_1 Int) (v_v_4132_1 Int) (v_b_368_1 Int) (v_v_4130_1 Int) (v_b_370_1 Int) (v_b_371_1 Int) (v_b_372_1 Int) (v_b_373_1 Int)) (let ((.cse16 (+ v_b_369_1 1)) (.cse21 (+ v_b_372_1 1)) (.cse19 (+ v_b_368_1 2)) (.cse17 (+ c_ULTIMATE.start_main_p1 3)) (.cse20 (+ v_b_368_1 1)) (.cse23 (+ c_ULTIMATE.start_main_p1 2)) (.cse18 (+ v_b_370_1 1)) (.cse22 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_369_1 v_b_370_1) (<= 0 v_v_4129_1) (<= (+ v_b_368_1 3) v_b_373_1) (<= .cse16 v_b_371_1) (<= .cse17 v_b_371_1) (or (= (select |c_#memory_int| v_idx_672) v_v_4136_1) (< v_idx_672 v_b_373_1)) (<= .cse18 v_b_372_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_373_1) (<= (+ v_b_371_1 1) v_b_373_1) (<= .cse18 v_b_371_1) (or (<= v_b_370_1 v_idx_668) (= (select |c_#memory_int| v_idx_668) v_v_4132_1) (< v_idx_668 v_b_369_1)) (<= .cse19 v_b_372_1) (<= .cse20 v_b_369_1) (<= (+ v_b_369_1 2) v_b_373_1) (or (<= v_b_373_1 v_idx_671) (= (select |c_#memory_int| v_idx_671) v_v_4135_1) (< v_idx_671 v_b_372_1)) (<= v_b_373_1 .cse21) (<= .cse16 v_b_372_1) (or (<= .cse22 v_idx_665) (< v_idx_665 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_665) v_v_4129_1)) (<= 0 (* 2 v_v_4129_1)) (or (< v_idx_666 .cse22) (<= v_b_368_1 v_idx_666) (= (select |c_#memory_int| v_idx_666) v_v_4130_1)) (<= .cse20 v_b_370_1) (<= .cse21 v_b_373_1) (<= .cse19 v_b_371_1) (or (= (select |c_#memory_int| v_idx_667) 0) (<= v_b_369_1 v_idx_667) (< v_idx_667 v_b_368_1)) (<= v_v_4135_1 v_v_4129_1) (<= .cse17 v_b_372_1) (<= .cse23 v_b_370_1) (or (= (select |c_#memory_int| v_idx_664) v_v_4128_1) (<= c_ULTIMATE.start_main_p1 v_idx_664)) (or (< v_idx_670 v_b_371_1) (<= v_b_372_1 v_idx_670) (= (select |c_#memory_int| v_idx_670) v_v_4134_1)) (or (< v_idx_669 v_b_370_1) (= 0 (select |c_#memory_int| v_idx_669)) (<= v_b_371_1 v_idx_669)) (<= v_b_369_1 .cse20) (<= .cse23 v_b_369_1) (<= (+ v_b_370_1 2) v_b_373_1) (<= v_b_371_1 .cse18) (<= (* 2 v_v_4135_1) 0) (<= v_v_4135_1 0) (<= v_b_371_1 v_b_372_1) (<= .cse22 v_b_368_1)))))) is different from false [2019-01-08 14:37:28,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:37:28,897 INFO L93 Difference]: Finished difference Result 18 states and 45 transitions. [2019-01-08 14:37:28,898 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-08 14:37:28,898 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-08 14:37:28,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:37:28,898 INFO L225 Difference]: With dead ends: 18 [2019-01-08 14:37:28,899 INFO L226 Difference]: Without dead ends: 17 [2019-01-08 14:37:28,899 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 13.5s TimeCoverageRelationStatistics Valid=9, Invalid=3, Unknown=6, NotChecked=12, Total=30 [2019-01-08 14:37:28,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2019-01-08 14:37:28,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 15. [2019-01-08 14:37:28,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-08 14:37:28,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 34 transitions. [2019-01-08 14:37:28,913 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 34 transitions. Word has length 4 [2019-01-08 14:37:28,914 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:37:28,914 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 34 transitions. [2019-01-08 14:37:28,914 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-08 14:37:28,914 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 34 transitions. [2019-01-08 14:37:28,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-08 14:37:28,914 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:37:28,915 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-08 14:37:28,915 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:37:28,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:37:28,915 INFO L82 PathProgramCache]: Analyzing trace with hash 939226, now seen corresponding path program 1 times [2019-01-08 14:37:28,915 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:37:28,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:37:28,916 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:37:28,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:37:28,916 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:37:28,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:37:29,007 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:37:29,007 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:37:29,008 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:37:29,008 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-08 14:37:29,008 INFO L207 CegarAbsIntRunner]: [0], [10], [16], [19] [2019-01-08 14:37:29,010 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:37:29,010 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:37:43,394 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:37:43,395 INFO L272 AbstractInterpreter]: Visited 4 different actions 31 times. Merged at 2 different actions 9 times. Widened at 2 different actions 5 times. Found 11 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-08 14:37:43,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:37:43,395 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:37:43,805 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 62.5% of their original sizes. [2019-01-08 14:37:43,806 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:37:46,222 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_797 Int) (v_idx_798 Int) (v_idx_795 Int) (v_idx_796 Int) (v_idx_790 Int) (v_idx_793 Int) (v_idx_794 Int) (v_idx_791 Int) (v_idx_792 Int)) (exists ((v_v_4182_2 Int) (v_v_4183_2 Int) (v_v_4185_2 Int) (v_b_382_2 Int) (v_v_4181_2 Int) (v_b_383_2 Int) (v_v_4179_2 Int) (v_v_4186_2 Int) (v_v_4187_2 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse3 (+ c_ULTIMATE.start_main_p4 1)) (.cse0 (+ v_b_382_2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse5 (+ c_ULTIMATE.start_main_p2 2))) (and (<= .cse0 v_b_383_2) (<= .cse1 v_b_383_2) (or (= (select |c_#memory_int| v_idx_790) v_v_4179_2) (<= c_ULTIMATE.start_main_p1 v_idx_790)) (<= v_v_4186_2 0) (or (<= c_ULTIMATE.start_main_p2 v_idx_792) (< v_idx_792 .cse2) (= (select |c_#memory_int| v_idx_792) v_v_4181_2)) (<= (+ v_v_4182_2 v_v_4186_2) 0) (or (= (select |c_#memory_int| v_idx_797) v_v_4186_2) (<= .cse3 v_idx_797) (< v_idx_797 c_ULTIMATE.start_main_p4)) (<= v_b_383_2 c_ULTIMATE.start_main_p4) (<= (* 2 v_v_4186_2) 0) (<= .cse1 c_ULTIMATE.start_main_p4) (<= .cse4 v_b_382_2) (or (<= v_b_382_2 v_idx_794) (< v_idx_794 .cse4) (= (select |c_#memory_int| v_idx_794) v_v_4183_2)) (or (< v_idx_793 c_ULTIMATE.start_main_p2) (<= .cse4 v_idx_793) (= (select |c_#memory_int| v_idx_793) v_v_4182_2)) (or (< v_idx_798 .cse3) (= (select |c_#memory_int| v_idx_798) v_v_4187_2)) (or (<= c_ULTIMATE.start_main_p4 v_idx_796) (< v_idx_796 v_b_383_2) (= (select |c_#memory_int| v_idx_796) v_v_4185_2)) (or (<= .cse2 v_idx_791) (< v_idx_791 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_791) 0)) (<= .cse5 c_ULTIMATE.start_main_p4) (<= v_b_383_2 .cse0) (<= .cse0 c_ULTIMATE.start_main_p4) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_382_2) (or (< v_idx_795 v_b_382_2) (<= v_b_383_2 v_idx_795) (= (select |c_#memory_int| v_idx_795) 0)) (<= (* 2 v_v_4182_2) 0) (<= .cse2 c_ULTIMATE.start_main_p2) (<= v_v_4182_2 0) (<= .cse5 v_b_383_2))))) is different from false [2019-01-08 14:37:48,678 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_801 Int) (v_idx_802 Int) (v_idx_799 Int) (v_idx_800 Int) (v_idx_805 Int) (v_idx_806 Int) (v_idx_803 Int) (v_idx_804 Int) (v_idx_807 Int)) (exists ((v_v_4182_2 Int) (v_b_384_2 Int) (v_b_385_2 Int) (v_v_4183_2 Int) (v_v_4185_2 Int) (v_b_382_2 Int) (v_v_4181_2 Int) (v_b_383_2 Int) (v_v_4179_2 Int) (v_v_4186_2 Int) (v_v_4187_2 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_382_2 1)) (.cse4 (+ v_b_384_2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 3)) (.cse3 (+ c_ULTIMATE.start_main_p1 1)) (.cse5 (+ c_ULTIMATE.start_main_p2 2))) (and (or (< v_idx_802 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_802) v_v_4182_2) (<= .cse0 v_idx_802)) (or (= (select |c_#memory_int| v_idx_799) v_v_4179_2) (<= c_ULTIMATE.start_main_p1 v_idx_799)) (or (<= v_b_383_2 v_idx_804) (< v_idx_804 v_b_382_2) (= (select |c_#memory_int| v_idx_804) 0)) (<= .cse1 v_b_383_2) (<= .cse2 v_b_383_2) (or (< v_idx_801 .cse3) (= (select |c_#memory_int| v_idx_801) v_v_4181_2) (<= c_ULTIMATE.start_main_p2 v_idx_801)) (<= v_v_4186_2 0) (<= (+ v_b_382_2 2) v_b_385_2) (<= (+ v_v_4182_2 v_v_4186_2) 0) (or (= (select |c_#memory_int| v_idx_800) 0) (<= .cse3 v_idx_800) (< v_idx_800 c_ULTIMATE.start_main_p1)) (<= (* 2 v_v_4186_2) 0) (or (< v_idx_807 v_b_385_2) (= (select |c_#memory_int| v_idx_807) v_v_4187_2)) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_385_2) (<= .cse0 v_b_382_2) (<= (+ v_b_383_2 1) v_b_385_2) (<= v_b_385_2 .cse4) (<= .cse5 v_b_384_2) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_385_2) (or (<= v_b_382_2 v_idx_803) (= (select |c_#memory_int| v_idx_803) v_v_4183_2) (< v_idx_803 .cse0)) (<= .cse1 v_b_384_2) (<= v_b_383_2 .cse1) (<= .cse4 v_b_385_2) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_382_2) (<= .cse2 v_b_384_2) (or (= (select |c_#memory_int| v_idx_805) v_v_4185_2) (< v_idx_805 v_b_383_2) (<= v_b_384_2 v_idx_805)) (<= v_b_383_2 v_b_384_2) (<= (* 2 v_v_4182_2) 0) (or (<= v_b_385_2 v_idx_806) (= (select |c_#memory_int| v_idx_806) v_v_4186_2) (< v_idx_806 v_b_384_2)) (<= .cse3 c_ULTIMATE.start_main_p2) (<= v_v_4182_2 0) (<= .cse5 v_b_383_2))))) is different from false [2019-01-08 14:37:51,292 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_812 Int) (v_idx_813 Int) (v_idx_810 Int) (v_idx_811 Int) (v_idx_816 Int) (v_idx_814 Int) (v_idx_815 Int) (v_idx_809 Int) (v_idx_808 Int)) (exists ((v_v_4179_2 Int) (v_v_4186_2 Int) (v_v_4187_2 Int) (v_v_4182_2 Int) (v_b_384_2 Int) (v_b_385_2 Int) (v_v_4183_2 Int) (v_v_4185_2 Int) (v_b_380_2 Int) (v_b_381_2 Int) (v_b_382_2 Int) (v_v_4181_2 Int) (v_b_383_2 Int)) (let ((.cse1 (+ v_b_380_2 2)) (.cse4 (+ v_b_380_2 1)) (.cse3 (+ v_b_381_2 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ v_b_382_2 1)) (.cse7 (+ v_b_384_2 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ c_ULTIMATE.start_main_p1 3))) (and (<= .cse0 v_b_383_2) (<= .cse1 v_b_383_2) (<= .cse2 v_b_383_2) (<= .cse3 v_b_383_2) (<= .cse4 v_b_382_2) (or (<= v_b_380_2 v_idx_810) (< v_idx_810 .cse5) (= (select |c_#memory_int| v_idx_810) v_v_4181_2)) (<= v_v_4186_2 0) (<= (+ v_b_382_2 2) v_b_385_2) (<= v_b_381_2 .cse4) (<= (+ v_v_4182_2 v_v_4186_2) 0) (<= .cse1 v_b_384_2) (<= .cse5 v_b_380_2) (<= .cse4 v_b_381_2) (<= .cse6 v_b_381_2) (<= (* 2 v_v_4186_2) 0) (or (= (select |c_#memory_int| v_idx_814) v_v_4185_2) (< v_idx_814 v_b_383_2) (<= v_b_384_2 v_idx_814)) (<= .cse3 v_b_384_2) (or (= (select |c_#memory_int| v_idx_811) v_v_4182_2) (<= v_b_381_2 v_idx_811) (< v_idx_811 v_b_380_2)) (<= (+ v_b_383_2 1) v_b_385_2) (<= v_b_385_2 .cse7) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_385_2) (<= (+ v_b_381_2 2) v_b_385_2) (or (< v_idx_816 v_b_385_2) (= (select |c_#memory_int| v_idx_816) v_v_4187_2)) (<= v_b_381_2 v_b_382_2) (or (= (select |c_#memory_int| v_idx_809) 0) (< v_idx_809 c_ULTIMATE.start_main_p1) (<= .cse5 v_idx_809)) (or (= (select |c_#memory_int| v_idx_808) v_v_4179_2) (<= c_ULTIMATE.start_main_p1 v_idx_808)) (<= .cse0 v_b_384_2) (or (<= v_b_385_2 v_idx_815) (= (select |c_#memory_int| v_idx_815) v_v_4186_2) (< v_idx_815 v_b_384_2)) (<= v_b_383_2 .cse0) (<= .cse7 v_b_385_2) (or (< v_idx_813 v_b_382_2) (= (select |c_#memory_int| v_idx_813) 0) (<= v_b_383_2 v_idx_813)) (<= .cse6 v_b_382_2) (<= .cse2 v_b_384_2) (<= v_b_383_2 v_b_384_2) (<= (* 2 v_v_4182_2) 0) (or (= (select |c_#memory_int| v_idx_812) v_v_4183_2) (< v_idx_812 v_b_381_2) (<= v_b_382_2 v_idx_812)) (<= v_v_4182_2 0) (<= (+ v_b_380_2 3) v_b_385_2))))) is different from false [2019-01-08 14:37:51,429 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-08 14:37:51,430 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:37:51,430 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:37:51,430 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 6 [2019-01-08 14:37:51,430 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:37:51,430 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-08 14:37:51,430 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-08 14:37:51,431 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:37:51,431 INFO L87 Difference]: Start difference. First operand 15 states and 34 transitions. Second operand 5 states. [2019-01-08 14:37:54,288 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_812 Int) (v_idx_813 Int) (v_idx_810 Int) (v_idx_811 Int) (v_idx_816 Int) (v_idx_814 Int) (v_idx_815 Int) (v_idx_809 Int) (v_idx_808 Int)) (exists ((v_v_4179_2 Int) (v_v_4186_2 Int) (v_v_4187_2 Int) (v_v_4182_2 Int) (v_b_384_2 Int) (v_b_385_2 Int) (v_v_4183_2 Int) (v_v_4185_2 Int) (v_b_380_2 Int) (v_b_381_2 Int) (v_b_382_2 Int) (v_v_4181_2 Int) (v_b_383_2 Int)) (let ((.cse1 (+ v_b_380_2 2)) (.cse4 (+ v_b_380_2 1)) (.cse3 (+ v_b_381_2 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ v_b_382_2 1)) (.cse7 (+ v_b_384_2 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ c_ULTIMATE.start_main_p1 3))) (and (<= .cse0 v_b_383_2) (<= .cse1 v_b_383_2) (<= .cse2 v_b_383_2) (<= .cse3 v_b_383_2) (<= .cse4 v_b_382_2) (or (<= v_b_380_2 v_idx_810) (< v_idx_810 .cse5) (= (select |c_#memory_int| v_idx_810) v_v_4181_2)) (<= v_v_4186_2 0) (<= (+ v_b_382_2 2) v_b_385_2) (<= v_b_381_2 .cse4) (<= (+ v_v_4182_2 v_v_4186_2) 0) (<= .cse1 v_b_384_2) (<= .cse5 v_b_380_2) (<= .cse4 v_b_381_2) (<= .cse6 v_b_381_2) (<= (* 2 v_v_4186_2) 0) (or (= (select |c_#memory_int| v_idx_814) v_v_4185_2) (< v_idx_814 v_b_383_2) (<= v_b_384_2 v_idx_814)) (<= .cse3 v_b_384_2) (or (= (select |c_#memory_int| v_idx_811) v_v_4182_2) (<= v_b_381_2 v_idx_811) (< v_idx_811 v_b_380_2)) (<= (+ v_b_383_2 1) v_b_385_2) (<= v_b_385_2 .cse7) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_385_2) (<= (+ v_b_381_2 2) v_b_385_2) (or (< v_idx_816 v_b_385_2) (= (select |c_#memory_int| v_idx_816) v_v_4187_2)) (<= v_b_381_2 v_b_382_2) (or (= (select |c_#memory_int| v_idx_809) 0) (< v_idx_809 c_ULTIMATE.start_main_p1) (<= .cse5 v_idx_809)) (or (= (select |c_#memory_int| v_idx_808) v_v_4179_2) (<= c_ULTIMATE.start_main_p1 v_idx_808)) (<= .cse0 v_b_384_2) (or (<= v_b_385_2 v_idx_815) (= (select |c_#memory_int| v_idx_815) v_v_4186_2) (< v_idx_815 v_b_384_2)) (<= v_b_383_2 .cse0) (<= .cse7 v_b_385_2) (or (< v_idx_813 v_b_382_2) (= (select |c_#memory_int| v_idx_813) 0) (<= v_b_383_2 v_idx_813)) (<= .cse6 v_b_382_2) (<= .cse2 v_b_384_2) (<= v_b_383_2 v_b_384_2) (<= (* 2 v_v_4182_2) 0) (or (= (select |c_#memory_int| v_idx_812) v_v_4183_2) (< v_idx_812 v_b_381_2) (<= v_b_382_2 v_idx_812)) (<= v_v_4182_2 0) (<= (+ v_b_380_2 3) v_b_385_2))))) (forall ((v_idx_801 Int) (v_idx_802 Int) (v_idx_799 Int) (v_idx_800 Int) (v_idx_805 Int) (v_idx_806 Int) (v_idx_803 Int) (v_idx_804 Int) (v_idx_807 Int)) (exists ((v_v_4182_2 Int) (v_b_384_2 Int) (v_b_385_2 Int) (v_v_4183_2 Int) (v_v_4185_2 Int) (v_b_382_2 Int) (v_v_4181_2 Int) (v_b_383_2 Int) (v_v_4179_2 Int) (v_v_4186_2 Int) (v_v_4187_2 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p2 1)) (.cse9 (+ v_b_382_2 1)) (.cse12 (+ v_b_384_2 1)) (.cse10 (+ c_ULTIMATE.start_main_p1 3)) (.cse11 (+ c_ULTIMATE.start_main_p1 1)) (.cse13 (+ c_ULTIMATE.start_main_p2 2))) (and (or (< v_idx_802 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_802) v_v_4182_2) (<= .cse8 v_idx_802)) (or (= (select |c_#memory_int| v_idx_799) v_v_4179_2) (<= c_ULTIMATE.start_main_p1 v_idx_799)) (or (<= v_b_383_2 v_idx_804) (< v_idx_804 v_b_382_2) (= (select |c_#memory_int| v_idx_804) 0)) (<= .cse9 v_b_383_2) (<= .cse10 v_b_383_2) (or (< v_idx_801 .cse11) (= (select |c_#memory_int| v_idx_801) v_v_4181_2) (<= c_ULTIMATE.start_main_p2 v_idx_801)) (<= v_v_4186_2 0) (<= (+ v_b_382_2 2) v_b_385_2) (<= (+ v_v_4182_2 v_v_4186_2) 0) (or (= (select |c_#memory_int| v_idx_800) 0) (<= .cse11 v_idx_800) (< v_idx_800 c_ULTIMATE.start_main_p1)) (<= (* 2 v_v_4186_2) 0) (or (< v_idx_807 v_b_385_2) (= (select |c_#memory_int| v_idx_807) v_v_4187_2)) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_385_2) (<= .cse8 v_b_382_2) (<= (+ v_b_383_2 1) v_b_385_2) (<= v_b_385_2 .cse12) (<= .cse13 v_b_384_2) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_385_2) (or (<= v_b_382_2 v_idx_803) (= (select |c_#memory_int| v_idx_803) v_v_4183_2) (< v_idx_803 .cse8)) (<= .cse9 v_b_384_2) (<= v_b_383_2 .cse9) (<= .cse12 v_b_385_2) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_382_2) (<= .cse10 v_b_384_2) (or (= (select |c_#memory_int| v_idx_805) v_v_4185_2) (< v_idx_805 v_b_383_2) (<= v_b_384_2 v_idx_805)) (<= v_b_383_2 v_b_384_2) (<= (* 2 v_v_4182_2) 0) (or (<= v_b_385_2 v_idx_806) (= (select |c_#memory_int| v_idx_806) v_v_4186_2) (< v_idx_806 v_b_384_2)) (<= .cse11 c_ULTIMATE.start_main_p2) (<= v_v_4182_2 0) (<= .cse13 v_b_383_2))))) (forall ((v_idx_797 Int) (v_idx_798 Int) (v_idx_795 Int) (v_idx_796 Int) (v_idx_790 Int) (v_idx_793 Int) (v_idx_794 Int) (v_idx_791 Int) (v_idx_792 Int)) (exists ((v_v_4182_2 Int) (v_v_4183_2 Int) (v_v_4185_2 Int) (v_b_382_2 Int) (v_v_4181_2 Int) (v_b_383_2 Int) (v_v_4179_2 Int) (v_v_4186_2 Int) (v_v_4187_2 Int)) (let ((.cse15 (+ c_ULTIMATE.start_main_p1 3)) (.cse18 (+ c_ULTIMATE.start_main_p2 1)) (.cse17 (+ c_ULTIMATE.start_main_p4 1)) (.cse14 (+ v_b_382_2 1)) (.cse16 (+ c_ULTIMATE.start_main_p1 1)) (.cse19 (+ c_ULTIMATE.start_main_p2 2))) (and (<= .cse14 v_b_383_2) (<= .cse15 v_b_383_2) (or (= (select |c_#memory_int| v_idx_790) v_v_4179_2) (<= c_ULTIMATE.start_main_p1 v_idx_790)) (<= v_v_4186_2 0) (or (<= c_ULTIMATE.start_main_p2 v_idx_792) (< v_idx_792 .cse16) (= (select |c_#memory_int| v_idx_792) v_v_4181_2)) (<= (+ v_v_4182_2 v_v_4186_2) 0) (or (= (select |c_#memory_int| v_idx_797) v_v_4186_2) (<= .cse17 v_idx_797) (< v_idx_797 c_ULTIMATE.start_main_p4)) (<= v_b_383_2 c_ULTIMATE.start_main_p4) (<= (* 2 v_v_4186_2) 0) (<= .cse15 c_ULTIMATE.start_main_p4) (<= .cse18 v_b_382_2) (or (<= v_b_382_2 v_idx_794) (< v_idx_794 .cse18) (= (select |c_#memory_int| v_idx_794) v_v_4183_2)) (or (< v_idx_793 c_ULTIMATE.start_main_p2) (<= .cse18 v_idx_793) (= (select |c_#memory_int| v_idx_793) v_v_4182_2)) (or (< v_idx_798 .cse17) (= (select |c_#memory_int| v_idx_798) v_v_4187_2)) (or (<= c_ULTIMATE.start_main_p4 v_idx_796) (< v_idx_796 v_b_383_2) (= (select |c_#memory_int| v_idx_796) v_v_4185_2)) (or (<= .cse16 v_idx_791) (< v_idx_791 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_791) 0)) (<= .cse19 c_ULTIMATE.start_main_p4) (<= v_b_383_2 .cse14) (<= .cse14 c_ULTIMATE.start_main_p4) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_382_2) (or (< v_idx_795 v_b_382_2) (<= v_b_383_2 v_idx_795) (= (select |c_#memory_int| v_idx_795) 0)) (<= (* 2 v_v_4182_2) 0) (<= .cse16 c_ULTIMATE.start_main_p2) (<= v_v_4182_2 0) (<= .cse19 v_b_383_2)))))) is different from false [2019-01-08 14:38:20,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:38:20,498 INFO L93 Difference]: Finished difference Result 18 states and 45 transitions. [2019-01-08 14:38:20,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-08 14:38:20,498 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-08 14:38:20,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:38:20,499 INFO L225 Difference]: With dead ends: 18 [2019-01-08 14:38:20,499 INFO L226 Difference]: Without dead ends: 17 [2019-01-08 14:38:20,500 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 10.1s TimeCoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-08 14:38:20,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2019-01-08 14:38:20,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 15. [2019-01-08 14:38:20,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-08 14:38:20,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 34 transitions. [2019-01-08 14:38:20,516 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 34 transitions. Word has length 4 [2019-01-08 14:38:20,516 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:38:20,516 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 34 transitions. [2019-01-08 14:38:20,516 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-08 14:38:20,516 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 34 transitions. [2019-01-08 14:38:20,517 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-08 14:38:20,517 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:38:20,517 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-08 14:38:20,517 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:38:20,517 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:38:20,517 INFO L82 PathProgramCache]: Analyzing trace with hash 939350, now seen corresponding path program 1 times [2019-01-08 14:38:20,517 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:38:20,518 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:20,518 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:38:20,518 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:20,518 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:38:20,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:38:20,621 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:38:20,622 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:38:20,622 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:38:20,622 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-08 14:38:20,622 INFO L207 CegarAbsIntRunner]: [0], [14], [16], [19] [2019-01-08 14:38:20,623 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:38:20,623 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:38:31,995 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:38:31,996 INFO L272 AbstractInterpreter]: Visited 4 different actions 28 times. Merged at 2 different actions 8 times. Widened at 2 different actions 4 times. Found 10 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-08 14:38:31,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:38:31,996 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:38:32,390 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 62.5% of their original sizes. [2019-01-08 14:38:32,391 INFO L418 sIntCurrentIteration]: Unifying AI predicates