java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml -s ../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf -i ../../../trunk/examples/programs/heapseparator/speedup-poc-dd-6-limited.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.24-f57a05f [2019-01-08 14:35:05,995 INFO L170 SettingsManager]: Resetting all preferences to default values... [2019-01-08 14:35:05,997 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2019-01-08 14:35:06,014 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2019-01-08 14:35:06,073 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf [2019-01-08 14:35:06,099 INFO L110 SettingsManager]: Loading preferences was successful [2019-01-08 14:35:06,100 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2019-01-08 14:35:06,100 INFO L131 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2019-01-08 14:35:06,101 INFO L133 SettingsManager]: * Show backtranslation warnings=false [2019-01-08 14:35:06,101 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-01-08 14:35:06,102 INFO L133 SettingsManager]: * User list type=DISABLED [2019-01-08 14:35:06,102 INFO L133 SettingsManager]: * Inline calls to unimplemented procedures=true [2019-01-08 14:35:06,102 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-01-08 14:35:06,102 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-01-08 14:35:06,103 INFO L133 SettingsManager]: * Underlying domain=OctagonDomain [2019-01-08 14:35:06,103 INFO L133 SettingsManager]: * Abstract domain=ArrayDomain [2019-01-08 14:35:06,103 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-01-08 14:35:06,103 INFO L133 SettingsManager]: * Interval Domain=false [2019-01-08 14:35:06,104 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-01-08 14:35:06,105 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2019-01-08 14:35:06,105 INFO L133 SettingsManager]: * Use SBE=true [2019-01-08 14:35:06,105 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-01-08 14:35:06,105 INFO L133 SettingsManager]: * sizeof long=4 [2019-01-08 14:35:06,107 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2019-01-08 14:35:06,108 INFO L133 SettingsManager]: * sizeof POINTER=4 [2019-01-08 14:35:06,108 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2019-01-08 14:35:06,108 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-01-08 14:35:06,108 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-01-08 14:35:06,109 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-01-08 14:35:06,109 INFO L133 SettingsManager]: * sizeof long double=12 [2019-01-08 14:35:06,109 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2019-01-08 14:35:06,110 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-01-08 14:35:06,110 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-01-08 14:35:06,110 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-01-08 14:35:06,110 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2019-01-08 14:35:06,111 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-08 14:35:06,111 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-01-08 14:35:06,111 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-01-08 14:35:06,111 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-01-08 14:35:06,112 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2019-01-08 14:35:06,112 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-01-08 14:35:06,112 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in [2019-01-08 14:35:06,113 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-01-08 14:35:06,113 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2019-01-08 14:35:06,168 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-01-08 14:35:06,186 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-01-08 14:35:06,193 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-01-08 14:35:06,195 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2019-01-08 14:35:06,195 INFO L276 PluginConnector]: Boogie PL CUP Parser initialized [2019-01-08 14:35:06,196 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-6-limited.bpl [2019-01-08 14:35:06,196 INFO L111 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-6-limited.bpl' [2019-01-08 14:35:06,251 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-01-08 14:35:06,253 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-01-08 14:35:06,254 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-01-08 14:35:06,254 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-01-08 14:35:06,254 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2019-01-08 14:35:06,270 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:06" (1/1) ... [2019-01-08 14:35:06,283 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:06" (1/1) ... [2019-01-08 14:35:06,313 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-01-08 14:35:06,314 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-01-08 14:35:06,314 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-01-08 14:35:06,314 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2019-01-08 14:35:06,326 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:06" (1/1) ... [2019-01-08 14:35:06,327 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:06" (1/1) ... [2019-01-08 14:35:06,329 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:06" (1/1) ... [2019-01-08 14:35:06,329 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:06" (1/1) ... [2019-01-08 14:35:06,333 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:06" (1/1) ... [2019-01-08 14:35:06,340 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:06" (1/1) ... [2019-01-08 14:35:06,342 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:06" (1/1) ... [2019-01-08 14:35:06,344 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-01-08 14:35:06,345 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-01-08 14:35:06,345 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-01-08 14:35:06,345 INFO L276 PluginConnector]: RCFGBuilder initialized [2019-01-08 14:35:06,346 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:06" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-08 14:35:06,421 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-01-08 14:35:06,422 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-01-08 14:35:06,823 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-01-08 14:35:06,823 INFO L286 CfgBuilder]: Removed 15 assue(true) statements. [2019-01-08 14:35:06,825 INFO L202 PluginConnector]: Adding new model speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.01 02:35:06 BoogieIcfgContainer [2019-01-08 14:35:06,825 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-01-08 14:35:06,826 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-01-08 14:35:06,826 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-01-08 14:35:06,830 INFO L276 PluginConnector]: TraceAbstraction initialized [2019-01-08 14:35:06,830 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:06" (1/2) ... [2019-01-08 14:35:06,831 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@307c1611 and model type speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.01 02:35:06, skipping insertion in model container [2019-01-08 14:35:06,831 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.01 02:35:06" (2/2) ... [2019-01-08 14:35:06,835 INFO L112 eAbstractionObserver]: Analyzing ICFG speedup-poc-dd-6-limited.bpl [2019-01-08 14:35:06,845 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-01-08 14:35:06,852 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 6 error locations. [2019-01-08 14:35:06,871 INFO L257 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-01-08 14:35:06,903 INFO L382 AbstractCegarLoop]: Interprodecural is true [2019-01-08 14:35:06,904 INFO L383 AbstractCegarLoop]: Hoare is true [2019-01-08 14:35:06,904 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-01-08 14:35:06,904 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-01-08 14:35:06,904 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-01-08 14:35:06,904 INFO L387 AbstractCegarLoop]: Difference is false [2019-01-08 14:35:06,904 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-01-08 14:35:06,905 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-01-08 14:35:06,919 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states. [2019-01-08 14:35:06,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3 [2019-01-08 14:35:06,925 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:35:06,926 INFO L402 BasicCegarLoop]: trace histogram [1, 1] [2019-01-08 14:35:06,929 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:35:06,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:35:06,935 INFO L82 PathProgramCache]: Analyzing trace with hash 988, now seen corresponding path program 1 times [2019-01-08 14:35:06,937 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:35:06,987 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:06,987 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:35:06,987 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:06,988 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:35:07,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:35:07,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:35:07,136 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-08 14:35:07,137 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-08 14:35:07,137 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:35:07,143 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-08 14:35:07,160 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-08 14:35:07,161 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:35:07,164 INFO L87 Difference]: Start difference. First operand 15 states. Second operand 3 states. [2019-01-08 14:35:07,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:35:07,483 INFO L93 Difference]: Finished difference Result 29 states and 39 transitions. [2019-01-08 14:35:07,484 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-08 14:35:07,485 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 2 [2019-01-08 14:35:07,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:35:07,499 INFO L225 Difference]: With dead ends: 29 [2019-01-08 14:35:07,500 INFO L226 Difference]: Without dead ends: 24 [2019-01-08 14:35:07,503 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:35:07,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2019-01-08 14:35:07,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 14. [2019-01-08 14:35:07,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2019-01-08 14:35:07,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 25 transitions. [2019-01-08 14:35:07,543 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 25 transitions. Word has length 2 [2019-01-08 14:35:07,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:35:07,545 INFO L480 AbstractCegarLoop]: Abstraction has 14 states and 25 transitions. [2019-01-08 14:35:07,545 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-08 14:35:07,545 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 25 transitions. [2019-01-08 14:35:07,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:35:07,546 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:35:07,546 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:35:07,547 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:35:07,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:35:07,547 INFO L82 PathProgramCache]: Analyzing trace with hash 30376, now seen corresponding path program 1 times [2019-01-08 14:35:07,547 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:35:07,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:07,549 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:35:07,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:07,549 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:35:07,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:35:07,898 WARN L181 SmtUtils]: Spent 272.00 ms on a formula simplification. DAG size of input: 19 DAG size of output: 13 [2019-01-08 14:35:07,936 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:35:07,937 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:35:07,937 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:35:07,938 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:35:07,940 INFO L207 CegarAbsIntRunner]: [0], [18], [27] [2019-01-08 14:35:08,004 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:35:08,004 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:35:23,196 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:35:23,198 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:35:23,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:35:23,204 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:35:23,903 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 75% of their original sizes. [2019-01-08 14:35:23,903 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:35:26,266 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_104 Int) (v_idx_115 Int) (v_idx_105 Int) (v_idx_113 Int) (v_idx_103 Int) (v_idx_114 Int) (v_idx_108 Int) (v_idx_109 Int) (v_idx_106 Int) (v_idx_107 Int) (v_idx_111 Int) (v_idx_112 Int) (v_idx_110 Int)) (exists ((v_v_1875_1 Int) (v_v_1876_1 Int) (v_v_1877_1 Int) (v_v_1879_1 Int) (v_v_1869_1 Int) (v_b_159_1 Int) (v_b_158_1 Int) (v_v_1881_1 Int) (v_v_1871_1 Int) (v_v_1873_1 Int) (v_b_153_1 Int) (v_b_152_1 Int) (v_b_151_1 Int) (v_b_150_1 Int) (v_b_157_1 Int) (v_b_156_1 Int)) (let ((.cse6 (+ v_b_150_1 4)) (.cse0 (+ c_ULTIMATE.start_main_p4 2)) (.cse7 (+ v_b_152_1 3)) (.cse8 (+ v_b_158_1 1)) (.cse1 (+ v_b_153_1 2)) (.cse3 (+ v_b_150_1 1)) (.cse10 (+ v_b_151_1 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 5)) (.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse15 (+ c_ULTIMATE.start_main_p1 3)) (.cse4 (+ v_b_156_1 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse12 (+ v_b_150_1 2)) (.cse9 (+ v_b_151_1 3)) (.cse13 (+ c_ULTIMATE.start_main_p4 1)) (.cse14 (+ v_b_152_1 1))) (and (<= .cse0 v_b_157_1) (or (= (select |c_#memory_int| v_idx_103) v_v_1869_1) (<= c_ULTIMATE.start_main_p1 v_idx_103)) (<= (+ v_b_151_1 4) v_b_159_1) (<= .cse1 v_b_158_1) (<= (+ v_b_152_1 2) v_b_156_1) (<= (+ c_ULTIMATE.start_main_p4 3) v_b_159_1) (<= .cse2 v_b_152_1) (<= (+ v_b_150_1 3) v_b_156_1) (<= .cse3 v_b_151_1) (<= .cse4 v_b_158_1) (or (= (select |c_#memory_int| v_idx_109) v_v_1875_1) (<= c_ULTIMATE.start_main_p4 v_idx_109) (< v_idx_109 v_b_153_1)) (<= .cse5 v_b_150_1) (<= v_b_153_1 c_ULTIMATE.start_main_p4) (<= (+ v_b_152_1 4) v_b_159_1) (or (< v_idx_106 v_b_150_1) (<= v_b_151_1 v_idx_106) (= (select |c_#memory_int| v_idx_106) 0)) (<= .cse6 v_b_158_1) (<= (+ v_b_153_1 1) v_b_156_1) (or (= (select |c_#memory_int| v_idx_114) 0) (<= v_b_159_1 v_idx_114) (< v_idx_114 v_b_158_1)) (<= .cse7 v_b_158_1) (<= v_b_159_1 .cse8) (<= .cse9 v_b_158_1) (<= .cse10 v_b_153_1) (<= v_b_157_1 .cse4) (<= .cse11 v_b_157_1) (<= .cse12 c_ULTIMATE.start_main_p4) (<= .cse6 v_b_157_1) (<= .cse0 v_b_158_1) (or (< v_idx_111 .cse13) (= v_v_1877_1 (select |c_#memory_int| v_idx_111)) (<= v_b_156_1 v_idx_111)) (<= v_v_1876_1 0) (<= .cse7 v_b_157_1) (<= v_b_151_1 .cse3) (or (< v_idx_108 v_b_152_1) (= (select |c_#memory_int| v_idx_108) 0) (<= v_b_153_1 v_idx_108)) (or (= (select |c_#memory_int| v_idx_112) 0) (< v_idx_112 v_b_156_1) (<= v_b_157_1 v_idx_112)) (or (= (select |c_#memory_int| v_idx_104) 0) (<= .cse5 v_idx_104) (< v_idx_104 c_ULTIMATE.start_main_p1)) (<= (+ v_b_157_1 1) v_b_159_1) (or (= (select |c_#memory_int| v_idx_113) v_v_1879_1) (< v_idx_113 v_b_157_1) (<= v_b_158_1 v_idx_113)) (<= .cse8 v_b_159_1) (<= .cse1 v_b_157_1) (<= v_b_157_1 v_b_158_1) (<= .cse3 v_b_152_1) (<= .cse10 c_ULTIMATE.start_main_p4) (or (< v_idx_110 c_ULTIMATE.start_main_p4) (<= .cse13 v_idx_110) (= (select |c_#memory_int| v_idx_110) v_v_1876_1)) (<= .cse11 v_b_158_1) (<= .cse14 v_b_153_1) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_1) (<= (+ v_b_153_1 3) v_b_159_1) (<= .cse2 v_b_151_1) (or (<= v_b_152_1 v_idx_107) (= (select |c_#memory_int| v_idx_107) v_v_1873_1) (< v_idx_107 v_b_151_1)) (<= (+ v_b_151_1 2) v_b_156_1) (<= .cse15 c_ULTIMATE.start_main_p4) (<= (* 2 v_v_1876_1) 0) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_156_1) (<= .cse15 v_b_153_1) (<= v_b_151_1 v_b_152_1) (<= (+ v_b_150_1 5) v_b_159_1) (or (< v_idx_115 v_b_159_1) (= (select |c_#memory_int| v_idx_115) v_v_1881_1)) (<= .cse4 v_b_157_1) (<= (+ v_b_156_1 2) v_b_159_1) (or (< v_idx_105 .cse5) (<= v_b_150_1 v_idx_105) (= (select |c_#memory_int| v_idx_105) v_v_1871_1)) (<= .cse14 c_ULTIMATE.start_main_p4) (<= .cse12 v_b_153_1) (<= .cse9 v_b_157_1) (<= .cse13 v_b_156_1) (<= v_b_153_1 .cse14))))) is different from false [2019-01-08 14:35:28,675 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_126 Int) (v_idx_127 Int) (v_idx_116 Int) (v_idx_124 Int) (v_idx_125 Int) (v_idx_119 Int) (v_idx_128 Int) (v_idx_117 Int) (v_idx_118 Int) (v_idx_122 Int) (v_idx_123 Int) (v_idx_120 Int) (v_idx_121 Int)) (exists ((v_v_1875_1 Int) (v_v_1876_1 Int) (v_v_1877_1 Int) (v_v_1879_1 Int) (v_v_1869_1 Int) (v_b_159_1 Int) (v_b_158_1 Int) (v_v_1881_1 Int) (v_v_1871_1 Int) (v_v_1873_1 Int) (v_b_153_1 Int) (v_b_152_1 Int) (v_b_151_1 Int) (v_b_150_1 Int) (v_b_157_1 Int) (v_b_156_1 Int) (v_b_155_1 Int) (v_b_154_1 Int)) (let ((.cse1 (+ v_b_152_1 2)) (.cse11 (+ v_b_150_1 4)) (.cse9 (+ c_ULTIMATE.start_main_p1 1)) (.cse13 (+ v_b_152_1 3)) (.cse16 (+ v_b_151_1 1)) (.cse5 (+ v_b_150_1 3)) (.cse14 (+ v_b_158_1 1)) (.cse0 (+ v_b_153_1 2)) (.cse7 (+ v_b_150_1 1)) (.cse17 (+ c_ULTIMATE.start_main_p1 5)) (.cse3 (+ v_b_154_1 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 2)) (.cse18 (+ v_b_155_1 1)) (.cse20 (+ v_b_151_1 2)) (.cse2 (+ c_ULTIMATE.start_main_p1 4)) (.cse8 (+ v_b_156_1 1)) (.cse10 (+ v_b_150_1 2)) (.cse15 (+ v_b_151_1 3)) (.cse21 (+ c_ULTIMATE.start_main_p1 3)) (.cse6 (+ v_b_154_1 1)) (.cse19 (+ v_b_152_1 1)) (.cse12 (+ v_b_153_1 1))) (and (or (= (select |c_#memory_int| v_idx_124) v_v_1877_1) (<= v_b_156_1 v_idx_124) (< v_idx_124 v_b_155_1)) (<= (+ v_b_151_1 4) v_b_159_1) (<= .cse0 v_b_158_1) (<= .cse1 v_b_156_1) (or (= (select |c_#memory_int| v_idx_119) 0) (<= v_b_151_1 v_idx_119) (< v_idx_119 v_b_150_1)) (<= .cse2 v_b_155_1) (<= .cse3 v_b_157_1) (<= .cse4 v_b_152_1) (<= .cse5 v_b_156_1) (<= .cse6 v_b_156_1) (<= .cse7 v_b_151_1) (<= .cse8 v_b_158_1) (or (< v_idx_117 c_ULTIMATE.start_main_p1) (<= .cse9 v_idx_117) (= (select |c_#memory_int| v_idx_117) 0)) (<= .cse9 v_b_150_1) (<= (+ v_b_152_1 4) v_b_159_1) (<= .cse10 v_b_154_1) (<= .cse1 v_b_155_1) (<= .cse11 v_b_158_1) (<= .cse12 v_b_156_1) (<= .cse13 v_b_158_1) (<= v_b_159_1 .cse14) (<= .cse15 v_b_158_1) (<= .cse16 v_b_153_1) (<= v_b_157_1 .cse8) (<= .cse17 v_b_157_1) (<= .cse11 v_b_157_1) (or (< v_idx_127 v_b_158_1) (= (select |c_#memory_int| v_idx_127) 0) (<= v_b_159_1 v_idx_127)) (or (= (select |c_#memory_int| v_idx_118) v_v_1871_1) (< v_idx_118 .cse9) (<= v_b_150_1 v_idx_118)) (<= (+ v_b_155_1 2) v_b_159_1) (<= v_v_1876_1 0) (<= .cse13 v_b_157_1) (<= v_b_151_1 .cse7) (or (< v_idx_122 v_b_153_1) (= (select |c_#memory_int| v_idx_122) v_v_1875_1) (<= v_b_154_1 v_idx_122)) (<= .cse16 v_b_154_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_116) (= (select |c_#memory_int| v_idx_116) v_v_1869_1)) (<= .cse5 v_b_155_1) (<= (+ v_b_157_1 1) v_b_159_1) (<= .cse14 v_b_159_1) (<= .cse0 v_b_157_1) (<= v_b_157_1 v_b_158_1) (<= .cse7 v_b_152_1) (<= .cse18 v_b_157_1) (or (<= v_b_152_1 v_idx_120) (< v_idx_120 v_b_151_1) (= (select |c_#memory_int| v_idx_120) v_v_1873_1)) (<= .cse17 v_b_158_1) (<= .cse3 v_b_158_1) (<= .cse19 v_b_153_1) (<= (+ v_b_154_1 3) v_b_159_1) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_1) (<= .cse20 v_b_155_1) (or (< v_idx_128 v_b_159_1) (= (select |c_#memory_int| v_idx_128) v_v_1881_1)) (<= (+ v_b_153_1 3) v_b_159_1) (<= .cse4 v_b_151_1) (<= .cse18 v_b_158_1) (<= .cse20 v_b_156_1) (<= (* 2 v_v_1876_1) 0) (<= .cse2 v_b_156_1) (<= .cse21 v_b_153_1) (<= v_b_151_1 v_b_152_1) (<= v_b_155_1 .cse6) (<= (+ v_b_150_1 5) v_b_159_1) (<= .cse8 v_b_157_1) (<= (+ v_b_156_1 2) v_b_159_1) (<= .cse19 v_b_154_1) (or (= (select |c_#memory_int| v_idx_123) v_v_1876_1) (<= v_b_155_1 v_idx_123) (< v_idx_123 v_b_154_1)) (or (< v_idx_125 v_b_156_1) (<= v_b_157_1 v_idx_125) (= 0 (select |c_#memory_int| v_idx_125))) (or (<= v_b_153_1 v_idx_121) (< v_idx_121 v_b_152_1) (= 0 (select |c_#memory_int| v_idx_121))) (<= .cse10 v_b_153_1) (or (< v_idx_126 v_b_157_1) (<= v_b_158_1 v_idx_126) (= (select |c_#memory_int| v_idx_126) v_v_1879_1)) (<= .cse15 v_b_157_1) (<= .cse21 v_b_154_1) (<= .cse6 v_b_155_1) (<= v_b_155_1 v_b_156_1) (<= v_b_153_1 v_b_154_1) (<= v_b_153_1 .cse19) (<= .cse12 v_b_155_1))))) is different from false [2019-01-08 14:35:28,851 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:35:28,852 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:35:28,852 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:35:28,853 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:35:28,853 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:35:28,855 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:35:28,855 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:35:28,855 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-08 14:35:28,856 INFO L87 Difference]: Start difference. First operand 14 states and 25 transitions. Second operand 4 states. [2019-01-08 14:35:31,432 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_126 Int) (v_idx_127 Int) (v_idx_116 Int) (v_idx_124 Int) (v_idx_125 Int) (v_idx_119 Int) (v_idx_128 Int) (v_idx_117 Int) (v_idx_118 Int) (v_idx_122 Int) (v_idx_123 Int) (v_idx_120 Int) (v_idx_121 Int)) (exists ((v_v_1875_1 Int) (v_v_1876_1 Int) (v_v_1877_1 Int) (v_v_1879_1 Int) (v_v_1869_1 Int) (v_b_159_1 Int) (v_b_158_1 Int) (v_v_1881_1 Int) (v_v_1871_1 Int) (v_v_1873_1 Int) (v_b_153_1 Int) (v_b_152_1 Int) (v_b_151_1 Int) (v_b_150_1 Int) (v_b_157_1 Int) (v_b_156_1 Int) (v_b_155_1 Int) (v_b_154_1 Int)) (let ((.cse1 (+ v_b_152_1 2)) (.cse11 (+ v_b_150_1 4)) (.cse9 (+ c_ULTIMATE.start_main_p1 1)) (.cse13 (+ v_b_152_1 3)) (.cse16 (+ v_b_151_1 1)) (.cse5 (+ v_b_150_1 3)) (.cse14 (+ v_b_158_1 1)) (.cse0 (+ v_b_153_1 2)) (.cse7 (+ v_b_150_1 1)) (.cse17 (+ c_ULTIMATE.start_main_p1 5)) (.cse3 (+ v_b_154_1 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 2)) (.cse18 (+ v_b_155_1 1)) (.cse20 (+ v_b_151_1 2)) (.cse2 (+ c_ULTIMATE.start_main_p1 4)) (.cse8 (+ v_b_156_1 1)) (.cse10 (+ v_b_150_1 2)) (.cse15 (+ v_b_151_1 3)) (.cse21 (+ c_ULTIMATE.start_main_p1 3)) (.cse6 (+ v_b_154_1 1)) (.cse19 (+ v_b_152_1 1)) (.cse12 (+ v_b_153_1 1))) (and (or (= (select |c_#memory_int| v_idx_124) v_v_1877_1) (<= v_b_156_1 v_idx_124) (< v_idx_124 v_b_155_1)) (<= (+ v_b_151_1 4) v_b_159_1) (<= .cse0 v_b_158_1) (<= .cse1 v_b_156_1) (or (= (select |c_#memory_int| v_idx_119) 0) (<= v_b_151_1 v_idx_119) (< v_idx_119 v_b_150_1)) (<= .cse2 v_b_155_1) (<= .cse3 v_b_157_1) (<= .cse4 v_b_152_1) (<= .cse5 v_b_156_1) (<= .cse6 v_b_156_1) (<= .cse7 v_b_151_1) (<= .cse8 v_b_158_1) (or (< v_idx_117 c_ULTIMATE.start_main_p1) (<= .cse9 v_idx_117) (= (select |c_#memory_int| v_idx_117) 0)) (<= .cse9 v_b_150_1) (<= (+ v_b_152_1 4) v_b_159_1) (<= .cse10 v_b_154_1) (<= .cse1 v_b_155_1) (<= .cse11 v_b_158_1) (<= .cse12 v_b_156_1) (<= .cse13 v_b_158_1) (<= v_b_159_1 .cse14) (<= .cse15 v_b_158_1) (<= .cse16 v_b_153_1) (<= v_b_157_1 .cse8) (<= .cse17 v_b_157_1) (<= .cse11 v_b_157_1) (or (< v_idx_127 v_b_158_1) (= (select |c_#memory_int| v_idx_127) 0) (<= v_b_159_1 v_idx_127)) (or (= (select |c_#memory_int| v_idx_118) v_v_1871_1) (< v_idx_118 .cse9) (<= v_b_150_1 v_idx_118)) (<= (+ v_b_155_1 2) v_b_159_1) (<= v_v_1876_1 0) (<= .cse13 v_b_157_1) (<= v_b_151_1 .cse7) (or (< v_idx_122 v_b_153_1) (= (select |c_#memory_int| v_idx_122) v_v_1875_1) (<= v_b_154_1 v_idx_122)) (<= .cse16 v_b_154_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_116) (= (select |c_#memory_int| v_idx_116) v_v_1869_1)) (<= .cse5 v_b_155_1) (<= (+ v_b_157_1 1) v_b_159_1) (<= .cse14 v_b_159_1) (<= .cse0 v_b_157_1) (<= v_b_157_1 v_b_158_1) (<= .cse7 v_b_152_1) (<= .cse18 v_b_157_1) (or (<= v_b_152_1 v_idx_120) (< v_idx_120 v_b_151_1) (= (select |c_#memory_int| v_idx_120) v_v_1873_1)) (<= .cse17 v_b_158_1) (<= .cse3 v_b_158_1) (<= .cse19 v_b_153_1) (<= (+ v_b_154_1 3) v_b_159_1) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_1) (<= .cse20 v_b_155_1) (or (< v_idx_128 v_b_159_1) (= (select |c_#memory_int| v_idx_128) v_v_1881_1)) (<= (+ v_b_153_1 3) v_b_159_1) (<= .cse4 v_b_151_1) (<= .cse18 v_b_158_1) (<= .cse20 v_b_156_1) (<= (* 2 v_v_1876_1) 0) (<= .cse2 v_b_156_1) (<= .cse21 v_b_153_1) (<= v_b_151_1 v_b_152_1) (<= v_b_155_1 .cse6) (<= (+ v_b_150_1 5) v_b_159_1) (<= .cse8 v_b_157_1) (<= (+ v_b_156_1 2) v_b_159_1) (<= .cse19 v_b_154_1) (or (= (select |c_#memory_int| v_idx_123) v_v_1876_1) (<= v_b_155_1 v_idx_123) (< v_idx_123 v_b_154_1)) (or (< v_idx_125 v_b_156_1) (<= v_b_157_1 v_idx_125) (= 0 (select |c_#memory_int| v_idx_125))) (or (<= v_b_153_1 v_idx_121) (< v_idx_121 v_b_152_1) (= 0 (select |c_#memory_int| v_idx_121))) (<= .cse10 v_b_153_1) (or (< v_idx_126 v_b_157_1) (<= v_b_158_1 v_idx_126) (= (select |c_#memory_int| v_idx_126) v_v_1879_1)) (<= .cse15 v_b_157_1) (<= .cse21 v_b_154_1) (<= .cse6 v_b_155_1) (<= v_b_155_1 v_b_156_1) (<= v_b_153_1 v_b_154_1) (<= v_b_153_1 .cse19) (<= .cse12 v_b_155_1))))) (forall ((v_idx_104 Int) (v_idx_115 Int) (v_idx_105 Int) (v_idx_113 Int) (v_idx_103 Int) (v_idx_114 Int) (v_idx_108 Int) (v_idx_109 Int) (v_idx_106 Int) (v_idx_107 Int) (v_idx_111 Int) (v_idx_112 Int) (v_idx_110 Int)) (exists ((v_v_1875_1 Int) (v_v_1876_1 Int) (v_v_1877_1 Int) (v_v_1879_1 Int) (v_v_1869_1 Int) (v_b_159_1 Int) (v_b_158_1 Int) (v_v_1881_1 Int) (v_v_1871_1 Int) (v_v_1873_1 Int) (v_b_153_1 Int) (v_b_152_1 Int) (v_b_151_1 Int) (v_b_150_1 Int) (v_b_157_1 Int) (v_b_156_1 Int)) (let ((.cse28 (+ v_b_150_1 4)) (.cse22 (+ c_ULTIMATE.start_main_p4 2)) (.cse29 (+ v_b_152_1 3)) (.cse30 (+ v_b_158_1 1)) (.cse23 (+ v_b_153_1 2)) (.cse25 (+ v_b_150_1 1)) (.cse32 (+ v_b_151_1 1)) (.cse33 (+ c_ULTIMATE.start_main_p1 5)) (.cse24 (+ c_ULTIMATE.start_main_p1 2)) (.cse37 (+ c_ULTIMATE.start_main_p1 3)) (.cse26 (+ v_b_156_1 1)) (.cse27 (+ c_ULTIMATE.start_main_p1 1)) (.cse34 (+ v_b_150_1 2)) (.cse31 (+ v_b_151_1 3)) (.cse35 (+ c_ULTIMATE.start_main_p4 1)) (.cse36 (+ v_b_152_1 1))) (and (<= .cse22 v_b_157_1) (or (= (select |c_#memory_int| v_idx_103) v_v_1869_1) (<= c_ULTIMATE.start_main_p1 v_idx_103)) (<= (+ v_b_151_1 4) v_b_159_1) (<= .cse23 v_b_158_1) (<= (+ v_b_152_1 2) v_b_156_1) (<= (+ c_ULTIMATE.start_main_p4 3) v_b_159_1) (<= .cse24 v_b_152_1) (<= (+ v_b_150_1 3) v_b_156_1) (<= .cse25 v_b_151_1) (<= .cse26 v_b_158_1) (or (= (select |c_#memory_int| v_idx_109) v_v_1875_1) (<= c_ULTIMATE.start_main_p4 v_idx_109) (< v_idx_109 v_b_153_1)) (<= .cse27 v_b_150_1) (<= v_b_153_1 c_ULTIMATE.start_main_p4) (<= (+ v_b_152_1 4) v_b_159_1) (or (< v_idx_106 v_b_150_1) (<= v_b_151_1 v_idx_106) (= (select |c_#memory_int| v_idx_106) 0)) (<= .cse28 v_b_158_1) (<= (+ v_b_153_1 1) v_b_156_1) (or (= (select |c_#memory_int| v_idx_114) 0) (<= v_b_159_1 v_idx_114) (< v_idx_114 v_b_158_1)) (<= .cse29 v_b_158_1) (<= v_b_159_1 .cse30) (<= .cse31 v_b_158_1) (<= .cse32 v_b_153_1) (<= v_b_157_1 .cse26) (<= .cse33 v_b_157_1) (<= .cse34 c_ULTIMATE.start_main_p4) (<= .cse28 v_b_157_1) (<= .cse22 v_b_158_1) (or (< v_idx_111 .cse35) (= v_v_1877_1 (select |c_#memory_int| v_idx_111)) (<= v_b_156_1 v_idx_111)) (<= v_v_1876_1 0) (<= .cse29 v_b_157_1) (<= v_b_151_1 .cse25) (or (< v_idx_108 v_b_152_1) (= (select |c_#memory_int| v_idx_108) 0) (<= v_b_153_1 v_idx_108)) (or (= (select |c_#memory_int| v_idx_112) 0) (< v_idx_112 v_b_156_1) (<= v_b_157_1 v_idx_112)) (or (= (select |c_#memory_int| v_idx_104) 0) (<= .cse27 v_idx_104) (< v_idx_104 c_ULTIMATE.start_main_p1)) (<= (+ v_b_157_1 1) v_b_159_1) (or (= (select |c_#memory_int| v_idx_113) v_v_1879_1) (< v_idx_113 v_b_157_1) (<= v_b_158_1 v_idx_113)) (<= .cse30 v_b_159_1) (<= .cse23 v_b_157_1) (<= v_b_157_1 v_b_158_1) (<= .cse25 v_b_152_1) (<= .cse32 c_ULTIMATE.start_main_p4) (or (< v_idx_110 c_ULTIMATE.start_main_p4) (<= .cse35 v_idx_110) (= (select |c_#memory_int| v_idx_110) v_v_1876_1)) (<= .cse33 v_b_158_1) (<= .cse36 v_b_153_1) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_1) (<= (+ v_b_153_1 3) v_b_159_1) (<= .cse24 v_b_151_1) (or (<= v_b_152_1 v_idx_107) (= (select |c_#memory_int| v_idx_107) v_v_1873_1) (< v_idx_107 v_b_151_1)) (<= (+ v_b_151_1 2) v_b_156_1) (<= .cse37 c_ULTIMATE.start_main_p4) (<= (* 2 v_v_1876_1) 0) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_156_1) (<= .cse37 v_b_153_1) (<= v_b_151_1 v_b_152_1) (<= (+ v_b_150_1 5) v_b_159_1) (or (< v_idx_115 v_b_159_1) (= (select |c_#memory_int| v_idx_115) v_v_1881_1)) (<= .cse26 v_b_157_1) (<= (+ v_b_156_1 2) v_b_159_1) (or (< v_idx_105 .cse27) (<= v_b_150_1 v_idx_105) (= (select |c_#memory_int| v_idx_105) v_v_1871_1)) (<= .cse36 c_ULTIMATE.start_main_p4) (<= .cse34 v_b_153_1) (<= .cse31 v_b_157_1) (<= .cse35 v_b_156_1) (<= v_b_153_1 .cse36)))))) is different from false [2019-01-08 14:36:07,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:36:07,727 INFO L93 Difference]: Finished difference Result 16 states and 33 transitions. [2019-01-08 14:36:07,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-08 14:36:07,728 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-08 14:36:07,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:36:07,729 INFO L225 Difference]: With dead ends: 16 [2019-01-08 14:36:07,729 INFO L226 Difference]: Without dead ends: 15 [2019-01-08 14:36:07,731 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.2s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:36:07,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states. [2019-01-08 14:36:07,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2019-01-08 14:36:07,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-08 14:36:07,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 32 transitions. [2019-01-08 14:36:07,745 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 32 transitions. Word has length 3 [2019-01-08 14:36:07,745 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:36:07,746 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 32 transitions. [2019-01-08 14:36:07,747 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:36:07,747 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 32 transitions. [2019-01-08 14:36:07,748 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:36:07,748 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:36:07,748 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:36:07,749 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:36:07,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:36:07,750 INFO L82 PathProgramCache]: Analyzing trace with hash 30004, now seen corresponding path program 1 times [2019-01-08 14:36:07,750 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:36:07,754 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:36:07,754 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:36:07,754 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:36:07,755 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:36:07,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:36:07,862 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:36:07,863 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:36:07,863 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:36:07,863 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:36:07,863 INFO L207 CegarAbsIntRunner]: [0], [6], [27] [2019-01-08 14:36:07,869 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:36:07,869 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:36:19,822 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:36:19,822 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:36:19,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:36:19,823 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:36:20,323 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 80% of their original sizes. [2019-01-08 14:36:20,323 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:36:22,847 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_236 Int) (v_idx_237 Int) (v_idx_234 Int) (v_idx_235 Int) (v_idx_238 Int) (v_idx_239 Int) (v_idx_240 Int) (v_idx_243 Int) (v_idx_232 Int) (v_idx_233 Int) (v_idx_241 Int) (v_idx_242 Int) (v_idx_231 Int)) (exists ((v_v_1831_2 Int) (v_v_1835_2 Int) (v_v_1833_2 Int) (v_b_159_2 Int) (v_b_158_2 Int) (v_b_157_2 Int) (v_b_152_2 Int) (v_b_151_2 Int) (v_b_150_2 Int) (v_b_156_2 Int) (v_b_155_2 Int) (v_b_154_2 Int) (v_b_153_2 Int) (v_v_1839_2 Int) (v_v_1828_2 Int) (v_v_1829_2 Int) (v_v_1837_2 Int) (v_v_1827_2 Int)) (let ((.cse4 (+ v_b_158_2 1)) (.cse12 (+ v_b_151_2 3)) (.cse1 (+ c_ULTIMATE.start_main_p1 5)) (.cse8 (+ c_ULTIMATE.start_main_p1 2)) (.cse11 (+ c_ULTIMATE.start_main_p1 3)) (.cse14 (+ v_b_153_2 1)) (.cse0 (+ v_b_150_2 3)) (.cse13 (+ c_ULTIMATE.start_main_p1 4)) (.cse6 (+ v_b_151_2 2)) (.cse9 (+ v_b_150_2 4)) (.cse15 (+ v_b_152_2 3)) (.cse2 (+ v_b_152_2 1)) (.cse5 (+ v_b_150_2 1)) (.cse18 (+ v_b_153_2 2)) (.cse20 (+ v_b_152_2 2)) (.cse3 (+ v_b_154_2 2)) (.cse19 (+ c_ULTIMATE.start_main_p1 1)) (.cse17 (+ v_b_154_2 1)) (.cse21 (+ v_b_150_2 2)) (.cse10 (+ v_b_156_2 1)) (.cse16 (+ v_b_151_2 1)) (.cse7 (+ v_b_155_2 1))) (and (<= .cse0 v_b_156_2) (<= .cse1 v_b_158_2) (or (< v_idx_240 v_b_156_2) (= 0 (select |c_#memory_int| v_idx_240)) (<= v_b_157_2 v_idx_240)) (<= .cse2 v_b_153_2) (<= .cse3 v_b_158_2) (<= .cse4 v_b_159_2) (<= .cse5 v_b_151_2) (or (< v_idx_237 v_b_153_2) (= (select |c_#memory_int| v_idx_237) v_v_1833_2) (<= v_b_154_2 v_idx_237)) (<= .cse6 v_b_156_2) (<= v_b_159_2 .cse4) (<= v_b_157_2 v_b_158_2) (<= .cse7 v_b_157_2) (<= (+ v_b_150_2 5) v_b_159_2) (<= .cse8 v_b_152_2) (<= .cse9 v_b_158_2) (<= (+ v_b_155_2 2) v_b_159_2) (or (< v_idx_236 v_b_152_2) (= (select |c_#memory_int| v_idx_236) 0) (<= v_b_153_2 v_idx_236)) (<= v_b_157_2 .cse10) (<= v_b_153_2 v_b_154_2) (<= .cse11 v_b_154_2) (<= .cse12 v_b_157_2) (or (< v_idx_234 v_b_150_2) (<= v_b_151_2 v_idx_234) (= 0 (select |c_#memory_int| v_idx_234))) (<= v_b_151_2 .cse5) (<= .cse13 v_b_155_2) (<= .cse12 v_b_158_2) (<= .cse1 v_b_157_2) (or (< v_idx_243 v_b_159_2) (= (select |c_#memory_int| v_idx_243) v_v_1839_2)) (or (<= v_b_152_2 v_idx_235) (< v_idx_235 v_b_151_2) (= (select |c_#memory_int| v_idx_235) v_v_1831_2)) (<= .cse14 v_b_156_2) (<= .cse8 v_b_151_2) (or (<= v_b_155_2 v_idx_238) (< v_idx_238 v_b_154_2) (= 0 (select |c_#memory_int| v_idx_238))) (<= .cse15 v_b_158_2) (<= 0 v_v_1828_2) (<= .cse16 v_b_153_2) (<= v_b_153_2 .cse2) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_2) (<= .cse11 v_b_153_2) (<= .cse17 v_b_155_2) (<= .cse14 v_b_155_2) (<= (+ v_b_151_2 4) v_b_159_2) (<= .cse18 v_b_158_2) (<= (+ v_b_154_2 3) v_b_159_2) (<= (+ v_b_156_2 2) v_b_159_2) (<= 0 (* 2 v_v_1828_2)) (<= .cse0 v_b_155_2) (<= v_b_155_2 v_b_156_2) (<= .cse13 v_b_156_2) (<= (+ v_b_153_2 3) v_b_159_2) (<= .cse6 v_b_155_2) (<= .cse9 v_b_157_2) (<= .cse15 v_b_157_2) (<= .cse19 v_b_150_2) (or (<= v_b_159_2 v_idx_242) (= 0 (select |c_#memory_int| v_idx_242)) (< v_idx_242 v_b_158_2)) (<= .cse2 v_b_154_2) (or (< v_idx_232 c_ULTIMATE.start_main_p1) (<= .cse19 v_idx_232) (= (select |c_#memory_int| v_idx_232) v_v_1828_2)) (<= .cse5 v_b_152_2) (<= (+ v_b_157_2 1) v_b_159_2) (<= .cse10 v_b_157_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_231) (= (select |c_#memory_int| v_idx_231) v_v_1827_2)) (<= .cse18 v_b_157_2) (<= .cse20 v_b_156_2) (<= .cse20 v_b_155_2) (<= .cse21 v_b_153_2) (<= .cse3 v_b_157_2) (or (<= v_b_150_2 v_idx_233) (= (select |c_#memory_int| v_idx_233) v_v_1829_2) (< v_idx_233 .cse19)) (or (< v_idx_241 v_b_157_2) (= (select |c_#memory_int| v_idx_241) v_v_1837_2) (<= v_b_158_2 v_idx_241)) (or (< v_idx_239 v_b_155_2) (<= v_b_156_2 v_idx_239) (= (select |c_#memory_int| v_idx_239) v_v_1835_2)) (<= (+ v_b_152_2 4) v_b_159_2) (<= v_b_155_2 .cse17) (<= .cse17 v_b_156_2) (<= .cse21 v_b_154_2) (<= .cse10 v_b_158_2) (<= v_b_151_2 v_b_152_2) (<= .cse16 v_b_154_2) (<= .cse7 v_b_158_2))))) is different from false [2019-01-08 14:36:24,862 WARN L860 $PredicateComparison]: unable to prove that (forall ((v_idx_236 Int) (v_idx_237 Int) (v_idx_234 Int) (v_idx_235 Int) (v_idx_238 Int) (v_idx_239 Int) (v_idx_240 Int) (v_idx_243 Int) (v_idx_232 Int) (v_idx_233 Int) (v_idx_241 Int) (v_idx_242 Int) (v_idx_231 Int)) (exists ((v_v_1831_2 Int) (v_v_1835_2 Int) (v_v_1833_2 Int) (v_b_159_2 Int) (v_b_158_2 Int) (v_b_157_2 Int) (v_b_152_2 Int) (v_b_151_2 Int) (v_b_150_2 Int) (v_b_156_2 Int) (v_b_155_2 Int) (v_b_154_2 Int) (v_b_153_2 Int) (v_v_1839_2 Int) (v_v_1828_2 Int) (v_v_1829_2 Int) (v_v_1837_2 Int) (v_v_1827_2 Int)) (let ((.cse4 (+ v_b_158_2 1)) (.cse12 (+ v_b_151_2 3)) (.cse1 (+ c_ULTIMATE.start_main_p1 5)) (.cse8 (+ c_ULTIMATE.start_main_p1 2)) (.cse11 (+ c_ULTIMATE.start_main_p1 3)) (.cse14 (+ v_b_153_2 1)) (.cse0 (+ v_b_150_2 3)) (.cse13 (+ c_ULTIMATE.start_main_p1 4)) (.cse6 (+ v_b_151_2 2)) (.cse9 (+ v_b_150_2 4)) (.cse15 (+ v_b_152_2 3)) (.cse2 (+ v_b_152_2 1)) (.cse5 (+ v_b_150_2 1)) (.cse18 (+ v_b_153_2 2)) (.cse20 (+ v_b_152_2 2)) (.cse3 (+ v_b_154_2 2)) (.cse19 (+ c_ULTIMATE.start_main_p1 1)) (.cse17 (+ v_b_154_2 1)) (.cse21 (+ v_b_150_2 2)) (.cse10 (+ v_b_156_2 1)) (.cse16 (+ v_b_151_2 1)) (.cse7 (+ v_b_155_2 1))) (and (<= .cse0 v_b_156_2) (<= .cse1 v_b_158_2) (or (< v_idx_240 v_b_156_2) (= 0 (select |c_#memory_int| v_idx_240)) (<= v_b_157_2 v_idx_240)) (<= .cse2 v_b_153_2) (<= .cse3 v_b_158_2) (<= .cse4 v_b_159_2) (<= .cse5 v_b_151_2) (or (< v_idx_237 v_b_153_2) (= (select |c_#memory_int| v_idx_237) v_v_1833_2) (<= v_b_154_2 v_idx_237)) (<= .cse6 v_b_156_2) (<= v_b_159_2 .cse4) (<= v_b_157_2 v_b_158_2) (<= .cse7 v_b_157_2) (<= (+ v_b_150_2 5) v_b_159_2) (<= .cse8 v_b_152_2) (<= .cse9 v_b_158_2) (<= (+ v_b_155_2 2) v_b_159_2) (or (< v_idx_236 v_b_152_2) (= (select |c_#memory_int| v_idx_236) 0) (<= v_b_153_2 v_idx_236)) (<= v_b_157_2 .cse10) (<= v_b_153_2 v_b_154_2) (<= .cse11 v_b_154_2) (<= .cse12 v_b_157_2) (or (< v_idx_234 v_b_150_2) (<= v_b_151_2 v_idx_234) (= 0 (select |c_#memory_int| v_idx_234))) (<= v_b_151_2 .cse5) (<= .cse13 v_b_155_2) (<= .cse12 v_b_158_2) (<= .cse1 v_b_157_2) (or (< v_idx_243 v_b_159_2) (= (select |c_#memory_int| v_idx_243) v_v_1839_2)) (or (<= v_b_152_2 v_idx_235) (< v_idx_235 v_b_151_2) (= (select |c_#memory_int| v_idx_235) v_v_1831_2)) (<= .cse14 v_b_156_2) (<= .cse8 v_b_151_2) (or (<= v_b_155_2 v_idx_238) (< v_idx_238 v_b_154_2) (= 0 (select |c_#memory_int| v_idx_238))) (<= .cse15 v_b_158_2) (<= 0 v_v_1828_2) (<= .cse16 v_b_153_2) (<= v_b_153_2 .cse2) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_2) (<= .cse11 v_b_153_2) (<= .cse17 v_b_155_2) (<= .cse14 v_b_155_2) (<= (+ v_b_151_2 4) v_b_159_2) (<= .cse18 v_b_158_2) (<= (+ v_b_154_2 3) v_b_159_2) (<= (+ v_b_156_2 2) v_b_159_2) (<= 0 (* 2 v_v_1828_2)) (<= .cse0 v_b_155_2) (<= v_b_155_2 v_b_156_2) (<= .cse13 v_b_156_2) (<= (+ v_b_153_2 3) v_b_159_2) (<= .cse6 v_b_155_2) (<= .cse9 v_b_157_2) (<= .cse15 v_b_157_2) (<= .cse19 v_b_150_2) (or (<= v_b_159_2 v_idx_242) (= 0 (select |c_#memory_int| v_idx_242)) (< v_idx_242 v_b_158_2)) (<= .cse2 v_b_154_2) (or (< v_idx_232 c_ULTIMATE.start_main_p1) (<= .cse19 v_idx_232) (= (select |c_#memory_int| v_idx_232) v_v_1828_2)) (<= .cse5 v_b_152_2) (<= (+ v_b_157_2 1) v_b_159_2) (<= .cse10 v_b_157_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_231) (= (select |c_#memory_int| v_idx_231) v_v_1827_2)) (<= .cse18 v_b_157_2) (<= .cse20 v_b_156_2) (<= .cse20 v_b_155_2) (<= .cse21 v_b_153_2) (<= .cse3 v_b_157_2) (or (<= v_b_150_2 v_idx_233) (= (select |c_#memory_int| v_idx_233) v_v_1829_2) (< v_idx_233 .cse19)) (or (< v_idx_241 v_b_157_2) (= (select |c_#memory_int| v_idx_241) v_v_1837_2) (<= v_b_158_2 v_idx_241)) (or (< v_idx_239 v_b_155_2) (<= v_b_156_2 v_idx_239) (= (select |c_#memory_int| v_idx_239) v_v_1835_2)) (<= (+ v_b_152_2 4) v_b_159_2) (<= v_b_155_2 .cse17) (<= .cse17 v_b_156_2) (<= .cse21 v_b_154_2) (<= .cse10 v_b_158_2) (<= v_b_151_2 v_b_152_2) (<= .cse16 v_b_154_2) (<= .cse7 v_b_158_2))))) is different from true [2019-01-08 14:36:27,367 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_247 Int) (v_idx_248 Int) (v_idx_245 Int) (v_idx_256 Int) (v_idx_246 Int) (v_idx_249 Int) (v_idx_250 Int) (v_idx_251 Int) (v_idx_254 Int) (v_idx_244 Int) (v_idx_255 Int) (v_idx_252 Int) (v_idx_253 Int)) (exists ((v_v_1831_2 Int) (v_v_1835_2 Int) (v_v_1833_2 Int) (v_b_159_2 Int) (v_b_158_2 Int) (v_b_157_2 Int) (v_b_152_2 Int) (v_b_151_2 Int) (v_b_150_2 Int) (v_b_156_2 Int) (v_b_155_2 Int) (v_b_154_2 Int) (v_b_153_2 Int) (v_v_1828_2 Int) (v_v_1839_2 Int) (v_v_1829_2 Int) (v_v_1837_2 Int) (v_v_1827_2 Int)) (let ((.cse4 (+ v_b_158_2 1)) (.cse13 (+ v_b_151_2 3)) (.cse1 (+ c_ULTIMATE.start_main_p1 5)) (.cse8 (+ c_ULTIMATE.start_main_p1 2)) (.cse12 (+ c_ULTIMATE.start_main_p1 3)) (.cse15 (+ v_b_153_2 1)) (.cse0 (+ v_b_150_2 3)) (.cse14 (+ c_ULTIMATE.start_main_p1 4)) (.cse6 (+ v_b_151_2 2)) (.cse9 (+ v_b_150_2 4)) (.cse16 (+ v_b_152_2 3)) (.cse10 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ v_b_152_2 1)) (.cse5 (+ v_b_150_2 1)) (.cse19 (+ v_b_153_2 2)) (.cse20 (+ v_b_152_2 2)) (.cse3 (+ v_b_154_2 2)) (.cse18 (+ v_b_154_2 1)) (.cse21 (+ v_b_150_2 2)) (.cse11 (+ v_b_156_2 1)) (.cse17 (+ v_b_151_2 1)) (.cse7 (+ v_b_155_2 1))) (and (<= .cse0 v_b_156_2) (<= .cse1 v_b_158_2) (<= .cse2 v_b_153_2) (<= .cse3 v_b_158_2) (<= .cse4 v_b_159_2) (<= .cse5 v_b_151_2) (<= .cse6 v_b_156_2) (<= v_b_159_2 .cse4) (<= v_b_157_2 v_b_158_2) (<= .cse7 v_b_157_2) (<= (+ v_b_150_2 5) v_b_159_2) (<= .cse8 v_b_152_2) (<= .cse9 v_b_158_2) (<= (+ v_b_155_2 2) v_b_159_2) (or (<= v_b_156_2 v_idx_252) (= (select |c_#memory_int| v_idx_252) v_v_1835_2) (< v_idx_252 v_b_155_2)) (or (< v_idx_245 c_ULTIMATE.start_main_p1) (<= .cse10 v_idx_245) (= (select |c_#memory_int| v_idx_245) v_v_1828_2)) (or (< v_idx_254 v_b_157_2) (= (select |c_#memory_int| v_idx_254) v_v_1837_2) (<= v_b_158_2 v_idx_254)) (or (= v_v_1829_2 (select |c_#memory_int| v_idx_246)) (<= v_b_150_2 v_idx_246) (< v_idx_246 .cse10)) (<= v_b_157_2 .cse11) (<= v_b_153_2 v_b_154_2) (<= .cse12 v_b_154_2) (<= .cse13 v_b_157_2) (<= v_b_151_2 .cse5) (<= .cse14 v_b_155_2) (or (< v_idx_247 v_b_150_2) (<= v_b_151_2 v_idx_247) (= 0 (select |c_#memory_int| v_idx_247))) (<= .cse13 v_b_158_2) (<= .cse1 v_b_157_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_244) (= (select |c_#memory_int| v_idx_244) v_v_1827_2)) (<= .cse15 v_b_156_2) (<= .cse8 v_b_151_2) (or (< v_idx_255 v_b_158_2) (= 0 (select |c_#memory_int| v_idx_255)) (<= v_b_159_2 v_idx_255)) (<= .cse16 v_b_158_2) (<= 0 v_v_1828_2) (<= .cse17 v_b_153_2) (<= v_b_153_2 .cse2) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_2) (<= .cse12 v_b_153_2) (<= .cse18 v_b_155_2) (<= .cse15 v_b_155_2) (or (< v_idx_249 v_b_152_2) (= 0 (select |c_#memory_int| v_idx_249)) (<= v_b_153_2 v_idx_249)) (<= (+ v_b_151_2 4) v_b_159_2) (<= .cse19 v_b_158_2) (<= (+ v_b_154_2 3) v_b_159_2) (<= (+ v_b_156_2 2) v_b_159_2) (or (= (select |c_#memory_int| v_idx_248) v_v_1831_2) (<= v_b_152_2 v_idx_248) (< v_idx_248 v_b_151_2)) (or (< v_idx_256 v_b_159_2) (= (select |c_#memory_int| v_idx_256) v_v_1839_2)) (<= 0 (* 2 v_v_1828_2)) (<= .cse0 v_b_155_2) (<= v_b_155_2 v_b_156_2) (<= .cse14 v_b_156_2) (<= (+ v_b_153_2 3) v_b_159_2) (<= .cse6 v_b_155_2) (<= .cse9 v_b_157_2) (<= .cse16 v_b_157_2) (<= .cse10 v_b_150_2) (<= .cse2 v_b_154_2) (<= .cse5 v_b_152_2) (<= (+ v_b_157_2 1) v_b_159_2) (<= .cse11 v_b_157_2) (<= .cse19 v_b_157_2) (<= .cse20 v_b_156_2) (or (< v_idx_250 v_b_153_2) (= (select |c_#memory_int| v_idx_250) v_v_1833_2) (<= v_b_154_2 v_idx_250)) (<= .cse20 v_b_155_2) (<= .cse21 v_b_153_2) (<= .cse3 v_b_157_2) (<= (+ v_b_152_2 4) v_b_159_2) (<= v_b_155_2 .cse18) (or (< v_idx_251 v_b_154_2) (<= v_b_155_2 v_idx_251) (= (select |c_#memory_int| v_idx_251) 0)) (<= .cse18 v_b_156_2) (<= .cse21 v_b_154_2) (<= .cse11 v_b_158_2) (<= v_b_151_2 v_b_152_2) (or (= 0 (select |c_#memory_int| v_idx_253)) (< v_idx_253 v_b_156_2) (<= v_b_157_2 v_idx_253)) (<= .cse17 v_b_154_2) (<= .cse7 v_b_158_2))))) is different from false [2019-01-08 14:36:29,385 WARN L860 $PredicateComparison]: unable to prove that (forall ((v_idx_247 Int) (v_idx_248 Int) (v_idx_245 Int) (v_idx_256 Int) (v_idx_246 Int) (v_idx_249 Int) (v_idx_250 Int) (v_idx_251 Int) (v_idx_254 Int) (v_idx_244 Int) (v_idx_255 Int) (v_idx_252 Int) (v_idx_253 Int)) (exists ((v_v_1831_2 Int) (v_v_1835_2 Int) (v_v_1833_2 Int) (v_b_159_2 Int) (v_b_158_2 Int) (v_b_157_2 Int) (v_b_152_2 Int) (v_b_151_2 Int) (v_b_150_2 Int) (v_b_156_2 Int) (v_b_155_2 Int) (v_b_154_2 Int) (v_b_153_2 Int) (v_v_1828_2 Int) (v_v_1839_2 Int) (v_v_1829_2 Int) (v_v_1837_2 Int) (v_v_1827_2 Int)) (let ((.cse4 (+ v_b_158_2 1)) (.cse13 (+ v_b_151_2 3)) (.cse1 (+ c_ULTIMATE.start_main_p1 5)) (.cse8 (+ c_ULTIMATE.start_main_p1 2)) (.cse12 (+ c_ULTIMATE.start_main_p1 3)) (.cse15 (+ v_b_153_2 1)) (.cse0 (+ v_b_150_2 3)) (.cse14 (+ c_ULTIMATE.start_main_p1 4)) (.cse6 (+ v_b_151_2 2)) (.cse9 (+ v_b_150_2 4)) (.cse16 (+ v_b_152_2 3)) (.cse10 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ v_b_152_2 1)) (.cse5 (+ v_b_150_2 1)) (.cse19 (+ v_b_153_2 2)) (.cse20 (+ v_b_152_2 2)) (.cse3 (+ v_b_154_2 2)) (.cse18 (+ v_b_154_2 1)) (.cse21 (+ v_b_150_2 2)) (.cse11 (+ v_b_156_2 1)) (.cse17 (+ v_b_151_2 1)) (.cse7 (+ v_b_155_2 1))) (and (<= .cse0 v_b_156_2) (<= .cse1 v_b_158_2) (<= .cse2 v_b_153_2) (<= .cse3 v_b_158_2) (<= .cse4 v_b_159_2) (<= .cse5 v_b_151_2) (<= .cse6 v_b_156_2) (<= v_b_159_2 .cse4) (<= v_b_157_2 v_b_158_2) (<= .cse7 v_b_157_2) (<= (+ v_b_150_2 5) v_b_159_2) (<= .cse8 v_b_152_2) (<= .cse9 v_b_158_2) (<= (+ v_b_155_2 2) v_b_159_2) (or (<= v_b_156_2 v_idx_252) (= (select |c_#memory_int| v_idx_252) v_v_1835_2) (< v_idx_252 v_b_155_2)) (or (< v_idx_245 c_ULTIMATE.start_main_p1) (<= .cse10 v_idx_245) (= (select |c_#memory_int| v_idx_245) v_v_1828_2)) (or (< v_idx_254 v_b_157_2) (= (select |c_#memory_int| v_idx_254) v_v_1837_2) (<= v_b_158_2 v_idx_254)) (or (= v_v_1829_2 (select |c_#memory_int| v_idx_246)) (<= v_b_150_2 v_idx_246) (< v_idx_246 .cse10)) (<= v_b_157_2 .cse11) (<= v_b_153_2 v_b_154_2) (<= .cse12 v_b_154_2) (<= .cse13 v_b_157_2) (<= v_b_151_2 .cse5) (<= .cse14 v_b_155_2) (or (< v_idx_247 v_b_150_2) (<= v_b_151_2 v_idx_247) (= 0 (select |c_#memory_int| v_idx_247))) (<= .cse13 v_b_158_2) (<= .cse1 v_b_157_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_244) (= (select |c_#memory_int| v_idx_244) v_v_1827_2)) (<= .cse15 v_b_156_2) (<= .cse8 v_b_151_2) (or (< v_idx_255 v_b_158_2) (= 0 (select |c_#memory_int| v_idx_255)) (<= v_b_159_2 v_idx_255)) (<= .cse16 v_b_158_2) (<= 0 v_v_1828_2) (<= .cse17 v_b_153_2) (<= v_b_153_2 .cse2) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_2) (<= .cse12 v_b_153_2) (<= .cse18 v_b_155_2) (<= .cse15 v_b_155_2) (or (< v_idx_249 v_b_152_2) (= 0 (select |c_#memory_int| v_idx_249)) (<= v_b_153_2 v_idx_249)) (<= (+ v_b_151_2 4) v_b_159_2) (<= .cse19 v_b_158_2) (<= (+ v_b_154_2 3) v_b_159_2) (<= (+ v_b_156_2 2) v_b_159_2) (or (= (select |c_#memory_int| v_idx_248) v_v_1831_2) (<= v_b_152_2 v_idx_248) (< v_idx_248 v_b_151_2)) (or (< v_idx_256 v_b_159_2) (= (select |c_#memory_int| v_idx_256) v_v_1839_2)) (<= 0 (* 2 v_v_1828_2)) (<= .cse0 v_b_155_2) (<= v_b_155_2 v_b_156_2) (<= .cse14 v_b_156_2) (<= (+ v_b_153_2 3) v_b_159_2) (<= .cse6 v_b_155_2) (<= .cse9 v_b_157_2) (<= .cse16 v_b_157_2) (<= .cse10 v_b_150_2) (<= .cse2 v_b_154_2) (<= .cse5 v_b_152_2) (<= (+ v_b_157_2 1) v_b_159_2) (<= .cse11 v_b_157_2) (<= .cse19 v_b_157_2) (<= .cse20 v_b_156_2) (or (< v_idx_250 v_b_153_2) (= (select |c_#memory_int| v_idx_250) v_v_1833_2) (<= v_b_154_2 v_idx_250)) (<= .cse20 v_b_155_2) (<= .cse21 v_b_153_2) (<= .cse3 v_b_157_2) (<= (+ v_b_152_2 4) v_b_159_2) (<= v_b_155_2 .cse18) (or (< v_idx_251 v_b_154_2) (<= v_b_155_2 v_idx_251) (= (select |c_#memory_int| v_idx_251) 0)) (<= .cse18 v_b_156_2) (<= .cse21 v_b_154_2) (<= .cse11 v_b_158_2) (<= v_b_151_2 v_b_152_2) (or (= 0 (select |c_#memory_int| v_idx_253)) (< v_idx_253 v_b_156_2) (<= v_b_157_2 v_idx_253)) (<= .cse17 v_b_154_2) (<= .cse7 v_b_158_2))))) is different from true [2019-01-08 14:36:29,387 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:36:29,387 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:36:29,387 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:36:29,387 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:36:29,387 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:36:29,388 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:36:29,388 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:36:29,388 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=1, Unknown=4, NotChecked=2, Total=12 [2019-01-08 14:36:29,389 INFO L87 Difference]: Start difference. First operand 15 states and 32 transitions. Second operand 4 states. [2019-01-08 14:36:32,071 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_247 Int) (v_idx_248 Int) (v_idx_245 Int) (v_idx_256 Int) (v_idx_246 Int) (v_idx_249 Int) (v_idx_250 Int) (v_idx_251 Int) (v_idx_254 Int) (v_idx_244 Int) (v_idx_255 Int) (v_idx_252 Int) (v_idx_253 Int)) (exists ((v_v_1831_2 Int) (v_v_1835_2 Int) (v_v_1833_2 Int) (v_b_159_2 Int) (v_b_158_2 Int) (v_b_157_2 Int) (v_b_152_2 Int) (v_b_151_2 Int) (v_b_150_2 Int) (v_b_156_2 Int) (v_b_155_2 Int) (v_b_154_2 Int) (v_b_153_2 Int) (v_v_1828_2 Int) (v_v_1839_2 Int) (v_v_1829_2 Int) (v_v_1837_2 Int) (v_v_1827_2 Int)) (let ((.cse4 (+ v_b_158_2 1)) (.cse13 (+ v_b_151_2 3)) (.cse1 (+ c_ULTIMATE.start_main_p1 5)) (.cse8 (+ c_ULTIMATE.start_main_p1 2)) (.cse12 (+ c_ULTIMATE.start_main_p1 3)) (.cse15 (+ v_b_153_2 1)) (.cse0 (+ v_b_150_2 3)) (.cse14 (+ c_ULTIMATE.start_main_p1 4)) (.cse6 (+ v_b_151_2 2)) (.cse9 (+ v_b_150_2 4)) (.cse16 (+ v_b_152_2 3)) (.cse10 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ v_b_152_2 1)) (.cse5 (+ v_b_150_2 1)) (.cse19 (+ v_b_153_2 2)) (.cse20 (+ v_b_152_2 2)) (.cse3 (+ v_b_154_2 2)) (.cse18 (+ v_b_154_2 1)) (.cse21 (+ v_b_150_2 2)) (.cse11 (+ v_b_156_2 1)) (.cse17 (+ v_b_151_2 1)) (.cse7 (+ v_b_155_2 1))) (and (<= .cse0 v_b_156_2) (<= .cse1 v_b_158_2) (<= .cse2 v_b_153_2) (<= .cse3 v_b_158_2) (<= .cse4 v_b_159_2) (<= .cse5 v_b_151_2) (<= .cse6 v_b_156_2) (<= v_b_159_2 .cse4) (<= v_b_157_2 v_b_158_2) (<= .cse7 v_b_157_2) (<= (+ v_b_150_2 5) v_b_159_2) (<= .cse8 v_b_152_2) (<= .cse9 v_b_158_2) (<= (+ v_b_155_2 2) v_b_159_2) (or (<= v_b_156_2 v_idx_252) (= (select |c_#memory_int| v_idx_252) v_v_1835_2) (< v_idx_252 v_b_155_2)) (or (< v_idx_245 c_ULTIMATE.start_main_p1) (<= .cse10 v_idx_245) (= (select |c_#memory_int| v_idx_245) v_v_1828_2)) (or (< v_idx_254 v_b_157_2) (= (select |c_#memory_int| v_idx_254) v_v_1837_2) (<= v_b_158_2 v_idx_254)) (or (= v_v_1829_2 (select |c_#memory_int| v_idx_246)) (<= v_b_150_2 v_idx_246) (< v_idx_246 .cse10)) (<= v_b_157_2 .cse11) (<= v_b_153_2 v_b_154_2) (<= .cse12 v_b_154_2) (<= .cse13 v_b_157_2) (<= v_b_151_2 .cse5) (<= .cse14 v_b_155_2) (or (< v_idx_247 v_b_150_2) (<= v_b_151_2 v_idx_247) (= 0 (select |c_#memory_int| v_idx_247))) (<= .cse13 v_b_158_2) (<= .cse1 v_b_157_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_244) (= (select |c_#memory_int| v_idx_244) v_v_1827_2)) (<= .cse15 v_b_156_2) (<= .cse8 v_b_151_2) (or (< v_idx_255 v_b_158_2) (= 0 (select |c_#memory_int| v_idx_255)) (<= v_b_159_2 v_idx_255)) (<= .cse16 v_b_158_2) (<= 0 v_v_1828_2) (<= .cse17 v_b_153_2) (<= v_b_153_2 .cse2) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_2) (<= .cse12 v_b_153_2) (<= .cse18 v_b_155_2) (<= .cse15 v_b_155_2) (or (< v_idx_249 v_b_152_2) (= 0 (select |c_#memory_int| v_idx_249)) (<= v_b_153_2 v_idx_249)) (<= (+ v_b_151_2 4) v_b_159_2) (<= .cse19 v_b_158_2) (<= (+ v_b_154_2 3) v_b_159_2) (<= (+ v_b_156_2 2) v_b_159_2) (or (= (select |c_#memory_int| v_idx_248) v_v_1831_2) (<= v_b_152_2 v_idx_248) (< v_idx_248 v_b_151_2)) (or (< v_idx_256 v_b_159_2) (= (select |c_#memory_int| v_idx_256) v_v_1839_2)) (<= 0 (* 2 v_v_1828_2)) (<= .cse0 v_b_155_2) (<= v_b_155_2 v_b_156_2) (<= .cse14 v_b_156_2) (<= (+ v_b_153_2 3) v_b_159_2) (<= .cse6 v_b_155_2) (<= .cse9 v_b_157_2) (<= .cse16 v_b_157_2) (<= .cse10 v_b_150_2) (<= .cse2 v_b_154_2) (<= .cse5 v_b_152_2) (<= (+ v_b_157_2 1) v_b_159_2) (<= .cse11 v_b_157_2) (<= .cse19 v_b_157_2) (<= .cse20 v_b_156_2) (or (< v_idx_250 v_b_153_2) (= (select |c_#memory_int| v_idx_250) v_v_1833_2) (<= v_b_154_2 v_idx_250)) (<= .cse20 v_b_155_2) (<= .cse21 v_b_153_2) (<= .cse3 v_b_157_2) (<= (+ v_b_152_2 4) v_b_159_2) (<= v_b_155_2 .cse18) (or (< v_idx_251 v_b_154_2) (<= v_b_155_2 v_idx_251) (= (select |c_#memory_int| v_idx_251) 0)) (<= .cse18 v_b_156_2) (<= .cse21 v_b_154_2) (<= .cse11 v_b_158_2) (<= v_b_151_2 v_b_152_2) (or (= 0 (select |c_#memory_int| v_idx_253)) (< v_idx_253 v_b_156_2) (<= v_b_157_2 v_idx_253)) (<= .cse17 v_b_154_2) (<= .cse7 v_b_158_2))))) (forall ((v_idx_236 Int) (v_idx_237 Int) (v_idx_234 Int) (v_idx_235 Int) (v_idx_238 Int) (v_idx_239 Int) (v_idx_240 Int) (v_idx_243 Int) (v_idx_232 Int) (v_idx_233 Int) (v_idx_241 Int) (v_idx_242 Int) (v_idx_231 Int)) (exists ((v_v_1831_2 Int) (v_v_1835_2 Int) (v_v_1833_2 Int) (v_b_159_2 Int) (v_b_158_2 Int) (v_b_157_2 Int) (v_b_152_2 Int) (v_b_151_2 Int) (v_b_150_2 Int) (v_b_156_2 Int) (v_b_155_2 Int) (v_b_154_2 Int) (v_b_153_2 Int) (v_v_1839_2 Int) (v_v_1828_2 Int) (v_v_1829_2 Int) (v_v_1837_2 Int) (v_v_1827_2 Int)) (let ((.cse26 (+ v_b_158_2 1)) (.cse34 (+ v_b_151_2 3)) (.cse23 (+ c_ULTIMATE.start_main_p1 5)) (.cse30 (+ c_ULTIMATE.start_main_p1 2)) (.cse33 (+ c_ULTIMATE.start_main_p1 3)) (.cse36 (+ v_b_153_2 1)) (.cse22 (+ v_b_150_2 3)) (.cse35 (+ c_ULTIMATE.start_main_p1 4)) (.cse28 (+ v_b_151_2 2)) (.cse31 (+ v_b_150_2 4)) (.cse37 (+ v_b_152_2 3)) (.cse24 (+ v_b_152_2 1)) (.cse27 (+ v_b_150_2 1)) (.cse40 (+ v_b_153_2 2)) (.cse42 (+ v_b_152_2 2)) (.cse25 (+ v_b_154_2 2)) (.cse41 (+ c_ULTIMATE.start_main_p1 1)) (.cse39 (+ v_b_154_2 1)) (.cse43 (+ v_b_150_2 2)) (.cse32 (+ v_b_156_2 1)) (.cse38 (+ v_b_151_2 1)) (.cse29 (+ v_b_155_2 1))) (and (<= .cse22 v_b_156_2) (<= .cse23 v_b_158_2) (or (< v_idx_240 v_b_156_2) (= 0 (select |c_#memory_int| v_idx_240)) (<= v_b_157_2 v_idx_240)) (<= .cse24 v_b_153_2) (<= .cse25 v_b_158_2) (<= .cse26 v_b_159_2) (<= .cse27 v_b_151_2) (or (< v_idx_237 v_b_153_2) (= (select |c_#memory_int| v_idx_237) v_v_1833_2) (<= v_b_154_2 v_idx_237)) (<= .cse28 v_b_156_2) (<= v_b_159_2 .cse26) (<= v_b_157_2 v_b_158_2) (<= .cse29 v_b_157_2) (<= (+ v_b_150_2 5) v_b_159_2) (<= .cse30 v_b_152_2) (<= .cse31 v_b_158_2) (<= (+ v_b_155_2 2) v_b_159_2) (or (< v_idx_236 v_b_152_2) (= (select |c_#memory_int| v_idx_236) 0) (<= v_b_153_2 v_idx_236)) (<= v_b_157_2 .cse32) (<= v_b_153_2 v_b_154_2) (<= .cse33 v_b_154_2) (<= .cse34 v_b_157_2) (or (< v_idx_234 v_b_150_2) (<= v_b_151_2 v_idx_234) (= 0 (select |c_#memory_int| v_idx_234))) (<= v_b_151_2 .cse27) (<= .cse35 v_b_155_2) (<= .cse34 v_b_158_2) (<= .cse23 v_b_157_2) (or (< v_idx_243 v_b_159_2) (= (select |c_#memory_int| v_idx_243) v_v_1839_2)) (or (<= v_b_152_2 v_idx_235) (< v_idx_235 v_b_151_2) (= (select |c_#memory_int| v_idx_235) v_v_1831_2)) (<= .cse36 v_b_156_2) (<= .cse30 v_b_151_2) (or (<= v_b_155_2 v_idx_238) (< v_idx_238 v_b_154_2) (= 0 (select |c_#memory_int| v_idx_238))) (<= .cse37 v_b_158_2) (<= 0 v_v_1828_2) (<= .cse38 v_b_153_2) (<= v_b_153_2 .cse24) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_2) (<= .cse33 v_b_153_2) (<= .cse39 v_b_155_2) (<= .cse36 v_b_155_2) (<= (+ v_b_151_2 4) v_b_159_2) (<= .cse40 v_b_158_2) (<= (+ v_b_154_2 3) v_b_159_2) (<= (+ v_b_156_2 2) v_b_159_2) (<= 0 (* 2 v_v_1828_2)) (<= .cse22 v_b_155_2) (<= v_b_155_2 v_b_156_2) (<= .cse35 v_b_156_2) (<= (+ v_b_153_2 3) v_b_159_2) (<= .cse28 v_b_155_2) (<= .cse31 v_b_157_2) (<= .cse37 v_b_157_2) (<= .cse41 v_b_150_2) (or (<= v_b_159_2 v_idx_242) (= 0 (select |c_#memory_int| v_idx_242)) (< v_idx_242 v_b_158_2)) (<= .cse24 v_b_154_2) (or (< v_idx_232 c_ULTIMATE.start_main_p1) (<= .cse41 v_idx_232) (= (select |c_#memory_int| v_idx_232) v_v_1828_2)) (<= .cse27 v_b_152_2) (<= (+ v_b_157_2 1) v_b_159_2) (<= .cse32 v_b_157_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_231) (= (select |c_#memory_int| v_idx_231) v_v_1827_2)) (<= .cse40 v_b_157_2) (<= .cse42 v_b_156_2) (<= .cse42 v_b_155_2) (<= .cse43 v_b_153_2) (<= .cse25 v_b_157_2) (or (<= v_b_150_2 v_idx_233) (= (select |c_#memory_int| v_idx_233) v_v_1829_2) (< v_idx_233 .cse41)) (or (< v_idx_241 v_b_157_2) (= (select |c_#memory_int| v_idx_241) v_v_1837_2) (<= v_b_158_2 v_idx_241)) (or (< v_idx_239 v_b_155_2) (<= v_b_156_2 v_idx_239) (= (select |c_#memory_int| v_idx_239) v_v_1835_2)) (<= (+ v_b_152_2 4) v_b_159_2) (<= v_b_155_2 .cse39) (<= .cse39 v_b_156_2) (<= .cse43 v_b_154_2) (<= .cse32 v_b_158_2) (<= v_b_151_2 v_b_152_2) (<= .cse38 v_b_154_2) (<= .cse29 v_b_158_2)))))) is different from false [2019-01-08 14:37:07,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:37:07,528 INFO L93 Difference]: Finished difference Result 17 states and 40 transitions. [2019-01-08 14:37:07,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-08 14:37:07,528 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-08 14:37:07,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:37:07,529 INFO L225 Difference]: With dead ends: 17 [2019-01-08 14:37:07,529 INFO L226 Difference]: Without dead ends: 16 [2019-01-08 14:37:07,530 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 11.7s TimeCoverageRelationStatistics Valid=7, Invalid=2, Unknown=5, NotChecked=6, Total=20 [2019-01-08 14:37:07,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-08 14:37:07,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2019-01-08 14:37:07,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-08 14:37:07,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 32 transitions. [2019-01-08 14:37:07,537 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 32 transitions. Word has length 3 [2019-01-08 14:37:07,538 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:37:07,538 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 32 transitions. [2019-01-08 14:37:07,538 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:37:07,538 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 32 transitions. [2019-01-08 14:37:07,538 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:37:07,538 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:37:07,538 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:37:07,539 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:37:07,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:37:07,539 INFO L82 PathProgramCache]: Analyzing trace with hash 30500, now seen corresponding path program 1 times [2019-01-08 14:37:07,539 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:37:07,540 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:37:07,540 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:37:07,540 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:37:07,540 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:37:07,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:37:07,698 WARN L181 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 24 DAG size of output: 13 [2019-01-08 14:37:07,703 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:37:07,704 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:37:07,704 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:37:07,704 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:37:07,704 INFO L207 CegarAbsIntRunner]: [0], [22], [27] [2019-01-08 14:37:07,705 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:37:07,705 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:37:17,848 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:37:17,849 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:37:17,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:37:17,849 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:37:18,343 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 75% of their original sizes. [2019-01-08 14:37:18,343 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:37:20,698 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_368 Int) (v_idx_369 Int) (v_idx_366 Int) (v_idx_367 Int) (v_idx_359 Int) (v_idx_360 Int) (v_idx_371 Int) (v_idx_361 Int) (v_idx_370 Int) (v_idx_364 Int) (v_idx_365 Int) (v_idx_362 Int) (v_idx_363 Int)) (exists ((v_v_1600_3 Int) (v_v_1602_3 Int) (v_v_1604_3 Int) (v_b_169_3 Int) (v_b_168_3 Int) (v_b_167_3 Int) (v_b_170_3 Int) (v_b_171_3 Int) (v_b_166_3 Int) (v_b_174_3 Int) (v_v_1596_3 Int) (v_b_175_3 Int) (v_v_1606_3 Int) (v_v_1605_3 Int) (v_v_1608_3 Int) (v_v_1598_3 Int)) (let ((.cse8 (+ v_b_167_3 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 3)) (.cse6 (+ v_b_174_3 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 2)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_169_3 1)) (.cse2 (+ v_b_168_3 1)) (.cse5 (+ v_b_166_3 1)) (.cse3 (+ v_b_168_3 2)) (.cse9 (+ v_b_170_3 1)) (.cse13 (+ v_b_166_3 3)) (.cse12 (+ c_ULTIMATE.start_main_p5 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 4)) (.cse10 (+ v_b_167_3 2)) (.cse14 (+ v_b_166_3 2))) (and (or (<= .cse0 v_idx_360) (= (select |c_#memory_int| v_idx_360) 0) (< v_idx_360 c_ULTIMATE.start_main_p1)) (<= .cse1 v_b_171_3) (or (= (select |c_#memory_int| v_idx_365) v_v_1602_3) (< v_idx_365 v_b_169_3) (<= v_b_170_3 v_idx_365)) (<= .cse2 v_b_169_3) (<= .cse3 v_b_171_3) (<= .cse4 v_b_167_3) (or (= (select |c_#memory_int| v_idx_371) v_v_1608_3) (< v_idx_371 v_b_175_3)) (<= .cse5 v_b_167_3) (<= v_b_175_3 .cse6) (<= .cse7 v_b_169_3) (<= v_b_167_3 .cse5) (<= .cse8 v_b_169_3) (<= (+ v_b_167_3 3) v_b_174_3) (<= (+ c_ULTIMATE.start_main_p5 2) v_b_175_3) (<= .cse9 v_b_171_3) (<= (+ v_b_169_3 3) v_b_175_3) (<= (+ v_b_168_3 4) v_b_175_3) (<= .cse8 v_b_170_3) (<= .cse2 v_b_170_3) (<= .cse7 v_b_170_3) (or (<= v_b_166_3 v_idx_361) (= (select |c_#memory_int| v_idx_361) v_v_1598_3) (< v_idx_361 .cse0)) (<= 0 v_v_1605_3) (<= .cse10 v_b_171_3) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_3) (or (= 0 (select |c_#memory_int| v_idx_366)) (<= v_b_171_3 v_idx_366) (< v_idx_366 v_b_170_3)) (<= .cse6 v_b_175_3) (<= (+ v_b_171_3 1) v_b_174_3) (<= .cse4 v_b_168_3) (<= .cse9 c_ULTIMATE.start_main_p5) (or (< v_idx_362 v_b_166_3) (<= v_b_167_3 v_idx_362) (= 0 (select |c_#memory_int| v_idx_362))) (<= .cse11 c_ULTIMATE.start_main_p5) (<= 0 (* 2 v_v_1605_3)) (or (<= .cse12 v_idx_368) (= v_v_1605_3 (select |c_#memory_int| v_idx_368)) (< v_idx_368 c_ULTIMATE.start_main_p5)) (<= (+ v_b_166_3 4) v_b_174_3) (<= .cse0 v_b_166_3) (<= .cse1 c_ULTIMATE.start_main_p5) (<= (+ v_b_170_3 2) v_b_174_3) (<= v_b_169_3 .cse2) (<= .cse5 v_b_168_3) (<= (+ v_b_170_3 3) v_b_175_3) (<= .cse3 c_ULTIMATE.start_main_p5) (<= (+ v_b_166_3 5) v_b_175_3) (<= v_b_171_3 .cse9) (<= (+ v_b_171_3 2) v_b_175_3) (or (<= v_b_175_3 v_idx_370) (< v_idx_370 v_b_174_3) (= 0 (select |c_#memory_int| v_idx_370))) (<= v_b_171_3 c_ULTIMATE.start_main_p5) (<= .cse13 v_b_171_3) (<= v_b_167_3 v_b_168_3) (<= .cse12 v_b_174_3) (<= (+ v_b_167_3 4) v_b_175_3) (<= v_b_169_3 v_b_170_3) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_174_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_359) (= (select |c_#memory_int| v_idx_359) v_v_1596_3)) (or (<= c_ULTIMATE.start_main_p5 v_idx_367) (= (select |c_#memory_int| v_idx_367) v_v_1604_3) (< v_idx_367 v_b_171_3)) (<= (+ v_b_168_3 3) v_b_174_3) (<= .cse13 c_ULTIMATE.start_main_p5) (or (< v_idx_369 .cse12) (= (select |c_#memory_int| v_idx_369) v_v_1606_3) (<= v_b_174_3 v_idx_369)) (<= .cse14 v_b_170_3) (<= .cse11 v_b_171_3) (or (<= v_b_169_3 v_idx_364) (< v_idx_364 v_b_168_3) (= (select |c_#memory_int| v_idx_364) 0)) (<= (+ v_b_169_3 2) v_b_174_3) (or (<= v_b_168_3 v_idx_363) (= (select |c_#memory_int| v_idx_363) v_v_1600_3) (< v_idx_363 v_b_167_3)) (<= .cse10 c_ULTIMATE.start_main_p5) (<= .cse14 v_b_169_3))))) is different from false [2019-01-08 14:37:23,208 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_379 Int) (v_idx_377 Int) (v_idx_378 Int) (v_idx_382 Int) (v_idx_383 Int) (v_idx_372 Int) (v_idx_380 Int) (v_idx_381 Int) (v_idx_375 Int) (v_idx_376 Int) (v_idx_384 Int) (v_idx_373 Int) (v_idx_374 Int)) (exists ((v_v_1600_3 Int) (v_v_1602_3 Int) (v_v_1604_3 Int) (v_b_169_3 Int) (v_b_168_3 Int) (v_b_167_3 Int) (v_b_170_3 Int) (v_b_171_3 Int) (v_b_172_3 Int) (v_b_173_3 Int) (v_b_166_3 Int) (v_b_174_3 Int) (v_v_1596_3 Int) (v_b_175_3 Int) (v_v_1606_3 Int) (v_v_1605_3 Int) (v_v_1598_3 Int) (v_v_1608_3 Int)) (let ((.cse8 (+ v_b_167_3 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 3)) (.cse6 (+ v_b_174_3 1)) (.cse11 (+ v_b_171_3 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2)) (.cse4 (+ v_b_172_3 1)) (.cse12 (+ v_b_167_3 2)) (.cse1 (+ v_b_168_3 1)) (.cse5 (+ v_b_166_3 1)) (.cse0 (+ v_b_169_3 1)) (.cse10 (+ v_b_170_3 1)) (.cse14 (+ c_ULTIMATE.start_main_p1 1)) (.cse16 (+ v_b_166_3 3)) (.cse13 (+ v_b_166_3 4)) (.cse17 (+ c_ULTIMATE.start_main_p1 5)) (.cse15 (+ v_b_170_3 2)) (.cse20 (+ v_b_168_3 3)) (.cse2 (+ v_b_168_3 2)) (.cse18 (+ c_ULTIMATE.start_main_p1 4)) (.cse19 (+ v_b_169_3 2)) (.cse9 (+ v_b_167_3 3)) (.cse21 (+ v_b_166_3 2))) (and (<= .cse0 v_b_171_3) (<= .cse1 v_b_169_3) (<= .cse2 v_b_171_3) (<= .cse3 v_b_167_3) (<= .cse4 v_b_173_3) (<= .cse5 v_b_167_3) (<= v_b_175_3 .cse6) (<= (+ v_b_172_3 2) v_b_175_3) (<= .cse7 v_b_169_3) (<= v_b_171_3 v_b_172_3) (<= v_b_167_3 .cse5) (<= .cse8 v_b_169_3) (<= .cse9 v_b_174_3) (<= .cse10 v_b_171_3) (<= (+ v_b_169_3 3) v_b_175_3) (<= (+ v_b_168_3 4) v_b_175_3) (or (<= v_b_172_3 v_idx_380) (= (select |c_#memory_int| v_idx_380) v_v_1604_3) (< v_idx_380 v_b_171_3)) (or (<= v_b_173_3 v_idx_381) (= (select |c_#memory_int| v_idx_381) v_v_1605_3) (< v_idx_381 v_b_172_3)) (<= .cse8 v_b_170_3) (<= .cse1 v_b_170_3) (<= .cse7 v_b_170_3) (<= 0 v_v_1605_3) (<= .cse11 v_b_173_3) (<= .cse12 v_b_171_3) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_3) (<= .cse4 v_b_174_3) (<= .cse6 v_b_175_3) (<= .cse11 v_b_174_3) (<= .cse3 v_b_168_3) (<= v_b_173_3 .cse4) (<= v_b_173_3 v_b_174_3) (<= .cse10 v_b_172_3) (or (<= v_b_171_3 v_idx_379) (= 0 (select |c_#memory_int| v_idx_379)) (< v_idx_379 v_b_170_3)) (<= 0 (* 2 v_v_1605_3)) (<= .cse13 v_b_174_3) (<= (+ v_b_173_3 1) v_b_175_3) (<= .cse14 v_b_166_3) (<= .cse12 v_b_172_3) (<= .cse15 v_b_174_3) (<= v_b_169_3 .cse1) (or (= 0 (select |c_#memory_int| v_idx_373)) (<= .cse14 v_idx_373) (< v_idx_373 c_ULTIMATE.start_main_p1)) (or (<= v_b_170_3 v_idx_378) (< v_idx_378 v_b_169_3) (= (select |c_#memory_int| v_idx_378) v_v_1602_3)) (<= .cse5 v_b_168_3) (<= .cse0 v_b_172_3) (<= (+ v_b_170_3 3) v_b_175_3) (<= (+ v_b_166_3 5) v_b_175_3) (<= v_b_171_3 .cse10) (or (<= v_b_166_3 v_idx_374) (= (select |c_#memory_int| v_idx_374) v_v_1598_3) (< v_idx_374 .cse14)) (or (= (select |c_#memory_int| v_idx_376) v_v_1600_3) (< v_idx_376 v_b_167_3) (<= v_b_168_3 v_idx_376)) (<= (+ v_b_171_3 2) v_b_175_3) (<= .cse16 v_b_172_3) (<= .cse17 v_b_173_3) (or (< v_idx_384 v_b_175_3) (= (select |c_#memory_int| v_idx_384) v_v_1608_3)) (or (< v_idx_377 v_b_168_3) (<= v_b_169_3 v_idx_377) (= 0 (select |c_#memory_int| v_idx_377))) (<= .cse16 v_b_171_3) (<= v_b_167_3 v_b_168_3) (or (< v_idx_383 v_b_174_3) (= 0 (select |c_#memory_int| v_idx_383)) (<= v_b_175_3 v_idx_383)) (<= .cse18 v_b_172_3) (<= (+ v_b_167_3 4) v_b_175_3) (or (<= v_b_174_3 v_idx_382) (= (select |c_#memory_int| v_idx_382) v_v_1606_3) (< v_idx_382 v_b_173_3)) (<= .cse19 v_b_173_3) (<= .cse13 v_b_173_3) (<= v_b_169_3 v_b_170_3) (<= .cse17 v_b_174_3) (<= .cse15 v_b_173_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_372) (= (select |c_#memory_int| v_idx_372) v_v_1596_3)) (<= .cse20 v_b_173_3) (<= .cse20 v_b_174_3) (<= .cse21 v_b_170_3) (or (< v_idx_375 v_b_166_3) (<= v_b_167_3 v_idx_375) (= 0 (select |c_#memory_int| v_idx_375))) (<= .cse2 v_b_172_3) (<= .cse18 v_b_171_3) (<= .cse19 v_b_174_3) (<= .cse9 v_b_173_3) (<= .cse21 v_b_169_3))))) is different from false [2019-01-08 14:37:23,795 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:37:23,795 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:37:23,796 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:37:23,796 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:37:23,796 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:37:23,796 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:37:23,796 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:37:23,796 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-08 14:37:23,797 INFO L87 Difference]: Start difference. First operand 15 states and 32 transitions. Second operand 4 states. [2019-01-08 14:37:26,317 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_379 Int) (v_idx_377 Int) (v_idx_378 Int) (v_idx_382 Int) (v_idx_383 Int) (v_idx_372 Int) (v_idx_380 Int) (v_idx_381 Int) (v_idx_375 Int) (v_idx_376 Int) (v_idx_384 Int) (v_idx_373 Int) (v_idx_374 Int)) (exists ((v_v_1600_3 Int) (v_v_1602_3 Int) (v_v_1604_3 Int) (v_b_169_3 Int) (v_b_168_3 Int) (v_b_167_3 Int) (v_b_170_3 Int) (v_b_171_3 Int) (v_b_172_3 Int) (v_b_173_3 Int) (v_b_166_3 Int) (v_b_174_3 Int) (v_v_1596_3 Int) (v_b_175_3 Int) (v_v_1606_3 Int) (v_v_1605_3 Int) (v_v_1598_3 Int) (v_v_1608_3 Int)) (let ((.cse8 (+ v_b_167_3 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 3)) (.cse6 (+ v_b_174_3 1)) (.cse11 (+ v_b_171_3 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2)) (.cse4 (+ v_b_172_3 1)) (.cse12 (+ v_b_167_3 2)) (.cse1 (+ v_b_168_3 1)) (.cse5 (+ v_b_166_3 1)) (.cse0 (+ v_b_169_3 1)) (.cse10 (+ v_b_170_3 1)) (.cse14 (+ c_ULTIMATE.start_main_p1 1)) (.cse16 (+ v_b_166_3 3)) (.cse13 (+ v_b_166_3 4)) (.cse17 (+ c_ULTIMATE.start_main_p1 5)) (.cse15 (+ v_b_170_3 2)) (.cse20 (+ v_b_168_3 3)) (.cse2 (+ v_b_168_3 2)) (.cse18 (+ c_ULTIMATE.start_main_p1 4)) (.cse19 (+ v_b_169_3 2)) (.cse9 (+ v_b_167_3 3)) (.cse21 (+ v_b_166_3 2))) (and (<= .cse0 v_b_171_3) (<= .cse1 v_b_169_3) (<= .cse2 v_b_171_3) (<= .cse3 v_b_167_3) (<= .cse4 v_b_173_3) (<= .cse5 v_b_167_3) (<= v_b_175_3 .cse6) (<= (+ v_b_172_3 2) v_b_175_3) (<= .cse7 v_b_169_3) (<= v_b_171_3 v_b_172_3) (<= v_b_167_3 .cse5) (<= .cse8 v_b_169_3) (<= .cse9 v_b_174_3) (<= .cse10 v_b_171_3) (<= (+ v_b_169_3 3) v_b_175_3) (<= (+ v_b_168_3 4) v_b_175_3) (or (<= v_b_172_3 v_idx_380) (= (select |c_#memory_int| v_idx_380) v_v_1604_3) (< v_idx_380 v_b_171_3)) (or (<= v_b_173_3 v_idx_381) (= (select |c_#memory_int| v_idx_381) v_v_1605_3) (< v_idx_381 v_b_172_3)) (<= .cse8 v_b_170_3) (<= .cse1 v_b_170_3) (<= .cse7 v_b_170_3) (<= 0 v_v_1605_3) (<= .cse11 v_b_173_3) (<= .cse12 v_b_171_3) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_3) (<= .cse4 v_b_174_3) (<= .cse6 v_b_175_3) (<= .cse11 v_b_174_3) (<= .cse3 v_b_168_3) (<= v_b_173_3 .cse4) (<= v_b_173_3 v_b_174_3) (<= .cse10 v_b_172_3) (or (<= v_b_171_3 v_idx_379) (= 0 (select |c_#memory_int| v_idx_379)) (< v_idx_379 v_b_170_3)) (<= 0 (* 2 v_v_1605_3)) (<= .cse13 v_b_174_3) (<= (+ v_b_173_3 1) v_b_175_3) (<= .cse14 v_b_166_3) (<= .cse12 v_b_172_3) (<= .cse15 v_b_174_3) (<= v_b_169_3 .cse1) (or (= 0 (select |c_#memory_int| v_idx_373)) (<= .cse14 v_idx_373) (< v_idx_373 c_ULTIMATE.start_main_p1)) (or (<= v_b_170_3 v_idx_378) (< v_idx_378 v_b_169_3) (= (select |c_#memory_int| v_idx_378) v_v_1602_3)) (<= .cse5 v_b_168_3) (<= .cse0 v_b_172_3) (<= (+ v_b_170_3 3) v_b_175_3) (<= (+ v_b_166_3 5) v_b_175_3) (<= v_b_171_3 .cse10) (or (<= v_b_166_3 v_idx_374) (= (select |c_#memory_int| v_idx_374) v_v_1598_3) (< v_idx_374 .cse14)) (or (= (select |c_#memory_int| v_idx_376) v_v_1600_3) (< v_idx_376 v_b_167_3) (<= v_b_168_3 v_idx_376)) (<= (+ v_b_171_3 2) v_b_175_3) (<= .cse16 v_b_172_3) (<= .cse17 v_b_173_3) (or (< v_idx_384 v_b_175_3) (= (select |c_#memory_int| v_idx_384) v_v_1608_3)) (or (< v_idx_377 v_b_168_3) (<= v_b_169_3 v_idx_377) (= 0 (select |c_#memory_int| v_idx_377))) (<= .cse16 v_b_171_3) (<= v_b_167_3 v_b_168_3) (or (< v_idx_383 v_b_174_3) (= 0 (select |c_#memory_int| v_idx_383)) (<= v_b_175_3 v_idx_383)) (<= .cse18 v_b_172_3) (<= (+ v_b_167_3 4) v_b_175_3) (or (<= v_b_174_3 v_idx_382) (= (select |c_#memory_int| v_idx_382) v_v_1606_3) (< v_idx_382 v_b_173_3)) (<= .cse19 v_b_173_3) (<= .cse13 v_b_173_3) (<= v_b_169_3 v_b_170_3) (<= .cse17 v_b_174_3) (<= .cse15 v_b_173_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_372) (= (select |c_#memory_int| v_idx_372) v_v_1596_3)) (<= .cse20 v_b_173_3) (<= .cse20 v_b_174_3) (<= .cse21 v_b_170_3) (or (< v_idx_375 v_b_166_3) (<= v_b_167_3 v_idx_375) (= 0 (select |c_#memory_int| v_idx_375))) (<= .cse2 v_b_172_3) (<= .cse18 v_b_171_3) (<= .cse19 v_b_174_3) (<= .cse9 v_b_173_3) (<= .cse21 v_b_169_3))))) (forall ((v_idx_368 Int) (v_idx_369 Int) (v_idx_366 Int) (v_idx_367 Int) (v_idx_359 Int) (v_idx_360 Int) (v_idx_371 Int) (v_idx_361 Int) (v_idx_370 Int) (v_idx_364 Int) (v_idx_365 Int) (v_idx_362 Int) (v_idx_363 Int)) (exists ((v_v_1600_3 Int) (v_v_1602_3 Int) (v_v_1604_3 Int) (v_b_169_3 Int) (v_b_168_3 Int) (v_b_167_3 Int) (v_b_170_3 Int) (v_b_171_3 Int) (v_b_166_3 Int) (v_b_174_3 Int) (v_v_1596_3 Int) (v_b_175_3 Int) (v_v_1606_3 Int) (v_v_1605_3 Int) (v_v_1608_3 Int) (v_v_1598_3 Int)) (let ((.cse30 (+ v_b_167_3 1)) (.cse29 (+ c_ULTIMATE.start_main_p1 3)) (.cse28 (+ v_b_174_3 1)) (.cse26 (+ c_ULTIMATE.start_main_p1 2)) (.cse22 (+ c_ULTIMATE.start_main_p1 1)) (.cse23 (+ v_b_169_3 1)) (.cse24 (+ v_b_168_3 1)) (.cse27 (+ v_b_166_3 1)) (.cse25 (+ v_b_168_3 2)) (.cse31 (+ v_b_170_3 1)) (.cse35 (+ v_b_166_3 3)) (.cse34 (+ c_ULTIMATE.start_main_p5 1)) (.cse33 (+ c_ULTIMATE.start_main_p1 4)) (.cse32 (+ v_b_167_3 2)) (.cse36 (+ v_b_166_3 2))) (and (or (<= .cse22 v_idx_360) (= (select |c_#memory_int| v_idx_360) 0) (< v_idx_360 c_ULTIMATE.start_main_p1)) (<= .cse23 v_b_171_3) (or (= (select |c_#memory_int| v_idx_365) v_v_1602_3) (< v_idx_365 v_b_169_3) (<= v_b_170_3 v_idx_365)) (<= .cse24 v_b_169_3) (<= .cse25 v_b_171_3) (<= .cse26 v_b_167_3) (or (= (select |c_#memory_int| v_idx_371) v_v_1608_3) (< v_idx_371 v_b_175_3)) (<= .cse27 v_b_167_3) (<= v_b_175_3 .cse28) (<= .cse29 v_b_169_3) (<= v_b_167_3 .cse27) (<= .cse30 v_b_169_3) (<= (+ v_b_167_3 3) v_b_174_3) (<= (+ c_ULTIMATE.start_main_p5 2) v_b_175_3) (<= .cse31 v_b_171_3) (<= (+ v_b_169_3 3) v_b_175_3) (<= (+ v_b_168_3 4) v_b_175_3) (<= .cse30 v_b_170_3) (<= .cse24 v_b_170_3) (<= .cse29 v_b_170_3) (or (<= v_b_166_3 v_idx_361) (= (select |c_#memory_int| v_idx_361) v_v_1598_3) (< v_idx_361 .cse22)) (<= 0 v_v_1605_3) (<= .cse32 v_b_171_3) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_3) (or (= 0 (select |c_#memory_int| v_idx_366)) (<= v_b_171_3 v_idx_366) (< v_idx_366 v_b_170_3)) (<= .cse28 v_b_175_3) (<= (+ v_b_171_3 1) v_b_174_3) (<= .cse26 v_b_168_3) (<= .cse31 c_ULTIMATE.start_main_p5) (or (< v_idx_362 v_b_166_3) (<= v_b_167_3 v_idx_362) (= 0 (select |c_#memory_int| v_idx_362))) (<= .cse33 c_ULTIMATE.start_main_p5) (<= 0 (* 2 v_v_1605_3)) (or (<= .cse34 v_idx_368) (= v_v_1605_3 (select |c_#memory_int| v_idx_368)) (< v_idx_368 c_ULTIMATE.start_main_p5)) (<= (+ v_b_166_3 4) v_b_174_3) (<= .cse22 v_b_166_3) (<= .cse23 c_ULTIMATE.start_main_p5) (<= (+ v_b_170_3 2) v_b_174_3) (<= v_b_169_3 .cse24) (<= .cse27 v_b_168_3) (<= (+ v_b_170_3 3) v_b_175_3) (<= .cse25 c_ULTIMATE.start_main_p5) (<= (+ v_b_166_3 5) v_b_175_3) (<= v_b_171_3 .cse31) (<= (+ v_b_171_3 2) v_b_175_3) (or (<= v_b_175_3 v_idx_370) (< v_idx_370 v_b_174_3) (= 0 (select |c_#memory_int| v_idx_370))) (<= v_b_171_3 c_ULTIMATE.start_main_p5) (<= .cse35 v_b_171_3) (<= v_b_167_3 v_b_168_3) (<= .cse34 v_b_174_3) (<= (+ v_b_167_3 4) v_b_175_3) (<= v_b_169_3 v_b_170_3) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_174_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_359) (= (select |c_#memory_int| v_idx_359) v_v_1596_3)) (or (<= c_ULTIMATE.start_main_p5 v_idx_367) (= (select |c_#memory_int| v_idx_367) v_v_1604_3) (< v_idx_367 v_b_171_3)) (<= (+ v_b_168_3 3) v_b_174_3) (<= .cse35 c_ULTIMATE.start_main_p5) (or (< v_idx_369 .cse34) (= (select |c_#memory_int| v_idx_369) v_v_1606_3) (<= v_b_174_3 v_idx_369)) (<= .cse36 v_b_170_3) (<= .cse33 v_b_171_3) (or (<= v_b_169_3 v_idx_364) (< v_idx_364 v_b_168_3) (= (select |c_#memory_int| v_idx_364) 0)) (<= (+ v_b_169_3 2) v_b_174_3) (or (<= v_b_168_3 v_idx_363) (= (select |c_#memory_int| v_idx_363) v_v_1600_3) (< v_idx_363 v_b_167_3)) (<= .cse32 c_ULTIMATE.start_main_p5) (<= .cse36 v_b_169_3)))))) is different from false [2019-01-08 14:37:45,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:37:45,410 INFO L93 Difference]: Finished difference Result 17 states and 40 transitions. [2019-01-08 14:37:45,411 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-08 14:37:45,411 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-08 14:37:45,411 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:37:45,412 INFO L225 Difference]: With dead ends: 17 [2019-01-08 14:37:45,412 INFO L226 Difference]: Without dead ends: 16 [2019-01-08 14:37:45,412 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.7s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:37:45,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-08 14:37:45,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2019-01-08 14:37:45,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-08 14:37:45,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 32 transitions. [2019-01-08 14:37:45,424 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 32 transitions. Word has length 3 [2019-01-08 14:37:45,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:37:45,424 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 32 transitions. [2019-01-08 14:37:45,424 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:37:45,424 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 32 transitions. [2019-01-08 14:37:45,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:37:45,425 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:37:45,425 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:37:45,425 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:37:45,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:37:45,425 INFO L82 PathProgramCache]: Analyzing trace with hash 30562, now seen corresponding path program 1 times [2019-01-08 14:37:45,426 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:37:45,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:37:45,427 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:37:45,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:37:45,427 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:37:45,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:37:45,496 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:37:45,496 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:37:45,496 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:37:45,497 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:37:45,497 INFO L207 CegarAbsIntRunner]: [0], [24], [27] [2019-01-08 14:37:45,498 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:37:45,498 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:37:54,328 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:37:54,329 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:37:54,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:37:54,329 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:37:54,866 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 75% of their original sizes. [2019-01-08 14:37:54,866 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:37:57,872 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_489 Int) (v_idx_487 Int) (v_idx_498 Int) (v_idx_488 Int) (v_idx_499 Int) (v_idx_492 Int) (v_idx_493 Int) (v_idx_490 Int) (v_idx_491 Int) (v_idx_496 Int) (v_idx_497 Int) (v_idx_494 Int) (v_idx_495 Int)) (exists ((v_v_1398_4 Int) (v_v_1388_4 Int) (v_b_169_4 Int) (v_v_1396_4 Int) (v_b_168_4 Int) (v_v_1397_4 Int) (v_v_1386_4 Int) (v_b_167_4 Int) (v_v_1394_4 Int) (v_b_166_4 Int) (v_v_1392_4 Int) (v_v_1390_4 Int) (v_b_170_4 Int) (v_b_171_4 Int) (v_b_172_4 Int) (v_b_173_4 Int)) (let ((.cse4 (+ v_b_169_4 2)) (.cse8 (+ v_b_166_4 3)) (.cse5 (+ v_b_171_4 1)) (.cse7 (+ v_b_166_4 2)) (.cse14 (+ v_b_167_4 3)) (.cse0 (+ v_b_166_4 1)) (.cse12 (+ v_b_166_4 4)) (.cse10 (+ v_b_170_4 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 1)) (.cse19 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ c_ULTIMATE.start_main_p1 3)) (.cse17 (+ v_b_167_4 2)) (.cse18 (+ v_b_169_4 1)) (.cse15 (+ c_ULTIMATE.start_main_p1 5)) (.cse3 (+ v_b_168_4 1)) (.cse13 (+ v_b_172_4 1)) (.cse9 (+ v_b_168_4 2)) (.cse21 (+ v_b_170_4 2)) (.cse1 (+ c_ULTIMATE.start_main_p6 1)) (.cse20 (+ c_ULTIMATE.start_main_p1 4)) (.cse16 (+ v_b_167_4 1)) (.cse11 (+ v_b_168_4 3))) (and (<= .cse0 v_b_168_4) (or (= (select |c_#memory_int| v_idx_490) 0) (<= v_b_167_4 v_idx_490) (< v_idx_490 v_b_166_4)) (or (= (select |c_#memory_int| v_idx_498) v_v_1397_4) (< v_idx_498 c_ULTIMATE.start_main_p6) (<= .cse1 v_idx_498)) (<= .cse2 v_b_169_4) (<= v_b_169_4 .cse3) (<= .cse4 v_b_173_4) (<= .cse5 c_ULTIMATE.start_main_p6) (or (< v_idx_489 .cse6) (<= v_b_166_4 v_idx_489) (= (select |c_#memory_int| v_idx_489) v_v_1388_4)) (or (<= v_b_169_4 v_idx_492) (< v_idx_492 v_b_168_4) (= (select |c_#memory_int| v_idx_492) 0)) (<= v_b_173_4 c_ULTIMATE.start_main_p6) (<= v_b_171_4 v_b_172_4) (<= .cse7 v_b_169_4) (<= v_b_169_4 v_b_170_4) (<= .cse3 v_b_170_4) (<= .cse8 v_b_171_4) (<= .cse9 v_b_172_4) (<= .cse4 c_ULTIMATE.start_main_p6) (<= v_b_171_4 .cse10) (<= .cse11 v_b_173_4) (<= .cse8 v_b_172_4) (<= .cse12 v_b_173_4) (<= .cse13 c_ULTIMATE.start_main_p6) (<= .cse5 v_b_173_4) (<= .cse14 c_ULTIMATE.start_main_p6) (<= .cse7 v_b_170_4) (<= .cse6 v_b_166_4) (<= .cse0 v_b_167_4) (<= .cse10 v_b_171_4) (<= v_v_1397_4 0) (<= .cse14 v_b_173_4) (<= v_b_167_4 .cse0) (<= .cse15 v_b_173_4) (<= .cse16 v_b_169_4) (<= .cse12 c_ULTIMATE.start_main_p6) (<= .cse17 v_b_171_4) (<= .cse10 v_b_172_4) (<= .cse18 v_b_171_4) (<= .cse19 v_b_168_4) (or (< v_idx_491 v_b_167_4) (<= v_b_168_4 v_idx_491) (= (select |c_#memory_int| v_idx_491) v_v_1390_4)) (or (<= .cse6 v_idx_488) (< v_idx_488 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_488) 0)) (or (<= v_b_170_4 v_idx_493) (< v_idx_493 v_b_169_4) (= (select |c_#memory_int| v_idx_493) v_v_1392_4)) (<= .cse19 v_b_167_4) (<= .cse2 v_b_170_4) (<= .cse17 v_b_172_4) (<= .cse20 v_b_172_4) (<= .cse18 v_b_172_4) (or (<= v_b_172_4 v_idx_495) (< v_idx_495 v_b_171_4) (= (select |c_#memory_int| v_idx_495) v_v_1394_4)) (<= .cse15 c_ULTIMATE.start_main_p6) (<= v_b_173_4 .cse13) (<= .cse3 v_b_169_4) (<= .cse21 c_ULTIMATE.start_main_p6) (or (<= v_b_171_4 v_idx_494) (< v_idx_494 v_b_170_4) (= (select |c_#memory_int| v_idx_494) 0)) (or (= (select |c_#memory_int| v_idx_487) v_v_1386_4) (<= c_ULTIMATE.start_main_p1 v_idx_487)) (or (<= v_b_173_4 v_idx_496) (= (select |c_#memory_int| v_idx_496) 0) (< v_idx_496 v_b_172_4)) (<= v_b_167_4 v_b_168_4) (<= .cse13 v_b_173_4) (<= .cse9 v_b_171_4) (<= .cse21 v_b_173_4) (or (= (select |c_#memory_int| v_idx_499) v_v_1398_4) (< v_idx_499 .cse1)) (<= (* 2 v_v_1397_4) 0) (or (<= c_ULTIMATE.start_main_p6 v_idx_497) (= (select |c_#memory_int| v_idx_497) v_v_1396_4) (< v_idx_497 v_b_173_4)) (<= .cse20 v_b_171_4) (<= .cse16 v_b_170_4) (<= .cse11 c_ULTIMATE.start_main_p6))))) is different from false [2019-01-08 14:38:00,350 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_508 Int) (v_idx_509 Int) (v_idx_506 Int) (v_idx_507 Int) (v_idx_500 Int) (v_idx_511 Int) (v_idx_501 Int) (v_idx_512 Int) (v_idx_510 Int) (v_idx_504 Int) (v_idx_505 Int) (v_idx_502 Int) (v_idx_503 Int)) (exists ((v_v_1398_4 Int) (v_v_1388_4 Int) (v_b_169_4 Int) (v_v_1396_4 Int) (v_b_168_4 Int) (v_v_1397_4 Int) (v_v_1386_4 Int) (v_b_167_4 Int) (v_v_1394_4 Int) (v_b_166_4 Int) (v_v_1392_4 Int) (v_v_1390_4 Int) (v_b_170_4 Int) (v_b_171_4 Int) (v_b_172_4 Int) (v_b_173_4 Int) (v_b_174_4 Int) (v_b_175_4 Int)) (let ((.cse2 (+ v_b_169_4 2)) (.cse5 (+ v_b_166_4 3)) (.cse6 (+ v_b_171_4 1)) (.cse4 (+ v_b_166_4 2)) (.cse0 (+ v_b_166_4 1)) (.cse10 (+ v_b_170_4 1)) (.cse19 (+ c_ULTIMATE.start_main_p1 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse15 (+ c_ULTIMATE.start_main_p1 5)) (.cse17 (+ v_b_167_4 2)) (.cse18 (+ v_b_169_4 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 1)) (.cse14 (+ v_b_167_4 3)) (.cse3 (+ v_b_168_4 1)) (.cse12 (+ v_b_166_4 4)) (.cse7 (+ v_b_174_4 1)) (.cse13 (+ v_b_172_4 1)) (.cse8 (+ v_b_168_4 2)) (.cse20 (+ v_b_170_4 2)) (.cse21 (+ c_ULTIMATE.start_main_p1 4)) (.cse16 (+ v_b_167_4 1)) (.cse11 (+ v_b_168_4 3))) (and (<= .cse0 v_b_168_4) (<= .cse1 v_b_169_4) (<= .cse2 v_b_174_4) (<= v_b_169_4 .cse3) (<= (+ v_b_171_4 2) v_b_175_4) (<= .cse2 v_b_173_4) (<= (+ v_b_170_4 3) v_b_175_4) (<= v_b_171_4 v_b_172_4) (<= .cse4 v_b_169_4) (<= v_b_169_4 v_b_170_4) (<= v_b_173_4 v_b_174_4) (<= .cse3 v_b_170_4) (<= .cse5 v_b_171_4) (<= .cse6 v_b_174_4) (<= .cse7 v_b_175_4) (<= .cse8 v_b_172_4) (or (= 0 (select |c_#memory_int| v_idx_501)) (<= .cse9 v_idx_501) (< v_idx_501 c_ULTIMATE.start_main_p1)) (or (= (select |c_#memory_int| v_idx_512) v_v_1398_4) (< v_idx_512 v_b_175_4)) (<= v_b_171_4 .cse10) (or (<= v_b_167_4 v_idx_503) (< v_idx_503 v_b_166_4) (= 0 (select |c_#memory_int| v_idx_503))) (<= .cse11 v_b_173_4) (<= .cse5 v_b_172_4) (<= .cse12 v_b_173_4) (or (<= v_b_169_4 v_idx_505) (= 0 (select |c_#memory_int| v_idx_505)) (< v_idx_505 v_b_168_4)) (<= .cse6 v_b_173_4) (<= .cse13 v_b_174_4) (<= .cse4 v_b_170_4) (<= .cse9 v_b_166_4) (<= .cse0 v_b_167_4) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_4) (<= .cse10 v_b_171_4) (<= v_v_1397_4 0) (or (= (select |c_#memory_int| v_idx_504) v_v_1390_4) (< v_idx_504 v_b_167_4) (<= v_b_168_4 v_idx_504)) (<= .cse14 v_b_173_4) (<= v_b_167_4 .cse0) (<= .cse15 v_b_173_4) (<= .cse16 v_b_169_4) (or (< v_idx_506 v_b_169_4) (= (select |c_#memory_int| v_idx_506) v_v_1392_4) (<= v_b_170_4 v_idx_506)) (<= .cse17 v_b_171_4) (<= .cse10 v_b_172_4) (<= .cse18 v_b_171_4) (<= .cse19 v_b_168_4) (<= .cse19 v_b_167_4) (<= .cse1 v_b_170_4) (<= .cse15 v_b_174_4) (<= .cse17 v_b_172_4) (or (<= v_b_174_4 v_idx_510) (= (select |c_#memory_int| v_idx_510) v_v_1396_4) (< v_idx_510 v_b_173_4)) (<= .cse20 v_b_174_4) (<= .cse21 v_b_172_4) (<= .cse18 v_b_172_4) (<= (+ v_b_172_4 2) v_b_175_4) (<= v_b_173_4 .cse13) (or (= (select |c_#memory_int| v_idx_502) v_v_1388_4) (< v_idx_502 .cse9) (<= v_b_166_4 v_idx_502)) (<= .cse14 v_b_174_4) (<= (+ v_b_173_4 1) v_b_175_4) (<= .cse3 v_b_169_4) (<= .cse12 v_b_174_4) (<= v_b_175_4 .cse7) (<= v_b_167_4 v_b_168_4) (<= .cse13 v_b_173_4) (<= .cse8 v_b_171_4) (or (< v_idx_508 v_b_171_4) (= (select |c_#memory_int| v_idx_508) v_v_1394_4) (<= v_b_172_4 v_idx_508)) (<= (+ v_b_169_4 3) v_b_175_4) (<= .cse20 v_b_173_4) (or (< v_idx_511 v_b_174_4) (= (select |c_#memory_int| v_idx_511) v_v_1397_4) (<= v_b_175_4 v_idx_511)) (<= (+ v_b_167_4 4) v_b_175_4) (<= (+ v_b_166_4 5) v_b_175_4) (<= (* 2 v_v_1397_4) 0) (<= (+ v_b_168_4 4) v_b_175_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_500) (= (select |c_#memory_int| v_idx_500) v_v_1386_4)) (or (<= v_b_173_4 v_idx_509) (= 0 (select |c_#memory_int| v_idx_509)) (< v_idx_509 v_b_172_4)) (<= .cse21 v_b_171_4) (<= .cse16 v_b_170_4) (<= .cse11 v_b_174_4) (or (= 0 (select |c_#memory_int| v_idx_507)) (< v_idx_507 v_b_170_4) (<= v_b_171_4 v_idx_507)))))) is different from false [2019-01-08 14:38:00,570 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:38:00,570 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:38:00,570 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:38:00,570 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:38:00,571 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:38:00,571 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:38:00,571 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:38:00,571 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-08 14:38:00,572 INFO L87 Difference]: Start difference. First operand 15 states and 32 transitions. Second operand 4 states. [2019-01-08 14:38:03,720 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_489 Int) (v_idx_487 Int) (v_idx_498 Int) (v_idx_488 Int) (v_idx_499 Int) (v_idx_492 Int) (v_idx_493 Int) (v_idx_490 Int) (v_idx_491 Int) (v_idx_496 Int) (v_idx_497 Int) (v_idx_494 Int) (v_idx_495 Int)) (exists ((v_v_1398_4 Int) (v_v_1388_4 Int) (v_b_169_4 Int) (v_v_1396_4 Int) (v_b_168_4 Int) (v_v_1397_4 Int) (v_v_1386_4 Int) (v_b_167_4 Int) (v_v_1394_4 Int) (v_b_166_4 Int) (v_v_1392_4 Int) (v_v_1390_4 Int) (v_b_170_4 Int) (v_b_171_4 Int) (v_b_172_4 Int) (v_b_173_4 Int)) (let ((.cse4 (+ v_b_169_4 2)) (.cse8 (+ v_b_166_4 3)) (.cse5 (+ v_b_171_4 1)) (.cse7 (+ v_b_166_4 2)) (.cse14 (+ v_b_167_4 3)) (.cse0 (+ v_b_166_4 1)) (.cse12 (+ v_b_166_4 4)) (.cse10 (+ v_b_170_4 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 1)) (.cse19 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ c_ULTIMATE.start_main_p1 3)) (.cse17 (+ v_b_167_4 2)) (.cse18 (+ v_b_169_4 1)) (.cse15 (+ c_ULTIMATE.start_main_p1 5)) (.cse3 (+ v_b_168_4 1)) (.cse13 (+ v_b_172_4 1)) (.cse9 (+ v_b_168_4 2)) (.cse21 (+ v_b_170_4 2)) (.cse1 (+ c_ULTIMATE.start_main_p6 1)) (.cse20 (+ c_ULTIMATE.start_main_p1 4)) (.cse16 (+ v_b_167_4 1)) (.cse11 (+ v_b_168_4 3))) (and (<= .cse0 v_b_168_4) (or (= (select |c_#memory_int| v_idx_490) 0) (<= v_b_167_4 v_idx_490) (< v_idx_490 v_b_166_4)) (or (= (select |c_#memory_int| v_idx_498) v_v_1397_4) (< v_idx_498 c_ULTIMATE.start_main_p6) (<= .cse1 v_idx_498)) (<= .cse2 v_b_169_4) (<= v_b_169_4 .cse3) (<= .cse4 v_b_173_4) (<= .cse5 c_ULTIMATE.start_main_p6) (or (< v_idx_489 .cse6) (<= v_b_166_4 v_idx_489) (= (select |c_#memory_int| v_idx_489) v_v_1388_4)) (or (<= v_b_169_4 v_idx_492) (< v_idx_492 v_b_168_4) (= (select |c_#memory_int| v_idx_492) 0)) (<= v_b_173_4 c_ULTIMATE.start_main_p6) (<= v_b_171_4 v_b_172_4) (<= .cse7 v_b_169_4) (<= v_b_169_4 v_b_170_4) (<= .cse3 v_b_170_4) (<= .cse8 v_b_171_4) (<= .cse9 v_b_172_4) (<= .cse4 c_ULTIMATE.start_main_p6) (<= v_b_171_4 .cse10) (<= .cse11 v_b_173_4) (<= .cse8 v_b_172_4) (<= .cse12 v_b_173_4) (<= .cse13 c_ULTIMATE.start_main_p6) (<= .cse5 v_b_173_4) (<= .cse14 c_ULTIMATE.start_main_p6) (<= .cse7 v_b_170_4) (<= .cse6 v_b_166_4) (<= .cse0 v_b_167_4) (<= .cse10 v_b_171_4) (<= v_v_1397_4 0) (<= .cse14 v_b_173_4) (<= v_b_167_4 .cse0) (<= .cse15 v_b_173_4) (<= .cse16 v_b_169_4) (<= .cse12 c_ULTIMATE.start_main_p6) (<= .cse17 v_b_171_4) (<= .cse10 v_b_172_4) (<= .cse18 v_b_171_4) (<= .cse19 v_b_168_4) (or (< v_idx_491 v_b_167_4) (<= v_b_168_4 v_idx_491) (= (select |c_#memory_int| v_idx_491) v_v_1390_4)) (or (<= .cse6 v_idx_488) (< v_idx_488 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_488) 0)) (or (<= v_b_170_4 v_idx_493) (< v_idx_493 v_b_169_4) (= (select |c_#memory_int| v_idx_493) v_v_1392_4)) (<= .cse19 v_b_167_4) (<= .cse2 v_b_170_4) (<= .cse17 v_b_172_4) (<= .cse20 v_b_172_4) (<= .cse18 v_b_172_4) (or (<= v_b_172_4 v_idx_495) (< v_idx_495 v_b_171_4) (= (select |c_#memory_int| v_idx_495) v_v_1394_4)) (<= .cse15 c_ULTIMATE.start_main_p6) (<= v_b_173_4 .cse13) (<= .cse3 v_b_169_4) (<= .cse21 c_ULTIMATE.start_main_p6) (or (<= v_b_171_4 v_idx_494) (< v_idx_494 v_b_170_4) (= (select |c_#memory_int| v_idx_494) 0)) (or (= (select |c_#memory_int| v_idx_487) v_v_1386_4) (<= c_ULTIMATE.start_main_p1 v_idx_487)) (or (<= v_b_173_4 v_idx_496) (= (select |c_#memory_int| v_idx_496) 0) (< v_idx_496 v_b_172_4)) (<= v_b_167_4 v_b_168_4) (<= .cse13 v_b_173_4) (<= .cse9 v_b_171_4) (<= .cse21 v_b_173_4) (or (= (select |c_#memory_int| v_idx_499) v_v_1398_4) (< v_idx_499 .cse1)) (<= (* 2 v_v_1397_4) 0) (or (<= c_ULTIMATE.start_main_p6 v_idx_497) (= (select |c_#memory_int| v_idx_497) v_v_1396_4) (< v_idx_497 v_b_173_4)) (<= .cse20 v_b_171_4) (<= .cse16 v_b_170_4) (<= .cse11 c_ULTIMATE.start_main_p6))))) (forall ((v_idx_508 Int) (v_idx_509 Int) (v_idx_506 Int) (v_idx_507 Int) (v_idx_500 Int) (v_idx_511 Int) (v_idx_501 Int) (v_idx_512 Int) (v_idx_510 Int) (v_idx_504 Int) (v_idx_505 Int) (v_idx_502 Int) (v_idx_503 Int)) (exists ((v_v_1398_4 Int) (v_v_1388_4 Int) (v_b_169_4 Int) (v_v_1396_4 Int) (v_b_168_4 Int) (v_v_1397_4 Int) (v_v_1386_4 Int) (v_b_167_4 Int) (v_v_1394_4 Int) (v_b_166_4 Int) (v_v_1392_4 Int) (v_v_1390_4 Int) (v_b_170_4 Int) (v_b_171_4 Int) (v_b_172_4 Int) (v_b_173_4 Int) (v_b_174_4 Int) (v_b_175_4 Int)) (let ((.cse24 (+ v_b_169_4 2)) (.cse27 (+ v_b_166_4 3)) (.cse28 (+ v_b_171_4 1)) (.cse26 (+ v_b_166_4 2)) (.cse22 (+ v_b_166_4 1)) (.cse32 (+ v_b_170_4 1)) (.cse41 (+ c_ULTIMATE.start_main_p1 2)) (.cse23 (+ c_ULTIMATE.start_main_p1 3)) (.cse37 (+ c_ULTIMATE.start_main_p1 5)) (.cse39 (+ v_b_167_4 2)) (.cse40 (+ v_b_169_4 1)) (.cse31 (+ c_ULTIMATE.start_main_p1 1)) (.cse36 (+ v_b_167_4 3)) (.cse25 (+ v_b_168_4 1)) (.cse34 (+ v_b_166_4 4)) (.cse29 (+ v_b_174_4 1)) (.cse35 (+ v_b_172_4 1)) (.cse30 (+ v_b_168_4 2)) (.cse42 (+ v_b_170_4 2)) (.cse43 (+ c_ULTIMATE.start_main_p1 4)) (.cse38 (+ v_b_167_4 1)) (.cse33 (+ v_b_168_4 3))) (and (<= .cse22 v_b_168_4) (<= .cse23 v_b_169_4) (<= .cse24 v_b_174_4) (<= v_b_169_4 .cse25) (<= (+ v_b_171_4 2) v_b_175_4) (<= .cse24 v_b_173_4) (<= (+ v_b_170_4 3) v_b_175_4) (<= v_b_171_4 v_b_172_4) (<= .cse26 v_b_169_4) (<= v_b_169_4 v_b_170_4) (<= v_b_173_4 v_b_174_4) (<= .cse25 v_b_170_4) (<= .cse27 v_b_171_4) (<= .cse28 v_b_174_4) (<= .cse29 v_b_175_4) (<= .cse30 v_b_172_4) (or (= 0 (select |c_#memory_int| v_idx_501)) (<= .cse31 v_idx_501) (< v_idx_501 c_ULTIMATE.start_main_p1)) (or (= (select |c_#memory_int| v_idx_512) v_v_1398_4) (< v_idx_512 v_b_175_4)) (<= v_b_171_4 .cse32) (or (<= v_b_167_4 v_idx_503) (< v_idx_503 v_b_166_4) (= 0 (select |c_#memory_int| v_idx_503))) (<= .cse33 v_b_173_4) (<= .cse27 v_b_172_4) (<= .cse34 v_b_173_4) (or (<= v_b_169_4 v_idx_505) (= 0 (select |c_#memory_int| v_idx_505)) (< v_idx_505 v_b_168_4)) (<= .cse28 v_b_173_4) (<= .cse35 v_b_174_4) (<= .cse26 v_b_170_4) (<= .cse31 v_b_166_4) (<= .cse22 v_b_167_4) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_4) (<= .cse32 v_b_171_4) (<= v_v_1397_4 0) (or (= (select |c_#memory_int| v_idx_504) v_v_1390_4) (< v_idx_504 v_b_167_4) (<= v_b_168_4 v_idx_504)) (<= .cse36 v_b_173_4) (<= v_b_167_4 .cse22) (<= .cse37 v_b_173_4) (<= .cse38 v_b_169_4) (or (< v_idx_506 v_b_169_4) (= (select |c_#memory_int| v_idx_506) v_v_1392_4) (<= v_b_170_4 v_idx_506)) (<= .cse39 v_b_171_4) (<= .cse32 v_b_172_4) (<= .cse40 v_b_171_4) (<= .cse41 v_b_168_4) (<= .cse41 v_b_167_4) (<= .cse23 v_b_170_4) (<= .cse37 v_b_174_4) (<= .cse39 v_b_172_4) (or (<= v_b_174_4 v_idx_510) (= (select |c_#memory_int| v_idx_510) v_v_1396_4) (< v_idx_510 v_b_173_4)) (<= .cse42 v_b_174_4) (<= .cse43 v_b_172_4) (<= .cse40 v_b_172_4) (<= (+ v_b_172_4 2) v_b_175_4) (<= v_b_173_4 .cse35) (or (= (select |c_#memory_int| v_idx_502) v_v_1388_4) (< v_idx_502 .cse31) (<= v_b_166_4 v_idx_502)) (<= .cse36 v_b_174_4) (<= (+ v_b_173_4 1) v_b_175_4) (<= .cse25 v_b_169_4) (<= .cse34 v_b_174_4) (<= v_b_175_4 .cse29) (<= v_b_167_4 v_b_168_4) (<= .cse35 v_b_173_4) (<= .cse30 v_b_171_4) (or (< v_idx_508 v_b_171_4) (= (select |c_#memory_int| v_idx_508) v_v_1394_4) (<= v_b_172_4 v_idx_508)) (<= (+ v_b_169_4 3) v_b_175_4) (<= .cse42 v_b_173_4) (or (< v_idx_511 v_b_174_4) (= (select |c_#memory_int| v_idx_511) v_v_1397_4) (<= v_b_175_4 v_idx_511)) (<= (+ v_b_167_4 4) v_b_175_4) (<= (+ v_b_166_4 5) v_b_175_4) (<= (* 2 v_v_1397_4) 0) (<= (+ v_b_168_4 4) v_b_175_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_500) (= (select |c_#memory_int| v_idx_500) v_v_1386_4)) (or (<= v_b_173_4 v_idx_509) (= 0 (select |c_#memory_int| v_idx_509)) (< v_idx_509 v_b_172_4)) (<= .cse43 v_b_171_4) (<= .cse38 v_b_170_4) (<= .cse33 v_b_174_4) (or (= 0 (select |c_#memory_int| v_idx_507)) (< v_idx_507 v_b_170_4) (<= v_b_171_4 v_idx_507))))))) is different from false [2019-01-08 14:38:22,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:38:22,478 INFO L93 Difference]: Finished difference Result 17 states and 40 transitions. [2019-01-08 14:38:22,478 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-08 14:38:22,478 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-08 14:38:22,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:38:22,479 INFO L225 Difference]: With dead ends: 17 [2019-01-08 14:38:22,479 INFO L226 Difference]: Without dead ends: 16 [2019-01-08 14:38:22,479 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 8.6s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:38:22,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-08 14:38:22,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2019-01-08 14:38:22,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-08 14:38:22,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 32 transitions. [2019-01-08 14:38:22,491 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 32 transitions. Word has length 3 [2019-01-08 14:38:22,491 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:38:22,491 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 32 transitions. [2019-01-08 14:38:22,492 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:38:22,492 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 32 transitions. [2019-01-08 14:38:22,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:38:22,492 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:38:22,492 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:38:22,493 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:38:22,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:38:22,493 INFO L82 PathProgramCache]: Analyzing trace with hash 30128, now seen corresponding path program 1 times [2019-01-08 14:38:22,493 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:38:22,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:22,494 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:38:22,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:22,495 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:38:22,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:38:22,565 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:38:22,566 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:38:22,566 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:38:22,566 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:38:22,566 INFO L207 CegarAbsIntRunner]: [0], [10], [27] [2019-01-08 14:38:22,567 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:38:22,568 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:38:33,223 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:38:33,224 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:38:33,224 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:38:33,224 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:38:33,705 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 75% of their original sizes. [2019-01-08 14:38:33,706 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:38:36,108 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_618 Int) (v_idx_619 Int) (v_idx_627 Int) (v_idx_616 Int) (v_idx_617 Int) (v_idx_621 Int) (v_idx_622 Int) (v_idx_620 Int) (v_idx_625 Int) (v_idx_626 Int) (v_idx_615 Int) (v_idx_623 Int) (v_idx_624 Int)) (exists ((v_v_1833_5 Int) (v_v_1830_5 Int) (v_v_1831_5 Int) (v_b_157_5 Int) (v_b_156_5 Int) (v_b_155_5 Int) (v_b_154_5 Int) (v_b_159_5 Int) (v_b_158_5 Int) (v_b_153_5 Int) (v_b_152_5 Int) (v_v_1837_5 Int) (v_v_1835_5 Int) (v_v_1829_5 Int) (v_v_1827_5 Int) (v_v_1839_5 Int)) (let ((.cse3 (+ v_b_153_5 1)) (.cse1 (+ v_b_154_5 2)) (.cse12 (+ v_b_152_5 3)) (.cse15 (+ c_ULTIMATE.start_main_p2 3)) (.cse2 (+ v_b_158_5 1)) (.cse8 (+ c_ULTIMATE.start_main_p2 4)) (.cse10 (+ c_ULTIMATE.start_main_p1 3)) (.cse9 (+ c_ULTIMATE.start_main_p2 2)) (.cse11 (+ v_b_152_5 1)) (.cse6 (+ v_b_154_5 1)) (.cse5 (+ v_b_155_5 1)) (.cse13 (+ c_ULTIMATE.start_main_p1 5)) (.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse16 (+ c_ULTIMATE.start_main_p1 4)) (.cse0 (+ v_b_153_5 2)) (.cse17 (+ v_b_152_5 2)) (.cse7 (+ v_b_156_5 1)) (.cse14 (+ c_ULTIMATE.start_main_p1 1))) (and (<= .cse0 v_b_157_5) (<= .cse1 v_b_158_5) (or (= (select |c_#memory_int| v_idx_615) v_v_1827_5) (<= c_ULTIMATE.start_main_p1 v_idx_615)) (or (< v_idx_620 v_b_152_5) (= (select |c_#memory_int| v_idx_620) 0) (<= v_b_153_5 v_idx_620)) (<= .cse2 v_b_159_5) (<= .cse3 v_b_155_5) (or (< v_idx_618 c_ULTIMATE.start_main_p2) (<= .cse4 v_idx_618) (= (select |c_#memory_int| v_idx_618) v_v_1830_5)) (<= .cse5 v_b_158_5) (<= (+ v_b_154_5 3) v_b_159_5) (<= (+ v_b_152_5 4) v_b_159_5) (<= v_b_155_5 .cse6) (<= .cse7 v_b_158_5) (<= .cse8 v_b_157_5) (<= .cse9 v_b_153_5) (<= v_v_1830_5 0) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_5) (<= .cse10 v_b_154_5) (<= (* 2 v_v_1830_5) 0) (or (= (select |c_#memory_int| v_idx_622) 0) (<= v_b_155_5 v_idx_622) (< v_idx_622 v_b_154_5)) (or (< v_idx_621 v_b_153_5) (<= v_b_154_5 v_idx_621) (= (select |c_#memory_int| v_idx_621) v_v_1833_5)) (<= .cse11 v_b_153_5) (<= .cse3 v_b_156_5) (<= .cse1 v_b_157_5) (<= (+ c_ULTIMATE.start_main_p2 5) v_b_159_5) (<= .cse12 v_b_157_5) (<= (+ v_b_156_5 2) v_b_159_5) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_152_5) (or (<= v_b_156_5 v_idx_623) (= (select |c_#memory_int| v_idx_623) v_v_1835_5) (< v_idx_623 v_b_155_5)) (<= .cse13 v_b_157_5) (<= (+ v_b_155_5 2) v_b_159_5) (<= .cse12 v_b_158_5) (or (< v_idx_617 .cse14) (= (select |c_#memory_int| v_idx_617) v_v_1829_5) (<= c_ULTIMATE.start_main_p2 v_idx_617)) (<= .cse15 v_b_155_5) (<= .cse15 v_b_156_5) (<= v_b_159_5 .cse2) (<= .cse8 v_b_158_5) (<= .cse10 v_b_153_5) (<= .cse16 v_b_155_5) (<= .cse4 v_b_152_5) (<= v_b_157_5 .cse7) (<= v_b_153_5 .cse11) (<= .cse9 v_b_154_5) (<= v_b_157_5 v_b_158_5) (<= .cse17 v_b_155_5) (<= v_b_153_5 v_b_154_5) (<= .cse6 v_b_156_5) (<= (+ v_b_157_5 1) v_b_159_5) (<= v_b_155_5 v_b_156_5) (<= .cse11 v_b_154_5) (<= .cse6 v_b_155_5) (or (< v_idx_624 v_b_156_5) (= (select |c_#memory_int| v_idx_624) 0) (<= v_b_157_5 v_idx_624)) (<= .cse5 v_b_157_5) (<= .cse13 v_b_158_5) (or (<= .cse14 v_idx_616) (= (select |c_#memory_int| v_idx_616) 0) (< v_idx_616 c_ULTIMATE.start_main_p1)) (or (= (select |c_#memory_int| v_idx_619) v_v_1831_5) (< v_idx_619 .cse4) (<= v_b_152_5 v_idx_619)) (<= .cse16 v_b_156_5) (or (<= v_b_158_5 v_idx_625) (= (select |c_#memory_int| v_idx_625) v_v_1837_5) (< v_idx_625 v_b_157_5)) (or (< v_idx_627 v_b_159_5) (= (select |c_#memory_int| v_idx_627) v_v_1839_5)) (<= (+ v_b_153_5 3) v_b_159_5) (<= .cse0 v_b_158_5) (<= .cse17 v_b_156_5) (<= .cse7 v_b_157_5) (or (= (select |c_#memory_int| v_idx_626) 0) (<= v_b_159_5 v_idx_626) (< v_idx_626 v_b_158_5)) (<= .cse14 c_ULTIMATE.start_main_p2))))) is different from false [2019-01-08 14:38:38,554 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_629 Int) (v_idx_638 Int) (v_idx_628 Int) (v_idx_639 Int) (v_idx_632 Int) (v_idx_633 Int) (v_idx_630 Int) (v_idx_631 Int) (v_idx_636 Int) (v_idx_637 Int) (v_idx_634 Int) (v_idx_635 Int) (v_idx_640 Int)) (exists ((v_v_1833_5 Int) (v_v_1830_5 Int) (v_v_1831_5 Int) (v_b_157_5 Int) (v_b_156_5 Int) (v_b_155_5 Int) (v_b_154_5 Int) (v_b_159_5 Int) (v_b_158_5 Int) (v_b_153_5 Int) (v_b_152_5 Int) (v_b_151_5 Int) (v_b_150_5 Int) (v_v_1837_5 Int) (v_v_1835_5 Int) (v_v_1829_5 Int) (v_v_1827_5 Int) (v_v_1839_5 Int)) (let ((.cse3 (+ v_b_153_5 1)) (.cse1 (+ v_b_154_5 2)) (.cse15 (+ v_b_152_5 3)) (.cse2 (+ v_b_158_5 1)) (.cse16 (+ c_ULTIMATE.start_main_p1 2)) (.cse9 (+ c_ULTIMATE.start_main_p1 3)) (.cse14 (+ v_b_151_5 2)) (.cse12 (+ v_b_150_5 4)) (.cse18 (+ v_b_151_5 1)) (.cse13 (+ v_b_152_5 1)) (.cse6 (+ v_b_154_5 1)) (.cse5 (+ v_b_155_5 1)) (.cse17 (+ c_ULTIMATE.start_main_p1 5)) (.cse7 (+ v_b_150_5 1)) (.cse11 (+ v_b_151_5 3)) (.cse20 (+ c_ULTIMATE.start_main_p1 4)) (.cse10 (+ v_b_150_5 3)) (.cse19 (+ v_b_150_5 2)) (.cse0 (+ v_b_153_5 2)) (.cse21 (+ v_b_152_5 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse8 (+ v_b_156_5 1))) (and (<= .cse0 v_b_157_5) (<= .cse1 v_b_158_5) (<= .cse2 v_b_159_5) (<= .cse3 v_b_155_5) (<= .cse4 v_b_150_5) (or (<= v_b_152_5 v_idx_632) (= (select |c_#memory_int| v_idx_632) v_v_1831_5) (< v_idx_632 v_b_151_5)) (<= .cse5 v_b_158_5) (<= (+ v_b_154_5 3) v_b_159_5) (or (<= v_b_151_5 v_idx_631) (= (select |c_#memory_int| v_idx_631) v_v_1830_5) (< v_idx_631 v_b_150_5)) (<= (+ v_b_152_5 4) v_b_159_5) (<= v_b_155_5 .cse6) (<= .cse7 v_b_151_5) (<= .cse8 v_b_158_5) (or (<= v_b_153_5 v_idx_633) (= 0 (select |c_#memory_int| v_idx_633)) (< v_idx_633 v_b_152_5)) (<= v_v_1830_5 0) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_5) (or (= (select |c_#memory_int| v_idx_629) 0) (<= .cse4 v_idx_629) (< v_idx_629 c_ULTIMATE.start_main_p1)) (<= .cse9 v_b_154_5) (<= .cse10 v_b_155_5) (<= (* 2 v_v_1830_5) 0) (<= .cse11 v_b_158_5) (<= .cse12 v_b_158_5) (<= .cse13 v_b_153_5) (<= .cse14 v_b_156_5) (<= .cse3 v_b_156_5) (<= .cse1 v_b_157_5) (<= .cse15 v_b_157_5) (<= (+ v_b_156_5 2) v_b_159_5) (<= .cse16 v_b_152_5) (<= .cse17 v_b_157_5) (<= (+ v_b_155_5 2) v_b_159_5) (<= .cse15 v_b_158_5) (<= .cse18 v_b_153_5) (<= v_b_151_5 .cse7) (<= v_b_159_5 .cse2) (or (<= c_ULTIMATE.start_main_p1 v_idx_628) (= (select |c_#memory_int| v_idx_628) v_v_1827_5)) (or (= 0 (select |c_#memory_int| v_idx_637)) (<= v_b_157_5 v_idx_637) (< v_idx_637 v_b_156_5)) (<= .cse16 v_b_151_5) (<= v_b_151_5 v_b_152_5) (<= .cse19 v_b_153_5) (<= .cse9 v_b_153_5) (<= .cse20 v_b_155_5) (<= v_b_157_5 .cse8) (<= v_b_153_5 .cse13) (<= v_b_157_5 v_b_158_5) (<= (+ v_b_151_5 4) v_b_159_5) (<= .cse14 v_b_155_5) (<= .cse21 v_b_155_5) (<= .cse12 v_b_157_5) (or (< v_idx_634 v_b_153_5) (= (select |c_#memory_int| v_idx_634) v_v_1833_5) (<= v_b_154_5 v_idx_634)) (<= .cse18 v_b_154_5) (<= v_b_153_5 v_b_154_5) (<= .cse6 v_b_156_5) (<= (+ v_b_157_5 1) v_b_159_5) (or (< v_idx_640 v_b_159_5) (= (select |c_#memory_int| v_idx_640) v_v_1839_5)) (or (= 0 (select |c_#memory_int| v_idx_639)) (< v_idx_639 v_b_158_5) (<= v_b_159_5 v_idx_639)) (<= v_b_155_5 v_b_156_5) (<= .cse13 v_b_154_5) (<= .cse6 v_b_155_5) (<= .cse5 v_b_157_5) (<= .cse17 v_b_158_5) (<= .cse7 v_b_152_5) (<= .cse11 v_b_157_5) (<= .cse20 v_b_156_5) (or (< v_idx_636 v_b_155_5) (= (select |c_#memory_int| v_idx_636) v_v_1835_5) (<= v_b_156_5 v_idx_636)) (or (<= v_b_155_5 v_idx_635) (= (select |c_#memory_int| v_idx_635) 0) (< v_idx_635 v_b_154_5)) (<= (+ v_b_153_5 3) v_b_159_5) (or (<= v_b_158_5 v_idx_638) (= (select |c_#memory_int| v_idx_638) v_v_1837_5) (< v_idx_638 v_b_157_5)) (<= .cse10 v_b_156_5) (<= .cse19 v_b_154_5) (<= .cse0 v_b_158_5) (<= .cse21 v_b_156_5) (or (< v_idx_630 .cse4) (= (select |c_#memory_int| v_idx_630) v_v_1829_5) (<= v_b_150_5 v_idx_630)) (<= .cse8 v_b_157_5) (<= (+ v_b_150_5 5) v_b_159_5))))) is different from false [2019-01-08 14:38:38,757 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:38:38,758 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:38:38,758 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:38:38,758 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:38:38,758 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:38:38,759 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:38:38,759 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:38:38,759 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-08 14:38:38,759 INFO L87 Difference]: Start difference. First operand 15 states and 32 transitions. Second operand 4 states.