java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml -s ../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf -i ../../../trunk/examples/programs/heapseparator/speedup-poc-dd-7-limited.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.24-f57a05f [2019-01-08 14:35:54,218 INFO L170 SettingsManager]: Resetting all preferences to default values... [2019-01-08 14:35:54,220 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2019-01-08 14:35:54,236 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2019-01-08 14:35:54,269 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf [2019-01-08 14:35:54,291 INFO L110 SettingsManager]: Loading preferences was successful [2019-01-08 14:35:54,291 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2019-01-08 14:35:54,292 INFO L131 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2019-01-08 14:35:54,293 INFO L133 SettingsManager]: * Show backtranslation warnings=false [2019-01-08 14:35:54,293 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-01-08 14:35:54,293 INFO L133 SettingsManager]: * User list type=DISABLED [2019-01-08 14:35:54,293 INFO L133 SettingsManager]: * Inline calls to unimplemented procedures=true [2019-01-08 14:35:54,293 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-01-08 14:35:54,294 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-01-08 14:35:54,294 INFO L133 SettingsManager]: * Underlying domain=OctagonDomain [2019-01-08 14:35:54,294 INFO L133 SettingsManager]: * Abstract domain=ArrayDomain [2019-01-08 14:35:54,294 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-01-08 14:35:54,294 INFO L133 SettingsManager]: * Interval Domain=false [2019-01-08 14:35:54,296 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-01-08 14:35:54,296 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2019-01-08 14:35:54,296 INFO L133 SettingsManager]: * Use SBE=true [2019-01-08 14:35:54,296 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-01-08 14:35:54,296 INFO L133 SettingsManager]: * sizeof long=4 [2019-01-08 14:35:54,298 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2019-01-08 14:35:54,299 INFO L133 SettingsManager]: * sizeof POINTER=4 [2019-01-08 14:35:54,299 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2019-01-08 14:35:54,299 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-01-08 14:35:54,299 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-01-08 14:35:54,299 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-01-08 14:35:54,300 INFO L133 SettingsManager]: * sizeof long double=12 [2019-01-08 14:35:54,300 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2019-01-08 14:35:54,300 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-01-08 14:35:54,300 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-01-08 14:35:54,300 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-01-08 14:35:54,301 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2019-01-08 14:35:54,301 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-08 14:35:54,301 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-01-08 14:35:54,301 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-01-08 14:35:54,301 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-01-08 14:35:54,302 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2019-01-08 14:35:54,302 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-01-08 14:35:54,302 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in [2019-01-08 14:35:54,302 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-01-08 14:35:54,302 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2019-01-08 14:35:54,332 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-01-08 14:35:54,345 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-01-08 14:35:54,348 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-01-08 14:35:54,350 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2019-01-08 14:35:54,351 INFO L276 PluginConnector]: Boogie PL CUP Parser initialized [2019-01-08 14:35:54,351 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-7-limited.bpl [2019-01-08 14:35:54,352 INFO L111 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-7-limited.bpl' [2019-01-08 14:35:54,391 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-01-08 14:35:54,393 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-01-08 14:35:54,394 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-01-08 14:35:54,394 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-01-08 14:35:54,394 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2019-01-08 14:35:54,410 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:54" (1/1) ... [2019-01-08 14:35:54,422 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:54" (1/1) ... [2019-01-08 14:35:54,450 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-01-08 14:35:54,451 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-01-08 14:35:54,451 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-01-08 14:35:54,452 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2019-01-08 14:35:54,463 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:54" (1/1) ... [2019-01-08 14:35:54,464 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:54" (1/1) ... [2019-01-08 14:35:54,466 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:54" (1/1) ... [2019-01-08 14:35:54,466 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:54" (1/1) ... [2019-01-08 14:35:54,470 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:54" (1/1) ... [2019-01-08 14:35:54,474 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:54" (1/1) ... [2019-01-08 14:35:54,475 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:54" (1/1) ... [2019-01-08 14:35:54,477 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-01-08 14:35:54,478 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-01-08 14:35:54,478 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-01-08 14:35:54,478 INFO L276 PluginConnector]: RCFGBuilder initialized [2019-01-08 14:35:54,479 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:54" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-08 14:35:54,551 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-01-08 14:35:54,552 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-01-08 14:35:55,020 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-01-08 14:35:55,021 INFO L286 CfgBuilder]: Removed 17 assue(true) statements. [2019-01-08 14:35:55,022 INFO L202 PluginConnector]: Adding new model speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.01 02:35:55 BoogieIcfgContainer [2019-01-08 14:35:55,023 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-01-08 14:35:55,024 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-01-08 14:35:55,024 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-01-08 14:35:55,027 INFO L276 PluginConnector]: TraceAbstraction initialized [2019-01-08 14:35:55,028 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 08.01 02:35:54" (1/2) ... [2019-01-08 14:35:55,029 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4eb46ff0 and model type speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.01 02:35:55, skipping insertion in model container [2019-01-08 14:35:55,029 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.01 02:35:55" (2/2) ... [2019-01-08 14:35:55,031 INFO L112 eAbstractionObserver]: Analyzing ICFG speedup-poc-dd-7-limited.bpl [2019-01-08 14:35:55,042 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-01-08 14:35:55,051 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 7 error locations. [2019-01-08 14:35:55,070 INFO L257 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-01-08 14:35:55,106 INFO L382 AbstractCegarLoop]: Interprodecural is true [2019-01-08 14:35:55,106 INFO L383 AbstractCegarLoop]: Hoare is true [2019-01-08 14:35:55,106 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-01-08 14:35:55,107 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-01-08 14:35:55,107 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-01-08 14:35:55,107 INFO L387 AbstractCegarLoop]: Difference is false [2019-01-08 14:35:55,107 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-01-08 14:35:55,107 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-01-08 14:35:55,124 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states. [2019-01-08 14:35:55,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3 [2019-01-08 14:35:55,131 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:35:55,132 INFO L402 BasicCegarLoop]: trace histogram [1, 1] [2019-01-08 14:35:55,135 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:35:55,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:35:55,142 INFO L82 PathProgramCache]: Analyzing trace with hash 992, now seen corresponding path program 1 times [2019-01-08 14:35:55,144 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:35:55,201 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:55,202 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:35:55,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:55,202 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:35:55,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:35:55,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:35:55,360 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-08 14:35:55,360 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-08 14:35:55,360 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:35:55,367 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-08 14:35:55,383 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-08 14:35:55,384 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:35:55,386 INFO L87 Difference]: Start difference. First operand 17 states. Second operand 3 states. [2019-01-08 14:35:55,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:35:55,635 INFO L93 Difference]: Finished difference Result 33 states and 45 transitions. [2019-01-08 14:35:55,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-08 14:35:55,638 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 2 [2019-01-08 14:35:55,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:35:55,652 INFO L225 Difference]: With dead ends: 33 [2019-01-08 14:35:55,652 INFO L226 Difference]: Without dead ends: 28 [2019-01-08 14:35:55,656 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:35:55,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2019-01-08 14:35:55,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 16. [2019-01-08 14:35:55,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2019-01-08 14:35:55,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 29 transitions. [2019-01-08 14:35:55,698 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 29 transitions. Word has length 2 [2019-01-08 14:35:55,699 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:35:55,700 INFO L480 AbstractCegarLoop]: Abstraction has 16 states and 29 transitions. [2019-01-08 14:35:55,700 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-08 14:35:55,700 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 29 transitions. [2019-01-08 14:35:55,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:35:55,701 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:35:55,701 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:35:55,702 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:35:55,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:35:55,702 INFO L82 PathProgramCache]: Analyzing trace with hash 30816, now seen corresponding path program 1 times [2019-01-08 14:35:55,702 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:35:55,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:55,704 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:35:55,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:55,704 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:35:55,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:35:55,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:35:55,801 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-08 14:35:55,802 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-08 14:35:55,802 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:35:55,804 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-08 14:35:55,804 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-08 14:35:55,804 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:35:55,805 INFO L87 Difference]: Start difference. First operand 16 states and 29 transitions. Second operand 3 states. [2019-01-08 14:35:56,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:35:56,106 INFO L93 Difference]: Finished difference Result 28 states and 40 transitions. [2019-01-08 14:35:56,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-08 14:35:56,106 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-01-08 14:35:56,107 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:35:56,108 INFO L225 Difference]: With dead ends: 28 [2019-01-08 14:35:56,108 INFO L226 Difference]: Without dead ends: 27 [2019-01-08 14:35:56,109 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-08 14:35:56,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2019-01-08 14:35:56,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 17. [2019-01-08 14:35:56,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2019-01-08 14:35:56,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 30 transitions. [2019-01-08 14:35:56,114 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 30 transitions. Word has length 3 [2019-01-08 14:35:56,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:35:56,114 INFO L480 AbstractCegarLoop]: Abstraction has 17 states and 30 transitions. [2019-01-08 14:35:56,115 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-08 14:35:56,115 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 30 transitions. [2019-01-08 14:35:56,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:35:56,115 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:35:56,115 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:35:56,116 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:35:56,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:35:56,116 INFO L82 PathProgramCache]: Analyzing trace with hash 30380, now seen corresponding path program 1 times [2019-01-08 14:35:56,117 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:35:56,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:56,118 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:35:56,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:35:56,118 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:35:56,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:35:56,315 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:35:56,315 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:35:56,316 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:35:56,317 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:35:56,319 INFO L207 CegarAbsIntRunner]: [0], [18], [31] [2019-01-08 14:35:56,384 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:35:56,385 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:36:11,663 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:36:11,665 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:36:11,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:36:11,672 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:36:12,620 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 77.27% of their original sizes. [2019-01-08 14:36:12,620 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:36:15,268 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_126 Int) (v_idx_115 Int) (v_idx_127 Int) (v_idx_116 Int) (v_idx_124 Int) (v_idx_125 Int) (v_idx_119 Int) (v_idx_128 Int) (v_idx_117 Int) (v_idx_129 Int) (v_idx_118 Int) (v_idx_122 Int) (v_idx_123 Int) (v_idx_120 Int) (v_idx_121 Int)) (exists ((v_v_1519_1 Int) (v_b_195_1 Int) (v_v_1521_1 Int) (v_b_184_1 Int) (v_b_194_1 Int) (v_b_185_1 Int) (v_b_186_1 Int) (v_b_187_1 Int) (v_v_1529_1 Int) (v_v_1517_1 Int) (v_v_1527_1 Int) (v_v_1515_1 Int) (v_b_191_1 Int) (v_v_1525_1 Int) (v_b_190_1 Int) (v_b_193_1 Int) (v_v_1523_1 Int) (v_b_192_1 Int) (v_v_1522_1 Int)) (let ((.cse14 (+ v_b_184_1 4)) (.cse4 (+ c_ULTIMATE.start_main_p4 2)) (.cse12 (+ v_b_184_1 2)) (.cse8 (+ c_ULTIMATE.start_main_p1 6)) (.cse16 (+ c_ULTIMATE.start_main_p4 1)) (.cse10 (+ v_b_186_1 4)) (.cse0 (+ v_b_184_1 5)) (.cse9 (+ v_b_185_1 1)) (.cse3 (+ v_b_190_1 2)) (.cse2 (+ v_b_192_1 1)) (.cse20 (+ v_b_187_1 2)) (.cse13 (+ c_ULTIMATE.start_main_p1 3)) (.cse17 (+ v_b_185_1 4)) (.cse19 (+ c_ULTIMATE.start_main_p1 2)) (.cse22 (+ v_b_191_1 1)) (.cse15 (+ v_b_187_1 3)) (.cse18 (+ v_b_185_1 3)) (.cse1 (+ v_b_190_1 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse24 (+ c_ULTIMATE.start_main_p4 3)) (.cse21 (+ v_b_186_1 3)) (.cse7 (+ v_b_184_1 1)) (.cse23 (+ v_b_194_1 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 5)) (.cse11 (+ v_b_186_1 1))) (and (or (<= v_b_186_1 v_idx_119) (< v_idx_119 v_b_185_1) (= (select |c_#memory_int| v_idx_119) v_v_1519_1)) (<= .cse0 v_b_193_1) (<= (+ v_b_184_1 6) v_b_195_1) (<= .cse1 v_b_192_1) (<= (+ v_b_191_1 2) v_b_195_1) (<= (+ v_b_185_1 5) v_b_195_1) (<= v_b_187_1 c_ULTIMATE.start_main_p4) (or (<= v_b_185_1 v_idx_118) (< v_idx_118 v_b_184_1) (= (select |c_#memory_int| v_idx_118) 0)) (<= v_b_193_1 .cse2) (<= (+ v_b_186_1 2) v_b_190_1) (<= v_b_193_1 v_b_194_1) (<= (+ v_b_184_1 3) v_b_190_1) (<= .cse3 v_b_193_1) (<= .cse4 v_b_191_1) (or (<= v_b_192_1 v_idx_125) (= (select |c_#memory_int| v_idx_125) v_v_1525_1) (< v_idx_125 v_b_191_1)) (or (= (select |c_#memory_int| v_idx_116) 0) (< v_idx_116 c_ULTIMATE.start_main_p1) (<= .cse5 v_idx_116)) (or (< v_idx_124 v_b_190_1) (<= v_b_191_1 v_idx_124) (= (select |c_#memory_int| v_idx_124) 0)) (<= (+ v_b_187_1 1) v_b_190_1) (<= .cse6 v_b_191_1) (<= .cse7 v_b_186_1) (<= v_v_1522_1 0) (<= .cse8 v_b_194_1) (<= v_b_185_1 .cse7) (<= .cse9 v_b_187_1) (<= .cse10 v_b_193_1) (<= .cse2 v_b_194_1) (<= v_b_187_1 .cse11) (<= .cse12 c_ULTIMATE.start_main_p4) (or (< v_idx_127 v_b_193_1) (<= v_b_194_1 v_idx_127) (= (select |c_#memory_int| v_idx_127) v_v_1527_1)) (<= (+ v_b_187_1 4) v_b_195_1) (<= .cse13 v_b_187_1) (<= v_b_191_1 .cse1) (<= .cse14 v_b_191_1) (or (= (select |c_#memory_int| v_idx_120) 0) (<= v_b_187_1 v_idx_120) (< v_idx_120 v_b_186_1)) (<= (+ v_b_186_1 5) v_b_195_1) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_1) (<= (+ v_b_193_1 1) v_b_195_1) (<= .cse14 v_b_192_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_115) (= (select |c_#memory_int| v_idx_115) v_v_1515_1)) (<= .cse4 v_b_192_1) (or (= (select |c_#memory_int| v_idx_121) v_v_1521_1) (< v_idx_121 v_b_187_1) (<= c_ULTIMATE.start_main_p4 v_idx_121)) (<= .cse15 v_b_194_1) (<= .cse16 v_b_190_1) (<= .cse12 v_b_187_1) (<= .cse8 v_b_193_1) (<= (+ v_b_185_1 2) v_b_190_1) (<= (+ v_b_190_1 3) v_b_195_1) (or (< v_idx_122 c_ULTIMATE.start_main_p4) (= (select |c_#memory_int| v_idx_122) v_v_1522_1) (<= .cse16 v_idx_122)) (or (< v_idx_123 .cse16) (<= v_b_190_1 v_idx_123) (= (select |c_#memory_int| v_idx_123) v_v_1523_1)) (<= .cse10 v_b_194_1) (<= .cse0 v_b_194_1) (<= .cse17 v_b_194_1) (<= .cse18 v_b_192_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_190_1) (<= .cse9 c_ULTIMATE.start_main_p4) (<= .cse19 v_b_186_1) (or (< v_idx_128 v_b_194_1) (<= v_b_195_1 v_idx_128) (= (select |c_#memory_int| v_idx_128) 0)) (<= .cse3 v_b_194_1) (<= .cse2 v_b_193_1) (<= .cse20 v_b_191_1) (or (= (select |c_#memory_int| v_idx_117) v_v_1517_1) (< v_idx_117 .cse5) (<= v_b_184_1 v_idx_117)) (<= .cse20 v_b_192_1) (<= .cse21 v_b_191_1) (<= .cse22 v_b_194_1) (<= .cse13 c_ULTIMATE.start_main_p4) (<= .cse17 v_b_193_1) (<= .cse11 v_b_187_1) (<= .cse19 v_b_185_1) (<= v_b_195_1 .cse23) (<= .cse22 v_b_193_1) (<= (+ v_b_192_1 2) v_b_195_1) (<= .cse15 v_b_193_1) (or (< v_idx_126 v_b_192_1) (= 0 (select |c_#memory_int| v_idx_126)) (<= v_b_193_1 v_idx_126)) (<= (* 2 v_v_1522_1) 0) (<= .cse18 v_b_191_1) (<= .cse24 v_b_194_1) (<= .cse1 v_b_191_1) (<= .cse5 v_b_184_1) (<= .cse24 v_b_193_1) (<= .cse21 v_b_192_1) (<= .cse7 v_b_185_1) (<= v_b_185_1 v_b_186_1) (<= .cse23 v_b_195_1) (<= .cse6 v_b_192_1) (<= .cse11 c_ULTIMATE.start_main_p4) (<= v_b_191_1 v_b_192_1) (or (< v_idx_129 v_b_195_1) (= (select |c_#memory_int| v_idx_129) v_v_1529_1)) (<= (+ c_ULTIMATE.start_main_p4 4) v_b_195_1))))) is different from false [2019-01-08 14:36:17,620 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_137 Int) (v_idx_138 Int) (v_idx_135 Int) (v_idx_136 Int) (v_idx_139 Int) (v_idx_140 Int) (v_idx_141 Int) (v_idx_130 Int) (v_idx_144 Int) (v_idx_133 Int) (v_idx_134 Int) (v_idx_142 Int) (v_idx_131 Int) (v_idx_143 Int) (v_idx_132 Int)) (exists ((v_v_1519_1 Int) (v_b_195_1 Int) (v_v_1521_1 Int) (v_b_184_1 Int) (v_b_194_1 Int) (v_b_185_1 Int) (v_b_186_1 Int) (v_b_187_1 Int) (v_b_188_1 Int) (v_b_189_1 Int) (v_v_1529_1 Int) (v_v_1517_1 Int) (v_v_1527_1 Int) (v_v_1515_1 Int) (v_b_191_1 Int) (v_v_1525_1 Int) (v_b_190_1 Int) (v_b_193_1 Int) (v_v_1523_1 Int) (v_b_192_1 Int) (v_v_1522_1 Int)) (let ((.cse4 (+ v_b_189_1 2)) (.cse11 (+ c_ULTIMATE.start_main_p1 3)) (.cse15 (+ v_b_184_1 2)) (.cse18 (+ v_b_184_1 5)) (.cse16 (+ v_b_185_1 2)) (.cse7 (+ v_b_189_1 1)) (.cse17 (+ v_b_188_1 1)) (.cse1 (+ v_b_186_1 2)) (.cse2 (+ v_b_184_1 3)) (.cse19 (+ v_b_190_1 2)) (.cse20 (+ v_b_187_1 1)) (.cse3 (+ v_b_188_1 3)) (.cse13 (+ v_b_185_1 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 1)) (.cse28 (+ v_b_184_1 4)) (.cse27 (+ c_ULTIMATE.start_main_p1 6)) (.cse8 (+ v_b_186_1 4)) (.cse21 (+ v_b_185_1 4)) (.cse23 (+ v_b_185_1 3)) (.cse25 (+ c_ULTIMATE.start_main_p1 4)) (.cse0 (+ v_b_188_1 2)) (.cse5 (+ v_b_192_1 1)) (.cse30 (+ v_b_187_1 2)) (.cse22 (+ v_b_191_1 1)) (.cse29 (+ c_ULTIMATE.start_main_p1 2)) (.cse24 (+ v_b_194_1 1)) (.cse14 (+ v_b_187_1 3)) (.cse12 (+ v_b_190_1 1)) (.cse31 (+ v_b_186_1 3)) (.cse26 (+ v_b_184_1 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 5)) (.cse10 (+ v_b_186_1 1))) (and (<= .cse0 v_b_191_1) (<= .cse1 v_b_189_1) (<= .cse2 v_b_189_1) (<= (+ v_b_184_1 6) v_b_195_1) (<= (+ v_b_191_1 2) v_b_195_1) (<= .cse3 v_b_193_1) (<= .cse4 v_b_193_1) (<= .cse4 v_b_194_1) (<= v_b_193_1 .cse5) (<= v_b_193_1 v_b_194_1) (<= .cse6 v_b_191_1) (<= .cse7 v_b_191_1) (<= v_v_1522_1 0) (or (<= v_b_185_1 v_idx_133) (= (select |c_#memory_int| v_idx_133) 0) (< v_idx_133 v_b_184_1)) (<= .cse8 v_b_193_1) (<= .cse5 v_b_194_1) (or (< v_idx_131 c_ULTIMATE.start_main_p1) (<= .cse9 v_idx_131) (= (select |c_#memory_int| v_idx_131) 0)) (<= v_b_187_1 .cse10) (<= (+ v_b_187_1 4) v_b_195_1) (<= .cse11 v_b_187_1) (<= v_b_191_1 .cse12) (<= (+ v_b_186_1 5) v_b_195_1) (<= (+ v_b_193_1 1) v_b_195_1) (<= .cse13 v_b_188_1) (<= .cse14 v_b_194_1) (<= .cse15 v_b_187_1) (<= .cse16 v_b_190_1) (<= (+ v_b_190_1 3) v_b_195_1) (or (<= v_b_186_1 v_idx_134) (< v_idx_134 v_b_185_1) (= (select |c_#memory_int| v_idx_134) v_v_1519_1)) (<= v_b_189_1 .cse17) (<= .cse18 v_b_194_1) (or (< v_idx_137 v_b_188_1) (= (select |c_#memory_int| v_idx_137) v_v_1522_1) (<= v_b_189_1 v_idx_137)) (<= .cse19 v_b_194_1) (<= .cse20 v_b_189_1) (<= .cse11 v_b_188_1) (<= .cse15 v_b_188_1) (<= .cse21 v_b_193_1) (<= .cse22 v_b_193_1) (<= (+ v_b_192_1 2) v_b_195_1) (<= (* 2 v_v_1522_1) 0) (<= .cse23 v_b_191_1) (<= .cse9 v_b_184_1) (<= v_b_185_1 v_b_186_1) (<= .cse24 v_b_195_1) (or (<= v_b_192_1 v_idx_140) (= (select |c_#memory_int| v_idx_140) v_v_1525_1) (< v_idx_140 v_b_191_1)) (or (= (select |c_#memory_int| v_idx_144) v_v_1529_1) (< v_idx_144 v_b_195_1)) (<= .cse17 v_b_189_1) (<= .cse18 v_b_193_1) (<= .cse16 v_b_189_1) (or (= 0 (select |c_#memory_int| v_idx_141)) (< v_idx_141 v_b_192_1) (<= v_b_193_1 v_idx_141)) (<= (+ v_b_188_1 4) v_b_195_1) (<= .cse12 v_b_192_1) (<= (+ v_b_185_1 5) v_b_195_1) (<= .cse7 v_b_192_1) (<= .cse17 v_b_190_1) (<= .cse1 v_b_190_1) (<= (+ v_b_189_1 3) v_b_195_1) (<= .cse2 v_b_190_1) (<= .cse19 v_b_193_1) (or (= (select |c_#memory_int| v_idx_136) v_v_1521_1) (< v_idx_136 v_b_187_1) (<= v_b_188_1 v_idx_136)) (<= .cse25 v_b_189_1) (<= .cse20 v_b_190_1) (<= .cse26 v_b_186_1) (<= .cse27 v_b_194_1) (<= .cse3 v_b_194_1) (<= v_b_185_1 .cse26) (<= .cse13 v_b_187_1) (<= .cse28 v_b_191_1) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_1) (or (< v_idx_132 .cse9) (= (select |c_#memory_int| v_idx_132) v_v_1517_1) (<= v_b_184_1 v_idx_132)) (<= .cse28 v_b_192_1) (<= .cse27 v_b_193_1) (or (= (select |c_#memory_int| v_idx_138) v_v_1523_1) (<= v_b_190_1 v_idx_138) (< v_idx_138 v_b_189_1)) (or (< v_idx_143 v_b_194_1) (= (select |c_#memory_int| v_idx_143) 0) (<= v_b_195_1 v_idx_143)) (<= .cse8 v_b_194_1) (or (< v_idx_139 v_b_190_1) (= (select |c_#memory_int| v_idx_139) 0) (<= v_b_191_1 v_idx_139)) (<= .cse21 v_b_194_1) (<= .cse23 v_b_192_1) (<= .cse25 v_b_190_1) (<= .cse29 v_b_186_1) (<= .cse0 v_b_192_1) (<= .cse5 v_b_193_1) (<= .cse30 v_b_191_1) (or (<= v_b_187_1 v_idx_135) (< v_idx_135 v_b_186_1) (= (select |c_#memory_int| v_idx_135) 0)) (<= .cse30 v_b_192_1) (<= .cse31 v_b_191_1) (<= v_b_187_1 v_b_188_1) (<= .cse22 v_b_194_1) (or (= (select |c_#memory_int| v_idx_142) v_v_1527_1) (<= v_b_194_1 v_idx_142) (< v_idx_142 v_b_193_1)) (<= .cse10 v_b_187_1) (<= .cse29 v_b_185_1) (<= v_b_195_1 .cse24) (<= .cse14 v_b_193_1) (<= .cse12 v_b_191_1) (<= v_b_189_1 v_b_190_1) (<= .cse31 v_b_192_1) (<= .cse26 v_b_185_1) (or (= (select |c_#memory_int| v_idx_130) v_v_1515_1) (<= c_ULTIMATE.start_main_p1 v_idx_130)) (<= .cse6 v_b_192_1) (<= .cse10 v_b_188_1) (<= v_b_191_1 v_b_192_1))))) is different from false [2019-01-08 14:36:19,665 WARN L860 $PredicateComparison]: unable to prove that (forall ((v_idx_137 Int) (v_idx_138 Int) (v_idx_135 Int) (v_idx_136 Int) (v_idx_139 Int) (v_idx_140 Int) (v_idx_141 Int) (v_idx_130 Int) (v_idx_144 Int) (v_idx_133 Int) (v_idx_134 Int) (v_idx_142 Int) (v_idx_131 Int) (v_idx_143 Int) (v_idx_132 Int)) (exists ((v_v_1519_1 Int) (v_b_195_1 Int) (v_v_1521_1 Int) (v_b_184_1 Int) (v_b_194_1 Int) (v_b_185_1 Int) (v_b_186_1 Int) (v_b_187_1 Int) (v_b_188_1 Int) (v_b_189_1 Int) (v_v_1529_1 Int) (v_v_1517_1 Int) (v_v_1527_1 Int) (v_v_1515_1 Int) (v_b_191_1 Int) (v_v_1525_1 Int) (v_b_190_1 Int) (v_b_193_1 Int) (v_v_1523_1 Int) (v_b_192_1 Int) (v_v_1522_1 Int)) (let ((.cse4 (+ v_b_189_1 2)) (.cse11 (+ c_ULTIMATE.start_main_p1 3)) (.cse15 (+ v_b_184_1 2)) (.cse18 (+ v_b_184_1 5)) (.cse16 (+ v_b_185_1 2)) (.cse7 (+ v_b_189_1 1)) (.cse17 (+ v_b_188_1 1)) (.cse1 (+ v_b_186_1 2)) (.cse2 (+ v_b_184_1 3)) (.cse19 (+ v_b_190_1 2)) (.cse20 (+ v_b_187_1 1)) (.cse3 (+ v_b_188_1 3)) (.cse13 (+ v_b_185_1 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 1)) (.cse28 (+ v_b_184_1 4)) (.cse27 (+ c_ULTIMATE.start_main_p1 6)) (.cse8 (+ v_b_186_1 4)) (.cse21 (+ v_b_185_1 4)) (.cse23 (+ v_b_185_1 3)) (.cse25 (+ c_ULTIMATE.start_main_p1 4)) (.cse0 (+ v_b_188_1 2)) (.cse5 (+ v_b_192_1 1)) (.cse30 (+ v_b_187_1 2)) (.cse22 (+ v_b_191_1 1)) (.cse29 (+ c_ULTIMATE.start_main_p1 2)) (.cse24 (+ v_b_194_1 1)) (.cse14 (+ v_b_187_1 3)) (.cse12 (+ v_b_190_1 1)) (.cse31 (+ v_b_186_1 3)) (.cse26 (+ v_b_184_1 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 5)) (.cse10 (+ v_b_186_1 1))) (and (<= .cse0 v_b_191_1) (<= .cse1 v_b_189_1) (<= .cse2 v_b_189_1) (<= (+ v_b_184_1 6) v_b_195_1) (<= (+ v_b_191_1 2) v_b_195_1) (<= .cse3 v_b_193_1) (<= .cse4 v_b_193_1) (<= .cse4 v_b_194_1) (<= v_b_193_1 .cse5) (<= v_b_193_1 v_b_194_1) (<= .cse6 v_b_191_1) (<= .cse7 v_b_191_1) (<= v_v_1522_1 0) (or (<= v_b_185_1 v_idx_133) (= (select |c_#memory_int| v_idx_133) 0) (< v_idx_133 v_b_184_1)) (<= .cse8 v_b_193_1) (<= .cse5 v_b_194_1) (or (< v_idx_131 c_ULTIMATE.start_main_p1) (<= .cse9 v_idx_131) (= (select |c_#memory_int| v_idx_131) 0)) (<= v_b_187_1 .cse10) (<= (+ v_b_187_1 4) v_b_195_1) (<= .cse11 v_b_187_1) (<= v_b_191_1 .cse12) (<= (+ v_b_186_1 5) v_b_195_1) (<= (+ v_b_193_1 1) v_b_195_1) (<= .cse13 v_b_188_1) (<= .cse14 v_b_194_1) (<= .cse15 v_b_187_1) (<= .cse16 v_b_190_1) (<= (+ v_b_190_1 3) v_b_195_1) (or (<= v_b_186_1 v_idx_134) (< v_idx_134 v_b_185_1) (= (select |c_#memory_int| v_idx_134) v_v_1519_1)) (<= v_b_189_1 .cse17) (<= .cse18 v_b_194_1) (or (< v_idx_137 v_b_188_1) (= (select |c_#memory_int| v_idx_137) v_v_1522_1) (<= v_b_189_1 v_idx_137)) (<= .cse19 v_b_194_1) (<= .cse20 v_b_189_1) (<= .cse11 v_b_188_1) (<= .cse15 v_b_188_1) (<= .cse21 v_b_193_1) (<= .cse22 v_b_193_1) (<= (+ v_b_192_1 2) v_b_195_1) (<= (* 2 v_v_1522_1) 0) (<= .cse23 v_b_191_1) (<= .cse9 v_b_184_1) (<= v_b_185_1 v_b_186_1) (<= .cse24 v_b_195_1) (or (<= v_b_192_1 v_idx_140) (= (select |c_#memory_int| v_idx_140) v_v_1525_1) (< v_idx_140 v_b_191_1)) (or (= (select |c_#memory_int| v_idx_144) v_v_1529_1) (< v_idx_144 v_b_195_1)) (<= .cse17 v_b_189_1) (<= .cse18 v_b_193_1) (<= .cse16 v_b_189_1) (or (= 0 (select |c_#memory_int| v_idx_141)) (< v_idx_141 v_b_192_1) (<= v_b_193_1 v_idx_141)) (<= (+ v_b_188_1 4) v_b_195_1) (<= .cse12 v_b_192_1) (<= (+ v_b_185_1 5) v_b_195_1) (<= .cse7 v_b_192_1) (<= .cse17 v_b_190_1) (<= .cse1 v_b_190_1) (<= (+ v_b_189_1 3) v_b_195_1) (<= .cse2 v_b_190_1) (<= .cse19 v_b_193_1) (or (= (select |c_#memory_int| v_idx_136) v_v_1521_1) (< v_idx_136 v_b_187_1) (<= v_b_188_1 v_idx_136)) (<= .cse25 v_b_189_1) (<= .cse20 v_b_190_1) (<= .cse26 v_b_186_1) (<= .cse27 v_b_194_1) (<= .cse3 v_b_194_1) (<= v_b_185_1 .cse26) (<= .cse13 v_b_187_1) (<= .cse28 v_b_191_1) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_1) (or (< v_idx_132 .cse9) (= (select |c_#memory_int| v_idx_132) v_v_1517_1) (<= v_b_184_1 v_idx_132)) (<= .cse28 v_b_192_1) (<= .cse27 v_b_193_1) (or (= (select |c_#memory_int| v_idx_138) v_v_1523_1) (<= v_b_190_1 v_idx_138) (< v_idx_138 v_b_189_1)) (or (< v_idx_143 v_b_194_1) (= (select |c_#memory_int| v_idx_143) 0) (<= v_b_195_1 v_idx_143)) (<= .cse8 v_b_194_1) (or (< v_idx_139 v_b_190_1) (= (select |c_#memory_int| v_idx_139) 0) (<= v_b_191_1 v_idx_139)) (<= .cse21 v_b_194_1) (<= .cse23 v_b_192_1) (<= .cse25 v_b_190_1) (<= .cse29 v_b_186_1) (<= .cse0 v_b_192_1) (<= .cse5 v_b_193_1) (<= .cse30 v_b_191_1) (or (<= v_b_187_1 v_idx_135) (< v_idx_135 v_b_186_1) (= (select |c_#memory_int| v_idx_135) 0)) (<= .cse30 v_b_192_1) (<= .cse31 v_b_191_1) (<= v_b_187_1 v_b_188_1) (<= .cse22 v_b_194_1) (or (= (select |c_#memory_int| v_idx_142) v_v_1527_1) (<= v_b_194_1 v_idx_142) (< v_idx_142 v_b_193_1)) (<= .cse10 v_b_187_1) (<= .cse29 v_b_185_1) (<= v_b_195_1 .cse24) (<= .cse14 v_b_193_1) (<= .cse12 v_b_191_1) (<= v_b_189_1 v_b_190_1) (<= .cse31 v_b_192_1) (<= .cse26 v_b_185_1) (or (= (select |c_#memory_int| v_idx_130) v_v_1515_1) (<= c_ULTIMATE.start_main_p1 v_idx_130)) (<= .cse6 v_b_192_1) (<= .cse10 v_b_188_1) (<= v_b_191_1 v_b_192_1))))) is different from true [2019-01-08 14:36:19,667 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:36:19,668 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:36:19,669 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:36:19,669 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:36:19,669 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:36:19,670 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:36:19,670 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:36:19,670 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=2, Unknown=3, NotChecked=2, Total=12 [2019-01-08 14:36:19,671 INFO L87 Difference]: Start difference. First operand 17 states and 30 transitions. Second operand 4 states. [2019-01-08 14:36:22,901 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_137 Int) (v_idx_138 Int) (v_idx_135 Int) (v_idx_136 Int) (v_idx_139 Int) (v_idx_140 Int) (v_idx_141 Int) (v_idx_130 Int) (v_idx_144 Int) (v_idx_133 Int) (v_idx_134 Int) (v_idx_142 Int) (v_idx_131 Int) (v_idx_143 Int) (v_idx_132 Int)) (exists ((v_v_1519_1 Int) (v_b_195_1 Int) (v_v_1521_1 Int) (v_b_184_1 Int) (v_b_194_1 Int) (v_b_185_1 Int) (v_b_186_1 Int) (v_b_187_1 Int) (v_b_188_1 Int) (v_b_189_1 Int) (v_v_1529_1 Int) (v_v_1517_1 Int) (v_v_1527_1 Int) (v_v_1515_1 Int) (v_b_191_1 Int) (v_v_1525_1 Int) (v_b_190_1 Int) (v_b_193_1 Int) (v_v_1523_1 Int) (v_b_192_1 Int) (v_v_1522_1 Int)) (let ((.cse4 (+ v_b_189_1 2)) (.cse11 (+ c_ULTIMATE.start_main_p1 3)) (.cse15 (+ v_b_184_1 2)) (.cse18 (+ v_b_184_1 5)) (.cse16 (+ v_b_185_1 2)) (.cse7 (+ v_b_189_1 1)) (.cse17 (+ v_b_188_1 1)) (.cse1 (+ v_b_186_1 2)) (.cse2 (+ v_b_184_1 3)) (.cse19 (+ v_b_190_1 2)) (.cse20 (+ v_b_187_1 1)) (.cse3 (+ v_b_188_1 3)) (.cse13 (+ v_b_185_1 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 1)) (.cse28 (+ v_b_184_1 4)) (.cse27 (+ c_ULTIMATE.start_main_p1 6)) (.cse8 (+ v_b_186_1 4)) (.cse21 (+ v_b_185_1 4)) (.cse23 (+ v_b_185_1 3)) (.cse25 (+ c_ULTIMATE.start_main_p1 4)) (.cse0 (+ v_b_188_1 2)) (.cse5 (+ v_b_192_1 1)) (.cse30 (+ v_b_187_1 2)) (.cse22 (+ v_b_191_1 1)) (.cse29 (+ c_ULTIMATE.start_main_p1 2)) (.cse24 (+ v_b_194_1 1)) (.cse14 (+ v_b_187_1 3)) (.cse12 (+ v_b_190_1 1)) (.cse31 (+ v_b_186_1 3)) (.cse26 (+ v_b_184_1 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 5)) (.cse10 (+ v_b_186_1 1))) (and (<= .cse0 v_b_191_1) (<= .cse1 v_b_189_1) (<= .cse2 v_b_189_1) (<= (+ v_b_184_1 6) v_b_195_1) (<= (+ v_b_191_1 2) v_b_195_1) (<= .cse3 v_b_193_1) (<= .cse4 v_b_193_1) (<= .cse4 v_b_194_1) (<= v_b_193_1 .cse5) (<= v_b_193_1 v_b_194_1) (<= .cse6 v_b_191_1) (<= .cse7 v_b_191_1) (<= v_v_1522_1 0) (or (<= v_b_185_1 v_idx_133) (= (select |c_#memory_int| v_idx_133) 0) (< v_idx_133 v_b_184_1)) (<= .cse8 v_b_193_1) (<= .cse5 v_b_194_1) (or (< v_idx_131 c_ULTIMATE.start_main_p1) (<= .cse9 v_idx_131) (= (select |c_#memory_int| v_idx_131) 0)) (<= v_b_187_1 .cse10) (<= (+ v_b_187_1 4) v_b_195_1) (<= .cse11 v_b_187_1) (<= v_b_191_1 .cse12) (<= (+ v_b_186_1 5) v_b_195_1) (<= (+ v_b_193_1 1) v_b_195_1) (<= .cse13 v_b_188_1) (<= .cse14 v_b_194_1) (<= .cse15 v_b_187_1) (<= .cse16 v_b_190_1) (<= (+ v_b_190_1 3) v_b_195_1) (or (<= v_b_186_1 v_idx_134) (< v_idx_134 v_b_185_1) (= (select |c_#memory_int| v_idx_134) v_v_1519_1)) (<= v_b_189_1 .cse17) (<= .cse18 v_b_194_1) (or (< v_idx_137 v_b_188_1) (= (select |c_#memory_int| v_idx_137) v_v_1522_1) (<= v_b_189_1 v_idx_137)) (<= .cse19 v_b_194_1) (<= .cse20 v_b_189_1) (<= .cse11 v_b_188_1) (<= .cse15 v_b_188_1) (<= .cse21 v_b_193_1) (<= .cse22 v_b_193_1) (<= (+ v_b_192_1 2) v_b_195_1) (<= (* 2 v_v_1522_1) 0) (<= .cse23 v_b_191_1) (<= .cse9 v_b_184_1) (<= v_b_185_1 v_b_186_1) (<= .cse24 v_b_195_1) (or (<= v_b_192_1 v_idx_140) (= (select |c_#memory_int| v_idx_140) v_v_1525_1) (< v_idx_140 v_b_191_1)) (or (= (select |c_#memory_int| v_idx_144) v_v_1529_1) (< v_idx_144 v_b_195_1)) (<= .cse17 v_b_189_1) (<= .cse18 v_b_193_1) (<= .cse16 v_b_189_1) (or (= 0 (select |c_#memory_int| v_idx_141)) (< v_idx_141 v_b_192_1) (<= v_b_193_1 v_idx_141)) (<= (+ v_b_188_1 4) v_b_195_1) (<= .cse12 v_b_192_1) (<= (+ v_b_185_1 5) v_b_195_1) (<= .cse7 v_b_192_1) (<= .cse17 v_b_190_1) (<= .cse1 v_b_190_1) (<= (+ v_b_189_1 3) v_b_195_1) (<= .cse2 v_b_190_1) (<= .cse19 v_b_193_1) (or (= (select |c_#memory_int| v_idx_136) v_v_1521_1) (< v_idx_136 v_b_187_1) (<= v_b_188_1 v_idx_136)) (<= .cse25 v_b_189_1) (<= .cse20 v_b_190_1) (<= .cse26 v_b_186_1) (<= .cse27 v_b_194_1) (<= .cse3 v_b_194_1) (<= v_b_185_1 .cse26) (<= .cse13 v_b_187_1) (<= .cse28 v_b_191_1) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_1) (or (< v_idx_132 .cse9) (= (select |c_#memory_int| v_idx_132) v_v_1517_1) (<= v_b_184_1 v_idx_132)) (<= .cse28 v_b_192_1) (<= .cse27 v_b_193_1) (or (= (select |c_#memory_int| v_idx_138) v_v_1523_1) (<= v_b_190_1 v_idx_138) (< v_idx_138 v_b_189_1)) (or (< v_idx_143 v_b_194_1) (= (select |c_#memory_int| v_idx_143) 0) (<= v_b_195_1 v_idx_143)) (<= .cse8 v_b_194_1) (or (< v_idx_139 v_b_190_1) (= (select |c_#memory_int| v_idx_139) 0) (<= v_b_191_1 v_idx_139)) (<= .cse21 v_b_194_1) (<= .cse23 v_b_192_1) (<= .cse25 v_b_190_1) (<= .cse29 v_b_186_1) (<= .cse0 v_b_192_1) (<= .cse5 v_b_193_1) (<= .cse30 v_b_191_1) (or (<= v_b_187_1 v_idx_135) (< v_idx_135 v_b_186_1) (= (select |c_#memory_int| v_idx_135) 0)) (<= .cse30 v_b_192_1) (<= .cse31 v_b_191_1) (<= v_b_187_1 v_b_188_1) (<= .cse22 v_b_194_1) (or (= (select |c_#memory_int| v_idx_142) v_v_1527_1) (<= v_b_194_1 v_idx_142) (< v_idx_142 v_b_193_1)) (<= .cse10 v_b_187_1) (<= .cse29 v_b_185_1) (<= v_b_195_1 .cse24) (<= .cse14 v_b_193_1) (<= .cse12 v_b_191_1) (<= v_b_189_1 v_b_190_1) (<= .cse31 v_b_192_1) (<= .cse26 v_b_185_1) (or (= (select |c_#memory_int| v_idx_130) v_v_1515_1) (<= c_ULTIMATE.start_main_p1 v_idx_130)) (<= .cse6 v_b_192_1) (<= .cse10 v_b_188_1) (<= v_b_191_1 v_b_192_1))))) (forall ((v_idx_126 Int) (v_idx_115 Int) (v_idx_127 Int) (v_idx_116 Int) (v_idx_124 Int) (v_idx_125 Int) (v_idx_119 Int) (v_idx_128 Int) (v_idx_117 Int) (v_idx_129 Int) (v_idx_118 Int) (v_idx_122 Int) (v_idx_123 Int) (v_idx_120 Int) (v_idx_121 Int)) (exists ((v_v_1519_1 Int) (v_b_195_1 Int) (v_v_1521_1 Int) (v_b_184_1 Int) (v_b_194_1 Int) (v_b_185_1 Int) (v_b_186_1 Int) (v_b_187_1 Int) (v_v_1529_1 Int) (v_v_1517_1 Int) (v_v_1527_1 Int) (v_v_1515_1 Int) (v_b_191_1 Int) (v_v_1525_1 Int) (v_b_190_1 Int) (v_b_193_1 Int) (v_v_1523_1 Int) (v_b_192_1 Int) (v_v_1522_1 Int)) (let ((.cse46 (+ v_b_184_1 4)) (.cse36 (+ c_ULTIMATE.start_main_p4 2)) (.cse44 (+ v_b_184_1 2)) (.cse40 (+ c_ULTIMATE.start_main_p1 6)) (.cse48 (+ c_ULTIMATE.start_main_p4 1)) (.cse42 (+ v_b_186_1 4)) (.cse32 (+ v_b_184_1 5)) (.cse41 (+ v_b_185_1 1)) (.cse35 (+ v_b_190_1 2)) (.cse34 (+ v_b_192_1 1)) (.cse52 (+ v_b_187_1 2)) (.cse45 (+ c_ULTIMATE.start_main_p1 3)) (.cse49 (+ v_b_185_1 4)) (.cse51 (+ c_ULTIMATE.start_main_p1 2)) (.cse54 (+ v_b_191_1 1)) (.cse47 (+ v_b_187_1 3)) (.cse50 (+ v_b_185_1 3)) (.cse33 (+ v_b_190_1 1)) (.cse37 (+ c_ULTIMATE.start_main_p1 1)) (.cse56 (+ c_ULTIMATE.start_main_p4 3)) (.cse53 (+ v_b_186_1 3)) (.cse39 (+ v_b_184_1 1)) (.cse55 (+ v_b_194_1 1)) (.cse38 (+ c_ULTIMATE.start_main_p1 5)) (.cse43 (+ v_b_186_1 1))) (and (or (<= v_b_186_1 v_idx_119) (< v_idx_119 v_b_185_1) (= (select |c_#memory_int| v_idx_119) v_v_1519_1)) (<= .cse32 v_b_193_1) (<= (+ v_b_184_1 6) v_b_195_1) (<= .cse33 v_b_192_1) (<= (+ v_b_191_1 2) v_b_195_1) (<= (+ v_b_185_1 5) v_b_195_1) (<= v_b_187_1 c_ULTIMATE.start_main_p4) (or (<= v_b_185_1 v_idx_118) (< v_idx_118 v_b_184_1) (= (select |c_#memory_int| v_idx_118) 0)) (<= v_b_193_1 .cse34) (<= (+ v_b_186_1 2) v_b_190_1) (<= v_b_193_1 v_b_194_1) (<= (+ v_b_184_1 3) v_b_190_1) (<= .cse35 v_b_193_1) (<= .cse36 v_b_191_1) (or (<= v_b_192_1 v_idx_125) (= (select |c_#memory_int| v_idx_125) v_v_1525_1) (< v_idx_125 v_b_191_1)) (or (= (select |c_#memory_int| v_idx_116) 0) (< v_idx_116 c_ULTIMATE.start_main_p1) (<= .cse37 v_idx_116)) (or (< v_idx_124 v_b_190_1) (<= v_b_191_1 v_idx_124) (= (select |c_#memory_int| v_idx_124) 0)) (<= (+ v_b_187_1 1) v_b_190_1) (<= .cse38 v_b_191_1) (<= .cse39 v_b_186_1) (<= v_v_1522_1 0) (<= .cse40 v_b_194_1) (<= v_b_185_1 .cse39) (<= .cse41 v_b_187_1) (<= .cse42 v_b_193_1) (<= .cse34 v_b_194_1) (<= v_b_187_1 .cse43) (<= .cse44 c_ULTIMATE.start_main_p4) (or (< v_idx_127 v_b_193_1) (<= v_b_194_1 v_idx_127) (= (select |c_#memory_int| v_idx_127) v_v_1527_1)) (<= (+ v_b_187_1 4) v_b_195_1) (<= .cse45 v_b_187_1) (<= v_b_191_1 .cse33) (<= .cse46 v_b_191_1) (or (= (select |c_#memory_int| v_idx_120) 0) (<= v_b_187_1 v_idx_120) (< v_idx_120 v_b_186_1)) (<= (+ v_b_186_1 5) v_b_195_1) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_1) (<= (+ v_b_193_1 1) v_b_195_1) (<= .cse46 v_b_192_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_115) (= (select |c_#memory_int| v_idx_115) v_v_1515_1)) (<= .cse36 v_b_192_1) (or (= (select |c_#memory_int| v_idx_121) v_v_1521_1) (< v_idx_121 v_b_187_1) (<= c_ULTIMATE.start_main_p4 v_idx_121)) (<= .cse47 v_b_194_1) (<= .cse48 v_b_190_1) (<= .cse44 v_b_187_1) (<= .cse40 v_b_193_1) (<= (+ v_b_185_1 2) v_b_190_1) (<= (+ v_b_190_1 3) v_b_195_1) (or (< v_idx_122 c_ULTIMATE.start_main_p4) (= (select |c_#memory_int| v_idx_122) v_v_1522_1) (<= .cse48 v_idx_122)) (or (< v_idx_123 .cse48) (<= v_b_190_1 v_idx_123) (= (select |c_#memory_int| v_idx_123) v_v_1523_1)) (<= .cse42 v_b_194_1) (<= .cse32 v_b_194_1) (<= .cse49 v_b_194_1) (<= .cse50 v_b_192_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_190_1) (<= .cse41 c_ULTIMATE.start_main_p4) (<= .cse51 v_b_186_1) (or (< v_idx_128 v_b_194_1) (<= v_b_195_1 v_idx_128) (= (select |c_#memory_int| v_idx_128) 0)) (<= .cse35 v_b_194_1) (<= .cse34 v_b_193_1) (<= .cse52 v_b_191_1) (or (= (select |c_#memory_int| v_idx_117) v_v_1517_1) (< v_idx_117 .cse37) (<= v_b_184_1 v_idx_117)) (<= .cse52 v_b_192_1) (<= .cse53 v_b_191_1) (<= .cse54 v_b_194_1) (<= .cse45 c_ULTIMATE.start_main_p4) (<= .cse49 v_b_193_1) (<= .cse43 v_b_187_1) (<= .cse51 v_b_185_1) (<= v_b_195_1 .cse55) (<= .cse54 v_b_193_1) (<= (+ v_b_192_1 2) v_b_195_1) (<= .cse47 v_b_193_1) (or (< v_idx_126 v_b_192_1) (= 0 (select |c_#memory_int| v_idx_126)) (<= v_b_193_1 v_idx_126)) (<= (* 2 v_v_1522_1) 0) (<= .cse50 v_b_191_1) (<= .cse56 v_b_194_1) (<= .cse33 v_b_191_1) (<= .cse37 v_b_184_1) (<= .cse56 v_b_193_1) (<= .cse53 v_b_192_1) (<= .cse39 v_b_185_1) (<= v_b_185_1 v_b_186_1) (<= .cse55 v_b_195_1) (<= .cse38 v_b_192_1) (<= .cse43 c_ULTIMATE.start_main_p4) (<= v_b_191_1 v_b_192_1) (or (< v_idx_129 v_b_195_1) (= (select |c_#memory_int| v_idx_129) v_v_1529_1)) (<= (+ c_ULTIMATE.start_main_p4 4) v_b_195_1)))))) is different from false [2019-01-08 14:37:08,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:37:08,487 INFO L93 Difference]: Finished difference Result 19 states and 39 transitions. [2019-01-08 14:37:08,487 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-08 14:37:08,487 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-08 14:37:08,487 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:37:08,488 INFO L225 Difference]: With dead ends: 19 [2019-01-08 14:37:08,488 INFO L226 Difference]: Without dead ends: 18 [2019-01-08 14:37:08,489 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 9.9s TimeCoverageRelationStatistics Valid=7, Invalid=3, Unknown=4, NotChecked=6, Total=20 [2019-01-08 14:37:08,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states. [2019-01-08 14:37:08,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2019-01-08 14:37:08,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2019-01-08 14:37:08,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 38 transitions. [2019-01-08 14:37:08,496 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 38 transitions. Word has length 3 [2019-01-08 14:37:08,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:37:08,497 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 38 transitions. [2019-01-08 14:37:08,497 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:37:08,497 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 38 transitions. [2019-01-08 14:37:08,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:37:08,498 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:37:08,498 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:37:08,499 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:37:08,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:37:08,500 INFO L82 PathProgramCache]: Analyzing trace with hash 30008, now seen corresponding path program 1 times [2019-01-08 14:37:08,500 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:37:08,501 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:37:08,501 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:37:08,502 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:37:08,502 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:37:08,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:37:08,663 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:37:08,663 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:37:08,663 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:37:08,664 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:37:08,664 INFO L207 CegarAbsIntRunner]: [0], [6], [31] [2019-01-08 14:37:08,666 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:37:08,666 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:37:21,471 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:37:21,472 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:37:21,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:37:21,472 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:37:22,332 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 81.82% of their original sizes. [2019-01-08 14:37:22,333 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:37:24,794 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_269 Int) (v_idx_259 Int) (v_idx_267 Int) (v_idx_268 Int) (v_idx_261 Int) (v_idx_272 Int) (v_idx_262 Int) (v_idx_273 Int) (v_idx_270 Int) (v_idx_260 Int) (v_idx_271 Int) (v_idx_265 Int) (v_idx_266 Int) (v_idx_263 Int) (v_idx_264 Int)) (exists ((v_v_1519_2 Int) (v_v_1529_2 Int) (v_b_194_2 Int) (v_b_193_2 Int) (v_b_184_2 Int) (v_b_185_2 Int) (v_b_195_2 Int) (v_b_186_2 Int) (v_b_187_2 Int) (v_b_188_2 Int) (v_b_189_2 Int) (v_v_1517_2 Int) (v_v_1516_2 Int) (v_v_1527_2 Int) (v_v_1515_2 Int) (v_v_1525_2 Int) (v_b_190_2 Int) (v_v_1523_2 Int) (v_b_192_2 Int) (v_b_191_2 Int) (v_v_1521_2 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse5 (+ v_b_185_2 4)) (.cse9 (+ c_ULTIMATE.start_main_p1 6)) (.cse11 (+ v_b_187_2 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 3)) (.cse16 (+ v_b_185_2 3)) (.cse14 (+ v_b_188_2 2)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse22 (+ v_b_184_2 3)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse15 (+ v_b_186_2 2)) (.cse17 (+ v_b_187_2 3)) (.cse10 (+ v_b_184_2 4)) (.cse28 (+ v_b_185_2 1)) (.cse12 (+ v_b_190_2 2)) (.cse19 (+ v_b_186_2 1)) (.cse23 (+ v_b_184_2 5)) (.cse31 (+ v_b_189_2 2)) (.cse30 (+ v_b_194_2 1)) (.cse13 (+ v_b_190_2 1)) (.cse26 (+ v_b_186_2 4)) (.cse6 (+ v_b_187_2 2)) (.cse25 (+ v_b_184_2 2)) (.cse20 (+ v_b_188_2 3)) (.cse2 (+ v_b_192_2 1)) (.cse1 (+ v_b_191_2 1)) (.cse21 (+ v_b_186_2 3)) (.cse29 (+ v_b_188_2 1)) (.cse4 (+ v_b_185_2 2)) (.cse27 (+ c_ULTIMATE.start_main_p1 5)) (.cse24 (+ v_b_189_2 1)) (.cse0 (+ v_b_184_2 1))) (and (<= v_b_185_2 .cse0) (<= .cse1 v_b_193_2) (<= .cse2 v_b_193_2) (<= .cse3 v_b_189_2) (<= .cse4 v_b_190_2) (or (< v_idx_270 v_b_192_2) (= 0 (select |c_#memory_int| v_idx_270)) (<= v_b_193_2 v_idx_270)) (or (= v_v_1525_2 (select |c_#memory_int| v_idx_269)) (<= v_b_192_2 v_idx_269) (< v_idx_269 v_b_191_2)) (<= .cse5 v_b_194_2) (<= .cse6 v_b_192_2) (<= .cse7 v_b_186_2) (or (= (select |c_#memory_int| v_idx_260) v_v_1516_2) (< v_idx_260 c_ULTIMATE.start_main_p1) (<= .cse8 v_idx_260)) (<= .cse9 v_b_194_2) (<= .cse10 v_b_191_2) (<= .cse11 v_b_190_2) (<= .cse12 v_b_194_2) (<= .cse13 v_b_192_2) (<= .cse8 v_b_184_2) (<= .cse14 v_b_191_2) (<= (+ v_b_185_2 5) v_b_195_2) (<= .cse15 v_b_190_2) (<= .cse16 v_b_191_2) (or (< v_idx_264 v_b_186_2) (= 0 (select |c_#memory_int| v_idx_264)) (<= v_b_187_2 v_idx_264)) (<= .cse3 v_b_190_2) (<= (+ v_b_190_2 3) v_b_195_2) (<= .cse5 v_b_193_2) (<= .cse9 v_b_193_2) (<= .cse17 v_b_193_2) (<= .cse0 v_b_186_2) (or (= 0 (select |c_#memory_int| v_idx_262)) (< v_idx_262 v_b_184_2) (<= v_b_185_2 v_idx_262)) (<= .cse11 v_b_189_2) (<= (+ v_b_189_2 3) v_b_195_2) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_2) (or (< v_idx_266 v_b_188_2) (<= v_b_189_2 v_idx_266) (= 0 (select |c_#memory_int| v_idx_266))) (<= .cse18 v_b_187_2) (<= .cse18 v_b_188_2) (<= .cse16 v_b_192_2) (<= 0 (* 2 v_v_1516_2)) (<= .cse19 v_b_188_2) (<= .cse20 v_b_193_2) (<= .cse14 v_b_192_2) (<= (+ v_b_184_2 6) v_b_195_2) (<= .cse21 v_b_192_2) (<= .cse22 v_b_189_2) (<= .cse7 v_b_185_2) (<= .cse23 v_b_194_2) (<= .cse24 v_b_192_2) (<= (+ v_b_192_2 2) v_b_195_2) (<= v_b_189_2 v_b_190_2) (<= .cse22 v_b_190_2) (<= v_b_187_2 v_b_188_2) (<= .cse25 v_b_187_2) (or (= (select |c_#memory_int| v_idx_271) v_v_1527_2) (< v_idx_271 v_b_193_2) (<= v_b_194_2 v_idx_271)) (or (= (select |c_#memory_int| v_idx_263) v_v_1519_2) (<= v_b_186_2 v_idx_263) (< v_idx_263 v_b_185_2)) (<= (+ v_b_191_2 2) v_b_195_2) (or (< v_idx_261 .cse8) (= (select |c_#memory_int| v_idx_261) v_v_1517_2) (<= v_b_184_2 v_idx_261)) (<= .cse2 v_b_194_2) (<= (+ v_b_188_2 4) v_b_195_2) (<= .cse26 v_b_194_2) (<= .cse27 v_b_191_2) (<= .cse15 v_b_189_2) (or (< v_idx_268 v_b_190_2) (= 0 (select |c_#memory_int| v_idx_268)) (<= v_b_191_2 v_idx_268)) (or (= (select |c_#memory_int| v_idx_259) v_v_1515_2) (<= c_ULTIMATE.start_main_p1 v_idx_259)) (<= (+ v_b_193_2 1) v_b_195_2) (<= .cse28 v_b_187_2) (<= v_b_187_2 .cse19) (<= .cse17 v_b_194_2) (<= .cse10 v_b_192_2) (<= .cse28 v_b_188_2) (<= .cse12 v_b_193_2) (<= v_b_193_2 v_b_194_2) (<= (+ v_b_186_2 5) v_b_195_2) (<= v_b_189_2 .cse29) (<= .cse19 v_b_187_2) (<= (+ v_b_187_2 4) v_b_195_2) (<= v_b_195_2 .cse30) (<= .cse31 v_b_193_2) (<= v_b_191_2 v_b_192_2) (<= 0 v_v_1516_2) (<= .cse23 v_b_193_2) (<= v_b_191_2 .cse13) (<= .cse31 v_b_194_2) (or (< v_idx_272 v_b_194_2) (<= v_b_195_2 v_idx_272) (= (select |c_#memory_int| v_idx_272) 0)) (<= .cse30 v_b_195_2) (<= .cse13 v_b_191_2) (<= .cse26 v_b_193_2) (or (= (select |c_#memory_int| v_idx_273) v_v_1529_2) (< v_idx_273 v_b_195_2)) (or (< v_idx_265 v_b_187_2) (= (select |c_#memory_int| v_idx_265) v_v_1521_2) (<= v_b_188_2 v_idx_265)) (<= .cse6 v_b_191_2) (<= .cse25 v_b_188_2) (<= .cse20 v_b_194_2) (<= v_b_193_2 .cse2) (<= .cse1 v_b_194_2) (<= v_b_185_2 v_b_186_2) (<= .cse29 v_b_190_2) (<= .cse21 v_b_191_2) (<= .cse29 v_b_189_2) (or (<= v_b_190_2 v_idx_267) (< v_idx_267 v_b_189_2) (= (select |c_#memory_int| v_idx_267) v_v_1523_2)) (<= .cse4 v_b_189_2) (<= .cse27 v_b_192_2) (<= .cse24 v_b_191_2) (<= .cse0 v_b_185_2))))) is different from false [2019-01-08 14:37:26,813 WARN L860 $PredicateComparison]: unable to prove that (forall ((v_idx_269 Int) (v_idx_259 Int) (v_idx_267 Int) (v_idx_268 Int) (v_idx_261 Int) (v_idx_272 Int) (v_idx_262 Int) (v_idx_273 Int) (v_idx_270 Int) (v_idx_260 Int) (v_idx_271 Int) (v_idx_265 Int) (v_idx_266 Int) (v_idx_263 Int) (v_idx_264 Int)) (exists ((v_v_1519_2 Int) (v_v_1529_2 Int) (v_b_194_2 Int) (v_b_193_2 Int) (v_b_184_2 Int) (v_b_185_2 Int) (v_b_195_2 Int) (v_b_186_2 Int) (v_b_187_2 Int) (v_b_188_2 Int) (v_b_189_2 Int) (v_v_1517_2 Int) (v_v_1516_2 Int) (v_v_1527_2 Int) (v_v_1515_2 Int) (v_v_1525_2 Int) (v_b_190_2 Int) (v_v_1523_2 Int) (v_b_192_2 Int) (v_b_191_2 Int) (v_v_1521_2 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse5 (+ v_b_185_2 4)) (.cse9 (+ c_ULTIMATE.start_main_p1 6)) (.cse11 (+ v_b_187_2 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 3)) (.cse16 (+ v_b_185_2 3)) (.cse14 (+ v_b_188_2 2)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse22 (+ v_b_184_2 3)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse15 (+ v_b_186_2 2)) (.cse17 (+ v_b_187_2 3)) (.cse10 (+ v_b_184_2 4)) (.cse28 (+ v_b_185_2 1)) (.cse12 (+ v_b_190_2 2)) (.cse19 (+ v_b_186_2 1)) (.cse23 (+ v_b_184_2 5)) (.cse31 (+ v_b_189_2 2)) (.cse30 (+ v_b_194_2 1)) (.cse13 (+ v_b_190_2 1)) (.cse26 (+ v_b_186_2 4)) (.cse6 (+ v_b_187_2 2)) (.cse25 (+ v_b_184_2 2)) (.cse20 (+ v_b_188_2 3)) (.cse2 (+ v_b_192_2 1)) (.cse1 (+ v_b_191_2 1)) (.cse21 (+ v_b_186_2 3)) (.cse29 (+ v_b_188_2 1)) (.cse4 (+ v_b_185_2 2)) (.cse27 (+ c_ULTIMATE.start_main_p1 5)) (.cse24 (+ v_b_189_2 1)) (.cse0 (+ v_b_184_2 1))) (and (<= v_b_185_2 .cse0) (<= .cse1 v_b_193_2) (<= .cse2 v_b_193_2) (<= .cse3 v_b_189_2) (<= .cse4 v_b_190_2) (or (< v_idx_270 v_b_192_2) (= 0 (select |c_#memory_int| v_idx_270)) (<= v_b_193_2 v_idx_270)) (or (= v_v_1525_2 (select |c_#memory_int| v_idx_269)) (<= v_b_192_2 v_idx_269) (< v_idx_269 v_b_191_2)) (<= .cse5 v_b_194_2) (<= .cse6 v_b_192_2) (<= .cse7 v_b_186_2) (or (= (select |c_#memory_int| v_idx_260) v_v_1516_2) (< v_idx_260 c_ULTIMATE.start_main_p1) (<= .cse8 v_idx_260)) (<= .cse9 v_b_194_2) (<= .cse10 v_b_191_2) (<= .cse11 v_b_190_2) (<= .cse12 v_b_194_2) (<= .cse13 v_b_192_2) (<= .cse8 v_b_184_2) (<= .cse14 v_b_191_2) (<= (+ v_b_185_2 5) v_b_195_2) (<= .cse15 v_b_190_2) (<= .cse16 v_b_191_2) (or (< v_idx_264 v_b_186_2) (= 0 (select |c_#memory_int| v_idx_264)) (<= v_b_187_2 v_idx_264)) (<= .cse3 v_b_190_2) (<= (+ v_b_190_2 3) v_b_195_2) (<= .cse5 v_b_193_2) (<= .cse9 v_b_193_2) (<= .cse17 v_b_193_2) (<= .cse0 v_b_186_2) (or (= 0 (select |c_#memory_int| v_idx_262)) (< v_idx_262 v_b_184_2) (<= v_b_185_2 v_idx_262)) (<= .cse11 v_b_189_2) (<= (+ v_b_189_2 3) v_b_195_2) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_2) (or (< v_idx_266 v_b_188_2) (<= v_b_189_2 v_idx_266) (= 0 (select |c_#memory_int| v_idx_266))) (<= .cse18 v_b_187_2) (<= .cse18 v_b_188_2) (<= .cse16 v_b_192_2) (<= 0 (* 2 v_v_1516_2)) (<= .cse19 v_b_188_2) (<= .cse20 v_b_193_2) (<= .cse14 v_b_192_2) (<= (+ v_b_184_2 6) v_b_195_2) (<= .cse21 v_b_192_2) (<= .cse22 v_b_189_2) (<= .cse7 v_b_185_2) (<= .cse23 v_b_194_2) (<= .cse24 v_b_192_2) (<= (+ v_b_192_2 2) v_b_195_2) (<= v_b_189_2 v_b_190_2) (<= .cse22 v_b_190_2) (<= v_b_187_2 v_b_188_2) (<= .cse25 v_b_187_2) (or (= (select |c_#memory_int| v_idx_271) v_v_1527_2) (< v_idx_271 v_b_193_2) (<= v_b_194_2 v_idx_271)) (or (= (select |c_#memory_int| v_idx_263) v_v_1519_2) (<= v_b_186_2 v_idx_263) (< v_idx_263 v_b_185_2)) (<= (+ v_b_191_2 2) v_b_195_2) (or (< v_idx_261 .cse8) (= (select |c_#memory_int| v_idx_261) v_v_1517_2) (<= v_b_184_2 v_idx_261)) (<= .cse2 v_b_194_2) (<= (+ v_b_188_2 4) v_b_195_2) (<= .cse26 v_b_194_2) (<= .cse27 v_b_191_2) (<= .cse15 v_b_189_2) (or (< v_idx_268 v_b_190_2) (= 0 (select |c_#memory_int| v_idx_268)) (<= v_b_191_2 v_idx_268)) (or (= (select |c_#memory_int| v_idx_259) v_v_1515_2) (<= c_ULTIMATE.start_main_p1 v_idx_259)) (<= (+ v_b_193_2 1) v_b_195_2) (<= .cse28 v_b_187_2) (<= v_b_187_2 .cse19) (<= .cse17 v_b_194_2) (<= .cse10 v_b_192_2) (<= .cse28 v_b_188_2) (<= .cse12 v_b_193_2) (<= v_b_193_2 v_b_194_2) (<= (+ v_b_186_2 5) v_b_195_2) (<= v_b_189_2 .cse29) (<= .cse19 v_b_187_2) (<= (+ v_b_187_2 4) v_b_195_2) (<= v_b_195_2 .cse30) (<= .cse31 v_b_193_2) (<= v_b_191_2 v_b_192_2) (<= 0 v_v_1516_2) (<= .cse23 v_b_193_2) (<= v_b_191_2 .cse13) (<= .cse31 v_b_194_2) (or (< v_idx_272 v_b_194_2) (<= v_b_195_2 v_idx_272) (= (select |c_#memory_int| v_idx_272) 0)) (<= .cse30 v_b_195_2) (<= .cse13 v_b_191_2) (<= .cse26 v_b_193_2) (or (= (select |c_#memory_int| v_idx_273) v_v_1529_2) (< v_idx_273 v_b_195_2)) (or (< v_idx_265 v_b_187_2) (= (select |c_#memory_int| v_idx_265) v_v_1521_2) (<= v_b_188_2 v_idx_265)) (<= .cse6 v_b_191_2) (<= .cse25 v_b_188_2) (<= .cse20 v_b_194_2) (<= v_b_193_2 .cse2) (<= .cse1 v_b_194_2) (<= v_b_185_2 v_b_186_2) (<= .cse29 v_b_190_2) (<= .cse21 v_b_191_2) (<= .cse29 v_b_189_2) (or (<= v_b_190_2 v_idx_267) (< v_idx_267 v_b_189_2) (= (select |c_#memory_int| v_idx_267) v_v_1523_2)) (<= .cse4 v_b_189_2) (<= .cse27 v_b_192_2) (<= .cse24 v_b_191_2) (<= .cse0 v_b_185_2))))) is different from true [2019-01-08 14:37:29,241 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_280 Int) (v_idx_278 Int) (v_idx_279 Int) (v_idx_283 Int) (v_idx_284 Int) (v_idx_281 Int) (v_idx_282 Int) (v_idx_287 Int) (v_idx_276 Int) (v_idx_288 Int) (v_idx_277 Int) (v_idx_285 Int) (v_idx_274 Int) (v_idx_286 Int) (v_idx_275 Int)) (exists ((v_v_1519_2 Int) (v_v_1529_2 Int) (v_b_194_2 Int) (v_b_193_2 Int) (v_b_184_2 Int) (v_b_185_2 Int) (v_b_195_2 Int) (v_b_186_2 Int) (v_b_187_2 Int) (v_b_188_2 Int) (v_b_189_2 Int) (v_v_1517_2 Int) (v_v_1516_2 Int) (v_v_1527_2 Int) (v_v_1515_2 Int) (v_v_1525_2 Int) (v_b_190_2 Int) (v_v_1523_2 Int) (v_b_192_2 Int) (v_b_191_2 Int) (v_v_1521_2 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse5 (+ v_b_185_2 4)) (.cse8 (+ c_ULTIMATE.start_main_p1 6)) (.cse10 (+ v_b_187_2 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 3)) (.cse16 (+ v_b_185_2 3)) (.cse14 (+ v_b_188_2 2)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse22 (+ v_b_184_2 3)) (.cse15 (+ v_b_186_2 2)) (.cse17 (+ v_b_187_2 3)) (.cse9 (+ v_b_184_2 4)) (.cse28 (+ v_b_185_2 1)) (.cse11 (+ v_b_190_2 2)) (.cse19 (+ v_b_186_2 1)) (.cse13 (+ c_ULTIMATE.start_main_p1 1)) (.cse23 (+ v_b_184_2 5)) (.cse31 (+ v_b_189_2 2)) (.cse30 (+ v_b_194_2 1)) (.cse12 (+ v_b_190_2 1)) (.cse26 (+ v_b_186_2 4)) (.cse6 (+ v_b_187_2 2)) (.cse25 (+ v_b_184_2 2)) (.cse20 (+ v_b_188_2 3)) (.cse2 (+ v_b_192_2 1)) (.cse1 (+ v_b_191_2 1)) (.cse21 (+ v_b_186_2 3)) (.cse29 (+ v_b_188_2 1)) (.cse4 (+ v_b_185_2 2)) (.cse27 (+ c_ULTIMATE.start_main_p1 5)) (.cse24 (+ v_b_189_2 1)) (.cse0 (+ v_b_184_2 1))) (and (<= v_b_185_2 .cse0) (<= .cse1 v_b_193_2) (<= .cse2 v_b_193_2) (<= .cse3 v_b_189_2) (or (<= v_b_189_2 v_idx_281) (< v_idx_281 v_b_188_2) (= 0 (select |c_#memory_int| v_idx_281))) (<= .cse4 v_b_190_2) (<= .cse5 v_b_194_2) (<= .cse6 v_b_192_2) (<= .cse7 v_b_186_2) (<= .cse8 v_b_194_2) (<= .cse9 v_b_191_2) (<= .cse10 v_b_190_2) (<= .cse11 v_b_194_2) (<= .cse12 v_b_192_2) (<= .cse13 v_b_184_2) (<= .cse14 v_b_191_2) (<= (+ v_b_185_2 5) v_b_195_2) (<= .cse15 v_b_190_2) (or (= (select |c_#memory_int| v_idx_284) v_v_1525_2) (< v_idx_284 v_b_191_2) (<= v_b_192_2 v_idx_284)) (<= .cse16 v_b_191_2) (<= .cse3 v_b_190_2) (<= (+ v_b_190_2 3) v_b_195_2) (<= .cse5 v_b_193_2) (<= .cse8 v_b_193_2) (<= .cse17 v_b_193_2) (<= .cse0 v_b_186_2) (or (< v_idx_275 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_275) v_v_1516_2) (<= .cse13 v_idx_275)) (or (= (select |c_#memory_int| v_idx_274) v_v_1515_2) (<= c_ULTIMATE.start_main_p1 v_idx_274)) (<= .cse10 v_b_189_2) (<= (+ v_b_189_2 3) v_b_195_2) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_2) (<= .cse18 v_b_187_2) (<= .cse18 v_b_188_2) (<= .cse16 v_b_192_2) (<= 0 (* 2 v_v_1516_2)) (or (= (select |c_#memory_int| v_idx_278) v_v_1519_2) (<= v_b_186_2 v_idx_278) (< v_idx_278 v_b_185_2)) (<= .cse19 v_b_188_2) (or (<= v_b_185_2 v_idx_277) (< v_idx_277 v_b_184_2) (= 0 (select |c_#memory_int| v_idx_277))) (<= .cse20 v_b_193_2) (<= .cse14 v_b_192_2) (<= (+ v_b_184_2 6) v_b_195_2) (<= .cse21 v_b_192_2) (<= .cse22 v_b_189_2) (<= .cse7 v_b_185_2) (<= .cse23 v_b_194_2) (<= .cse24 v_b_192_2) (<= (+ v_b_192_2 2) v_b_195_2) (<= v_b_189_2 v_b_190_2) (or (<= v_b_187_2 v_idx_279) (< v_idx_279 v_b_186_2) (= (select |c_#memory_int| v_idx_279) 0)) (<= .cse22 v_b_190_2) (<= v_b_187_2 v_b_188_2) (<= .cse25 v_b_187_2) (or (< v_idx_288 v_b_195_2) (= (select |c_#memory_int| v_idx_288) v_v_1529_2)) (<= (+ v_b_191_2 2) v_b_195_2) (<= .cse2 v_b_194_2) (<= (+ v_b_188_2 4) v_b_195_2) (<= .cse26 v_b_194_2) (<= .cse27 v_b_191_2) (<= .cse15 v_b_189_2) (<= (+ v_b_193_2 1) v_b_195_2) (<= .cse28 v_b_187_2) (<= v_b_187_2 .cse19) (or (= 0 (select |c_#memory_int| v_idx_287)) (< v_idx_287 v_b_194_2) (<= v_b_195_2 v_idx_287)) (<= .cse17 v_b_194_2) (<= .cse9 v_b_192_2) (<= .cse28 v_b_188_2) (<= .cse11 v_b_193_2) (<= v_b_193_2 v_b_194_2) (<= (+ v_b_186_2 5) v_b_195_2) (<= v_b_189_2 .cse29) (<= .cse19 v_b_187_2) (<= (+ v_b_187_2 4) v_b_195_2) (<= v_b_195_2 .cse30) (<= .cse31 v_b_193_2) (<= v_b_191_2 v_b_192_2) (<= 0 v_v_1516_2) (or (= (select |c_#memory_int| v_idx_276) v_v_1517_2) (<= v_b_184_2 v_idx_276) (< v_idx_276 .cse13)) (<= .cse23 v_b_193_2) (<= v_b_191_2 .cse12) (<= .cse31 v_b_194_2) (or (<= v_b_193_2 v_idx_285) (= 0 (select |c_#memory_int| v_idx_285)) (< v_idx_285 v_b_192_2)) (or (= (select |c_#memory_int| v_idx_282) v_v_1523_2) (< v_idx_282 v_b_189_2) (<= v_b_190_2 v_idx_282)) (or (= (select |c_#memory_int| v_idx_286) v_v_1527_2) (< v_idx_286 v_b_193_2) (<= v_b_194_2 v_idx_286)) (<= .cse30 v_b_195_2) (<= .cse12 v_b_191_2) (<= .cse26 v_b_193_2) (<= .cse6 v_b_191_2) (<= .cse25 v_b_188_2) (<= .cse20 v_b_194_2) (<= v_b_193_2 .cse2) (<= .cse1 v_b_194_2) (<= v_b_185_2 v_b_186_2) (<= .cse29 v_b_190_2) (or (< v_idx_283 v_b_190_2) (= 0 (select |c_#memory_int| v_idx_283)) (<= v_b_191_2 v_idx_283)) (<= .cse21 v_b_191_2) (<= .cse29 v_b_189_2) (<= .cse4 v_b_189_2) (<= .cse27 v_b_192_2) (<= .cse24 v_b_191_2) (<= .cse0 v_b_185_2) (or (= (select |c_#memory_int| v_idx_280) v_v_1521_2) (< v_idx_280 v_b_187_2) (<= v_b_188_2 v_idx_280)))))) is different from false [2019-01-08 14:37:29,385 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:37:29,385 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:37:29,385 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:37:29,385 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:37:29,386 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:37:29,386 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:37:29,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:37:29,386 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=2, Unknown=3, NotChecked=2, Total=12 [2019-01-08 14:37:29,386 INFO L87 Difference]: Start difference. First operand 18 states and 38 transitions. Second operand 4 states. [2019-01-08 14:37:32,085 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_269 Int) (v_idx_259 Int) (v_idx_267 Int) (v_idx_268 Int) (v_idx_261 Int) (v_idx_272 Int) (v_idx_262 Int) (v_idx_273 Int) (v_idx_270 Int) (v_idx_260 Int) (v_idx_271 Int) (v_idx_265 Int) (v_idx_266 Int) (v_idx_263 Int) (v_idx_264 Int)) (exists ((v_v_1519_2 Int) (v_v_1529_2 Int) (v_b_194_2 Int) (v_b_193_2 Int) (v_b_184_2 Int) (v_b_185_2 Int) (v_b_195_2 Int) (v_b_186_2 Int) (v_b_187_2 Int) (v_b_188_2 Int) (v_b_189_2 Int) (v_v_1517_2 Int) (v_v_1516_2 Int) (v_v_1527_2 Int) (v_v_1515_2 Int) (v_v_1525_2 Int) (v_b_190_2 Int) (v_v_1523_2 Int) (v_b_192_2 Int) (v_b_191_2 Int) (v_v_1521_2 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse5 (+ v_b_185_2 4)) (.cse9 (+ c_ULTIMATE.start_main_p1 6)) (.cse11 (+ v_b_187_2 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 3)) (.cse16 (+ v_b_185_2 3)) (.cse14 (+ v_b_188_2 2)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse22 (+ v_b_184_2 3)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse15 (+ v_b_186_2 2)) (.cse17 (+ v_b_187_2 3)) (.cse10 (+ v_b_184_2 4)) (.cse28 (+ v_b_185_2 1)) (.cse12 (+ v_b_190_2 2)) (.cse19 (+ v_b_186_2 1)) (.cse23 (+ v_b_184_2 5)) (.cse31 (+ v_b_189_2 2)) (.cse30 (+ v_b_194_2 1)) (.cse13 (+ v_b_190_2 1)) (.cse26 (+ v_b_186_2 4)) (.cse6 (+ v_b_187_2 2)) (.cse25 (+ v_b_184_2 2)) (.cse20 (+ v_b_188_2 3)) (.cse2 (+ v_b_192_2 1)) (.cse1 (+ v_b_191_2 1)) (.cse21 (+ v_b_186_2 3)) (.cse29 (+ v_b_188_2 1)) (.cse4 (+ v_b_185_2 2)) (.cse27 (+ c_ULTIMATE.start_main_p1 5)) (.cse24 (+ v_b_189_2 1)) (.cse0 (+ v_b_184_2 1))) (and (<= v_b_185_2 .cse0) (<= .cse1 v_b_193_2) (<= .cse2 v_b_193_2) (<= .cse3 v_b_189_2) (<= .cse4 v_b_190_2) (or (< v_idx_270 v_b_192_2) (= 0 (select |c_#memory_int| v_idx_270)) (<= v_b_193_2 v_idx_270)) (or (= v_v_1525_2 (select |c_#memory_int| v_idx_269)) (<= v_b_192_2 v_idx_269) (< v_idx_269 v_b_191_2)) (<= .cse5 v_b_194_2) (<= .cse6 v_b_192_2) (<= .cse7 v_b_186_2) (or (= (select |c_#memory_int| v_idx_260) v_v_1516_2) (< v_idx_260 c_ULTIMATE.start_main_p1) (<= .cse8 v_idx_260)) (<= .cse9 v_b_194_2) (<= .cse10 v_b_191_2) (<= .cse11 v_b_190_2) (<= .cse12 v_b_194_2) (<= .cse13 v_b_192_2) (<= .cse8 v_b_184_2) (<= .cse14 v_b_191_2) (<= (+ v_b_185_2 5) v_b_195_2) (<= .cse15 v_b_190_2) (<= .cse16 v_b_191_2) (or (< v_idx_264 v_b_186_2) (= 0 (select |c_#memory_int| v_idx_264)) (<= v_b_187_2 v_idx_264)) (<= .cse3 v_b_190_2) (<= (+ v_b_190_2 3) v_b_195_2) (<= .cse5 v_b_193_2) (<= .cse9 v_b_193_2) (<= .cse17 v_b_193_2) (<= .cse0 v_b_186_2) (or (= 0 (select |c_#memory_int| v_idx_262)) (< v_idx_262 v_b_184_2) (<= v_b_185_2 v_idx_262)) (<= .cse11 v_b_189_2) (<= (+ v_b_189_2 3) v_b_195_2) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_2) (or (< v_idx_266 v_b_188_2) (<= v_b_189_2 v_idx_266) (= 0 (select |c_#memory_int| v_idx_266))) (<= .cse18 v_b_187_2) (<= .cse18 v_b_188_2) (<= .cse16 v_b_192_2) (<= 0 (* 2 v_v_1516_2)) (<= .cse19 v_b_188_2) (<= .cse20 v_b_193_2) (<= .cse14 v_b_192_2) (<= (+ v_b_184_2 6) v_b_195_2) (<= .cse21 v_b_192_2) (<= .cse22 v_b_189_2) (<= .cse7 v_b_185_2) (<= .cse23 v_b_194_2) (<= .cse24 v_b_192_2) (<= (+ v_b_192_2 2) v_b_195_2) (<= v_b_189_2 v_b_190_2) (<= .cse22 v_b_190_2) (<= v_b_187_2 v_b_188_2) (<= .cse25 v_b_187_2) (or (= (select |c_#memory_int| v_idx_271) v_v_1527_2) (< v_idx_271 v_b_193_2) (<= v_b_194_2 v_idx_271)) (or (= (select |c_#memory_int| v_idx_263) v_v_1519_2) (<= v_b_186_2 v_idx_263) (< v_idx_263 v_b_185_2)) (<= (+ v_b_191_2 2) v_b_195_2) (or (< v_idx_261 .cse8) (= (select |c_#memory_int| v_idx_261) v_v_1517_2) (<= v_b_184_2 v_idx_261)) (<= .cse2 v_b_194_2) (<= (+ v_b_188_2 4) v_b_195_2) (<= .cse26 v_b_194_2) (<= .cse27 v_b_191_2) (<= .cse15 v_b_189_2) (or (< v_idx_268 v_b_190_2) (= 0 (select |c_#memory_int| v_idx_268)) (<= v_b_191_2 v_idx_268)) (or (= (select |c_#memory_int| v_idx_259) v_v_1515_2) (<= c_ULTIMATE.start_main_p1 v_idx_259)) (<= (+ v_b_193_2 1) v_b_195_2) (<= .cse28 v_b_187_2) (<= v_b_187_2 .cse19) (<= .cse17 v_b_194_2) (<= .cse10 v_b_192_2) (<= .cse28 v_b_188_2) (<= .cse12 v_b_193_2) (<= v_b_193_2 v_b_194_2) (<= (+ v_b_186_2 5) v_b_195_2) (<= v_b_189_2 .cse29) (<= .cse19 v_b_187_2) (<= (+ v_b_187_2 4) v_b_195_2) (<= v_b_195_2 .cse30) (<= .cse31 v_b_193_2) (<= v_b_191_2 v_b_192_2) (<= 0 v_v_1516_2) (<= .cse23 v_b_193_2) (<= v_b_191_2 .cse13) (<= .cse31 v_b_194_2) (or (< v_idx_272 v_b_194_2) (<= v_b_195_2 v_idx_272) (= (select |c_#memory_int| v_idx_272) 0)) (<= .cse30 v_b_195_2) (<= .cse13 v_b_191_2) (<= .cse26 v_b_193_2) (or (= (select |c_#memory_int| v_idx_273) v_v_1529_2) (< v_idx_273 v_b_195_2)) (or (< v_idx_265 v_b_187_2) (= (select |c_#memory_int| v_idx_265) v_v_1521_2) (<= v_b_188_2 v_idx_265)) (<= .cse6 v_b_191_2) (<= .cse25 v_b_188_2) (<= .cse20 v_b_194_2) (<= v_b_193_2 .cse2) (<= .cse1 v_b_194_2) (<= v_b_185_2 v_b_186_2) (<= .cse29 v_b_190_2) (<= .cse21 v_b_191_2) (<= .cse29 v_b_189_2) (or (<= v_b_190_2 v_idx_267) (< v_idx_267 v_b_189_2) (= (select |c_#memory_int| v_idx_267) v_v_1523_2)) (<= .cse4 v_b_189_2) (<= .cse27 v_b_192_2) (<= .cse24 v_b_191_2) (<= .cse0 v_b_185_2))))) (forall ((v_idx_280 Int) (v_idx_278 Int) (v_idx_279 Int) (v_idx_283 Int) (v_idx_284 Int) (v_idx_281 Int) (v_idx_282 Int) (v_idx_287 Int) (v_idx_276 Int) (v_idx_288 Int) (v_idx_277 Int) (v_idx_285 Int) (v_idx_274 Int) (v_idx_286 Int) (v_idx_275 Int)) (exists ((v_v_1519_2 Int) (v_v_1529_2 Int) (v_b_194_2 Int) (v_b_193_2 Int) (v_b_184_2 Int) (v_b_185_2 Int) (v_b_195_2 Int) (v_b_186_2 Int) (v_b_187_2 Int) (v_b_188_2 Int) (v_b_189_2 Int) (v_v_1517_2 Int) (v_v_1516_2 Int) (v_v_1527_2 Int) (v_v_1515_2 Int) (v_v_1525_2 Int) (v_b_190_2 Int) (v_v_1523_2 Int) (v_b_192_2 Int) (v_b_191_2 Int) (v_v_1521_2 Int)) (let ((.cse35 (+ c_ULTIMATE.start_main_p1 4)) (.cse37 (+ v_b_185_2 4)) (.cse40 (+ c_ULTIMATE.start_main_p1 6)) (.cse42 (+ v_b_187_2 1)) (.cse50 (+ c_ULTIMATE.start_main_p1 3)) (.cse48 (+ v_b_185_2 3)) (.cse46 (+ v_b_188_2 2)) (.cse39 (+ c_ULTIMATE.start_main_p1 2)) (.cse54 (+ v_b_184_2 3)) (.cse47 (+ v_b_186_2 2)) (.cse49 (+ v_b_187_2 3)) (.cse41 (+ v_b_184_2 4)) (.cse60 (+ v_b_185_2 1)) (.cse43 (+ v_b_190_2 2)) (.cse51 (+ v_b_186_2 1)) (.cse45 (+ c_ULTIMATE.start_main_p1 1)) (.cse55 (+ v_b_184_2 5)) (.cse63 (+ v_b_189_2 2)) (.cse62 (+ v_b_194_2 1)) (.cse44 (+ v_b_190_2 1)) (.cse58 (+ v_b_186_2 4)) (.cse38 (+ v_b_187_2 2)) (.cse57 (+ v_b_184_2 2)) (.cse52 (+ v_b_188_2 3)) (.cse34 (+ v_b_192_2 1)) (.cse33 (+ v_b_191_2 1)) (.cse53 (+ v_b_186_2 3)) (.cse61 (+ v_b_188_2 1)) (.cse36 (+ v_b_185_2 2)) (.cse59 (+ c_ULTIMATE.start_main_p1 5)) (.cse56 (+ v_b_189_2 1)) (.cse32 (+ v_b_184_2 1))) (and (<= v_b_185_2 .cse32) (<= .cse33 v_b_193_2) (<= .cse34 v_b_193_2) (<= .cse35 v_b_189_2) (or (<= v_b_189_2 v_idx_281) (< v_idx_281 v_b_188_2) (= 0 (select |c_#memory_int| v_idx_281))) (<= .cse36 v_b_190_2) (<= .cse37 v_b_194_2) (<= .cse38 v_b_192_2) (<= .cse39 v_b_186_2) (<= .cse40 v_b_194_2) (<= .cse41 v_b_191_2) (<= .cse42 v_b_190_2) (<= .cse43 v_b_194_2) (<= .cse44 v_b_192_2) (<= .cse45 v_b_184_2) (<= .cse46 v_b_191_2) (<= (+ v_b_185_2 5) v_b_195_2) (<= .cse47 v_b_190_2) (or (= (select |c_#memory_int| v_idx_284) v_v_1525_2) (< v_idx_284 v_b_191_2) (<= v_b_192_2 v_idx_284)) (<= .cse48 v_b_191_2) (<= .cse35 v_b_190_2) (<= (+ v_b_190_2 3) v_b_195_2) (<= .cse37 v_b_193_2) (<= .cse40 v_b_193_2) (<= .cse49 v_b_193_2) (<= .cse32 v_b_186_2) (or (< v_idx_275 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_275) v_v_1516_2) (<= .cse45 v_idx_275)) (or (= (select |c_#memory_int| v_idx_274) v_v_1515_2) (<= c_ULTIMATE.start_main_p1 v_idx_274)) (<= .cse42 v_b_189_2) (<= (+ v_b_189_2 3) v_b_195_2) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_2) (<= .cse50 v_b_187_2) (<= .cse50 v_b_188_2) (<= .cse48 v_b_192_2) (<= 0 (* 2 v_v_1516_2)) (or (= (select |c_#memory_int| v_idx_278) v_v_1519_2) (<= v_b_186_2 v_idx_278) (< v_idx_278 v_b_185_2)) (<= .cse51 v_b_188_2) (or (<= v_b_185_2 v_idx_277) (< v_idx_277 v_b_184_2) (= 0 (select |c_#memory_int| v_idx_277))) (<= .cse52 v_b_193_2) (<= .cse46 v_b_192_2) (<= (+ v_b_184_2 6) v_b_195_2) (<= .cse53 v_b_192_2) (<= .cse54 v_b_189_2) (<= .cse39 v_b_185_2) (<= .cse55 v_b_194_2) (<= .cse56 v_b_192_2) (<= (+ v_b_192_2 2) v_b_195_2) (<= v_b_189_2 v_b_190_2) (or (<= v_b_187_2 v_idx_279) (< v_idx_279 v_b_186_2) (= (select |c_#memory_int| v_idx_279) 0)) (<= .cse54 v_b_190_2) (<= v_b_187_2 v_b_188_2) (<= .cse57 v_b_187_2) (or (< v_idx_288 v_b_195_2) (= (select |c_#memory_int| v_idx_288) v_v_1529_2)) (<= (+ v_b_191_2 2) v_b_195_2) (<= .cse34 v_b_194_2) (<= (+ v_b_188_2 4) v_b_195_2) (<= .cse58 v_b_194_2) (<= .cse59 v_b_191_2) (<= .cse47 v_b_189_2) (<= (+ v_b_193_2 1) v_b_195_2) (<= .cse60 v_b_187_2) (<= v_b_187_2 .cse51) (or (= 0 (select |c_#memory_int| v_idx_287)) (< v_idx_287 v_b_194_2) (<= v_b_195_2 v_idx_287)) (<= .cse49 v_b_194_2) (<= .cse41 v_b_192_2) (<= .cse60 v_b_188_2) (<= .cse43 v_b_193_2) (<= v_b_193_2 v_b_194_2) (<= (+ v_b_186_2 5) v_b_195_2) (<= v_b_189_2 .cse61) (<= .cse51 v_b_187_2) (<= (+ v_b_187_2 4) v_b_195_2) (<= v_b_195_2 .cse62) (<= .cse63 v_b_193_2) (<= v_b_191_2 v_b_192_2) (<= 0 v_v_1516_2) (or (= (select |c_#memory_int| v_idx_276) v_v_1517_2) (<= v_b_184_2 v_idx_276) (< v_idx_276 .cse45)) (<= .cse55 v_b_193_2) (<= v_b_191_2 .cse44) (<= .cse63 v_b_194_2) (or (<= v_b_193_2 v_idx_285) (= 0 (select |c_#memory_int| v_idx_285)) (< v_idx_285 v_b_192_2)) (or (= (select |c_#memory_int| v_idx_282) v_v_1523_2) (< v_idx_282 v_b_189_2) (<= v_b_190_2 v_idx_282)) (or (= (select |c_#memory_int| v_idx_286) v_v_1527_2) (< v_idx_286 v_b_193_2) (<= v_b_194_2 v_idx_286)) (<= .cse62 v_b_195_2) (<= .cse44 v_b_191_2) (<= .cse58 v_b_193_2) (<= .cse38 v_b_191_2) (<= .cse57 v_b_188_2) (<= .cse52 v_b_194_2) (<= v_b_193_2 .cse34) (<= .cse33 v_b_194_2) (<= v_b_185_2 v_b_186_2) (<= .cse61 v_b_190_2) (or (< v_idx_283 v_b_190_2) (= 0 (select |c_#memory_int| v_idx_283)) (<= v_b_191_2 v_idx_283)) (<= .cse53 v_b_191_2) (<= .cse61 v_b_189_2) (<= .cse36 v_b_189_2) (<= .cse59 v_b_192_2) (<= .cse56 v_b_191_2) (<= .cse32 v_b_185_2) (or (= (select |c_#memory_int| v_idx_280) v_v_1521_2) (< v_idx_280 v_b_187_2) (<= v_b_188_2 v_idx_280))))))) is different from false [2019-01-08 14:38:06,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:38:06,681 INFO L93 Difference]: Finished difference Result 20 states and 47 transitions. [2019-01-08 14:38:06,681 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-08 14:38:06,681 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-08 14:38:06,681 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:38:06,682 INFO L225 Difference]: With dead ends: 20 [2019-01-08 14:38:06,682 INFO L226 Difference]: Without dead ends: 19 [2019-01-08 14:38:06,683 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 9.6s TimeCoverageRelationStatistics Valid=7, Invalid=3, Unknown=4, NotChecked=6, Total=20 [2019-01-08 14:38:06,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2019-01-08 14:38:06,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 18. [2019-01-08 14:38:06,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2019-01-08 14:38:06,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 38 transitions. [2019-01-08 14:38:06,692 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 38 transitions. Word has length 3 [2019-01-08 14:38:06,692 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:38:06,692 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 38 transitions. [2019-01-08 14:38:06,692 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:38:06,693 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 38 transitions. [2019-01-08 14:38:06,693 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:38:06,693 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:38:06,693 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:38:06,693 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:38:06,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:38:06,694 INFO L82 PathProgramCache]: Analyzing trace with hash 30504, now seen corresponding path program 1 times [2019-01-08 14:38:06,694 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:38:06,695 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:06,695 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:38:06,695 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:06,695 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:38:06,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:38:06,763 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:38:06,764 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:38:06,764 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:38:06,764 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:38:06,765 INFO L207 CegarAbsIntRunner]: [0], [22], [31] [2019-01-08 14:38:06,772 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:38:06,772 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:38:19,618 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:38:19,618 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:38:19,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:38:19,618 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:38:20,232 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 77.27% of their original sizes. [2019-01-08 14:38:20,233 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:38:23,091 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_409 Int) (v_idx_407 Int) (v_idx_408 Int) (v_idx_412 Int) (v_idx_413 Int) (v_idx_410 Int) (v_idx_411 Int) (v_idx_405 Int) (v_idx_416 Int) (v_idx_406 Int) (v_idx_417 Int) (v_idx_403 Int) (v_idx_414 Int) (v_idx_404 Int) (v_idx_415 Int)) (exists ((v_b_189_3 Int) (v_v_1749_3 Int) (v_v_1759_3 Int) (v_b_193_3 Int) (v_v_1751_3 Int) (v_b_192_3 Int) (v_b_195_3 Int) (v_v_1754_3 Int) (v_b_184_3 Int) (v_b_194_3 Int) (v_v_1753_3 Int) (v_b_185_3 Int) (v_b_186_3 Int) (v_v_1755_3 Int) (v_v_1745_3 Int) (v_b_187_3 Int) (v_v_1747_3 Int) (v_b_188_3 Int) (v_v_1757_3 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p1 6)) (.cse6 (+ v_b_185_3 1)) (.cse4 (+ v_b_186_3 2)) (.cse0 (+ c_ULTIMATE.start_main_p5 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 3)) (.cse2 (+ v_b_188_3 1)) (.cse15 (+ c_ULTIMATE.start_main_p1 4)) (.cse12 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_185_3 4)) (.cse3 (+ v_b_184_3 2)) (.cse19 (+ v_b_184_3 5)) (.cse18 (+ v_b_186_3 4)) (.cse14 (+ c_ULTIMATE.start_main_p1 2)) (.cse22 (+ v_b_189_3 2)) (.cse20 (+ v_b_194_3 1)) (.cse16 (+ v_b_187_3 1)) (.cse23 (+ v_b_184_3 3)) (.cse17 (+ v_b_186_3 1)) (.cse9 (+ v_b_192_3 1)) (.cse13 (+ v_b_188_3 3)) (.cse10 (+ c_ULTIMATE.start_main_p5 2)) (.cse11 (+ v_b_184_3 1)) (.cse5 (+ v_b_185_3 2)) (.cse21 (+ v_b_187_3 3))) (and (<= (+ v_b_185_3 3) v_b_192_3) (<= .cse0 v_b_192_3) (<= (+ v_b_184_3 6) v_b_195_3) (or (= (select |c_#memory_int| v_idx_408) 0) (< v_idx_408 v_b_186_3) (<= v_b_187_3 v_idx_408)) (<= .cse1 v_b_193_3) (<= v_b_189_3 .cse2) (or (<= v_b_195_3 v_idx_416) (= (select |c_#memory_int| v_idx_416) 0) (< v_idx_416 v_b_194_3)) (<= .cse3 v_b_187_3) (<= .cse4 v_b_189_3) (<= (+ v_b_189_3 1) v_b_192_3) (<= .cse5 c_ULTIMATE.start_main_p5) (<= (+ v_b_184_3 4) v_b_192_3) (<= v_b_185_3 v_b_186_3) (or (<= .cse0 v_idx_412) (< v_idx_412 c_ULTIMATE.start_main_p5) (= (select |c_#memory_int| v_idx_412) v_v_1754_3)) (<= .cse6 v_b_187_3) (<= .cse2 v_b_189_3) (<= .cse7 v_b_187_3) (<= .cse8 v_b_193_3) (<= v_b_193_3 .cse9) (<= .cse8 v_b_194_3) (<= .cse6 v_b_188_3) (or (= (select |c_#memory_int| v_idx_409) v_v_1751_3) (<= v_b_188_3 v_idx_409) (< v_idx_409 v_b_187_3)) (<= .cse10 v_b_193_3) (<= .cse4 c_ULTIMATE.start_main_p5) (<= .cse11 v_b_186_3) (or (< v_idx_414 v_b_192_3) (= (select |c_#memory_int| v_idx_414) 0) (<= v_b_193_3 v_idx_414)) (<= .cse12 v_b_184_3) (<= (+ v_b_187_3 2) v_b_192_3) (<= v_b_187_3 v_b_188_3) (or (= (select |c_#memory_int| v_idx_410) 0) (<= v_b_189_3 v_idx_410) (< v_idx_410 v_b_188_3)) (<= .cse13 v_b_193_3) (or (= (select |c_#memory_int| v_idx_413) v_v_1755_3) (<= v_b_192_3 v_idx_413) (< v_idx_413 .cse0)) (<= .cse9 v_b_194_3) (<= (+ v_b_186_3 5) v_b_195_3) (<= .cse7 v_b_188_3) (<= .cse14 v_b_186_3) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_3) (<= .cse15 c_ULTIMATE.start_main_p5) (<= .cse16 c_ULTIMATE.start_main_p5) (<= v_b_187_3 .cse17) (<= .cse18 v_b_194_3) (or (< v_idx_415 v_b_193_3) (<= v_b_194_3 v_idx_415) (= (select |c_#memory_int| v_idx_415) v_v_1757_3)) (<= .cse19 v_b_194_3) (<= v_b_185_3 .cse11) (<= (+ v_b_188_3 4) v_b_195_3) (or (= (select |c_#memory_int| v_idx_417) v_v_1759_3) (< v_idx_417 v_b_195_3)) (or (< v_idx_404 c_ULTIMATE.start_main_p1) (<= .cse12 v_idx_404) (= (select |c_#memory_int| v_idx_404) 0)) (<= v_b_193_3 v_b_194_3) (<= v_b_189_3 c_ULTIMATE.start_main_p5) (<= .cse2 c_ULTIMATE.start_main_p5) (<= (+ v_b_185_3 5) v_b_195_3) (<= .cse15 v_b_189_3) (or (<= v_b_184_3 v_idx_405) (= (select |c_#memory_int| v_idx_405) v_v_1747_3) (< v_idx_405 .cse12)) (<= (+ v_b_193_3 1) v_b_195_3) (<= (+ v_b_192_3 2) v_b_195_3) (<= .cse1 v_b_194_3) (<= .cse3 v_b_188_3) (<= .cse19 v_b_193_3) (<= .cse20 v_b_195_3) (<= .cse17 v_b_188_3) (<= .cse18 v_b_193_3) (or (< v_idx_406 v_b_184_3) (= (select |c_#memory_int| v_idx_406) 0) (<= v_b_185_3 v_idx_406)) (or (= (select |c_#memory_int| v_idx_407) v_v_1749_3) (< v_idx_407 v_b_185_3) (<= v_b_186_3 v_idx_407)) (<= .cse14 v_b_185_3) (<= .cse21 v_b_193_3) (<= .cse22 v_b_193_3) (<= 0 v_v_1754_3) (<= (+ v_b_189_3 3) v_b_195_3) (<= (+ v_b_188_3 2) v_b_192_3) (<= .cse22 v_b_194_3) (<= 0 (* 2 v_v_1754_3)) (<= .cse23 c_ULTIMATE.start_main_p5) (<= (+ v_b_186_3 3) v_b_192_3) (<= v_b_195_3 .cse20) (<= .cse16 v_b_189_3) (<= .cse23 v_b_189_3) (<= .cse17 v_b_187_3) (or (< v_idx_411 v_b_189_3) (= (select |c_#memory_int| v_idx_411) v_v_1753_3) (<= c_ULTIMATE.start_main_p5 v_idx_411)) (<= .cse9 v_b_193_3) (<= .cse13 v_b_194_3) (<= .cse10 v_b_194_3) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_192_3) (<= .cse11 v_b_185_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_403) (= (select |c_#memory_int| v_idx_403) v_v_1745_3)) (<= .cse5 v_b_189_3) (<= (+ c_ULTIMATE.start_main_p5 3) v_b_195_3) (<= .cse21 v_b_194_3) (<= (+ v_b_187_3 4) v_b_195_3))))) is different from false [2019-01-08 14:38:25,542 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_429 Int) (v_idx_418 Int) (v_idx_419 Int) (v_idx_423 Int) (v_idx_424 Int) (v_idx_421 Int) (v_idx_432 Int) (v_idx_422 Int) (v_idx_427 Int) (v_idx_428 Int) (v_idx_425 Int) (v_idx_426 Int) (v_idx_430 Int) (v_idx_420 Int) (v_idx_431 Int)) (exists ((v_b_189_3 Int) (v_v_1749_3 Int) (v_v_1759_3 Int) (v_b_193_3 Int) (v_b_192_3 Int) (v_v_1751_3 Int) (v_b_195_3 Int) (v_v_1754_3 Int) (v_b_184_3 Int) (v_b_194_3 Int) (v_v_1753_3 Int) (v_b_185_3 Int) (v_v_1755_3 Int) (v_v_1745_3 Int) (v_b_186_3 Int) (v_b_187_3 Int) (v_v_1747_3 Int) (v_b_188_3 Int) (v_v_1757_3 Int) (v_b_191_3 Int) (v_b_190_3 Int)) (let ((.cse7 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ v_b_185_3 4)) (.cse1 (+ v_b_184_3 2)) (.cse3 (+ v_b_184_3 4)) (.cse14 (+ v_b_189_3 2)) (.cse6 (+ v_b_191_3 1)) (.cse2 (+ v_b_184_3 3)) (.cse4 (+ c_ULTIMATE.start_main_p1 5)) (.cse25 (+ c_ULTIMATE.start_main_p1 6)) (.cse5 (+ v_b_185_3 1)) (.cse21 (+ v_b_188_3 1)) (.cse13 (+ c_ULTIMATE.start_main_p1 4)) (.cse17 (+ v_b_192_3 1)) (.cse8 (+ v_b_187_3 2)) (.cse24 (+ c_ULTIMATE.start_main_p1 3)) (.cse20 (+ v_b_185_3 3)) (.cse23 (+ v_b_189_3 1)) (.cse18 (+ v_b_184_3 1)) (.cse29 (+ v_b_184_3 5)) (.cse16 (+ v_b_186_3 1)) (.cse12 (+ v_b_186_3 4)) (.cse15 (+ v_b_188_3 2)) (.cse27 (+ c_ULTIMATE.start_main_p1 2)) (.cse28 (+ v_b_186_3 3)) (.cse30 (+ v_b_194_3 1)) (.cse26 (+ v_b_190_3 2)) (.cse11 (+ v_b_187_3 1)) (.cse10 (+ v_b_190_3 1)) (.cse9 (+ v_b_188_3 3)) (.cse19 (+ v_b_185_3 2)) (.cse22 (+ v_b_186_3 2)) (.cse31 (+ v_b_187_3 3))) (and (or (= (select |c_#memory_int| v_idx_418) v_v_1745_3) (<= c_ULTIMATE.start_main_p1 v_idx_418)) (<= .cse0 v_b_193_3) (<= .cse1 v_b_187_3) (<= .cse2 v_b_190_3) (<= .cse3 v_b_192_3) (<= .cse4 v_b_191_3) (<= .cse5 v_b_187_3) (or (<= v_b_195_3 v_idx_431) (< v_idx_431 v_b_194_3) (= (select |c_#memory_int| v_idx_431) 0)) (or (< v_idx_429 v_b_192_3) (= (select |c_#memory_int| v_idx_429) 0) (<= v_b_193_3 v_idx_429)) (<= .cse6 v_b_193_3) (<= .cse7 v_b_184_3) (<= .cse8 v_b_192_3) (<= v_b_187_3 v_b_188_3) (<= .cse9 v_b_193_3) (<= (+ v_b_186_3 5) v_b_195_3) (or (< v_idx_419 c_ULTIMATE.start_main_p1) (<= .cse7 v_idx_419) (= (select |c_#memory_int| v_idx_419) 0)) (<= .cse10 v_b_191_3) (<= .cse11 v_b_190_3) (or (= (select |c_#memory_int| v_idx_428) v_v_1755_3) (< v_idx_428 v_b_191_3) (<= v_b_192_3 v_idx_428)) (<= .cse12 v_b_194_3) (or (<= v_b_189_3 v_idx_425) (< v_idx_425 v_b_188_3) (= (select |c_#memory_int| v_idx_425) 0)) (<= (+ v_b_188_3 4) v_b_195_3) (<= .cse13 v_b_189_3) (or (<= v_b_184_3 v_idx_420) (= (select |c_#memory_int| v_idx_420) v_v_1747_3) (< v_idx_420 .cse7)) (<= (+ v_b_193_3 1) v_b_195_3) (<= (+ v_b_192_3 2) v_b_195_3) (<= .cse0 v_b_194_3) (<= .cse1 v_b_188_3) (<= .cse3 v_b_191_3) (<= .cse14 v_b_193_3) (<= 0 v_v_1754_3) (<= (+ v_b_189_3 3) v_b_195_3) (<= .cse15 v_b_192_3) (<= .cse14 v_b_194_3) (<= 0 (* 2 v_v_1754_3)) (<= v_b_189_3 v_b_190_3) (<= .cse6 v_b_194_3) (<= .cse2 v_b_189_3) (<= .cse16 v_b_187_3) (<= .cse17 v_b_193_3) (<= .cse4 v_b_192_3) (<= .cse18 v_b_185_3) (<= .cse19 v_b_189_3) (or (< v_idx_426 v_b_189_3) (= (select |c_#memory_int| v_idx_426) v_v_1753_3) (<= v_b_190_3 v_idx_426)) (<= .cse20 v_b_192_3) (<= (+ v_b_184_3 6) v_b_195_3) (<= v_b_189_3 .cse21) (<= .cse22 v_b_189_3) (<= .cse23 v_b_192_3) (<= (+ v_b_191_3 2) v_b_195_3) (<= v_b_185_3 v_b_186_3) (or (<= v_b_186_3 v_idx_422) (< v_idx_422 v_b_185_3) (= (select |c_#memory_int| v_idx_422) v_v_1749_3)) (<= .cse21 v_b_189_3) (or (< v_idx_432 v_b_195_3) (= (select |c_#memory_int| v_idx_432) v_v_1759_3)) (<= v_b_191_3 v_b_192_3) (<= .cse24 v_b_187_3) (<= .cse25 v_b_193_3) (<= v_b_193_3 .cse17) (<= .cse25 v_b_194_3) (or (= (select |c_#memory_int| v_idx_430) v_v_1757_3) (< v_idx_430 v_b_193_3) (<= v_b_194_3 v_idx_430)) (<= .cse5 v_b_188_3) (<= .cse21 v_b_190_3) (<= .cse13 v_b_190_3) (<= .cse18 v_b_186_3) (<= .cse17 v_b_194_3) (<= .cse26 v_b_193_3) (or (< v_idx_423 v_b_186_3) (= (select |c_#memory_int| v_idx_423) 0) (<= v_b_187_3 v_idx_423)) (<= .cse8 v_b_191_3) (or (< v_idx_421 v_b_184_3) (<= v_b_185_3 v_idx_421) (= (select |c_#memory_int| v_idx_421) 0)) (<= .cse24 v_b_188_3) (<= .cse27 v_b_186_3) (<= .cse28 v_b_191_3) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_3) (<= v_b_187_3 .cse16) (<= .cse20 v_b_191_3) (<= .cse23 v_b_191_3) (<= .cse29 v_b_194_3) (<= v_b_185_3 .cse18) (or (< v_idx_427 v_b_190_3) (= (select |c_#memory_int| v_idx_427) v_v_1754_3) (<= v_b_191_3 v_idx_427)) (<= v_b_193_3 v_b_194_3) (<= (+ v_b_185_3 5) v_b_195_3) (<= (+ v_b_190_3 3) v_b_195_3) (<= .cse29 v_b_193_3) (<= .cse30 v_b_195_3) (<= .cse16 v_b_188_3) (<= .cse12 v_b_193_3) (<= .cse15 v_b_191_3) (<= .cse27 v_b_185_3) (<= .cse31 v_b_193_3) (<= .cse28 v_b_192_3) (<= .cse10 v_b_192_3) (<= v_b_195_3 .cse30) (<= .cse26 v_b_194_3) (<= .cse11 v_b_189_3) (<= v_b_191_3 .cse10) (<= .cse9 v_b_194_3) (<= .cse19 v_b_190_3) (<= .cse22 v_b_190_3) (or (= (select |c_#memory_int| v_idx_424) v_v_1751_3) (<= v_b_188_3 v_idx_424) (< v_idx_424 v_b_187_3)) (<= .cse31 v_b_194_3) (<= (+ v_b_187_3 4) v_b_195_3))))) is different from false [2019-01-08 14:38:25,681 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:38:25,681 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:38:25,682 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:38:25,682 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:38:25,682 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:38:25,682 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:38:25,682 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:38:25,682 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-08 14:38:25,683 INFO L87 Difference]: Start difference. First operand 18 states and 38 transitions. Second operand 4 states. [2019-01-08 14:38:28,690 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_409 Int) (v_idx_407 Int) (v_idx_408 Int) (v_idx_412 Int) (v_idx_413 Int) (v_idx_410 Int) (v_idx_411 Int) (v_idx_405 Int) (v_idx_416 Int) (v_idx_406 Int) (v_idx_417 Int) (v_idx_403 Int) (v_idx_414 Int) (v_idx_404 Int) (v_idx_415 Int)) (exists ((v_b_189_3 Int) (v_v_1749_3 Int) (v_v_1759_3 Int) (v_b_193_3 Int) (v_v_1751_3 Int) (v_b_192_3 Int) (v_b_195_3 Int) (v_v_1754_3 Int) (v_b_184_3 Int) (v_b_194_3 Int) (v_v_1753_3 Int) (v_b_185_3 Int) (v_b_186_3 Int) (v_v_1755_3 Int) (v_v_1745_3 Int) (v_b_187_3 Int) (v_v_1747_3 Int) (v_b_188_3 Int) (v_v_1757_3 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p1 6)) (.cse6 (+ v_b_185_3 1)) (.cse4 (+ v_b_186_3 2)) (.cse0 (+ c_ULTIMATE.start_main_p5 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 3)) (.cse2 (+ v_b_188_3 1)) (.cse15 (+ c_ULTIMATE.start_main_p1 4)) (.cse12 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_185_3 4)) (.cse3 (+ v_b_184_3 2)) (.cse19 (+ v_b_184_3 5)) (.cse18 (+ v_b_186_3 4)) (.cse14 (+ c_ULTIMATE.start_main_p1 2)) (.cse22 (+ v_b_189_3 2)) (.cse20 (+ v_b_194_3 1)) (.cse16 (+ v_b_187_3 1)) (.cse23 (+ v_b_184_3 3)) (.cse17 (+ v_b_186_3 1)) (.cse9 (+ v_b_192_3 1)) (.cse13 (+ v_b_188_3 3)) (.cse10 (+ c_ULTIMATE.start_main_p5 2)) (.cse11 (+ v_b_184_3 1)) (.cse5 (+ v_b_185_3 2)) (.cse21 (+ v_b_187_3 3))) (and (<= (+ v_b_185_3 3) v_b_192_3) (<= .cse0 v_b_192_3) (<= (+ v_b_184_3 6) v_b_195_3) (or (= (select |c_#memory_int| v_idx_408) 0) (< v_idx_408 v_b_186_3) (<= v_b_187_3 v_idx_408)) (<= .cse1 v_b_193_3) (<= v_b_189_3 .cse2) (or (<= v_b_195_3 v_idx_416) (= (select |c_#memory_int| v_idx_416) 0) (< v_idx_416 v_b_194_3)) (<= .cse3 v_b_187_3) (<= .cse4 v_b_189_3) (<= (+ v_b_189_3 1) v_b_192_3) (<= .cse5 c_ULTIMATE.start_main_p5) (<= (+ v_b_184_3 4) v_b_192_3) (<= v_b_185_3 v_b_186_3) (or (<= .cse0 v_idx_412) (< v_idx_412 c_ULTIMATE.start_main_p5) (= (select |c_#memory_int| v_idx_412) v_v_1754_3)) (<= .cse6 v_b_187_3) (<= .cse2 v_b_189_3) (<= .cse7 v_b_187_3) (<= .cse8 v_b_193_3) (<= v_b_193_3 .cse9) (<= .cse8 v_b_194_3) (<= .cse6 v_b_188_3) (or (= (select |c_#memory_int| v_idx_409) v_v_1751_3) (<= v_b_188_3 v_idx_409) (< v_idx_409 v_b_187_3)) (<= .cse10 v_b_193_3) (<= .cse4 c_ULTIMATE.start_main_p5) (<= .cse11 v_b_186_3) (or (< v_idx_414 v_b_192_3) (= (select |c_#memory_int| v_idx_414) 0) (<= v_b_193_3 v_idx_414)) (<= .cse12 v_b_184_3) (<= (+ v_b_187_3 2) v_b_192_3) (<= v_b_187_3 v_b_188_3) (or (= (select |c_#memory_int| v_idx_410) 0) (<= v_b_189_3 v_idx_410) (< v_idx_410 v_b_188_3)) (<= .cse13 v_b_193_3) (or (= (select |c_#memory_int| v_idx_413) v_v_1755_3) (<= v_b_192_3 v_idx_413) (< v_idx_413 .cse0)) (<= .cse9 v_b_194_3) (<= (+ v_b_186_3 5) v_b_195_3) (<= .cse7 v_b_188_3) (<= .cse14 v_b_186_3) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_3) (<= .cse15 c_ULTIMATE.start_main_p5) (<= .cse16 c_ULTIMATE.start_main_p5) (<= v_b_187_3 .cse17) (<= .cse18 v_b_194_3) (or (< v_idx_415 v_b_193_3) (<= v_b_194_3 v_idx_415) (= (select |c_#memory_int| v_idx_415) v_v_1757_3)) (<= .cse19 v_b_194_3) (<= v_b_185_3 .cse11) (<= (+ v_b_188_3 4) v_b_195_3) (or (= (select |c_#memory_int| v_idx_417) v_v_1759_3) (< v_idx_417 v_b_195_3)) (or (< v_idx_404 c_ULTIMATE.start_main_p1) (<= .cse12 v_idx_404) (= (select |c_#memory_int| v_idx_404) 0)) (<= v_b_193_3 v_b_194_3) (<= v_b_189_3 c_ULTIMATE.start_main_p5) (<= .cse2 c_ULTIMATE.start_main_p5) (<= (+ v_b_185_3 5) v_b_195_3) (<= .cse15 v_b_189_3) (or (<= v_b_184_3 v_idx_405) (= (select |c_#memory_int| v_idx_405) v_v_1747_3) (< v_idx_405 .cse12)) (<= (+ v_b_193_3 1) v_b_195_3) (<= (+ v_b_192_3 2) v_b_195_3) (<= .cse1 v_b_194_3) (<= .cse3 v_b_188_3) (<= .cse19 v_b_193_3) (<= .cse20 v_b_195_3) (<= .cse17 v_b_188_3) (<= .cse18 v_b_193_3) (or (< v_idx_406 v_b_184_3) (= (select |c_#memory_int| v_idx_406) 0) (<= v_b_185_3 v_idx_406)) (or (= (select |c_#memory_int| v_idx_407) v_v_1749_3) (< v_idx_407 v_b_185_3) (<= v_b_186_3 v_idx_407)) (<= .cse14 v_b_185_3) (<= .cse21 v_b_193_3) (<= .cse22 v_b_193_3) (<= 0 v_v_1754_3) (<= (+ v_b_189_3 3) v_b_195_3) (<= (+ v_b_188_3 2) v_b_192_3) (<= .cse22 v_b_194_3) (<= 0 (* 2 v_v_1754_3)) (<= .cse23 c_ULTIMATE.start_main_p5) (<= (+ v_b_186_3 3) v_b_192_3) (<= v_b_195_3 .cse20) (<= .cse16 v_b_189_3) (<= .cse23 v_b_189_3) (<= .cse17 v_b_187_3) (or (< v_idx_411 v_b_189_3) (= (select |c_#memory_int| v_idx_411) v_v_1753_3) (<= c_ULTIMATE.start_main_p5 v_idx_411)) (<= .cse9 v_b_193_3) (<= .cse13 v_b_194_3) (<= .cse10 v_b_194_3) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_192_3) (<= .cse11 v_b_185_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_403) (= (select |c_#memory_int| v_idx_403) v_v_1745_3)) (<= .cse5 v_b_189_3) (<= (+ c_ULTIMATE.start_main_p5 3) v_b_195_3) (<= .cse21 v_b_194_3) (<= (+ v_b_187_3 4) v_b_195_3))))) (forall ((v_idx_429 Int) (v_idx_418 Int) (v_idx_419 Int) (v_idx_423 Int) (v_idx_424 Int) (v_idx_421 Int) (v_idx_432 Int) (v_idx_422 Int) (v_idx_427 Int) (v_idx_428 Int) (v_idx_425 Int) (v_idx_426 Int) (v_idx_430 Int) (v_idx_420 Int) (v_idx_431 Int)) (exists ((v_b_189_3 Int) (v_v_1749_3 Int) (v_v_1759_3 Int) (v_b_193_3 Int) (v_b_192_3 Int) (v_v_1751_3 Int) (v_b_195_3 Int) (v_v_1754_3 Int) (v_b_184_3 Int) (v_b_194_3 Int) (v_v_1753_3 Int) (v_b_185_3 Int) (v_v_1755_3 Int) (v_v_1745_3 Int) (v_b_186_3 Int) (v_b_187_3 Int) (v_v_1747_3 Int) (v_b_188_3 Int) (v_v_1757_3 Int) (v_b_191_3 Int) (v_b_190_3 Int)) (let ((.cse31 (+ c_ULTIMATE.start_main_p1 1)) (.cse24 (+ v_b_185_3 4)) (.cse25 (+ v_b_184_3 2)) (.cse27 (+ v_b_184_3 4)) (.cse38 (+ v_b_189_3 2)) (.cse30 (+ v_b_191_3 1)) (.cse26 (+ v_b_184_3 3)) (.cse28 (+ c_ULTIMATE.start_main_p1 5)) (.cse49 (+ c_ULTIMATE.start_main_p1 6)) (.cse29 (+ v_b_185_3 1)) (.cse45 (+ v_b_188_3 1)) (.cse37 (+ c_ULTIMATE.start_main_p1 4)) (.cse41 (+ v_b_192_3 1)) (.cse32 (+ v_b_187_3 2)) (.cse48 (+ c_ULTIMATE.start_main_p1 3)) (.cse44 (+ v_b_185_3 3)) (.cse47 (+ v_b_189_3 1)) (.cse42 (+ v_b_184_3 1)) (.cse53 (+ v_b_184_3 5)) (.cse40 (+ v_b_186_3 1)) (.cse36 (+ v_b_186_3 4)) (.cse39 (+ v_b_188_3 2)) (.cse51 (+ c_ULTIMATE.start_main_p1 2)) (.cse52 (+ v_b_186_3 3)) (.cse54 (+ v_b_194_3 1)) (.cse50 (+ v_b_190_3 2)) (.cse35 (+ v_b_187_3 1)) (.cse34 (+ v_b_190_3 1)) (.cse33 (+ v_b_188_3 3)) (.cse43 (+ v_b_185_3 2)) (.cse46 (+ v_b_186_3 2)) (.cse55 (+ v_b_187_3 3))) (and (or (= (select |c_#memory_int| v_idx_418) v_v_1745_3) (<= c_ULTIMATE.start_main_p1 v_idx_418)) (<= .cse24 v_b_193_3) (<= .cse25 v_b_187_3) (<= .cse26 v_b_190_3) (<= .cse27 v_b_192_3) (<= .cse28 v_b_191_3) (<= .cse29 v_b_187_3) (or (<= v_b_195_3 v_idx_431) (< v_idx_431 v_b_194_3) (= (select |c_#memory_int| v_idx_431) 0)) (or (< v_idx_429 v_b_192_3) (= (select |c_#memory_int| v_idx_429) 0) (<= v_b_193_3 v_idx_429)) (<= .cse30 v_b_193_3) (<= .cse31 v_b_184_3) (<= .cse32 v_b_192_3) (<= v_b_187_3 v_b_188_3) (<= .cse33 v_b_193_3) (<= (+ v_b_186_3 5) v_b_195_3) (or (< v_idx_419 c_ULTIMATE.start_main_p1) (<= .cse31 v_idx_419) (= (select |c_#memory_int| v_idx_419) 0)) (<= .cse34 v_b_191_3) (<= .cse35 v_b_190_3) (or (= (select |c_#memory_int| v_idx_428) v_v_1755_3) (< v_idx_428 v_b_191_3) (<= v_b_192_3 v_idx_428)) (<= .cse36 v_b_194_3) (or (<= v_b_189_3 v_idx_425) (< v_idx_425 v_b_188_3) (= (select |c_#memory_int| v_idx_425) 0)) (<= (+ v_b_188_3 4) v_b_195_3) (<= .cse37 v_b_189_3) (or (<= v_b_184_3 v_idx_420) (= (select |c_#memory_int| v_idx_420) v_v_1747_3) (< v_idx_420 .cse31)) (<= (+ v_b_193_3 1) v_b_195_3) (<= (+ v_b_192_3 2) v_b_195_3) (<= .cse24 v_b_194_3) (<= .cse25 v_b_188_3) (<= .cse27 v_b_191_3) (<= .cse38 v_b_193_3) (<= 0 v_v_1754_3) (<= (+ v_b_189_3 3) v_b_195_3) (<= .cse39 v_b_192_3) (<= .cse38 v_b_194_3) (<= 0 (* 2 v_v_1754_3)) (<= v_b_189_3 v_b_190_3) (<= .cse30 v_b_194_3) (<= .cse26 v_b_189_3) (<= .cse40 v_b_187_3) (<= .cse41 v_b_193_3) (<= .cse28 v_b_192_3) (<= .cse42 v_b_185_3) (<= .cse43 v_b_189_3) (or (< v_idx_426 v_b_189_3) (= (select |c_#memory_int| v_idx_426) v_v_1753_3) (<= v_b_190_3 v_idx_426)) (<= .cse44 v_b_192_3) (<= (+ v_b_184_3 6) v_b_195_3) (<= v_b_189_3 .cse45) (<= .cse46 v_b_189_3) (<= .cse47 v_b_192_3) (<= (+ v_b_191_3 2) v_b_195_3) (<= v_b_185_3 v_b_186_3) (or (<= v_b_186_3 v_idx_422) (< v_idx_422 v_b_185_3) (= (select |c_#memory_int| v_idx_422) v_v_1749_3)) (<= .cse45 v_b_189_3) (or (< v_idx_432 v_b_195_3) (= (select |c_#memory_int| v_idx_432) v_v_1759_3)) (<= v_b_191_3 v_b_192_3) (<= .cse48 v_b_187_3) (<= .cse49 v_b_193_3) (<= v_b_193_3 .cse41) (<= .cse49 v_b_194_3) (or (= (select |c_#memory_int| v_idx_430) v_v_1757_3) (< v_idx_430 v_b_193_3) (<= v_b_194_3 v_idx_430)) (<= .cse29 v_b_188_3) (<= .cse45 v_b_190_3) (<= .cse37 v_b_190_3) (<= .cse42 v_b_186_3) (<= .cse41 v_b_194_3) (<= .cse50 v_b_193_3) (or (< v_idx_423 v_b_186_3) (= (select |c_#memory_int| v_idx_423) 0) (<= v_b_187_3 v_idx_423)) (<= .cse32 v_b_191_3) (or (< v_idx_421 v_b_184_3) (<= v_b_185_3 v_idx_421) (= (select |c_#memory_int| v_idx_421) 0)) (<= .cse48 v_b_188_3) (<= .cse51 v_b_186_3) (<= .cse52 v_b_191_3) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_3) (<= v_b_187_3 .cse40) (<= .cse44 v_b_191_3) (<= .cse47 v_b_191_3) (<= .cse53 v_b_194_3) (<= v_b_185_3 .cse42) (or (< v_idx_427 v_b_190_3) (= (select |c_#memory_int| v_idx_427) v_v_1754_3) (<= v_b_191_3 v_idx_427)) (<= v_b_193_3 v_b_194_3) (<= (+ v_b_185_3 5) v_b_195_3) (<= (+ v_b_190_3 3) v_b_195_3) (<= .cse53 v_b_193_3) (<= .cse54 v_b_195_3) (<= .cse40 v_b_188_3) (<= .cse36 v_b_193_3) (<= .cse39 v_b_191_3) (<= .cse51 v_b_185_3) (<= .cse55 v_b_193_3) (<= .cse52 v_b_192_3) (<= .cse34 v_b_192_3) (<= v_b_195_3 .cse54) (<= .cse50 v_b_194_3) (<= .cse35 v_b_189_3) (<= v_b_191_3 .cse34) (<= .cse33 v_b_194_3) (<= .cse43 v_b_190_3) (<= .cse46 v_b_190_3) (or (= (select |c_#memory_int| v_idx_424) v_v_1751_3) (<= v_b_188_3 v_idx_424) (< v_idx_424 v_b_187_3)) (<= .cse55 v_b_194_3) (<= (+ v_b_187_3 4) v_b_195_3)))))) is different from false [2019-01-08 14:38:56,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-08 14:38:56,239 INFO L93 Difference]: Finished difference Result 20 states and 47 transitions. [2019-01-08 14:38:56,239 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-08 14:38:56,239 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-08 14:38:56,239 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-08 14:38:56,240 INFO L225 Difference]: With dead ends: 20 [2019-01-08 14:38:56,240 INFO L226 Difference]: Without dead ends: 19 [2019-01-08 14:38:56,240 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 8.0s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-08 14:38:56,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2019-01-08 14:38:56,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 18. [2019-01-08 14:38:56,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2019-01-08 14:38:56,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 38 transitions. [2019-01-08 14:38:56,252 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 38 transitions. Word has length 3 [2019-01-08 14:38:56,252 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-08 14:38:56,252 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 38 transitions. [2019-01-08 14:38:56,253 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-08 14:38:56,253 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 38 transitions. [2019-01-08 14:38:56,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-08 14:38:56,253 INFO L394 BasicCegarLoop]: Found error trace [2019-01-08 14:38:56,253 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-08 14:38:56,254 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT]=== [2019-01-08 14:38:56,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:38:56,254 INFO L82 PathProgramCache]: Analyzing trace with hash 30132, now seen corresponding path program 1 times [2019-01-08 14:38:56,254 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-08 14:38:56,255 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:56,255 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-08 14:38:56,255 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-08 14:38:56,255 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-08 14:38:56,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-08 14:38:56,411 WARN L181 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 20 DAG size of output: 13 [2019-01-08 14:38:56,488 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-08 14:38:56,489 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-08 14:38:56,489 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-08 14:38:56,489 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-08 14:38:56,489 INFO L207 CegarAbsIntRunner]: [0], [10], [31] [2019-01-08 14:38:56,490 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-08 14:38:56,491 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-08 14:39:09,175 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-08 14:39:09,176 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-08 14:39:09,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-08 14:39:09,176 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-08 14:39:09,823 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 77.27% of their original sizes. [2019-01-08 14:39:09,823 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-08 14:39:12,678 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_555 Int) (v_idx_556 Int) (v_idx_553 Int) (v_idx_554 Int) (v_idx_548 Int) (v_idx_559 Int) (v_idx_549 Int) (v_idx_557 Int) (v_idx_547 Int) (v_idx_558 Int) (v_idx_551 Int) (v_idx_552 Int) (v_idx_560 Int) (v_idx_561 Int) (v_idx_550 Int)) (exists ((v_v_1725_4 Int) (v_b_169_4 Int) (v_b_177_4 Int) (v_v_1736_4 Int) (v_v_1726_4 Int) (v_b_168_4 Int) (v_v_1728_4 Int) (v_b_170_4 Int) (v_b_171_4 Int) (v_v_1730_4 Int) (v_b_172_4 Int) (v_b_173_4 Int) (v_v_1732_4 Int) (v_b_174_4 Int) (v_v_1722_4 Int) (v_b_175_4 Int) (v_v_1734_4 Int) (v_b_176_4 Int) (v_v_1724_4 Int)) (let ((.cse2 (+ v_b_169_4 2)) (.cse6 (+ v_b_170_4 3)) (.cse8 (+ v_b_171_4 1)) (.cse13 (+ c_ULTIMATE.start_main_p2 5)) (.cse11 (+ v_b_170_4 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 6)) (.cse0 (+ c_ULTIMATE.start_main_p1 3)) (.cse20 (+ c_ULTIMATE.start_main_p1 5)) (.cse22 (+ c_ULTIMATE.start_main_p2 2)) (.cse1 (+ v_b_176_4 1)) (.cse23 (+ c_ULTIMATE.start_main_p2 4)) (.cse21 (+ v_b_169_4 1)) (.cse15 (+ v_b_173_4 1)) (.cse3 (+ v_b_168_4 1)) (.cse9 (+ v_b_174_4 1)) (.cse26 (+ v_b_172_4 2)) (.cse17 (+ v_b_172_4 1)) (.cse10 (+ v_b_168_4 2)) (.cse16 (+ v_b_169_4 3)) (.cse12 (+ c_ULTIMATE.start_main_p2 3)) (.cse7 (+ c_ULTIMATE.start_main_p2 1)) (.cse24 (+ v_b_170_4 2)) (.cse19 (+ v_b_168_4 4)) (.cse25 (+ c_ULTIMATE.start_main_p1 4)) (.cse4 (+ v_b_171_4 2)) (.cse14 (+ v_b_168_4 3)) (.cse5 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (* 2 v_v_1725_4) 0) (<= .cse0 v_b_169_4) (<= .cse1 v_b_177_4) (<= .cse2 v_b_174_4) (<= (+ v_b_174_4 2) v_b_177_4) (<= v_b_169_4 .cse3) (<= .cse4 v_b_175_4) (or (<= v_b_173_4 v_idx_556) (< v_idx_556 v_b_172_4) (= (select |c_#memory_int| v_idx_556) 0)) (<= .cse2 v_b_173_4) (or (< v_idx_560 v_b_176_4) (<= v_b_177_4 v_idx_560) (= (select |c_#memory_int| v_idx_560) 0)) (<= (+ v_b_168_4 5) v_b_177_4) (or (= (select |c_#memory_int| v_idx_548) 0) (<= .cse5 v_idx_548) (< v_idx_548 c_ULTIMATE.start_main_p1)) (<= .cse6 v_b_175_4) (<= v_b_171_4 v_b_172_4) (or (<= v_b_169_4 v_idx_552) (< v_idx_552 v_b_168_4) (= (select |c_#memory_int| v_idx_552) 0)) (<= v_b_169_4 v_b_170_4) (<= .cse7 v_b_168_4) (<= v_b_173_4 v_b_174_4) (<= .cse3 v_b_170_4) (<= .cse8 v_b_174_4) (<= .cse9 v_b_175_4) (<= (+ v_b_172_4 3) v_b_177_4) (<= .cse10 v_b_172_4) (<= v_v_1725_4 0) (<= v_b_171_4 .cse11) (<= .cse6 v_b_176_4) (<= .cse12 v_b_172_4) (<= .cse13 v_b_175_4) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_177_4) (or (< v_idx_554 v_b_170_4) (<= v_b_171_4 v_idx_554) (= (select |c_#memory_int| v_idx_554) 0)) (<= .cse14 v_b_173_4) (or (= (select |c_#memory_int| v_idx_551) v_v_1726_4) (< v_idx_551 .cse7) (<= v_b_168_4 v_idx_551)) (<= .cse15 v_b_176_4) (or (< v_idx_558 v_b_174_4) (<= v_b_175_4 v_idx_558) (= (select |c_#memory_int| v_idx_558) 0)) (<= .cse8 v_b_173_4) (<= .cse16 v_b_176_4) (<= .cse9 v_b_176_4) (or (< v_idx_561 v_b_177_4) (= (select |c_#memory_int| v_idx_561) v_v_1736_4)) (<= (+ v_b_169_4 4) v_b_177_4) (<= .cse13 v_b_176_4) (<= .cse17 v_b_174_4) (<= .cse18 v_b_175_4) (<= .cse11 v_b_171_4) (<= .cse19 v_b_176_4) (<= .cse20 v_b_173_4) (<= .cse11 v_b_172_4) (<= .cse21 v_b_171_4) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_168_4) (<= (+ v_b_173_4 2) v_b_177_4) (<= .cse18 v_b_176_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_547) (= (select |c_#memory_int| v_idx_547) v_v_1722_4)) (<= v_b_175_4 v_b_176_4) (or (< v_idx_559 v_b_175_4) (= (select |c_#memory_int| v_idx_559) v_v_1734_4) (<= v_b_176_4 v_idx_559)) (<= .cse22 v_b_170_4) (<= .cse0 v_b_170_4) (<= .cse20 v_b_174_4) (<= .cse23 v_b_174_4) (<= .cse22 v_b_169_4) (<= .cse24 v_b_174_4) (<= v_b_177_4 .cse1) (<= .cse23 v_b_173_4) (<= .cse25 v_b_172_4) (<= .cse21 v_b_172_4) (<= .cse26 v_b_175_4) (or (< v_idx_553 v_b_169_4) (<= v_b_170_4 v_idx_553) (= (select |c_#memory_int| v_idx_553) v_v_1728_4)) (<= (+ v_b_170_4 4) v_b_177_4) (<= v_b_173_4 .cse17) (<= .cse15 v_b_175_4) (<= (+ v_b_175_4 1) v_b_177_4) (<= .cse3 v_b_169_4) (or (< v_idx_555 v_b_171_4) (<= v_b_172_4 v_idx_555) (= (select |c_#memory_int| v_idx_555) v_v_1730_4)) (<= v_b_175_4 .cse9) (<= .cse26 v_b_176_4) (<= .cse17 v_b_173_4) (<= .cse10 v_b_171_4) (<= .cse16 v_b_175_4) (<= .cse12 v_b_171_4) (or (< v_idx_550 c_ULTIMATE.start_main_p2) (<= .cse7 v_idx_550) (= (select |c_#memory_int| v_idx_550) v_v_1725_4)) (<= .cse24 v_b_173_4) (or (< v_idx_557 v_b_173_4) (= (select |c_#memory_int| v_idx_557) v_v_1732_4) (<= v_b_174_4 v_idx_557)) (<= .cse19 v_b_175_4) (<= (+ v_b_171_4 3) v_b_177_4) (<= .cse25 v_b_171_4) (<= (+ c_ULTIMATE.start_main_p2 6) v_b_177_4) (<= .cse4 v_b_176_4) (<= .cse14 v_b_174_4) (<= .cse5 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_549) v_v_1724_4) (< v_idx_549 .cse5) (<= c_ULTIMATE.start_main_p2 v_idx_549)))))) is different from false [2019-01-08 14:39:15,116 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_566 Int) (v_idx_567 Int) (v_idx_564 Int) (v_idx_575 Int) (v_idx_565 Int) (v_idx_576 Int) (v_idx_568 Int) (v_idx_569 Int) (v_idx_570 Int) (v_idx_562 Int) (v_idx_573 Int) (v_idx_563 Int) (v_idx_574 Int) (v_idx_571 Int) (v_idx_572 Int)) (exists ((v_v_1725_4 Int) (v_v_1736_4 Int) (v_b_177_4 Int) (v_b_169_4 Int) (v_b_168_4 Int) (v_v_1726_4 Int) (v_b_167_4 Int) (v_b_166_4 Int) (v_v_1728_4 Int) (v_b_170_4 Int) (v_b_171_4 Int) (v_v_1730_4 Int) (v_b_172_4 Int) (v_b_173_4 Int) (v_v_1732_4 Int) (v_b_174_4 Int) (v_v_1722_4 Int) (v_b_175_4 Int) (v_v_1734_4 Int) (v_b_176_4 Int) (v_v_1724_4 Int)) (let ((.cse3 (+ v_b_166_4 2)) (.cse16 (+ c_ULTIMATE.start_main_p1 2)) (.cse15 (+ v_b_167_4 2)) (.cse21 (+ v_b_172_4 2)) (.cse5 (+ v_b_168_4 2)) (.cse18 (+ v_b_170_4 2)) (.cse13 (+ v_b_168_4 4)) (.cse1 (+ v_b_171_4 2)) (.cse19 (+ v_b_176_4 1)) (.cse22 (+ v_b_166_4 5)) (.cse26 (+ v_b_169_4 2)) (.cse0 (+ v_b_168_4 1)) (.cse8 (+ v_b_171_4 1)) (.cse2 (+ v_b_170_4 3)) (.cse4 (+ v_b_166_4 3)) (.cse11 (+ c_ULTIMATE.start_main_p1 1)) (.cse17 (+ c_ULTIMATE.start_main_p1 6)) (.cse12 (+ v_b_166_4 1)) (.cse24 (+ v_b_167_4 1)) (.cse28 (+ v_b_170_4 1)) (.cse20 (+ v_b_169_4 1)) (.cse25 (+ c_ULTIMATE.start_main_p1 3)) (.cse14 (+ c_ULTIMATE.start_main_p1 5)) (.cse23 (+ c_ULTIMATE.start_main_p1 4)) (.cse30 (+ v_b_167_4 3)) (.cse7 (+ v_b_173_4 1)) (.cse6 (+ v_b_166_4 4)) (.cse27 (+ v_b_174_4 1)) (.cse10 (+ v_b_172_4 1)) (.cse9 (+ v_b_169_4 3)) (.cse31 (+ v_b_167_4 4)) (.cse29 (+ v_b_168_4 3))) (and (or (< v_idx_576 v_b_177_4) (= (select |c_#memory_int| v_idx_576) v_v_1736_4)) (<= v_b_169_4 .cse0) (or (= (select |c_#memory_int| v_idx_565) v_v_1725_4) (< v_idx_565 v_b_166_4) (<= v_b_167_4 v_idx_565)) (<= .cse1 v_b_175_4) (<= (+ v_b_168_4 5) v_b_177_4) (<= .cse2 v_b_175_4) (<= .cse3 v_b_169_4) (<= v_b_169_4 v_b_170_4) (<= v_b_173_4 v_b_174_4) (<= .cse4 v_b_171_4) (<= (+ v_b_172_4 3) v_b_177_4) (<= .cse5 v_b_172_4) (or (< v_idx_567 v_b_168_4) (<= v_b_169_4 v_idx_567) (= (select |c_#memory_int| v_idx_567) 0)) (<= .cse6 v_b_173_4) (<= .cse7 v_b_176_4) (<= .cse8 v_b_173_4) (<= .cse9 v_b_176_4) (<= (+ v_b_169_4 4) v_b_177_4) (<= .cse10 v_b_174_4) (<= .cse3 v_b_170_4) (<= .cse11 v_b_166_4) (<= .cse12 v_b_167_4) (<= .cse13 v_b_176_4) (or (< v_idx_573 v_b_174_4) (= (select |c_#memory_int| v_idx_573) 0) (<= v_b_175_4 v_idx_573)) (<= .cse14 v_b_173_4) (<= .cse15 v_b_171_4) (<= .cse16 v_b_168_4) (<= (+ v_b_167_4 5) v_b_177_4) (or (< v_idx_571 v_b_172_4) (= (select |c_#memory_int| v_idx_571) 0) (<= v_b_173_4 v_idx_571)) (<= (+ v_b_173_4 2) v_b_177_4) (<= .cse17 v_b_176_4) (or (< v_idx_569 v_b_170_4) (<= v_b_171_4 v_idx_569) (= (select |c_#memory_int| v_idx_569) 0)) (<= .cse16 v_b_167_4) (<= .cse15 v_b_172_4) (<= .cse18 v_b_174_4) (<= v_b_177_4 .cse19) (<= .cse20 v_b_172_4) (<= .cse21 v_b_175_4) (<= (+ v_b_175_4 1) v_b_177_4) (or (< v_idx_575 v_b_176_4) (<= v_b_177_4 v_idx_575) (= (select |c_#memory_int| v_idx_575) 0)) (<= .cse0 v_b_169_4) (or (<= v_b_172_4 v_idx_570) (< v_idx_570 v_b_171_4) (= (select |c_#memory_int| v_idx_570) v_v_1730_4)) (<= v_b_167_4 v_b_168_4) (<= .cse21 v_b_176_4) (<= .cse5 v_b_171_4) (<= .cse18 v_b_173_4) (<= .cse22 v_b_175_4) (<= .cse13 v_b_175_4) (<= (+ v_b_171_4 3) v_b_177_4) (<= .cse23 v_b_171_4) (<= .cse24 v_b_170_4) (<= .cse1 v_b_176_4) (<= (* 2 v_v_1725_4) 0) (<= .cse12 v_b_168_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_562) (= (select |c_#memory_int| v_idx_562) v_v_1722_4)) (<= .cse25 v_b_169_4) (<= .cse19 v_b_177_4) (<= .cse26 v_b_174_4) (<= (+ v_b_166_4 6) v_b_177_4) (<= (+ v_b_174_4 2) v_b_177_4) (<= .cse22 v_b_176_4) (<= .cse26 v_b_173_4) (<= v_b_171_4 v_b_172_4) (or (< v_idx_563 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_563) 0) (<= .cse11 v_idx_563)) (<= .cse0 v_b_170_4) (<= .cse8 v_b_174_4) (<= .cse27 v_b_175_4) (<= v_v_1725_4 0) (<= v_b_171_4 .cse28) (<= .cse2 v_b_176_4) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_177_4) (<= .cse29 v_b_173_4) (<= .cse4 v_b_172_4) (or (= (select |c_#memory_int| v_idx_564) v_v_1724_4) (< v_idx_564 .cse11) (<= v_b_166_4 v_idx_564)) (or (< v_idx_566 v_b_167_4) (= (select |c_#memory_int| v_idx_566) v_v_1726_4) (<= v_b_168_4 v_idx_566)) (or (< v_idx_568 v_b_169_4) (= (select |c_#memory_int| v_idx_568) v_v_1728_4) (<= v_b_170_4 v_idx_568)) (<= .cse27 v_b_176_4) (or (= (select |c_#memory_int| v_idx_574) v_v_1734_4) (<= v_b_176_4 v_idx_574) (< v_idx_574 v_b_175_4)) (<= .cse17 v_b_175_4) (<= .cse28 v_b_171_4) (or (<= v_b_174_4 v_idx_572) (= (select |c_#memory_int| v_idx_572) v_v_1732_4) (< v_idx_572 v_b_173_4)) (<= .cse30 v_b_173_4) (<= v_b_167_4 .cse12) (<= .cse24 v_b_169_4) (<= .cse28 v_b_172_4) (<= .cse20 v_b_171_4) (<= v_b_175_4 v_b_176_4) (<= .cse25 v_b_170_4) (<= .cse14 v_b_174_4) (<= .cse23 v_b_172_4) (<= (+ v_b_170_4 4) v_b_177_4) (<= v_b_173_4 .cse10) (<= .cse30 v_b_174_4) (<= .cse7 v_b_175_4) (<= .cse6 v_b_174_4) (<= v_b_175_4 .cse27) (<= .cse10 v_b_173_4) (<= .cse9 v_b_175_4) (<= .cse31 v_b_175_4) (<= .cse31 v_b_176_4) (<= .cse29 v_b_174_4))))) is different from false [2019-01-08 14:39:17,132 WARN L860 $PredicateComparison]: unable to prove that (forall ((v_idx_566 Int) (v_idx_567 Int) (v_idx_564 Int) (v_idx_575 Int) (v_idx_565 Int) (v_idx_576 Int) (v_idx_568 Int) (v_idx_569 Int) (v_idx_570 Int) (v_idx_562 Int) (v_idx_573 Int) (v_idx_563 Int) (v_idx_574 Int) (v_idx_571 Int) (v_idx_572 Int)) (exists ((v_v_1725_4 Int) (v_v_1736_4 Int) (v_b_177_4 Int) (v_b_169_4 Int) (v_b_168_4 Int) (v_v_1726_4 Int) (v_b_167_4 Int) (v_b_166_4 Int) (v_v_1728_4 Int) (v_b_170_4 Int) (v_b_171_4 Int) (v_v_1730_4 Int) (v_b_172_4 Int) (v_b_173_4 Int) (v_v_1732_4 Int) (v_b_174_4 Int) (v_v_1722_4 Int) (v_b_175_4 Int) (v_v_1734_4 Int) (v_b_176_4 Int) (v_v_1724_4 Int)) (let ((.cse3 (+ v_b_166_4 2)) (.cse16 (+ c_ULTIMATE.start_main_p1 2)) (.cse15 (+ v_b_167_4 2)) (.cse21 (+ v_b_172_4 2)) (.cse5 (+ v_b_168_4 2)) (.cse18 (+ v_b_170_4 2)) (.cse13 (+ v_b_168_4 4)) (.cse1 (+ v_b_171_4 2)) (.cse19 (+ v_b_176_4 1)) (.cse22 (+ v_b_166_4 5)) (.cse26 (+ v_b_169_4 2)) (.cse0 (+ v_b_168_4 1)) (.cse8 (+ v_b_171_4 1)) (.cse2 (+ v_b_170_4 3)) (.cse4 (+ v_b_166_4 3)) (.cse11 (+ c_ULTIMATE.start_main_p1 1)) (.cse17 (+ c_ULTIMATE.start_main_p1 6)) (.cse12 (+ v_b_166_4 1)) (.cse24 (+ v_b_167_4 1)) (.cse28 (+ v_b_170_4 1)) (.cse20 (+ v_b_169_4 1)) (.cse25 (+ c_ULTIMATE.start_main_p1 3)) (.cse14 (+ c_ULTIMATE.start_main_p1 5)) (.cse23 (+ c_ULTIMATE.start_main_p1 4)) (.cse30 (+ v_b_167_4 3)) (.cse7 (+ v_b_173_4 1)) (.cse6 (+ v_b_166_4 4)) (.cse27 (+ v_b_174_4 1)) (.cse10 (+ v_b_172_4 1)) (.cse9 (+ v_b_169_4 3)) (.cse31 (+ v_b_167_4 4)) (.cse29 (+ v_b_168_4 3))) (and (or (< v_idx_576 v_b_177_4) (= (select |c_#memory_int| v_idx_576) v_v_1736_4)) (<= v_b_169_4 .cse0) (or (= (select |c_#memory_int| v_idx_565) v_v_1725_4) (< v_idx_565 v_b_166_4) (<= v_b_167_4 v_idx_565)) (<= .cse1 v_b_175_4) (<= (+ v_b_168_4 5) v_b_177_4) (<= .cse2 v_b_175_4) (<= .cse3 v_b_169_4) (<= v_b_169_4 v_b_170_4) (<= v_b_173_4 v_b_174_4) (<= .cse4 v_b_171_4) (<= (+ v_b_172_4 3) v_b_177_4) (<= .cse5 v_b_172_4) (or (< v_idx_567 v_b_168_4) (<= v_b_169_4 v_idx_567) (= (select |c_#memory_int| v_idx_567) 0)) (<= .cse6 v_b_173_4) (<= .cse7 v_b_176_4) (<= .cse8 v_b_173_4) (<= .cse9 v_b_176_4) (<= (+ v_b_169_4 4) v_b_177_4) (<= .cse10 v_b_174_4) (<= .cse3 v_b_170_4) (<= .cse11 v_b_166_4) (<= .cse12 v_b_167_4) (<= .cse13 v_b_176_4) (or (< v_idx_573 v_b_174_4) (= (select |c_#memory_int| v_idx_573) 0) (<= v_b_175_4 v_idx_573)) (<= .cse14 v_b_173_4) (<= .cse15 v_b_171_4) (<= .cse16 v_b_168_4) (<= (+ v_b_167_4 5) v_b_177_4) (or (< v_idx_571 v_b_172_4) (= (select |c_#memory_int| v_idx_571) 0) (<= v_b_173_4 v_idx_571)) (<= (+ v_b_173_4 2) v_b_177_4) (<= .cse17 v_b_176_4) (or (< v_idx_569 v_b_170_4) (<= v_b_171_4 v_idx_569) (= (select |c_#memory_int| v_idx_569) 0)) (<= .cse16 v_b_167_4) (<= .cse15 v_b_172_4) (<= .cse18 v_b_174_4) (<= v_b_177_4 .cse19) (<= .cse20 v_b_172_4) (<= .cse21 v_b_175_4) (<= (+ v_b_175_4 1) v_b_177_4) (or (< v_idx_575 v_b_176_4) (<= v_b_177_4 v_idx_575) (= (select |c_#memory_int| v_idx_575) 0)) (<= .cse0 v_b_169_4) (or (<= v_b_172_4 v_idx_570) (< v_idx_570 v_b_171_4) (= (select |c_#memory_int| v_idx_570) v_v_1730_4)) (<= v_b_167_4 v_b_168_4) (<= .cse21 v_b_176_4) (<= .cse5 v_b_171_4) (<= .cse18 v_b_173_4) (<= .cse22 v_b_175_4) (<= .cse13 v_b_175_4) (<= (+ v_b_171_4 3) v_b_177_4) (<= .cse23 v_b_171_4) (<= .cse24 v_b_170_4) (<= .cse1 v_b_176_4) (<= (* 2 v_v_1725_4) 0) (<= .cse12 v_b_168_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_562) (= (select |c_#memory_int| v_idx_562) v_v_1722_4)) (<= .cse25 v_b_169_4) (<= .cse19 v_b_177_4) (<= .cse26 v_b_174_4) (<= (+ v_b_166_4 6) v_b_177_4) (<= (+ v_b_174_4 2) v_b_177_4) (<= .cse22 v_b_176_4) (<= .cse26 v_b_173_4) (<= v_b_171_4 v_b_172_4) (or (< v_idx_563 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_563) 0) (<= .cse11 v_idx_563)) (<= .cse0 v_b_170_4) (<= .cse8 v_b_174_4) (<= .cse27 v_b_175_4) (<= v_v_1725_4 0) (<= v_b_171_4 .cse28) (<= .cse2 v_b_176_4) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_177_4) (<= .cse29 v_b_173_4) (<= .cse4 v_b_172_4) (or (= (select |c_#memory_int| v_idx_564) v_v_1724_4) (< v_idx_564 .cse11) (<= v_b_166_4 v_idx_564)) (or (< v_idx_566 v_b_167_4) (= (select |c_#memory_int| v_idx_566) v_v_1726_4) (<= v_b_168_4 v_idx_566)) (or (< v_idx_568 v_b_169_4) (= (select |c_#memory_int| v_idx_568) v_v_1728_4) (<= v_b_170_4 v_idx_568)) (<= .cse27 v_b_176_4) (or (= (select |c_#memory_int| v_idx_574) v_v_1734_4) (<= v_b_176_4 v_idx_574) (< v_idx_574 v_b_175_4)) (<= .cse17 v_b_175_4) (<= .cse28 v_b_171_4) (or (<= v_b_174_4 v_idx_572) (= (select |c_#memory_int| v_idx_572) v_v_1732_4) (< v_idx_572 v_b_173_4)) (<= .cse30 v_b_173_4) (<= v_b_167_4 .cse12) (<= .cse24 v_b_169_4) (<= .cse28 v_b_172_4) (<= .cse20 v_b_171_4) (<= v_b_175_4 v_b_176_4) (<= .cse25 v_b_170_4) (<= .cse14 v_b_174_4) (<= .cse23 v_b_172_4) (<= (+ v_b_170_4 4) v_b_177_4) (<= v_b_173_4 .cse10) (<= .cse30 v_b_174_4) (<= .cse7 v_b_175_4) (<= .cse6 v_b_174_4) (<= v_b_175_4 .cse27) (<= .cse10 v_b_173_4) (<= .cse9 v_b_175_4) (<= .cse31 v_b_175_4) (<= .cse31 v_b_176_4) (<= .cse29 v_b_174_4))))) is different from true [2019-01-08 14:39:17,133 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-08 14:39:17,133 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-08 14:39:17,133 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-08 14:39:17,134 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-08 14:39:17,134 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-08 14:39:17,134 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-08 14:39:17,134 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-08 14:39:17,134 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=2, Unknown=3, NotChecked=2, Total=12 [2019-01-08 14:39:17,135 INFO L87 Difference]: Start difference. First operand 18 states and 38 transitions. Second operand 4 states. [2019-01-08 14:39:20,252 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_555 Int) (v_idx_556 Int) (v_idx_553 Int) (v_idx_554 Int) (v_idx_548 Int) (v_idx_559 Int) (v_idx_549 Int) (v_idx_557 Int) (v_idx_547 Int) (v_idx_558 Int) (v_idx_551 Int) (v_idx_552 Int) (v_idx_560 Int) (v_idx_561 Int) (v_idx_550 Int)) (exists ((v_v_1725_4 Int) (v_b_169_4 Int) (v_b_177_4 Int) (v_v_1736_4 Int) (v_v_1726_4 Int) (v_b_168_4 Int) (v_v_1728_4 Int) (v_b_170_4 Int) (v_b_171_4 Int) (v_v_1730_4 Int) (v_b_172_4 Int) (v_b_173_4 Int) (v_v_1732_4 Int) (v_b_174_4 Int) (v_v_1722_4 Int) (v_b_175_4 Int) (v_v_1734_4 Int) (v_b_176_4 Int) (v_v_1724_4 Int)) (let ((.cse2 (+ v_b_169_4 2)) (.cse6 (+ v_b_170_4 3)) (.cse8 (+ v_b_171_4 1)) (.cse13 (+ c_ULTIMATE.start_main_p2 5)) (.cse11 (+ v_b_170_4 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 6)) (.cse0 (+ c_ULTIMATE.start_main_p1 3)) (.cse20 (+ c_ULTIMATE.start_main_p1 5)) (.cse22 (+ c_ULTIMATE.start_main_p2 2)) (.cse1 (+ v_b_176_4 1)) (.cse23 (+ c_ULTIMATE.start_main_p2 4)) (.cse21 (+ v_b_169_4 1)) (.cse15 (+ v_b_173_4 1)) (.cse3 (+ v_b_168_4 1)) (.cse9 (+ v_b_174_4 1)) (.cse26 (+ v_b_172_4 2)) (.cse17 (+ v_b_172_4 1)) (.cse10 (+ v_b_168_4 2)) (.cse16 (+ v_b_169_4 3)) (.cse12 (+ c_ULTIMATE.start_main_p2 3)) (.cse7 (+ c_ULTIMATE.start_main_p2 1)) (.cse24 (+ v_b_170_4 2)) (.cse19 (+ v_b_168_4 4)) (.cse25 (+ c_ULTIMATE.start_main_p1 4)) (.cse4 (+ v_b_171_4 2)) (.cse14 (+ v_b_168_4 3)) (.cse5 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (* 2 v_v_1725_4) 0) (<= .cse0 v_b_169_4) (<= .cse1 v_b_177_4) (<= .cse2 v_b_174_4) (<= (+ v_b_174_4 2) v_b_177_4) (<= v_b_169_4 .cse3) (<= .cse4 v_b_175_4) (or (<= v_b_173_4 v_idx_556) (< v_idx_556 v_b_172_4) (= (select |c_#memory_int| v_idx_556) 0)) (<= .cse2 v_b_173_4) (or (< v_idx_560 v_b_176_4) (<= v_b_177_4 v_idx_560) (= (select |c_#memory_int| v_idx_560) 0)) (<= (+ v_b_168_4 5) v_b_177_4) (or (= (select |c_#memory_int| v_idx_548) 0) (<= .cse5 v_idx_548) (< v_idx_548 c_ULTIMATE.start_main_p1)) (<= .cse6 v_b_175_4) (<= v_b_171_4 v_b_172_4) (or (<= v_b_169_4 v_idx_552) (< v_idx_552 v_b_168_4) (= (select |c_#memory_int| v_idx_552) 0)) (<= v_b_169_4 v_b_170_4) (<= .cse7 v_b_168_4) (<= v_b_173_4 v_b_174_4) (<= .cse3 v_b_170_4) (<= .cse8 v_b_174_4) (<= .cse9 v_b_175_4) (<= (+ v_b_172_4 3) v_b_177_4) (<= .cse10 v_b_172_4) (<= v_v_1725_4 0) (<= v_b_171_4 .cse11) (<= .cse6 v_b_176_4) (<= .cse12 v_b_172_4) (<= .cse13 v_b_175_4) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_177_4) (or (< v_idx_554 v_b_170_4) (<= v_b_171_4 v_idx_554) (= (select |c_#memory_int| v_idx_554) 0)) (<= .cse14 v_b_173_4) (or (= (select |c_#memory_int| v_idx_551) v_v_1726_4) (< v_idx_551 .cse7) (<= v_b_168_4 v_idx_551)) (<= .cse15 v_b_176_4) (or (< v_idx_558 v_b_174_4) (<= v_b_175_4 v_idx_558) (= (select |c_#memory_int| v_idx_558) 0)) (<= .cse8 v_b_173_4) (<= .cse16 v_b_176_4) (<= .cse9 v_b_176_4) (or (< v_idx_561 v_b_177_4) (= (select |c_#memory_int| v_idx_561) v_v_1736_4)) (<= (+ v_b_169_4 4) v_b_177_4) (<= .cse13 v_b_176_4) (<= .cse17 v_b_174_4) (<= .cse18 v_b_175_4) (<= .cse11 v_b_171_4) (<= .cse19 v_b_176_4) (<= .cse20 v_b_173_4) (<= .cse11 v_b_172_4) (<= .cse21 v_b_171_4) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_168_4) (<= (+ v_b_173_4 2) v_b_177_4) (<= .cse18 v_b_176_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_547) (= (select |c_#memory_int| v_idx_547) v_v_1722_4)) (<= v_b_175_4 v_b_176_4) (or (< v_idx_559 v_b_175_4) (= (select |c_#memory_int| v_idx_559) v_v_1734_4) (<= v_b_176_4 v_idx_559)) (<= .cse22 v_b_170_4) (<= .cse0 v_b_170_4) (<= .cse20 v_b_174_4) (<= .cse23 v_b_174_4) (<= .cse22 v_b_169_4) (<= .cse24 v_b_174_4) (<= v_b_177_4 .cse1) (<= .cse23 v_b_173_4) (<= .cse25 v_b_172_4) (<= .cse21 v_b_172_4) (<= .cse26 v_b_175_4) (or (< v_idx_553 v_b_169_4) (<= v_b_170_4 v_idx_553) (= (select |c_#memory_int| v_idx_553) v_v_1728_4)) (<= (+ v_b_170_4 4) v_b_177_4) (<= v_b_173_4 .cse17) (<= .cse15 v_b_175_4) (<= (+ v_b_175_4 1) v_b_177_4) (<= .cse3 v_b_169_4) (or (< v_idx_555 v_b_171_4) (<= v_b_172_4 v_idx_555) (= (select |c_#memory_int| v_idx_555) v_v_1730_4)) (<= v_b_175_4 .cse9) (<= .cse26 v_b_176_4) (<= .cse17 v_b_173_4) (<= .cse10 v_b_171_4) (<= .cse16 v_b_175_4) (<= .cse12 v_b_171_4) (or (< v_idx_550 c_ULTIMATE.start_main_p2) (<= .cse7 v_idx_550) (= (select |c_#memory_int| v_idx_550) v_v_1725_4)) (<= .cse24 v_b_173_4) (or (< v_idx_557 v_b_173_4) (= (select |c_#memory_int| v_idx_557) v_v_1732_4) (<= v_b_174_4 v_idx_557)) (<= .cse19 v_b_175_4) (<= (+ v_b_171_4 3) v_b_177_4) (<= .cse25 v_b_171_4) (<= (+ c_ULTIMATE.start_main_p2 6) v_b_177_4) (<= .cse4 v_b_176_4) (<= .cse14 v_b_174_4) (<= .cse5 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_549) v_v_1724_4) (< v_idx_549 .cse5) (<= c_ULTIMATE.start_main_p2 v_idx_549)))))) (forall ((v_idx_566 Int) (v_idx_567 Int) (v_idx_564 Int) (v_idx_575 Int) (v_idx_565 Int) (v_idx_576 Int) (v_idx_568 Int) (v_idx_569 Int) (v_idx_570 Int) (v_idx_562 Int) (v_idx_573 Int) (v_idx_563 Int) (v_idx_574 Int) (v_idx_571 Int) (v_idx_572 Int)) (exists ((v_v_1725_4 Int) (v_v_1736_4 Int) (v_b_177_4 Int) (v_b_169_4 Int) (v_b_168_4 Int) (v_v_1726_4 Int) (v_b_167_4 Int) (v_b_166_4 Int) (v_v_1728_4 Int) (v_b_170_4 Int) (v_b_171_4 Int) (v_v_1730_4 Int) (v_b_172_4 Int) (v_b_173_4 Int) (v_v_1732_4 Int) (v_b_174_4 Int) (v_v_1722_4 Int) (v_b_175_4 Int) (v_v_1734_4 Int) (v_b_176_4 Int) (v_v_1724_4 Int)) (let ((.cse30 (+ v_b_166_4 2)) (.cse43 (+ c_ULTIMATE.start_main_p1 2)) (.cse42 (+ v_b_167_4 2)) (.cse48 (+ v_b_172_4 2)) (.cse32 (+ v_b_168_4 2)) (.cse45 (+ v_b_170_4 2)) (.cse40 (+ v_b_168_4 4)) (.cse28 (+ v_b_171_4 2)) (.cse46 (+ v_b_176_4 1)) (.cse49 (+ v_b_166_4 5)) (.cse53 (+ v_b_169_4 2)) (.cse27 (+ v_b_168_4 1)) (.cse35 (+ v_b_171_4 1)) (.cse29 (+ v_b_170_4 3)) (.cse31 (+ v_b_166_4 3)) (.cse38 (+ c_ULTIMATE.start_main_p1 1)) (.cse44 (+ c_ULTIMATE.start_main_p1 6)) (.cse39 (+ v_b_166_4 1)) (.cse51 (+ v_b_167_4 1)) (.cse55 (+ v_b_170_4 1)) (.cse47 (+ v_b_169_4 1)) (.cse52 (+ c_ULTIMATE.start_main_p1 3)) (.cse41 (+ c_ULTIMATE.start_main_p1 5)) (.cse50 (+ c_ULTIMATE.start_main_p1 4)) (.cse57 (+ v_b_167_4 3)) (.cse34 (+ v_b_173_4 1)) (.cse33 (+ v_b_166_4 4)) (.cse54 (+ v_b_174_4 1)) (.cse37 (+ v_b_172_4 1)) (.cse36 (+ v_b_169_4 3)) (.cse58 (+ v_b_167_4 4)) (.cse56 (+ v_b_168_4 3))) (and (or (< v_idx_576 v_b_177_4) (= (select |c_#memory_int| v_idx_576) v_v_1736_4)) (<= v_b_169_4 .cse27) (or (= (select |c_#memory_int| v_idx_565) v_v_1725_4) (< v_idx_565 v_b_166_4) (<= v_b_167_4 v_idx_565)) (<= .cse28 v_b_175_4) (<= (+ v_b_168_4 5) v_b_177_4) (<= .cse29 v_b_175_4) (<= .cse30 v_b_169_4) (<= v_b_169_4 v_b_170_4) (<= v_b_173_4 v_b_174_4) (<= .cse31 v_b_171_4) (<= (+ v_b_172_4 3) v_b_177_4) (<= .cse32 v_b_172_4) (or (< v_idx_567 v_b_168_4) (<= v_b_169_4 v_idx_567) (= (select |c_#memory_int| v_idx_567) 0)) (<= .cse33 v_b_173_4) (<= .cse34 v_b_176_4) (<= .cse35 v_b_173_4) (<= .cse36 v_b_176_4) (<= (+ v_b_169_4 4) v_b_177_4) (<= .cse37 v_b_174_4) (<= .cse30 v_b_170_4) (<= .cse38 v_b_166_4) (<= .cse39 v_b_167_4) (<= .cse40 v_b_176_4) (or (< v_idx_573 v_b_174_4) (= (select |c_#memory_int| v_idx_573) 0) (<= v_b_175_4 v_idx_573)) (<= .cse41 v_b_173_4) (<= .cse42 v_b_171_4) (<= .cse43 v_b_168_4) (<= (+ v_b_167_4 5) v_b_177_4) (or (< v_idx_571 v_b_172_4) (= (select |c_#memory_int| v_idx_571) 0) (<= v_b_173_4 v_idx_571)) (<= (+ v_b_173_4 2) v_b_177_4) (<= .cse44 v_b_176_4) (or (< v_idx_569 v_b_170_4) (<= v_b_171_4 v_idx_569) (= (select |c_#memory_int| v_idx_569) 0)) (<= .cse43 v_b_167_4) (<= .cse42 v_b_172_4) (<= .cse45 v_b_174_4) (<= v_b_177_4 .cse46) (<= .cse47 v_b_172_4) (<= .cse48 v_b_175_4) (<= (+ v_b_175_4 1) v_b_177_4) (or (< v_idx_575 v_b_176_4) (<= v_b_177_4 v_idx_575) (= (select |c_#memory_int| v_idx_575) 0)) (<= .cse27 v_b_169_4) (or (<= v_b_172_4 v_idx_570) (< v_idx_570 v_b_171_4) (= (select |c_#memory_int| v_idx_570) v_v_1730_4)) (<= v_b_167_4 v_b_168_4) (<= .cse48 v_b_176_4) (<= .cse32 v_b_171_4) (<= .cse45 v_b_173_4) (<= .cse49 v_b_175_4) (<= .cse40 v_b_175_4) (<= (+ v_b_171_4 3) v_b_177_4) (<= .cse50 v_b_171_4) (<= .cse51 v_b_170_4) (<= .cse28 v_b_176_4) (<= (* 2 v_v_1725_4) 0) (<= .cse39 v_b_168_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_562) (= (select |c_#memory_int| v_idx_562) v_v_1722_4)) (<= .cse52 v_b_169_4) (<= .cse46 v_b_177_4) (<= .cse53 v_b_174_4) (<= (+ v_b_166_4 6) v_b_177_4) (<= (+ v_b_174_4 2) v_b_177_4) (<= .cse49 v_b_176_4) (<= .cse53 v_b_173_4) (<= v_b_171_4 v_b_172_4) (or (< v_idx_563 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_563) 0) (<= .cse38 v_idx_563)) (<= .cse27 v_b_170_4) (<= .cse35 v_b_174_4) (<= .cse54 v_b_175_4) (<= v_v_1725_4 0) (<= v_b_171_4 .cse55) (<= .cse29 v_b_176_4) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_177_4) (<= .cse56 v_b_173_4) (<= .cse31 v_b_172_4) (or (= (select |c_#memory_int| v_idx_564) v_v_1724_4) (< v_idx_564 .cse38) (<= v_b_166_4 v_idx_564)) (or (< v_idx_566 v_b_167_4) (= (select |c_#memory_int| v_idx_566) v_v_1726_4) (<= v_b_168_4 v_idx_566)) (or (< v_idx_568 v_b_169_4) (= (select |c_#memory_int| v_idx_568) v_v_1728_4) (<= v_b_170_4 v_idx_568)) (<= .cse54 v_b_176_4) (or (= (select |c_#memory_int| v_idx_574) v_v_1734_4) (<= v_b_176_4 v_idx_574) (< v_idx_574 v_b_175_4)) (<= .cse44 v_b_175_4) (<= .cse55 v_b_171_4) (or (<= v_b_174_4 v_idx_572) (= (select |c_#memory_int| v_idx_572) v_v_1732_4) (< v_idx_572 v_b_173_4)) (<= .cse57 v_b_173_4) (<= v_b_167_4 .cse39) (<= .cse51 v_b_169_4) (<= .cse55 v_b_172_4) (<= .cse47 v_b_171_4) (<= v_b_175_4 v_b_176_4) (<= .cse52 v_b_170_4) (<= .cse41 v_b_174_4) (<= .cse50 v_b_172_4) (<= (+ v_b_170_4 4) v_b_177_4) (<= v_b_173_4 .cse37) (<= .cse57 v_b_174_4) (<= .cse34 v_b_175_4) (<= .cse33 v_b_174_4) (<= v_b_175_4 .cse54) (<= .cse37 v_b_173_4) (<= .cse36 v_b_175_4) (<= .cse58 v_b_175_4) (<= .cse58 v_b_176_4) (<= .cse56 v_b_174_4)))))) is different from false