java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml -s ../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf -i ../../../trunk/examples/programs/heapseparator/speedup-poc-dd-3-limited.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.24-df3cc4e-m [2019-01-11 11:42:10,194 INFO L170 SettingsManager]: Resetting all preferences to default values... [2019-01-11 11:42:10,196 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2019-01-11 11:42:10,214 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2019-01-11 11:42:10,247 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf [2019-01-11 11:42:10,260 INFO L110 SettingsManager]: Loading preferences was successful [2019-01-11 11:42:10,260 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2019-01-11 11:42:10,261 INFO L131 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2019-01-11 11:42:10,261 INFO L133 SettingsManager]: * Show backtranslation warnings=false [2019-01-11 11:42:10,261 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-01-11 11:42:10,261 INFO L133 SettingsManager]: * User list type=DISABLED [2019-01-11 11:42:10,262 INFO L133 SettingsManager]: * Inline calls to unimplemented procedures=true [2019-01-11 11:42:10,264 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-01-11 11:42:10,264 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-01-11 11:42:10,264 INFO L133 SettingsManager]: * Underlying domain=OctagonDomain [2019-01-11 11:42:10,264 INFO L133 SettingsManager]: * Abstract domain=ArrayDomain [2019-01-11 11:42:10,264 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-01-11 11:42:10,264 INFO L133 SettingsManager]: * Interval Domain=false [2019-01-11 11:42:10,265 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-01-11 11:42:10,265 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2019-01-11 11:42:10,266 INFO L133 SettingsManager]: * Use SBE=true [2019-01-11 11:42:10,266 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-01-11 11:42:10,266 INFO L133 SettingsManager]: * sizeof long=4 [2019-01-11 11:42:10,266 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2019-01-11 11:42:10,266 INFO L133 SettingsManager]: * sizeof POINTER=4 [2019-01-11 11:42:10,267 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2019-01-11 11:42:10,267 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-01-11 11:42:10,267 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-01-11 11:42:10,267 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-01-11 11:42:10,267 INFO L133 SettingsManager]: * sizeof long double=12 [2019-01-11 11:42:10,267 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2019-01-11 11:42:10,268 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-01-11 11:42:10,269 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-01-11 11:42:10,269 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-01-11 11:42:10,270 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2019-01-11 11:42:10,270 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-11 11:42:10,270 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-01-11 11:42:10,270 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-01-11 11:42:10,270 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-01-11 11:42:10,270 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2019-01-11 11:42:10,271 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-01-11 11:42:10,271 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in [2019-01-11 11:42:10,271 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-01-11 11:42:10,271 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2019-01-11 11:42:10,306 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-01-11 11:42:10,318 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-01-11 11:42:10,322 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-01-11 11:42:10,323 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2019-01-11 11:42:10,324 INFO L276 PluginConnector]: Boogie PL CUP Parser initialized [2019-01-11 11:42:10,325 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-3-limited.bpl [2019-01-11 11:42:10,325 INFO L111 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-3-limited.bpl' [2019-01-11 11:42:10,362 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-01-11 11:42:10,363 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-01-11 11:42:10,364 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-01-11 11:42:10,364 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-01-11 11:42:10,364 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2019-01-11 11:42:10,381 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:10" (1/1) ... [2019-01-11 11:42:10,393 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:10" (1/1) ... [2019-01-11 11:42:10,417 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-01-11 11:42:10,418 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-01-11 11:42:10,418 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-01-11 11:42:10,418 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2019-01-11 11:42:10,430 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:10" (1/1) ... [2019-01-11 11:42:10,430 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:10" (1/1) ... [2019-01-11 11:42:10,431 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:10" (1/1) ... [2019-01-11 11:42:10,431 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:10" (1/1) ... [2019-01-11 11:42:10,434 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:10" (1/1) ... [2019-01-11 11:42:10,438 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:10" (1/1) ... [2019-01-11 11:42:10,439 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:10" (1/1) ... [2019-01-11 11:42:10,440 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-01-11 11:42:10,441 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-01-11 11:42:10,441 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-01-11 11:42:10,441 INFO L276 PluginConnector]: RCFGBuilder initialized [2019-01-11 11:42:10,442 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:10" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-11 11:42:10,508 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-01-11 11:42:10,508 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-01-11 11:42:10,837 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-01-11 11:42:10,837 INFO L286 CfgBuilder]: Removed 9 assue(true) statements. [2019-01-11 11:42:10,839 INFO L202 PluginConnector]: Adding new model speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.01 11:42:10 BoogieIcfgContainer [2019-01-11 11:42:10,839 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-01-11 11:42:10,840 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-01-11 11:42:10,840 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-01-11 11:42:10,842 INFO L276 PluginConnector]: TraceAbstraction initialized [2019-01-11 11:42:10,842 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:10" (1/2) ... [2019-01-11 11:42:10,843 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5d3e1bfd and model type speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.01 11:42:10, skipping insertion in model container [2019-01-11 11:42:10,844 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-3-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.01 11:42:10" (2/2) ... [2019-01-11 11:42:10,845 INFO L112 eAbstractionObserver]: Analyzing ICFG speedup-poc-dd-3-limited.bpl [2019-01-11 11:42:10,853 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-01-11 11:42:10,859 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 3 error locations. [2019-01-11 11:42:10,874 INFO L257 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2019-01-11 11:42:10,902 INFO L382 AbstractCegarLoop]: Interprodecural is true [2019-01-11 11:42:10,902 INFO L383 AbstractCegarLoop]: Hoare is true [2019-01-11 11:42:10,902 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-01-11 11:42:10,903 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-01-11 11:42:10,903 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-01-11 11:42:10,903 INFO L387 AbstractCegarLoop]: Difference is false [2019-01-11 11:42:10,903 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-01-11 11:42:10,903 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-01-11 11:42:10,918 INFO L276 IsEmpty]: Start isEmpty. Operand 9 states. [2019-01-11 11:42:10,924 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3 [2019-01-11 11:42:10,924 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:42:10,925 INFO L402 BasicCegarLoop]: trace histogram [1, 1] [2019-01-11 11:42:10,928 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:42:10,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:42:10,933 INFO L82 PathProgramCache]: Analyzing trace with hash 976, now seen corresponding path program 1 times [2019-01-11 11:42:10,935 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:42:10,976 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:10,976 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:42:10,976 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:10,977 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:42:11,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:42:11,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:42:11,105 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-11 11:42:11,105 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-11 11:42:11,105 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:42:11,113 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-11 11:42:11,128 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-11 11:42:11,129 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:42:11,132 INFO L87 Difference]: Start difference. First operand 9 states. Second operand 3 states. [2019-01-11 11:42:11,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:42:11,345 INFO L93 Difference]: Finished difference Result 17 states and 21 transitions. [2019-01-11 11:42:11,345 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:42:11,347 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 2 [2019-01-11 11:42:11,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:42:11,360 INFO L225 Difference]: With dead ends: 17 [2019-01-11 11:42:11,360 INFO L226 Difference]: Without dead ends: 12 [2019-01-11 11:42:11,363 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:42:11,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states. [2019-01-11 11:42:11,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 8. [2019-01-11 11:42:11,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8 states. [2019-01-11 11:42:11,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 13 transitions. [2019-01-11 11:42:11,401 INFO L78 Accepts]: Start accepts. Automaton has 8 states and 13 transitions. Word has length 2 [2019-01-11 11:42:11,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:42:11,403 INFO L480 AbstractCegarLoop]: Abstraction has 8 states and 13 transitions. [2019-01-11 11:42:11,403 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-11 11:42:11,403 INFO L276 IsEmpty]: Start isEmpty. Operand 8 states and 13 transitions. [2019-01-11 11:42:11,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:42:11,411 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:42:11,411 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:42:11,412 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:42:11,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:42:11,412 INFO L82 PathProgramCache]: Analyzing trace with hash 30304, now seen corresponding path program 1 times [2019-01-11 11:42:11,413 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:42:11,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:11,416 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:42:11,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:11,416 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:42:11,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:42:11,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:42:11,525 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-11 11:42:11,525 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-11 11:42:11,526 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:42:11,528 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-11 11:42:11,529 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-11 11:42:11,529 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:42:11,529 INFO L87 Difference]: Start difference. First operand 8 states and 13 transitions. Second operand 3 states. [2019-01-11 11:42:11,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:42:11,723 INFO L93 Difference]: Finished difference Result 12 states and 16 transitions. [2019-01-11 11:42:11,723 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:42:11,724 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-01-11 11:42:11,724 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:42:11,724 INFO L225 Difference]: With dead ends: 12 [2019-01-11 11:42:11,725 INFO L226 Difference]: Without dead ends: 11 [2019-01-11 11:42:11,726 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:42:11,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2019-01-11 11:42:11,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 9. [2019-01-11 11:42:11,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9 states. [2019-01-11 11:42:11,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 14 transitions. [2019-01-11 11:42:11,732 INFO L78 Accepts]: Start accepts. Automaton has 9 states and 14 transitions. Word has length 3 [2019-01-11 11:42:11,732 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:42:11,732 INFO L480 AbstractCegarLoop]: Abstraction has 9 states and 14 transitions. [2019-01-11 11:42:11,732 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-11 11:42:11,733 INFO L276 IsEmpty]: Start isEmpty. Operand 9 states and 14 transitions. [2019-01-11 11:42:11,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:42:11,733 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:42:11,733 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:42:11,734 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:42:11,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:42:11,735 INFO L82 PathProgramCache]: Analyzing trace with hash 29992, now seen corresponding path program 1 times [2019-01-11 11:42:11,735 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:42:11,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:11,736 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:42:11,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:11,736 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:42:11,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:42:11,819 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:42:11,819 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:42:11,819 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:42:11,820 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:42:11,822 INFO L207 CegarAbsIntRunner]: [0], [6], [15] [2019-01-11 11:42:11,894 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:42:11,894 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:42:19,448 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:42:19,450 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:42:19,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:42:19,456 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:42:19,785 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 71.43% of their original sizes. [2019-01-11 11:42:19,785 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:42:21,965 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_69 Int) (v_idx_67 Int) (v_idx_68 Int) (v_idx_72 Int) (v_idx_73 Int) (v_idx_70 Int) (v_idx_71 Int)) (exists ((v_b_113_1 Int) (v_b_112_1 Int) (v_v_999_1 Int) (v_v_1005_1 Int) (v_v_1001_1 Int) (v_v_1003_1 Int) (v_b_115_1 Int) (v_b_114_1 Int) (v_v_1000_1 Int)) (let ((.cse2 (+ v_b_114_1 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ v_b_112_1 1))) (and (<= (+ v_b_112_1 2) v_b_115_1) (<= .cse0 v_b_112_1) (or (< v_idx_73 v_b_115_1) (= (select |c_#memory_int| v_idx_73) v_v_1005_1)) (<= .cse1 v_b_113_1) (or (< v_idx_72 v_b_114_1) (<= v_b_115_1 v_idx_72) (= 0 (select |c_#memory_int| v_idx_72))) (<= v_b_115_1 .cse2) (or (= (select |c_#memory_int| v_idx_68) v_v_1000_1) (<= .cse0 v_idx_68) (< v_idx_68 c_ULTIMATE.start_main_p1)) (<= .cse2 v_b_115_1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_1) (or (< v_idx_69 .cse0) (<= v_b_112_1 v_idx_69) (= (select |c_#memory_int| v_idx_69) v_v_1001_1)) (<= .cse3 v_b_113_1) (or (= v_v_999_1 (select |c_#memory_int| v_idx_67)) (<= c_ULTIMATE.start_main_p1 v_idx_67)) (or (< v_idx_71 v_b_113_1) (<= v_b_114_1 v_idx_71) (= (select |c_#memory_int| v_idx_71) v_v_1003_1)) (or (<= v_b_113_1 v_idx_70) (= 0 (select |c_#memory_int| v_idx_70)) (< v_idx_70 v_b_112_1)) (<= v_b_113_1 .cse3) (<= v_b_113_1 v_b_114_1) (<= .cse1 v_b_114_1) (<= (+ v_b_113_1 1) v_b_115_1) (<= 0 (* 2 v_v_1000_1)) (<= 0 v_v_1000_1) (<= .cse3 v_b_114_1))))) is different from false [2019-01-11 11:42:24,006 WARN L860 $PredicateComparison]: unable to prove that (forall ((v_idx_69 Int) (v_idx_67 Int) (v_idx_68 Int) (v_idx_72 Int) (v_idx_73 Int) (v_idx_70 Int) (v_idx_71 Int)) (exists ((v_b_113_1 Int) (v_b_112_1 Int) (v_v_999_1 Int) (v_v_1005_1 Int) (v_v_1001_1 Int) (v_v_1003_1 Int) (v_b_115_1 Int) (v_b_114_1 Int) (v_v_1000_1 Int)) (let ((.cse2 (+ v_b_114_1 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ v_b_112_1 1))) (and (<= (+ v_b_112_1 2) v_b_115_1) (<= .cse0 v_b_112_1) (or (< v_idx_73 v_b_115_1) (= (select |c_#memory_int| v_idx_73) v_v_1005_1)) (<= .cse1 v_b_113_1) (or (< v_idx_72 v_b_114_1) (<= v_b_115_1 v_idx_72) (= 0 (select |c_#memory_int| v_idx_72))) (<= v_b_115_1 .cse2) (or (= (select |c_#memory_int| v_idx_68) v_v_1000_1) (<= .cse0 v_idx_68) (< v_idx_68 c_ULTIMATE.start_main_p1)) (<= .cse2 v_b_115_1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_1) (or (< v_idx_69 .cse0) (<= v_b_112_1 v_idx_69) (= (select |c_#memory_int| v_idx_69) v_v_1001_1)) (<= .cse3 v_b_113_1) (or (= v_v_999_1 (select |c_#memory_int| v_idx_67)) (<= c_ULTIMATE.start_main_p1 v_idx_67)) (or (< v_idx_71 v_b_113_1) (<= v_b_114_1 v_idx_71) (= (select |c_#memory_int| v_idx_71) v_v_1003_1)) (or (<= v_b_113_1 v_idx_70) (= 0 (select |c_#memory_int| v_idx_70)) (< v_idx_70 v_b_112_1)) (<= v_b_113_1 .cse3) (<= v_b_113_1 v_b_114_1) (<= .cse1 v_b_114_1) (<= (+ v_b_113_1 1) v_b_115_1) (<= 0 (* 2 v_v_1000_1)) (<= 0 v_v_1000_1) (<= .cse3 v_b_114_1))))) is different from true [2019-01-11 11:42:26,168 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_78 Int) (v_idx_79 Int) (v_idx_76 Int) (v_idx_77 Int) (v_idx_74 Int) (v_idx_75 Int) (v_idx_80 Int)) (exists ((v_b_113_1 Int) (v_b_112_1 Int) (v_v_999_1 Int) (v_v_1005_1 Int) (v_v_1001_1 Int) (v_v_1003_1 Int) (v_b_115_1 Int) (v_b_114_1 Int) (v_v_1000_1 Int)) (let ((.cse2 (+ v_b_114_1 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ v_b_112_1 1))) (and (<= (+ v_b_112_1 2) v_b_115_1) (<= .cse0 v_b_112_1) (or (<= v_b_112_1 v_idx_76) (= (select |c_#memory_int| v_idx_76) v_v_1001_1) (< v_idx_76 .cse0)) (<= .cse1 v_b_113_1) (or (= (select |c_#memory_int| v_idx_80) v_v_1005_1) (< v_idx_80 v_b_115_1)) (<= v_b_115_1 .cse2) (<= .cse2 v_b_115_1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_1) (or (< v_idx_77 v_b_112_1) (= (select |c_#memory_int| v_idx_77) 0) (<= v_b_113_1 v_idx_77)) (or (= (select |c_#memory_int| v_idx_75) v_v_1000_1) (< v_idx_75 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_75)) (<= .cse3 v_b_113_1) (<= v_b_113_1 .cse3) (<= v_b_113_1 v_b_114_1) (<= .cse1 v_b_114_1) (or (= (select |c_#memory_int| v_idx_79) 0) (< v_idx_79 v_b_114_1) (<= v_b_115_1 v_idx_79)) (or (= (select |c_#memory_int| v_idx_74) v_v_999_1) (<= c_ULTIMATE.start_main_p1 v_idx_74)) (<= (+ v_b_113_1 1) v_b_115_1) (<= 0 (* 2 v_v_1000_1)) (<= 0 v_v_1000_1) (<= .cse3 v_b_114_1) (or (= (select |c_#memory_int| v_idx_78) v_v_1003_1) (<= v_b_114_1 v_idx_78) (< v_idx_78 v_b_113_1)))))) is different from false [2019-01-11 11:42:26,213 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:42:26,214 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:42:26,214 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:42:26,215 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:42:26,215 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:42:26,215 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:42:26,215 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:42:26,216 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=2, Unknown=3, NotChecked=2, Total=12 [2019-01-11 11:42:26,216 INFO L87 Difference]: Start difference. First operand 9 states and 14 transitions. Second operand 4 states. [2019-01-11 11:42:29,978 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_69 Int) (v_idx_67 Int) (v_idx_68 Int) (v_idx_72 Int) (v_idx_73 Int) (v_idx_70 Int) (v_idx_71 Int)) (exists ((v_b_113_1 Int) (v_b_112_1 Int) (v_v_999_1 Int) (v_v_1005_1 Int) (v_v_1001_1 Int) (v_v_1003_1 Int) (v_b_115_1 Int) (v_b_114_1 Int) (v_v_1000_1 Int)) (let ((.cse2 (+ v_b_114_1 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ v_b_112_1 1))) (and (<= (+ v_b_112_1 2) v_b_115_1) (<= .cse0 v_b_112_1) (or (< v_idx_73 v_b_115_1) (= (select |c_#memory_int| v_idx_73) v_v_1005_1)) (<= .cse1 v_b_113_1) (or (< v_idx_72 v_b_114_1) (<= v_b_115_1 v_idx_72) (= 0 (select |c_#memory_int| v_idx_72))) (<= v_b_115_1 .cse2) (or (= (select |c_#memory_int| v_idx_68) v_v_1000_1) (<= .cse0 v_idx_68) (< v_idx_68 c_ULTIMATE.start_main_p1)) (<= .cse2 v_b_115_1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_1) (or (< v_idx_69 .cse0) (<= v_b_112_1 v_idx_69) (= (select |c_#memory_int| v_idx_69) v_v_1001_1)) (<= .cse3 v_b_113_1) (or (= v_v_999_1 (select |c_#memory_int| v_idx_67)) (<= c_ULTIMATE.start_main_p1 v_idx_67)) (or (< v_idx_71 v_b_113_1) (<= v_b_114_1 v_idx_71) (= (select |c_#memory_int| v_idx_71) v_v_1003_1)) (or (<= v_b_113_1 v_idx_70) (= 0 (select |c_#memory_int| v_idx_70)) (< v_idx_70 v_b_112_1)) (<= v_b_113_1 .cse3) (<= v_b_113_1 v_b_114_1) (<= .cse1 v_b_114_1) (<= (+ v_b_113_1 1) v_b_115_1) (<= 0 (* 2 v_v_1000_1)) (<= 0 v_v_1000_1) (<= .cse3 v_b_114_1))))) (forall ((v_idx_78 Int) (v_idx_79 Int) (v_idx_76 Int) (v_idx_77 Int) (v_idx_74 Int) (v_idx_75 Int) (v_idx_80 Int)) (exists ((v_b_113_1 Int) (v_b_112_1 Int) (v_v_999_1 Int) (v_v_1005_1 Int) (v_v_1001_1 Int) (v_v_1003_1 Int) (v_b_115_1 Int) (v_b_114_1 Int) (v_v_1000_1 Int)) (let ((.cse6 (+ v_b_114_1 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ v_b_112_1 1))) (and (<= (+ v_b_112_1 2) v_b_115_1) (<= .cse4 v_b_112_1) (or (<= v_b_112_1 v_idx_76) (= (select |c_#memory_int| v_idx_76) v_v_1001_1) (< v_idx_76 .cse4)) (<= .cse5 v_b_113_1) (or (= (select |c_#memory_int| v_idx_80) v_v_1005_1) (< v_idx_80 v_b_115_1)) (<= v_b_115_1 .cse6) (<= .cse6 v_b_115_1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_1) (or (< v_idx_77 v_b_112_1) (= (select |c_#memory_int| v_idx_77) 0) (<= v_b_113_1 v_idx_77)) (or (= (select |c_#memory_int| v_idx_75) v_v_1000_1) (< v_idx_75 c_ULTIMATE.start_main_p1) (<= .cse4 v_idx_75)) (<= .cse7 v_b_113_1) (<= v_b_113_1 .cse7) (<= v_b_113_1 v_b_114_1) (<= .cse5 v_b_114_1) (or (= (select |c_#memory_int| v_idx_79) 0) (< v_idx_79 v_b_114_1) (<= v_b_115_1 v_idx_79)) (or (= (select |c_#memory_int| v_idx_74) v_v_999_1) (<= c_ULTIMATE.start_main_p1 v_idx_74)) (<= (+ v_b_113_1 1) v_b_115_1) (<= 0 (* 2 v_v_1000_1)) (<= 0 v_v_1000_1) (<= .cse7 v_b_114_1) (or (= (select |c_#memory_int| v_idx_78) v_v_1003_1) (<= v_b_114_1 v_idx_78) (< v_idx_78 v_b_113_1))))))) is different from false [2019-01-11 11:42:55,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:42:55,595 INFO L93 Difference]: Finished difference Result 11 states and 19 transitions. [2019-01-11 11:42:55,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:42:55,595 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:42:55,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:42:55,596 INFO L225 Difference]: With dead ends: 11 [2019-01-11 11:42:55,596 INFO L226 Difference]: Without dead ends: 10 [2019-01-11 11:42:55,597 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 10.2s TimeCoverageRelationStatistics Valid=7, Invalid=3, Unknown=4, NotChecked=6, Total=20 [2019-01-11 11:42:55,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states. [2019-01-11 11:42:55,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2019-01-11 11:42:55,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2019-01-11 11:42:55,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 18 transitions. [2019-01-11 11:42:55,603 INFO L78 Accepts]: Start accepts. Automaton has 10 states and 18 transitions. Word has length 3 [2019-01-11 11:42:55,604 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:42:55,606 INFO L480 AbstractCegarLoop]: Abstraction has 10 states and 18 transitions. [2019-01-11 11:42:55,606 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:42:55,606 INFO L276 IsEmpty]: Start isEmpty. Operand 10 states and 18 transitions. [2019-01-11 11:42:55,607 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:42:55,607 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:42:55,607 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:42:55,608 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:42:55,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:42:55,609 INFO L82 PathProgramCache]: Analyzing trace with hash 30116, now seen corresponding path program 1 times [2019-01-11 11:42:55,609 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:42:55,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:55,610 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:42:55,611 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:55,611 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:42:55,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:42:55,721 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:42:55,722 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:42:55,722 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:42:55,722 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:42:55,723 INFO L207 CegarAbsIntRunner]: [0], [10], [15] [2019-01-11 11:42:55,725 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:42:55,725 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:43:00,164 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:43:00,164 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:43:00,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:43:00,165 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:43:00,350 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 64.29% of their original sizes. [2019-01-11 11:43:00,351 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:43:02,899 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_148 Int) (v_idx_149 Int) (v_idx_147 Int) (v_idx_151 Int) (v_idx_152 Int) (v_idx_150 Int) (v_idx_153 Int)) (exists ((v_v_1303_2 Int) (v_v_1301_2 Int) (v_v_1299_2 Int) (v_v_1302_2 Int) (v_b_114_2 Int) (v_v_1305_2 Int) (v_b_115_2 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_114_2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= v_b_114_2 v_idx_151) (= (select |c_#memory_int| v_idx_151) v_v_1303_2) (< v_idx_151 .cse0)) (or (= (select |c_#memory_int| v_idx_153) v_v_1305_2) (< v_idx_153 v_b_115_2)) (or (<= c_ULTIMATE.start_main_p2 v_idx_149) (= (select |c_#memory_int| v_idx_149) v_v_1301_2) (< v_idx_149 .cse1)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_2) (<= v_v_1302_2 0) (<= v_b_115_2 .cse2) (or (< v_idx_150 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_150) v_v_1302_2) (<= .cse0 v_idx_150)) (<= .cse0 v_b_114_2) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_115_2) (<= .cse2 v_b_115_2) (<= (* 2 v_v_1302_2) 0) (or (< v_idx_152 v_b_114_2) (= (select |c_#memory_int| v_idx_152) 0) (<= v_b_115_2 v_idx_152)) (<= .cse1 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_147) v_v_1299_2) (<= c_ULTIMATE.start_main_p1 v_idx_147)) (or (= (select |c_#memory_int| v_idx_148) 0) (<= .cse1 v_idx_148) (< v_idx_148 c_ULTIMATE.start_main_p1)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_114_2))))) is different from false [2019-01-11 11:43:05,214 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_159 Int) (v_idx_157 Int) (v_idx_158 Int) (v_idx_160 Int) (v_idx_155 Int) (v_idx_156 Int) (v_idx_154 Int)) (exists ((v_b_112_2 Int) (v_v_1303_2 Int) (v_v_1301_2 Int) (v_v_1299_2 Int) (v_v_1302_2 Int) (v_b_114_2 Int) (v_b_113_2 Int) (v_v_1305_2 Int) (v_b_115_2 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ v_b_114_2 1)) (.cse0 (+ v_b_112_2 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2))) (and (<= .cse0 v_b_114_2) (or (<= v_b_115_2 v_idx_159) (= (select |c_#memory_int| v_idx_159) 0) (< v_idx_159 v_b_114_2)) (<= .cse1 v_b_112_2) (<= v_b_113_2 v_b_114_2) (or (= (select |c_#memory_int| v_idx_156) v_v_1301_2) (<= v_b_112_2 v_idx_156) (< v_idx_156 .cse1)) (<= (+ v_b_112_2 2) v_b_115_2) (<= (+ v_b_113_2 1) v_b_115_2) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_2) (<= .cse0 v_b_113_2) (<= v_v_1302_2 0) (<= v_b_115_2 .cse2) (<= .cse3 v_b_113_2) (or (= (select |c_#memory_int| v_idx_160) v_v_1305_2) (< v_idx_160 v_b_115_2)) (or (< v_idx_155 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_155)) (<= .cse1 v_idx_155)) (<= .cse2 v_b_115_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_154) (= (select |c_#memory_int| v_idx_154) v_v_1299_2)) (<= (* 2 v_v_1302_2) 0) (<= v_b_113_2 .cse0) (or (<= v_b_113_2 v_idx_157) (< v_idx_157 v_b_112_2) (= (select |c_#memory_int| v_idx_157) v_v_1302_2)) (or (< v_idx_158 v_b_113_2) (<= v_b_114_2 v_idx_158) (= (select |c_#memory_int| v_idx_158) v_v_1303_2)) (<= .cse3 v_b_114_2))))) is different from false [2019-01-11 11:43:05,274 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:43:05,274 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:43:05,274 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:43:05,274 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:43:05,274 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:43:05,275 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:43:05,275 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:43:05,275 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:43:05,275 INFO L87 Difference]: Start difference. First operand 10 states and 18 transitions. Second operand 4 states. [2019-01-11 11:43:07,934 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_159 Int) (v_idx_157 Int) (v_idx_158 Int) (v_idx_160 Int) (v_idx_155 Int) (v_idx_156 Int) (v_idx_154 Int)) (exists ((v_b_112_2 Int) (v_v_1303_2 Int) (v_v_1301_2 Int) (v_v_1299_2 Int) (v_v_1302_2 Int) (v_b_114_2 Int) (v_b_113_2 Int) (v_v_1305_2 Int) (v_b_115_2 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ v_b_114_2 1)) (.cse0 (+ v_b_112_2 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2))) (and (<= .cse0 v_b_114_2) (or (<= v_b_115_2 v_idx_159) (= (select |c_#memory_int| v_idx_159) 0) (< v_idx_159 v_b_114_2)) (<= .cse1 v_b_112_2) (<= v_b_113_2 v_b_114_2) (or (= (select |c_#memory_int| v_idx_156) v_v_1301_2) (<= v_b_112_2 v_idx_156) (< v_idx_156 .cse1)) (<= (+ v_b_112_2 2) v_b_115_2) (<= (+ v_b_113_2 1) v_b_115_2) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_2) (<= .cse0 v_b_113_2) (<= v_v_1302_2 0) (<= v_b_115_2 .cse2) (<= .cse3 v_b_113_2) (or (= (select |c_#memory_int| v_idx_160) v_v_1305_2) (< v_idx_160 v_b_115_2)) (or (< v_idx_155 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_155)) (<= .cse1 v_idx_155)) (<= .cse2 v_b_115_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_154) (= (select |c_#memory_int| v_idx_154) v_v_1299_2)) (<= (* 2 v_v_1302_2) 0) (<= v_b_113_2 .cse0) (or (<= v_b_113_2 v_idx_157) (< v_idx_157 v_b_112_2) (= (select |c_#memory_int| v_idx_157) v_v_1302_2)) (or (< v_idx_158 v_b_113_2) (<= v_b_114_2 v_idx_158) (= (select |c_#memory_int| v_idx_158) v_v_1303_2)) (<= .cse3 v_b_114_2))))) (forall ((v_idx_148 Int) (v_idx_149 Int) (v_idx_147 Int) (v_idx_151 Int) (v_idx_152 Int) (v_idx_150 Int) (v_idx_153 Int)) (exists ((v_v_1303_2 Int) (v_v_1301_2 Int) (v_v_1299_2 Int) (v_v_1302_2 Int) (v_b_114_2 Int) (v_v_1305_2 Int) (v_b_115_2 Int)) (let ((.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse6 (+ v_b_114_2 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= v_b_114_2 v_idx_151) (= (select |c_#memory_int| v_idx_151) v_v_1303_2) (< v_idx_151 .cse4)) (or (= (select |c_#memory_int| v_idx_153) v_v_1305_2) (< v_idx_153 v_b_115_2)) (or (<= c_ULTIMATE.start_main_p2 v_idx_149) (= (select |c_#memory_int| v_idx_149) v_v_1301_2) (< v_idx_149 .cse5)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_2) (<= v_v_1302_2 0) (<= v_b_115_2 .cse6) (or (< v_idx_150 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_150) v_v_1302_2) (<= .cse4 v_idx_150)) (<= .cse4 v_b_114_2) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_115_2) (<= .cse6 v_b_115_2) (<= (* 2 v_v_1302_2) 0) (or (< v_idx_152 v_b_114_2) (= (select |c_#memory_int| v_idx_152) 0) (<= v_b_115_2 v_idx_152)) (<= .cse5 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_147) v_v_1299_2) (<= c_ULTIMATE.start_main_p1 v_idx_147)) (or (= (select |c_#memory_int| v_idx_148) 0) (<= .cse5 v_idx_148) (< v_idx_148 c_ULTIMATE.start_main_p1)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_114_2)))))) is different from false [2019-01-11 11:43:17,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:43:17,633 INFO L93 Difference]: Finished difference Result 12 states and 23 transitions. [2019-01-11 11:43:17,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:43:17,634 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:43:17,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:43:17,635 INFO L225 Difference]: With dead ends: 12 [2019-01-11 11:43:17,635 INFO L226 Difference]: Without dead ends: 11 [2019-01-11 11:43:17,635 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.6s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:43:17,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2019-01-11 11:43:17,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 10. [2019-01-11 11:43:17,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2019-01-11 11:43:17,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 18 transitions. [2019-01-11 11:43:17,641 INFO L78 Accepts]: Start accepts. Automaton has 10 states and 18 transitions. Word has length 3 [2019-01-11 11:43:17,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:43:17,642 INFO L480 AbstractCegarLoop]: Abstraction has 10 states and 18 transitions. [2019-01-11 11:43:17,642 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:43:17,642 INFO L276 IsEmpty]: Start isEmpty. Operand 10 states and 18 transitions. [2019-01-11 11:43:17,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:43:17,642 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:43:17,643 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:43:17,643 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:43:17,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:43:17,643 INFO L82 PathProgramCache]: Analyzing trace with hash 30178, now seen corresponding path program 1 times [2019-01-11 11:43:17,643 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:43:17,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:43:17,645 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:43:17,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:43:17,645 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:43:17,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:43:17,853 WARN L181 SmtUtils]: Spent 145.00 ms on a formula simplification. DAG size of input: 23 DAG size of output: 13 [2019-01-11 11:43:17,901 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:43:17,901 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:43:17,901 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:43:17,901 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:43:17,902 INFO L207 CegarAbsIntRunner]: [0], [12], [15] [2019-01-11 11:43:17,903 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:43:17,903 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:43:22,484 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:43:22,485 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:43:22,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:43:22,485 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:43:22,670 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 64.29% of their original sizes. [2019-01-11 11:43:22,670 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:43:25,161 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_229 Int) (v_idx_227 Int) (v_idx_228 Int) (v_idx_232 Int) (v_idx_233 Int) (v_idx_230 Int) (v_idx_231 Int)) (exists ((v_v_1149_3 Int) (v_v_1153_3 Int) (v_v_1154_3 Int) (v_v_1155_3 Int) (v_b_113_3 Int) (v_b_112_3 Int) (v_v_1151_3 Int)) (let ((.cse1 (+ v_b_112_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse0 c_ULTIMATE.start_main_p3) (<= v_b_113_3 .cse1) (<= 0 v_v_1154_3) (or (< v_idx_228 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_228)) (<= .cse2 v_idx_228)) (<= v_b_113_3 c_ULTIMATE.start_main_p3) (<= .cse1 c_ULTIMATE.start_main_p3) (<= .cse1 v_b_113_3) (<= .cse0 v_b_113_3) (or (< v_idx_229 .cse2) (= (select |c_#memory_int| v_idx_229) v_v_1151_3) (<= v_b_112_3 v_idx_229)) (<= .cse2 v_b_112_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_227) (= (select |c_#memory_int| v_idx_227) v_v_1149_3)) (or (< v_idx_233 .cse3) (= (select |c_#memory_int| v_idx_233) v_v_1155_3)) (or (= (select |c_#memory_int| v_idx_232) v_v_1154_3) (< v_idx_232 c_ULTIMATE.start_main_p3) (<= .cse3 v_idx_232)) (or (= 0 (select |c_#memory_int| v_idx_230)) (<= v_b_113_3 v_idx_230) (< v_idx_230 v_b_112_3)) (or (< v_idx_231 v_b_113_3) (= (select |c_#memory_int| v_idx_231) v_v_1153_3) (<= c_ULTIMATE.start_main_p3 v_idx_231)) (<= 0 (* 2 v_v_1154_3)))))) is different from false [2019-01-11 11:43:27,480 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_236 Int) (v_idx_237 Int) (v_idx_234 Int) (v_idx_235 Int) (v_idx_238 Int) (v_idx_239 Int) (v_idx_240 Int)) (exists ((v_v_1149_3 Int) (v_v_1153_3 Int) (v_v_1154_3 Int) (v_v_1155_3 Int) (v_b_113_3 Int) (v_b_112_3 Int) (v_v_1151_3 Int) (v_b_115_3 Int) (v_b_114_3 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ v_b_114_3 1)) (.cse0 (+ v_b_112_3 1))) (and (<= v_b_113_3 .cse0) (<= 0 v_v_1154_3) (or (= 0 (select |c_#memory_int| v_idx_235)) (<= .cse1 v_idx_235) (< v_idx_235 c_ULTIMATE.start_main_p1)) (or (< v_idx_236 .cse1) (= (select |c_#memory_int| v_idx_236) v_v_1151_3) (<= v_b_112_3 v_idx_236)) (<= .cse0 v_b_113_3) (<= .cse2 v_b_113_3) (<= v_b_115_3 .cse3) (<= .cse2 v_b_114_3) (<= .cse1 v_b_112_3) (or (< v_idx_240 v_b_115_3) (= (select |c_#memory_int| v_idx_240) v_v_1155_3)) (<= v_b_113_3 v_b_114_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_3) (<= (+ v_b_112_3 2) v_b_115_3) (<= .cse3 v_b_115_3) (or (<= v_b_113_3 v_idx_237) (< v_idx_237 v_b_112_3) (= 0 (select |c_#memory_int| v_idx_237))) (<= .cse0 v_b_114_3) (<= (+ v_b_113_3 1) v_b_115_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_234) (= (select |c_#memory_int| v_idx_234) v_v_1149_3)) (or (<= v_b_115_3 v_idx_239) (= (select |c_#memory_int| v_idx_239) v_v_1154_3) (< v_idx_239 v_b_114_3)) (or (< v_idx_238 v_b_113_3) (<= v_b_114_3 v_idx_238) (= (select |c_#memory_int| v_idx_238) v_v_1153_3)) (<= 0 (* 2 v_v_1154_3)))))) is different from false [2019-01-11 11:43:27,544 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:43:27,544 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:43:27,545 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:43:27,545 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:43:27,545 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:43:27,545 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:43:27,545 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:43:27,545 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:43:27,546 INFO L87 Difference]: Start difference. First operand 10 states and 18 transitions. Second operand 4 states. [2019-01-11 11:43:30,097 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_236 Int) (v_idx_237 Int) (v_idx_234 Int) (v_idx_235 Int) (v_idx_238 Int) (v_idx_239 Int) (v_idx_240 Int)) (exists ((v_v_1149_3 Int) (v_v_1153_3 Int) (v_v_1154_3 Int) (v_v_1155_3 Int) (v_b_113_3 Int) (v_b_112_3 Int) (v_v_1151_3 Int) (v_b_115_3 Int) (v_b_114_3 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ v_b_114_3 1)) (.cse0 (+ v_b_112_3 1))) (and (<= v_b_113_3 .cse0) (<= 0 v_v_1154_3) (or (= 0 (select |c_#memory_int| v_idx_235)) (<= .cse1 v_idx_235) (< v_idx_235 c_ULTIMATE.start_main_p1)) (or (< v_idx_236 .cse1) (= (select |c_#memory_int| v_idx_236) v_v_1151_3) (<= v_b_112_3 v_idx_236)) (<= .cse0 v_b_113_3) (<= .cse2 v_b_113_3) (<= v_b_115_3 .cse3) (<= .cse2 v_b_114_3) (<= .cse1 v_b_112_3) (or (< v_idx_240 v_b_115_3) (= (select |c_#memory_int| v_idx_240) v_v_1155_3)) (<= v_b_113_3 v_b_114_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_115_3) (<= (+ v_b_112_3 2) v_b_115_3) (<= .cse3 v_b_115_3) (or (<= v_b_113_3 v_idx_237) (< v_idx_237 v_b_112_3) (= 0 (select |c_#memory_int| v_idx_237))) (<= .cse0 v_b_114_3) (<= (+ v_b_113_3 1) v_b_115_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_234) (= (select |c_#memory_int| v_idx_234) v_v_1149_3)) (or (<= v_b_115_3 v_idx_239) (= (select |c_#memory_int| v_idx_239) v_v_1154_3) (< v_idx_239 v_b_114_3)) (or (< v_idx_238 v_b_113_3) (<= v_b_114_3 v_idx_238) (= (select |c_#memory_int| v_idx_238) v_v_1153_3)) (<= 0 (* 2 v_v_1154_3)))))) (forall ((v_idx_229 Int) (v_idx_227 Int) (v_idx_228 Int) (v_idx_232 Int) (v_idx_233 Int) (v_idx_230 Int) (v_idx_231 Int)) (exists ((v_v_1149_3 Int) (v_v_1153_3 Int) (v_v_1154_3 Int) (v_v_1155_3 Int) (v_b_113_3 Int) (v_b_112_3 Int) (v_v_1151_3 Int)) (let ((.cse5 (+ v_b_112_3 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 2)) (.cse6 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse4 c_ULTIMATE.start_main_p3) (<= v_b_113_3 .cse5) (<= 0 v_v_1154_3) (or (< v_idx_228 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_228)) (<= .cse6 v_idx_228)) (<= v_b_113_3 c_ULTIMATE.start_main_p3) (<= .cse5 c_ULTIMATE.start_main_p3) (<= .cse5 v_b_113_3) (<= .cse4 v_b_113_3) (or (< v_idx_229 .cse6) (= (select |c_#memory_int| v_idx_229) v_v_1151_3) (<= v_b_112_3 v_idx_229)) (<= .cse6 v_b_112_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_227) (= (select |c_#memory_int| v_idx_227) v_v_1149_3)) (or (< v_idx_233 .cse7) (= (select |c_#memory_int| v_idx_233) v_v_1155_3)) (or (= (select |c_#memory_int| v_idx_232) v_v_1154_3) (< v_idx_232 c_ULTIMATE.start_main_p3) (<= .cse7 v_idx_232)) (or (= 0 (select |c_#memory_int| v_idx_230)) (<= v_b_113_3 v_idx_230) (< v_idx_230 v_b_112_3)) (or (< v_idx_231 v_b_113_3) (= (select |c_#memory_int| v_idx_231) v_v_1153_3) (<= c_ULTIMATE.start_main_p3 v_idx_231)) (<= 0 (* 2 v_v_1154_3))))))) is different from false [2019-01-11 11:43:40,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:43:40,464 INFO L93 Difference]: Finished difference Result 12 states and 23 transitions. [2019-01-11 11:43:40,464 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:43:40,464 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:43:40,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:43:40,465 INFO L225 Difference]: With dead ends: 12 [2019-01-11 11:43:40,465 INFO L226 Difference]: Without dead ends: 11 [2019-01-11 11:43:40,465 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.5s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:43:40,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2019-01-11 11:43:40,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 10. [2019-01-11 11:43:40,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2019-01-11 11:43:40,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 18 transitions. [2019-01-11 11:43:40,472 INFO L78 Accepts]: Start accepts. Automaton has 10 states and 18 transitions. Word has length 3 [2019-01-11 11:43:40,473 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:43:40,473 INFO L480 AbstractCegarLoop]: Abstraction has 10 states and 18 transitions. [2019-01-11 11:43:40,473 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:43:40,473 INFO L276 IsEmpty]: Start isEmpty. Operand 10 states and 18 transitions. [2019-01-11 11:43:40,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:43:40,473 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:43:40,474 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-11 11:43:40,474 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:43:40,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:43:40,474 INFO L82 PathProgramCache]: Analyzing trace with hash 939474, now seen corresponding path program 1 times [2019-01-11 11:43:40,475 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:43:40,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:43:40,476 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:43:40,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:43:40,476 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:43:40,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:43:40,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:43:40,499 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-11 11:43:40,500 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-11 11:43:40,500 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:43:40,500 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-11 11:43:40,500 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-11 11:43:40,500 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:43:40,501 INFO L87 Difference]: Start difference. First operand 10 states and 18 transitions. Second operand 3 states. [2019-01-11 11:43:40,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:43:40,551 INFO L93 Difference]: Finished difference Result 12 states and 19 transitions. [2019-01-11 11:43:40,551 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:43:40,551 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 4 [2019-01-11 11:43:40,552 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:43:40,552 INFO L225 Difference]: With dead ends: 12 [2019-01-11 11:43:40,552 INFO L226 Difference]: Without dead ends: 9 [2019-01-11 11:43:40,553 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:43:40,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states. [2019-01-11 11:43:40,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2019-01-11 11:43:40,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9 states. [2019-01-11 11:43:40,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 16 transitions. [2019-01-11 11:43:40,560 INFO L78 Accepts]: Start accepts. Automaton has 9 states and 16 transitions. Word has length 4 [2019-01-11 11:43:40,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:43:40,561 INFO L480 AbstractCegarLoop]: Abstraction has 9 states and 16 transitions. [2019-01-11 11:43:40,561 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-11 11:43:40,561 INFO L276 IsEmpty]: Start isEmpty. Operand 9 states and 16 transitions. [2019-01-11 11:43:40,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:43:40,562 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:43:40,562 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-11 11:43:40,562 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:43:40,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:43:40,562 INFO L82 PathProgramCache]: Analyzing trace with hash 929800, now seen corresponding path program 1 times [2019-01-11 11:43:40,562 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:43:40,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:43:40,564 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:43:40,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:43:40,564 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:43:40,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:43:40,835 WARN L181 SmtUtils]: Spent 215.00 ms on a formula simplification. DAG size of input: 19 DAG size of output: 13 [2019-01-11 11:43:40,894 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:43:40,895 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:43:40,895 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:43:40,895 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-11 11:43:40,895 INFO L207 CegarAbsIntRunner]: [0], [6], [16], [17] [2019-01-11 11:43:40,896 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:43:40,897 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:43:46,721 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:43:46,721 INFO L272 AbstractInterpreter]: Visited 4 different actions 16 times. Merged at 2 different actions 8 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:43:46,721 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:43:46,721 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:43:46,982 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 61.9% of their original sizes. [2019-01-11 11:43:46,982 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:43:49,447 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_346 Int) (v_idx_344 Int) (v_idx_345 Int) (v_idx_342 Int) (v_idx_343 Int) (v_idx_340 Int) (v_idx_341 Int)) (exists ((v_b_121_4 Int) (v_v_1509_4 Int) (v_b_120_4 Int) (v_v_1508_4 Int) (v_v_1514_4 Int) (v_v_1512_4 Int) (v_v_1510_4 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_120_4 1))) (and (or (= (select |c_#memory_int| v_idx_342) v_v_1510_4) (< v_idx_342 .cse0) (<= c_ULTIMATE.start_main_p2 v_idx_342)) (or (= (select |c_#memory_int| v_idx_343) 0) (<= .cse1 v_idx_343) (< v_idx_343 c_ULTIMATE.start_main_p2)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_121_4) (or (< v_idx_341 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_341) (= (select |c_#memory_int| v_idx_341) v_v_1509_4)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_120_4) (or (< v_idx_346 v_b_121_4) (= (select |c_#memory_int| v_idx_346) v_v_1514_4)) (or (<= v_b_120_4 v_idx_344) (< v_idx_344 .cse1) (= (select |c_#memory_int| v_idx_344) v_v_1512_4)) (<= 0 v_v_1509_4) (<= 0 (* 2 v_v_1509_4)) (<= v_b_121_4 .cse2) (or (<= c_ULTIMATE.start_main_p1 v_idx_340) (= (select |c_#memory_int| v_idx_340) v_v_1508_4)) (<= .cse0 c_ULTIMATE.start_main_p2) (<= .cse1 v_b_120_4) (or (<= v_b_121_4 v_idx_345) (= 0 (select |c_#memory_int| v_idx_345)) (< v_idx_345 v_b_120_4)) (<= .cse2 v_b_121_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_121_4))))) is different from false [2019-01-11 11:43:52,053 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_347 Int) (v_idx_348 Int) (v_idx_349 Int) (v_idx_350 Int) (v_idx_353 Int) (v_idx_351 Int) (v_idx_352 Int)) (exists ((v_b_121_4 Int) (v_b_120_4 Int) (v_v_1509_4 Int) (v_v_1508_4 Int) (v_v_1514_4 Int) (v_v_1512_4 Int) (v_v_1510_4 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_120_4 1))) (and (<= (+ c_ULTIMATE.start_main_p2 2) v_b_121_4) (or (= 0 (select |c_#memory_int| v_idx_350)) (<= .cse0 v_idx_350) (< v_idx_350 c_ULTIMATE.start_main_p2)) (or (< v_idx_353 v_b_121_4) (= (select |c_#memory_int| v_idx_353) v_v_1514_4)) (or (<= c_ULTIMATE.start_main_p1 v_idx_347) (= (select |c_#memory_int| v_idx_347) v_v_1508_4)) (or (= 0 (select |c_#memory_int| v_idx_352)) (<= v_b_121_4 v_idx_352) (< v_idx_352 v_b_120_4)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_120_4) (or (= (select |c_#memory_int| v_idx_348) v_v_1509_4) (< v_idx_348 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_348)) (<= 0 v_v_1509_4) (<= 0 (* 2 v_v_1509_4)) (<= v_b_121_4 .cse2) (or (= (select |c_#memory_int| v_idx_349) v_v_1510_4) (<= c_ULTIMATE.start_main_p2 v_idx_349) (< v_idx_349 .cse1)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= .cse0 v_b_120_4) (or (= (select |c_#memory_int| v_idx_351) v_v_1512_4) (< v_idx_351 .cse0) (<= v_b_120_4 v_idx_351)) (<= .cse2 v_b_121_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_121_4))))) is different from false [2019-01-11 11:43:54,409 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_357 Int) (v_idx_358 Int) (v_idx_355 Int) (v_idx_356 Int) (v_idx_359 Int) (v_idx_360 Int) (v_idx_354 Int)) (exists ((v_b_121_4 Int) (v_b_120_4 Int) (v_v_1508_4 Int) (v_v_1836_2 Int) (v_v_1514_4 Int) (v_b_117_4 Int) (v_b_128_4 Int) (v_v_1512_4 Int) (v_v_1510_4 Int)) (let ((.cse0 (+ v_b_128_4 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_120_4 1))) (and (<= v_b_117_4 .cse0) (<= (+ v_b_128_4 2) v_b_120_4) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_121_4) (<= (+ v_b_117_4 1) v_b_120_4) (<= (+ v_b_117_4 2) v_b_121_4) (<= .cse0 v_b_117_4) (<= .cse0 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_355) v_v_1836_2) (<= v_b_117_4 v_idx_355) (< v_idx_355 v_b_128_4)) (or (= (select |c_#memory_int| v_idx_358) v_v_1512_4) (< v_idx_358 .cse1) (<= v_b_120_4 v_idx_358)) (<= 0 v_v_1836_2) (or (<= c_ULTIMATE.start_main_p2 v_idx_356) (= (select |c_#memory_int| v_idx_356) v_v_1510_4) (< v_idx_356 v_b_117_4)) (or (= 0 (select |c_#memory_int| v_idx_357)) (<= .cse1 v_idx_357) (< v_idx_357 c_ULTIMATE.start_main_p2)) (or (< v_idx_360 v_b_121_4) (= (select |c_#memory_int| v_idx_360) v_v_1514_4)) (<= 0 (* 2 v_v_1836_2)) (<= v_b_121_4 .cse2) (<= v_b_117_4 c_ULTIMATE.start_main_p2) (<= .cse1 v_b_120_4) (or (<= v_b_128_4 v_idx_354) (= (select |c_#memory_int| v_idx_354) v_v_1508_4)) (or (<= v_b_121_4 v_idx_359) (= 0 (select |c_#memory_int| v_idx_359)) (< v_idx_359 v_b_120_4)) (<= (+ v_b_128_4 3) v_b_121_4) (<= .cse2 v_b_121_4))))) is different from false [2019-01-11 11:43:54,460 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-11 11:43:54,460 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:43:54,460 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:43:54,460 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [2] total 5 [2019-01-11 11:43:54,460 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:43:54,461 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-11 11:43:54,461 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-11 11:43:54,461 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:43:54,461 INFO L87 Difference]: Start difference. First operand 9 states and 16 transitions. Second operand 5 states. [2019-01-11 11:43:56,855 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_357 Int) (v_idx_358 Int) (v_idx_355 Int) (v_idx_356 Int) (v_idx_359 Int) (v_idx_360 Int) (v_idx_354 Int)) (exists ((v_b_121_4 Int) (v_b_120_4 Int) (v_v_1508_4 Int) (v_v_1836_2 Int) (v_v_1514_4 Int) (v_b_117_4 Int) (v_b_128_4 Int) (v_v_1512_4 Int) (v_v_1510_4 Int)) (let ((.cse0 (+ v_b_128_4 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_120_4 1))) (and (<= v_b_117_4 .cse0) (<= (+ v_b_128_4 2) v_b_120_4) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_121_4) (<= (+ v_b_117_4 1) v_b_120_4) (<= (+ v_b_117_4 2) v_b_121_4) (<= .cse0 v_b_117_4) (<= .cse0 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_355) v_v_1836_2) (<= v_b_117_4 v_idx_355) (< v_idx_355 v_b_128_4)) (or (= (select |c_#memory_int| v_idx_358) v_v_1512_4) (< v_idx_358 .cse1) (<= v_b_120_4 v_idx_358)) (<= 0 v_v_1836_2) (or (<= c_ULTIMATE.start_main_p2 v_idx_356) (= (select |c_#memory_int| v_idx_356) v_v_1510_4) (< v_idx_356 v_b_117_4)) (or (= 0 (select |c_#memory_int| v_idx_357)) (<= .cse1 v_idx_357) (< v_idx_357 c_ULTIMATE.start_main_p2)) (or (< v_idx_360 v_b_121_4) (= (select |c_#memory_int| v_idx_360) v_v_1514_4)) (<= 0 (* 2 v_v_1836_2)) (<= v_b_121_4 .cse2) (<= v_b_117_4 c_ULTIMATE.start_main_p2) (<= .cse1 v_b_120_4) (or (<= v_b_128_4 v_idx_354) (= (select |c_#memory_int| v_idx_354) v_v_1508_4)) (or (<= v_b_121_4 v_idx_359) (= 0 (select |c_#memory_int| v_idx_359)) (< v_idx_359 v_b_120_4)) (<= (+ v_b_128_4 3) v_b_121_4) (<= .cse2 v_b_121_4))))) (forall ((v_idx_347 Int) (v_idx_348 Int) (v_idx_349 Int) (v_idx_350 Int) (v_idx_353 Int) (v_idx_351 Int) (v_idx_352 Int)) (exists ((v_b_121_4 Int) (v_b_120_4 Int) (v_v_1509_4 Int) (v_v_1508_4 Int) (v_v_1514_4 Int) (v_v_1512_4 Int) (v_v_1510_4 Int)) (let ((.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ v_b_120_4 1))) (and (<= (+ c_ULTIMATE.start_main_p2 2) v_b_121_4) (or (= 0 (select |c_#memory_int| v_idx_350)) (<= .cse3 v_idx_350) (< v_idx_350 c_ULTIMATE.start_main_p2)) (or (< v_idx_353 v_b_121_4) (= (select |c_#memory_int| v_idx_353) v_v_1514_4)) (or (<= c_ULTIMATE.start_main_p1 v_idx_347) (= (select |c_#memory_int| v_idx_347) v_v_1508_4)) (or (= 0 (select |c_#memory_int| v_idx_352)) (<= v_b_121_4 v_idx_352) (< v_idx_352 v_b_120_4)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_120_4) (or (= (select |c_#memory_int| v_idx_348) v_v_1509_4) (< v_idx_348 c_ULTIMATE.start_main_p1) (<= .cse4 v_idx_348)) (<= 0 v_v_1509_4) (<= 0 (* 2 v_v_1509_4)) (<= v_b_121_4 .cse5) (or (= (select |c_#memory_int| v_idx_349) v_v_1510_4) (<= c_ULTIMATE.start_main_p2 v_idx_349) (< v_idx_349 .cse4)) (<= .cse4 c_ULTIMATE.start_main_p2) (<= .cse3 v_b_120_4) (or (= (select |c_#memory_int| v_idx_351) v_v_1512_4) (< v_idx_351 .cse3) (<= v_b_120_4 v_idx_351)) (<= .cse5 v_b_121_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_121_4))))) (forall ((v_idx_346 Int) (v_idx_344 Int) (v_idx_345 Int) (v_idx_342 Int) (v_idx_343 Int) (v_idx_340 Int) (v_idx_341 Int)) (exists ((v_b_121_4 Int) (v_v_1509_4 Int) (v_b_120_4 Int) (v_v_1508_4 Int) (v_v_1514_4 Int) (v_v_1512_4 Int) (v_v_1510_4 Int)) (let ((.cse6 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ c_ULTIMATE.start_main_p2 1)) (.cse8 (+ v_b_120_4 1))) (and (or (= (select |c_#memory_int| v_idx_342) v_v_1510_4) (< v_idx_342 .cse6) (<= c_ULTIMATE.start_main_p2 v_idx_342)) (or (= (select |c_#memory_int| v_idx_343) 0) (<= .cse7 v_idx_343) (< v_idx_343 c_ULTIMATE.start_main_p2)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_121_4) (or (< v_idx_341 c_ULTIMATE.start_main_p1) (<= .cse6 v_idx_341) (= (select |c_#memory_int| v_idx_341) v_v_1509_4)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_120_4) (or (< v_idx_346 v_b_121_4) (= (select |c_#memory_int| v_idx_346) v_v_1514_4)) (or (<= v_b_120_4 v_idx_344) (< v_idx_344 .cse7) (= (select |c_#memory_int| v_idx_344) v_v_1512_4)) (<= 0 v_v_1509_4) (<= 0 (* 2 v_v_1509_4)) (<= v_b_121_4 .cse8) (or (<= c_ULTIMATE.start_main_p1 v_idx_340) (= (select |c_#memory_int| v_idx_340) v_v_1508_4)) (<= .cse6 c_ULTIMATE.start_main_p2) (<= .cse7 v_b_120_4) (or (<= v_b_121_4 v_idx_345) (= 0 (select |c_#memory_int| v_idx_345)) (< v_idx_345 v_b_120_4)) (<= .cse8 v_b_121_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_121_4)))))) is different from false [2019-01-11 11:44:16,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:44:16,533 INFO L93 Difference]: Finished difference Result 12 states and 22 transitions. [2019-01-11 11:44:16,533 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-11 11:44:16,533 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-11 11:44:16,533 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:44:16,533 INFO L225 Difference]: With dead ends: 12 [2019-01-11 11:44:16,533 INFO L226 Difference]: Without dead ends: 11 [2019-01-11 11:44:16,534 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 9.8s TimeCoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-11 11:44:16,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2019-01-11 11:44:16,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2019-01-11 11:44:16,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11 states. [2019-01-11 11:44:16,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 21 transitions. [2019-01-11 11:44:16,543 INFO L78 Accepts]: Start accepts. Automaton has 11 states and 21 transitions. Word has length 4 [2019-01-11 11:44:16,543 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:44:16,543 INFO L480 AbstractCegarLoop]: Abstraction has 11 states and 21 transitions. [2019-01-11 11:44:16,544 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-11 11:44:16,544 INFO L276 IsEmpty]: Start isEmpty. Operand 11 states and 21 transitions. [2019-01-11 11:44:16,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:44:16,544 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:44:16,544 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1] [2019-01-11 11:44:16,545 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:44:16,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:16,545 INFO L82 PathProgramCache]: Analyzing trace with hash 929488, now seen corresponding path program 2 times [2019-01-11 11:44:16,545 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:44:16,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:16,546 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:44:16,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:16,546 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:44:16,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:44:16,622 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:44:16,622 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:44:16,622 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:44:16,623 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:44:16,624 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:44:16,624 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:44:16,625 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:44:16,635 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-11 11:44:16,635 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-11 11:44:16,645 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-11 11:44:16,645 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:44:16,651 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:44:16,698 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-11 11:44:16,725 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:16,727 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-11 11:44:16,733 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:16,735 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:16,736 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-11 11:44:16,737 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-11 11:44:16,757 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:44:16,771 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:44:16,785 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:44:16,786 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:19, output treesize:22 [2019-01-11 11:44:16,950 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:16,967 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:16,969 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:16,971 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:16,973 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 28 [2019-01-11 11:44:16,973 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:44:16,995 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:44:16,996 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-11 11:44:17,151 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:17,176 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:17,201 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:17,226 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:17,251 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:17,264 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:17,264 INFO L303 Elim1Store]: Index analysis took 141 ms [2019-01-11 11:44:17,265 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 40 [2019-01-11 11:44:17,266 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:44:17,348 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:44:17,348 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-11 11:44:17,365 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:44:17,366 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:44:17,375 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:44:17,394 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-01-11 11:44:17,395 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3, 3] total 7 [2019-01-11 11:44:17,395 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:44:17,395 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-11 11:44:17,395 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-11 11:44:17,395 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=41, Unknown=0, NotChecked=0, Total=72 [2019-01-11 11:44:17,396 INFO L87 Difference]: Start difference. First operand 11 states and 21 transitions. Second operand 5 states. [2019-01-11 11:44:17,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:44:17,637 INFO L93 Difference]: Finished difference Result 18 states and 40 transitions. [2019-01-11 11:44:17,638 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-11 11:44:17,638 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-11 11:44:17,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:44:17,639 INFO L225 Difference]: With dead ends: 18 [2019-01-11 11:44:17,639 INFO L226 Difference]: Without dead ends: 17 [2019-01-11 11:44:17,640 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=31, Invalid=41, Unknown=0, NotChecked=0, Total=72 [2019-01-11 11:44:17,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2019-01-11 11:44:17,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 14. [2019-01-11 11:44:17,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2019-01-11 11:44:17,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 35 transitions. [2019-01-11 11:44:17,651 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 35 transitions. Word has length 4 [2019-01-11 11:44:17,651 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:44:17,651 INFO L480 AbstractCegarLoop]: Abstraction has 14 states and 35 transitions. [2019-01-11 11:44:17,652 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-11 11:44:17,652 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 35 transitions. [2019-01-11 11:44:17,652 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:44:17,652 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:44:17,652 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-11 11:44:17,653 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:44:17,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:17,653 INFO L82 PathProgramCache]: Analyzing trace with hash 929612, now seen corresponding path program 1 times [2019-01-11 11:44:17,653 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:44:17,654 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:17,654 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:44:17,654 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:17,654 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:44:17,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:44:17,924 WARN L181 SmtUtils]: Spent 226.00 ms on a formula simplification. DAG size of input: 17 DAG size of output: 9 [2019-01-11 11:44:17,971 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:44:17,971 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:44:17,971 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:44:17,972 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-11 11:44:17,972 INFO L207 CegarAbsIntRunner]: [0], [6], [10], [15] [2019-01-11 11:44:17,974 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:44:17,974 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:44:28,342 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:44:28,342 INFO L272 AbstractInterpreter]: Visited 4 different actions 31 times. Merged at 2 different actions 9 times. Widened at 2 different actions 5 times. Found 11 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-11 11:44:28,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:28,343 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:44:28,645 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 61.9% of their original sizes. [2019-01-11 11:44:28,645 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:44:31,135 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_465 Int) (v_idx_466 Int) (v_idx_460 Int) (v_idx_463 Int) (v_idx_464 Int) (v_idx_461 Int) (v_idx_462 Int)) (exists ((v_v_3679_1 Int) (v_v_3678_1 Int) (v_b_299_1 Int) (v_b_298_1 Int) (v_v_3675_1 Int) (v_v_3681_1 Int) (v_v_3677_1 Int) (v_v_3676_1 Int)) (let ((.cse1 (+ v_b_298_1 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_v_3678_1 v_v_3676_1) (<= 0 (* 2 v_v_3676_1)) (or (= (select |c_#memory_int| v_idx_461) v_v_3676_1) (< v_idx_461 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_461)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_298_1) (<= v_b_299_1 .cse1) (or (< v_idx_466 v_b_299_1) (= (select |c_#memory_int| v_idx_466) v_v_3681_1)) (<= 0 v_v_3676_1) (or (< v_idx_463 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_463) v_v_3678_1) (<= .cse2 v_idx_463)) (<= .cse1 v_b_299_1) (<= .cse2 v_b_298_1) (or (<= v_b_298_1 v_idx_464) (< v_idx_464 .cse2) (= (select |c_#memory_int| v_idx_464) v_v_3679_1)) (or (<= v_b_299_1 v_idx_465) (= (select |c_#memory_int| v_idx_465) 0) (< v_idx_465 v_b_298_1)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_299_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_299_1) (<= (* 2 v_v_3678_1) 0) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_v_3678_1 0) (or (<= c_ULTIMATE.start_main_p2 v_idx_462) (< v_idx_462 .cse0) (= (select |c_#memory_int| v_idx_462) v_v_3677_1)) (or (= (select |c_#memory_int| v_idx_460) v_v_3675_1) (<= c_ULTIMATE.start_main_p1 v_idx_460)))))) is different from false [2019-01-11 11:44:33,412 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_467 Int) (v_idx_468 Int) (v_idx_469 Int) (v_idx_470 Int) (v_idx_471 Int) (v_idx_472 Int) (v_idx_473 Int)) (exists ((v_v_3679_1 Int) (v_v_3678_1 Int) (v_b_299_1 Int) (v_b_298_1 Int) (v_v_3675_1 Int) (v_v_3677_1 Int) (v_v_3681_1 Int) (v_v_3676_1 Int)) (let ((.cse2 (+ v_b_298_1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_467) (= (select |c_#memory_int| v_idx_467) v_v_3675_1)) (<= v_v_3678_1 v_v_3676_1) (<= 0 (* 2 v_v_3676_1)) (or (< v_idx_470 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_470) v_v_3678_1) (<= .cse0 v_idx_470)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_298_1) (or (< v_idx_472 v_b_298_1) (<= v_b_299_1 v_idx_472) (= (select |c_#memory_int| v_idx_472) 0)) (or (<= c_ULTIMATE.start_main_p2 v_idx_469) (= (select |c_#memory_int| v_idx_469) v_v_3677_1) (< v_idx_469 .cse1)) (<= v_b_299_1 .cse2) (or (= (select |c_#memory_int| v_idx_471) v_v_3679_1) (<= v_b_298_1 v_idx_471) (< v_idx_471 .cse0)) (<= 0 v_v_3676_1) (<= .cse2 v_b_299_1) (or (= (select |c_#memory_int| v_idx_473) v_v_3681_1) (< v_idx_473 v_b_299_1)) (<= .cse0 v_b_298_1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_299_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_299_1) (<= (* 2 v_v_3678_1) 0) (<= .cse1 c_ULTIMATE.start_main_p2) (<= v_v_3678_1 0) (or (= (select |c_#memory_int| v_idx_468) v_v_3676_1) (< v_idx_468 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_468)))))) is different from false [2019-01-11 11:44:36,095 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_478 Int) (v_idx_479 Int) (v_idx_476 Int) (v_idx_477 Int) (v_idx_480 Int) (v_idx_474 Int) (v_idx_475 Int)) (exists ((v_b_296_1 Int) (v_v_3679_1 Int) (v_v_3678_1 Int) (v_b_299_1 Int) (v_b_298_1 Int) (v_b_297_1 Int) (v_v_3675_1 Int) (v_v_3681_1 Int) (v_v_3677_1 Int) (v_v_3676_1 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse0 (+ v_b_296_1 1)) (.cse2 (+ v_b_298_1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_v_3678_1 v_v_3676_1) (<= 0 (* 2 v_v_3676_1)) (<= .cse0 v_b_297_1) (<= v_b_297_1 .cse0) (<= .cse1 v_b_298_1) (<= (+ v_b_296_1 2) v_b_299_1) (or (< v_idx_480 v_b_299_1) (= (select |c_#memory_int| v_idx_480) v_v_3681_1)) (<= v_b_299_1 .cse2) (<= .cse1 v_b_297_1) (<= (+ v_b_297_1 1) v_b_299_1) (<= 0 v_v_3676_1) (<= .cse3 v_b_296_1) (<= .cse0 v_b_298_1) (or (= (select |c_#memory_int| v_idx_474) v_v_3675_1) (<= c_ULTIMATE.start_main_p1 v_idx_474)) (or (= (select |c_#memory_int| v_idx_479) 0) (< v_idx_479 v_b_298_1) (<= v_b_299_1 v_idx_479)) (<= .cse2 v_b_299_1) (<= v_b_297_1 v_b_298_1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_299_1) (or (= (select |c_#memory_int| v_idx_478) v_v_3679_1) (<= v_b_298_1 v_idx_478) (< v_idx_478 v_b_297_1)) (or (= (select |c_#memory_int| v_idx_475) v_v_3676_1) (<= .cse3 v_idx_475) (< v_idx_475 c_ULTIMATE.start_main_p1)) (or (< v_idx_476 .cse3) (<= v_b_296_1 v_idx_476) (= (select |c_#memory_int| v_idx_476) v_v_3677_1)) (<= (* 2 v_v_3678_1) 0) (<= v_v_3678_1 0) (or (<= v_b_297_1 v_idx_477) (= (select |c_#memory_int| v_idx_477) v_v_3678_1) (< v_idx_477 v_b_296_1)))))) is different from false [2019-01-11 11:44:36,158 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-11 11:44:36,159 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:44:36,159 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:44:36,159 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 6 [2019-01-11 11:44:36,159 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:44:36,159 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-11 11:44:36,159 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-11 11:44:36,160 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:44:36,160 INFO L87 Difference]: Start difference. First operand 14 states and 35 transitions. Second operand 5 states. [2019-01-11 11:44:38,700 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_478 Int) (v_idx_479 Int) (v_idx_476 Int) (v_idx_477 Int) (v_idx_480 Int) (v_idx_474 Int) (v_idx_475 Int)) (exists ((v_b_296_1 Int) (v_v_3679_1 Int) (v_v_3678_1 Int) (v_b_299_1 Int) (v_b_298_1 Int) (v_b_297_1 Int) (v_v_3675_1 Int) (v_v_3681_1 Int) (v_v_3677_1 Int) (v_v_3676_1 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse0 (+ v_b_296_1 1)) (.cse2 (+ v_b_298_1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_v_3678_1 v_v_3676_1) (<= 0 (* 2 v_v_3676_1)) (<= .cse0 v_b_297_1) (<= v_b_297_1 .cse0) (<= .cse1 v_b_298_1) (<= (+ v_b_296_1 2) v_b_299_1) (or (< v_idx_480 v_b_299_1) (= (select |c_#memory_int| v_idx_480) v_v_3681_1)) (<= v_b_299_1 .cse2) (<= .cse1 v_b_297_1) (<= (+ v_b_297_1 1) v_b_299_1) (<= 0 v_v_3676_1) (<= .cse3 v_b_296_1) (<= .cse0 v_b_298_1) (or (= (select |c_#memory_int| v_idx_474) v_v_3675_1) (<= c_ULTIMATE.start_main_p1 v_idx_474)) (or (= (select |c_#memory_int| v_idx_479) 0) (< v_idx_479 v_b_298_1) (<= v_b_299_1 v_idx_479)) (<= .cse2 v_b_299_1) (<= v_b_297_1 v_b_298_1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_299_1) (or (= (select |c_#memory_int| v_idx_478) v_v_3679_1) (<= v_b_298_1 v_idx_478) (< v_idx_478 v_b_297_1)) (or (= (select |c_#memory_int| v_idx_475) v_v_3676_1) (<= .cse3 v_idx_475) (< v_idx_475 c_ULTIMATE.start_main_p1)) (or (< v_idx_476 .cse3) (<= v_b_296_1 v_idx_476) (= (select |c_#memory_int| v_idx_476) v_v_3677_1)) (<= (* 2 v_v_3678_1) 0) (<= v_v_3678_1 0) (or (<= v_b_297_1 v_idx_477) (= (select |c_#memory_int| v_idx_477) v_v_3678_1) (< v_idx_477 v_b_296_1)))))) (forall ((v_idx_467 Int) (v_idx_468 Int) (v_idx_469 Int) (v_idx_470 Int) (v_idx_471 Int) (v_idx_472 Int) (v_idx_473 Int)) (exists ((v_v_3679_1 Int) (v_v_3678_1 Int) (v_b_299_1 Int) (v_b_298_1 Int) (v_v_3675_1 Int) (v_v_3677_1 Int) (v_v_3681_1 Int) (v_v_3676_1 Int)) (let ((.cse6 (+ v_b_298_1 1)) (.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_467) (= (select |c_#memory_int| v_idx_467) v_v_3675_1)) (<= v_v_3678_1 v_v_3676_1) (<= 0 (* 2 v_v_3676_1)) (or (< v_idx_470 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_470) v_v_3678_1) (<= .cse4 v_idx_470)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_298_1) (or (< v_idx_472 v_b_298_1) (<= v_b_299_1 v_idx_472) (= (select |c_#memory_int| v_idx_472) 0)) (or (<= c_ULTIMATE.start_main_p2 v_idx_469) (= (select |c_#memory_int| v_idx_469) v_v_3677_1) (< v_idx_469 .cse5)) (<= v_b_299_1 .cse6) (or (= (select |c_#memory_int| v_idx_471) v_v_3679_1) (<= v_b_298_1 v_idx_471) (< v_idx_471 .cse4)) (<= 0 v_v_3676_1) (<= .cse6 v_b_299_1) (or (= (select |c_#memory_int| v_idx_473) v_v_3681_1) (< v_idx_473 v_b_299_1)) (<= .cse4 v_b_298_1) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_299_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_299_1) (<= (* 2 v_v_3678_1) 0) (<= .cse5 c_ULTIMATE.start_main_p2) (<= v_v_3678_1 0) (or (= (select |c_#memory_int| v_idx_468) v_v_3676_1) (< v_idx_468 c_ULTIMATE.start_main_p1) (<= .cse5 v_idx_468)))))) (forall ((v_idx_465 Int) (v_idx_466 Int) (v_idx_460 Int) (v_idx_463 Int) (v_idx_464 Int) (v_idx_461 Int) (v_idx_462 Int)) (exists ((v_v_3679_1 Int) (v_v_3678_1 Int) (v_b_299_1 Int) (v_b_298_1 Int) (v_v_3675_1 Int) (v_v_3681_1 Int) (v_v_3677_1 Int) (v_v_3676_1 Int)) (let ((.cse8 (+ v_b_298_1 1)) (.cse9 (+ c_ULTIMATE.start_main_p2 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_v_3678_1 v_v_3676_1) (<= 0 (* 2 v_v_3676_1)) (or (= (select |c_#memory_int| v_idx_461) v_v_3676_1) (< v_idx_461 c_ULTIMATE.start_main_p1) (<= .cse7 v_idx_461)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_298_1) (<= v_b_299_1 .cse8) (or (< v_idx_466 v_b_299_1) (= (select |c_#memory_int| v_idx_466) v_v_3681_1)) (<= 0 v_v_3676_1) (or (< v_idx_463 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_463) v_v_3678_1) (<= .cse9 v_idx_463)) (<= .cse8 v_b_299_1) (<= .cse9 v_b_298_1) (or (<= v_b_298_1 v_idx_464) (< v_idx_464 .cse9) (= (select |c_#memory_int| v_idx_464) v_v_3679_1)) (or (<= v_b_299_1 v_idx_465) (= (select |c_#memory_int| v_idx_465) 0) (< v_idx_465 v_b_298_1)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_299_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_299_1) (<= (* 2 v_v_3678_1) 0) (<= .cse7 c_ULTIMATE.start_main_p2) (<= v_v_3678_1 0) (or (<= c_ULTIMATE.start_main_p2 v_idx_462) (< v_idx_462 .cse7) (= (select |c_#memory_int| v_idx_462) v_v_3677_1)) (or (= (select |c_#memory_int| v_idx_460) v_v_3675_1) (<= c_ULTIMATE.start_main_p1 v_idx_460))))))) is different from false [2019-01-11 11:45:05,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:45:05,736 INFO L93 Difference]: Finished difference Result 16 states and 40 transitions. [2019-01-11 11:45:05,737 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-11 11:45:05,737 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-11 11:45:05,737 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:45:05,737 INFO L225 Difference]: With dead ends: 16 [2019-01-11 11:45:05,738 INFO L226 Difference]: Without dead ends: 15 [2019-01-11 11:45:05,738 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 9.9s TimeCoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-11 11:45:05,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states. [2019-01-11 11:45:05,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 14. [2019-01-11 11:45:05,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2019-01-11 11:45:05,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 35 transitions. [2019-01-11 11:45:05,748 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 35 transitions. Word has length 4 [2019-01-11 11:45:05,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:45:05,748 INFO L480 AbstractCegarLoop]: Abstraction has 14 states and 35 transitions. [2019-01-11 11:45:05,748 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-11 11:45:05,748 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 35 transitions. [2019-01-11 11:45:05,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:45:05,749 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:45:05,749 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-11 11:45:05,750 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:45:05,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:05,750 INFO L82 PathProgramCache]: Analyzing trace with hash 933644, now seen corresponding path program 1 times [2019-01-11 11:45:05,750 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:45:05,751 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:05,751 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:45:05,751 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:05,751 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:45:05,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:45:05,779 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:45:05,779 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:45:05,779 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:45:05,780 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-11 11:45:05,780 INFO L207 CegarAbsIntRunner]: [0], [10], [16], [17] [2019-01-11 11:45:05,781 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:45:05,781 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:45:10,761 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:45:10,761 INFO L272 AbstractInterpreter]: Visited 4 different actions 16 times. Merged at 2 different actions 8 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:45:10,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:10,762 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:45:11,063 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 61.9% of their original sizes. [2019-01-11 11:45:11,063 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:45:13,532 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_586 Int) (v_idx_580 Int) (v_idx_581 Int) (v_idx_584 Int) (v_idx_585 Int) (v_idx_582 Int) (v_idx_583 Int)) (exists ((v_v_1559_6 Int) (v_b_130_6 Int) (v_v_1555_6 Int) (v_v_1557_6 Int) (v_b_131_6 Int) (v_v_1556_6 Int) (v_v_1553_6 Int)) (let ((.cse2 (+ v_b_130_6 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_586 v_b_131_6) (= (select |c_#memory_int| v_idx_586) v_v_1559_6)) (or (< v_idx_581 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_581) (= (select |c_#memory_int| v_idx_581) 0)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_6) (<= .cse1 v_b_130_6) (or (< v_idx_583 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_583) (= (select |c_#memory_int| v_idx_583) v_v_1556_6)) (<= (* 2 v_v_1556_6) 0) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_6) (<= v_b_131_6 .cse2) (<= .cse2 v_b_131_6) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_6) (or (< v_idx_584 .cse1) (= (select |c_#memory_int| v_idx_584) v_v_1557_6) (<= v_b_130_6 v_idx_584)) (or (<= v_b_131_6 v_idx_585) (= (select |c_#memory_int| v_idx_585) 0) (< v_idx_585 v_b_130_6)) (or (= (select |c_#memory_int| v_idx_580) v_v_1553_6) (<= c_ULTIMATE.start_main_p1 v_idx_580)) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_v_1556_6 0) (or (= (select |c_#memory_int| v_idx_582) v_v_1555_6) (< v_idx_582 .cse0) (<= c_ULTIMATE.start_main_p2 v_idx_582)))))) is different from false [2019-01-11 11:45:15,819 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_588 Int) (v_idx_589 Int) (v_idx_587 Int) (v_idx_591 Int) (v_idx_592 Int) (v_idx_590 Int) (v_idx_593 Int)) (exists ((v_v_1559_6 Int) (v_b_130_6 Int) (v_v_1555_6 Int) (v_b_131_6 Int) (v_v_1557_6 Int) (v_v_1556_6 Int) (v_v_1553_6 Int)) (let ((.cse2 (+ v_b_130_6 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_587) (= (select |c_#memory_int| v_idx_587) v_v_1553_6)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_6) (<= .cse0 v_b_130_6) (or (< v_idx_588 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_588) (= (select |c_#memory_int| v_idx_588) 0)) (<= (* 2 v_v_1556_6) 0) (or (= (select |c_#memory_int| v_idx_589) v_v_1555_6) (< v_idx_589 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_589)) (or (< v_idx_592 v_b_130_6) (= 0 (select |c_#memory_int| v_idx_592)) (<= v_b_131_6 v_idx_592)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_6) (<= v_b_131_6 .cse2) (<= .cse2 v_b_131_6) (or (< v_idx_593 v_b_131_6) (= (select |c_#memory_int| v_idx_593) v_v_1559_6)) (or (< v_idx_591 .cse0) (<= v_b_130_6 v_idx_591) (= (select |c_#memory_int| v_idx_591) v_v_1557_6)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_6) (<= .cse1 c_ULTIMATE.start_main_p2) (or (< v_idx_590 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_590) (= (select |c_#memory_int| v_idx_590) v_v_1556_6)) (<= v_v_1556_6 0))))) is different from false [2019-01-11 11:45:17,984 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_599 Int) (v_idx_600 Int) (v_idx_597 Int) (v_idx_598 Int) (v_idx_595 Int) (v_idx_596 Int) (v_idx_594 Int)) (exists ((v_v_1559_6 Int) (v_b_130_6 Int) (v_v_1555_6 Int) (v_b_127_6 Int) (v_v_1557_6 Int) (v_b_131_6 Int) (v_v_1556_6 Int) (v_b_138_6 Int) (v_v_1553_6 Int)) (let ((.cse2 (+ v_b_130_6 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_138_6 1))) (and (<= (+ v_b_138_6 2) v_b_130_6) (or (< v_idx_595 v_b_138_6) (<= v_b_127_6 v_idx_595) (= (select |c_#memory_int| v_idx_595) 0)) (or (< v_idx_596 v_b_127_6) (= (select |c_#memory_int| v_idx_596) v_v_1555_6) (<= c_ULTIMATE.start_main_p2 v_idx_596)) (<= .cse0 v_b_127_6) (<= .cse1 v_b_130_6) (or (<= v_b_130_6 v_idx_598) (= (select |c_#memory_int| v_idx_598) v_v_1557_6) (< v_idx_598 .cse1)) (<= (* 2 v_v_1556_6) 0) (<= v_b_131_6 .cse2) (<= .cse2 v_b_131_6) (<= (+ v_b_138_6 3) v_b_131_6) (or (= (select |c_#memory_int| v_idx_594) v_v_1553_6) (<= v_b_138_6 v_idx_594)) (or (= (select |c_#memory_int| v_idx_597) v_v_1556_6) (< v_idx_597 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_597)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_6) (or (= (select |c_#memory_int| v_idx_599) 0) (< v_idx_599 v_b_130_6) (<= v_b_131_6 v_idx_599)) (<= (+ v_b_127_6 1) v_b_130_6) (<= (+ v_b_127_6 2) v_b_131_6) (<= v_b_127_6 c_ULTIMATE.start_main_p2) (or (< v_idx_600 v_b_131_6) (= (select |c_#memory_int| v_idx_600) v_v_1559_6)) (<= v_b_127_6 .cse0) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_v_1556_6 0))))) is different from false [2019-01-11 11:45:19,298 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-11 11:45:19,298 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:45:19,298 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:45:19,298 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [2] total 5 [2019-01-11 11:45:19,298 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:45:19,298 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-11 11:45:19,299 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-11 11:45:19,299 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:45:19,299 INFO L87 Difference]: Start difference. First operand 14 states and 35 transitions. Second operand 5 states. [2019-01-11 11:45:21,710 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_599 Int) (v_idx_600 Int) (v_idx_597 Int) (v_idx_598 Int) (v_idx_595 Int) (v_idx_596 Int) (v_idx_594 Int)) (exists ((v_v_1559_6 Int) (v_b_130_6 Int) (v_v_1555_6 Int) (v_b_127_6 Int) (v_v_1557_6 Int) (v_b_131_6 Int) (v_v_1556_6 Int) (v_b_138_6 Int) (v_v_1553_6 Int)) (let ((.cse2 (+ v_b_130_6 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_138_6 1))) (and (<= (+ v_b_138_6 2) v_b_130_6) (or (< v_idx_595 v_b_138_6) (<= v_b_127_6 v_idx_595) (= (select |c_#memory_int| v_idx_595) 0)) (or (< v_idx_596 v_b_127_6) (= (select |c_#memory_int| v_idx_596) v_v_1555_6) (<= c_ULTIMATE.start_main_p2 v_idx_596)) (<= .cse0 v_b_127_6) (<= .cse1 v_b_130_6) (or (<= v_b_130_6 v_idx_598) (= (select |c_#memory_int| v_idx_598) v_v_1557_6) (< v_idx_598 .cse1)) (<= (* 2 v_v_1556_6) 0) (<= v_b_131_6 .cse2) (<= .cse2 v_b_131_6) (<= (+ v_b_138_6 3) v_b_131_6) (or (= (select |c_#memory_int| v_idx_594) v_v_1553_6) (<= v_b_138_6 v_idx_594)) (or (= (select |c_#memory_int| v_idx_597) v_v_1556_6) (< v_idx_597 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_597)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_6) (or (= (select |c_#memory_int| v_idx_599) 0) (< v_idx_599 v_b_130_6) (<= v_b_131_6 v_idx_599)) (<= (+ v_b_127_6 1) v_b_130_6) (<= (+ v_b_127_6 2) v_b_131_6) (<= v_b_127_6 c_ULTIMATE.start_main_p2) (or (< v_idx_600 v_b_131_6) (= (select |c_#memory_int| v_idx_600) v_v_1559_6)) (<= v_b_127_6 .cse0) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_v_1556_6 0))))) (forall ((v_idx_588 Int) (v_idx_589 Int) (v_idx_587 Int) (v_idx_591 Int) (v_idx_592 Int) (v_idx_590 Int) (v_idx_593 Int)) (exists ((v_v_1559_6 Int) (v_b_130_6 Int) (v_v_1555_6 Int) (v_b_131_6 Int) (v_v_1557_6 Int) (v_v_1556_6 Int) (v_v_1553_6 Int)) (let ((.cse5 (+ v_b_130_6 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ c_ULTIMATE.start_main_p2 1))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_587) (= (select |c_#memory_int| v_idx_587) v_v_1553_6)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_6) (<= .cse3 v_b_130_6) (or (< v_idx_588 c_ULTIMATE.start_main_p1) (<= .cse4 v_idx_588) (= (select |c_#memory_int| v_idx_588) 0)) (<= (* 2 v_v_1556_6) 0) (or (= (select |c_#memory_int| v_idx_589) v_v_1555_6) (< v_idx_589 .cse4) (<= c_ULTIMATE.start_main_p2 v_idx_589)) (or (< v_idx_592 v_b_130_6) (= 0 (select |c_#memory_int| v_idx_592)) (<= v_b_131_6 v_idx_592)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_6) (<= v_b_131_6 .cse5) (<= .cse5 v_b_131_6) (or (< v_idx_593 v_b_131_6) (= (select |c_#memory_int| v_idx_593) v_v_1559_6)) (or (< v_idx_591 .cse3) (<= v_b_130_6 v_idx_591) (= (select |c_#memory_int| v_idx_591) v_v_1557_6)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_6) (<= .cse4 c_ULTIMATE.start_main_p2) (or (< v_idx_590 c_ULTIMATE.start_main_p2) (<= .cse3 v_idx_590) (= (select |c_#memory_int| v_idx_590) v_v_1556_6)) (<= v_v_1556_6 0))))) (forall ((v_idx_586 Int) (v_idx_580 Int) (v_idx_581 Int) (v_idx_584 Int) (v_idx_585 Int) (v_idx_582 Int) (v_idx_583 Int)) (exists ((v_v_1559_6 Int) (v_b_130_6 Int) (v_v_1555_6 Int) (v_v_1557_6 Int) (v_b_131_6 Int) (v_v_1556_6 Int) (v_v_1553_6 Int)) (let ((.cse8 (+ v_b_130_6 1)) (.cse7 (+ c_ULTIMATE.start_main_p2 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_586 v_b_131_6) (= (select |c_#memory_int| v_idx_586) v_v_1559_6)) (or (< v_idx_581 c_ULTIMATE.start_main_p1) (<= .cse6 v_idx_581) (= (select |c_#memory_int| v_idx_581) 0)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_130_6) (<= .cse7 v_b_130_6) (or (< v_idx_583 c_ULTIMATE.start_main_p2) (<= .cse7 v_idx_583) (= (select |c_#memory_int| v_idx_583) v_v_1556_6)) (<= (* 2 v_v_1556_6) 0) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_131_6) (<= v_b_131_6 .cse8) (<= .cse8 v_b_131_6) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_131_6) (or (< v_idx_584 .cse7) (= (select |c_#memory_int| v_idx_584) v_v_1557_6) (<= v_b_130_6 v_idx_584)) (or (<= v_b_131_6 v_idx_585) (= (select |c_#memory_int| v_idx_585) 0) (< v_idx_585 v_b_130_6)) (or (= (select |c_#memory_int| v_idx_580) v_v_1553_6) (<= c_ULTIMATE.start_main_p1 v_idx_580)) (<= .cse6 c_ULTIMATE.start_main_p2) (<= v_v_1556_6 0) (or (= (select |c_#memory_int| v_idx_582) v_v_1555_6) (< v_idx_582 .cse6) (<= c_ULTIMATE.start_main_p2 v_idx_582))))))) is different from false [2019-01-11 11:45:38,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:45:38,307 INFO L93 Difference]: Finished difference Result 17 states and 41 transitions. [2019-01-11 11:45:38,307 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-11 11:45:38,307 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-11 11:45:38,309 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:45:38,309 INFO L225 Difference]: With dead ends: 17 [2019-01-11 11:45:38,309 INFO L226 Difference]: Without dead ends: 16 [2019-01-11 11:45:38,310 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 10.6s TimeCoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-11 11:45:38,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-11 11:45:38,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2019-01-11 11:45:38,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-11 11:45:38,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 39 transitions. [2019-01-11 11:45:38,321 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 39 transitions. Word has length 4 [2019-01-11 11:45:38,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:45:38,321 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 39 transitions. [2019-01-11 11:45:38,321 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-11 11:45:38,322 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 39 transitions. [2019-01-11 11:45:38,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:45:38,322 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:45:38,322 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1] [2019-01-11 11:45:38,322 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:45:38,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:38,323 INFO L82 PathProgramCache]: Analyzing trace with hash 933456, now seen corresponding path program 2 times [2019-01-11 11:45:38,323 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:45:38,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:38,324 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:45:38,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:38,324 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:45:38,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:45:38,391 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-11 11:45:38,391 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:45:38,391 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:45:38,392 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:45:38,392 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:45:38,392 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:45:38,392 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:45:38,401 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-11 11:45:38,401 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-11 11:45:38,410 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-11 11:45:38,410 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:45:38,411 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:45:38,414 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-11 11:45:38,419 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:38,420 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-11 11:45:38,438 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:38,440 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:38,441 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-11 11:45:38,442 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-11 11:45:38,460 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:45:38,469 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:45:38,487 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:45:38,487 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:19, output treesize:22 [2019-01-11 11:45:38,520 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:38,522 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:38,523 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:38,523 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:38,524 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-11 11:45:38,525 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:45:38,560 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:45:38,560 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-11 11:45:38,581 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:38,582 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:38,585 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:38,586 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:38,587 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:38,588 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:38,589 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 40 [2019-01-11 11:45:38,589 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:45:38,621 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:45:38,622 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:22 [2019-01-11 11:45:38,654 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:45:38,655 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:45:38,700 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:45:38,719 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-11 11:45:38,720 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 3, 3] total 8 [2019-01-11 11:45:38,720 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-11 11:45:38,720 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-01-11 11:45:38,720 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-01-11 11:45:38,720 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=53, Unknown=0, NotChecked=0, Total=90 [2019-01-11 11:45:38,721 INFO L87 Difference]: Start difference. First operand 15 states and 39 transitions. Second operand 7 states. [2019-01-11 11:45:39,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:45:39,038 INFO L93 Difference]: Finished difference Result 29 states and 57 transitions. [2019-01-11 11:45:39,040 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-11 11:45:39,040 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 4 [2019-01-11 11:45:39,040 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:45:39,041 INFO L225 Difference]: With dead ends: 29 [2019-01-11 11:45:39,041 INFO L226 Difference]: Without dead ends: 28 [2019-01-11 11:45:39,043 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-01-11 11:45:39,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2019-01-11 11:45:39,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 17. [2019-01-11 11:45:39,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2019-01-11 11:45:39,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 47 transitions. [2019-01-11 11:45:39,063 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 47 transitions. Word has length 4 [2019-01-11 11:45:39,063 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:45:39,063 INFO L480 AbstractCegarLoop]: Abstraction has 17 states and 47 transitions. [2019-01-11 11:45:39,064 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-01-11 11:45:39,064 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 47 transitions. [2019-01-11 11:45:39,064 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:45:39,064 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:45:39,064 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-11 11:45:39,065 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:45:39,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:39,065 INFO L82 PathProgramCache]: Analyzing trace with hash 933518, now seen corresponding path program 1 times [2019-01-11 11:45:39,065 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:45:39,066 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:39,066 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:45:39,066 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:39,066 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:45:39,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:45:39,192 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:45:39,192 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:45:39,192 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:45:39,193 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-11 11:45:39,193 INFO L207 CegarAbsIntRunner]: [0], [10], [12], [15] [2019-01-11 11:45:39,194 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:45:39,194 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:45:47,725 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:45:47,725 INFO L272 AbstractInterpreter]: Visited 4 different actions 28 times. Merged at 2 different actions 8 times. Widened at 2 different actions 4 times. Found 10 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-11 11:45:47,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:47,726 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:45:48,032 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 57.14% of their original sizes. [2019-01-11 11:45:48,032 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:45:50,464 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_702 Int) (v_idx_703 Int) (v_idx_700 Int) (v_idx_701 Int) (v_idx_706 Int) (v_idx_704 Int) (v_idx_705 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_v_3066_2 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_v_3062_2 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_3067_2)) (or (<= .cse0 v_idx_703) (= (select |c_#memory_int| v_idx_703) v_v_3065_2) (< v_idx_703 c_ULTIMATE.start_main_p2)) (<= (* 2 v_v_3065_2) 0) (<= v_v_3065_2 v_v_3067_2) (<= 0 v_v_3067_2) (<= .cse0 c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p3 v_idx_704) (= (select |c_#memory_int| v_idx_704) v_v_3066_2) (< v_idx_704 .cse0)) (or (<= c_ULTIMATE.start_main_p1 v_idx_700) (= (select |c_#memory_int| v_idx_700) v_v_3062_2)) (or (= (select |c_#memory_int| v_idx_701) 0) (<= .cse1 v_idx_701) (< v_idx_701 c_ULTIMATE.start_main_p1)) (or (= (select |c_#memory_int| v_idx_706) v_v_3068_2) (< v_idx_706 .cse2)) (<= .cse1 c_ULTIMATE.start_main_p2) (or (< v_idx_702 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_702) (= (select |c_#memory_int| v_idx_702) v_v_3064_2)) (or (< v_idx_705 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_705) v_v_3067_2) (<= .cse2 v_idx_705)) (<= v_v_3065_2 0))))) is different from false [2019-01-11 11:45:53,113 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_710 Int) (v_idx_713 Int) (v_idx_711 Int) (v_idx_712 Int) (v_idx_707 Int) (v_idx_708 Int) (v_idx_709 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_b_254_3 Int) (v_v_3066_2 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_b_255_3 Int) (v_v_3062_2 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse3 (+ v_b_254_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= .cse0 v_b_254_3) (<= .cse1 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_3067_2)) (or (= (select |c_#memory_int| v_idx_712) v_v_3067_2) (<= .cse2 v_idx_712) (< v_idx_712 c_ULTIMATE.start_main_p3)) (<= .cse1 v_b_255_3) (or (= (select |c_#memory_int| v_idx_713) v_v_3068_2) (< v_idx_713 .cse2)) (<= (* 2 v_v_3065_2) 0) (or (<= v_b_255_3 v_idx_710) (< v_idx_710 v_b_254_3) (= (select |c_#memory_int| v_idx_710) v_v_3065_2)) (<= v_v_3065_2 v_v_3067_2) (or (= (select |c_#memory_int| v_idx_708) 0) (<= .cse0 v_idx_708) (< v_idx_708 c_ULTIMATE.start_main_p1)) (<= 0 v_v_3067_2) (or (< v_idx_711 v_b_255_3) (= (select |c_#memory_int| v_idx_711) v_v_3066_2) (<= c_ULTIMATE.start_main_p3 v_idx_711)) (or (= (select |c_#memory_int| v_idx_707) v_v_3062_2) (<= c_ULTIMATE.start_main_p1 v_idx_707)) (<= v_b_255_3 c_ULTIMATE.start_main_p3) (<= .cse3 v_b_255_3) (<= v_b_255_3 .cse3) (<= v_v_3065_2 0) (<= .cse3 c_ULTIMATE.start_main_p3) (or (<= v_b_254_3 v_idx_709) (= (select |c_#memory_int| v_idx_709) v_v_3064_2) (< v_idx_709 .cse0)))))) is different from false [2019-01-11 11:45:55,437 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_720 Int) (v_idx_714 Int) (v_idx_717 Int) (v_idx_718 Int) (v_idx_715 Int) (v_idx_716 Int) (v_idx_719 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_v_3066_2 Int) (v_b_254_3 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_b_256_3 Int) (v_b_255_3 Int) (v_v_3062_2 Int) (v_b_257_3 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ v_b_256_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ v_b_254_3 1))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_714) (= (select |c_#memory_int| v_idx_714) v_v_3062_2)) (<= .cse0 v_b_256_3) (<= .cse1 v_b_254_3) (<= .cse2 v_b_257_3) (<= 0 (* 2 v_v_3067_2)) (<= .cse0 v_b_255_3) (or (< v_idx_718 v_b_255_3) (<= v_b_256_3 v_idx_718) (= (select |c_#memory_int| v_idx_718) v_v_3066_2)) (<= v_b_257_3 .cse2) (or (<= .cse1 v_idx_715) (< v_idx_715 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_715) 0)) (<= (* 2 v_v_3065_2) 0) (or (= (select |c_#memory_int| v_idx_719) v_v_3067_2) (<= v_b_257_3 v_idx_719) (< v_idx_719 v_b_256_3)) (<= v_v_3065_2 v_v_3067_2) (or (< v_idx_716 .cse1) (<= v_b_254_3 v_idx_716) (= (select |c_#memory_int| v_idx_716) v_v_3064_2)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_257_3) (or (< v_idx_717 v_b_254_3) (= (select |c_#memory_int| v_idx_717) v_v_3065_2) (<= v_b_255_3 v_idx_717)) (<= 0 v_v_3067_2) (or (< v_idx_720 v_b_257_3) (= (select |c_#memory_int| v_idx_720) v_v_3068_2)) (<= (+ v_b_255_3 1) v_b_257_3) (<= (+ v_b_254_3 2) v_b_257_3) (<= .cse3 v_b_256_3) (<= v_b_255_3 v_b_256_3) (<= .cse3 v_b_255_3) (<= v_b_255_3 .cse3) (<= v_v_3065_2 0))))) is different from false [2019-01-11 11:45:55,502 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-11 11:45:55,502 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:45:55,502 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:45:55,503 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 6 [2019-01-11 11:45:55,503 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:45:55,503 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-11 11:45:55,503 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-11 11:45:55,503 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:45:55,503 INFO L87 Difference]: Start difference. First operand 17 states and 47 transitions. Second operand 5 states. [2019-01-11 11:45:58,056 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_710 Int) (v_idx_713 Int) (v_idx_711 Int) (v_idx_712 Int) (v_idx_707 Int) (v_idx_708 Int) (v_idx_709 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_b_254_3 Int) (v_v_3066_2 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_b_255_3 Int) (v_v_3062_2 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse3 (+ v_b_254_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= .cse0 v_b_254_3) (<= .cse1 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_3067_2)) (or (= (select |c_#memory_int| v_idx_712) v_v_3067_2) (<= .cse2 v_idx_712) (< v_idx_712 c_ULTIMATE.start_main_p3)) (<= .cse1 v_b_255_3) (or (= (select |c_#memory_int| v_idx_713) v_v_3068_2) (< v_idx_713 .cse2)) (<= (* 2 v_v_3065_2) 0) (or (<= v_b_255_3 v_idx_710) (< v_idx_710 v_b_254_3) (= (select |c_#memory_int| v_idx_710) v_v_3065_2)) (<= v_v_3065_2 v_v_3067_2) (or (= (select |c_#memory_int| v_idx_708) 0) (<= .cse0 v_idx_708) (< v_idx_708 c_ULTIMATE.start_main_p1)) (<= 0 v_v_3067_2) (or (< v_idx_711 v_b_255_3) (= (select |c_#memory_int| v_idx_711) v_v_3066_2) (<= c_ULTIMATE.start_main_p3 v_idx_711)) (or (= (select |c_#memory_int| v_idx_707) v_v_3062_2) (<= c_ULTIMATE.start_main_p1 v_idx_707)) (<= v_b_255_3 c_ULTIMATE.start_main_p3) (<= .cse3 v_b_255_3) (<= v_b_255_3 .cse3) (<= v_v_3065_2 0) (<= .cse3 c_ULTIMATE.start_main_p3) (or (<= v_b_254_3 v_idx_709) (= (select |c_#memory_int| v_idx_709) v_v_3064_2) (< v_idx_709 .cse0)))))) (forall ((v_idx_702 Int) (v_idx_703 Int) (v_idx_700 Int) (v_idx_701 Int) (v_idx_706 Int) (v_idx_704 Int) (v_idx_705 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_v_3066_2 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_v_3062_2 Int)) (let ((.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse6 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_3067_2)) (or (<= .cse4 v_idx_703) (= (select |c_#memory_int| v_idx_703) v_v_3065_2) (< v_idx_703 c_ULTIMATE.start_main_p2)) (<= (* 2 v_v_3065_2) 0) (<= v_v_3065_2 v_v_3067_2) (<= 0 v_v_3067_2) (<= .cse4 c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p3 v_idx_704) (= (select |c_#memory_int| v_idx_704) v_v_3066_2) (< v_idx_704 .cse4)) (or (<= c_ULTIMATE.start_main_p1 v_idx_700) (= (select |c_#memory_int| v_idx_700) v_v_3062_2)) (or (= (select |c_#memory_int| v_idx_701) 0) (<= .cse5 v_idx_701) (< v_idx_701 c_ULTIMATE.start_main_p1)) (or (= (select |c_#memory_int| v_idx_706) v_v_3068_2) (< v_idx_706 .cse6)) (<= .cse5 c_ULTIMATE.start_main_p2) (or (< v_idx_702 .cse5) (<= c_ULTIMATE.start_main_p2 v_idx_702) (= (select |c_#memory_int| v_idx_702) v_v_3064_2)) (or (< v_idx_705 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_705) v_v_3067_2) (<= .cse6 v_idx_705)) (<= v_v_3065_2 0))))) (forall ((v_idx_720 Int) (v_idx_714 Int) (v_idx_717 Int) (v_idx_718 Int) (v_idx_715 Int) (v_idx_716 Int) (v_idx_719 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_v_3066_2 Int) (v_b_254_3 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_b_256_3 Int) (v_b_255_3 Int) (v_v_3062_2 Int) (v_b_257_3 Int)) (let ((.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse9 (+ v_b_256_3 1)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse10 (+ v_b_254_3 1))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_714) (= (select |c_#memory_int| v_idx_714) v_v_3062_2)) (<= .cse7 v_b_256_3) (<= .cse8 v_b_254_3) (<= .cse9 v_b_257_3) (<= 0 (* 2 v_v_3067_2)) (<= .cse7 v_b_255_3) (or (< v_idx_718 v_b_255_3) (<= v_b_256_3 v_idx_718) (= (select |c_#memory_int| v_idx_718) v_v_3066_2)) (<= v_b_257_3 .cse9) (or (<= .cse8 v_idx_715) (< v_idx_715 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_715) 0)) (<= (* 2 v_v_3065_2) 0) (or (= (select |c_#memory_int| v_idx_719) v_v_3067_2) (<= v_b_257_3 v_idx_719) (< v_idx_719 v_b_256_3)) (<= v_v_3065_2 v_v_3067_2) (or (< v_idx_716 .cse8) (<= v_b_254_3 v_idx_716) (= (select |c_#memory_int| v_idx_716) v_v_3064_2)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_257_3) (or (< v_idx_717 v_b_254_3) (= (select |c_#memory_int| v_idx_717) v_v_3065_2) (<= v_b_255_3 v_idx_717)) (<= 0 v_v_3067_2) (or (< v_idx_720 v_b_257_3) (= (select |c_#memory_int| v_idx_720) v_v_3068_2)) (<= (+ v_b_255_3 1) v_b_257_3) (<= (+ v_b_254_3 2) v_b_257_3) (<= .cse10 v_b_256_3) (<= v_b_255_3 v_b_256_3) (<= .cse10 v_b_255_3) (<= v_b_255_3 .cse10) (<= v_v_3065_2 0)))))) is different from false [2019-01-11 11:46:12,751 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_710 Int) (v_idx_713 Int) (v_idx_711 Int) (v_idx_712 Int) (v_idx_707 Int) (v_idx_708 Int) (v_idx_709 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_b_254_3 Int) (v_v_3066_2 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_b_255_3 Int) (v_v_3062_2 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse3 (+ v_b_254_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= .cse0 v_b_254_3) (<= .cse1 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_3067_2)) (or (= (select |c_#memory_int| v_idx_712) v_v_3067_2) (<= .cse2 v_idx_712) (< v_idx_712 c_ULTIMATE.start_main_p3)) (<= .cse1 v_b_255_3) (or (= (select |c_#memory_int| v_idx_713) v_v_3068_2) (< v_idx_713 .cse2)) (<= (* 2 v_v_3065_2) 0) (or (<= v_b_255_3 v_idx_710) (< v_idx_710 v_b_254_3) (= (select |c_#memory_int| v_idx_710) v_v_3065_2)) (<= v_v_3065_2 v_v_3067_2) (or (= (select |c_#memory_int| v_idx_708) 0) (<= .cse0 v_idx_708) (< v_idx_708 c_ULTIMATE.start_main_p1)) (<= 0 v_v_3067_2) (or (< v_idx_711 v_b_255_3) (= (select |c_#memory_int| v_idx_711) v_v_3066_2) (<= c_ULTIMATE.start_main_p3 v_idx_711)) (or (= (select |c_#memory_int| v_idx_707) v_v_3062_2) (<= c_ULTIMATE.start_main_p1 v_idx_707)) (<= v_b_255_3 c_ULTIMATE.start_main_p3) (<= .cse3 v_b_255_3) (<= v_b_255_3 .cse3) (<= v_v_3065_2 0) (<= .cse3 c_ULTIMATE.start_main_p3) (or (<= v_b_254_3 v_idx_709) (= (select |c_#memory_int| v_idx_709) v_v_3064_2) (< v_idx_709 .cse0)))))) (forall ((v_idx_720 Int) (v_idx_714 Int) (v_idx_717 Int) (v_idx_718 Int) (v_idx_715 Int) (v_idx_716 Int) (v_idx_719 Int)) (exists ((v_v_3064_2 Int) (v_v_3065_2 Int) (v_v_3066_2 Int) (v_b_254_3 Int) (v_v_3067_2 Int) (v_v_3068_2 Int) (v_b_256_3 Int) (v_b_255_3 Int) (v_v_3062_2 Int) (v_b_257_3 Int)) (let ((.cse4 (+ c_ULTIMATE.start_main_p1 2)) (.cse6 (+ v_b_256_3 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ v_b_254_3 1))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_714) (= (select |c_#memory_int| v_idx_714) v_v_3062_2)) (<= .cse4 v_b_256_3) (<= .cse5 v_b_254_3) (<= .cse6 v_b_257_3) (<= 0 (* 2 v_v_3067_2)) (<= .cse4 v_b_255_3) (or (< v_idx_718 v_b_255_3) (<= v_b_256_3 v_idx_718) (= (select |c_#memory_int| v_idx_718) v_v_3066_2)) (<= v_b_257_3 .cse6) (or (<= .cse5 v_idx_715) (< v_idx_715 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_715) 0)) (<= (* 2 v_v_3065_2) 0) (or (= (select |c_#memory_int| v_idx_719) v_v_3067_2) (<= v_b_257_3 v_idx_719) (< v_idx_719 v_b_256_3)) (<= v_v_3065_2 v_v_3067_2) (or (< v_idx_716 .cse5) (<= v_b_254_3 v_idx_716) (= (select |c_#memory_int| v_idx_716) v_v_3064_2)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_257_3) (or (< v_idx_717 v_b_254_3) (= (select |c_#memory_int| v_idx_717) v_v_3065_2) (<= v_b_255_3 v_idx_717)) (<= 0 v_v_3067_2) (or (< v_idx_720 v_b_257_3) (= (select |c_#memory_int| v_idx_720) v_v_3068_2)) (<= (+ v_b_255_3 1) v_b_257_3) (<= (+ v_b_254_3 2) v_b_257_3) (<= .cse7 v_b_256_3) (<= v_b_255_3 v_b_256_3) (<= .cse7 v_b_255_3) (<= v_b_255_3 .cse7) (<= v_v_3065_2 0)))))) is different from false [2019-01-11 11:46:18,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:46:18,295 INFO L93 Difference]: Finished difference Result 21 states and 57 transitions. [2019-01-11 11:46:18,295 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-11 11:46:18,295 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-11 11:46:18,295 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:46:18,296 INFO L225 Difference]: With dead ends: 21 [2019-01-11 11:46:18,296 INFO L226 Difference]: Without dead ends: 20 [2019-01-11 11:46:18,296 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.6s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-11 11:46:18,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-01-11 11:46:18,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 17. [2019-01-11 11:46:18,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2019-01-11 11:46:18,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 47 transitions. [2019-01-11 11:46:18,315 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 47 transitions. Word has length 4 [2019-01-11 11:46:18,315 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:46:18,315 INFO L480 AbstractCegarLoop]: Abstraction has 17 states and 47 transitions. [2019-01-11 11:46:18,315 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-11 11:46:18,315 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 47 transitions. [2019-01-11 11:46:18,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:46:18,316 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:46:18,316 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-11 11:46:18,316 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:46:18,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:46:18,317 INFO L82 PathProgramCache]: Analyzing trace with hash 935566, now seen corresponding path program 1 times [2019-01-11 11:46:18,317 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:46:18,318 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:46:18,318 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:46:18,318 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:46:18,318 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:46:18,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:46:18,412 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:46:18,413 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:46:18,413 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:46:18,413 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-11 11:46:18,413 INFO L207 CegarAbsIntRunner]: [0], [12], [16], [17] [2019-01-11 11:46:18,414 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:46:18,414 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:46:23,581 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:46:23,581 INFO L272 AbstractInterpreter]: Visited 4 different actions 16 times. Merged at 2 different actions 8 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:46:23,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:46:23,582 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:46:23,856 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 57.14% of their original sizes. [2019-01-11 11:46:23,856 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:46:26,238 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_820 Int) (v_idx_823 Int) (v_idx_824 Int) (v_idx_821 Int) (v_idx_822 Int) (v_idx_825 Int) (v_idx_826 Int)) (exists ((v_v_1752_7 Int) (v_v_1753_6 Int) (v_v_1750_8 Int) (v_v_1754_7 Int) (v_v_1748_8 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_823) 0) (<= .cse0 v_idx_823) (< v_idx_823 c_ULTIMATE.start_main_p2)) (or (= (select |c_#memory_int| v_idx_824) v_v_1752_7) (<= c_ULTIMATE.start_main_p3 v_idx_824) (< v_idx_824 .cse0)) (or (<= c_ULTIMATE.start_main_p2 v_idx_822) (< v_idx_822 .cse1) (= (select |c_#memory_int| v_idx_822) v_v_1750_8)) (or (= (select |c_#memory_int| v_idx_826) v_v_1754_7) (< v_idx_826 .cse2)) (<= 0 v_v_1753_6) (or (= (select |c_#memory_int| v_idx_820) v_v_1748_8) (<= c_ULTIMATE.start_main_p1 v_idx_820)) (or (< v_idx_821 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_821) (= (select |c_#memory_int| v_idx_821) 0)) (or (<= .cse2 v_idx_825) (< v_idx_825 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_825) v_v_1753_6)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= 0 (* 2 v_v_1753_6)) (<= .cse0 c_ULTIMATE.start_main_p3))))) is different from false [2019-01-11 11:46:28,875 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_830 Int) (v_idx_831 Int) (v_idx_832 Int) (v_idx_833 Int) (v_idx_827 Int) (v_idx_828 Int) (v_idx_829 Int)) (exists ((v_v_1752_7 Int) (v_v_1753_6 Int) (v_v_1750_8 Int) (v_v_1754_7 Int) (v_b_140_8 Int) (v_b_141_8 Int) (v_v_1748_8 Int)) (let ((.cse1 (+ v_b_140_8 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (or (<= .cse0 v_idx_830) (= (select |c_#memory_int| v_idx_830) 0) (< v_idx_830 c_ULTIMATE.start_main_p2)) (or (< v_idx_831 .cse0) (= (select |c_#memory_int| v_idx_831) v_v_1752_7) (<= v_b_140_8 v_idx_831)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_141_8) (<= 0 v_v_1753_6) (or (< v_idx_833 v_b_141_8) (= (select |c_#memory_int| v_idx_833) v_v_1754_7)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_140_8) (or (< v_idx_832 v_b_140_8) (= (select |c_#memory_int| v_idx_832) v_v_1753_6) (<= v_b_141_8 v_idx_832)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_141_8) (<= v_b_141_8 .cse1) (or (<= c_ULTIMATE.start_main_p1 v_idx_827) (= (select |c_#memory_int| v_idx_827) v_v_1748_8)) (or (< v_idx_828 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_828) (= (select |c_#memory_int| v_idx_828) 0)) (or (<= c_ULTIMATE.start_main_p2 v_idx_829) (= (select |c_#memory_int| v_idx_829) v_v_1750_8) (< v_idx_829 .cse2)) (<= .cse1 v_b_141_8) (<= .cse2 c_ULTIMATE.start_main_p2) (<= .cse0 v_b_140_8) (<= 0 (* 2 v_v_1753_6)))))) is different from false [2019-01-11 11:46:31,984 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_840 Int) (v_idx_834 Int) (v_idx_835 Int) (v_idx_838 Int) (v_idx_839 Int) (v_idx_836 Int) (v_idx_837 Int)) (exists ((v_b_137_8 Int) (v_b_148_8 Int) (v_v_1753_6 Int) (v_v_1752_7 Int) (v_v_1750_8 Int) (v_v_1754_7 Int) (v_b_140_8 Int) (v_b_141_8 Int) (v_v_1748_8 Int)) (let ((.cse0 (+ v_b_148_8 1)) (.cse2 (+ v_b_140_8 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1))) (and (<= v_b_137_8 .cse0) (or (< v_idx_840 v_b_141_8) (= (select |c_#memory_int| v_idx_840) v_v_1754_7)) (<= (+ v_b_148_8 2) v_b_140_8) (or (= (select |c_#memory_int| v_idx_836) v_v_1750_8) (<= c_ULTIMATE.start_main_p2 v_idx_836) (< v_idx_836 v_b_137_8)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_141_8) (<= 0 v_v_1753_6) (or (= (select |c_#memory_int| v_idx_837) 0) (<= .cse1 v_idx_837) (< v_idx_837 c_ULTIMATE.start_main_p2)) (or (< v_idx_835 v_b_148_8) (<= v_b_137_8 v_idx_835) (= (select |c_#memory_int| v_idx_835) 0)) (<= .cse0 v_b_137_8) (or (<= v_b_148_8 v_idx_834) (= (select |c_#memory_int| v_idx_834) v_v_1748_8)) (<= (+ v_b_148_8 3) v_b_141_8) (or (<= v_b_141_8 v_idx_839) (= (select |c_#memory_int| v_idx_839) v_v_1753_6) (< v_idx_839 v_b_140_8)) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_b_141_8 .cse2) (or (= (select |c_#memory_int| v_idx_838) v_v_1752_7) (<= v_b_140_8 v_idx_838) (< v_idx_838 .cse1)) (<= (+ v_b_137_8 1) v_b_140_8) (<= v_b_137_8 c_ULTIMATE.start_main_p2) (<= .cse2 v_b_141_8) (<= (+ v_b_137_8 2) v_b_141_8) (<= .cse1 v_b_140_8) (<= 0 (* 2 v_v_1753_6)))))) is different from false [2019-01-11 11:46:32,060 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-11 11:46:32,060 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:46:32,060 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:46:32,061 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [2] total 5 [2019-01-11 11:46:32,061 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:46:32,061 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-11 11:46:32,061 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-11 11:46:32,061 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:46:32,061 INFO L87 Difference]: Start difference. First operand 17 states and 47 transitions. Second operand 5 states. [2019-01-11 11:46:34,582 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_830 Int) (v_idx_831 Int) (v_idx_832 Int) (v_idx_833 Int) (v_idx_827 Int) (v_idx_828 Int) (v_idx_829 Int)) (exists ((v_v_1752_7 Int) (v_v_1753_6 Int) (v_v_1750_8 Int) (v_v_1754_7 Int) (v_b_140_8 Int) (v_b_141_8 Int) (v_v_1748_8 Int)) (let ((.cse1 (+ v_b_140_8 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (or (<= .cse0 v_idx_830) (= (select |c_#memory_int| v_idx_830) 0) (< v_idx_830 c_ULTIMATE.start_main_p2)) (or (< v_idx_831 .cse0) (= (select |c_#memory_int| v_idx_831) v_v_1752_7) (<= v_b_140_8 v_idx_831)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_141_8) (<= 0 v_v_1753_6) (or (< v_idx_833 v_b_141_8) (= (select |c_#memory_int| v_idx_833) v_v_1754_7)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_140_8) (or (< v_idx_832 v_b_140_8) (= (select |c_#memory_int| v_idx_832) v_v_1753_6) (<= v_b_141_8 v_idx_832)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_141_8) (<= v_b_141_8 .cse1) (or (<= c_ULTIMATE.start_main_p1 v_idx_827) (= (select |c_#memory_int| v_idx_827) v_v_1748_8)) (or (< v_idx_828 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_828) (= (select |c_#memory_int| v_idx_828) 0)) (or (<= c_ULTIMATE.start_main_p2 v_idx_829) (= (select |c_#memory_int| v_idx_829) v_v_1750_8) (< v_idx_829 .cse2)) (<= .cse1 v_b_141_8) (<= .cse2 c_ULTIMATE.start_main_p2) (<= .cse0 v_b_140_8) (<= 0 (* 2 v_v_1753_6)))))) (forall ((v_idx_820 Int) (v_idx_823 Int) (v_idx_824 Int) (v_idx_821 Int) (v_idx_822 Int) (v_idx_825 Int) (v_idx_826 Int)) (exists ((v_v_1752_7 Int) (v_v_1753_6 Int) (v_v_1750_8 Int) (v_v_1754_7 Int) (v_v_1748_8 Int)) (let ((.cse5 (+ c_ULTIMATE.start_main_p3 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_823) 0) (<= .cse3 v_idx_823) (< v_idx_823 c_ULTIMATE.start_main_p2)) (or (= (select |c_#memory_int| v_idx_824) v_v_1752_7) (<= c_ULTIMATE.start_main_p3 v_idx_824) (< v_idx_824 .cse3)) (or (<= c_ULTIMATE.start_main_p2 v_idx_822) (< v_idx_822 .cse4) (= (select |c_#memory_int| v_idx_822) v_v_1750_8)) (or (= (select |c_#memory_int| v_idx_826) v_v_1754_7) (< v_idx_826 .cse5)) (<= 0 v_v_1753_6) (or (= (select |c_#memory_int| v_idx_820) v_v_1748_8) (<= c_ULTIMATE.start_main_p1 v_idx_820)) (or (< v_idx_821 c_ULTIMATE.start_main_p1) (<= .cse4 v_idx_821) (= (select |c_#memory_int| v_idx_821) 0)) (or (<= .cse5 v_idx_825) (< v_idx_825 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_825) v_v_1753_6)) (<= .cse4 c_ULTIMATE.start_main_p2) (<= 0 (* 2 v_v_1753_6)) (<= .cse3 c_ULTIMATE.start_main_p3))))) (forall ((v_idx_840 Int) (v_idx_834 Int) (v_idx_835 Int) (v_idx_838 Int) (v_idx_839 Int) (v_idx_836 Int) (v_idx_837 Int)) (exists ((v_b_137_8 Int) (v_b_148_8 Int) (v_v_1753_6 Int) (v_v_1752_7 Int) (v_v_1750_8 Int) (v_v_1754_7 Int) (v_b_140_8 Int) (v_b_141_8 Int) (v_v_1748_8 Int)) (let ((.cse6 (+ v_b_148_8 1)) (.cse8 (+ v_b_140_8 1)) (.cse7 (+ c_ULTIMATE.start_main_p2 1))) (and (<= v_b_137_8 .cse6) (or (< v_idx_840 v_b_141_8) (= (select |c_#memory_int| v_idx_840) v_v_1754_7)) (<= (+ v_b_148_8 2) v_b_140_8) (or (= (select |c_#memory_int| v_idx_836) v_v_1750_8) (<= c_ULTIMATE.start_main_p2 v_idx_836) (< v_idx_836 v_b_137_8)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_141_8) (<= 0 v_v_1753_6) (or (= (select |c_#memory_int| v_idx_837) 0) (<= .cse7 v_idx_837) (< v_idx_837 c_ULTIMATE.start_main_p2)) (or (< v_idx_835 v_b_148_8) (<= v_b_137_8 v_idx_835) (= (select |c_#memory_int| v_idx_835) 0)) (<= .cse6 v_b_137_8) (or (<= v_b_148_8 v_idx_834) (= (select |c_#memory_int| v_idx_834) v_v_1748_8)) (<= (+ v_b_148_8 3) v_b_141_8) (or (<= v_b_141_8 v_idx_839) (= (select |c_#memory_int| v_idx_839) v_v_1753_6) (< v_idx_839 v_b_140_8)) (<= .cse6 c_ULTIMATE.start_main_p2) (<= v_b_141_8 .cse8) (or (= (select |c_#memory_int| v_idx_838) v_v_1752_7) (<= v_b_140_8 v_idx_838) (< v_idx_838 .cse7)) (<= (+ v_b_137_8 1) v_b_140_8) (<= v_b_137_8 c_ULTIMATE.start_main_p2) (<= .cse8 v_b_141_8) (<= (+ v_b_137_8 2) v_b_141_8) (<= .cse7 v_b_140_8) (<= 0 (* 2 v_v_1753_6))))))) is different from false [2019-01-11 11:46:49,424 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_830 Int) (v_idx_831 Int) (v_idx_832 Int) (v_idx_833 Int) (v_idx_827 Int) (v_idx_828 Int) (v_idx_829 Int)) (exists ((v_v_1752_7 Int) (v_v_1753_6 Int) (v_v_1750_8 Int) (v_v_1754_7 Int) (v_b_140_8 Int) (v_b_141_8 Int) (v_v_1748_8 Int)) (let ((.cse1 (+ v_b_140_8 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (or (<= .cse0 v_idx_830) (= (select |c_#memory_int| v_idx_830) 0) (< v_idx_830 c_ULTIMATE.start_main_p2)) (or (< v_idx_831 .cse0) (= (select |c_#memory_int| v_idx_831) v_v_1752_7) (<= v_b_140_8 v_idx_831)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_141_8) (<= 0 v_v_1753_6) (or (< v_idx_833 v_b_141_8) (= (select |c_#memory_int| v_idx_833) v_v_1754_7)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_140_8) (or (< v_idx_832 v_b_140_8) (= (select |c_#memory_int| v_idx_832) v_v_1753_6) (<= v_b_141_8 v_idx_832)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_141_8) (<= v_b_141_8 .cse1) (or (<= c_ULTIMATE.start_main_p1 v_idx_827) (= (select |c_#memory_int| v_idx_827) v_v_1748_8)) (or (< v_idx_828 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_828) (= (select |c_#memory_int| v_idx_828) 0)) (or (<= c_ULTIMATE.start_main_p2 v_idx_829) (= (select |c_#memory_int| v_idx_829) v_v_1750_8) (< v_idx_829 .cse2)) (<= .cse1 v_b_141_8) (<= .cse2 c_ULTIMATE.start_main_p2) (<= .cse0 v_b_140_8) (<= 0 (* 2 v_v_1753_6)))))) (forall ((v_idx_840 Int) (v_idx_834 Int) (v_idx_835 Int) (v_idx_838 Int) (v_idx_839 Int) (v_idx_836 Int) (v_idx_837 Int)) (exists ((v_b_137_8 Int) (v_b_148_8 Int) (v_v_1753_6 Int) (v_v_1752_7 Int) (v_v_1750_8 Int) (v_v_1754_7 Int) (v_b_140_8 Int) (v_b_141_8 Int) (v_v_1748_8 Int)) (let ((.cse3 (+ v_b_148_8 1)) (.cse5 (+ v_b_140_8 1)) (.cse4 (+ c_ULTIMATE.start_main_p2 1))) (and (<= v_b_137_8 .cse3) (or (< v_idx_840 v_b_141_8) (= (select |c_#memory_int| v_idx_840) v_v_1754_7)) (<= (+ v_b_148_8 2) v_b_140_8) (or (= (select |c_#memory_int| v_idx_836) v_v_1750_8) (<= c_ULTIMATE.start_main_p2 v_idx_836) (< v_idx_836 v_b_137_8)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_141_8) (<= 0 v_v_1753_6) (or (= (select |c_#memory_int| v_idx_837) 0) (<= .cse4 v_idx_837) (< v_idx_837 c_ULTIMATE.start_main_p2)) (or (< v_idx_835 v_b_148_8) (<= v_b_137_8 v_idx_835) (= (select |c_#memory_int| v_idx_835) 0)) (<= .cse3 v_b_137_8) (or (<= v_b_148_8 v_idx_834) (= (select |c_#memory_int| v_idx_834) v_v_1748_8)) (<= (+ v_b_148_8 3) v_b_141_8) (or (<= v_b_141_8 v_idx_839) (= (select |c_#memory_int| v_idx_839) v_v_1753_6) (< v_idx_839 v_b_140_8)) (<= .cse3 c_ULTIMATE.start_main_p2) (<= v_b_141_8 .cse5) (or (= (select |c_#memory_int| v_idx_838) v_v_1752_7) (<= v_b_140_8 v_idx_838) (< v_idx_838 .cse4)) (<= (+ v_b_137_8 1) v_b_140_8) (<= v_b_137_8 c_ULTIMATE.start_main_p2) (<= .cse5 v_b_141_8) (<= (+ v_b_137_8 2) v_b_141_8) (<= .cse4 v_b_140_8) (<= 0 (* 2 v_v_1753_6))))))) is different from false [2019-01-11 11:46:53,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:46:53,047 INFO L93 Difference]: Finished difference Result 20 states and 53 transitions. [2019-01-11 11:46:53,047 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-11 11:46:53,047 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-11 11:46:53,047 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:46:53,048 INFO L225 Difference]: With dead ends: 20 [2019-01-11 11:46:53,048 INFO L226 Difference]: Without dead ends: 19 [2019-01-11 11:46:53,048 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 13.1s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-11 11:46:53,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2019-01-11 11:46:53,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 18. [2019-01-11 11:46:53,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2019-01-11 11:46:53,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 51 transitions. [2019-01-11 11:46:53,066 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 51 transitions. Word has length 4 [2019-01-11 11:46:53,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:46:53,066 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 51 transitions. [2019-01-11 11:46:53,066 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-11 11:46:53,066 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 51 transitions. [2019-01-11 11:46:53,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:46:53,067 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:46:53,067 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-11 11:46:53,067 INFO L423 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:46:53,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:46:53,067 INFO L82 PathProgramCache]: Analyzing trace with hash 935378, now seen corresponding path program 2 times [2019-01-11 11:46:53,067 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:46:53,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:46:53,068 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:46:53,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:46:53,069 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:46:53,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:46:53,214 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:46:53,214 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:46:53,214 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:46:53,214 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:46:53,215 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:46:53,215 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:46:53,215 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:46:53,224 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-11 11:46:53,224 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-11 11:46:53,229 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-11 11:46:53,229 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:46:53,230 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:46:53,233 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-11 11:46:53,236 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:46:53,237 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-11 11:46:53,244 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:46:53,246 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:46:53,246 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-11 11:46:53,247 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-11 11:46:53,290 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:46:53,298 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:46:53,308 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:46:53,308 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:19, output treesize:22 [2019-01-11 11:46:53,326 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:46:53,327 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:46:53,328 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:46:53,328 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:46:53,329 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-11 11:46:53,330 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:46:53,357 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:46:53,358 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-11 11:46:53,381 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:46:53,381 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:46:53,382 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:46:53,384 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:46:53,385 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:46:53,386 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:46:53,387 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 48 [2019-01-11 11:46:53,388 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:46:53,435 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:46:53,435 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-11 11:46:53,450 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:46:53,450 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:46:53,481 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:46:53,500 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-11 11:46:53,501 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 9 [2019-01-11 11:46:53,501 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-11 11:46:53,501 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-01-11 11:46:53,501 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-01-11 11:46:53,502 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=66, Unknown=0, NotChecked=0, Total=110 [2019-01-11 11:46:53,502 INFO L87 Difference]: Start difference. First operand 18 states and 51 transitions. Second operand 8 states. [2019-01-11 11:46:53,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:46:53,785 INFO L93 Difference]: Finished difference Result 37 states and 88 transitions. [2019-01-11 11:46:53,786 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-11 11:46:53,786 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 4 [2019-01-11 11:46:53,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:46:53,787 INFO L225 Difference]: With dead ends: 37 [2019-01-11 11:46:53,787 INFO L226 Difference]: Without dead ends: 36 [2019-01-11 11:46:53,788 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=62, Invalid=94, Unknown=0, NotChecked=0, Total=156 [2019-01-11 11:46:53,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-01-11 11:46:53,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 20. [2019-01-11 11:46:53,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-01-11 11:46:53,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 59 transitions. [2019-01-11 11:46:53,810 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 59 transitions. Word has length 4 [2019-01-11 11:46:53,810 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:46:53,810 INFO L480 AbstractCegarLoop]: Abstraction has 20 states and 59 transitions. [2019-01-11 11:46:53,810 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-01-11 11:46:53,810 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 59 transitions. [2019-01-11 11:46:53,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-11 11:46:53,811 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:46:53,811 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-11 11:46:53,811 INFO L423 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:46:53,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:46:53,812 INFO L82 PathProgramCache]: Analyzing trace with hash 28823850, now seen corresponding path program 1 times [2019-01-11 11:46:53,812 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:46:53,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:46:53,812 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:46:53,813 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:46:53,813 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:46:53,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:46:53,888 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:46:53,889 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:46:53,889 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:46:53,889 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-11 11:46:53,889 INFO L207 CegarAbsIntRunner]: [0], [6], [16], [18], [19] [2019-01-11 11:46:53,891 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:46:53,891 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:47:00,403 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:47:00,403 INFO L272 AbstractInterpreter]: Visited 5 different actions 21 times. Merged at 3 different actions 12 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:47:00,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:00,404 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:47:00,760 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 53.57% of their original sizes. [2019-01-11 11:47:00,760 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:47:03,151 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_973 Int) (v_idx_974 Int) (v_idx_977 Int) (v_idx_978 Int) (v_idx_975 Int) (v_idx_976 Int) (v_idx_979 Int)) (exists ((v_v_1852_8 Int) (v_v_1856_8 Int) (v_v_1854_8 Int) (v_v_1853_8 Int) (v_v_1858_8 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 v_v_1853_8) (or (<= c_ULTIMATE.start_main_p1 v_idx_973) (= (select |c_#memory_int| v_idx_973) v_v_1852_8)) (or (< v_idx_976 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_976) (= (select |c_#memory_int| v_idx_976) 0)) (or (< v_idx_979 .cse1) (= (select |c_#memory_int| v_idx_979) v_v_1858_8)) (or (= (select |c_#memory_int| v_idx_977) v_v_1856_8) (<= c_ULTIMATE.start_main_p3 v_idx_977) (< v_idx_977 .cse0)) (or (<= .cse2 v_idx_974) (= (select |c_#memory_int| v_idx_974) v_v_1853_8) (< v_idx_974 c_ULTIMATE.start_main_p1)) (or (= (select |c_#memory_int| v_idx_975) v_v_1854_8) (< v_idx_975 .cse2) (<= c_ULTIMATE.start_main_p2 v_idx_975)) (<= .cse2 c_ULTIMATE.start_main_p2) (or (= 0 (select |c_#memory_int| v_idx_978)) (<= .cse1 v_idx_978) (< v_idx_978 c_ULTIMATE.start_main_p3)) (<= 0 (* 2 v_v_1853_8)) (<= .cse0 c_ULTIMATE.start_main_p3))))) is different from false [2019-01-11 11:47:05,705 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_984 Int) (v_idx_985 Int) (v_idx_982 Int) (v_idx_983 Int) (v_idx_986 Int) (v_idx_980 Int) (v_idx_981 Int)) (exists ((v_v_1852_8 Int) (v_v_1856_8 Int) (v_v_1854_8 Int) (v_v_1853_8 Int) (v_v_1858_8 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p1 v_idx_980) (= (select |c_#memory_int| v_idx_980) v_v_1852_8)) (or (= (select |c_#memory_int| v_idx_983) 0) (< v_idx_983 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_983)) (or (<= c_ULTIMATE.start_main_p3 v_idx_984) (< v_idx_984 .cse0) (= (select |c_#memory_int| v_idx_984) v_v_1856_8)) (<= 0 v_v_1853_8) (or (< v_idx_986 .cse1) (= (select |c_#memory_int| v_idx_986) v_v_1858_8)) (or (= (select |c_#memory_int| v_idx_982) v_v_1854_8) (< v_idx_982 .cse2) (<= c_ULTIMATE.start_main_p2 v_idx_982)) (or (<= .cse2 v_idx_981) (= (select |c_#memory_int| v_idx_981) v_v_1853_8) (< v_idx_981 c_ULTIMATE.start_main_p1)) (<= .cse2 c_ULTIMATE.start_main_p2) (<= 0 (* 2 v_v_1853_8)) (or (= (select |c_#memory_int| v_idx_985) 0) (<= .cse1 v_idx_985) (< v_idx_985 c_ULTIMATE.start_main_p3)) (<= .cse0 c_ULTIMATE.start_main_p3))))) is different from false [2019-01-11 11:47:08,310 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_993 Int) (v_idx_988 Int) (v_idx_989 Int) (v_idx_987 Int) (v_idx_991 Int) (v_idx_992 Int) (v_idx_990 Int)) (exists ((v_v_2348_6 Int) (v_v_1852_8 Int) (v_v_1856_8 Int) (v_v_1854_8 Int) (v_b_123_9 Int) (v_b_146_9 Int) (v_v_1858_8 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_146_9 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1))) (and (<= 0 v_v_2348_6) (<= (+ v_b_146_9 2) c_ULTIMATE.start_main_p3) (<= .cse0 v_b_123_9) (<= v_b_123_9 c_ULTIMATE.start_main_p2) (or (< v_idx_989 v_b_123_9) (= (select |c_#memory_int| v_idx_989) v_v_1854_8) (<= c_ULTIMATE.start_main_p2 v_idx_989)) (or (= (select |c_#memory_int| v_idx_990) 0) (<= .cse1 v_idx_990) (< v_idx_990 c_ULTIMATE.start_main_p2)) (or (< v_idx_991 .cse1) (<= c_ULTIMATE.start_main_p3 v_idx_991) (= (select |c_#memory_int| v_idx_991) v_v_1856_8)) (<= v_b_123_9 .cse0) (<= .cse1 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_993) v_v_1858_8) (< v_idx_993 .cse2)) (or (<= v_b_146_9 v_idx_987) (= (select |c_#memory_int| v_idx_987) v_v_1852_8)) (or (<= v_b_123_9 v_idx_988) (< v_idx_988 v_b_146_9) (= (select |c_#memory_int| v_idx_988) v_v_2348_6)) (<= (+ v_b_123_9 1) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_2348_6)) (<= .cse0 c_ULTIMATE.start_main_p2) (or (<= .cse2 v_idx_992) (= (select |c_#memory_int| v_idx_992) 0) (< v_idx_992 c_ULTIMATE.start_main_p3)))))) is different from false [2019-01-11 11:47:10,493 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_995 Int) (v_idx_996 Int) (v_idx_994 Int) (v_idx_999 Int) (v_idx_1000 Int) (v_idx_997 Int) (v_idx_998 Int)) (exists ((v_v_2348_6 Int) (v_b_160_9 Int) (v_v_1852_8 Int) (v_b_125_9 Int) (v_v_1856_8 Int) (v_v_1854_8 Int) (v_b_123_9 Int) (v_b_146_9 Int) (v_v_1858_8 Int)) (let ((.cse0 (+ v_b_146_9 2)) (.cse2 (+ v_b_146_9 1)) (.cse3 (+ c_ULTIMATE.start_main_p3 1)) (.cse4 (+ v_b_123_9 1)) (.cse1 (+ v_b_160_9 1))) (and (<= .cse0 v_b_125_9) (<= .cse1 c_ULTIMATE.start_main_p3) (<= v_b_123_9 v_b_160_9) (or (<= c_ULTIMATE.start_main_p3 v_idx_998) (= (select |c_#memory_int| v_idx_998) v_v_1856_8) (< v_idx_998 v_b_125_9)) (<= 0 v_v_2348_6) (<= .cse0 c_ULTIMATE.start_main_p3) (<= .cse2 v_b_123_9) (or (<= v_b_146_9 v_idx_994) (= (select |c_#memory_int| v_idx_994) v_v_1852_8)) (or (= 0 (select |c_#memory_int| v_idx_999)) (<= .cse3 v_idx_999) (< v_idx_999 c_ULTIMATE.start_main_p3)) (<= .cse4 v_b_125_9) (<= v_b_123_9 .cse2) (or (<= v_b_160_9 v_idx_996) (= (select |c_#memory_int| v_idx_996) v_v_1854_8) (< v_idx_996 v_b_123_9)) (or (= (select |c_#memory_int| v_idx_997) 0) (<= v_b_125_9 v_idx_997) (< v_idx_997 v_b_160_9)) (<= .cse1 v_b_125_9) (<= .cse2 v_b_160_9) (or (= (select |c_#memory_int| v_idx_1000) v_v_1858_8) (< v_idx_1000 .cse3)) (<= .cse4 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_2348_6)) (<= v_b_125_9 .cse1) (<= v_b_125_9 c_ULTIMATE.start_main_p3) (or (< v_idx_995 v_b_146_9) (<= v_b_123_9 v_idx_995) (= (select |c_#memory_int| v_idx_995) v_v_2348_6)))))) is different from false [2019-01-11 11:47:10,535 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-11 11:47:10,535 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:47:10,535 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:47:10,535 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [2] total 6 [2019-01-11 11:47:10,535 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:47:10,536 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-11 11:47:10,536 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-11 11:47:10,536 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-11 11:47:10,536 INFO L87 Difference]: Start difference. First operand 20 states and 59 transitions. Second operand 6 states. [2019-01-11 11:47:13,046 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_993 Int) (v_idx_988 Int) (v_idx_989 Int) (v_idx_987 Int) (v_idx_991 Int) (v_idx_992 Int) (v_idx_990 Int)) (exists ((v_v_2348_6 Int) (v_v_1852_8 Int) (v_v_1856_8 Int) (v_v_1854_8 Int) (v_b_123_9 Int) (v_b_146_9 Int) (v_v_1858_8 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_146_9 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1))) (and (<= 0 v_v_2348_6) (<= (+ v_b_146_9 2) c_ULTIMATE.start_main_p3) (<= .cse0 v_b_123_9) (<= v_b_123_9 c_ULTIMATE.start_main_p2) (or (< v_idx_989 v_b_123_9) (= (select |c_#memory_int| v_idx_989) v_v_1854_8) (<= c_ULTIMATE.start_main_p2 v_idx_989)) (or (= (select |c_#memory_int| v_idx_990) 0) (<= .cse1 v_idx_990) (< v_idx_990 c_ULTIMATE.start_main_p2)) (or (< v_idx_991 .cse1) (<= c_ULTIMATE.start_main_p3 v_idx_991) (= (select |c_#memory_int| v_idx_991) v_v_1856_8)) (<= v_b_123_9 .cse0) (<= .cse1 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_993) v_v_1858_8) (< v_idx_993 .cse2)) (or (<= v_b_146_9 v_idx_987) (= (select |c_#memory_int| v_idx_987) v_v_1852_8)) (or (<= v_b_123_9 v_idx_988) (< v_idx_988 v_b_146_9) (= (select |c_#memory_int| v_idx_988) v_v_2348_6)) (<= (+ v_b_123_9 1) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_2348_6)) (<= .cse0 c_ULTIMATE.start_main_p2) (or (<= .cse2 v_idx_992) (= (select |c_#memory_int| v_idx_992) 0) (< v_idx_992 c_ULTIMATE.start_main_p3)))))) (forall ((v_idx_995 Int) (v_idx_996 Int) (v_idx_994 Int) (v_idx_999 Int) (v_idx_1000 Int) (v_idx_997 Int) (v_idx_998 Int)) (exists ((v_v_2348_6 Int) (v_b_160_9 Int) (v_v_1852_8 Int) (v_b_125_9 Int) (v_v_1856_8 Int) (v_v_1854_8 Int) (v_b_123_9 Int) (v_b_146_9 Int) (v_v_1858_8 Int)) (let ((.cse3 (+ v_b_146_9 2)) (.cse5 (+ v_b_146_9 1)) (.cse6 (+ c_ULTIMATE.start_main_p3 1)) (.cse7 (+ v_b_123_9 1)) (.cse4 (+ v_b_160_9 1))) (and (<= .cse3 v_b_125_9) (<= .cse4 c_ULTIMATE.start_main_p3) (<= v_b_123_9 v_b_160_9) (or (<= c_ULTIMATE.start_main_p3 v_idx_998) (= (select |c_#memory_int| v_idx_998) v_v_1856_8) (< v_idx_998 v_b_125_9)) (<= 0 v_v_2348_6) (<= .cse3 c_ULTIMATE.start_main_p3) (<= .cse5 v_b_123_9) (or (<= v_b_146_9 v_idx_994) (= (select |c_#memory_int| v_idx_994) v_v_1852_8)) (or (= 0 (select |c_#memory_int| v_idx_999)) (<= .cse6 v_idx_999) (< v_idx_999 c_ULTIMATE.start_main_p3)) (<= .cse7 v_b_125_9) (<= v_b_123_9 .cse5) (or (<= v_b_160_9 v_idx_996) (= (select |c_#memory_int| v_idx_996) v_v_1854_8) (< v_idx_996 v_b_123_9)) (or (= (select |c_#memory_int| v_idx_997) 0) (<= v_b_125_9 v_idx_997) (< v_idx_997 v_b_160_9)) (<= .cse4 v_b_125_9) (<= .cse5 v_b_160_9) (or (= (select |c_#memory_int| v_idx_1000) v_v_1858_8) (< v_idx_1000 .cse6)) (<= .cse7 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_2348_6)) (<= v_b_125_9 .cse4) (<= v_b_125_9 c_ULTIMATE.start_main_p3) (or (< v_idx_995 v_b_146_9) (<= v_b_123_9 v_idx_995) (= (select |c_#memory_int| v_idx_995) v_v_2348_6)))))) (forall ((v_idx_973 Int) (v_idx_974 Int) (v_idx_977 Int) (v_idx_978 Int) (v_idx_975 Int) (v_idx_976 Int) (v_idx_979 Int)) (exists ((v_v_1852_8 Int) (v_v_1856_8 Int) (v_v_1854_8 Int) (v_v_1853_8 Int) (v_v_1858_8 Int)) (let ((.cse10 (+ c_ULTIMATE.start_main_p1 1)) (.cse9 (+ c_ULTIMATE.start_main_p3 1)) (.cse8 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 v_v_1853_8) (or (<= c_ULTIMATE.start_main_p1 v_idx_973) (= (select |c_#memory_int| v_idx_973) v_v_1852_8)) (or (< v_idx_976 c_ULTIMATE.start_main_p2) (<= .cse8 v_idx_976) (= (select |c_#memory_int| v_idx_976) 0)) (or (< v_idx_979 .cse9) (= (select |c_#memory_int| v_idx_979) v_v_1858_8)) (or (= (select |c_#memory_int| v_idx_977) v_v_1856_8) (<= c_ULTIMATE.start_main_p3 v_idx_977) (< v_idx_977 .cse8)) (or (<= .cse10 v_idx_974) (= (select |c_#memory_int| v_idx_974) v_v_1853_8) (< v_idx_974 c_ULTIMATE.start_main_p1)) (or (= (select |c_#memory_int| v_idx_975) v_v_1854_8) (< v_idx_975 .cse10) (<= c_ULTIMATE.start_main_p2 v_idx_975)) (<= .cse10 c_ULTIMATE.start_main_p2) (or (= 0 (select |c_#memory_int| v_idx_978)) (<= .cse9 v_idx_978) (< v_idx_978 c_ULTIMATE.start_main_p3)) (<= 0 (* 2 v_v_1853_8)) (<= .cse8 c_ULTIMATE.start_main_p3))))) (forall ((v_idx_984 Int) (v_idx_985 Int) (v_idx_982 Int) (v_idx_983 Int) (v_idx_986 Int) (v_idx_980 Int) (v_idx_981 Int)) (exists ((v_v_1852_8 Int) (v_v_1856_8 Int) (v_v_1854_8 Int) (v_v_1853_8 Int) (v_v_1858_8 Int)) (let ((.cse13 (+ c_ULTIMATE.start_main_p1 1)) (.cse12 (+ c_ULTIMATE.start_main_p3 1)) (.cse11 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p1 v_idx_980) (= (select |c_#memory_int| v_idx_980) v_v_1852_8)) (or (= (select |c_#memory_int| v_idx_983) 0) (< v_idx_983 c_ULTIMATE.start_main_p2) (<= .cse11 v_idx_983)) (or (<= c_ULTIMATE.start_main_p3 v_idx_984) (< v_idx_984 .cse11) (= (select |c_#memory_int| v_idx_984) v_v_1856_8)) (<= 0 v_v_1853_8) (or (< v_idx_986 .cse12) (= (select |c_#memory_int| v_idx_986) v_v_1858_8)) (or (= (select |c_#memory_int| v_idx_982) v_v_1854_8) (< v_idx_982 .cse13) (<= c_ULTIMATE.start_main_p2 v_idx_982)) (or (<= .cse13 v_idx_981) (= (select |c_#memory_int| v_idx_981) v_v_1853_8) (< v_idx_981 c_ULTIMATE.start_main_p1)) (<= .cse13 c_ULTIMATE.start_main_p2) (<= 0 (* 2 v_v_1853_8)) (or (= (select |c_#memory_int| v_idx_985) 0) (<= .cse12 v_idx_985) (< v_idx_985 c_ULTIMATE.start_main_p3)) (<= .cse11 c_ULTIMATE.start_main_p3)))))) is different from false [2019-01-11 11:47:35,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:47:35,642 INFO L93 Difference]: Finished difference Result 23 states and 61 transitions. [2019-01-11 11:47:35,642 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-11 11:47:35,642 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2019-01-11 11:47:35,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:47:35,642 INFO L225 Difference]: With dead ends: 23 [2019-01-11 11:47:35,643 INFO L226 Difference]: Without dead ends: 20 [2019-01-11 11:47:35,643 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.2s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-11 11:47:35,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-01-11 11:47:35,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2019-01-11 11:47:35,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-01-11 11:47:35,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 58 transitions. [2019-01-11 11:47:35,666 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 58 transitions. Word has length 5 [2019-01-11 11:47:35,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:47:35,666 INFO L480 AbstractCegarLoop]: Abstraction has 20 states and 58 transitions. [2019-01-11 11:47:35,666 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-01-11 11:47:35,666 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 58 transitions. [2019-01-11 11:47:35,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-11 11:47:35,667 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:47:35,667 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1] [2019-01-11 11:47:35,667 INFO L423 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:47:35,667 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:35,667 INFO L82 PathProgramCache]: Analyzing trace with hash 28814176, now seen corresponding path program 2 times [2019-01-11 11:47:35,667 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:47:35,668 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:35,668 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:47:35,668 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:35,668 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:47:35,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:47:35,736 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2019-01-11 11:47:35,737 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-11 11:47:35,737 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-01-11 11:47:35,737 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:47:35,737 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:47:35,737 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:47:35,737 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-01-11 11:47:35,738 INFO L87 Difference]: Start difference. First operand 20 states and 58 transitions. Second operand 4 states. [2019-01-11 11:47:35,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:47:35,813 INFO L93 Difference]: Finished difference Result 25 states and 65 transitions. [2019-01-11 11:47:35,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:47:35,813 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 5 [2019-01-11 11:47:35,813 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:47:35,814 INFO L225 Difference]: With dead ends: 25 [2019-01-11 11:47:35,814 INFO L226 Difference]: Without dead ends: 24 [2019-01-11 11:47:35,815 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-01-11 11:47:35,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2019-01-11 11:47:35,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 21. [2019-01-11 11:47:35,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-01-11 11:47:35,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 62 transitions. [2019-01-11 11:47:35,835 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 62 transitions. Word has length 5 [2019-01-11 11:47:35,835 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:47:35,835 INFO L480 AbstractCegarLoop]: Abstraction has 21 states and 62 transitions. [2019-01-11 11:47:35,835 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:47:35,835 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 62 transitions. [2019-01-11 11:47:35,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-11 11:47:35,835 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:47:35,836 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1] [2019-01-11 11:47:35,836 INFO L423 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:47:35,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:35,836 INFO L82 PathProgramCache]: Analyzing trace with hash 28813988, now seen corresponding path program 2 times [2019-01-11 11:47:35,836 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:47:35,837 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:35,837 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:47:35,837 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:35,837 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:47:35,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:47:35,937 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:47:35,937 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:47:35,937 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:47:35,938 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:47:35,938 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:47:35,938 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:47:35,938 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:47:35,948 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-11 11:47:35,948 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-11 11:47:35,957 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-01-11 11:47:35,958 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:47:35,959 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:47:35,965 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-11 11:47:35,968 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:35,969 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-11 11:47:35,994 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,016 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,017 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-11 11:47:36,018 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-11 11:47:36,094 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:47:36,101 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:47:36,113 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:47:36,113 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:19, output treesize:22 [2019-01-11 11:47:36,136 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,137 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,138 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,139 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,140 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 28 [2019-01-11 11:47:36,141 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:47:36,157 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:47:36,157 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-11 11:47:36,179 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,180 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,181 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,182 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,183 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,184 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,185 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 40 [2019-01-11 11:47:36,186 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:47:36,204 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:47:36,205 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-11 11:47:36,229 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,230 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,230 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,231 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,232 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,233 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:47:36,234 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 40 [2019-01-11 11:47:36,234 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:47:36,256 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:47:36,256 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-11 11:47:36,272 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:47:36,272 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:47:36,303 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 5 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:47:36,323 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-11 11:47:36,323 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 12 [2019-01-11 11:47:36,323 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-11 11:47:36,324 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-01-11 11:47:36,324 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-01-11 11:47:36,324 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=111, Unknown=0, NotChecked=0, Total=182 [2019-01-11 11:47:36,324 INFO L87 Difference]: Start difference. First operand 21 states and 62 transitions. Second operand 10 states. [2019-01-11 11:47:36,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:47:36,713 INFO L93 Difference]: Finished difference Result 55 states and 133 transitions. [2019-01-11 11:47:36,720 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-01-11 11:47:36,720 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 5 [2019-01-11 11:47:36,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:47:36,721 INFO L225 Difference]: With dead ends: 55 [2019-01-11 11:47:36,721 INFO L226 Difference]: Without dead ends: 54 [2019-01-11 11:47:36,721 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 58 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=81, Invalid=129, Unknown=0, NotChecked=0, Total=210 [2019-01-11 11:47:36,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2019-01-11 11:47:36,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 23. [2019-01-11 11:47:36,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23 states. [2019-01-11 11:47:36,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 70 transitions. [2019-01-11 11:47:36,748 INFO L78 Accepts]: Start accepts. Automaton has 23 states and 70 transitions. Word has length 5 [2019-01-11 11:47:36,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:47:36,749 INFO L480 AbstractCegarLoop]: Abstraction has 23 states and 70 transitions. [2019-01-11 11:47:36,749 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-01-11 11:47:36,749 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 70 transitions. [2019-01-11 11:47:36,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-11 11:47:36,749 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:47:36,749 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-11 11:47:36,749 INFO L423 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:47:36,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:36,750 INFO L82 PathProgramCache]: Analyzing trace with hash 28818020, now seen corresponding path program 1 times [2019-01-11 11:47:36,750 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:47:36,750 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:36,750 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:47:36,751 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:36,751 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:47:36,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:47:36,867 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:47:36,868 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:47:36,868 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:47:36,868 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-11 11:47:36,869 INFO L207 CegarAbsIntRunner]: [0], [6], [10], [16], [17] [2019-01-11 11:47:36,870 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:47:36,870 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:47:53,023 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:47:53,023 INFO L272 AbstractInterpreter]: Visited 5 different actions 40 times. Merged at 3 different actions 17 times. Widened at 2 different actions 7 times. Found 12 fixpoints after 3 different actions. Largest state had 0 variables. [2019-01-11 11:47:53,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:53,023 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:47:53,471 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 60.71% of their original sizes. [2019-01-11 11:47:53,472 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:47:55,974 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1137 Int) (v_idx_1136 Int) (v_idx_1135 Int) (v_idx_1134 Int) (v_idx_1133 Int) (v_idx_1139 Int) (v_idx_1138 Int)) (exists ((v_b_401_3 Int) (v_b_400_3 Int) (v_v_5252_1 Int) (v_v_5250_1 Int) (v_v_5251_1 Int) (v_v_5248_1 Int) (v_v_5254_1 Int) (v_v_5249_1 Int)) (let ((.cse1 (+ v_b_400_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1))) (and (or (<= c_ULTIMATE.start_main_p2 v_idx_1135) (< v_idx_1135 .cse0) (= (select |c_#memory_int| v_idx_1135) v_v_5250_1)) (<= 0 v_v_5249_1) (<= (* 2 v_v_5251_1) 0) (<= v_b_401_3 .cse1) (or (< v_idx_1138 v_b_400_3) (<= v_b_401_3 v_idx_1138) (= 0 (select |c_#memory_int| v_idx_1138))) (or (< v_idx_1136 c_ULTIMATE.start_main_p2) (<= .cse2 v_idx_1136) (= (select |c_#memory_int| v_idx_1136) v_v_5251_1)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_400_3) (<= 0 (* 2 v_v_5249_1)) (or (<= .cse0 v_idx_1134) (< v_idx_1134 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1134) v_v_5249_1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_1133) (= (select |c_#memory_int| v_idx_1133) v_v_5248_1)) (<= v_v_5251_1 v_v_5249_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_401_3) (<= .cse1 v_b_401_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_401_3) (<= .cse2 v_b_400_3) (or (< v_idx_1139 v_b_401_3) (= (select |c_#memory_int| v_idx_1139) v_v_5254_1)) (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_v_5251_1 0) (or (< v_idx_1137 .cse2) (= (select |c_#memory_int| v_idx_1137) v_v_5252_1) (<= v_b_400_3 v_idx_1137)))))) is different from false [2019-01-11 11:47:58,388 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1146 Int) (v_idx_1145 Int) (v_idx_1144 Int) (v_idx_1143 Int) (v_idx_1142 Int) (v_idx_1141 Int) (v_idx_1140 Int)) (exists ((v_b_401_3 Int) (v_b_400_3 Int) (v_v_5252_1 Int) (v_v_5250_1 Int) (v_v_5251_1 Int) (v_v_5248_1 Int) (v_v_5254_1 Int) (v_v_5249_1 Int)) (let ((.cse1 (+ v_b_400_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= (select |c_#memory_int| v_idx_1146) v_v_5254_1) (< v_idx_1146 v_b_401_3)) (or (< v_idx_1143 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_1143) (= (select |c_#memory_int| v_idx_1143) v_v_5251_1)) (or (< v_idx_1144 .cse0) (<= v_b_400_3 v_idx_1144) (= (select |c_#memory_int| v_idx_1144) v_v_5252_1)) (<= 0 v_v_5249_1) (<= (* 2 v_v_5251_1) 0) (<= v_b_401_3 .cse1) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_400_3) (or (<= c_ULTIMATE.start_main_p2 v_idx_1142) (= (select |c_#memory_int| v_idx_1142) v_v_5250_1) (< v_idx_1142 .cse2)) (or (= (select |c_#memory_int| v_idx_1141) v_v_5249_1) (< v_idx_1141 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_1141)) (<= 0 (* 2 v_v_5249_1)) (<= v_v_5251_1 v_v_5249_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_401_3) (<= .cse1 v_b_401_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_401_3) (<= .cse0 v_b_400_3) (<= .cse2 c_ULTIMATE.start_main_p2) (or (<= v_b_401_3 v_idx_1145) (< v_idx_1145 v_b_400_3) (= 0 (select |c_#memory_int| v_idx_1145))) (<= v_v_5251_1 0) (or (<= c_ULTIMATE.start_main_p1 v_idx_1140) (= (select |c_#memory_int| v_idx_1140) v_v_5248_1)))))) is different from false [2019-01-11 11:48:00,906 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1148 Int) (v_idx_1147 Int) (v_idx_1153 Int) (v_idx_1152 Int) (v_idx_1151 Int) (v_idx_1150 Int) (v_idx_1149 Int)) (exists ((v_b_401_3 Int) (v_b_400_3 Int) (v_v_5252_1 Int) (v_v_5250_1 Int) (v_v_5251_1 Int) (v_v_5248_1 Int) (v_v_5254_1 Int) (v_v_5249_1 Int)) (let ((.cse1 (+ v_b_400_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= .cse0 v_idx_1150) (= (select |c_#memory_int| v_idx_1150) v_v_5251_1) (< v_idx_1150 c_ULTIMATE.start_main_p2)) (or (= (select |c_#memory_int| v_idx_1153) v_v_5254_1) (< v_idx_1153 v_b_401_3)) (or (= (select |c_#memory_int| v_idx_1147) v_v_5248_1) (<= c_ULTIMATE.start_main_p1 v_idx_1147)) (<= 0 v_v_5249_1) (<= (* 2 v_v_5251_1) 0) (or (= (select |c_#memory_int| v_idx_1151) v_v_5252_1) (<= v_b_400_3 v_idx_1151) (< v_idx_1151 .cse0)) (<= v_b_401_3 .cse1) (or (< v_idx_1149 .cse2) (= (select |c_#memory_int| v_idx_1149) v_v_5250_1) (<= c_ULTIMATE.start_main_p2 v_idx_1149)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_400_3) (<= 0 (* 2 v_v_5249_1)) (or (<= v_b_401_3 v_idx_1152) (< v_idx_1152 v_b_400_3) (= (select |c_#memory_int| v_idx_1152) 0)) (or (<= .cse2 v_idx_1148) (= (select |c_#memory_int| v_idx_1148) v_v_5249_1) (< v_idx_1148 c_ULTIMATE.start_main_p1)) (<= v_v_5251_1 v_v_5249_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_401_3) (<= .cse1 v_b_401_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_401_3) (<= .cse0 v_b_400_3) (<= .cse2 c_ULTIMATE.start_main_p2) (<= v_v_5251_1 0))))) is different from false [2019-01-11 11:48:03,114 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1159 Int) (v_idx_1158 Int) (v_idx_1157 Int) (v_idx_1156 Int) (v_idx_1155 Int) (v_idx_1154 Int) (v_idx_1160 Int)) (exists ((v_v_5610_1 Int) (v_b_401_3 Int) (v_b_400_3 Int) (v_b_397_3 Int) (v_b_424_2 Int) (v_v_5252_1 Int) (v_v_5250_1 Int) (v_v_5251_1 Int) (v_v_5248_1 Int) (v_v_5254_1 Int)) (let ((.cse0 (+ v_b_400_3 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_424_2 1))) (and (<= (+ v_b_397_3 1) v_b_400_3) (<= 0 (* 2 v_v_5610_1)) (<= (* 2 v_v_5251_1) 0) (<= v_b_397_3 c_ULTIMATE.start_main_p2) (<= v_b_401_3 .cse0) (<= v_b_397_3 .cse1) (<= (+ v_b_424_2 3) v_b_401_3) (<= 0 v_v_5610_1) (<= .cse1 c_ULTIMATE.start_main_p2) (or (<= v_b_401_3 v_idx_1159) (= 0 (select |c_#memory_int| v_idx_1159)) (< v_idx_1159 v_b_400_3)) (or (< v_idx_1158 .cse2) (<= v_b_400_3 v_idx_1158) (= (select |c_#memory_int| v_idx_1158) v_v_5252_1)) (or (= (select |c_#memory_int| v_idx_1157) v_v_5251_1) (< v_idx_1157 c_ULTIMATE.start_main_p2) (<= .cse2 v_idx_1157)) (or (< v_idx_1160 v_b_401_3) (= (select |c_#memory_int| v_idx_1160) v_v_5254_1)) (or (<= v_b_424_2 v_idx_1154) (= (select |c_#memory_int| v_idx_1154) v_v_5248_1)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_401_3) (<= .cse0 v_b_401_3) (or (< v_idx_1155 v_b_424_2) (<= v_b_397_3 v_idx_1155) (= (select |c_#memory_int| v_idx_1155) v_v_5610_1)) (<= (+ v_b_397_3 2) v_b_401_3) (<= .cse2 v_b_400_3) (<= v_v_5251_1 v_v_5610_1) (or (= (select |c_#memory_int| v_idx_1156) v_v_5250_1) (< v_idx_1156 v_b_397_3) (<= c_ULTIMATE.start_main_p2 v_idx_1156)) (<= v_v_5251_1 0) (<= (+ v_b_424_2 2) v_b_400_3) (<= .cse1 v_b_397_3))))) is different from false [2019-01-11 11:48:03,178 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-11 11:48:03,179 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:48:03,179 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:48:03,179 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [3] total 7 [2019-01-11 11:48:03,179 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:48:03,179 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-11 11:48:03,180 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-11 11:48:03,180 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-11 11:48:03,180 INFO L87 Difference]: Start difference. First operand 23 states and 70 transitions. Second operand 6 states. [2019-01-11 11:48:05,964 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_1146 Int) (v_idx_1145 Int) (v_idx_1144 Int) (v_idx_1143 Int) (v_idx_1142 Int) (v_idx_1141 Int) (v_idx_1140 Int)) (exists ((v_b_401_3 Int) (v_b_400_3 Int) (v_v_5252_1 Int) (v_v_5250_1 Int) (v_v_5251_1 Int) (v_v_5248_1 Int) (v_v_5254_1 Int) (v_v_5249_1 Int)) (let ((.cse1 (+ v_b_400_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= (select |c_#memory_int| v_idx_1146) v_v_5254_1) (< v_idx_1146 v_b_401_3)) (or (< v_idx_1143 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_1143) (= (select |c_#memory_int| v_idx_1143) v_v_5251_1)) (or (< v_idx_1144 .cse0) (<= v_b_400_3 v_idx_1144) (= (select |c_#memory_int| v_idx_1144) v_v_5252_1)) (<= 0 v_v_5249_1) (<= (* 2 v_v_5251_1) 0) (<= v_b_401_3 .cse1) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_400_3) (or (<= c_ULTIMATE.start_main_p2 v_idx_1142) (= (select |c_#memory_int| v_idx_1142) v_v_5250_1) (< v_idx_1142 .cse2)) (or (= (select |c_#memory_int| v_idx_1141) v_v_5249_1) (< v_idx_1141 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_1141)) (<= 0 (* 2 v_v_5249_1)) (<= v_v_5251_1 v_v_5249_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_401_3) (<= .cse1 v_b_401_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_401_3) (<= .cse0 v_b_400_3) (<= .cse2 c_ULTIMATE.start_main_p2) (or (<= v_b_401_3 v_idx_1145) (< v_idx_1145 v_b_400_3) (= 0 (select |c_#memory_int| v_idx_1145))) (<= v_v_5251_1 0) (or (<= c_ULTIMATE.start_main_p1 v_idx_1140) (= (select |c_#memory_int| v_idx_1140) v_v_5248_1)))))) (forall ((v_idx_1137 Int) (v_idx_1136 Int) (v_idx_1135 Int) (v_idx_1134 Int) (v_idx_1133 Int) (v_idx_1139 Int) (v_idx_1138 Int)) (exists ((v_b_401_3 Int) (v_b_400_3 Int) (v_v_5252_1 Int) (v_v_5250_1 Int) (v_v_5251_1 Int) (v_v_5248_1 Int) (v_v_5254_1 Int) (v_v_5249_1 Int)) (let ((.cse4 (+ v_b_400_3 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1)) (.cse5 (+ c_ULTIMATE.start_main_p2 1))) (and (or (<= c_ULTIMATE.start_main_p2 v_idx_1135) (< v_idx_1135 .cse3) (= (select |c_#memory_int| v_idx_1135) v_v_5250_1)) (<= 0 v_v_5249_1) (<= (* 2 v_v_5251_1) 0) (<= v_b_401_3 .cse4) (or (< v_idx_1138 v_b_400_3) (<= v_b_401_3 v_idx_1138) (= 0 (select |c_#memory_int| v_idx_1138))) (or (< v_idx_1136 c_ULTIMATE.start_main_p2) (<= .cse5 v_idx_1136) (= (select |c_#memory_int| v_idx_1136) v_v_5251_1)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_400_3) (<= 0 (* 2 v_v_5249_1)) (or (<= .cse3 v_idx_1134) (< v_idx_1134 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1134) v_v_5249_1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_1133) (= (select |c_#memory_int| v_idx_1133) v_v_5248_1)) (<= v_v_5251_1 v_v_5249_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_401_3) (<= .cse4 v_b_401_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_401_3) (<= .cse5 v_b_400_3) (or (< v_idx_1139 v_b_401_3) (= (select |c_#memory_int| v_idx_1139) v_v_5254_1)) (<= .cse3 c_ULTIMATE.start_main_p2) (<= v_v_5251_1 0) (or (< v_idx_1137 .cse5) (= (select |c_#memory_int| v_idx_1137) v_v_5252_1) (<= v_b_400_3 v_idx_1137)))))) (forall ((v_idx_1159 Int) (v_idx_1158 Int) (v_idx_1157 Int) (v_idx_1156 Int) (v_idx_1155 Int) (v_idx_1154 Int) (v_idx_1160 Int)) (exists ((v_v_5610_1 Int) (v_b_401_3 Int) (v_b_400_3 Int) (v_b_397_3 Int) (v_b_424_2 Int) (v_v_5252_1 Int) (v_v_5250_1 Int) (v_v_5251_1 Int) (v_v_5248_1 Int) (v_v_5254_1 Int)) (let ((.cse6 (+ v_b_400_3 1)) (.cse8 (+ c_ULTIMATE.start_main_p2 1)) (.cse7 (+ v_b_424_2 1))) (and (<= (+ v_b_397_3 1) v_b_400_3) (<= 0 (* 2 v_v_5610_1)) (<= (* 2 v_v_5251_1) 0) (<= v_b_397_3 c_ULTIMATE.start_main_p2) (<= v_b_401_3 .cse6) (<= v_b_397_3 .cse7) (<= (+ v_b_424_2 3) v_b_401_3) (<= 0 v_v_5610_1) (<= .cse7 c_ULTIMATE.start_main_p2) (or (<= v_b_401_3 v_idx_1159) (= 0 (select |c_#memory_int| v_idx_1159)) (< v_idx_1159 v_b_400_3)) (or (< v_idx_1158 .cse8) (<= v_b_400_3 v_idx_1158) (= (select |c_#memory_int| v_idx_1158) v_v_5252_1)) (or (= (select |c_#memory_int| v_idx_1157) v_v_5251_1) (< v_idx_1157 c_ULTIMATE.start_main_p2) (<= .cse8 v_idx_1157)) (or (< v_idx_1160 v_b_401_3) (= (select |c_#memory_int| v_idx_1160) v_v_5254_1)) (or (<= v_b_424_2 v_idx_1154) (= (select |c_#memory_int| v_idx_1154) v_v_5248_1)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_401_3) (<= .cse6 v_b_401_3) (or (< v_idx_1155 v_b_424_2) (<= v_b_397_3 v_idx_1155) (= (select |c_#memory_int| v_idx_1155) v_v_5610_1)) (<= (+ v_b_397_3 2) v_b_401_3) (<= .cse8 v_b_400_3) (<= v_v_5251_1 v_v_5610_1) (or (= (select |c_#memory_int| v_idx_1156) v_v_5250_1) (< v_idx_1156 v_b_397_3) (<= c_ULTIMATE.start_main_p2 v_idx_1156)) (<= v_v_5251_1 0) (<= (+ v_b_424_2 2) v_b_400_3) (<= .cse7 v_b_397_3))))) (forall ((v_idx_1148 Int) (v_idx_1147 Int) (v_idx_1153 Int) (v_idx_1152 Int) (v_idx_1151 Int) (v_idx_1150 Int) (v_idx_1149 Int)) (exists ((v_b_401_3 Int) (v_b_400_3 Int) (v_v_5252_1 Int) (v_v_5250_1 Int) (v_v_5251_1 Int) (v_v_5248_1 Int) (v_v_5254_1 Int) (v_v_5249_1 Int)) (let ((.cse10 (+ v_b_400_3 1)) (.cse9 (+ c_ULTIMATE.start_main_p2 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= .cse9 v_idx_1150) (= (select |c_#memory_int| v_idx_1150) v_v_5251_1) (< v_idx_1150 c_ULTIMATE.start_main_p2)) (or (= (select |c_#memory_int| v_idx_1153) v_v_5254_1) (< v_idx_1153 v_b_401_3)) (or (= (select |c_#memory_int| v_idx_1147) v_v_5248_1) (<= c_ULTIMATE.start_main_p1 v_idx_1147)) (<= 0 v_v_5249_1) (<= (* 2 v_v_5251_1) 0) (or (= (select |c_#memory_int| v_idx_1151) v_v_5252_1) (<= v_b_400_3 v_idx_1151) (< v_idx_1151 .cse9)) (<= v_b_401_3 .cse10) (or (< v_idx_1149 .cse11) (= (select |c_#memory_int| v_idx_1149) v_v_5250_1) (<= c_ULTIMATE.start_main_p2 v_idx_1149)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_400_3) (<= 0 (* 2 v_v_5249_1)) (or (<= v_b_401_3 v_idx_1152) (< v_idx_1152 v_b_400_3) (= (select |c_#memory_int| v_idx_1152) 0)) (or (<= .cse11 v_idx_1148) (= (select |c_#memory_int| v_idx_1148) v_v_5249_1) (< v_idx_1148 c_ULTIMATE.start_main_p1)) (<= v_v_5251_1 v_v_5249_1) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_401_3) (<= .cse10 v_b_401_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_401_3) (<= .cse9 v_b_400_3) (<= .cse11 c_ULTIMATE.start_main_p2) (<= v_v_5251_1 0)))))) is different from false [2019-01-11 11:48:32,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:48:32,747 INFO L93 Difference]: Finished difference Result 27 states and 77 transitions. [2019-01-11 11:48:32,747 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-11 11:48:32,747 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2019-01-11 11:48:32,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:48:32,747 INFO L225 Difference]: With dead ends: 27 [2019-01-11 11:48:32,747 INFO L226 Difference]: Without dead ends: 26 [2019-01-11 11:48:32,748 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.2s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-11 11:48:32,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2019-01-11 11:48:32,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 24. [2019-01-11 11:48:32,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2019-01-11 11:48:32,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 74 transitions. [2019-01-11 11:48:32,779 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 74 transitions. Word has length 5 [2019-01-11 11:48:32,779 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:48:32,779 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 74 transitions. [2019-01-11 11:48:32,779 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-01-11 11:48:32,780 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 74 transitions. [2019-01-11 11:48:32,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-11 11:48:32,780 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:48:32,780 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-11 11:48:32,780 INFO L423 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:48:32,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:48:32,781 INFO L82 PathProgramCache]: Analyzing trace with hash 28819942, now seen corresponding path program 1 times [2019-01-11 11:48:32,781 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:48:32,781 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:48:32,782 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:48:32,782 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:48:32,782 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:48:32,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:48:32,893 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-11 11:48:32,894 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:48:32,894 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:48:32,894 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-11 11:48:32,894 INFO L207 CegarAbsIntRunner]: [0], [6], [12], [16], [17] [2019-01-11 11:48:32,895 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:48:32,896 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:48:48,672 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:48:48,672 INFO L272 AbstractInterpreter]: Visited 5 different actions 40 times. Merged at 3 different actions 17 times. Widened at 2 different actions 7 times. Found 12 fixpoints after 3 different actions. Largest state had 0 variables. [2019-01-11 11:48:48,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:48:48,672 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:48:49,105 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 53.57% of their original sizes. [2019-01-11 11:48:49,105 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:48:51,578 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1299 Int) (v_idx_1298 Int) (v_idx_1297 Int) (v_idx_1296 Int) (v_idx_1295 Int) (v_idx_1294 Int) (v_idx_1293 Int)) (exists ((v_v_5239_2 Int) (v_v_5235_2 Int) (v_v_5238_2 Int) (v_v_5237_2 Int) (v_v_5234_2 Int) (v_v_5233_2 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (+ v_v_5238_2 v_v_5234_2)) (or (< v_idx_1299 .cse0) (= (select |c_#memory_int| v_idx_1299) v_v_5239_2)) (<= 0 v_v_5234_2) (or (< v_idx_1295 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_1295) (= (select |c_#memory_int| v_idx_1295) v_v_5235_2)) (or (<= c_ULTIMATE.start_main_p1 v_idx_1293) (= (select |c_#memory_int| v_idx_1293) v_v_5233_2)) (or (= (select |c_#memory_int| v_idx_1297) v_v_5237_2) (< v_idx_1297 .cse2) (<= c_ULTIMATE.start_main_p3 v_idx_1297)) (<= .cse2 c_ULTIMATE.start_main_p3) (or (<= .cse2 v_idx_1296) (= 0 (select |c_#memory_int| v_idx_1296)) (< v_idx_1296 c_ULTIMATE.start_main_p2)) (<= 0 (* 2 v_v_5238_2)) (<= 0 (* 2 v_v_5234_2)) (<= 0 v_v_5238_2) (or (< v_idx_1294 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_1294) (= (select |c_#memory_int| v_idx_1294) v_v_5234_2)) (<= .cse1 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_1298) v_v_5238_2) (<= .cse0 v_idx_1298) (< v_idx_1298 c_ULTIMATE.start_main_p3)))))) is different from false [2019-01-11 11:48:54,176 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1302 Int) (v_idx_1301 Int) (v_idx_1300 Int) (v_idx_1306 Int) (v_idx_1305 Int) (v_idx_1304 Int) (v_idx_1303 Int)) (exists ((v_v_5239_2 Int) (v_v_5235_2 Int) (v_v_5238_2 Int) (v_v_5237_2 Int) (v_v_5234_2 Int) (v_v_5233_2 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (+ v_v_5238_2 v_v_5234_2)) (or (<= c_ULTIMATE.start_main_p2 v_idx_1302) (= (select |c_#memory_int| v_idx_1302) v_v_5235_2) (< v_idx_1302 .cse0)) (<= 0 v_v_5234_2) (<= .cse1 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_5238_2)) (<= 0 (* 2 v_v_5234_2)) (<= 0 v_v_5238_2) (or (= (select |c_#memory_int| v_idx_1300) v_v_5233_2) (<= c_ULTIMATE.start_main_p1 v_idx_1300)) (or (<= .cse2 v_idx_1305) (= (select |c_#memory_int| v_idx_1305) v_v_5238_2) (< v_idx_1305 c_ULTIMATE.start_main_p3)) (or (< v_idx_1303 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1303)) (<= .cse1 v_idx_1303)) (or (= (select |c_#memory_int| v_idx_1301) v_v_5234_2) (<= .cse0 v_idx_1301) (< v_idx_1301 c_ULTIMATE.start_main_p1)) (or (<= c_ULTIMATE.start_main_p3 v_idx_1304) (= (select |c_#memory_int| v_idx_1304) v_v_5237_2) (< v_idx_1304 .cse1)) (<= .cse0 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_1306) v_v_5239_2) (< v_idx_1306 .cse2)))))) is different from false [2019-01-11 11:48:56,855 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1313 Int) (v_idx_1312 Int) (v_idx_1311 Int) (v_idx_1310 Int) (v_idx_1309 Int) (v_idx_1308 Int) (v_idx_1307 Int)) (exists ((v_b_411_4 Int) (v_b_410_4 Int) (v_v_5239_2 Int) (v_v_5235_2 Int) (v_v_5238_2 Int) (v_v_5237_2 Int) (v_v_5234_2 Int) (v_v_5233_2 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_410_4 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (<= .cse0 v_b_410_4) (or (= 0 (select |c_#memory_int| v_idx_1310)) (< v_idx_1310 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_1310)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_411_4) (<= 0 (+ v_v_5238_2 v_v_5234_2)) (<= 0 v_v_5234_2) (or (< v_idx_1308 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_1308) (= (select |c_#memory_int| v_idx_1308) v_v_5234_2)) (or (= (select |c_#memory_int| v_idx_1307) v_v_5233_2) (<= c_ULTIMATE.start_main_p1 v_idx_1307)) (or (< v_idx_1309 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_1309) (= (select |c_#memory_int| v_idx_1309) v_v_5235_2)) (<= 0 (* 2 v_v_5238_2)) (<= 0 (* 2 v_v_5234_2)) (or (= (select |c_#memory_int| v_idx_1312) v_v_5238_2) (< v_idx_1312 v_b_410_4) (<= v_b_411_4 v_idx_1312)) (<= 0 v_v_5238_2) (<= .cse2 v_b_411_4) (or (<= v_b_410_4 v_idx_1311) (< v_idx_1311 .cse0) (= (select |c_#memory_int| v_idx_1311) v_v_5237_2)) (<= v_b_411_4 .cse2) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_411_4) (<= .cse1 c_ULTIMATE.start_main_p2) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_410_4) (or (< v_idx_1313 v_b_411_4) (= (select |c_#memory_int| v_idx_1313) v_v_5239_2)))))) is different from false [2019-01-11 11:48:59,325 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1320 Int) (v_idx_1319 Int) (v_idx_1318 Int) (v_idx_1317 Int) (v_idx_1316 Int) (v_idx_1315 Int) (v_idx_1314 Int)) (exists ((v_b_411_4 Int) (v_b_410_4 Int) (v_b_434_3 Int) (v_v_5239_2 Int) (v_b_407_4 Int) (v_v_5235_2 Int) (v_v_5238_2 Int) (v_v_5237_2 Int) (v_v_5595_2 Int) (v_v_5233_2 Int)) (let ((.cse2 (+ v_b_410_4 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_434_3 1))) (and (<= .cse0 v_b_410_4) (or (< v_idx_1315 v_b_434_3) (<= v_b_407_4 v_idx_1315) (= (select |c_#memory_int| v_idx_1315) v_v_5595_2)) (<= v_b_407_4 .cse1) (<= .cse1 v_b_407_4) (<= 0 (* 2 v_v_5595_2)) (or (< v_idx_1316 v_b_407_4) (= (select |c_#memory_int| v_idx_1316) v_v_5235_2) (<= c_ULTIMATE.start_main_p2 v_idx_1316)) (<= (+ v_b_434_3 3) v_b_411_4) (<= (+ v_b_407_4 2) v_b_411_4) (<= (+ v_b_407_4 1) v_b_410_4) (or (< v_idx_1318 .cse0) (= (select |c_#memory_int| v_idx_1318) v_v_5237_2) (<= v_b_410_4 v_idx_1318)) (or (< v_idx_1319 v_b_410_4) (= (select |c_#memory_int| v_idx_1319) v_v_5238_2) (<= v_b_411_4 v_idx_1319)) (<= (+ v_b_434_3 2) v_b_410_4) (<= 0 (* 2 v_v_5238_2)) (<= 0 (+ v_v_5238_2 v_v_5595_2)) (<= 0 v_v_5238_2) (<= .cse2 v_b_411_4) (<= v_b_407_4 c_ULTIMATE.start_main_p2) (or (<= v_b_434_3 v_idx_1314) (= (select |c_#memory_int| v_idx_1314) v_v_5233_2)) (<= 0 v_v_5595_2) (or (< v_idx_1320 v_b_411_4) (= (select |c_#memory_int| v_idx_1320) v_v_5239_2)) (<= v_b_411_4 .cse2) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_411_4) (or (<= .cse0 v_idx_1317) (< v_idx_1317 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1317))) (<= .cse1 c_ULTIMATE.start_main_p2))))) is different from false [2019-01-11 11:48:59,383 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-11 11:48:59,383 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:48:59,383 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:48:59,383 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [3] total 7 [2019-01-11 11:48:59,383 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:48:59,383 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-11 11:48:59,384 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-11 11:48:59,384 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-11 11:48:59,384 INFO L87 Difference]: Start difference. First operand 24 states and 74 transitions. Second operand 6 states. [2019-01-11 11:49:02,093 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_1299 Int) (v_idx_1298 Int) (v_idx_1297 Int) (v_idx_1296 Int) (v_idx_1295 Int) (v_idx_1294 Int) (v_idx_1293 Int)) (exists ((v_v_5239_2 Int) (v_v_5235_2 Int) (v_v_5238_2 Int) (v_v_5237_2 Int) (v_v_5234_2 Int) (v_v_5233_2 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (+ v_v_5238_2 v_v_5234_2)) (or (< v_idx_1299 .cse0) (= (select |c_#memory_int| v_idx_1299) v_v_5239_2)) (<= 0 v_v_5234_2) (or (< v_idx_1295 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_1295) (= (select |c_#memory_int| v_idx_1295) v_v_5235_2)) (or (<= c_ULTIMATE.start_main_p1 v_idx_1293) (= (select |c_#memory_int| v_idx_1293) v_v_5233_2)) (or (= (select |c_#memory_int| v_idx_1297) v_v_5237_2) (< v_idx_1297 .cse2) (<= c_ULTIMATE.start_main_p3 v_idx_1297)) (<= .cse2 c_ULTIMATE.start_main_p3) (or (<= .cse2 v_idx_1296) (= 0 (select |c_#memory_int| v_idx_1296)) (< v_idx_1296 c_ULTIMATE.start_main_p2)) (<= 0 (* 2 v_v_5238_2)) (<= 0 (* 2 v_v_5234_2)) (<= 0 v_v_5238_2) (or (< v_idx_1294 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_1294) (= (select |c_#memory_int| v_idx_1294) v_v_5234_2)) (<= .cse1 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_1298) v_v_5238_2) (<= .cse0 v_idx_1298) (< v_idx_1298 c_ULTIMATE.start_main_p3)))))) (forall ((v_idx_1302 Int) (v_idx_1301 Int) (v_idx_1300 Int) (v_idx_1306 Int) (v_idx_1305 Int) (v_idx_1304 Int) (v_idx_1303 Int)) (exists ((v_v_5239_2 Int) (v_v_5235_2 Int) (v_v_5238_2 Int) (v_v_5237_2 Int) (v_v_5234_2 Int) (v_v_5233_2 Int)) (let ((.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1)) (.cse5 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (+ v_v_5238_2 v_v_5234_2)) (or (<= c_ULTIMATE.start_main_p2 v_idx_1302) (= (select |c_#memory_int| v_idx_1302) v_v_5235_2) (< v_idx_1302 .cse3)) (<= 0 v_v_5234_2) (<= .cse4 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_5238_2)) (<= 0 (* 2 v_v_5234_2)) (<= 0 v_v_5238_2) (or (= (select |c_#memory_int| v_idx_1300) v_v_5233_2) (<= c_ULTIMATE.start_main_p1 v_idx_1300)) (or (<= .cse5 v_idx_1305) (= (select |c_#memory_int| v_idx_1305) v_v_5238_2) (< v_idx_1305 c_ULTIMATE.start_main_p3)) (or (< v_idx_1303 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1303)) (<= .cse4 v_idx_1303)) (or (= (select |c_#memory_int| v_idx_1301) v_v_5234_2) (<= .cse3 v_idx_1301) (< v_idx_1301 c_ULTIMATE.start_main_p1)) (or (<= c_ULTIMATE.start_main_p3 v_idx_1304) (= (select |c_#memory_int| v_idx_1304) v_v_5237_2) (< v_idx_1304 .cse4)) (<= .cse3 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_1306) v_v_5239_2) (< v_idx_1306 .cse5)))))) (forall ((v_idx_1320 Int) (v_idx_1319 Int) (v_idx_1318 Int) (v_idx_1317 Int) (v_idx_1316 Int) (v_idx_1315 Int) (v_idx_1314 Int)) (exists ((v_b_411_4 Int) (v_b_410_4 Int) (v_b_434_3 Int) (v_v_5239_2 Int) (v_b_407_4 Int) (v_v_5235_2 Int) (v_v_5238_2 Int) (v_v_5237_2 Int) (v_v_5595_2 Int) (v_v_5233_2 Int)) (let ((.cse8 (+ v_b_410_4 1)) (.cse6 (+ c_ULTIMATE.start_main_p2 1)) (.cse7 (+ v_b_434_3 1))) (and (<= .cse6 v_b_410_4) (or (< v_idx_1315 v_b_434_3) (<= v_b_407_4 v_idx_1315) (= (select |c_#memory_int| v_idx_1315) v_v_5595_2)) (<= v_b_407_4 .cse7) (<= .cse7 v_b_407_4) (<= 0 (* 2 v_v_5595_2)) (or (< v_idx_1316 v_b_407_4) (= (select |c_#memory_int| v_idx_1316) v_v_5235_2) (<= c_ULTIMATE.start_main_p2 v_idx_1316)) (<= (+ v_b_434_3 3) v_b_411_4) (<= (+ v_b_407_4 2) v_b_411_4) (<= (+ v_b_407_4 1) v_b_410_4) (or (< v_idx_1318 .cse6) (= (select |c_#memory_int| v_idx_1318) v_v_5237_2) (<= v_b_410_4 v_idx_1318)) (or (< v_idx_1319 v_b_410_4) (= (select |c_#memory_int| v_idx_1319) v_v_5238_2) (<= v_b_411_4 v_idx_1319)) (<= (+ v_b_434_3 2) v_b_410_4) (<= 0 (* 2 v_v_5238_2)) (<= 0 (+ v_v_5238_2 v_v_5595_2)) (<= 0 v_v_5238_2) (<= .cse8 v_b_411_4) (<= v_b_407_4 c_ULTIMATE.start_main_p2) (or (<= v_b_434_3 v_idx_1314) (= (select |c_#memory_int| v_idx_1314) v_v_5233_2)) (<= 0 v_v_5595_2) (or (< v_idx_1320 v_b_411_4) (= (select |c_#memory_int| v_idx_1320) v_v_5239_2)) (<= v_b_411_4 .cse8) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_411_4) (or (<= .cse6 v_idx_1317) (< v_idx_1317 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1317))) (<= .cse7 c_ULTIMATE.start_main_p2))))) (forall ((v_idx_1313 Int) (v_idx_1312 Int) (v_idx_1311 Int) (v_idx_1310 Int) (v_idx_1309 Int) (v_idx_1308 Int) (v_idx_1307 Int)) (exists ((v_b_411_4 Int) (v_b_410_4 Int) (v_v_5239_2 Int) (v_v_5235_2 Int) (v_v_5238_2 Int) (v_v_5237_2 Int) (v_v_5234_2 Int) (v_v_5233_2 Int)) (let ((.cse9 (+ c_ULTIMATE.start_main_p2 1)) (.cse11 (+ v_b_410_4 1)) (.cse10 (+ c_ULTIMATE.start_main_p1 1))) (and (<= .cse9 v_b_410_4) (or (= 0 (select |c_#memory_int| v_idx_1310)) (< v_idx_1310 c_ULTIMATE.start_main_p2) (<= .cse9 v_idx_1310)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_411_4) (<= 0 (+ v_v_5238_2 v_v_5234_2)) (<= 0 v_v_5234_2) (or (< v_idx_1308 c_ULTIMATE.start_main_p1) (<= .cse10 v_idx_1308) (= (select |c_#memory_int| v_idx_1308) v_v_5234_2)) (or (= (select |c_#memory_int| v_idx_1307) v_v_5233_2) (<= c_ULTIMATE.start_main_p1 v_idx_1307)) (or (< v_idx_1309 .cse10) (<= c_ULTIMATE.start_main_p2 v_idx_1309) (= (select |c_#memory_int| v_idx_1309) v_v_5235_2)) (<= 0 (* 2 v_v_5238_2)) (<= 0 (* 2 v_v_5234_2)) (or (= (select |c_#memory_int| v_idx_1312) v_v_5238_2) (< v_idx_1312 v_b_410_4) (<= v_b_411_4 v_idx_1312)) (<= 0 v_v_5238_2) (<= .cse11 v_b_411_4) (or (<= v_b_410_4 v_idx_1311) (< v_idx_1311 .cse9) (= (select |c_#memory_int| v_idx_1311) v_v_5237_2)) (<= v_b_411_4 .cse11) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_411_4) (<= .cse10 c_ULTIMATE.start_main_p2) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_410_4) (or (< v_idx_1313 v_b_411_4) (= (select |c_#memory_int| v_idx_1313) v_v_5239_2))))))) is different from false [2019-01-11 11:49:35,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:49:35,171 INFO L93 Difference]: Finished difference Result 28 states and 81 transitions. [2019-01-11 11:49:35,171 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-11 11:49:35,171 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2019-01-11 11:49:35,171 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:49:35,171 INFO L225 Difference]: With dead ends: 28 [2019-01-11 11:49:35,172 INFO L226 Difference]: Without dead ends: 27 [2019-01-11 11:49:35,172 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.7s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-11 11:49:35,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2019-01-11 11:49:35,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 24. [2019-01-11 11:49:35,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2019-01-11 11:49:35,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 74 transitions. [2019-01-11 11:49:35,197 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 74 transitions. Word has length 5 [2019-01-11 11:49:35,197 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:49:35,197 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 74 transitions. [2019-01-11 11:49:35,197 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-01-11 11:49:35,197 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 74 transitions. [2019-01-11 11:49:35,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-11 11:49:35,197 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:49:35,197 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-11 11:49:35,198 INFO L423 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:49:35,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:49:35,198 INFO L82 PathProgramCache]: Analyzing trace with hash 28943014, now seen corresponding path program 1 times [2019-01-11 11:49:35,198 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:49:35,199 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:49:35,199 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:49:35,199 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:49:35,199 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:49:35,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:49:35,256 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-11 11:49:35,257 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-11 11:49:35,257 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-01-11 11:49:35,257 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:49:35,257 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:49:35,257 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:49:35,257 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-01-11 11:49:35,258 INFO L87 Difference]: Start difference. First operand 24 states and 74 transitions. Second operand 4 states. [2019-01-11 11:49:35,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:49:35,326 INFO L93 Difference]: Finished difference Result 29 states and 78 transitions. [2019-01-11 11:49:35,327 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:49:35,327 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 5 [2019-01-11 11:49:35,327 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:49:35,328 INFO L225 Difference]: With dead ends: 29 [2019-01-11 11:49:35,328 INFO L226 Difference]: Without dead ends: 26 [2019-01-11 11:49:35,328 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2019-01-11 11:49:35,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2019-01-11 11:49:35,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 25. [2019-01-11 11:49:35,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-01-11 11:49:35,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 74 transitions. [2019-01-11 11:49:35,354 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 74 transitions. Word has length 5 [2019-01-11 11:49:35,354 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:49:35,354 INFO L480 AbstractCegarLoop]: Abstraction has 25 states and 74 transitions. [2019-01-11 11:49:35,354 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:49:35,354 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 74 transitions. [2019-01-11 11:49:35,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-11 11:49:35,354 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:49:35,355 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-11 11:49:35,355 INFO L423 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:49:35,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:49:35,355 INFO L82 PathProgramCache]: Analyzing trace with hash 28933340, now seen corresponding path program 2 times [2019-01-11 11:49:35,355 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:49:35,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:49:35,356 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:49:35,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:49:35,356 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:49:35,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:49:35,448 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:49:35,448 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:49:35,449 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:49:35,449 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:49:35,449 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:49:35,449 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:49:35,449 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:49:35,466 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-11 11:49:35,466 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-11 11:49:35,471 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-11 11:49:35,472 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:49:35,472 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:49:35,476 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-11 11:49:35,480 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:35,480 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-11 11:49:35,484 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:35,485 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:35,486 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-11 11:49:35,487 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-11 11:49:35,503 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:49:35,516 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:49:35,528 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:49:35,529 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:19, output treesize:22 [2019-01-11 11:49:35,559 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:35,561 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:35,563 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:35,565 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:35,566 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-11 11:49:35,566 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:49:35,588 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:49:35,588 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-11 11:49:35,611 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:35,613 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:35,615 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:35,640 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:35,645 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:35,646 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:35,647 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 42 [2019-01-11 11:49:35,647 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:49:35,680 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:49:35,681 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:24 [2019-01-11 11:49:35,736 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:49:35,737 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:49:35,758 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:49:35,777 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-11 11:49:35,777 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 9 [2019-01-11 11:49:35,777 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-11 11:49:35,777 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-01-11 11:49:35,777 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-01-11 11:49:35,777 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-01-11 11:49:35,778 INFO L87 Difference]: Start difference. First operand 25 states and 74 transitions. Second operand 8 states. [2019-01-11 11:49:36,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:49:36,079 INFO L93 Difference]: Finished difference Result 39 states and 95 transitions. [2019-01-11 11:49:36,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-01-11 11:49:36,079 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 5 [2019-01-11 11:49:36,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:49:36,080 INFO L225 Difference]: With dead ends: 39 [2019-01-11 11:49:36,080 INFO L226 Difference]: Without dead ends: 37 [2019-01-11 11:49:36,081 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=53, Invalid=79, Unknown=0, NotChecked=0, Total=132 [2019-01-11 11:49:36,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2019-01-11 11:49:36,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 24. [2019-01-11 11:49:36,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2019-01-11 11:49:36,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 71 transitions. [2019-01-11 11:49:36,106 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 71 transitions. Word has length 5 [2019-01-11 11:49:36,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:49:36,106 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 71 transitions. [2019-01-11 11:49:36,106 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-01-11 11:49:36,106 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 71 transitions. [2019-01-11 11:49:36,106 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-11 11:49:36,106 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:49:36,106 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-11 11:49:36,107 INFO L423 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:49:36,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:49:36,107 INFO L82 PathProgramCache]: Analyzing trace with hash 28939106, now seen corresponding path program 1 times [2019-01-11 11:49:36,107 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:49:36,108 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:49:36,108 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:49:36,108 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:49:36,108 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:49:36,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:49:36,190 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:49:36,190 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:49:36,190 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:49:36,190 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-11 11:49:36,191 INFO L207 CegarAbsIntRunner]: [0], [10], [12], [16], [17] [2019-01-11 11:49:36,192 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:49:36,192 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:49:49,504 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:49:49,505 INFO L272 AbstractInterpreter]: Visited 5 different actions 37 times. Merged at 3 different actions 16 times. Widened at 2 different actions 6 times. Found 10 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-11 11:49:49,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:49:49,505 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:49:49,945 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 53.57% of their original sizes. [2019-01-11 11:49:49,945 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:49:52,375 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1456 Int) (v_idx_1455 Int) (v_idx_1454 Int) (v_idx_1453 Int) (v_idx_1459 Int) (v_idx_1458 Int) (v_idx_1457 Int)) (exists ((v_v_4453_4 Int) (v_v_4452_4 Int) (v_v_4455_4 Int) (v_v_4454_4 Int) (v_v_4450_4 Int) (v_v_4456_4 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_1454 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_1454) (= (select |c_#memory_int| v_idx_1454) 0)) (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p2 v_idx_1455) (= (select |c_#memory_int| v_idx_1455) v_v_4452_4) (< v_idx_1455 .cse0)) (or (< v_idx_1459 .cse1) (= (select |c_#memory_int| v_idx_1459) v_v_4456_4)) (or (= (select |c_#memory_int| v_idx_1456) v_v_4453_4) (<= .cse2 v_idx_1456) (< v_idx_1456 c_ULTIMATE.start_main_p2)) (<= 0 v_v_4455_4) (<= v_v_4453_4 0) (or (= (select |c_#memory_int| v_idx_1453) v_v_4450_4) (<= c_ULTIMATE.start_main_p1 v_idx_1453)) (<= (* 2 v_v_4453_4) 0) (<= .cse2 c_ULTIMATE.start_main_p3) (or (< v_idx_1458 c_ULTIMATE.start_main_p3) (<= .cse1 v_idx_1458) (= (select |c_#memory_int| v_idx_1458) v_v_4455_4)) (or (= (select |c_#memory_int| v_idx_1457) v_v_4454_4) (<= c_ULTIMATE.start_main_p3 v_idx_1457) (< v_idx_1457 .cse2)) (<= 0 (* 2 v_v_4455_4)) (<= v_v_4453_4 v_v_4455_4) (<= .cse0 c_ULTIMATE.start_main_p2))))) is different from false [2019-01-11 11:49:54,993 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1466 Int) (v_idx_1465 Int) (v_idx_1464 Int) (v_idx_1463 Int) (v_idx_1462 Int) (v_idx_1461 Int) (v_idx_1460 Int)) (exists ((v_v_4453_4 Int) (v_v_4452_4 Int) (v_v_4455_4 Int) (v_v_4454_4 Int) (v_v_4450_4 Int) (v_v_4456_4 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= (select |c_#memory_int| v_idx_1466) v_v_4456_4) (< v_idx_1466 .cse0)) (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_1461 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_1461)) (<= .cse1 v_idx_1461)) (or (<= c_ULTIMATE.start_main_p2 v_idx_1462) (< v_idx_1462 .cse1) (= (select |c_#memory_int| v_idx_1462) v_v_4452_4)) (<= 0 v_v_4455_4) (or (< v_idx_1463 c_ULTIMATE.start_main_p2) (<= .cse2 v_idx_1463) (= (select |c_#memory_int| v_idx_1463) v_v_4453_4)) (<= v_v_4453_4 0) (<= (* 2 v_v_4453_4) 0) (<= .cse2 c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p3 v_idx_1464) (= (select |c_#memory_int| v_idx_1464) v_v_4454_4) (< v_idx_1464 .cse2)) (or (<= c_ULTIMATE.start_main_p1 v_idx_1460) (= (select |c_#memory_int| v_idx_1460) v_v_4450_4)) (<= 0 (* 2 v_v_4455_4)) (<= v_v_4453_4 v_v_4455_4) (or (<= .cse0 v_idx_1465) (= (select |c_#memory_int| v_idx_1465) v_v_4455_4) (< v_idx_1465 c_ULTIMATE.start_main_p3)) (<= .cse1 c_ULTIMATE.start_main_p2))))) is different from false [2019-01-11 11:49:57,601 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1467 Int) (v_idx_1473 Int) (v_idx_1472 Int) (v_idx_1471 Int) (v_idx_1470 Int) (v_idx_1469 Int) (v_idx_1468 Int)) (exists ((v_v_4453_4 Int) (v_v_4452_4 Int) (v_v_4455_4 Int) (v_v_4454_4 Int) (v_b_349_5 Int) (v_v_4450_4 Int) (v_b_348_5 Int) (v_v_4456_4 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ v_b_348_5 1))) (and (or (<= c_ULTIMATE.start_main_p2 v_idx_1469) (= (select |c_#memory_int| v_idx_1469) v_v_4452_4) (< v_idx_1469 .cse0)) (or (<= v_b_349_5 v_idx_1472) (= (select |c_#memory_int| v_idx_1472) v_v_4455_4) (< v_idx_1472 v_b_348_5)) (<= 0 v_v_4455_4) (<= v_v_4453_4 0) (or (= 0 (select |c_#memory_int| v_idx_1468)) (<= .cse0 v_idx_1468) (< v_idx_1468 c_ULTIMATE.start_main_p1)) (<= (* 2 v_v_4453_4) 0) (or (<= v_b_348_5 v_idx_1471) (= (select |c_#memory_int| v_idx_1471) v_v_4454_4) (< v_idx_1471 .cse1)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_348_5) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_349_5) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_349_5) (<= 0 (* 2 v_v_4455_4)) (or (<= c_ULTIMATE.start_main_p1 v_idx_1467) (= (select |c_#memory_int| v_idx_1467) v_v_4450_4)) (<= v_v_4453_4 v_v_4455_4) (<= .cse0 c_ULTIMATE.start_main_p2) (or (< v_idx_1473 v_b_349_5) (= (select |c_#memory_int| v_idx_1473) v_v_4456_4)) (<= .cse1 v_b_348_5) (<= .cse2 v_b_349_5) (or (< v_idx_1470 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1470) v_v_4453_4) (<= .cse1 v_idx_1470)) (<= v_b_349_5 .cse2))))) is different from false [2019-01-11 11:50:00,324 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1478 Int) (v_idx_1477 Int) (v_idx_1476 Int) (v_idx_1475 Int) (v_idx_1474 Int) (v_idx_1480 Int) (v_idx_1479 Int)) (exists ((v_v_4453_4 Int) (v_v_4452_4 Int) (v_v_4455_4 Int) (v_b_372_5 Int) (v_v_4454_4 Int) (v_b_349_5 Int) (v_v_4450_4 Int) (v_b_348_5 Int) (v_b_345_5 Int) (v_v_4456_4 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_372_5 1)) (.cse2 (+ v_b_348_5 1))) (and (or (<= v_b_349_5 v_idx_1479) (= (select |c_#memory_int| v_idx_1479) v_v_4455_4) (< v_idx_1479 v_b_348_5)) (<= (+ v_b_345_5 2) v_b_349_5) (or (<= .cse0 v_idx_1477) (= (select |c_#memory_int| v_idx_1477) v_v_4453_4) (< v_idx_1477 c_ULTIMATE.start_main_p2)) (<= v_b_345_5 c_ULTIMATE.start_main_p2) (<= 0 v_v_4455_4) (or (< v_idx_1478 .cse0) (<= v_b_348_5 v_idx_1478) (= (select |c_#memory_int| v_idx_1478) v_v_4454_4)) (or (<= c_ULTIMATE.start_main_p2 v_idx_1476) (= (select |c_#memory_int| v_idx_1476) v_v_4452_4) (< v_idx_1476 v_b_345_5)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= v_v_4453_4 0) (<= .cse1 v_b_345_5) (or (< v_idx_1480 v_b_349_5) (= (select |c_#memory_int| v_idx_1480) v_v_4456_4)) (<= (+ v_b_372_5 2) v_b_348_5) (<= (* 2 v_v_4453_4) 0) (<= (+ v_b_345_5 1) v_b_348_5) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_349_5) (<= 0 (* 2 v_v_4455_4)) (or (< v_idx_1475 v_b_372_5) (<= v_b_345_5 v_idx_1475) (= 0 (select |c_#memory_int| v_idx_1475))) (<= v_v_4453_4 v_v_4455_4) (<= (+ v_b_372_5 3) v_b_349_5) (or (= (select |c_#memory_int| v_idx_1474) v_v_4450_4) (<= v_b_372_5 v_idx_1474)) (<= .cse0 v_b_348_5) (<= v_b_345_5 .cse1) (<= .cse2 v_b_349_5) (<= v_b_349_5 .cse2))))) is different from false [2019-01-11 11:50:00,391 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-11 11:50:00,391 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:50:00,391 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:50:00,391 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [3] total 7 [2019-01-11 11:50:00,392 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:50:00,392 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-11 11:50:00,392 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-11 11:50:00,392 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-11 11:50:00,392 INFO L87 Difference]: Start difference. First operand 24 states and 71 transitions. Second operand 6 states. [2019-01-11 11:50:03,032 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_1478 Int) (v_idx_1477 Int) (v_idx_1476 Int) (v_idx_1475 Int) (v_idx_1474 Int) (v_idx_1480 Int) (v_idx_1479 Int)) (exists ((v_v_4453_4 Int) (v_v_4452_4 Int) (v_v_4455_4 Int) (v_b_372_5 Int) (v_v_4454_4 Int) (v_b_349_5 Int) (v_v_4450_4 Int) (v_b_348_5 Int) (v_b_345_5 Int) (v_v_4456_4 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_372_5 1)) (.cse2 (+ v_b_348_5 1))) (and (or (<= v_b_349_5 v_idx_1479) (= (select |c_#memory_int| v_idx_1479) v_v_4455_4) (< v_idx_1479 v_b_348_5)) (<= (+ v_b_345_5 2) v_b_349_5) (or (<= .cse0 v_idx_1477) (= (select |c_#memory_int| v_idx_1477) v_v_4453_4) (< v_idx_1477 c_ULTIMATE.start_main_p2)) (<= v_b_345_5 c_ULTIMATE.start_main_p2) (<= 0 v_v_4455_4) (or (< v_idx_1478 .cse0) (<= v_b_348_5 v_idx_1478) (= (select |c_#memory_int| v_idx_1478) v_v_4454_4)) (or (<= c_ULTIMATE.start_main_p2 v_idx_1476) (= (select |c_#memory_int| v_idx_1476) v_v_4452_4) (< v_idx_1476 v_b_345_5)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= v_v_4453_4 0) (<= .cse1 v_b_345_5) (or (< v_idx_1480 v_b_349_5) (= (select |c_#memory_int| v_idx_1480) v_v_4456_4)) (<= (+ v_b_372_5 2) v_b_348_5) (<= (* 2 v_v_4453_4) 0) (<= (+ v_b_345_5 1) v_b_348_5) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_349_5) (<= 0 (* 2 v_v_4455_4)) (or (< v_idx_1475 v_b_372_5) (<= v_b_345_5 v_idx_1475) (= 0 (select |c_#memory_int| v_idx_1475))) (<= v_v_4453_4 v_v_4455_4) (<= (+ v_b_372_5 3) v_b_349_5) (or (= (select |c_#memory_int| v_idx_1474) v_v_4450_4) (<= v_b_372_5 v_idx_1474)) (<= .cse0 v_b_348_5) (<= v_b_345_5 .cse1) (<= .cse2 v_b_349_5) (<= v_b_349_5 .cse2))))) (forall ((v_idx_1467 Int) (v_idx_1473 Int) (v_idx_1472 Int) (v_idx_1471 Int) (v_idx_1470 Int) (v_idx_1469 Int) (v_idx_1468 Int)) (exists ((v_v_4453_4 Int) (v_v_4452_4 Int) (v_v_4455_4 Int) (v_v_4454_4 Int) (v_b_349_5 Int) (v_v_4450_4 Int) (v_b_348_5 Int) (v_v_4456_4 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 1)) (.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ v_b_348_5 1))) (and (or (<= c_ULTIMATE.start_main_p2 v_idx_1469) (= (select |c_#memory_int| v_idx_1469) v_v_4452_4) (< v_idx_1469 .cse3)) (or (<= v_b_349_5 v_idx_1472) (= (select |c_#memory_int| v_idx_1472) v_v_4455_4) (< v_idx_1472 v_b_348_5)) (<= 0 v_v_4455_4) (<= v_v_4453_4 0) (or (= 0 (select |c_#memory_int| v_idx_1468)) (<= .cse3 v_idx_1468) (< v_idx_1468 c_ULTIMATE.start_main_p1)) (<= (* 2 v_v_4453_4) 0) (or (<= v_b_348_5 v_idx_1471) (= (select |c_#memory_int| v_idx_1471) v_v_4454_4) (< v_idx_1471 .cse4)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_348_5) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_349_5) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_349_5) (<= 0 (* 2 v_v_4455_4)) (or (<= c_ULTIMATE.start_main_p1 v_idx_1467) (= (select |c_#memory_int| v_idx_1467) v_v_4450_4)) (<= v_v_4453_4 v_v_4455_4) (<= .cse3 c_ULTIMATE.start_main_p2) (or (< v_idx_1473 v_b_349_5) (= (select |c_#memory_int| v_idx_1473) v_v_4456_4)) (<= .cse4 v_b_348_5) (<= .cse5 v_b_349_5) (or (< v_idx_1470 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1470) v_v_4453_4) (<= .cse4 v_idx_1470)) (<= v_b_349_5 .cse5))))) (forall ((v_idx_1456 Int) (v_idx_1455 Int) (v_idx_1454 Int) (v_idx_1453 Int) (v_idx_1459 Int) (v_idx_1458 Int) (v_idx_1457 Int)) (exists ((v_v_4453_4 Int) (v_v_4452_4 Int) (v_v_4455_4 Int) (v_v_4454_4 Int) (v_v_4450_4 Int) (v_v_4456_4 Int)) (let ((.cse7 (+ c_ULTIMATE.start_main_p3 1)) (.cse8 (+ c_ULTIMATE.start_main_p2 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_1454 c_ULTIMATE.start_main_p1) (<= .cse6 v_idx_1454) (= (select |c_#memory_int| v_idx_1454) 0)) (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p2 v_idx_1455) (= (select |c_#memory_int| v_idx_1455) v_v_4452_4) (< v_idx_1455 .cse6)) (or (< v_idx_1459 .cse7) (= (select |c_#memory_int| v_idx_1459) v_v_4456_4)) (or (= (select |c_#memory_int| v_idx_1456) v_v_4453_4) (<= .cse8 v_idx_1456) (< v_idx_1456 c_ULTIMATE.start_main_p2)) (<= 0 v_v_4455_4) (<= v_v_4453_4 0) (or (= (select |c_#memory_int| v_idx_1453) v_v_4450_4) (<= c_ULTIMATE.start_main_p1 v_idx_1453)) (<= (* 2 v_v_4453_4) 0) (<= .cse8 c_ULTIMATE.start_main_p3) (or (< v_idx_1458 c_ULTIMATE.start_main_p3) (<= .cse7 v_idx_1458) (= (select |c_#memory_int| v_idx_1458) v_v_4455_4)) (or (= (select |c_#memory_int| v_idx_1457) v_v_4454_4) (<= c_ULTIMATE.start_main_p3 v_idx_1457) (< v_idx_1457 .cse8)) (<= 0 (* 2 v_v_4455_4)) (<= v_v_4453_4 v_v_4455_4) (<= .cse6 c_ULTIMATE.start_main_p2))))) (forall ((v_idx_1466 Int) (v_idx_1465 Int) (v_idx_1464 Int) (v_idx_1463 Int) (v_idx_1462 Int) (v_idx_1461 Int) (v_idx_1460 Int)) (exists ((v_v_4453_4 Int) (v_v_4452_4 Int) (v_v_4455_4 Int) (v_v_4454_4 Int) (v_v_4450_4 Int) (v_v_4456_4 Int)) (let ((.cse11 (+ c_ULTIMATE.start_main_p2 1)) (.cse9 (+ c_ULTIMATE.start_main_p3 1)) (.cse10 (+ c_ULTIMATE.start_main_p1 1))) (and (or (= (select |c_#memory_int| v_idx_1466) v_v_4456_4) (< v_idx_1466 .cse9)) (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_1461 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_1461)) (<= .cse10 v_idx_1461)) (or (<= c_ULTIMATE.start_main_p2 v_idx_1462) (< v_idx_1462 .cse10) (= (select |c_#memory_int| v_idx_1462) v_v_4452_4)) (<= 0 v_v_4455_4) (or (< v_idx_1463 c_ULTIMATE.start_main_p2) (<= .cse11 v_idx_1463) (= (select |c_#memory_int| v_idx_1463) v_v_4453_4)) (<= v_v_4453_4 0) (<= (* 2 v_v_4453_4) 0) (<= .cse11 c_ULTIMATE.start_main_p3) (or (<= c_ULTIMATE.start_main_p3 v_idx_1464) (= (select |c_#memory_int| v_idx_1464) v_v_4454_4) (< v_idx_1464 .cse11)) (or (<= c_ULTIMATE.start_main_p1 v_idx_1460) (= (select |c_#memory_int| v_idx_1460) v_v_4450_4)) (<= 0 (* 2 v_v_4455_4)) (<= v_v_4453_4 v_v_4455_4) (or (<= .cse9 v_idx_1465) (= (select |c_#memory_int| v_idx_1465) v_v_4455_4) (< v_idx_1465 c_ULTIMATE.start_main_p3)) (<= .cse10 c_ULTIMATE.start_main_p2)))))) is different from false [2019-01-11 11:50:17,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:50:17,236 INFO L93 Difference]: Finished difference Result 28 states and 78 transitions. [2019-01-11 11:50:17,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-11 11:50:17,236 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2019-01-11 11:50:17,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:50:17,237 INFO L225 Difference]: With dead ends: 28 [2019-01-11 11:50:17,237 INFO L226 Difference]: Without dead ends: 27 [2019-01-11 11:50:17,237 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.9s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-11 11:50:17,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2019-01-11 11:50:17,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 25. [2019-01-11 11:50:17,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-01-11 11:50:17,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 75 transitions. [2019-01-11 11:50:17,266 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 75 transitions. Word has length 5 [2019-01-11 11:50:17,266 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:50:17,266 INFO L480 AbstractCegarLoop]: Abstraction has 25 states and 75 transitions. [2019-01-11 11:50:17,266 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-01-11 11:50:17,266 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 75 transitions. [2019-01-11 11:50:17,267 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-11 11:50:17,267 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:50:17,267 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-11 11:50:17,267 INFO L423 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:50:17,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:50:17,268 INFO L82 PathProgramCache]: Analyzing trace with hash 29002596, now seen corresponding path program 1 times [2019-01-11 11:50:17,268 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:50:17,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:50:17,269 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:50:17,269 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:50:17,269 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:50:17,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:50:17,292 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:50:17,293 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:50:17,293 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:50:17,293 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-11 11:50:17,293 INFO L207 CegarAbsIntRunner]: [0], [12], [16], [18], [19] [2019-01-11 11:50:17,295 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:50:17,295 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:50:24,325 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:50:24,326 INFO L272 AbstractInterpreter]: Visited 5 different actions 21 times. Merged at 3 different actions 12 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:50:24,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:50:24,326 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:50:24,686 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 53.57% of their original sizes. [2019-01-11 11:50:24,686 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:50:27,108 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1619 Int) (v_idx_1618 Int) (v_idx_1617 Int) (v_idx_1616 Int) (v_idx_1615 Int) (v_idx_1614 Int) (v_idx_1613 Int)) (exists ((v_v_2064_10 Int) (v_v_2068_10 Int) (v_v_2066_10 Int) (v_v_2067_10 Int) (v_v_2062_10 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= 0 (select |c_#memory_int| v_idx_1614)) (< v_idx_1614 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_1614)) (<= 0 v_v_2067_10) (or (< v_idx_1615 .cse0) (= v_v_2064_10 (select |c_#memory_int| v_idx_1615)) (<= c_ULTIMATE.start_main_p2 v_idx_1615)) (or (< v_idx_1617 .cse1) (= v_v_2066_10 (select |c_#memory_int| v_idx_1617)) (<= c_ULTIMATE.start_main_p3 v_idx_1617)) (or (< v_idx_1616 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_1616) (= 0 (select |c_#memory_int| v_idx_1616))) (<= .cse0 c_ULTIMATE.start_main_p2) (or (< v_idx_1618 c_ULTIMATE.start_main_p3) (= v_v_2067_10 (select |c_#memory_int| v_idx_1618)) (<= .cse2 v_idx_1618)) (or (< v_idx_1619 .cse2) (= v_v_2068_10 (select |c_#memory_int| v_idx_1619))) (or (<= c_ULTIMATE.start_main_p1 v_idx_1613) (= v_v_2062_10 (select |c_#memory_int| v_idx_1613))) (<= 0 (* 2 v_v_2067_10)) (<= .cse1 c_ULTIMATE.start_main_p3))))) is different from false [2019-01-11 11:50:29,685 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1621 Int) (v_idx_1620 Int) (v_idx_1626 Int) (v_idx_1625 Int) (v_idx_1624 Int) (v_idx_1623 Int) (v_idx_1622 Int)) (exists ((v_v_2064_10 Int) (v_v_2068_10 Int) (v_v_2066_10 Int) (v_v_2067_10 Int) (v_v_2062_10 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 v_v_2067_10) (or (= v_v_2062_10 (select |c_#memory_int| v_idx_1620)) (<= c_ULTIMATE.start_main_p1 v_idx_1620)) (or (< v_idx_1625 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_1625) v_v_2067_10) (<= .cse0 v_idx_1625)) (or (= (select |c_#memory_int| v_idx_1624) v_v_2066_10) (<= c_ULTIMATE.start_main_p3 v_idx_1624) (< v_idx_1624 .cse1)) (or (< v_idx_1622 .cse2) (<= c_ULTIMATE.start_main_p2 v_idx_1622) (= v_v_2064_10 (select |c_#memory_int| v_idx_1622))) (<= .cse2 c_ULTIMATE.start_main_p2) (or (< v_idx_1621 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1621) 0) (<= .cse2 v_idx_1621)) (or (<= .cse1 v_idx_1623) (< v_idx_1623 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1623))) (or (= v_v_2068_10 (select |c_#memory_int| v_idx_1626)) (< v_idx_1626 .cse0)) (<= 0 (* 2 v_v_2067_10)) (<= .cse1 c_ULTIMATE.start_main_p3))))) is different from false [2019-01-11 11:50:32,391 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1632 Int) (v_idx_1631 Int) (v_idx_1630 Int) (v_idx_1629 Int) (v_idx_1628 Int) (v_idx_1627 Int) (v_idx_1633 Int)) (exists ((v_v_2064_10 Int) (v_v_2068_10 Int) (v_b_158_13 Int) (v_v_2066_10 Int) (v_v_2067_10 Int) (v_v_2062_10 Int) (v_b_143_13 Int)) (let ((.cse2 (+ v_b_158_13 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p3 1))) (and (or (= v_v_2066_10 (select |c_#memory_int| v_idx_1631)) (<= c_ULTIMATE.start_main_p3 v_idx_1631) (< v_idx_1631 .cse0)) (or (= (select |c_#memory_int| v_idx_1633) v_v_2068_10) (< v_idx_1633 .cse1)) (<= .cse2 c_ULTIMATE.start_main_p2) (or (< v_idx_1630 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_1630) (= 0 (select |c_#memory_int| v_idx_1630))) (<= .cse2 v_b_143_13) (or (= 0 (select |c_#memory_int| v_idx_1628)) (< v_idx_1628 v_b_158_13) (<= v_b_143_13 v_idx_1628)) (<= v_b_143_13 .cse2) (or (<= v_b_158_13 v_idx_1627) (= (select |c_#memory_int| v_idx_1627) v_v_2062_10)) (<= .cse0 c_ULTIMATE.start_main_p3) (<= (+ v_b_158_13 2) c_ULTIMATE.start_main_p3) (<= 0 v_v_2067_10) (or (< v_idx_1629 v_b_143_13) (= (select |c_#memory_int| v_idx_1629) v_v_2064_10) (<= c_ULTIMATE.start_main_p2 v_idx_1629)) (<= v_b_143_13 c_ULTIMATE.start_main_p2) (<= (+ v_b_143_13 1) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_2067_10)) (or (< v_idx_1632 c_ULTIMATE.start_main_p3) (<= .cse1 v_idx_1632) (= v_v_2067_10 (select |c_#memory_int| v_idx_1632))))))) is different from false [2019-01-11 11:50:34,635 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1640 Int) (v_idx_1639 Int) (v_idx_1638 Int) (v_idx_1637 Int) (v_idx_1636 Int) (v_idx_1635 Int) (v_idx_1634 Int)) (exists ((v_v_2064_10 Int) (v_b_158_13 Int) (v_v_2068_10 Int) (v_v_2066_10 Int) (v_v_2067_10 Int) (v_v_2062_10 Int) (v_b_143_13 Int) (v_b_145_13 Int) (v_b_170_13 Int)) (let ((.cse2 (+ v_b_158_13 1)) (.cse1 (+ v_b_158_13 2)) (.cse3 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ v_b_170_13 1)) (.cse4 (+ v_b_143_13 1))) (and (<= .cse0 v_b_145_13) (<= .cse1 v_b_145_13) (<= .cse2 v_b_170_13) (or (= v_v_2067_10 (select |c_#memory_int| v_idx_1639)) (<= .cse3 v_idx_1639) (< v_idx_1639 c_ULTIMATE.start_main_p3)) (<= .cse4 v_b_145_13) (<= .cse2 v_b_143_13) (or (= v_v_2066_10 (select |c_#memory_int| v_idx_1638)) (<= c_ULTIMATE.start_main_p3 v_idx_1638) (< v_idx_1638 v_b_145_13)) (<= v_b_143_13 .cse2) (or (= v_v_2064_10 (select |c_#memory_int| v_idx_1636)) (< v_idx_1636 v_b_143_13) (<= v_b_170_13 v_idx_1636)) (<= v_b_145_13 c_ULTIMATE.start_main_p3) (<= .cse1 c_ULTIMATE.start_main_p3) (<= v_b_145_13 .cse0) (<= 0 v_v_2067_10) (or (= v_v_2068_10 (select |c_#memory_int| v_idx_1640)) (< v_idx_1640 .cse3)) (<= v_b_143_13 v_b_170_13) (or (<= v_b_158_13 v_idx_1634) (= (select |c_#memory_int| v_idx_1634) v_v_2062_10)) (<= .cse0 c_ULTIMATE.start_main_p3) (or (= 0 (select |c_#memory_int| v_idx_1637)) (<= v_b_145_13 v_idx_1637) (< v_idx_1637 v_b_170_13)) (<= .cse4 c_ULTIMATE.start_main_p3) (or (< v_idx_1635 v_b_158_13) (= 0 (select |c_#memory_int| v_idx_1635)) (<= v_b_143_13 v_idx_1635)) (<= 0 (* 2 v_v_2067_10)))))) is different from false [2019-01-11 11:50:34,688 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-11 11:50:34,688 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:50:34,689 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:50:34,689 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [2] total 6 [2019-01-11 11:50:34,689 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:50:34,689 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-11 11:50:34,689 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-11 11:50:34,690 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-11 11:50:34,690 INFO L87 Difference]: Start difference. First operand 25 states and 75 transitions. Second operand 6 states. [2019-01-11 11:50:37,190 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_1632 Int) (v_idx_1631 Int) (v_idx_1630 Int) (v_idx_1629 Int) (v_idx_1628 Int) (v_idx_1627 Int) (v_idx_1633 Int)) (exists ((v_v_2064_10 Int) (v_v_2068_10 Int) (v_b_158_13 Int) (v_v_2066_10 Int) (v_v_2067_10 Int) (v_v_2062_10 Int) (v_b_143_13 Int)) (let ((.cse2 (+ v_b_158_13 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p3 1))) (and (or (= v_v_2066_10 (select |c_#memory_int| v_idx_1631)) (<= c_ULTIMATE.start_main_p3 v_idx_1631) (< v_idx_1631 .cse0)) (or (= (select |c_#memory_int| v_idx_1633) v_v_2068_10) (< v_idx_1633 .cse1)) (<= .cse2 c_ULTIMATE.start_main_p2) (or (< v_idx_1630 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_1630) (= 0 (select |c_#memory_int| v_idx_1630))) (<= .cse2 v_b_143_13) (or (= 0 (select |c_#memory_int| v_idx_1628)) (< v_idx_1628 v_b_158_13) (<= v_b_143_13 v_idx_1628)) (<= v_b_143_13 .cse2) (or (<= v_b_158_13 v_idx_1627) (= (select |c_#memory_int| v_idx_1627) v_v_2062_10)) (<= .cse0 c_ULTIMATE.start_main_p3) (<= (+ v_b_158_13 2) c_ULTIMATE.start_main_p3) (<= 0 v_v_2067_10) (or (< v_idx_1629 v_b_143_13) (= (select |c_#memory_int| v_idx_1629) v_v_2064_10) (<= c_ULTIMATE.start_main_p2 v_idx_1629)) (<= v_b_143_13 c_ULTIMATE.start_main_p2) (<= (+ v_b_143_13 1) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_2067_10)) (or (< v_idx_1632 c_ULTIMATE.start_main_p3) (<= .cse1 v_idx_1632) (= v_v_2067_10 (select |c_#memory_int| v_idx_1632))))))) (forall ((v_idx_1640 Int) (v_idx_1639 Int) (v_idx_1638 Int) (v_idx_1637 Int) (v_idx_1636 Int) (v_idx_1635 Int) (v_idx_1634 Int)) (exists ((v_v_2064_10 Int) (v_b_158_13 Int) (v_v_2068_10 Int) (v_v_2066_10 Int) (v_v_2067_10 Int) (v_v_2062_10 Int) (v_b_143_13 Int) (v_b_145_13 Int) (v_b_170_13 Int)) (let ((.cse5 (+ v_b_158_13 1)) (.cse4 (+ v_b_158_13 2)) (.cse6 (+ c_ULTIMATE.start_main_p3 1)) (.cse3 (+ v_b_170_13 1)) (.cse7 (+ v_b_143_13 1))) (and (<= .cse3 v_b_145_13) (<= .cse4 v_b_145_13) (<= .cse5 v_b_170_13) (or (= v_v_2067_10 (select |c_#memory_int| v_idx_1639)) (<= .cse6 v_idx_1639) (< v_idx_1639 c_ULTIMATE.start_main_p3)) (<= .cse7 v_b_145_13) (<= .cse5 v_b_143_13) (or (= v_v_2066_10 (select |c_#memory_int| v_idx_1638)) (<= c_ULTIMATE.start_main_p3 v_idx_1638) (< v_idx_1638 v_b_145_13)) (<= v_b_143_13 .cse5) (or (= v_v_2064_10 (select |c_#memory_int| v_idx_1636)) (< v_idx_1636 v_b_143_13) (<= v_b_170_13 v_idx_1636)) (<= v_b_145_13 c_ULTIMATE.start_main_p3) (<= .cse4 c_ULTIMATE.start_main_p3) (<= v_b_145_13 .cse3) (<= 0 v_v_2067_10) (or (= v_v_2068_10 (select |c_#memory_int| v_idx_1640)) (< v_idx_1640 .cse6)) (<= v_b_143_13 v_b_170_13) (or (<= v_b_158_13 v_idx_1634) (= (select |c_#memory_int| v_idx_1634) v_v_2062_10)) (<= .cse3 c_ULTIMATE.start_main_p3) (or (= 0 (select |c_#memory_int| v_idx_1637)) (<= v_b_145_13 v_idx_1637) (< v_idx_1637 v_b_170_13)) (<= .cse7 c_ULTIMATE.start_main_p3) (or (< v_idx_1635 v_b_158_13) (= 0 (select |c_#memory_int| v_idx_1635)) (<= v_b_143_13 v_idx_1635)) (<= 0 (* 2 v_v_2067_10)))))) (forall ((v_idx_1619 Int) (v_idx_1618 Int) (v_idx_1617 Int) (v_idx_1616 Int) (v_idx_1615 Int) (v_idx_1614 Int) (v_idx_1613 Int)) (exists ((v_v_2064_10 Int) (v_v_2068_10 Int) (v_v_2066_10 Int) (v_v_2067_10 Int) (v_v_2062_10 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse10 (+ c_ULTIMATE.start_main_p3 1)) (.cse9 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= 0 (select |c_#memory_int| v_idx_1614)) (< v_idx_1614 c_ULTIMATE.start_main_p1) (<= .cse8 v_idx_1614)) (<= 0 v_v_2067_10) (or (< v_idx_1615 .cse8) (= v_v_2064_10 (select |c_#memory_int| v_idx_1615)) (<= c_ULTIMATE.start_main_p2 v_idx_1615)) (or (< v_idx_1617 .cse9) (= v_v_2066_10 (select |c_#memory_int| v_idx_1617)) (<= c_ULTIMATE.start_main_p3 v_idx_1617)) (or (< v_idx_1616 c_ULTIMATE.start_main_p2) (<= .cse9 v_idx_1616) (= 0 (select |c_#memory_int| v_idx_1616))) (<= .cse8 c_ULTIMATE.start_main_p2) (or (< v_idx_1618 c_ULTIMATE.start_main_p3) (= v_v_2067_10 (select |c_#memory_int| v_idx_1618)) (<= .cse10 v_idx_1618)) (or (< v_idx_1619 .cse10) (= v_v_2068_10 (select |c_#memory_int| v_idx_1619))) (or (<= c_ULTIMATE.start_main_p1 v_idx_1613) (= v_v_2062_10 (select |c_#memory_int| v_idx_1613))) (<= 0 (* 2 v_v_2067_10)) (<= .cse9 c_ULTIMATE.start_main_p3))))) (forall ((v_idx_1621 Int) (v_idx_1620 Int) (v_idx_1626 Int) (v_idx_1625 Int) (v_idx_1624 Int) (v_idx_1623 Int) (v_idx_1622 Int)) (exists ((v_v_2064_10 Int) (v_v_2068_10 Int) (v_v_2066_10 Int) (v_v_2067_10 Int) (v_v_2062_10 Int)) (let ((.cse13 (+ c_ULTIMATE.start_main_p1 1)) (.cse11 (+ c_ULTIMATE.start_main_p3 1)) (.cse12 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 v_v_2067_10) (or (= v_v_2062_10 (select |c_#memory_int| v_idx_1620)) (<= c_ULTIMATE.start_main_p1 v_idx_1620)) (or (< v_idx_1625 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_1625) v_v_2067_10) (<= .cse11 v_idx_1625)) (or (= (select |c_#memory_int| v_idx_1624) v_v_2066_10) (<= c_ULTIMATE.start_main_p3 v_idx_1624) (< v_idx_1624 .cse12)) (or (< v_idx_1622 .cse13) (<= c_ULTIMATE.start_main_p2 v_idx_1622) (= v_v_2064_10 (select |c_#memory_int| v_idx_1622))) (<= .cse13 c_ULTIMATE.start_main_p2) (or (< v_idx_1621 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1621) 0) (<= .cse13 v_idx_1621)) (or (<= .cse12 v_idx_1623) (< v_idx_1623 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_1623))) (or (= v_v_2068_10 (select |c_#memory_int| v_idx_1626)) (< v_idx_1626 .cse11)) (<= 0 (* 2 v_v_2067_10)) (<= .cse12 c_ULTIMATE.start_main_p3)))))) is different from false [2019-01-11 11:50:49,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:50:49,879 INFO L93 Difference]: Finished difference Result 28 states and 77 transitions. [2019-01-11 11:50:49,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-11 11:50:49,879 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2019-01-11 11:50:49,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:50:49,879 INFO L225 Difference]: With dead ends: 28 [2019-01-11 11:50:49,880 INFO L226 Difference]: Without dead ends: 25 [2019-01-11 11:50:49,880 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.4s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-11 11:50:49,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2019-01-11 11:50:49,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2019-01-11 11:50:49,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-01-11 11:50:49,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 74 transitions. [2019-01-11 11:50:49,909 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 74 transitions. Word has length 5 [2019-01-11 11:50:49,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:50:49,910 INFO L480 AbstractCegarLoop]: Abstraction has 25 states and 74 transitions. [2019-01-11 11:50:49,910 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-01-11 11:50:49,910 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 74 transitions. [2019-01-11 11:50:49,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-11 11:50:49,910 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:50:49,910 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-11 11:50:49,910 INFO L423 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:50:49,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:50:49,911 INFO L82 PathProgramCache]: Analyzing trace with hash 28992922, now seen corresponding path program 2 times [2019-01-11 11:50:49,911 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:50:49,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:50:49,911 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:50:49,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:50:49,912 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:50:49,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:50:50,005 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:50:50,005 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:50:50,005 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:50:50,005 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:50:50,006 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:50:50,006 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:50:50,006 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:50:50,016 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-11 11:50:50,017 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-11 11:50:50,022 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-11 11:50:50,022 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:50:50,023 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:50:50,026 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-11 11:50:50,035 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:50:50,035 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-11 11:50:50,040 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:50:50,043 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:50:50,043 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-11 11:50:50,044 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-11 11:50:50,058 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:50:50,069 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:50:50,078 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:50:50,079 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:19, output treesize:22 [2019-01-11 11:50:50,097 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:50:50,098 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:50:50,099 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:50:50,100 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:50:50,100 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-11 11:50:50,101 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:50:50,119 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:50:50,120 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-11 11:50:50,138 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:50:50,139 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:50:50,140 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:50:50,141 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:50:50,141 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:50:50,142 INFO L683 Elim1Store]: detected equality via solver [2019-01-11 11:50:50,143 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-11 11:50:50,143 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:50:50,163 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:50:50,163 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-11 11:50:50,181 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:50:50,181 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:50:50,223 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:50:50,243 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-11 11:50:50,244 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 9 [2019-01-11 11:50:50,244 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-11 11:50:50,244 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-01-11 11:50:50,244 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-01-11 11:50:50,244 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=67, Unknown=0, NotChecked=0, Total=110 [2019-01-11 11:50:50,245 INFO L87 Difference]: Start difference. First operand 25 states and 74 transitions. Second operand 8 states. [2019-01-11 11:50:50,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:50:50,492 INFO L93 Difference]: Finished difference Result 37 states and 97 transitions. [2019-01-11 11:50:50,492 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-11 11:50:50,492 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 5 [2019-01-11 11:50:50,492 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:50:50,493 INFO L225 Difference]: With dead ends: 37 [2019-01-11 11:50:50,493 INFO L226 Difference]: Without dead ends: 36 [2019-01-11 11:50:50,494 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=61, Invalid=95, Unknown=0, NotChecked=0, Total=156 [2019-01-11 11:50:50,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2019-01-11 11:50:50,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 27. [2019-01-11 11:50:50,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2019-01-11 11:50:50,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 82 transitions. [2019-01-11 11:50:50,527 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 82 transitions. Word has length 5 [2019-01-11 11:50:50,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:50:50,527 INFO L480 AbstractCegarLoop]: Abstraction has 27 states and 82 transitions. [2019-01-11 11:50:50,527 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-01-11 11:50:50,527 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 82 transitions. [2019-01-11 11:50:50,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-11 11:50:50,528 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:50:50,528 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-11 11:50:50,528 INFO L423 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:50:50,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:50:50,528 INFO L82 PathProgramCache]: Analyzing trace with hash 28992734, now seen corresponding path program 1 times [2019-01-11 11:50:50,528 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:50:50,529 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:50:50,529 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:50:50,529 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:50:50,529 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:50:50,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:50:50,752 WARN L181 SmtUtils]: Spent 180.00 ms on a formula simplification. DAG size of input: 32 DAG size of output: 17 [2019-01-11 11:50:50,828 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:50:50,828 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:50:50,828 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:50:50,828 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 6 with the following transitions: [2019-01-11 11:50:50,828 INFO L207 CegarAbsIntRunner]: [0], [6], [10], [12], [15] [2019-01-11 11:50:50,829 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:50:50,829 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:51:09,964 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:51:09,965 INFO L272 AbstractInterpreter]: Visited 5 different actions 57 times. Merged at 3 different actions 13 times. Widened at 3 different actions 9 times. Found 29 fixpoints after 3 different actions. Largest state had 0 variables. [2019-01-11 11:51:09,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:51:09,965 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:51:10,428 INFO L227 lantSequenceWeakener]: Weakened 4 states. On average, predicates are now at 57.14% of their original sizes. [2019-01-11 11:51:10,428 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:51:12,984 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1775 Int) (v_idx_1774 Int) (v_idx_1773 Int) (v_idx_1779 Int) (v_idx_1778 Int) (v_idx_1777 Int) (v_idx_1776 Int)) (exists ((v_v_6178_3 Int) (v_v_6179_3 Int) (v_v_6177_3 Int) (v_v_6181_3 Int) (v_v_6182_3 Int) (v_v_6180_3 Int) (v_v_6183_3 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1))) (and (<= 0 (* 2 v_v_6182_3)) (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= v_v_6180_3 v_v_6178_3) (or (= v_v_6178_3 (select |c_#memory_int| v_idx_1774)) (<= .cse0 v_idx_1774) (< v_idx_1774 c_ULTIMATE.start_main_p1)) (or (< v_idx_1779 .cse1) (= v_v_6183_3 (select |c_#memory_int| v_idx_1779))) (or (< v_idx_1775 .cse0) (<= c_ULTIMATE.start_main_p2 v_idx_1775) (= v_v_6179_3 (select |c_#memory_int| v_idx_1775))) (<= (* 2 v_v_6180_3) 0) (<= .cse2 c_ULTIMATE.start_main_p3) (or (= v_v_6180_3 (select |c_#memory_int| v_idx_1776)) (<= .cse2 v_idx_1776) (< v_idx_1776 c_ULTIMATE.start_main_p2)) (or (< v_idx_1778 c_ULTIMATE.start_main_p3) (<= .cse1 v_idx_1778) (= v_v_6182_3 (select |c_#memory_int| v_idx_1778))) (<= 0 (* 2 v_v_6178_3)) (or (<= c_ULTIMATE.start_main_p1 v_idx_1773) (= v_v_6177_3 (select |c_#memory_int| v_idx_1773))) (<= v_v_6180_3 v_v_6182_3) (<= .cse0 c_ULTIMATE.start_main_p2) (or (< v_idx_1777 .cse2) (= v_v_6181_3 (select |c_#memory_int| v_idx_1777)) (<= c_ULTIMATE.start_main_p3 v_idx_1777)) (<= 0 (+ v_v_6178_3 v_v_6182_3)))))) is different from false [2019-01-11 11:51:15,566 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1786 Int) (v_idx_1785 Int) (v_idx_1784 Int) (v_idx_1783 Int) (v_idx_1782 Int) (v_idx_1781 Int) (v_idx_1780 Int)) (exists ((v_v_6178_3 Int) (v_v_6179_3 Int) (v_v_6177_3 Int) (v_v_6181_3 Int) (v_v_6182_3 Int) (v_b_526_4 Int) (v_v_6180_3 Int) (v_b_527_4 Int) (v_v_6183_3 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_526_4 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= 0 (* 2 v_v_6182_3)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_526_4) (<= v_v_6180_3 v_v_6178_3) (<= .cse0 v_b_526_4) (<= .cse1 v_b_527_4) (<= (* 2 v_v_6180_3) 0) (or (= v_v_6178_3 (select |c_#memory_int| v_idx_1781)) (<= .cse2 v_idx_1781) (< v_idx_1781 c_ULTIMATE.start_main_p1)) (or (< v_idx_1782 .cse2) (= v_v_6179_3 (select |c_#memory_int| v_idx_1782)) (<= c_ULTIMATE.start_main_p2 v_idx_1782)) (or (<= .cse0 v_idx_1783) (< v_idx_1783 c_ULTIMATE.start_main_p2) (= v_v_6180_3 (select |c_#memory_int| v_idx_1783))) (or (< v_idx_1784 .cse0) (<= v_b_526_4 v_idx_1784) (= v_v_6181_3 (select |c_#memory_int| v_idx_1784))) (or (< v_idx_1785 v_b_526_4) (<= v_b_527_4 v_idx_1785) (= v_v_6182_3 (select |c_#memory_int| v_idx_1785))) (or (= v_v_6177_3 (select |c_#memory_int| v_idx_1780)) (<= c_ULTIMATE.start_main_p1 v_idx_1780)) (<= v_b_527_4 .cse1) (<= 0 (* 2 v_v_6178_3)) (<= v_v_6180_3 v_v_6182_3) (or (< v_idx_1786 v_b_527_4) (= v_v_6183_3 (select |c_#memory_int| v_idx_1786))) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_527_4) (<= .cse2 c_ULTIMATE.start_main_p2) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_527_4) (<= 0 (+ v_v_6178_3 v_v_6182_3)))))) is different from false [2019-01-11 11:51:17,800 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1793 Int) (v_idx_1792 Int) (v_idx_1791 Int) (v_idx_1790 Int) (v_idx_1789 Int) (v_idx_1788 Int) (v_idx_1787 Int)) (exists ((v_v_6178_3 Int) (v_v_6179_3 Int) (v_v_6177_3 Int) (v_v_6181_3 Int) (v_v_6182_3 Int) (v_b_526_4 Int) (v_b_527_4 Int) (v_v_6180_3 Int) (v_v_6183_3 Int)) (let ((.cse2 (+ v_b_526_4 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1))) (and (or (< v_idx_1793 v_b_527_4) (= v_v_6183_3 (select |c_#memory_int| v_idx_1793))) (<= 0 (* 2 v_v_6182_3)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_526_4) (or (< v_idx_1791 .cse0) (= v_v_6181_3 (select |c_#memory_int| v_idx_1791)) (<= v_b_526_4 v_idx_1791)) (<= v_v_6180_3 v_v_6178_3) (<= .cse0 v_b_526_4) (or (= v_v_6178_3 (select |c_#memory_int| v_idx_1788)) (< v_idx_1788 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_1788)) (<= .cse2 v_b_527_4) (<= (* 2 v_v_6180_3) 0) (<= v_b_527_4 .cse2) (or (< v_idx_1789 .cse1) (= v_v_6179_3 (select |c_#memory_int| v_idx_1789)) (<= c_ULTIMATE.start_main_p2 v_idx_1789)) (<= 0 (* 2 v_v_6178_3)) (or (<= v_b_527_4 v_idx_1792) (< v_idx_1792 v_b_526_4) (= v_v_6182_3 (select |c_#memory_int| v_idx_1792))) (<= v_v_6180_3 v_v_6182_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_1787) (= v_v_6177_3 (select |c_#memory_int| v_idx_1787))) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_527_4) (<= .cse1 c_ULTIMATE.start_main_p2) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_527_4) (or (= v_v_6180_3 (select |c_#memory_int| v_idx_1790)) (<= .cse0 v_idx_1790) (< v_idx_1790 c_ULTIMATE.start_main_p2)) (<= 0 (+ v_v_6178_3 v_v_6182_3)))))) is different from false [2019-01-11 11:51:20,035 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1797 Int) (v_idx_1796 Int) (v_idx_1795 Int) (v_idx_1794 Int) (v_idx_1800 Int) (v_idx_1799 Int) (v_idx_1798 Int)) (exists ((v_v_6178_3 Int) (v_v_6179_3 Int) (v_v_6177_3 Int) (v_b_524_4 Int) (v_b_525_4 Int) (v_v_6181_3 Int) (v_v_6182_3 Int) (v_b_526_4 Int) (v_b_527_4 Int) (v_v_6180_3 Int) (v_v_6183_3 Int)) (let ((.cse2 (+ v_b_526_4 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_524_4 1))) (and (<= v_b_525_4 v_b_526_4) (or (<= v_b_527_4 v_idx_1799) (< v_idx_1799 v_b_526_4) (= v_v_6182_3 (select |c_#memory_int| v_idx_1799))) (<= 0 (* 2 v_v_6182_3)) (<= .cse0 v_b_526_4) (<= v_v_6180_3 v_v_6178_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_1794) (= v_v_6177_3 (select |c_#memory_int| v_idx_1794))) (or (= v_v_6180_3 (select |c_#memory_int| v_idx_1797)) (<= v_b_525_4 v_idx_1797) (< v_idx_1797 v_b_524_4)) (<= .cse1 v_b_525_4) (<= .cse2 v_b_527_4) (<= (* 2 v_v_6180_3) 0) (or (= v_v_6183_3 (select |c_#memory_int| v_idx_1800)) (< v_idx_1800 v_b_527_4)) (or (< v_idx_1796 .cse3) (<= v_b_524_4 v_idx_1796) (= v_v_6179_3 (select |c_#memory_int| v_idx_1796))) (<= (+ v_b_525_4 1) v_b_527_4) (<= v_b_527_4 .cse2) (<= .cse0 v_b_525_4) (<= 0 (* 2 v_v_6178_3)) (or (< v_idx_1798 v_b_525_4) (<= v_b_526_4 v_idx_1798) (= v_v_6181_3 (select |c_#memory_int| v_idx_1798))) (<= .cse3 v_b_524_4) (or (= v_v_6178_3 (select |c_#memory_int| v_idx_1795)) (<= .cse3 v_idx_1795) (< v_idx_1795 c_ULTIMATE.start_main_p1)) (<= v_v_6180_3 v_v_6182_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_527_4) (<= (+ v_b_524_4 2) v_b_527_4) (<= v_b_525_4 .cse1) (<= .cse1 v_b_526_4) (<= 0 (+ v_v_6178_3 v_v_6182_3)))))) is different from false [2019-01-11 11:51:20,084 INFO L420 sIntCurrentIteration]: We unified 4 AI predicates to 4 [2019-01-11 11:51:20,084 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:51:20,084 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:51:20,084 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 8 [2019-01-11 11:51:20,084 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:51:20,085 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-01-11 11:51:20,085 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-01-11 11:51:20,085 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-11 11:51:20,085 INFO L87 Difference]: Start difference. First operand 27 states and 82 transitions. Second operand 6 states. [2019-01-11 11:51:22,876 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_1786 Int) (v_idx_1785 Int) (v_idx_1784 Int) (v_idx_1783 Int) (v_idx_1782 Int) (v_idx_1781 Int) (v_idx_1780 Int)) (exists ((v_v_6178_3 Int) (v_v_6179_3 Int) (v_v_6177_3 Int) (v_v_6181_3 Int) (v_v_6182_3 Int) (v_b_526_4 Int) (v_v_6180_3 Int) (v_b_527_4 Int) (v_v_6183_3 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_526_4 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= 0 (* 2 v_v_6182_3)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_526_4) (<= v_v_6180_3 v_v_6178_3) (<= .cse0 v_b_526_4) (<= .cse1 v_b_527_4) (<= (* 2 v_v_6180_3) 0) (or (= v_v_6178_3 (select |c_#memory_int| v_idx_1781)) (<= .cse2 v_idx_1781) (< v_idx_1781 c_ULTIMATE.start_main_p1)) (or (< v_idx_1782 .cse2) (= v_v_6179_3 (select |c_#memory_int| v_idx_1782)) (<= c_ULTIMATE.start_main_p2 v_idx_1782)) (or (<= .cse0 v_idx_1783) (< v_idx_1783 c_ULTIMATE.start_main_p2) (= v_v_6180_3 (select |c_#memory_int| v_idx_1783))) (or (< v_idx_1784 .cse0) (<= v_b_526_4 v_idx_1784) (= v_v_6181_3 (select |c_#memory_int| v_idx_1784))) (or (< v_idx_1785 v_b_526_4) (<= v_b_527_4 v_idx_1785) (= v_v_6182_3 (select |c_#memory_int| v_idx_1785))) (or (= v_v_6177_3 (select |c_#memory_int| v_idx_1780)) (<= c_ULTIMATE.start_main_p1 v_idx_1780)) (<= v_b_527_4 .cse1) (<= 0 (* 2 v_v_6178_3)) (<= v_v_6180_3 v_v_6182_3) (or (< v_idx_1786 v_b_527_4) (= v_v_6183_3 (select |c_#memory_int| v_idx_1786))) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_527_4) (<= .cse2 c_ULTIMATE.start_main_p2) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_527_4) (<= 0 (+ v_v_6178_3 v_v_6182_3)))))) (forall ((v_idx_1793 Int) (v_idx_1792 Int) (v_idx_1791 Int) (v_idx_1790 Int) (v_idx_1789 Int) (v_idx_1788 Int) (v_idx_1787 Int)) (exists ((v_v_6178_3 Int) (v_v_6179_3 Int) (v_v_6177_3 Int) (v_v_6181_3 Int) (v_v_6182_3 Int) (v_b_526_4 Int) (v_b_527_4 Int) (v_v_6180_3 Int) (v_v_6183_3 Int)) (let ((.cse5 (+ v_b_526_4 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ c_ULTIMATE.start_main_p2 1))) (and (or (< v_idx_1793 v_b_527_4) (= v_v_6183_3 (select |c_#memory_int| v_idx_1793))) (<= 0 (* 2 v_v_6182_3)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_526_4) (or (< v_idx_1791 .cse3) (= v_v_6181_3 (select |c_#memory_int| v_idx_1791)) (<= v_b_526_4 v_idx_1791)) (<= v_v_6180_3 v_v_6178_3) (<= .cse3 v_b_526_4) (or (= v_v_6178_3 (select |c_#memory_int| v_idx_1788)) (< v_idx_1788 c_ULTIMATE.start_main_p1) (<= .cse4 v_idx_1788)) (<= .cse5 v_b_527_4) (<= (* 2 v_v_6180_3) 0) (<= v_b_527_4 .cse5) (or (< v_idx_1789 .cse4) (= v_v_6179_3 (select |c_#memory_int| v_idx_1789)) (<= c_ULTIMATE.start_main_p2 v_idx_1789)) (<= 0 (* 2 v_v_6178_3)) (or (<= v_b_527_4 v_idx_1792) (< v_idx_1792 v_b_526_4) (= v_v_6182_3 (select |c_#memory_int| v_idx_1792))) (<= v_v_6180_3 v_v_6182_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_1787) (= v_v_6177_3 (select |c_#memory_int| v_idx_1787))) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_527_4) (<= .cse4 c_ULTIMATE.start_main_p2) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_527_4) (or (= v_v_6180_3 (select |c_#memory_int| v_idx_1790)) (<= .cse3 v_idx_1790) (< v_idx_1790 c_ULTIMATE.start_main_p2)) (<= 0 (+ v_v_6178_3 v_v_6182_3)))))) (forall ((v_idx_1775 Int) (v_idx_1774 Int) (v_idx_1773 Int) (v_idx_1779 Int) (v_idx_1778 Int) (v_idx_1777 Int) (v_idx_1776 Int)) (exists ((v_v_6178_3 Int) (v_v_6179_3 Int) (v_v_6177_3 Int) (v_v_6181_3 Int) (v_v_6182_3 Int) (v_v_6180_3 Int) (v_v_6183_3 Int)) (let ((.cse7 (+ c_ULTIMATE.start_main_p3 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 1)) (.cse8 (+ c_ULTIMATE.start_main_p2 1))) (and (<= 0 (* 2 v_v_6182_3)) (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= v_v_6180_3 v_v_6178_3) (or (= v_v_6178_3 (select |c_#memory_int| v_idx_1774)) (<= .cse6 v_idx_1774) (< v_idx_1774 c_ULTIMATE.start_main_p1)) (or (< v_idx_1779 .cse7) (= v_v_6183_3 (select |c_#memory_int| v_idx_1779))) (or (< v_idx_1775 .cse6) (<= c_ULTIMATE.start_main_p2 v_idx_1775) (= v_v_6179_3 (select |c_#memory_int| v_idx_1775))) (<= (* 2 v_v_6180_3) 0) (<= .cse8 c_ULTIMATE.start_main_p3) (or (= v_v_6180_3 (select |c_#memory_int| v_idx_1776)) (<= .cse8 v_idx_1776) (< v_idx_1776 c_ULTIMATE.start_main_p2)) (or (< v_idx_1778 c_ULTIMATE.start_main_p3) (<= .cse7 v_idx_1778) (= v_v_6182_3 (select |c_#memory_int| v_idx_1778))) (<= 0 (* 2 v_v_6178_3)) (or (<= c_ULTIMATE.start_main_p1 v_idx_1773) (= v_v_6177_3 (select |c_#memory_int| v_idx_1773))) (<= v_v_6180_3 v_v_6182_3) (<= .cse6 c_ULTIMATE.start_main_p2) (or (< v_idx_1777 .cse8) (= v_v_6181_3 (select |c_#memory_int| v_idx_1777)) (<= c_ULTIMATE.start_main_p3 v_idx_1777)) (<= 0 (+ v_v_6178_3 v_v_6182_3)))))) (forall ((v_idx_1797 Int) (v_idx_1796 Int) (v_idx_1795 Int) (v_idx_1794 Int) (v_idx_1800 Int) (v_idx_1799 Int) (v_idx_1798 Int)) (exists ((v_v_6178_3 Int) (v_v_6179_3 Int) (v_v_6177_3 Int) (v_b_524_4 Int) (v_b_525_4 Int) (v_v_6181_3 Int) (v_v_6182_3 Int) (v_b_526_4 Int) (v_b_527_4 Int) (v_v_6180_3 Int) (v_v_6183_3 Int)) (let ((.cse11 (+ v_b_526_4 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 2)) (.cse12 (+ c_ULTIMATE.start_main_p1 1)) (.cse10 (+ v_b_524_4 1))) (and (<= v_b_525_4 v_b_526_4) (or (<= v_b_527_4 v_idx_1799) (< v_idx_1799 v_b_526_4) (= v_v_6182_3 (select |c_#memory_int| v_idx_1799))) (<= 0 (* 2 v_v_6182_3)) (<= .cse9 v_b_526_4) (<= v_v_6180_3 v_v_6178_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_1794) (= v_v_6177_3 (select |c_#memory_int| v_idx_1794))) (or (= v_v_6180_3 (select |c_#memory_int| v_idx_1797)) (<= v_b_525_4 v_idx_1797) (< v_idx_1797 v_b_524_4)) (<= .cse10 v_b_525_4) (<= .cse11 v_b_527_4) (<= (* 2 v_v_6180_3) 0) (or (= v_v_6183_3 (select |c_#memory_int| v_idx_1800)) (< v_idx_1800 v_b_527_4)) (or (< v_idx_1796 .cse12) (<= v_b_524_4 v_idx_1796) (= v_v_6179_3 (select |c_#memory_int| v_idx_1796))) (<= (+ v_b_525_4 1) v_b_527_4) (<= v_b_527_4 .cse11) (<= .cse9 v_b_525_4) (<= 0 (* 2 v_v_6178_3)) (or (< v_idx_1798 v_b_525_4) (<= v_b_526_4 v_idx_1798) (= v_v_6181_3 (select |c_#memory_int| v_idx_1798))) (<= .cse12 v_b_524_4) (or (= v_v_6178_3 (select |c_#memory_int| v_idx_1795)) (<= .cse12 v_idx_1795) (< v_idx_1795 c_ULTIMATE.start_main_p1)) (<= v_v_6180_3 v_v_6182_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_527_4) (<= (+ v_b_524_4 2) v_b_527_4) (<= v_b_525_4 .cse10) (<= .cse10 v_b_526_4) (<= 0 (+ v_v_6178_3 v_v_6182_3))))))) is different from false [2019-01-11 11:51:57,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:51:57,796 INFO L93 Difference]: Finished difference Result 31 states and 95 transitions. [2019-01-11 11:51:57,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-11 11:51:57,796 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2019-01-11 11:51:57,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:51:57,796 INFO L225 Difference]: With dead ends: 31 [2019-01-11 11:51:57,796 INFO L226 Difference]: Without dead ends: 30 [2019-01-11 11:51:57,797 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.1s TimeCoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-11 11:51:57,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2019-01-11 11:51:57,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 29. [2019-01-11 11:51:57,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2019-01-11 11:51:57,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 90 transitions. [2019-01-11 11:51:57,838 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 90 transitions. Word has length 5 [2019-01-11 11:51:57,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:51:57,838 INFO L480 AbstractCegarLoop]: Abstraction has 29 states and 90 transitions. [2019-01-11 11:51:57,838 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-01-11 11:51:57,838 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 90 transitions. [2019-01-11 11:51:57,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2019-01-11 11:51:57,839 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:51:57,839 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2019-01-11 11:51:57,839 INFO L423 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:51:57,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:51:57,840 INFO L82 PathProgramCache]: Analyzing trace with hash 28996766, now seen corresponding path program 2 times [2019-01-11 11:51:57,840 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:51:57,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:51:57,840 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:51:57,841 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:51:57,841 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:51:57,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:51:57,903 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:51:57,903 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:51:57,904 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:51:57,904 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:51:57,904 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:51:57,904 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:51:57,904 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:51:57,913 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-11 11:51:57,913 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-11 11:51:57,933 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-11 11:51:57,933 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:51:57,934 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:51:57,937 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-11 11:51:57,940 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 17 [2019-01-11 11:51:57,948 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:57,949 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 20 [2019-01-11 11:51:57,950 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-11 11:51:57,977 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:51:57,986 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:51:57,996 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:51:57,997 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:16, output treesize:19 [2019-01-11 11:51:58,023 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,024 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,025 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 21 [2019-01-11 11:51:58,025 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:51:58,036 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:51:58,036 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:24, output treesize:14 [2019-01-11 11:51:58,052 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,053 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,055 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,056 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,057 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 27 [2019-01-11 11:51:58,057 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:51:58,089 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:51:58,089 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:24, output treesize:14 [2019-01-11 11:51:58,102 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:51:58,102 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:51:58,121 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:51:58,139 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-11 11:51:58,139 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 8 [2019-01-11 11:51:58,140 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-11 11:51:58,140 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-01-11 11:51:58,140 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-01-11 11:51:58,140 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=51, Unknown=0, NotChecked=0, Total=90 [2019-01-11 11:51:58,140 INFO L87 Difference]: Start difference. First operand 29 states and 90 transitions. Second operand 8 states. [2019-01-11 11:51:58,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:51:58,328 INFO L93 Difference]: Finished difference Result 46 states and 132 transitions. [2019-01-11 11:51:58,329 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-01-11 11:51:58,329 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 5 [2019-01-11 11:51:58,329 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:51:58,330 INFO L225 Difference]: With dead ends: 46 [2019-01-11 11:51:58,330 INFO L226 Difference]: Without dead ends: 45 [2019-01-11 11:51:58,330 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=63, Unknown=0, NotChecked=0, Total=110 [2019-01-11 11:51:58,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2019-01-11 11:51:58,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 37. [2019-01-11 11:51:58,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2019-01-11 11:51:58,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 125 transitions. [2019-01-11 11:51:58,370 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 125 transitions. Word has length 5 [2019-01-11 11:51:58,370 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:51:58,370 INFO L480 AbstractCegarLoop]: Abstraction has 37 states and 125 transitions. [2019-01-11 11:51:58,370 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-01-11 11:51:58,370 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 125 transitions. [2019-01-11 11:51:58,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-11 11:51:58,371 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:51:58,371 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1] [2019-01-11 11:51:58,371 INFO L423 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:51:58,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:51:58,371 INFO L82 PathProgramCache]: Analyzing trace with hash 893239506, now seen corresponding path program 2 times [2019-01-11 11:51:58,372 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:51:58,372 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:51:58,372 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:51:58,372 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:51:58,372 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:51:58,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:51:58,437 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-11 11:51:58,437 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:51:58,438 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:51:58,438 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:51:58,438 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:51:58,438 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:51:58,438 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:51:58,448 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-11 11:51:58,449 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-11 11:51:58,453 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-11 11:51:58,453 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:51:58,454 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:51:58,457 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-11 11:51:58,460 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,461 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-11 11:51:58,465 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,466 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,467 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-11 11:51:58,467 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-11 11:51:58,482 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:51:58,490 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:51:58,504 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:51:58,504 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:19, output treesize:22 [2019-01-11 11:51:58,522 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,523 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,524 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,525 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,526 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 28 [2019-01-11 11:51:58,527 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:51:58,560 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:51:58,560 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-11 11:51:58,575 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,576 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,577 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,578 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,579 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,580 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:51:58,581 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 40 [2019-01-11 11:51:58,582 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:51:58,600 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:51:58,601 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-11 11:51:58,616 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:51:58,616 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:51:58,638 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:51:58,656 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2019-01-11 11:51:58,656 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [2, 3] total 8 [2019-01-11 11:51:58,657 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:51:58,657 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-11 11:51:58,657 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-11 11:51:58,657 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=49, Unknown=0, NotChecked=0, Total=90 [2019-01-11 11:51:58,657 INFO L87 Difference]: Start difference. First operand 37 states and 125 transitions. Second operand 5 states. [2019-01-11 11:51:58,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:51:58,738 INFO L93 Difference]: Finished difference Result 40 states and 127 transitions. [2019-01-11 11:51:58,739 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:51:58,739 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 6 [2019-01-11 11:51:58,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:51:58,740 INFO L225 Difference]: With dead ends: 40 [2019-01-11 11:51:58,741 INFO L226 Difference]: Without dead ends: 37 [2019-01-11 11:51:58,741 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=49, Unknown=0, NotChecked=0, Total=90 [2019-01-11 11:51:58,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2019-01-11 11:51:58,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 36. [2019-01-11 11:51:58,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2019-01-11 11:51:58,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 117 transitions. [2019-01-11 11:51:58,779 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 117 transitions. Word has length 6 [2019-01-11 11:51:58,779 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:51:58,780 INFO L480 AbstractCegarLoop]: Abstraction has 36 states and 117 transitions. [2019-01-11 11:51:58,780 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-11 11:51:58,780 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 117 transitions. [2019-01-11 11:51:58,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-11 11:51:58,780 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:51:58,780 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2019-01-11 11:51:58,781 INFO L423 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:51:58,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:51:58,781 INFO L82 PathProgramCache]: Analyzing trace with hash 893358670, now seen corresponding path program 1 times [2019-01-11 11:51:58,781 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:51:58,782 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:51:58,782 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:51:58,782 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:51:58,782 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:51:58,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:51:58,894 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-11 11:51:58,894 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:51:58,894 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:51:58,894 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 7 with the following transitions: [2019-01-11 11:51:58,894 INFO L207 CegarAbsIntRunner]: [0], [6], [10], [16], [18], [19] [2019-01-11 11:51:58,895 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:51:58,895 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:52:16,819 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:52:16,819 INFO L272 AbstractInterpreter]: Visited 6 different actions 46 times. Merged at 4 different actions 24 times. Widened at 2 different actions 6 times. Found 10 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-11 11:52:16,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:52:16,819 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:52:17,450 INFO L227 lantSequenceWeakener]: Weakened 5 states. On average, predicates are now at 51.43% of their original sizes. [2019-01-11 11:52:17,450 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:52:19,911 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1972 Int) (v_idx_1971 Int) (v_idx_1970 Int) (v_idx_1969 Int) (v_idx_1968 Int) (v_idx_1967 Int) (v_idx_1966 Int)) (exists ((v_v_5066_5 Int) (v_v_5063_5 Int) (v_v_5064_5 Int) (v_v_5061_5 Int) (v_v_5062_5 Int) (v_v_5060_5 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= .cse0 v_idx_1971) (= 0 (select |c_#memory_int| v_idx_1971)) (< v_idx_1971 c_ULTIMATE.start_main_p3)) (<= v_v_5063_5 v_v_5061_5) (<= 0 (* 2 v_v_5061_5)) (<= .cse1 c_ULTIMATE.start_main_p3) (<= (* 2 v_v_5063_5) 0) (or (<= c_ULTIMATE.start_main_p2 v_idx_1968) (< v_idx_1968 .cse2) (= (select |c_#memory_int| v_idx_1968) v_v_5062_5)) (or (<= .cse2 v_idx_1967) (< v_idx_1967 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1967) v_v_5061_5)) (or (<= c_ULTIMATE.start_main_p3 v_idx_1970) (= (select |c_#memory_int| v_idx_1970) v_v_5064_5) (< v_idx_1970 .cse1)) (or (<= .cse1 v_idx_1969) (< v_idx_1969 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1969) v_v_5063_5)) (<= .cse2 c_ULTIMATE.start_main_p2) (or (< v_idx_1972 .cse0) (= (select |c_#memory_int| v_idx_1972) v_v_5066_5)) (<= 0 v_v_5061_5) (or (= (select |c_#memory_int| v_idx_1966) v_v_5060_5) (<= c_ULTIMATE.start_main_p1 v_idx_1966)) (<= v_v_5063_5 0))))) is different from false [2019-01-11 11:52:22,515 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1973 Int) (v_idx_1979 Int) (v_idx_1978 Int) (v_idx_1977 Int) (v_idx_1976 Int) (v_idx_1975 Int) (v_idx_1974 Int)) (exists ((v_v_5066_5 Int) (v_v_5063_5 Int) (v_v_5064_5 Int) (v_v_5061_5 Int) (v_v_5062_5 Int) (v_v_5060_5 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_1977) v_v_5064_5) (<= c_ULTIMATE.start_main_p3 v_idx_1977) (< v_idx_1977 .cse0)) (or (= (select |c_#memory_int| v_idx_1978) 0) (<= .cse1 v_idx_1978) (< v_idx_1978 c_ULTIMATE.start_main_p3)) (or (= (select |c_#memory_int| v_idx_1979) v_v_5066_5) (< v_idx_1979 .cse1)) (or (= (select |c_#memory_int| v_idx_1973) v_v_5060_5) (<= c_ULTIMATE.start_main_p1 v_idx_1973)) (<= v_v_5063_5 v_v_5061_5) (<= 0 (* 2 v_v_5061_5)) (or (< v_idx_1974 c_ULTIMATE.start_main_p1) (<= .cse2 v_idx_1974) (= (select |c_#memory_int| v_idx_1974) v_v_5061_5)) (<= .cse0 c_ULTIMATE.start_main_p3) (<= (* 2 v_v_5063_5) 0) (or (= (select |c_#memory_int| v_idx_1975) v_v_5062_5) (< v_idx_1975 .cse2) (<= c_ULTIMATE.start_main_p2 v_idx_1975)) (or (< v_idx_1976 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1976) v_v_5063_5) (<= .cse0 v_idx_1976)) (<= .cse2 c_ULTIMATE.start_main_p2) (<= 0 v_v_5061_5) (<= v_v_5063_5 0))))) is different from false [2019-01-11 11:52:25,153 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1984 Int) (v_idx_1983 Int) (v_idx_1982 Int) (v_idx_1981 Int) (v_idx_1980 Int) (v_idx_1986 Int) (v_idx_1985 Int)) (exists ((v_v_5066_5 Int) (v_v_5063_5 Int) (v_v_5064_5 Int) (v_v_5061_5 Int) (v_v_5062_5 Int) (v_v_5060_5 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= v_v_5063_5 v_v_5061_5) (<= 0 (* 2 v_v_5061_5)) (or (= (select |c_#memory_int| v_idx_1982) v_v_5062_5) (<= c_ULTIMATE.start_main_p2 v_idx_1982) (< v_idx_1982 .cse0)) (or (= (select |c_#memory_int| v_idx_1986) v_v_5066_5) (< v_idx_1986 .cse1)) (<= .cse2 c_ULTIMATE.start_main_p3) (<= (* 2 v_v_5063_5) 0) (or (< v_idx_1984 .cse2) (= (select |c_#memory_int| v_idx_1984) v_v_5064_5) (<= c_ULTIMATE.start_main_p3 v_idx_1984)) (or (= (select |c_#memory_int| v_idx_1985) 0) (< v_idx_1985 c_ULTIMATE.start_main_p3) (<= .cse1 v_idx_1985)) (<= .cse0 c_ULTIMATE.start_main_p2) (or (< v_idx_1981 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_1981) (= (select |c_#memory_int| v_idx_1981) v_v_5061_5)) (<= 0 v_v_5061_5) (or (<= c_ULTIMATE.start_main_p1 v_idx_1980) (= (select |c_#memory_int| v_idx_1980) v_v_5060_5)) (<= v_v_5063_5 0) (or (<= .cse2 v_idx_1983) (< v_idx_1983 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1983) v_v_5063_5)))))) is different from false [2019-01-11 11:52:27,860 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1993 Int) (v_idx_1992 Int) (v_idx_1991 Int) (v_idx_1990 Int) (v_idx_1989 Int) (v_idx_1988 Int) (v_idx_1987 Int)) (exists ((v_b_390_7 Int) (v_v_5066_5 Int) (v_v_5063_5 Int) (v_v_5064_5 Int) (v_v_5794_5 Int) (v_v_5062_5 Int) (v_b_355_7 Int) (v_v_5060_5 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_390_7 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse0 c_ULTIMATE.start_main_p2) (<= v_b_355_7 c_ULTIMATE.start_main_p2) (or (< v_idx_1990 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1990) v_v_5063_5) (<= .cse1 v_idx_1990)) (or (<= v_b_390_7 v_idx_1987) (= (select |c_#memory_int| v_idx_1987) v_v_5060_5)) (<= .cse0 v_b_355_7) (or (< v_idx_1991 .cse1) (<= c_ULTIMATE.start_main_p3 v_idx_1991) (= (select |c_#memory_int| v_idx_1991) v_v_5064_5)) (or (< v_idx_1993 .cse2) (= (select |c_#memory_int| v_idx_1993) v_v_5066_5)) (<= .cse1 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_5794_5)) (<= (* 2 v_v_5063_5) 0) (<= (+ v_b_355_7 1) c_ULTIMATE.start_main_p3) (<= 0 v_v_5794_5) (<= v_v_5063_5 v_v_5794_5) (<= v_b_355_7 .cse0) (or (<= .cse2 v_idx_1992) (= 0 (select |c_#memory_int| v_idx_1992)) (< v_idx_1992 c_ULTIMATE.start_main_p3)) (or (< v_idx_1988 v_b_390_7) (<= v_b_355_7 v_idx_1988) (= v_v_5794_5 (select |c_#memory_int| v_idx_1988))) (or (<= c_ULTIMATE.start_main_p2 v_idx_1989) (< v_idx_1989 v_b_355_7) (= (select |c_#memory_int| v_idx_1989) v_v_5062_5)) (<= (+ v_b_390_7 2) c_ULTIMATE.start_main_p3) (<= v_v_5063_5 0))))) is different from false [2019-01-11 11:52:30,200 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_1995 Int) (v_idx_1994 Int) (v_idx_2000 Int) (v_idx_1999 Int) (v_idx_1998 Int) (v_idx_1997 Int) (v_idx_1996 Int)) (exists ((v_b_390_7 Int) (v_v_5066_5 Int) (v_v_5794_5 Int) (v_v_5064_5 Int) (v_b_357_7 Int) (v_v_5062_5 Int) (v_v_6330_4 Int) (v_b_414_7 Int) (v_b_355_7 Int) (v_v_5060_5 Int)) (let ((.cse0 (+ v_b_355_7 1)) (.cse2 (+ v_b_390_7 1)) (.cse4 (+ c_ULTIMATE.start_main_p3 1)) (.cse3 (+ v_b_414_7 1)) (.cse1 (+ v_b_390_7 2))) (and (<= (* 2 v_v_6330_4) 0) (<= .cse0 v_b_357_7) (or (<= v_b_414_7 v_idx_1996) (< v_idx_1996 v_b_355_7) (= (select |c_#memory_int| v_idx_1996) v_v_5062_5)) (<= v_b_357_7 c_ULTIMATE.start_main_p3) (<= v_b_355_7 v_b_414_7) (<= .cse1 v_b_357_7) (or (< v_idx_1995 v_b_390_7) (<= v_b_355_7 v_idx_1995) (= v_v_5794_5 (select |c_#memory_int| v_idx_1995))) (<= .cse2 v_b_355_7) (<= v_v_6330_4 0) (<= 0 (* 2 v_v_5794_5)) (<= .cse3 v_b_357_7) (or (<= v_b_357_7 v_idx_1997) (= v_v_6330_4 (select |c_#memory_int| v_idx_1997)) (< v_idx_1997 v_b_414_7)) (<= .cse0 c_ULTIMATE.start_main_p3) (<= 0 v_v_5794_5) (<= v_b_355_7 .cse2) (or (= (select |c_#memory_int| v_idx_2000) v_v_5066_5) (< v_idx_2000 .cse4)) (or (= (select |c_#memory_int| v_idx_1998) v_v_5064_5) (<= c_ULTIMATE.start_main_p3 v_idx_1998) (< v_idx_1998 v_b_357_7)) (<= v_b_357_7 .cse3) (<= .cse2 v_b_414_7) (or (<= v_b_390_7 v_idx_1994) (= (select |c_#memory_int| v_idx_1994) v_v_5060_5)) (or (< v_idx_1999 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_1999) 0) (<= .cse4 v_idx_1999)) (<= .cse3 c_ULTIMATE.start_main_p3) (<= .cse1 c_ULTIMATE.start_main_p3) (<= v_v_6330_4 v_v_5794_5))))) is different from false [2019-01-11 11:52:30,260 INFO L420 sIntCurrentIteration]: We unified 5 AI predicates to 5 [2019-01-11 11:52:30,260 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:52:30,260 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:52:30,260 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [3] total 8 [2019-01-11 11:52:30,260 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:52:30,261 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-01-11 11:52:30,261 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-01-11 11:52:30,261 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-11 11:52:30,261 INFO L87 Difference]: Start difference. First operand 36 states and 117 transitions. Second operand 7 states. [2019-01-11 11:52:33,136 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_1995 Int) (v_idx_1994 Int) (v_idx_2000 Int) (v_idx_1999 Int) (v_idx_1998 Int) (v_idx_1997 Int) (v_idx_1996 Int)) (exists ((v_b_390_7 Int) (v_v_5066_5 Int) (v_v_5794_5 Int) (v_v_5064_5 Int) (v_b_357_7 Int) (v_v_5062_5 Int) (v_v_6330_4 Int) (v_b_414_7 Int) (v_b_355_7 Int) (v_v_5060_5 Int)) (let ((.cse0 (+ v_b_355_7 1)) (.cse2 (+ v_b_390_7 1)) (.cse4 (+ c_ULTIMATE.start_main_p3 1)) (.cse3 (+ v_b_414_7 1)) (.cse1 (+ v_b_390_7 2))) (and (<= (* 2 v_v_6330_4) 0) (<= .cse0 v_b_357_7) (or (<= v_b_414_7 v_idx_1996) (< v_idx_1996 v_b_355_7) (= (select |c_#memory_int| v_idx_1996) v_v_5062_5)) (<= v_b_357_7 c_ULTIMATE.start_main_p3) (<= v_b_355_7 v_b_414_7) (<= .cse1 v_b_357_7) (or (< v_idx_1995 v_b_390_7) (<= v_b_355_7 v_idx_1995) (= v_v_5794_5 (select |c_#memory_int| v_idx_1995))) (<= .cse2 v_b_355_7) (<= v_v_6330_4 0) (<= 0 (* 2 v_v_5794_5)) (<= .cse3 v_b_357_7) (or (<= v_b_357_7 v_idx_1997) (= v_v_6330_4 (select |c_#memory_int| v_idx_1997)) (< v_idx_1997 v_b_414_7)) (<= .cse0 c_ULTIMATE.start_main_p3) (<= 0 v_v_5794_5) (<= v_b_355_7 .cse2) (or (= (select |c_#memory_int| v_idx_2000) v_v_5066_5) (< v_idx_2000 .cse4)) (or (= (select |c_#memory_int| v_idx_1998) v_v_5064_5) (<= c_ULTIMATE.start_main_p3 v_idx_1998) (< v_idx_1998 v_b_357_7)) (<= v_b_357_7 .cse3) (<= .cse2 v_b_414_7) (or (<= v_b_390_7 v_idx_1994) (= (select |c_#memory_int| v_idx_1994) v_v_5060_5)) (or (< v_idx_1999 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_1999) 0) (<= .cse4 v_idx_1999)) (<= .cse3 c_ULTIMATE.start_main_p3) (<= .cse1 c_ULTIMATE.start_main_p3) (<= v_v_6330_4 v_v_5794_5))))) (forall ((v_idx_1973 Int) (v_idx_1979 Int) (v_idx_1978 Int) (v_idx_1977 Int) (v_idx_1976 Int) (v_idx_1975 Int) (v_idx_1974 Int)) (exists ((v_v_5066_5 Int) (v_v_5063_5 Int) (v_v_5064_5 Int) (v_v_5061_5 Int) (v_v_5062_5 Int) (v_v_5060_5 Int)) (let ((.cse6 (+ c_ULTIMATE.start_main_p3 1)) (.cse5 (+ c_ULTIMATE.start_main_p2 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_1977) v_v_5064_5) (<= c_ULTIMATE.start_main_p3 v_idx_1977) (< v_idx_1977 .cse5)) (or (= (select |c_#memory_int| v_idx_1978) 0) (<= .cse6 v_idx_1978) (< v_idx_1978 c_ULTIMATE.start_main_p3)) (or (= (select |c_#memory_int| v_idx_1979) v_v_5066_5) (< v_idx_1979 .cse6)) (or (= (select |c_#memory_int| v_idx_1973) v_v_5060_5) (<= c_ULTIMATE.start_main_p1 v_idx_1973)) (<= v_v_5063_5 v_v_5061_5) (<= 0 (* 2 v_v_5061_5)) (or (< v_idx_1974 c_ULTIMATE.start_main_p1) (<= .cse7 v_idx_1974) (= (select |c_#memory_int| v_idx_1974) v_v_5061_5)) (<= .cse5 c_ULTIMATE.start_main_p3) (<= (* 2 v_v_5063_5) 0) (or (= (select |c_#memory_int| v_idx_1975) v_v_5062_5) (< v_idx_1975 .cse7) (<= c_ULTIMATE.start_main_p2 v_idx_1975)) (or (< v_idx_1976 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1976) v_v_5063_5) (<= .cse5 v_idx_1976)) (<= .cse7 c_ULTIMATE.start_main_p2) (<= 0 v_v_5061_5) (<= v_v_5063_5 0))))) (forall ((v_idx_1972 Int) (v_idx_1971 Int) (v_idx_1970 Int) (v_idx_1969 Int) (v_idx_1968 Int) (v_idx_1967 Int) (v_idx_1966 Int)) (exists ((v_v_5066_5 Int) (v_v_5063_5 Int) (v_v_5064_5 Int) (v_v_5061_5 Int) (v_v_5062_5 Int) (v_v_5060_5 Int)) (let ((.cse9 (+ c_ULTIMATE.start_main_p2 1)) (.cse10 (+ c_ULTIMATE.start_main_p1 1)) (.cse8 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= .cse8 v_idx_1971) (= 0 (select |c_#memory_int| v_idx_1971)) (< v_idx_1971 c_ULTIMATE.start_main_p3)) (<= v_v_5063_5 v_v_5061_5) (<= 0 (* 2 v_v_5061_5)) (<= .cse9 c_ULTIMATE.start_main_p3) (<= (* 2 v_v_5063_5) 0) (or (<= c_ULTIMATE.start_main_p2 v_idx_1968) (< v_idx_1968 .cse10) (= (select |c_#memory_int| v_idx_1968) v_v_5062_5)) (or (<= .cse10 v_idx_1967) (< v_idx_1967 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_1967) v_v_5061_5)) (or (<= c_ULTIMATE.start_main_p3 v_idx_1970) (= (select |c_#memory_int| v_idx_1970) v_v_5064_5) (< v_idx_1970 .cse9)) (or (<= .cse9 v_idx_1969) (< v_idx_1969 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1969) v_v_5063_5)) (<= .cse10 c_ULTIMATE.start_main_p2) (or (< v_idx_1972 .cse8) (= (select |c_#memory_int| v_idx_1972) v_v_5066_5)) (<= 0 v_v_5061_5) (or (= (select |c_#memory_int| v_idx_1966) v_v_5060_5) (<= c_ULTIMATE.start_main_p1 v_idx_1966)) (<= v_v_5063_5 0))))) (forall ((v_idx_1984 Int) (v_idx_1983 Int) (v_idx_1982 Int) (v_idx_1981 Int) (v_idx_1980 Int) (v_idx_1986 Int) (v_idx_1985 Int)) (exists ((v_v_5066_5 Int) (v_v_5063_5 Int) (v_v_5064_5 Int) (v_v_5061_5 Int) (v_v_5062_5 Int) (v_v_5060_5 Int)) (let ((.cse12 (+ c_ULTIMATE.start_main_p3 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 1)) (.cse13 (+ c_ULTIMATE.start_main_p2 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= v_v_5063_5 v_v_5061_5) (<= 0 (* 2 v_v_5061_5)) (or (= (select |c_#memory_int| v_idx_1982) v_v_5062_5) (<= c_ULTIMATE.start_main_p2 v_idx_1982) (< v_idx_1982 .cse11)) (or (= (select |c_#memory_int| v_idx_1986) v_v_5066_5) (< v_idx_1986 .cse12)) (<= .cse13 c_ULTIMATE.start_main_p3) (<= (* 2 v_v_5063_5) 0) (or (< v_idx_1984 .cse13) (= (select |c_#memory_int| v_idx_1984) v_v_5064_5) (<= c_ULTIMATE.start_main_p3 v_idx_1984)) (or (= (select |c_#memory_int| v_idx_1985) 0) (< v_idx_1985 c_ULTIMATE.start_main_p3) (<= .cse12 v_idx_1985)) (<= .cse11 c_ULTIMATE.start_main_p2) (or (< v_idx_1981 c_ULTIMATE.start_main_p1) (<= .cse11 v_idx_1981) (= (select |c_#memory_int| v_idx_1981) v_v_5061_5)) (<= 0 v_v_5061_5) (or (<= c_ULTIMATE.start_main_p1 v_idx_1980) (= (select |c_#memory_int| v_idx_1980) v_v_5060_5)) (<= v_v_5063_5 0) (or (<= .cse13 v_idx_1983) (< v_idx_1983 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1983) v_v_5063_5)))))) (forall ((v_idx_1993 Int) (v_idx_1992 Int) (v_idx_1991 Int) (v_idx_1990 Int) (v_idx_1989 Int) (v_idx_1988 Int) (v_idx_1987 Int)) (exists ((v_b_390_7 Int) (v_v_5066_5 Int) (v_v_5063_5 Int) (v_v_5064_5 Int) (v_v_5794_5 Int) (v_v_5062_5 Int) (v_b_355_7 Int) (v_v_5060_5 Int)) (let ((.cse15 (+ c_ULTIMATE.start_main_p2 1)) (.cse14 (+ v_b_390_7 1)) (.cse16 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse14 c_ULTIMATE.start_main_p2) (<= v_b_355_7 c_ULTIMATE.start_main_p2) (or (< v_idx_1990 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_1990) v_v_5063_5) (<= .cse15 v_idx_1990)) (or (<= v_b_390_7 v_idx_1987) (= (select |c_#memory_int| v_idx_1987) v_v_5060_5)) (<= .cse14 v_b_355_7) (or (< v_idx_1991 .cse15) (<= c_ULTIMATE.start_main_p3 v_idx_1991) (= (select |c_#memory_int| v_idx_1991) v_v_5064_5)) (or (< v_idx_1993 .cse16) (= (select |c_#memory_int| v_idx_1993) v_v_5066_5)) (<= .cse15 c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_5794_5)) (<= (* 2 v_v_5063_5) 0) (<= (+ v_b_355_7 1) c_ULTIMATE.start_main_p3) (<= 0 v_v_5794_5) (<= v_v_5063_5 v_v_5794_5) (<= v_b_355_7 .cse14) (or (<= .cse16 v_idx_1992) (= 0 (select |c_#memory_int| v_idx_1992)) (< v_idx_1992 c_ULTIMATE.start_main_p3)) (or (< v_idx_1988 v_b_390_7) (<= v_b_355_7 v_idx_1988) (= v_v_5794_5 (select |c_#memory_int| v_idx_1988))) (or (<= c_ULTIMATE.start_main_p2 v_idx_1989) (< v_idx_1989 v_b_355_7) (= (select |c_#memory_int| v_idx_1989) v_v_5062_5)) (<= (+ v_b_390_7 2) c_ULTIMATE.start_main_p3) (<= v_v_5063_5 0)))))) is different from false [2019-01-11 11:53:15,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:53:15,919 INFO L93 Difference]: Finished difference Result 41 states and 126 transitions. [2019-01-11 11:53:15,919 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-01-11 11:53:15,919 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 6 [2019-01-11 11:53:15,919 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:53:15,920 INFO L225 Difference]: With dead ends: 41 [2019-01-11 11:53:15,920 INFO L226 Difference]: Without dead ends: 38 [2019-01-11 11:53:15,921 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 15.1s TimeCoverageRelationStatistics Valid=13, Invalid=7, Unknown=6, NotChecked=30, Total=56 [2019-01-11 11:53:15,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2019-01-11 11:53:15,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 38. [2019-01-11 11:53:15,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2019-01-11 11:53:15,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 123 transitions. [2019-01-11 11:53:15,970 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 123 transitions. Word has length 6 [2019-01-11 11:53:15,970 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:53:15,970 INFO L480 AbstractCegarLoop]: Abstraction has 38 states and 123 transitions. [2019-01-11 11:53:15,970 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-01-11 11:53:15,970 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 123 transitions. [2019-01-11 11:53:15,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-11 11:53:15,970 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:53:15,970 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2019-01-11 11:53:15,971 INFO L423 AbstractCegarLoop]: === Iteration 29 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:53:15,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:53:15,971 INFO L82 PathProgramCache]: Analyzing trace with hash 893354762, now seen corresponding path program 1 times [2019-01-11 11:53:15,971 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:53:15,971 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:53:15,972 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:53:15,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:53:15,972 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:53:15,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:53:16,115 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-11 11:53:16,115 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:53:16,115 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:53:16,115 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 7 with the following transitions: [2019-01-11 11:53:16,116 INFO L207 CegarAbsIntRunner]: [0], [6], [10], [12], [16], [17] [2019-01-11 11:53:16,117 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:53:16,117 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:53:44,056 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:53:44,056 INFO L272 AbstractInterpreter]: Visited 6 different actions 66 times. Merged at 4 different actions 24 times. Widened at 3 different actions 9 times. Found 27 fixpoints after 3 different actions. Largest state had 0 variables. [2019-01-11 11:53:44,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:53:44,056 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:53:44,812 INFO L227 lantSequenceWeakener]: Weakened 5 states. On average, predicates are now at 51.43% of their original sizes. [2019-01-11 11:53:44,812 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:53:47,330 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2169 Int) (v_idx_2168 Int) (v_idx_2167 Int) (v_idx_2166 Int) (v_idx_2172 Int) (v_idx_2171 Int) (v_idx_2170 Int)) (exists ((v_v_7539_2 Int) (v_v_7538_2 Int) (v_v_7533_2 Int) (v_v_7535_2 Int) (v_v_7534_2 Int) (v_v_7537_2 Int) (v_v_7536_2 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_7538_2)) (or (<= c_ULTIMATE.start_main_p1 v_idx_2166) (= v_v_7533_2 (select |c_#memory_int| v_idx_2166))) (<= 0 (* 2 v_v_7534_2)) (<= v_v_7536_2 v_v_7538_2) (or (< v_idx_2168 .cse0) (= (select |c_#memory_int| v_idx_2168) v_v_7535_2) (<= c_ULTIMATE.start_main_p2 v_idx_2168)) (<= 0 (+ v_v_7538_2 v_v_7534_2)) (<= .cse1 c_ULTIMATE.start_main_p3) (or (= v_v_7536_2 (select |c_#memory_int| v_idx_2169)) (<= .cse1 v_idx_2169) (< v_idx_2169 c_ULTIMATE.start_main_p2)) (or (<= .cse2 v_idx_2171) (< v_idx_2171 c_ULTIMATE.start_main_p3) (= v_v_7538_2 (select |c_#memory_int| v_idx_2171))) (<= v_v_7536_2 v_v_7534_2) (or (= v_v_7534_2 (select |c_#memory_int| v_idx_2167)) (<= .cse0 v_idx_2167) (< v_idx_2167 c_ULTIMATE.start_main_p1)) (or (= v_v_7537_2 (select |c_#memory_int| v_idx_2170)) (<= c_ULTIMATE.start_main_p3 v_idx_2170) (< v_idx_2170 .cse1)) (or (< v_idx_2172 .cse2) (= v_v_7539_2 (select |c_#memory_int| v_idx_2172))) (<= .cse0 c_ULTIMATE.start_main_p2) (<= (* 2 v_v_7536_2) 0))))) is different from false [2019-01-11 11:53:49,937 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2179 Int) (v_idx_2178 Int) (v_idx_2177 Int) (v_idx_2176 Int) (v_idx_2175 Int) (v_idx_2174 Int) (v_idx_2173 Int)) (exists ((v_v_7539_2 Int) (v_v_7538_2 Int) (v_v_7533_2 Int) (v_v_7535_2 Int) (v_v_7534_2 Int) (v_v_7537_2 Int) (v_v_7536_2 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_7538_2)) (or (= v_v_7534_2 (select |c_#memory_int| v_idx_2174)) (< v_idx_2174 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_2174)) (<= 0 (* 2 v_v_7534_2)) (<= v_v_7536_2 v_v_7538_2) (or (<= .cse1 v_idx_2178) (< v_idx_2178 c_ULTIMATE.start_main_p3) (= v_v_7538_2 (select |c_#memory_int| v_idx_2178))) (<= 0 (+ v_v_7538_2 v_v_7534_2)) (<= .cse2 c_ULTIMATE.start_main_p3) (<= v_v_7536_2 v_v_7534_2) (or (= v_v_7539_2 (select |c_#memory_int| v_idx_2179)) (< v_idx_2179 .cse1)) (or (<= .cse2 v_idx_2176) (< v_idx_2176 c_ULTIMATE.start_main_p2) (= v_v_7536_2 (select |c_#memory_int| v_idx_2176))) (or (< v_idx_2175 .cse0) (<= c_ULTIMATE.start_main_p2 v_idx_2175) (= v_v_7535_2 (select |c_#memory_int| v_idx_2175))) (or (= v_v_7537_2 (select |c_#memory_int| v_idx_2177)) (<= c_ULTIMATE.start_main_p3 v_idx_2177) (< v_idx_2177 .cse2)) (<= .cse0 c_ULTIMATE.start_main_p2) (<= (* 2 v_v_7536_2) 0) (or (= v_v_7533_2 (select |c_#memory_int| v_idx_2173)) (<= c_ULTIMATE.start_main_p1 v_idx_2173)))))) is different from false [2019-01-11 11:53:52,600 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2186 Int) (v_idx_2185 Int) (v_idx_2184 Int) (v_idx_2183 Int) (v_idx_2182 Int) (v_idx_2181 Int) (v_idx_2180 Int)) (exists ((v_v_7539_2 Int) (v_v_7538_2 Int) (v_v_7533_2 Int) (v_v_7535_2 Int) (v_v_7534_2 Int) (v_v_7537_2 Int) (v_v_7536_2 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_7538_2)) (or (<= .cse0 v_idx_2183) (< v_idx_2183 c_ULTIMATE.start_main_p2) (= v_v_7536_2 (select |c_#memory_int| v_idx_2183))) (or (<= c_ULTIMATE.start_main_p1 v_idx_2180) (= v_v_7533_2 (select |c_#memory_int| v_idx_2180))) (<= 0 (* 2 v_v_7534_2)) (or (= v_v_7539_2 (select |c_#memory_int| v_idx_2186)) (< v_idx_2186 .cse1)) (<= v_v_7536_2 v_v_7538_2) (or (<= .cse2 v_idx_2181) (< v_idx_2181 c_ULTIMATE.start_main_p1) (= v_v_7534_2 (select |c_#memory_int| v_idx_2181))) (<= 0 (+ v_v_7538_2 v_v_7534_2)) (<= .cse0 c_ULTIMATE.start_main_p3) (<= v_v_7536_2 v_v_7534_2) (or (<= c_ULTIMATE.start_main_p2 v_idx_2182) (= v_v_7535_2 (select |c_#memory_int| v_idx_2182)) (< v_idx_2182 .cse2)) (or (<= c_ULTIMATE.start_main_p3 v_idx_2184) (= v_v_7537_2 (select |c_#memory_int| v_idx_2184)) (< v_idx_2184 .cse0)) (<= .cse2 c_ULTIMATE.start_main_p2) (<= (* 2 v_v_7536_2) 0) (or (<= .cse1 v_idx_2185) (< v_idx_2185 c_ULTIMATE.start_main_p3) (= v_v_7538_2 (select |c_#memory_int| v_idx_2185))))))) is different from false [2019-01-11 11:53:54,855 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2189 Int) (v_idx_2188 Int) (v_idx_2187 Int) (v_idx_2193 Int) (v_idx_2192 Int) (v_idx_2191 Int) (v_idx_2190 Int)) (exists ((v_v_7539_2 Int) (v_v_7538_2 Int) (v_b_551_5 Int) (v_b_550_5 Int) (v_v_7533_2 Int) (v_v_7535_2 Int) (v_v_7534_2 Int) (v_v_7537_2 Int) (v_v_7536_2 Int)) (let ((.cse0 (+ v_b_550_5 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_551_5 .cse0) (<= 0 (* 2 v_v_7538_2)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_550_5) (<= .cse1 v_b_550_5) (or (= v_v_7533_2 (select |c_#memory_int| v_idx_2187)) (<= c_ULTIMATE.start_main_p1 v_idx_2187)) (<= 0 (* 2 v_v_7534_2)) (<= v_v_7536_2 v_v_7538_2) (or (<= .cse1 v_idx_2190) (= v_v_7536_2 (select |c_#memory_int| v_idx_2190)) (< v_idx_2190 c_ULTIMATE.start_main_p2)) (<= .cse0 v_b_551_5) (or (<= .cse2 v_idx_2188) (= v_v_7534_2 (select |c_#memory_int| v_idx_2188)) (< v_idx_2188 c_ULTIMATE.start_main_p1)) (or (= v_v_7539_2 (select |c_#memory_int| v_idx_2193)) (< v_idx_2193 v_b_551_5)) (<= 0 (+ v_v_7538_2 v_v_7534_2)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_551_5) (or (< v_idx_2189 .cse2) (= v_v_7535_2 (select |c_#memory_int| v_idx_2189)) (<= c_ULTIMATE.start_main_p2 v_idx_2189)) (or (= v_v_7538_2 (select |c_#memory_int| v_idx_2192)) (< v_idx_2192 v_b_550_5) (<= v_b_551_5 v_idx_2192)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_551_5) (<= v_v_7536_2 v_v_7534_2) (or (= v_v_7537_2 (select |c_#memory_int| v_idx_2191)) (< v_idx_2191 .cse1) (<= v_b_550_5 v_idx_2191)) (<= .cse2 c_ULTIMATE.start_main_p2) (<= (* 2 v_v_7536_2) 0))))) is different from false [2019-01-11 11:53:56,910 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2200 Int) (v_idx_2199 Int) (v_idx_2198 Int) (v_idx_2197 Int) (v_idx_2196 Int) (v_idx_2195 Int) (v_idx_2194 Int)) (exists ((v_v_7539_2 Int) (v_v_7538_2 Int) (v_b_551_5 Int) (v_b_550_5 Int) (v_v_8361_1 Int) (v_b_598_5 Int) (v_v_7533_2 Int) (v_b_547_5 Int) (v_v_7535_2 Int) (v_v_7537_2 Int) (v_v_7536_2 Int)) (let ((.cse2 (+ v_b_598_5 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_550_5 1))) (and (<= (+ v_b_598_5 3) v_b_551_5) (<= v_b_551_5 .cse0) (<= .cse1 v_b_550_5) (<= .cse2 v_b_547_5) (<= .cse2 c_ULTIMATE.start_main_p2) (or (<= v_b_547_5 v_idx_2195) (= v_v_8361_1 (select |c_#memory_int| v_idx_2195)) (< v_idx_2195 v_b_598_5)) (<= v_b_547_5 .cse2) (<= v_v_7536_2 v_v_7538_2) (or (= v_v_7537_2 (select |c_#memory_int| v_idx_2198)) (< v_idx_2198 .cse1) (<= v_b_550_5 v_idx_2198)) (or (<= v_b_551_5 v_idx_2199) (= v_v_7538_2 (select |c_#memory_int| v_idx_2199)) (< v_idx_2199 v_b_550_5)) (or (< v_idx_2196 v_b_547_5) (<= c_ULTIMATE.start_main_p2 v_idx_2196) (= v_v_7535_2 (select |c_#memory_int| v_idx_2196))) (<= (+ v_b_547_5 1) v_b_550_5) (<= 0 (+ v_v_7538_2 v_v_8361_1)) (<= (* 2 v_v_7536_2) 0) (or (= v_v_7536_2 (select |c_#memory_int| v_idx_2197)) (< v_idx_2197 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_2197)) (<= 0 (* 2 v_v_7538_2)) (<= v_v_7536_2 v_v_8361_1) (<= (+ v_b_547_5 2) v_b_551_5) (<= .cse0 v_b_551_5) (<= (+ v_b_598_5 2) v_b_550_5) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_551_5) (<= v_b_547_5 c_ULTIMATE.start_main_p2) (or (<= v_b_598_5 v_idx_2194) (= v_v_7533_2 (select |c_#memory_int| v_idx_2194))) (or (< v_idx_2200 v_b_551_5) (= v_v_7539_2 (select |c_#memory_int| v_idx_2200))) (<= 0 (* 2 v_v_8361_1)))))) is different from false [2019-01-11 11:53:56,923 INFO L420 sIntCurrentIteration]: We unified 5 AI predicates to 5 [2019-01-11 11:53:56,924 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:53:56,924 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:53:56,924 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [4] total 9 [2019-01-11 11:53:56,924 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:53:56,924 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-01-11 11:53:56,924 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-01-11 11:53:56,925 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-11 11:53:56,925 INFO L87 Difference]: Start difference. First operand 38 states and 123 transitions. Second operand 7 states. [2019-01-11 11:54:00,133 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_2179 Int) (v_idx_2178 Int) (v_idx_2177 Int) (v_idx_2176 Int) (v_idx_2175 Int) (v_idx_2174 Int) (v_idx_2173 Int)) (exists ((v_v_7539_2 Int) (v_v_7538_2 Int) (v_v_7533_2 Int) (v_v_7535_2 Int) (v_v_7534_2 Int) (v_v_7537_2 Int) (v_v_7536_2 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p3 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_7538_2)) (or (= v_v_7534_2 (select |c_#memory_int| v_idx_2174)) (< v_idx_2174 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_2174)) (<= 0 (* 2 v_v_7534_2)) (<= v_v_7536_2 v_v_7538_2) (or (<= .cse1 v_idx_2178) (< v_idx_2178 c_ULTIMATE.start_main_p3) (= v_v_7538_2 (select |c_#memory_int| v_idx_2178))) (<= 0 (+ v_v_7538_2 v_v_7534_2)) (<= .cse2 c_ULTIMATE.start_main_p3) (<= v_v_7536_2 v_v_7534_2) (or (= v_v_7539_2 (select |c_#memory_int| v_idx_2179)) (< v_idx_2179 .cse1)) (or (<= .cse2 v_idx_2176) (< v_idx_2176 c_ULTIMATE.start_main_p2) (= v_v_7536_2 (select |c_#memory_int| v_idx_2176))) (or (< v_idx_2175 .cse0) (<= c_ULTIMATE.start_main_p2 v_idx_2175) (= v_v_7535_2 (select |c_#memory_int| v_idx_2175))) (or (= v_v_7537_2 (select |c_#memory_int| v_idx_2177)) (<= c_ULTIMATE.start_main_p3 v_idx_2177) (< v_idx_2177 .cse2)) (<= .cse0 c_ULTIMATE.start_main_p2) (<= (* 2 v_v_7536_2) 0) (or (= v_v_7533_2 (select |c_#memory_int| v_idx_2173)) (<= c_ULTIMATE.start_main_p1 v_idx_2173)))))) (forall ((v_idx_2186 Int) (v_idx_2185 Int) (v_idx_2184 Int) (v_idx_2183 Int) (v_idx_2182 Int) (v_idx_2181 Int) (v_idx_2180 Int)) (exists ((v_v_7539_2 Int) (v_v_7538_2 Int) (v_v_7533_2 Int) (v_v_7535_2 Int) (v_v_7534_2 Int) (v_v_7537_2 Int) (v_v_7536_2 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse4 (+ c_ULTIMATE.start_main_p3 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_7538_2)) (or (<= .cse3 v_idx_2183) (< v_idx_2183 c_ULTIMATE.start_main_p2) (= v_v_7536_2 (select |c_#memory_int| v_idx_2183))) (or (<= c_ULTIMATE.start_main_p1 v_idx_2180) (= v_v_7533_2 (select |c_#memory_int| v_idx_2180))) (<= 0 (* 2 v_v_7534_2)) (or (= v_v_7539_2 (select |c_#memory_int| v_idx_2186)) (< v_idx_2186 .cse4)) (<= v_v_7536_2 v_v_7538_2) (or (<= .cse5 v_idx_2181) (< v_idx_2181 c_ULTIMATE.start_main_p1) (= v_v_7534_2 (select |c_#memory_int| v_idx_2181))) (<= 0 (+ v_v_7538_2 v_v_7534_2)) (<= .cse3 c_ULTIMATE.start_main_p3) (<= v_v_7536_2 v_v_7534_2) (or (<= c_ULTIMATE.start_main_p2 v_idx_2182) (= v_v_7535_2 (select |c_#memory_int| v_idx_2182)) (< v_idx_2182 .cse5)) (or (<= c_ULTIMATE.start_main_p3 v_idx_2184) (= v_v_7537_2 (select |c_#memory_int| v_idx_2184)) (< v_idx_2184 .cse3)) (<= .cse5 c_ULTIMATE.start_main_p2) (<= (* 2 v_v_7536_2) 0) (or (<= .cse4 v_idx_2185) (< v_idx_2185 c_ULTIMATE.start_main_p3) (= v_v_7538_2 (select |c_#memory_int| v_idx_2185))))))) (forall ((v_idx_2169 Int) (v_idx_2168 Int) (v_idx_2167 Int) (v_idx_2166 Int) (v_idx_2172 Int) (v_idx_2171 Int) (v_idx_2170 Int)) (exists ((v_v_7539_2 Int) (v_v_7538_2 Int) (v_v_7533_2 Int) (v_v_7535_2 Int) (v_v_7534_2 Int) (v_v_7537_2 Int) (v_v_7536_2 Int)) (let ((.cse7 (+ c_ULTIMATE.start_main_p2 1)) (.cse8 (+ c_ULTIMATE.start_main_p3 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (<= 0 (* 2 v_v_7538_2)) (or (<= c_ULTIMATE.start_main_p1 v_idx_2166) (= v_v_7533_2 (select |c_#memory_int| v_idx_2166))) (<= 0 (* 2 v_v_7534_2)) (<= v_v_7536_2 v_v_7538_2) (or (< v_idx_2168 .cse6) (= (select |c_#memory_int| v_idx_2168) v_v_7535_2) (<= c_ULTIMATE.start_main_p2 v_idx_2168)) (<= 0 (+ v_v_7538_2 v_v_7534_2)) (<= .cse7 c_ULTIMATE.start_main_p3) (or (= v_v_7536_2 (select |c_#memory_int| v_idx_2169)) (<= .cse7 v_idx_2169) (< v_idx_2169 c_ULTIMATE.start_main_p2)) (or (<= .cse8 v_idx_2171) (< v_idx_2171 c_ULTIMATE.start_main_p3) (= v_v_7538_2 (select |c_#memory_int| v_idx_2171))) (<= v_v_7536_2 v_v_7534_2) (or (= v_v_7534_2 (select |c_#memory_int| v_idx_2167)) (<= .cse6 v_idx_2167) (< v_idx_2167 c_ULTIMATE.start_main_p1)) (or (= v_v_7537_2 (select |c_#memory_int| v_idx_2170)) (<= c_ULTIMATE.start_main_p3 v_idx_2170) (< v_idx_2170 .cse7)) (or (< v_idx_2172 .cse8) (= v_v_7539_2 (select |c_#memory_int| v_idx_2172))) (<= .cse6 c_ULTIMATE.start_main_p2) (<= (* 2 v_v_7536_2) 0))))) (forall ((v_idx_2189 Int) (v_idx_2188 Int) (v_idx_2187 Int) (v_idx_2193 Int) (v_idx_2192 Int) (v_idx_2191 Int) (v_idx_2190 Int)) (exists ((v_v_7539_2 Int) (v_v_7538_2 Int) (v_b_551_5 Int) (v_b_550_5 Int) (v_v_7533_2 Int) (v_v_7535_2 Int) (v_v_7534_2 Int) (v_v_7537_2 Int) (v_v_7536_2 Int)) (let ((.cse9 (+ v_b_550_5 1)) (.cse10 (+ c_ULTIMATE.start_main_p2 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_551_5 .cse9) (<= 0 (* 2 v_v_7538_2)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_550_5) (<= .cse10 v_b_550_5) (or (= v_v_7533_2 (select |c_#memory_int| v_idx_2187)) (<= c_ULTIMATE.start_main_p1 v_idx_2187)) (<= 0 (* 2 v_v_7534_2)) (<= v_v_7536_2 v_v_7538_2) (or (<= .cse10 v_idx_2190) (= v_v_7536_2 (select |c_#memory_int| v_idx_2190)) (< v_idx_2190 c_ULTIMATE.start_main_p2)) (<= .cse9 v_b_551_5) (or (<= .cse11 v_idx_2188) (= v_v_7534_2 (select |c_#memory_int| v_idx_2188)) (< v_idx_2188 c_ULTIMATE.start_main_p1)) (or (= v_v_7539_2 (select |c_#memory_int| v_idx_2193)) (< v_idx_2193 v_b_551_5)) (<= 0 (+ v_v_7538_2 v_v_7534_2)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_551_5) (or (< v_idx_2189 .cse11) (= v_v_7535_2 (select |c_#memory_int| v_idx_2189)) (<= c_ULTIMATE.start_main_p2 v_idx_2189)) (or (= v_v_7538_2 (select |c_#memory_int| v_idx_2192)) (< v_idx_2192 v_b_550_5) (<= v_b_551_5 v_idx_2192)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_551_5) (<= v_v_7536_2 v_v_7534_2) (or (= v_v_7537_2 (select |c_#memory_int| v_idx_2191)) (< v_idx_2191 .cse10) (<= v_b_550_5 v_idx_2191)) (<= .cse11 c_ULTIMATE.start_main_p2) (<= (* 2 v_v_7536_2) 0))))) (forall ((v_idx_2200 Int) (v_idx_2199 Int) (v_idx_2198 Int) (v_idx_2197 Int) (v_idx_2196 Int) (v_idx_2195 Int) (v_idx_2194 Int)) (exists ((v_v_7539_2 Int) (v_v_7538_2 Int) (v_b_551_5 Int) (v_b_550_5 Int) (v_v_8361_1 Int) (v_b_598_5 Int) (v_v_7533_2 Int) (v_b_547_5 Int) (v_v_7535_2 Int) (v_v_7537_2 Int) (v_v_7536_2 Int)) (let ((.cse14 (+ v_b_598_5 1)) (.cse13 (+ c_ULTIMATE.start_main_p2 1)) (.cse12 (+ v_b_550_5 1))) (and (<= (+ v_b_598_5 3) v_b_551_5) (<= v_b_551_5 .cse12) (<= .cse13 v_b_550_5) (<= .cse14 v_b_547_5) (<= .cse14 c_ULTIMATE.start_main_p2) (or (<= v_b_547_5 v_idx_2195) (= v_v_8361_1 (select |c_#memory_int| v_idx_2195)) (< v_idx_2195 v_b_598_5)) (<= v_b_547_5 .cse14) (<= v_v_7536_2 v_v_7538_2) (or (= v_v_7537_2 (select |c_#memory_int| v_idx_2198)) (< v_idx_2198 .cse13) (<= v_b_550_5 v_idx_2198)) (or (<= v_b_551_5 v_idx_2199) (= v_v_7538_2 (select |c_#memory_int| v_idx_2199)) (< v_idx_2199 v_b_550_5)) (or (< v_idx_2196 v_b_547_5) (<= c_ULTIMATE.start_main_p2 v_idx_2196) (= v_v_7535_2 (select |c_#memory_int| v_idx_2196))) (<= (+ v_b_547_5 1) v_b_550_5) (<= 0 (+ v_v_7538_2 v_v_8361_1)) (<= (* 2 v_v_7536_2) 0) (or (= v_v_7536_2 (select |c_#memory_int| v_idx_2197)) (< v_idx_2197 c_ULTIMATE.start_main_p2) (<= .cse13 v_idx_2197)) (<= 0 (* 2 v_v_7538_2)) (<= v_v_7536_2 v_v_8361_1) (<= (+ v_b_547_5 2) v_b_551_5) (<= .cse12 v_b_551_5) (<= (+ v_b_598_5 2) v_b_550_5) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_551_5) (<= v_b_547_5 c_ULTIMATE.start_main_p2) (or (<= v_b_598_5 v_idx_2194) (= v_v_7533_2 (select |c_#memory_int| v_idx_2194))) (or (< v_idx_2200 v_b_551_5) (= v_v_7539_2 (select |c_#memory_int| v_idx_2200))) (<= 0 (* 2 v_v_8361_1))))))) is different from false [2019-01-11 11:54:41,678 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_2189 Int) (v_idx_2188 Int) (v_idx_2187 Int) (v_idx_2193 Int) (v_idx_2192 Int) (v_idx_2191 Int) (v_idx_2190 Int)) (exists ((v_v_7539_2 Int) (v_v_7538_2 Int) (v_b_551_5 Int) (v_b_550_5 Int) (v_v_7533_2 Int) (v_v_7535_2 Int) (v_v_7534_2 Int) (v_v_7537_2 Int) (v_v_7536_2 Int)) (let ((.cse0 (+ v_b_550_5 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_551_5 .cse0) (<= 0 (* 2 v_v_7538_2)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_550_5) (<= .cse1 v_b_550_5) (or (= v_v_7533_2 (select |c_#memory_int| v_idx_2187)) (<= c_ULTIMATE.start_main_p1 v_idx_2187)) (<= 0 (* 2 v_v_7534_2)) (<= v_v_7536_2 v_v_7538_2) (or (<= .cse1 v_idx_2190) (= v_v_7536_2 (select |c_#memory_int| v_idx_2190)) (< v_idx_2190 c_ULTIMATE.start_main_p2)) (<= .cse0 v_b_551_5) (or (<= .cse2 v_idx_2188) (= v_v_7534_2 (select |c_#memory_int| v_idx_2188)) (< v_idx_2188 c_ULTIMATE.start_main_p1)) (or (= v_v_7539_2 (select |c_#memory_int| v_idx_2193)) (< v_idx_2193 v_b_551_5)) (<= 0 (+ v_v_7538_2 v_v_7534_2)) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_551_5) (or (< v_idx_2189 .cse2) (= v_v_7535_2 (select |c_#memory_int| v_idx_2189)) (<= c_ULTIMATE.start_main_p2 v_idx_2189)) (or (= v_v_7538_2 (select |c_#memory_int| v_idx_2192)) (< v_idx_2192 v_b_550_5) (<= v_b_551_5 v_idx_2192)) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_551_5) (<= v_v_7536_2 v_v_7534_2) (or (= v_v_7537_2 (select |c_#memory_int| v_idx_2191)) (< v_idx_2191 .cse1) (<= v_b_550_5 v_idx_2191)) (<= .cse2 c_ULTIMATE.start_main_p2) (<= (* 2 v_v_7536_2) 0))))) (forall ((v_idx_2200 Int) (v_idx_2199 Int) (v_idx_2198 Int) (v_idx_2197 Int) (v_idx_2196 Int) (v_idx_2195 Int) (v_idx_2194 Int)) (exists ((v_v_7539_2 Int) (v_v_7538_2 Int) (v_b_551_5 Int) (v_b_550_5 Int) (v_v_8361_1 Int) (v_b_598_5 Int) (v_v_7533_2 Int) (v_b_547_5 Int) (v_v_7535_2 Int) (v_v_7537_2 Int) (v_v_7536_2 Int)) (let ((.cse5 (+ v_b_598_5 1)) (.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse3 (+ v_b_550_5 1))) (and (<= (+ v_b_598_5 3) v_b_551_5) (<= v_b_551_5 .cse3) (<= .cse4 v_b_550_5) (<= .cse5 v_b_547_5) (<= .cse5 c_ULTIMATE.start_main_p2) (or (<= v_b_547_5 v_idx_2195) (= v_v_8361_1 (select |c_#memory_int| v_idx_2195)) (< v_idx_2195 v_b_598_5)) (<= v_b_547_5 .cse5) (<= v_v_7536_2 v_v_7538_2) (or (= v_v_7537_2 (select |c_#memory_int| v_idx_2198)) (< v_idx_2198 .cse4) (<= v_b_550_5 v_idx_2198)) (or (<= v_b_551_5 v_idx_2199) (= v_v_7538_2 (select |c_#memory_int| v_idx_2199)) (< v_idx_2199 v_b_550_5)) (or (< v_idx_2196 v_b_547_5) (<= c_ULTIMATE.start_main_p2 v_idx_2196) (= v_v_7535_2 (select |c_#memory_int| v_idx_2196))) (<= (+ v_b_547_5 1) v_b_550_5) (<= 0 (+ v_v_7538_2 v_v_8361_1)) (<= (* 2 v_v_7536_2) 0) (or (= v_v_7536_2 (select |c_#memory_int| v_idx_2197)) (< v_idx_2197 c_ULTIMATE.start_main_p2) (<= .cse4 v_idx_2197)) (<= 0 (* 2 v_v_7538_2)) (<= v_v_7536_2 v_v_8361_1) (<= (+ v_b_547_5 2) v_b_551_5) (<= .cse3 v_b_551_5) (<= (+ v_b_598_5 2) v_b_550_5) (<= (+ c_ULTIMATE.start_main_p2 2) v_b_551_5) (<= v_b_547_5 c_ULTIMATE.start_main_p2) (or (<= v_b_598_5 v_idx_2194) (= v_v_7533_2 (select |c_#memory_int| v_idx_2194))) (or (< v_idx_2200 v_b_551_5) (= v_v_7539_2 (select |c_#memory_int| v_idx_2200))) (<= 0 (* 2 v_v_8361_1))))))) is different from false [2019-01-11 11:54:51,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:54:51,667 INFO L93 Difference]: Finished difference Result 42 states and 130 transitions. [2019-01-11 11:54:51,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-01-11 11:54:51,667 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 6 [2019-01-11 11:54:51,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:54:51,667 INFO L225 Difference]: With dead ends: 42 [2019-01-11 11:54:51,667 INFO L226 Difference]: Without dead ends: 41 [2019-01-11 11:54:51,668 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 7 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 17.0s TimeCoverageRelationStatistics Valid=15, Invalid=8, Unknown=7, NotChecked=42, Total=72 [2019-01-11 11:54:51,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2019-01-11 11:54:51,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 39. [2019-01-11 11:54:51,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2019-01-11 11:54:51,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 127 transitions. [2019-01-11 11:54:51,716 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 127 transitions. Word has length 6 [2019-01-11 11:54:51,716 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:54:51,716 INFO L480 AbstractCegarLoop]: Abstraction has 39 states and 127 transitions. [2019-01-11 11:54:51,716 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-01-11 11:54:51,716 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 127 transitions. [2019-01-11 11:54:51,716 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-11 11:54:51,716 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:54:51,717 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2019-01-11 11:54:51,717 INFO L423 AbstractCegarLoop]: === Iteration 30 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:54:51,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:54:51,717 INFO L82 PathProgramCache]: Analyzing trace with hash 893412422, now seen corresponding path program 2 times [2019-01-11 11:54:51,717 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:54:51,718 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:54:51,718 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:54:51,718 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:54:51,718 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:54:51,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:54:51,829 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-11 11:54:51,830 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:54:51,830 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:54:51,830 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:54:51,830 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:54:51,830 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:54:51,830 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:54:51,839 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-11 11:54:51,839 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-11 11:54:51,844 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-01-11 11:54:51,845 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:54:51,846 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:54:51,848 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-11 11:54:51,855 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,856 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-11 11:54:51,862 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,863 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,863 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-11 11:54:51,864 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:51,875 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:54:51,882 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:54:51,894 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:54:51,894 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:19, output treesize:22 [2019-01-11 11:54:51,911 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,912 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,913 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,914 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,915 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 28 [2019-01-11 11:54:51,916 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:51,933 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:54:51,933 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-11 11:54:51,955 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,956 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,956 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,957 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,958 INFO L683 Elim1Store]: detected equality via solver [2019-01-11 11:54:51,958 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 36 [2019-01-11 11:54:51,959 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:51,975 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:54:51,975 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-11 11:54:51,995 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,996 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,997 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,997 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,998 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:51,999 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:52,000 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 40 [2019-01-11 11:54:52,001 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:52,021 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:54:52,021 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:32, output treesize:22 [2019-01-11 11:54:52,040 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:54:52,041 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:54:52,072 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:54:52,090 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-11 11:54:52,091 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 11 [2019-01-11 11:54:52,091 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-11 11:54:52,091 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-01-11 11:54:52,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-01-11 11:54:52,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=95, Unknown=0, NotChecked=0, Total=156 [2019-01-11 11:54:52,092 INFO L87 Difference]: Start difference. First operand 39 states and 127 transitions. Second operand 10 states. [2019-01-11 11:54:52,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:54:52,404 INFO L93 Difference]: Finished difference Result 58 states and 176 transitions. [2019-01-11 11:54:52,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-01-11 11:54:52,405 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 6 [2019-01-11 11:54:52,405 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:54:52,406 INFO L225 Difference]: With dead ends: 58 [2019-01-11 11:54:52,406 INFO L226 Difference]: Without dead ends: 57 [2019-01-11 11:54:52,407 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=89, Invalid=151, Unknown=0, NotChecked=0, Total=240 [2019-01-11 11:54:52,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2019-01-11 11:54:52,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 43. [2019-01-11 11:54:52,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2019-01-11 11:54:52,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 143 transitions. [2019-01-11 11:54:52,457 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 143 transitions. Word has length 6 [2019-01-11 11:54:52,458 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:54:52,458 INFO L480 AbstractCegarLoop]: Abstraction has 43 states and 143 transitions. [2019-01-11 11:54:52,458 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-01-11 11:54:52,458 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 143 transitions. [2019-01-11 11:54:52,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-11 11:54:52,458 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:54:52,458 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2019-01-11 11:54:52,459 INFO L423 AbstractCegarLoop]: === Iteration 31 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:54:52,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:54:52,459 INFO L82 PathProgramCache]: Analyzing trace with hash 896933590, now seen corresponding path program 2 times [2019-01-11 11:54:52,459 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:54:52,460 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:54:52,460 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:54:52,460 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:54:52,460 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:54:52,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:54:52,599 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-11 11:54:52,600 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:54:52,600 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:54:52,600 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:54:52,600 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:54:52,600 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:54:52,601 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:54:52,609 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-11 11:54:52,610 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-11 11:54:52,614 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-11 11:54:52,614 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:54:52,615 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:54:52,617 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-11 11:54:52,619 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:52,620 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-11 11:54:52,622 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:52,623 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:52,623 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-11 11:54:52,624 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:52,635 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:54:52,642 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:54:52,652 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:54:52,653 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:19, output treesize:22 [2019-01-11 11:54:52,671 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:52,672 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:52,673 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:52,674 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:52,675 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-11 11:54:52,675 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:52,691 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:54:52,691 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:32, output treesize:22 [2019-01-11 11:54:52,709 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:52,710 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:52,712 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:52,712 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:52,713 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:52,714 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:52,715 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 42 [2019-01-11 11:54:52,715 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:52,735 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:54:52,735 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:24 [2019-01-11 11:54:52,753 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:54:52,753 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:54:52,815 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:54:52,834 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-11 11:54:52,834 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 9 [2019-01-11 11:54:52,834 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-11 11:54:52,834 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-01-11 11:54:52,835 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-01-11 11:54:52,835 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=66, Unknown=0, NotChecked=0, Total=110 [2019-01-11 11:54:52,835 INFO L87 Difference]: Start difference. First operand 43 states and 143 transitions. Second operand 8 states. [2019-01-11 11:54:53,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:54:53,046 INFO L93 Difference]: Finished difference Result 51 states and 158 transitions. [2019-01-11 11:54:53,046 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-11 11:54:53,047 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 6 [2019-01-11 11:54:53,047 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:54:53,047 INFO L225 Difference]: With dead ends: 51 [2019-01-11 11:54:53,048 INFO L226 Difference]: Without dead ends: 46 [2019-01-11 11:54:53,048 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=62, Invalid=94, Unknown=0, NotChecked=0, Total=156 [2019-01-11 11:54:53,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2019-01-11 11:54:53,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 45. [2019-01-11 11:54:53,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2019-01-11 11:54:53,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 149 transitions. [2019-01-11 11:54:53,103 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 149 transitions. Word has length 6 [2019-01-11 11:54:53,104 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:54:53,104 INFO L480 AbstractCegarLoop]: Abstraction has 45 states and 149 transitions. [2019-01-11 11:54:53,104 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-01-11 11:54:53,104 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 149 transitions. [2019-01-11 11:54:53,104 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-11 11:54:53,104 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:54:53,104 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2019-01-11 11:54:53,104 INFO L423 AbstractCegarLoop]: === Iteration 32 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:54:53,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:54:53,105 INFO L82 PathProgramCache]: Analyzing trace with hash 896929682, now seen corresponding path program 3 times [2019-01-11 11:54:53,105 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:54:53,105 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:54:53,106 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:54:53,106 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:54:53,106 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:54:53,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:54:53,308 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-11 11:54:53,309 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:54:53,309 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:54:53,309 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:54:53,309 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:54:53,309 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:54:53,309 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:54:53,318 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2019-01-11 11:54:53,318 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2019-01-11 11:54:53,323 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-01-11 11:54:53,323 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:54:53,324 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:54:53,329 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-11 11:54:53,331 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,332 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-11 11:54:53,334 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,335 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,335 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-11 11:54:53,335 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:53,349 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:54:53,357 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:54:53,368 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:54:53,368 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:19, output treesize:22 [2019-01-11 11:54:53,388 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,389 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,389 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,390 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,391 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-11 11:54:53,392 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:53,413 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:54:53,414 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:32, output treesize:22 [2019-01-11 11:54:53,435 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,436 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,438 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,439 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,440 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,441 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,442 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 42 [2019-01-11 11:54:53,443 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:53,460 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:54:53,460 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:34, output treesize:24 [2019-01-11 11:54:53,482 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,483 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,484 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,485 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,486 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,486 INFO L683 Elim1Store]: detected equality via solver [2019-01-11 11:54:53,487 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:53,488 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 50 [2019-01-11 11:54:53,489 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:53,509 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:54:53,509 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:24 [2019-01-11 11:54:53,531 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:54:53,532 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:54:53,591 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:54:53,610 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-11 11:54:53,610 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 11 [2019-01-11 11:54:53,610 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-11 11:54:53,611 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2019-01-11 11:54:53,611 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2019-01-11 11:54:53,611 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=97, Unknown=0, NotChecked=0, Total=156 [2019-01-11 11:54:53,611 INFO L87 Difference]: Start difference. First operand 45 states and 149 transitions. Second operand 10 states. [2019-01-11 11:54:53,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:54:53,976 INFO L93 Difference]: Finished difference Result 50 states and 159 transitions. [2019-01-11 11:54:53,976 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-01-11 11:54:53,976 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 6 [2019-01-11 11:54:53,976 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:54:53,977 INFO L225 Difference]: With dead ends: 50 [2019-01-11 11:54:53,977 INFO L226 Difference]: Without dead ends: 49 [2019-01-11 11:54:53,978 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=77, Invalid=133, Unknown=0, NotChecked=0, Total=210 [2019-01-11 11:54:53,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2019-01-11 11:54:54,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 25. [2019-01-11 11:54:54,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2019-01-11 11:54:54,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 75 transitions. [2019-01-11 11:54:54,016 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 75 transitions. Word has length 6 [2019-01-11 11:54:54,016 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:54:54,017 INFO L480 AbstractCegarLoop]: Abstraction has 25 states and 75 transitions. [2019-01-11 11:54:54,017 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2019-01-11 11:54:54,017 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 75 transitions. [2019-01-11 11:54:54,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-11 11:54:54,017 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:54:54,017 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1] [2019-01-11 11:54:54,017 INFO L423 AbstractCegarLoop]: === Iteration 33 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:54:54,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:54:54,018 INFO L82 PathProgramCache]: Analyzing trace with hash 897048534, now seen corresponding path program 2 times [2019-01-11 11:54:54,018 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:54:54,018 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:54:54,018 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:54:54,018 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:54:54,018 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:54:54,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:54:54,157 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-11 11:54:54,157 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:54:54,157 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:54:54,157 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:54:54,157 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:54:54,157 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:54:54,157 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:54:54,170 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-11 11:54:54,170 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-11 11:54:54,174 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2019-01-11 11:54:54,175 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:54:54,175 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:54:54,177 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-11 11:54:54,179 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,180 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-11 11:54:54,183 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,184 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,185 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-11 11:54:54,185 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:54,197 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:54:54,204 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:54:54,215 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:54:54,216 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:19, output treesize:22 [2019-01-11 11:54:54,232 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,233 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,234 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,236 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,237 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-11 11:54:54,237 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:54,275 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:54:54,276 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:32, output treesize:22 [2019-01-11 11:54:54,294 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,295 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,296 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,297 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,298 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,299 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,300 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 40 [2019-01-11 11:54:54,301 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:54,320 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:54:54,320 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:34, output treesize:22 [2019-01-11 11:54:54,343 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,344 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,346 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,347 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,348 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,349 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,350 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 50 [2019-01-11 11:54:54,351 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:54,373 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:54:54,373 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:24 [2019-01-11 11:54:54,392 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,393 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,394 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,396 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,397 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,398 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,399 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,400 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:54:54,401 INFO L683 Elim1Store]: detected equality via solver [2019-01-11 11:54:54,401 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 56 [2019-01-11 11:54:54,402 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:54:54,426 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:54:54,427 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:24 [2019-01-11 11:54:54,441 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:54:54,441 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:54:54,490 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:54:54,509 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-11 11:54:54,509 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5, 5] total 13 [2019-01-11 11:54:54,510 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-11 11:54:54,510 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-01-11 11:54:54,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-01-11 11:54:54,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=128, Unknown=0, NotChecked=0, Total=210 [2019-01-11 11:54:54,511 INFO L87 Difference]: Start difference. First operand 25 states and 75 transitions. Second operand 11 states. [2019-01-11 11:54:54,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:54:54,951 INFO L93 Difference]: Finished difference Result 43 states and 116 transitions. [2019-01-11 11:54:54,951 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-01-11 11:54:54,951 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 6 [2019-01-11 11:54:54,951 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:54:54,952 INFO L225 Difference]: With dead ends: 43 [2019-01-11 11:54:54,952 INFO L226 Difference]: Without dead ends: 42 [2019-01-11 11:54:54,953 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 77 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=104, Invalid=168, Unknown=0, NotChecked=0, Total=272 [2019-01-11 11:54:54,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2019-01-11 11:54:54,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 30. [2019-01-11 11:54:54,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2019-01-11 11:54:54,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 95 transitions. [2019-01-11 11:54:54,992 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 95 transitions. Word has length 6 [2019-01-11 11:54:54,992 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:54:54,992 INFO L480 AbstractCegarLoop]: Abstraction has 30 states and 95 transitions. [2019-01-11 11:54:54,992 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-01-11 11:54:54,992 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 95 transitions. [2019-01-11 11:54:54,992 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-11 11:54:54,992 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:54:54,992 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2019-01-11 11:54:54,992 INFO L423 AbstractCegarLoop]: === Iteration 34 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:54:54,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:54:54,993 INFO L82 PathProgramCache]: Analyzing trace with hash 897112336, now seen corresponding path program 1 times [2019-01-11 11:54:54,993 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:54:54,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:54:54,993 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:54:54,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:54:54,994 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:54:54,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:54:55,330 WARN L181 SmtUtils]: Spent 302.00 ms on a formula simplification. DAG size of input: 21 DAG size of output: 13 [2019-01-11 11:54:55,560 WARN L181 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 17 DAG size of output: 9 [2019-01-11 11:54:55,566 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-11 11:54:55,566 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:54:55,567 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:54:55,567 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 7 with the following transitions: [2019-01-11 11:54:55,567 INFO L207 CegarAbsIntRunner]: [0], [10], [12], [16], [18], [19] [2019-01-11 11:54:55,569 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:54:55,569 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:55:13,749 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:55:13,750 INFO L272 AbstractInterpreter]: Visited 6 different actions 46 times. Merged at 4 different actions 24 times. Widened at 2 different actions 6 times. Found 10 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-11 11:55:13,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:55:13,750 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:55:14,344 INFO L227 lantSequenceWeakener]: Weakened 5 states. On average, predicates are now at 51.43% of their original sizes. [2019-01-11 11:55:14,344 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:55:16,760 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2369 Int) (v_idx_2368 Int) (v_idx_2367 Int) (v_idx_2366 Int) (v_idx_2372 Int) (v_idx_2371 Int) (v_idx_2370 Int)) (exists ((v_v_5150_7 Int) (v_v_5152_7 Int) (v_v_5153_7 Int) (v_v_5154_7 Int) (v_v_5155_7 Int) (v_v_5156_7 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_2368) v_v_5152_7) (< v_idx_2368 .cse0) (<= c_ULTIMATE.start_main_p2 v_idx_2368)) (or (= (select |c_#memory_int| v_idx_2369) v_v_5153_7) (< v_idx_2369 c_ULTIMATE.start_main_p2) (<= .cse1 v_idx_2369)) (<= v_v_5153_7 v_v_5155_7) (or (<= c_ULTIMATE.start_main_p1 v_idx_2366) (= (select |c_#memory_int| v_idx_2366) v_v_5150_7)) (or (< v_idx_2367 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_2367) 0) (<= .cse0 v_idx_2367)) (<= v_v_5153_7 0) (or (= (select |c_#memory_int| v_idx_2370) v_v_5154_7) (< v_idx_2370 .cse1) (<= c_ULTIMATE.start_main_p3 v_idx_2370)) (<= .cse1 c_ULTIMATE.start_main_p3) (<= 0 v_v_5155_7) (or (< v_idx_2372 .cse2) (= (select |c_#memory_int| v_idx_2372) v_v_5156_7)) (<= 0 (* 2 v_v_5155_7)) (or (= (select |c_#memory_int| v_idx_2371) v_v_5155_7) (<= .cse2 v_idx_2371) (< v_idx_2371 c_ULTIMATE.start_main_p3)) (<= .cse0 c_ULTIMATE.start_main_p2) (<= (* 2 v_v_5153_7) 0))))) is different from false [2019-01-11 11:55:19,411 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2379 Int) (v_idx_2378 Int) (v_idx_2377 Int) (v_idx_2376 Int) (v_idx_2375 Int) (v_idx_2374 Int) (v_idx_2373 Int)) (exists ((v_v_5150_7 Int) (v_v_5152_7 Int) (v_v_5153_7 Int) (v_v_5154_7 Int) (v_v_5155_7 Int) (v_v_5156_7 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1))) (and (or (= (select |c_#memory_int| v_idx_2379) v_v_5156_7) (< v_idx_2379 .cse0)) (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= .cse0 v_idx_2378) (< v_idx_2378 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_2378) v_v_5155_7)) (or (= (select |c_#memory_int| v_idx_2375) v_v_5152_7) (< v_idx_2375 .cse1) (<= c_ULTIMATE.start_main_p2 v_idx_2375)) (or (= (select |c_#memory_int| v_idx_2373) v_v_5150_7) (<= c_ULTIMATE.start_main_p1 v_idx_2373)) (<= v_v_5153_7 v_v_5155_7) (<= v_v_5153_7 0) (<= .cse2 c_ULTIMATE.start_main_p3) (<= 0 v_v_5155_7) (or (< v_idx_2376 c_ULTIMATE.start_main_p2) (<= .cse2 v_idx_2376) (= (select |c_#memory_int| v_idx_2376) v_v_5153_7)) (<= 0 (* 2 v_v_5155_7)) (<= .cse1 c_ULTIMATE.start_main_p2) (or (< v_idx_2374 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_2374) 0) (<= .cse1 v_idx_2374)) (or (= (select |c_#memory_int| v_idx_2377) v_v_5154_7) (<= c_ULTIMATE.start_main_p3 v_idx_2377) (< v_idx_2377 .cse2)) (<= (* 2 v_v_5153_7) 0))))) is different from false [2019-01-11 11:55:22,033 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2386 Int) (v_idx_2385 Int) (v_idx_2384 Int) (v_idx_2383 Int) (v_idx_2382 Int) (v_idx_2381 Int) (v_idx_2380 Int)) (exists ((v_v_5150_7 Int) (v_v_5152_7 Int) (v_v_5153_7 Int) (v_v_5154_7 Int) (v_v_5155_7 Int) (v_v_5156_7 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_2386 .cse0) (= (select |c_#memory_int| v_idx_2386) v_v_5156_7)) (or (<= .cse1 v_idx_2381) (< v_idx_2381 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_2381) 0)) (<= v_v_5153_7 v_v_5155_7) (or (<= .cse2 v_idx_2383) (< v_idx_2383 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_2383) v_v_5153_7)) (or (< v_idx_2384 .cse2) (= (select |c_#memory_int| v_idx_2384) v_v_5154_7) (<= c_ULTIMATE.start_main_p3 v_idx_2384)) (<= v_v_5153_7 0) (<= .cse2 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_2380) v_v_5150_7) (<= c_ULTIMATE.start_main_p1 v_idx_2380)) (<= 0 v_v_5155_7) (or (< v_idx_2385 c_ULTIMATE.start_main_p3) (<= .cse0 v_idx_2385) (= (select |c_#memory_int| v_idx_2385) v_v_5155_7)) (or (< v_idx_2382 .cse1) (= (select |c_#memory_int| v_idx_2382) v_v_5152_7) (<= c_ULTIMATE.start_main_p2 v_idx_2382)) (<= 0 (* 2 v_v_5155_7)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= (* 2 v_v_5153_7) 0))))) is different from false [2019-01-11 11:55:24,456 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2389 Int) (v_idx_2388 Int) (v_idx_2387 Int) (v_idx_2393 Int) (v_idx_2392 Int) (v_idx_2391 Int) (v_idx_2390 Int)) (exists ((v_b_390_9 Int) (v_b_355_9 Int) (v_v_5150_7 Int) (v_v_5152_7 Int) (v_v_5153_7 Int) (v_v_5154_7 Int) (v_v_5155_7 Int) (v_v_5156_7 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ v_b_390_9 1))) (and (or (< v_idx_2393 .cse0) (= (select |c_#memory_int| v_idx_2393) v_v_5156_7)) (<= v_b_355_9 .cse1) (<= .cse1 v_b_355_9) (or (<= c_ULTIMATE.start_main_p2 v_idx_2389) (= (select |c_#memory_int| v_idx_2389) v_v_5152_7) (< v_idx_2389 v_b_355_9)) (or (<= v_b_355_9 v_idx_2388) (= (select |c_#memory_int| v_idx_2388) 0) (< v_idx_2388 v_b_390_9)) (<= (+ v_b_390_9 2) c_ULTIMATE.start_main_p3) (or (<= .cse2 v_idx_2390) (= (select |c_#memory_int| v_idx_2390) v_v_5153_7) (< v_idx_2390 c_ULTIMATE.start_main_p2)) (<= v_v_5153_7 v_v_5155_7) (<= (+ v_b_355_9 1) c_ULTIMATE.start_main_p3) (<= v_v_5153_7 0) (or (<= .cse0 v_idx_2392) (= (select |c_#memory_int| v_idx_2392) v_v_5155_7) (< v_idx_2392 c_ULTIMATE.start_main_p3)) (<= .cse2 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_2387) v_v_5150_7) (<= v_b_390_9 v_idx_2387)) (<= v_b_355_9 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_2391) v_v_5154_7) (<= c_ULTIMATE.start_main_p3 v_idx_2391) (< v_idx_2391 .cse2)) (<= 0 v_v_5155_7) (<= .cse1 c_ULTIMATE.start_main_p2) (<= 0 (* 2 v_v_5155_7)) (<= (* 2 v_v_5153_7) 0))))) is different from false [2019-01-11 11:55:26,715 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_2400 Int) (v_idx_2399 Int) (v_idx_2398 Int) (v_idx_2397 Int) (v_idx_2396 Int) (v_idx_2395 Int) (v_idx_2394 Int)) (exists ((v_b_390_9 Int) (v_b_357_9 Int) (v_b_414_9 Int) (v_b_355_9 Int) (v_v_5150_7 Int) (v_v_6420_5 Int) (v_v_5152_7 Int) (v_v_5154_7 Int) (v_v_5155_7 Int) (v_v_5156_7 Int)) (let ((.cse0 (+ v_b_390_9 1)) (.cse1 (+ v_b_414_9 1)) (.cse2 (+ v_b_390_9 2)) (.cse4 (+ v_b_355_9 1)) (.cse3 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse0 v_b_414_9) (<= v_b_355_9 .cse0) (<= v_b_357_9 .cse1) (<= .cse1 c_ULTIMATE.start_main_p3) (<= .cse0 v_b_355_9) (or (= (select |c_#memory_int| v_idx_2394) v_v_5150_7) (<= v_b_390_9 v_idx_2394)) (<= .cse2 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_2400) v_v_5156_7) (< v_idx_2400 .cse3)) (<= v_b_355_9 v_b_414_9) (<= .cse4 c_ULTIMATE.start_main_p3) (<= .cse1 v_b_357_9) (<= v_v_6420_5 0) (<= v_b_357_9 c_ULTIMATE.start_main_p3) (<= .cse2 v_b_357_9) (or (= (select |c_#memory_int| v_idx_2396) v_v_5152_7) (<= v_b_414_9 v_idx_2396) (< v_idx_2396 v_b_355_9)) (<= 0 v_v_5155_7) (<= (* 2 v_v_6420_5) 0) (or (< v_idx_2397 v_b_414_9) (= v_v_6420_5 (select |c_#memory_int| v_idx_2397)) (<= v_b_357_9 v_idx_2397)) (<= 0 (* 2 v_v_5155_7)) (<= .cse4 v_b_357_9) (or (<= c_ULTIMATE.start_main_p3 v_idx_2398) (< v_idx_2398 v_b_357_9) (= (select |c_#memory_int| v_idx_2398) v_v_5154_7)) (or (<= .cse3 v_idx_2399) (< v_idx_2399 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_2399) v_v_5155_7)) (<= v_v_6420_5 v_v_5155_7) (or (= 0 (select |c_#memory_int| v_idx_2395)) (<= v_b_355_9 v_idx_2395) (< v_idx_2395 v_b_390_9)))))) is different from false [2019-01-11 11:55:26,825 INFO L420 sIntCurrentIteration]: We unified 5 AI predicates to 5 [2019-01-11 11:55:26,825 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:55:26,826 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:55:26,826 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [3] total 8 [2019-01-11 11:55:26,826 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:55:26,826 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-01-11 11:55:26,826 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-01-11 11:55:26,826 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=6, Unknown=5, NotChecked=20, Total=42 [2019-01-11 11:55:26,826 INFO L87 Difference]: Start difference. First operand 30 states and 95 transitions. Second operand 7 states. [2019-01-11 11:55:29,721 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_2386 Int) (v_idx_2385 Int) (v_idx_2384 Int) (v_idx_2383 Int) (v_idx_2382 Int) (v_idx_2381 Int) (v_idx_2380 Int)) (exists ((v_v_5150_7 Int) (v_v_5152_7 Int) (v_v_5153_7 Int) (v_v_5154_7 Int) (v_v_5155_7 Int) (v_v_5156_7 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (< v_idx_2386 .cse0) (= (select |c_#memory_int| v_idx_2386) v_v_5156_7)) (or (<= .cse1 v_idx_2381) (< v_idx_2381 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_2381) 0)) (<= v_v_5153_7 v_v_5155_7) (or (<= .cse2 v_idx_2383) (< v_idx_2383 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_2383) v_v_5153_7)) (or (< v_idx_2384 .cse2) (= (select |c_#memory_int| v_idx_2384) v_v_5154_7) (<= c_ULTIMATE.start_main_p3 v_idx_2384)) (<= v_v_5153_7 0) (<= .cse2 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_2380) v_v_5150_7) (<= c_ULTIMATE.start_main_p1 v_idx_2380)) (<= 0 v_v_5155_7) (or (< v_idx_2385 c_ULTIMATE.start_main_p3) (<= .cse0 v_idx_2385) (= (select |c_#memory_int| v_idx_2385) v_v_5155_7)) (or (< v_idx_2382 .cse1) (= (select |c_#memory_int| v_idx_2382) v_v_5152_7) (<= c_ULTIMATE.start_main_p2 v_idx_2382)) (<= 0 (* 2 v_v_5155_7)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= (* 2 v_v_5153_7) 0))))) (forall ((v_idx_2400 Int) (v_idx_2399 Int) (v_idx_2398 Int) (v_idx_2397 Int) (v_idx_2396 Int) (v_idx_2395 Int) (v_idx_2394 Int)) (exists ((v_b_390_9 Int) (v_b_357_9 Int) (v_b_414_9 Int) (v_b_355_9 Int) (v_v_5150_7 Int) (v_v_6420_5 Int) (v_v_5152_7 Int) (v_v_5154_7 Int) (v_v_5155_7 Int) (v_v_5156_7 Int)) (let ((.cse3 (+ v_b_390_9 1)) (.cse4 (+ v_b_414_9 1)) (.cse5 (+ v_b_390_9 2)) (.cse7 (+ v_b_355_9 1)) (.cse6 (+ c_ULTIMATE.start_main_p3 1))) (and (<= .cse3 v_b_414_9) (<= v_b_355_9 .cse3) (<= v_b_357_9 .cse4) (<= .cse4 c_ULTIMATE.start_main_p3) (<= .cse3 v_b_355_9) (or (= (select |c_#memory_int| v_idx_2394) v_v_5150_7) (<= v_b_390_9 v_idx_2394)) (<= .cse5 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_2400) v_v_5156_7) (< v_idx_2400 .cse6)) (<= v_b_355_9 v_b_414_9) (<= .cse7 c_ULTIMATE.start_main_p3) (<= .cse4 v_b_357_9) (<= v_v_6420_5 0) (<= v_b_357_9 c_ULTIMATE.start_main_p3) (<= .cse5 v_b_357_9) (or (= (select |c_#memory_int| v_idx_2396) v_v_5152_7) (<= v_b_414_9 v_idx_2396) (< v_idx_2396 v_b_355_9)) (<= 0 v_v_5155_7) (<= (* 2 v_v_6420_5) 0) (or (< v_idx_2397 v_b_414_9) (= v_v_6420_5 (select |c_#memory_int| v_idx_2397)) (<= v_b_357_9 v_idx_2397)) (<= 0 (* 2 v_v_5155_7)) (<= .cse7 v_b_357_9) (or (<= c_ULTIMATE.start_main_p3 v_idx_2398) (< v_idx_2398 v_b_357_9) (= (select |c_#memory_int| v_idx_2398) v_v_5154_7)) (or (<= .cse6 v_idx_2399) (< v_idx_2399 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_2399) v_v_5155_7)) (<= v_v_6420_5 v_v_5155_7) (or (= 0 (select |c_#memory_int| v_idx_2395)) (<= v_b_355_9 v_idx_2395) (< v_idx_2395 v_b_390_9)))))) (forall ((v_idx_2379 Int) (v_idx_2378 Int) (v_idx_2377 Int) (v_idx_2376 Int) (v_idx_2375 Int) (v_idx_2374 Int) (v_idx_2373 Int)) (exists ((v_v_5150_7 Int) (v_v_5152_7 Int) (v_v_5153_7 Int) (v_v_5154_7 Int) (v_v_5155_7 Int) (v_v_5156_7 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p3 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 1)) (.cse10 (+ c_ULTIMATE.start_main_p2 1))) (and (or (= (select |c_#memory_int| v_idx_2379) v_v_5156_7) (< v_idx_2379 .cse8)) (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (<= .cse8 v_idx_2378) (< v_idx_2378 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_2378) v_v_5155_7)) (or (= (select |c_#memory_int| v_idx_2375) v_v_5152_7) (< v_idx_2375 .cse9) (<= c_ULTIMATE.start_main_p2 v_idx_2375)) (or (= (select |c_#memory_int| v_idx_2373) v_v_5150_7) (<= c_ULTIMATE.start_main_p1 v_idx_2373)) (<= v_v_5153_7 v_v_5155_7) (<= v_v_5153_7 0) (<= .cse10 c_ULTIMATE.start_main_p3) (<= 0 v_v_5155_7) (or (< v_idx_2376 c_ULTIMATE.start_main_p2) (<= .cse10 v_idx_2376) (= (select |c_#memory_int| v_idx_2376) v_v_5153_7)) (<= 0 (* 2 v_v_5155_7)) (<= .cse9 c_ULTIMATE.start_main_p2) (or (< v_idx_2374 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_2374) 0) (<= .cse9 v_idx_2374)) (or (= (select |c_#memory_int| v_idx_2377) v_v_5154_7) (<= c_ULTIMATE.start_main_p3 v_idx_2377) (< v_idx_2377 .cse10)) (<= (* 2 v_v_5153_7) 0))))) (forall ((v_idx_2389 Int) (v_idx_2388 Int) (v_idx_2387 Int) (v_idx_2393 Int) (v_idx_2392 Int) (v_idx_2391 Int) (v_idx_2390 Int)) (exists ((v_b_390_9 Int) (v_b_355_9 Int) (v_v_5150_7 Int) (v_v_5152_7 Int) (v_v_5153_7 Int) (v_v_5154_7 Int) (v_v_5155_7 Int) (v_v_5156_7 Int)) (let ((.cse11 (+ c_ULTIMATE.start_main_p3 1)) (.cse13 (+ c_ULTIMATE.start_main_p2 1)) (.cse12 (+ v_b_390_9 1))) (and (or (< v_idx_2393 .cse11) (= (select |c_#memory_int| v_idx_2393) v_v_5156_7)) (<= v_b_355_9 .cse12) (<= .cse12 v_b_355_9) (or (<= c_ULTIMATE.start_main_p2 v_idx_2389) (= (select |c_#memory_int| v_idx_2389) v_v_5152_7) (< v_idx_2389 v_b_355_9)) (or (<= v_b_355_9 v_idx_2388) (= (select |c_#memory_int| v_idx_2388) 0) (< v_idx_2388 v_b_390_9)) (<= (+ v_b_390_9 2) c_ULTIMATE.start_main_p3) (or (<= .cse13 v_idx_2390) (= (select |c_#memory_int| v_idx_2390) v_v_5153_7) (< v_idx_2390 c_ULTIMATE.start_main_p2)) (<= v_v_5153_7 v_v_5155_7) (<= (+ v_b_355_9 1) c_ULTIMATE.start_main_p3) (<= v_v_5153_7 0) (or (<= .cse11 v_idx_2392) (= (select |c_#memory_int| v_idx_2392) v_v_5155_7) (< v_idx_2392 c_ULTIMATE.start_main_p3)) (<= .cse13 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_2387) v_v_5150_7) (<= v_b_390_9 v_idx_2387)) (<= v_b_355_9 c_ULTIMATE.start_main_p2) (or (= (select |c_#memory_int| v_idx_2391) v_v_5154_7) (<= c_ULTIMATE.start_main_p3 v_idx_2391) (< v_idx_2391 .cse13)) (<= 0 v_v_5155_7) (<= .cse12 c_ULTIMATE.start_main_p2) (<= 0 (* 2 v_v_5155_7)) (<= (* 2 v_v_5153_7) 0))))) (forall ((v_idx_2369 Int) (v_idx_2368 Int) (v_idx_2367 Int) (v_idx_2366 Int) (v_idx_2372 Int) (v_idx_2371 Int) (v_idx_2370 Int)) (exists ((v_v_5150_7 Int) (v_v_5152_7 Int) (v_v_5153_7 Int) (v_v_5154_7 Int) (v_v_5155_7 Int) (v_v_5156_7 Int)) (let ((.cse15 (+ c_ULTIMATE.start_main_p2 1)) (.cse16 (+ c_ULTIMATE.start_main_p3 1)) (.cse14 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 2) c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_2368) v_v_5152_7) (< v_idx_2368 .cse14) (<= c_ULTIMATE.start_main_p2 v_idx_2368)) (or (= (select |c_#memory_int| v_idx_2369) v_v_5153_7) (< v_idx_2369 c_ULTIMATE.start_main_p2) (<= .cse15 v_idx_2369)) (<= v_v_5153_7 v_v_5155_7) (or (<= c_ULTIMATE.start_main_p1 v_idx_2366) (= (select |c_#memory_int| v_idx_2366) v_v_5150_7)) (or (< v_idx_2367 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_2367) 0) (<= .cse14 v_idx_2367)) (<= v_v_5153_7 0) (or (= (select |c_#memory_int| v_idx_2370) v_v_5154_7) (< v_idx_2370 .cse15) (<= c_ULTIMATE.start_main_p3 v_idx_2370)) (<= .cse15 c_ULTIMATE.start_main_p3) (<= 0 v_v_5155_7) (or (< v_idx_2372 .cse16) (= (select |c_#memory_int| v_idx_2372) v_v_5156_7)) (<= 0 (* 2 v_v_5155_7)) (or (= (select |c_#memory_int| v_idx_2371) v_v_5155_7) (<= .cse16 v_idx_2371) (< v_idx_2371 c_ULTIMATE.start_main_p3)) (<= .cse14 c_ULTIMATE.start_main_p2) (<= (* 2 v_v_5153_7) 0)))))) is different from false [2019-01-11 11:55:41,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:55:41,885 INFO L93 Difference]: Finished difference Result 34 states and 101 transitions. [2019-01-11 11:55:41,885 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-01-11 11:55:41,885 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 6 [2019-01-11 11:55:41,885 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:55:41,886 INFO L225 Difference]: With dead ends: 34 [2019-01-11 11:55:41,886 INFO L226 Difference]: Without dead ends: 31 [2019-01-11 11:55:41,886 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 14.8s TimeCoverageRelationStatistics Valid=13, Invalid=7, Unknown=6, NotChecked=30, Total=56 [2019-01-11 11:55:41,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2019-01-11 11:55:41,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 31. [2019-01-11 11:55:41,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2019-01-11 11:55:41,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 98 transitions. [2019-01-11 11:55:41,929 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 98 transitions. Word has length 6 [2019-01-11 11:55:41,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:55:41,929 INFO L480 AbstractCegarLoop]: Abstraction has 31 states and 98 transitions. [2019-01-11 11:55:41,929 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-01-11 11:55:41,929 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 98 transitions. [2019-01-11 11:55:41,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-11 11:55:41,929 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:55:41,929 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1] [2019-01-11 11:55:41,929 INFO L423 AbstractCegarLoop]: === Iteration 35 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:55:41,930 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:55:41,930 INFO L82 PathProgramCache]: Analyzing trace with hash 897102474, now seen corresponding path program 3 times [2019-01-11 11:55:41,930 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:55:41,930 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:55:41,930 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:55:41,930 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:55:41,931 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:55:41,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:55:42,105 WARN L181 SmtUtils]: Spent 134.00 ms on a formula simplification. DAG size of input: 31 DAG size of output: 17 [2019-01-11 11:55:42,154 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-11 11:55:42,154 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:55:42,154 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:55:42,154 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:55:42,155 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:55:42,155 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:55:42,155 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:55:42,164 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2019-01-11 11:55:42,165 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2019-01-11 11:55:42,169 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2019-01-11 11:55:42,169 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:55:42,170 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:55:42,173 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-11 11:55:42,175 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,176 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 21 [2019-01-11 11:55:42,181 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,182 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,183 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 28 [2019-01-11 11:55:42,183 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-11 11:55:42,194 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:55:42,201 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:55:42,213 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:55:42,213 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 1 variables, input treesize:19, output treesize:22 [2019-01-11 11:55:42,242 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,244 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,245 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,246 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,247 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 34 [2019-01-11 11:55:42,248 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:55:42,264 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:55:42,264 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:32, output treesize:22 [2019-01-11 11:55:42,284 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,285 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,286 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,287 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,288 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,289 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,290 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 50 [2019-01-11 11:55:42,291 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:55:42,311 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:55:42,311 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:34, output treesize:24 [2019-01-11 11:55:42,333 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,334 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,335 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,336 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,337 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,339 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,340 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,341 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,341 INFO L683 Elim1Store]: detected equality via solver [2019-01-11 11:55:42,342 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 56 [2019-01-11 11:55:42,343 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:55:42,365 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:55:42,365 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:34, output treesize:24 [2019-01-11 11:55:42,398 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,399 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,400 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,401 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,402 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,403 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:42,404 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 40 [2019-01-11 11:55:42,405 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:55:42,424 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:55:42,424 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:22 [2019-01-11 11:55:42,440 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:55:42,440 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:55:42,491 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:55:42,510 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-11 11:55:42,510 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5, 5] total 14 [2019-01-11 11:55:42,510 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-11 11:55:42,510 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2019-01-11 11:55:42,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2019-01-11 11:55:42,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=148, Unknown=0, NotChecked=0, Total=240 [2019-01-11 11:55:42,511 INFO L87 Difference]: Start difference. First operand 31 states and 98 transitions. Second operand 11 states. [2019-01-11 11:55:42,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:55:42,847 INFO L93 Difference]: Finished difference Result 42 states and 113 transitions. [2019-01-11 11:55:42,848 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-01-11 11:55:42,848 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 6 [2019-01-11 11:55:42,848 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:55:42,849 INFO L225 Difference]: With dead ends: 42 [2019-01-11 11:55:42,849 INFO L226 Difference]: Without dead ends: 41 [2019-01-11 11:55:42,849 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 0 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 87 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=112, Invalid=194, Unknown=0, NotChecked=0, Total=306 [2019-01-11 11:55:42,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2019-01-11 11:55:42,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 11. [2019-01-11 11:55:42,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11 states. [2019-01-11 11:55:42,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 25 transitions. [2019-01-11 11:55:42,886 INFO L78 Accepts]: Start accepts. Automaton has 11 states and 25 transitions. Word has length 6 [2019-01-11 11:55:42,887 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:55:42,887 INFO L480 AbstractCegarLoop]: Abstraction has 11 states and 25 transitions. [2019-01-11 11:55:42,887 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2019-01-11 11:55:42,887 INFO L276 IsEmpty]: Start isEmpty. Operand 11 states and 25 transitions. [2019-01-11 11:55:42,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2019-01-11 11:55:42,887 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:55:42,887 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1] [2019-01-11 11:55:42,887 INFO L423 AbstractCegarLoop]: === Iteration 36 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:55:42,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:55:42,887 INFO L82 PathProgramCache]: Analyzing trace with hash 898899796, now seen corresponding path program 2 times [2019-01-11 11:55:42,888 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:55:42,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:55:42,888 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:55:42,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:55:42,888 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:55:42,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:55:43,193 WARN L181 SmtUtils]: Spent 272.00 ms on a formula simplification. DAG size of input: 17 DAG size of output: 9 [2019-01-11 11:55:43,242 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:55:43,243 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:55:43,243 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:55:43,243 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:55:43,243 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:55:43,243 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:55:43,243 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:55:43,253 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-11 11:55:43,253 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-11 11:55:43,260 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-11 11:55:43,260 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:55:43,261 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:55:43,263 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2019-01-11 11:55:43,266 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 17 [2019-01-11 11:55:43,271 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:43,271 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 20 [2019-01-11 11:55:43,272 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2019-01-11 11:55:43,279 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:55:43,286 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:55:43,296 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:55:43,296 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 2 variables, input treesize:16, output treesize:19 [2019-01-11 11:55:43,318 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:43,318 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:43,319 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 21 [2019-01-11 11:55:43,319 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:55:43,329 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:55:43,329 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:24, output treesize:14 [2019-01-11 11:55:43,343 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:43,344 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:43,345 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:43,346 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:55:43,347 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 4 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 27 [2019-01-11 11:55:43,348 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:55:43,359 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2019-01-11 11:55:43,360 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:24, output treesize:14 [2019-01-11 11:55:43,374 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:55:43,374 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:55:43,394 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:55:43,413 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-11 11:55:43,413 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 3, 3] total 9 [2019-01-11 11:55:43,413 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-11 11:55:43,413 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-01-11 11:55:43,413 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-01-11 11:55:43,413 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=64, Unknown=0, NotChecked=0, Total=110 [2019-01-11 11:55:43,414 INFO L87 Difference]: Start difference. First operand 11 states and 25 transitions. Second operand 9 states. [2019-01-11 11:55:43,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:55:43,568 INFO L93 Difference]: Finished difference Result 16 states and 37 transitions. [2019-01-11 11:55:43,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-01-11 11:55:43,569 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 6 [2019-01-11 11:55:43,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:55:43,569 INFO L225 Difference]: With dead ends: 16 [2019-01-11 11:55:43,569 INFO L226 Difference]: Without dead ends: 0 [2019-01-11 11:55:43,570 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=54, Invalid=78, Unknown=0, NotChecked=0, Total=132 [2019-01-11 11:55:43,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2019-01-11 11:55:43,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2019-01-11 11:55:43,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 0 states. [2019-01-11 11:55:43,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2019-01-11 11:55:43,571 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 6 [2019-01-11 11:55:43,571 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:55:43,571 INFO L480 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2019-01-11 11:55:43,572 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-01-11 11:55:43,572 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2019-01-11 11:55:43,572 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2019-01-11 11:55:43,575 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 0 states and 0 transitions. [2019-01-11 11:55:43,688 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2019-01-11 11:55:43,689 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2019-01-11 11:55:43,699 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2019-01-11 11:55:43,704 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2019-01-11 11:55:43,710 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2019-01-11 11:55:43,714 WARN L250 erpolLogProxyWrapper]: Already inconsistent. [2019-01-11 11:55:43,963 WARN L181 SmtUtils]: Spent 370.00 ms on a formula simplification. DAG size of input: 3441 DAG size of output: 3382