java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml -s ../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf -i ../../../trunk/examples/programs/heapseparator/speedup-poc-dd-4-limited.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.24-df3cc4e-m [2019-01-11 11:42:13,642 INFO L170 SettingsManager]: Resetting all preferences to default values... [2019-01-11 11:42:13,644 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2019-01-11 11:42:13,660 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2019-01-11 11:42:13,720 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf [2019-01-11 11:42:13,739 INFO L110 SettingsManager]: Loading preferences was successful [2019-01-11 11:42:13,739 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2019-01-11 11:42:13,743 INFO L131 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2019-01-11 11:42:13,743 INFO L133 SettingsManager]: * Show backtranslation warnings=false [2019-01-11 11:42:13,743 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-01-11 11:42:13,744 INFO L133 SettingsManager]: * User list type=DISABLED [2019-01-11 11:42:13,744 INFO L133 SettingsManager]: * Inline calls to unimplemented procedures=true [2019-01-11 11:42:13,744 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-01-11 11:42:13,744 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-01-11 11:42:13,745 INFO L133 SettingsManager]: * Underlying domain=OctagonDomain [2019-01-11 11:42:13,745 INFO L133 SettingsManager]: * Abstract domain=ArrayDomain [2019-01-11 11:42:13,745 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-01-11 11:42:13,746 INFO L133 SettingsManager]: * Interval Domain=false [2019-01-11 11:42:13,746 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-01-11 11:42:13,747 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2019-01-11 11:42:13,747 INFO L133 SettingsManager]: * Use SBE=true [2019-01-11 11:42:13,747 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-01-11 11:42:13,747 INFO L133 SettingsManager]: * sizeof long=4 [2019-01-11 11:42:13,748 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2019-01-11 11:42:13,748 INFO L133 SettingsManager]: * sizeof POINTER=4 [2019-01-11 11:42:13,748 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2019-01-11 11:42:13,748 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-01-11 11:42:13,748 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-01-11 11:42:13,749 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-01-11 11:42:13,749 INFO L133 SettingsManager]: * sizeof long double=12 [2019-01-11 11:42:13,749 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2019-01-11 11:42:13,749 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-01-11 11:42:13,750 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-01-11 11:42:13,750 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-01-11 11:42:13,750 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2019-01-11 11:42:13,750 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-11 11:42:13,750 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-01-11 11:42:13,751 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-01-11 11:42:13,751 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-01-11 11:42:13,751 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2019-01-11 11:42:13,751 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-01-11 11:42:13,751 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in [2019-01-11 11:42:13,752 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-01-11 11:42:13,752 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2019-01-11 11:42:13,780 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-01-11 11:42:13,792 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-01-11 11:42:13,795 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-01-11 11:42:13,797 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2019-01-11 11:42:13,797 INFO L276 PluginConnector]: Boogie PL CUP Parser initialized [2019-01-11 11:42:13,798 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-4-limited.bpl [2019-01-11 11:42:13,798 INFO L111 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-4-limited.bpl' [2019-01-11 11:42:13,841 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-01-11 11:42:13,843 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-01-11 11:42:13,844 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-01-11 11:42:13,844 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-01-11 11:42:13,844 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2019-01-11 11:42:13,861 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:13" (1/1) ... [2019-01-11 11:42:13,877 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:13" (1/1) ... [2019-01-11 11:42:13,907 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-01-11 11:42:13,907 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-01-11 11:42:13,908 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-01-11 11:42:13,908 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2019-01-11 11:42:13,919 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:13" (1/1) ... [2019-01-11 11:42:13,920 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:13" (1/1) ... [2019-01-11 11:42:13,921 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:13" (1/1) ... [2019-01-11 11:42:13,922 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:13" (1/1) ... [2019-01-11 11:42:13,925 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:13" (1/1) ... [2019-01-11 11:42:13,930 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:13" (1/1) ... [2019-01-11 11:42:13,933 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:13" (1/1) ... [2019-01-11 11:42:13,939 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-01-11 11:42:13,940 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-01-11 11:42:13,940 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-01-11 11:42:13,940 INFO L276 PluginConnector]: RCFGBuilder initialized [2019-01-11 11:42:13,941 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:13" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-11 11:42:14,003 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-01-11 11:42:14,003 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-01-11 11:42:14,238 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-01-11 11:42:14,238 INFO L286 CfgBuilder]: Removed 11 assue(true) statements. [2019-01-11 11:42:14,241 INFO L202 PluginConnector]: Adding new model speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.01 11:42:14 BoogieIcfgContainer [2019-01-11 11:42:14,241 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-01-11 11:42:14,242 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-01-11 11:42:14,242 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-01-11 11:42:14,246 INFO L276 PluginConnector]: TraceAbstraction initialized [2019-01-11 11:42:14,247 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:13" (1/2) ... [2019-01-11 11:42:14,248 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7c45702b and model type speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.01 11:42:14, skipping insertion in model container [2019-01-11 11:42:14,248 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-4-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.01 11:42:14" (2/2) ... [2019-01-11 11:42:14,250 INFO L112 eAbstractionObserver]: Analyzing ICFG speedup-poc-dd-4-limited.bpl [2019-01-11 11:42:14,261 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-01-11 11:42:14,270 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 4 error locations. [2019-01-11 11:42:14,286 INFO L257 AbstractCegarLoop]: Starting to check reachability of 4 error locations. [2019-01-11 11:42:14,323 INFO L382 AbstractCegarLoop]: Interprodecural is true [2019-01-11 11:42:14,323 INFO L383 AbstractCegarLoop]: Hoare is true [2019-01-11 11:42:14,324 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-01-11 11:42:14,324 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-01-11 11:42:14,324 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-01-11 11:42:14,324 INFO L387 AbstractCegarLoop]: Difference is false [2019-01-11 11:42:14,324 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-01-11 11:42:14,325 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-01-11 11:42:14,342 INFO L276 IsEmpty]: Start isEmpty. Operand 11 states. [2019-01-11 11:42:14,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3 [2019-01-11 11:42:14,352 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:42:14,353 INFO L402 BasicCegarLoop]: trace histogram [1, 1] [2019-01-11 11:42:14,357 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:42:14,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:42:14,365 INFO L82 PathProgramCache]: Analyzing trace with hash 980, now seen corresponding path program 1 times [2019-01-11 11:42:14,368 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:42:14,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:14,410 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:42:14,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:14,410 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:42:14,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:42:14,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:42:14,591 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-11 11:42:14,592 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-11 11:42:14,592 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:42:14,598 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-11 11:42:14,612 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-11 11:42:14,613 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:42:14,617 INFO L87 Difference]: Start difference. First operand 11 states. Second operand 3 states. [2019-01-11 11:42:14,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:42:14,749 INFO L93 Difference]: Finished difference Result 21 states and 27 transitions. [2019-01-11 11:42:14,750 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:42:14,751 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 2 [2019-01-11 11:42:14,752 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:42:14,765 INFO L225 Difference]: With dead ends: 21 [2019-01-11 11:42:14,765 INFO L226 Difference]: Without dead ends: 16 [2019-01-11 11:42:14,769 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:42:14,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-11 11:42:14,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 10. [2019-01-11 11:42:14,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2019-01-11 11:42:14,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 17 transitions. [2019-01-11 11:42:14,806 INFO L78 Accepts]: Start accepts. Automaton has 10 states and 17 transitions. Word has length 2 [2019-01-11 11:42:14,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:42:14,808 INFO L480 AbstractCegarLoop]: Abstraction has 10 states and 17 transitions. [2019-01-11 11:42:14,808 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-11 11:42:14,808 INFO L276 IsEmpty]: Start isEmpty. Operand 10 states and 17 transitions. [2019-01-11 11:42:14,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:42:14,809 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:42:14,809 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:42:14,809 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:42:14,810 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:42:14,810 INFO L82 PathProgramCache]: Analyzing trace with hash 30306, now seen corresponding path program 1 times [2019-01-11 11:42:14,810 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:42:14,811 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:14,811 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:42:14,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:14,812 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:42:14,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:42:15,171 WARN L181 SmtUtils]: Spent 286.00 ms on a formula simplification. DAG size of input: 19 DAG size of output: 13 [2019-01-11 11:42:15,189 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:42:15,190 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:42:15,190 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:42:15,191 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:42:15,195 INFO L207 CegarAbsIntRunner]: [0], [16], [19] [2019-01-11 11:42:15,249 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:42:15,249 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:42:23,466 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:42:23,467 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:42:23,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:42:23,473 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:42:23,847 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 68.75% of their original sizes. [2019-01-11 11:42:23,847 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:42:26,132 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_79 Int) (v_idx_87 Int) (v_idx_85 Int) (v_idx_86 Int) (v_idx_83 Int) (v_idx_84 Int) (v_idx_81 Int) (v_idx_82 Int) (v_idx_80 Int)) (exists ((v_b_121_1 Int) (v_v_1149_1 Int) (v_b_120_1 Int) (v_b_119_1 Int) (v_b_118_1 Int) (v_v_1145_1 Int) (v_v_1147_1 Int) (v_v_1151_1 Int) (v_v_1152_1 Int) (v_v_1153_1 Int)) (let ((.cse0 (+ v_b_120_1 1)) (.cse3 (+ v_b_118_1 1)) (.cse2 (+ v_b_119_1 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 3)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ c_ULTIMATE.start_main_p4 1)) (.cse6 (+ v_b_118_1 2))) (and (<= .cse0 v_b_121_1) (<= v_b_121_1 .cse0) (<= .cse1 v_b_120_1) (<= .cse2 c_ULTIMATE.start_main_p4) (<= .cse3 v_b_120_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_79) (= (select |c_#memory_int| v_idx_79) v_v_1145_1)) (<= .cse4 v_b_118_1) (<= .cse3 v_b_119_1) (or (< v_idx_85 v_b_121_1) (<= c_ULTIMATE.start_main_p4 v_idx_85) (= (select |c_#memory_int| v_idx_85) v_v_1151_1)) (<= (* 2 v_v_1152_1) 0) (<= v_b_119_1 v_b_120_1) (<= .cse0 c_ULTIMATE.start_main_p4) (<= .cse5 c_ULTIMATE.start_main_p4) (<= v_b_119_1 .cse3) (or (< v_idx_82 v_b_118_1) (= 0 (select |c_#memory_int| v_idx_82)) (<= v_b_119_1 v_idx_82)) (<= v_v_1152_1 0) (<= .cse6 v_b_121_1) (or (<= .cse4 v_idx_80) (= 0 (select |c_#memory_int| v_idx_80)) (< v_idx_80 c_ULTIMATE.start_main_p1)) (<= .cse2 v_b_121_1) (<= v_b_121_1 c_ULTIMATE.start_main_p4) (<= .cse5 v_b_121_1) (or (= (select |c_#memory_int| v_idx_81) v_v_1147_1) (< v_idx_81 .cse4) (<= v_b_118_1 v_idx_81)) (<= .cse1 v_b_119_1) (or (= (select |c_#memory_int| v_idx_83) v_v_1149_1) (<= v_b_120_1 v_idx_83) (< v_idx_83 v_b_119_1)) (or (< v_idx_87 .cse7) (= (select |c_#memory_int| v_idx_87) v_v_1153_1)) (or (< v_idx_84 v_b_120_1) (= 0 (select |c_#memory_int| v_idx_84)) (<= v_b_121_1 v_idx_84)) (or (= (select |c_#memory_int| v_idx_86) v_v_1152_1) (<= .cse7 v_idx_86) (< v_idx_86 c_ULTIMATE.start_main_p4)) (<= .cse6 c_ULTIMATE.start_main_p4))))) is different from false [2019-01-11 11:42:28,526 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_89 Int) (v_idx_88 Int) (v_idx_96 Int) (v_idx_94 Int) (v_idx_95 Int) (v_idx_92 Int) (v_idx_93 Int) (v_idx_90 Int) (v_idx_91 Int)) (exists ((v_b_122_1 Int) (v_b_121_1 Int) (v_b_123_1 Int) (v_v_1149_1 Int) (v_b_120_1 Int) (v_b_119_1 Int) (v_b_118_1 Int) (v_v_1145_1 Int) (v_v_1147_1 Int) (v_v_1151_1 Int) (v_v_1152_1 Int) (v_v_1153_1 Int)) (let ((.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_120_1 1)) (.cse4 (+ v_b_118_1 1)) (.cse0 (+ v_b_118_1 2)) (.cse6 (+ v_b_119_1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 3)) (.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ v_b_122_1 1))) (and (<= .cse0 v_b_122_1) (<= .cse1 v_b_121_1) (or (= (select |c_#memory_int| v_idx_94) v_v_1151_1) (< v_idx_94 v_b_121_1) (<= v_b_122_1 v_idx_94)) (<= v_b_121_1 .cse1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_123_1) (<= .cse2 v_b_120_1) (<= .cse3 v_b_122_1) (<= .cse4 v_b_120_1) (<= .cse5 v_b_118_1) (<= .cse4 v_b_119_1) (<= (+ v_b_119_1 2) v_b_123_1) (or (< v_idx_90 .cse5) (<= v_b_118_1 v_idx_90) (= (select |c_#memory_int| v_idx_90) v_v_1147_1)) (or (< v_idx_91 v_b_118_1) (<= v_b_119_1 v_idx_91) (= 0 (select |c_#memory_int| v_idx_91))) (<= (* 2 v_v_1152_1) 0) (or (< v_idx_89 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_89)) (<= .cse5 v_idx_89)) (<= v_b_119_1 v_b_120_1) (<= .cse1 v_b_122_1) (or (= (select |c_#memory_int| v_idx_96) v_v_1153_1) (< v_idx_96 v_b_123_1)) (<= v_b_121_1 v_b_122_1) (or (< v_idx_95 v_b_122_1) (= (select |c_#memory_int| v_idx_95) v_v_1152_1) (<= v_b_123_1 v_idx_95)) (<= .cse6 v_b_122_1) (<= v_b_119_1 .cse4) (<= v_v_1152_1 0) (<= .cse0 v_b_121_1) (or (<= v_b_121_1 v_idx_93) (< v_idx_93 v_b_120_1) (= 0 (select |c_#memory_int| v_idx_93))) (<= .cse6 v_b_121_1) (<= (+ v_b_121_1 1) v_b_123_1) (<= .cse3 v_b_121_1) (<= .cse7 v_b_123_1) (or (= (select |c_#memory_int| v_idx_92) v_v_1149_1) (< v_idx_92 v_b_119_1) (<= v_b_120_1 v_idx_92)) (<= .cse2 v_b_119_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_88) (= (select |c_#memory_int| v_idx_88) v_v_1145_1)) (<= v_b_123_1 .cse7) (<= (+ v_b_120_1 2) v_b_123_1) (<= (+ v_b_118_1 3) v_b_123_1))))) is different from false [2019-01-11 11:42:28,605 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:42:28,605 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:42:28,606 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:42:28,606 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:42:28,607 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:42:28,608 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:42:28,608 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:42:28,608 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:42:28,609 INFO L87 Difference]: Start difference. First operand 10 states and 17 transitions. Second operand 4 states. [2019-01-11 11:42:30,872 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_89 Int) (v_idx_88 Int) (v_idx_96 Int) (v_idx_94 Int) (v_idx_95 Int) (v_idx_92 Int) (v_idx_93 Int) (v_idx_90 Int) (v_idx_91 Int)) (exists ((v_b_122_1 Int) (v_b_121_1 Int) (v_b_123_1 Int) (v_v_1149_1 Int) (v_b_120_1 Int) (v_b_119_1 Int) (v_b_118_1 Int) (v_v_1145_1 Int) (v_v_1147_1 Int) (v_v_1151_1 Int) (v_v_1152_1 Int) (v_v_1153_1 Int)) (let ((.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_120_1 1)) (.cse4 (+ v_b_118_1 1)) (.cse0 (+ v_b_118_1 2)) (.cse6 (+ v_b_119_1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 3)) (.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ v_b_122_1 1))) (and (<= .cse0 v_b_122_1) (<= .cse1 v_b_121_1) (or (= (select |c_#memory_int| v_idx_94) v_v_1151_1) (< v_idx_94 v_b_121_1) (<= v_b_122_1 v_idx_94)) (<= v_b_121_1 .cse1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_123_1) (<= .cse2 v_b_120_1) (<= .cse3 v_b_122_1) (<= .cse4 v_b_120_1) (<= .cse5 v_b_118_1) (<= .cse4 v_b_119_1) (<= (+ v_b_119_1 2) v_b_123_1) (or (< v_idx_90 .cse5) (<= v_b_118_1 v_idx_90) (= (select |c_#memory_int| v_idx_90) v_v_1147_1)) (or (< v_idx_91 v_b_118_1) (<= v_b_119_1 v_idx_91) (= 0 (select |c_#memory_int| v_idx_91))) (<= (* 2 v_v_1152_1) 0) (or (< v_idx_89 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_89)) (<= .cse5 v_idx_89)) (<= v_b_119_1 v_b_120_1) (<= .cse1 v_b_122_1) (or (= (select |c_#memory_int| v_idx_96) v_v_1153_1) (< v_idx_96 v_b_123_1)) (<= v_b_121_1 v_b_122_1) (or (< v_idx_95 v_b_122_1) (= (select |c_#memory_int| v_idx_95) v_v_1152_1) (<= v_b_123_1 v_idx_95)) (<= .cse6 v_b_122_1) (<= v_b_119_1 .cse4) (<= v_v_1152_1 0) (<= .cse0 v_b_121_1) (or (<= v_b_121_1 v_idx_93) (< v_idx_93 v_b_120_1) (= 0 (select |c_#memory_int| v_idx_93))) (<= .cse6 v_b_121_1) (<= (+ v_b_121_1 1) v_b_123_1) (<= .cse3 v_b_121_1) (<= .cse7 v_b_123_1) (or (= (select |c_#memory_int| v_idx_92) v_v_1149_1) (< v_idx_92 v_b_119_1) (<= v_b_120_1 v_idx_92)) (<= .cse2 v_b_119_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_88) (= (select |c_#memory_int| v_idx_88) v_v_1145_1)) (<= v_b_123_1 .cse7) (<= (+ v_b_120_1 2) v_b_123_1) (<= (+ v_b_118_1 3) v_b_123_1))))) (forall ((v_idx_79 Int) (v_idx_87 Int) (v_idx_85 Int) (v_idx_86 Int) (v_idx_83 Int) (v_idx_84 Int) (v_idx_81 Int) (v_idx_82 Int) (v_idx_80 Int)) (exists ((v_b_121_1 Int) (v_v_1149_1 Int) (v_b_120_1 Int) (v_b_119_1 Int) (v_b_118_1 Int) (v_v_1145_1 Int) (v_v_1147_1 Int) (v_v_1151_1 Int) (v_v_1152_1 Int) (v_v_1153_1 Int)) (let ((.cse8 (+ v_b_120_1 1)) (.cse11 (+ v_b_118_1 1)) (.cse10 (+ v_b_119_1 1)) (.cse13 (+ c_ULTIMATE.start_main_p1 3)) (.cse12 (+ c_ULTIMATE.start_main_p1 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 2)) (.cse15 (+ c_ULTIMATE.start_main_p4 1)) (.cse14 (+ v_b_118_1 2))) (and (<= .cse8 v_b_121_1) (<= v_b_121_1 .cse8) (<= .cse9 v_b_120_1) (<= .cse10 c_ULTIMATE.start_main_p4) (<= .cse11 v_b_120_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_79) (= (select |c_#memory_int| v_idx_79) v_v_1145_1)) (<= .cse12 v_b_118_1) (<= .cse11 v_b_119_1) (or (< v_idx_85 v_b_121_1) (<= c_ULTIMATE.start_main_p4 v_idx_85) (= (select |c_#memory_int| v_idx_85) v_v_1151_1)) (<= (* 2 v_v_1152_1) 0) (<= v_b_119_1 v_b_120_1) (<= .cse8 c_ULTIMATE.start_main_p4) (<= .cse13 c_ULTIMATE.start_main_p4) (<= v_b_119_1 .cse11) (or (< v_idx_82 v_b_118_1) (= 0 (select |c_#memory_int| v_idx_82)) (<= v_b_119_1 v_idx_82)) (<= v_v_1152_1 0) (<= .cse14 v_b_121_1) (or (<= .cse12 v_idx_80) (= 0 (select |c_#memory_int| v_idx_80)) (< v_idx_80 c_ULTIMATE.start_main_p1)) (<= .cse10 v_b_121_1) (<= v_b_121_1 c_ULTIMATE.start_main_p4) (<= .cse13 v_b_121_1) (or (= (select |c_#memory_int| v_idx_81) v_v_1147_1) (< v_idx_81 .cse12) (<= v_b_118_1 v_idx_81)) (<= .cse9 v_b_119_1) (or (= (select |c_#memory_int| v_idx_83) v_v_1149_1) (<= v_b_120_1 v_idx_83) (< v_idx_83 v_b_119_1)) (or (< v_idx_87 .cse15) (= (select |c_#memory_int| v_idx_87) v_v_1153_1)) (or (< v_idx_84 v_b_120_1) (= 0 (select |c_#memory_int| v_idx_84)) (<= v_b_121_1 v_idx_84)) (or (= (select |c_#memory_int| v_idx_86) v_v_1152_1) (<= .cse15 v_idx_86) (< v_idx_86 c_ULTIMATE.start_main_p4)) (<= .cse14 c_ULTIMATE.start_main_p4)))))) is different from false [2019-01-11 11:42:55,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:42:55,651 INFO L93 Difference]: Finished difference Result 12 states and 23 transitions. [2019-01-11 11:42:55,652 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:42:55,652 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:42:55,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:42:55,653 INFO L225 Difference]: With dead ends: 12 [2019-01-11 11:42:55,654 INFO L226 Difference]: Without dead ends: 11 [2019-01-11 11:42:55,655 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 6.9s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:42:55,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2019-01-11 11:42:55,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2019-01-11 11:42:55,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11 states. [2019-01-11 11:42:55,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 22 transitions. [2019-01-11 11:42:55,661 INFO L78 Accepts]: Start accepts. Automaton has 11 states and 22 transitions. Word has length 3 [2019-01-11 11:42:55,661 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:42:55,661 INFO L480 AbstractCegarLoop]: Abstraction has 11 states and 22 transitions. [2019-01-11 11:42:55,661 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:42:55,662 INFO L276 IsEmpty]: Start isEmpty. Operand 11 states and 22 transitions. [2019-01-11 11:42:55,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:42:55,662 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:42:55,662 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:42:55,663 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:42:55,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:42:55,664 INFO L82 PathProgramCache]: Analyzing trace with hash 30432, now seen corresponding path program 1 times [2019-01-11 11:42:55,664 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:42:55,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:55,665 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:42:55,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:55,666 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:42:55,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:42:55,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:42:55,740 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-11 11:42:55,740 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-11 11:42:55,740 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:42:55,740 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-11 11:42:55,741 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-11 11:42:55,741 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:42:55,741 INFO L87 Difference]: Start difference. First operand 11 states and 22 transitions. Second operand 3 states. [2019-01-11 11:42:55,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:42:55,940 INFO L93 Difference]: Finished difference Result 17 states and 27 transitions. [2019-01-11 11:42:55,941 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:42:55,941 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-01-11 11:42:55,941 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:42:55,942 INFO L225 Difference]: With dead ends: 17 [2019-01-11 11:42:55,942 INFO L226 Difference]: Without dead ends: 16 [2019-01-11 11:42:55,943 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:42:55,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-11 11:42:55,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 12. [2019-01-11 11:42:55,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2019-01-11 11:42:55,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 23 transitions. [2019-01-11 11:42:55,948 INFO L78 Accepts]: Start accepts. Automaton has 12 states and 23 transitions. Word has length 3 [2019-01-11 11:42:55,948 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:42:55,948 INFO L480 AbstractCegarLoop]: Abstraction has 12 states and 23 transitions. [2019-01-11 11:42:55,949 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-11 11:42:55,949 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 23 transitions. [2019-01-11 11:42:55,949 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:42:55,949 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:42:55,949 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:42:55,950 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:42:55,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:42:55,950 INFO L82 PathProgramCache]: Analyzing trace with hash 29996, now seen corresponding path program 1 times [2019-01-11 11:42:55,950 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:42:55,951 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:55,951 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:42:55,952 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:55,952 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:42:55,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:42:56,069 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:42:56,070 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:42:56,070 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:42:56,070 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:42:56,070 INFO L207 CegarAbsIntRunner]: [0], [6], [19] [2019-01-11 11:42:56,071 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:42:56,071 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:43:00,921 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:43:00,921 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:43:00,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:43:00,921 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:43:01,197 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 75% of their original sizes. [2019-01-11 11:43:01,197 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:43:03,442 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_179 Int) (v_idx_180 Int) (v_idx_181 Int) (v_idx_182 Int) (v_idx_183 Int) (v_idx_177 Int) (v_idx_178 Int) (v_idx_175 Int) (v_idx_176 Int)) (exists ((v_b_134_2 Int) (v_v_1148_2 Int) (v_b_137_2 Int) (v_b_138_2 Int) (v_v_1144_2 Int) (v_b_135_2 Int) (v_v_1145_2 Int) (v_v_1146_2 Int) (v_b_136_2 Int) (v_v_1150_2 Int) (v_b_139_2 Int) (v_v_1152_2 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p1 2)) (.cse5 (+ v_b_134_2 2)) (.cse4 (+ v_b_135_2 1)) (.cse3 (+ v_b_136_2 1)) (.cse2 (+ v_b_134_2 1)) (.cse7 (+ v_b_138_2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse6 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_2) (<= .cse0 v_b_135_2) (<= (+ v_b_136_2 2) v_b_139_2) (<= .cse1 v_b_137_2) (or (< v_idx_183 v_b_139_2) (= (select |c_#memory_int| v_idx_183) v_v_1152_2)) (<= .cse2 v_b_135_2) (or (<= v_b_139_2 v_idx_182) (= 0 (select |c_#memory_int| v_idx_182)) (< v_idx_182 v_b_138_2)) (or (= (select |c_#memory_int| v_idx_178) 0) (< v_idx_178 v_b_134_2) (<= v_b_135_2 v_idx_178)) (<= 0 (* 2 v_v_1145_2)) (<= v_b_135_2 v_b_136_2) (<= v_b_137_2 .cse3) (<= .cse4 v_b_138_2) (<= (+ v_b_137_2 1) v_b_139_2) (<= (+ v_b_135_2 2) v_b_139_2) (<= (+ v_b_134_2 3) v_b_139_2) (<= .cse0 v_b_136_2) (<= v_b_135_2 .cse2) (<= .cse5 v_b_137_2) (or (= (select |c_#memory_int| v_idx_176) v_v_1145_2) (< v_idx_176 c_ULTIMATE.start_main_p1) (<= .cse6 v_idx_176)) (<= .cse5 v_b_138_2) (<= .cse4 v_b_137_2) (or (< v_idx_177 .cse6) (= (select |c_#memory_int| v_idx_177) v_v_1146_2) (<= v_b_134_2 v_idx_177)) (<= v_b_137_2 v_b_138_2) (or (< v_idx_181 v_b_137_2) (<= v_b_138_2 v_idx_181) (= (select |c_#memory_int| v_idx_181) v_v_1150_2)) (<= .cse3 v_b_137_2) (or (= (select |c_#memory_int| v_idx_179) v_v_1148_2) (<= v_b_136_2 v_idx_179) (< v_idx_179 v_b_135_2)) (<= .cse3 v_b_138_2) (<= v_b_139_2 .cse7) (or (<= c_ULTIMATE.start_main_p1 v_idx_175) (= (select |c_#memory_int| v_idx_175) v_v_1144_2)) (<= .cse2 v_b_136_2) (<= .cse7 v_b_139_2) (or (< v_idx_180 v_b_136_2) (<= v_b_137_2 v_idx_180) (= (select |c_#memory_int| v_idx_180) 0)) (<= .cse1 v_b_138_2) (<= .cse6 v_b_134_2) (<= 0 v_v_1145_2))))) is different from false [2019-01-11 11:43:05,941 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_191 Int) (v_idx_192 Int) (v_idx_190 Int) (v_idx_184 Int) (v_idx_185 Int) (v_idx_188 Int) (v_idx_189 Int) (v_idx_186 Int) (v_idx_187 Int)) (exists ((v_v_1148_2 Int) (v_b_134_2 Int) (v_b_137_2 Int) (v_b_138_2 Int) (v_v_1144_2 Int) (v_b_135_2 Int) (v_v_1145_2 Int) (v_b_136_2 Int) (v_v_1146_2 Int) (v_v_1150_2 Int) (v_b_139_2 Int) (v_v_1152_2 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p1 2)) (.cse6 (+ v_b_134_2 2)) (.cse5 (+ v_b_135_2 1)) (.cse4 (+ v_b_136_2 1)) (.cse3 (+ v_b_134_2 1)) (.cse7 (+ v_b_138_2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 3)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_2) (<= .cse0 v_b_135_2) (or (< v_idx_185 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_185) (= (select |c_#memory_int| v_idx_185) v_v_1145_2)) (<= (+ v_b_136_2 2) v_b_139_2) (<= .cse2 v_b_137_2) (<= .cse3 v_b_135_2) (<= 0 (* 2 v_v_1145_2)) (<= v_b_135_2 v_b_136_2) (or (< v_idx_192 v_b_139_2) (= (select |c_#memory_int| v_idx_192) v_v_1152_2)) (<= v_b_137_2 .cse4) (<= .cse5 v_b_138_2) (<= (+ v_b_137_2 1) v_b_139_2) (<= (+ v_b_135_2 2) v_b_139_2) (<= (+ v_b_134_2 3) v_b_139_2) (<= .cse0 v_b_136_2) (<= v_b_135_2 .cse3) (<= .cse6 v_b_137_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_184) (= (select |c_#memory_int| v_idx_184) v_v_1144_2)) (<= .cse6 v_b_138_2) (<= .cse5 v_b_137_2) (or (< v_idx_187 v_b_134_2) (= 0 (select |c_#memory_int| v_idx_187)) (<= v_b_135_2 v_idx_187)) (or (<= v_b_136_2 v_idx_188) (= (select |c_#memory_int| v_idx_188) v_v_1148_2) (< v_idx_188 v_b_135_2)) (<= v_b_137_2 v_b_138_2) (<= .cse4 v_b_137_2) (or (<= v_b_138_2 v_idx_190) (< v_idx_190 v_b_137_2) (= (select |c_#memory_int| v_idx_190) v_v_1150_2)) (<= .cse4 v_b_138_2) (<= v_b_139_2 .cse7) (or (<= v_b_139_2 v_idx_191) (< v_idx_191 v_b_138_2) (= (select |c_#memory_int| v_idx_191) 0)) (or (= (select |c_#memory_int| v_idx_189) 0) (< v_idx_189 v_b_136_2) (<= v_b_137_2 v_idx_189)) (<= .cse3 v_b_136_2) (or (< v_idx_186 .cse1) (<= v_b_134_2 v_idx_186) (= (select |c_#memory_int| v_idx_186) v_v_1146_2)) (<= .cse7 v_b_139_2) (<= .cse2 v_b_138_2) (<= .cse1 v_b_134_2) (<= 0 v_v_1145_2))))) is different from false [2019-01-11 11:43:06,896 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:43:06,896 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:43:06,897 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:43:06,897 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:43:06,897 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:43:06,897 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:43:06,897 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:43:06,897 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:43:06,898 INFO L87 Difference]: Start difference. First operand 12 states and 23 transitions. Second operand 4 states. [2019-01-11 11:43:09,470 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_191 Int) (v_idx_192 Int) (v_idx_190 Int) (v_idx_184 Int) (v_idx_185 Int) (v_idx_188 Int) (v_idx_189 Int) (v_idx_186 Int) (v_idx_187 Int)) (exists ((v_v_1148_2 Int) (v_b_134_2 Int) (v_b_137_2 Int) (v_b_138_2 Int) (v_v_1144_2 Int) (v_b_135_2 Int) (v_v_1145_2 Int) (v_b_136_2 Int) (v_v_1146_2 Int) (v_v_1150_2 Int) (v_b_139_2 Int) (v_v_1152_2 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p1 2)) (.cse6 (+ v_b_134_2 2)) (.cse5 (+ v_b_135_2 1)) (.cse4 (+ v_b_136_2 1)) (.cse3 (+ v_b_134_2 1)) (.cse7 (+ v_b_138_2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 3)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_2) (<= .cse0 v_b_135_2) (or (< v_idx_185 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_185) (= (select |c_#memory_int| v_idx_185) v_v_1145_2)) (<= (+ v_b_136_2 2) v_b_139_2) (<= .cse2 v_b_137_2) (<= .cse3 v_b_135_2) (<= 0 (* 2 v_v_1145_2)) (<= v_b_135_2 v_b_136_2) (or (< v_idx_192 v_b_139_2) (= (select |c_#memory_int| v_idx_192) v_v_1152_2)) (<= v_b_137_2 .cse4) (<= .cse5 v_b_138_2) (<= (+ v_b_137_2 1) v_b_139_2) (<= (+ v_b_135_2 2) v_b_139_2) (<= (+ v_b_134_2 3) v_b_139_2) (<= .cse0 v_b_136_2) (<= v_b_135_2 .cse3) (<= .cse6 v_b_137_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_184) (= (select |c_#memory_int| v_idx_184) v_v_1144_2)) (<= .cse6 v_b_138_2) (<= .cse5 v_b_137_2) (or (< v_idx_187 v_b_134_2) (= 0 (select |c_#memory_int| v_idx_187)) (<= v_b_135_2 v_idx_187)) (or (<= v_b_136_2 v_idx_188) (= (select |c_#memory_int| v_idx_188) v_v_1148_2) (< v_idx_188 v_b_135_2)) (<= v_b_137_2 v_b_138_2) (<= .cse4 v_b_137_2) (or (<= v_b_138_2 v_idx_190) (< v_idx_190 v_b_137_2) (= (select |c_#memory_int| v_idx_190) v_v_1150_2)) (<= .cse4 v_b_138_2) (<= v_b_139_2 .cse7) (or (<= v_b_139_2 v_idx_191) (< v_idx_191 v_b_138_2) (= (select |c_#memory_int| v_idx_191) 0)) (or (= (select |c_#memory_int| v_idx_189) 0) (< v_idx_189 v_b_136_2) (<= v_b_137_2 v_idx_189)) (<= .cse3 v_b_136_2) (or (< v_idx_186 .cse1) (<= v_b_134_2 v_idx_186) (= (select |c_#memory_int| v_idx_186) v_v_1146_2)) (<= .cse7 v_b_139_2) (<= .cse2 v_b_138_2) (<= .cse1 v_b_134_2) (<= 0 v_v_1145_2))))) (forall ((v_idx_179 Int) (v_idx_180 Int) (v_idx_181 Int) (v_idx_182 Int) (v_idx_183 Int) (v_idx_177 Int) (v_idx_178 Int) (v_idx_175 Int) (v_idx_176 Int)) (exists ((v_b_134_2 Int) (v_v_1148_2 Int) (v_b_137_2 Int) (v_b_138_2 Int) (v_v_1144_2 Int) (v_b_135_2 Int) (v_v_1145_2 Int) (v_v_1146_2 Int) (v_b_136_2 Int) (v_v_1150_2 Int) (v_b_139_2 Int) (v_v_1152_2 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p1 2)) (.cse13 (+ v_b_134_2 2)) (.cse12 (+ v_b_135_2 1)) (.cse11 (+ v_b_136_2 1)) (.cse10 (+ v_b_134_2 1)) (.cse15 (+ v_b_138_2 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 3)) (.cse14 (+ c_ULTIMATE.start_main_p1 1))) (and (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_2) (<= .cse8 v_b_135_2) (<= (+ v_b_136_2 2) v_b_139_2) (<= .cse9 v_b_137_2) (or (< v_idx_183 v_b_139_2) (= (select |c_#memory_int| v_idx_183) v_v_1152_2)) (<= .cse10 v_b_135_2) (or (<= v_b_139_2 v_idx_182) (= 0 (select |c_#memory_int| v_idx_182)) (< v_idx_182 v_b_138_2)) (or (= (select |c_#memory_int| v_idx_178) 0) (< v_idx_178 v_b_134_2) (<= v_b_135_2 v_idx_178)) (<= 0 (* 2 v_v_1145_2)) (<= v_b_135_2 v_b_136_2) (<= v_b_137_2 .cse11) (<= .cse12 v_b_138_2) (<= (+ v_b_137_2 1) v_b_139_2) (<= (+ v_b_135_2 2) v_b_139_2) (<= (+ v_b_134_2 3) v_b_139_2) (<= .cse8 v_b_136_2) (<= v_b_135_2 .cse10) (<= .cse13 v_b_137_2) (or (= (select |c_#memory_int| v_idx_176) v_v_1145_2) (< v_idx_176 c_ULTIMATE.start_main_p1) (<= .cse14 v_idx_176)) (<= .cse13 v_b_138_2) (<= .cse12 v_b_137_2) (or (< v_idx_177 .cse14) (= (select |c_#memory_int| v_idx_177) v_v_1146_2) (<= v_b_134_2 v_idx_177)) (<= v_b_137_2 v_b_138_2) (or (< v_idx_181 v_b_137_2) (<= v_b_138_2 v_idx_181) (= (select |c_#memory_int| v_idx_181) v_v_1150_2)) (<= .cse11 v_b_137_2) (or (= (select |c_#memory_int| v_idx_179) v_v_1148_2) (<= v_b_136_2 v_idx_179) (< v_idx_179 v_b_135_2)) (<= .cse11 v_b_138_2) (<= v_b_139_2 .cse15) (or (<= c_ULTIMATE.start_main_p1 v_idx_175) (= (select |c_#memory_int| v_idx_175) v_v_1144_2)) (<= .cse10 v_b_136_2) (<= .cse15 v_b_139_2) (or (< v_idx_180 v_b_136_2) (<= v_b_137_2 v_idx_180) (= (select |c_#memory_int| v_idx_180) 0)) (<= .cse9 v_b_138_2) (<= .cse14 v_b_134_2) (<= 0 v_v_1145_2)))))) is different from false [2019-01-11 11:43:25,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:43:25,970 INFO L93 Difference]: Finished difference Result 14 states and 29 transitions. [2019-01-11 11:43:25,970 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:43:25,971 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:43:25,971 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:43:25,971 INFO L225 Difference]: With dead ends: 14 [2019-01-11 11:43:25,971 INFO L226 Difference]: Without dead ends: 13 [2019-01-11 11:43:25,972 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 8.3s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:43:25,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2019-01-11 11:43:25,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 12. [2019-01-11 11:43:25,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2019-01-11 11:43:25,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 23 transitions. [2019-01-11 11:43:25,978 INFO L78 Accepts]: Start accepts. Automaton has 12 states and 23 transitions. Word has length 3 [2019-01-11 11:43:25,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:43:25,978 INFO L480 AbstractCegarLoop]: Abstraction has 12 states and 23 transitions. [2019-01-11 11:43:25,978 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:43:25,978 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 23 transitions. [2019-01-11 11:43:25,978 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:43:25,979 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:43:25,979 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:43:25,979 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:43:25,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:43:25,979 INFO L82 PathProgramCache]: Analyzing trace with hash 30120, now seen corresponding path program 1 times [2019-01-11 11:43:25,980 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:43:25,980 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:43:25,981 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:43:25,981 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:43:25,981 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:43:25,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:43:26,069 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:43:26,069 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:43:26,069 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:43:26,069 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:43:26,069 INFO L207 CegarAbsIntRunner]: [0], [10], [19] [2019-01-11 11:43:26,071 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:43:26,071 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:43:31,923 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:43:31,924 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:43:31,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:43:31,924 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:43:32,206 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 68.75% of their original sizes. [2019-01-11 11:43:32,206 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:43:34,680 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_278 Int) (v_idx_279 Int) (v_idx_272 Int) (v_idx_273 Int) (v_idx_271 Int) (v_idx_276 Int) (v_idx_277 Int) (v_idx_274 Int) (v_idx_275 Int)) (exists ((v_v_1470_3 Int) (v_v_1471_3 Int) (v_v_1473_3 Int) (v_v_1475_3 Int) (v_b_127_3 Int) (v_v_1467_3 Int) (v_b_124_3 Int) (v_b_126_3 Int) (v_b_125_3 Int) (v_v_1469_3 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p1 3)) (.cse4 (+ v_b_126_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse3 (+ v_b_124_3 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 2))) (and (<= .cse0 v_b_126_3) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_127_3) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_127_3) (or (< v_idx_274 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_274) v_v_1470_3) (<= .cse1 v_idx_274)) (or (= 0 (select |c_#memory_int| v_idx_276)) (< v_idx_276 v_b_124_3) (<= v_b_125_3 v_idx_276)) (<= v_b_125_3 v_b_126_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_271) (= (select |c_#memory_int| v_idx_271) v_v_1467_3)) (or (<= v_b_126_3 v_idx_277) (= (select |c_#memory_int| v_idx_277) v_v_1473_3) (< v_idx_277 v_b_125_3)) (<= .cse2 v_b_126_3) (<= .cse3 v_b_126_3) (<= (+ v_b_125_3 1) v_b_127_3) (<= .cse3 v_b_125_3) (<= .cse4 v_b_127_3) (or (= (select |c_#memory_int| v_idx_275) v_v_1471_3) (< v_idx_275 .cse1) (<= v_b_124_3 v_idx_275)) (or (<= v_b_127_3 v_idx_278) (= 0 (select |c_#memory_int| v_idx_278)) (< v_idx_278 v_b_126_3)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_124_3) (or (< v_idx_273 .cse5) (<= c_ULTIMATE.start_main_p2 v_idx_273) (= (select |c_#memory_int| v_idx_273) v_v_1469_3)) (<= (* 2 v_v_1470_3) 0) (<= .cse0 v_b_125_3) (<= v_v_1470_3 0) (<= v_b_127_3 .cse4) (<= (+ v_b_124_3 2) v_b_127_3) (or (< v_idx_279 v_b_127_3) (= (select |c_#memory_int| v_idx_279) v_v_1475_3)) (<= .cse5 c_ULTIMATE.start_main_p2) (<= .cse1 v_b_124_3) (<= v_b_125_3 .cse3) (or (= (select |c_#memory_int| v_idx_272) 0) (<= .cse5 v_idx_272) (< v_idx_272 c_ULTIMATE.start_main_p1)) (<= .cse2 v_b_125_3))))) is different from false [2019-01-11 11:43:37,302 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_280 Int) (v_idx_283 Int) (v_idx_284 Int) (v_idx_281 Int) (v_idx_282 Int) (v_idx_287 Int) (v_idx_288 Int) (v_idx_285 Int) (v_idx_286 Int)) (exists ((v_v_1470_3 Int) (v_b_122_3 Int) (v_v_1471_3 Int) (v_v_1473_3 Int) (v_v_1475_3 Int) (v_b_127_3 Int) (v_v_1467_3 Int) (v_b_124_3 Int) (v_b_123_3 Int) (v_b_126_3 Int) (v_b_125_3 Int) (v_v_1469_3 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 2)) (.cse5 (+ v_b_122_3 2)) (.cse0 (+ c_ULTIMATE.start_main_p1 3)) (.cse7 (+ v_b_126_3 1)) (.cse3 (+ v_b_123_3 1)) (.cse6 (+ v_b_124_3 1)) (.cse1 (+ v_b_122_3 1))) (and (<= .cse0 v_b_126_3) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_127_3) (<= (+ v_b_122_3 3) v_b_127_3) (or (= 0 (select |c_#memory_int| v_idx_287)) (< v_idx_287 v_b_126_3) (<= v_b_127_3 v_idx_287)) (<= v_b_125_3 v_b_126_3) (<= .cse1 v_b_124_3) (or (= (select |c_#memory_int| v_idx_288) v_v_1475_3) (< v_idx_288 v_b_127_3)) (<= v_b_123_3 .cse1) (or (<= c_ULTIMATE.start_main_p1 v_idx_280) (= (select |c_#memory_int| v_idx_280) v_v_1467_3)) (<= .cse2 v_b_122_3) (<= .cse3 v_b_125_3) (or (< v_idx_283 v_b_122_3) (= (select |c_#memory_int| v_idx_283) v_v_1470_3) (<= v_b_123_3 v_idx_283)) (or (= (select |c_#memory_int| v_idx_282) v_v_1469_3) (< v_idx_282 .cse2) (<= v_b_122_3 v_idx_282)) (<= .cse4 v_b_123_3) (<= .cse5 v_b_126_3) (or (<= .cse2 v_idx_281) (< v_idx_281 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_281))) (or (< v_idx_286 v_b_125_3) (= (select |c_#memory_int| v_idx_286) v_v_1473_3) (<= v_b_126_3 v_idx_286)) (or (<= v_b_125_3 v_idx_285) (= 0 (select |c_#memory_int| v_idx_285)) (< v_idx_285 v_b_124_3)) (<= .cse6 v_b_126_3) (<= (+ v_b_125_3 1) v_b_127_3) (<= .cse6 v_b_125_3) (<= .cse7 v_b_127_3) (<= .cse4 v_b_124_3) (<= (+ v_b_123_3 2) v_b_127_3) (<= (* 2 v_v_1470_3) 0) (<= v_b_123_3 v_b_124_3) (<= .cse5 v_b_125_3) (<= .cse0 v_b_125_3) (<= v_v_1470_3 0) (or (= (select |c_#memory_int| v_idx_284) v_v_1471_3) (<= v_b_124_3 v_idx_284) (< v_idx_284 v_b_123_3)) (<= v_b_127_3 .cse7) (<= (+ v_b_124_3 2) v_b_127_3) (<= .cse3 v_b_126_3) (<= v_b_125_3 .cse6) (<= .cse1 v_b_123_3))))) is different from false [2019-01-11 11:43:37,448 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:43:37,448 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:43:37,448 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:43:37,448 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:43:37,449 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:43:37,449 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:43:37,449 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:43:37,449 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:43:37,449 INFO L87 Difference]: Start difference. First operand 12 states and 23 transitions. Second operand 4 states. [2019-01-11 11:43:39,998 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_280 Int) (v_idx_283 Int) (v_idx_284 Int) (v_idx_281 Int) (v_idx_282 Int) (v_idx_287 Int) (v_idx_288 Int) (v_idx_285 Int) (v_idx_286 Int)) (exists ((v_v_1470_3 Int) (v_b_122_3 Int) (v_v_1471_3 Int) (v_v_1473_3 Int) (v_v_1475_3 Int) (v_b_127_3 Int) (v_v_1467_3 Int) (v_b_124_3 Int) (v_b_123_3 Int) (v_b_126_3 Int) (v_b_125_3 Int) (v_v_1469_3 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 2)) (.cse5 (+ v_b_122_3 2)) (.cse0 (+ c_ULTIMATE.start_main_p1 3)) (.cse7 (+ v_b_126_3 1)) (.cse3 (+ v_b_123_3 1)) (.cse6 (+ v_b_124_3 1)) (.cse1 (+ v_b_122_3 1))) (and (<= .cse0 v_b_126_3) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_127_3) (<= (+ v_b_122_3 3) v_b_127_3) (or (= 0 (select |c_#memory_int| v_idx_287)) (< v_idx_287 v_b_126_3) (<= v_b_127_3 v_idx_287)) (<= v_b_125_3 v_b_126_3) (<= .cse1 v_b_124_3) (or (= (select |c_#memory_int| v_idx_288) v_v_1475_3) (< v_idx_288 v_b_127_3)) (<= v_b_123_3 .cse1) (or (<= c_ULTIMATE.start_main_p1 v_idx_280) (= (select |c_#memory_int| v_idx_280) v_v_1467_3)) (<= .cse2 v_b_122_3) (<= .cse3 v_b_125_3) (or (< v_idx_283 v_b_122_3) (= (select |c_#memory_int| v_idx_283) v_v_1470_3) (<= v_b_123_3 v_idx_283)) (or (= (select |c_#memory_int| v_idx_282) v_v_1469_3) (< v_idx_282 .cse2) (<= v_b_122_3 v_idx_282)) (<= .cse4 v_b_123_3) (<= .cse5 v_b_126_3) (or (<= .cse2 v_idx_281) (< v_idx_281 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_281))) (or (< v_idx_286 v_b_125_3) (= (select |c_#memory_int| v_idx_286) v_v_1473_3) (<= v_b_126_3 v_idx_286)) (or (<= v_b_125_3 v_idx_285) (= 0 (select |c_#memory_int| v_idx_285)) (< v_idx_285 v_b_124_3)) (<= .cse6 v_b_126_3) (<= (+ v_b_125_3 1) v_b_127_3) (<= .cse6 v_b_125_3) (<= .cse7 v_b_127_3) (<= .cse4 v_b_124_3) (<= (+ v_b_123_3 2) v_b_127_3) (<= (* 2 v_v_1470_3) 0) (<= v_b_123_3 v_b_124_3) (<= .cse5 v_b_125_3) (<= .cse0 v_b_125_3) (<= v_v_1470_3 0) (or (= (select |c_#memory_int| v_idx_284) v_v_1471_3) (<= v_b_124_3 v_idx_284) (< v_idx_284 v_b_123_3)) (<= v_b_127_3 .cse7) (<= (+ v_b_124_3 2) v_b_127_3) (<= .cse3 v_b_126_3) (<= v_b_125_3 .cse6) (<= .cse1 v_b_123_3))))) (forall ((v_idx_278 Int) (v_idx_279 Int) (v_idx_272 Int) (v_idx_273 Int) (v_idx_271 Int) (v_idx_276 Int) (v_idx_277 Int) (v_idx_274 Int) (v_idx_275 Int)) (exists ((v_v_1470_3 Int) (v_v_1471_3 Int) (v_v_1473_3 Int) (v_v_1475_3 Int) (v_b_127_3 Int) (v_v_1467_3 Int) (v_b_124_3 Int) (v_b_126_3 Int) (v_b_125_3 Int) (v_v_1469_3 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p1 3)) (.cse12 (+ v_b_126_3 1)) (.cse9 (+ c_ULTIMATE.start_main_p2 1)) (.cse11 (+ v_b_124_3 1)) (.cse13 (+ c_ULTIMATE.start_main_p1 1)) (.cse10 (+ c_ULTIMATE.start_main_p2 2))) (and (<= .cse8 v_b_126_3) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_127_3) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_127_3) (or (< v_idx_274 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_274) v_v_1470_3) (<= .cse9 v_idx_274)) (or (= 0 (select |c_#memory_int| v_idx_276)) (< v_idx_276 v_b_124_3) (<= v_b_125_3 v_idx_276)) (<= v_b_125_3 v_b_126_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_271) (= (select |c_#memory_int| v_idx_271) v_v_1467_3)) (or (<= v_b_126_3 v_idx_277) (= (select |c_#memory_int| v_idx_277) v_v_1473_3) (< v_idx_277 v_b_125_3)) (<= .cse10 v_b_126_3) (<= .cse11 v_b_126_3) (<= (+ v_b_125_3 1) v_b_127_3) (<= .cse11 v_b_125_3) (<= .cse12 v_b_127_3) (or (= (select |c_#memory_int| v_idx_275) v_v_1471_3) (< v_idx_275 .cse9) (<= v_b_124_3 v_idx_275)) (or (<= v_b_127_3 v_idx_278) (= 0 (select |c_#memory_int| v_idx_278)) (< v_idx_278 v_b_126_3)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_124_3) (or (< v_idx_273 .cse13) (<= c_ULTIMATE.start_main_p2 v_idx_273) (= (select |c_#memory_int| v_idx_273) v_v_1469_3)) (<= (* 2 v_v_1470_3) 0) (<= .cse8 v_b_125_3) (<= v_v_1470_3 0) (<= v_b_127_3 .cse12) (<= (+ v_b_124_3 2) v_b_127_3) (or (< v_idx_279 v_b_127_3) (= (select |c_#memory_int| v_idx_279) v_v_1475_3)) (<= .cse13 c_ULTIMATE.start_main_p2) (<= .cse9 v_b_124_3) (<= v_b_125_3 .cse11) (or (= (select |c_#memory_int| v_idx_272) 0) (<= .cse13 v_idx_272) (< v_idx_272 c_ULTIMATE.start_main_p1)) (<= .cse10 v_b_125_3)))))) is different from false [2019-01-11 11:43:53,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:43:53,976 INFO L93 Difference]: Finished difference Result 14 states and 29 transitions. [2019-01-11 11:43:53,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:43:53,977 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:43:53,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:43:53,978 INFO L225 Difference]: With dead ends: 14 [2019-01-11 11:43:53,978 INFO L226 Difference]: Without dead ends: 13 [2019-01-11 11:43:53,978 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.8s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:43:53,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2019-01-11 11:43:53,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 12. [2019-01-11 11:43:53,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2019-01-11 11:43:53,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 23 transitions. [2019-01-11 11:43:53,987 INFO L78 Accepts]: Start accepts. Automaton has 12 states and 23 transitions. Word has length 3 [2019-01-11 11:43:53,987 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:43:53,987 INFO L480 AbstractCegarLoop]: Abstraction has 12 states and 23 transitions. [2019-01-11 11:43:53,987 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:43:53,987 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 23 transitions. [2019-01-11 11:43:53,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:43:53,988 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:43:53,988 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:43:53,988 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:43:53,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:43:53,989 INFO L82 PathProgramCache]: Analyzing trace with hash 30244, now seen corresponding path program 1 times [2019-01-11 11:43:53,989 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:43:53,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:43:53,990 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:43:53,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:43:53,990 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:43:53,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:43:54,311 WARN L181 SmtUtils]: Spent 275.00 ms on a formula simplification. DAG size of input: 21 DAG size of output: 13 [2019-01-11 11:43:54,319 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:43:54,319 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:43:54,319 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:43:54,320 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:43:54,320 INFO L207 CegarAbsIntRunner]: [0], [14], [19] [2019-01-11 11:43:54,322 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:43:54,322 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:43:59,196 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:43:59,197 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:43:59,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:43:59,197 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:43:59,580 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 68.75% of their original sizes. [2019-01-11 11:43:59,580 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:44:02,016 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_368 Int) (v_idx_369 Int) (v_idx_367 Int) (v_idx_371 Int) (v_idx_372 Int) (v_idx_370 Int) (v_idx_375 Int) (v_idx_373 Int) (v_idx_374 Int)) (exists ((v_v_1149_4 Int) (v_v_1146_4 Int) (v_v_1148_4 Int) (v_b_135_4 Int) (v_v_1152_4 Int) (v_b_134_4 Int) (v_v_1144_4 Int) (v_b_139_4 Int) (v_v_1150_4 Int) (v_b_138_4 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_138_4 1)) (.cse4 (+ v_b_134_4 1)) (.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2))) (and (or (<= c_ULTIMATE.start_main_p3 v_idx_371) (< v_idx_371 v_b_135_4) (= (select |c_#memory_int| v_idx_371) v_v_1148_4)) (<= (+ c_ULTIMATE.start_main_p3 2) v_b_139_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_138_4) (or (= (select |c_#memory_int| v_idx_372) v_v_1149_4) (< v_idx_372 c_ULTIMATE.start_main_p3) (<= .cse0 v_idx_372)) (<= v_b_135_4 c_ULTIMATE.start_main_p3) (<= .cse1 v_b_139_4) (or (<= v_b_139_4 v_idx_374) (= 0 (select |c_#memory_int| v_idx_374)) (< v_idx_374 v_b_138_4)) (<= (+ v_b_134_4 3) v_b_139_4) (<= 0 v_v_1149_4) (<= .cse2 v_b_134_4) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_4) (or (= (select |c_#memory_int| v_idx_373) v_v_1150_4) (< v_idx_373 .cse0) (<= v_b_138_4 v_idx_373)) (<= .cse3 c_ULTIMATE.start_main_p3) (<= .cse4 v_b_135_4) (<= v_b_135_4 .cse4) (or (<= v_b_135_4 v_idx_370) (< v_idx_370 v_b_134_4) (= 0 (select |c_#memory_int| v_idx_370))) (or (= (select |c_#memory_int| v_idx_369) v_v_1146_4) (< v_idx_369 .cse2) (<= v_b_134_4 v_idx_369)) (or (= 0 (select |c_#memory_int| v_idx_368)) (<= .cse2 v_idx_368) (< v_idx_368 c_ULTIMATE.start_main_p1)) (<= v_b_139_4 .cse1) (<= (+ v_b_135_4 2) v_b_139_4) (<= 0 (* 2 v_v_1149_4)) (<= (+ v_b_134_4 2) v_b_138_4) (<= .cse4 c_ULTIMATE.start_main_p3) (<= (+ v_b_135_4 1) v_b_138_4) (or (= (select |c_#memory_int| v_idx_375) v_v_1152_4) (< v_idx_375 v_b_139_4)) (or (<= c_ULTIMATE.start_main_p1 v_idx_367) (= (select |c_#memory_int| v_idx_367) v_v_1144_4)) (<= .cse0 v_b_138_4) (<= .cse3 v_b_135_4))))) is different from false [2019-01-11 11:44:04,611 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_379 Int) (v_idx_377 Int) (v_idx_378 Int) (v_idx_382 Int) (v_idx_383 Int) (v_idx_380 Int) (v_idx_381 Int) (v_idx_376 Int) (v_idx_384 Int)) (exists ((v_v_1149_4 Int) (v_v_1146_4 Int) (v_v_1148_4 Int) (v_b_135_4 Int) (v_v_1152_4 Int) (v_b_136_4 Int) (v_b_134_4 Int) (v_v_1144_4 Int) (v_b_139_4 Int) (v_b_137_4 Int) (v_v_1150_4 Int) (v_b_138_4 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse4 (+ v_b_134_4 1)) (.cse3 (+ v_b_138_4 1)) (.cse2 (+ v_b_134_4 2)) (.cse6 (+ v_b_136_4 1)) (.cse7 (+ v_b_135_4 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 2))) (and (or (<= v_b_134_4 v_idx_378) (< v_idx_378 .cse0) (= (select |c_#memory_int| v_idx_378) v_v_1146_4)) (or (<= .cse0 v_idx_377) (< v_idx_377 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_377))) (<= (+ v_b_137_4 1) v_b_139_4) (<= .cse1 v_b_138_4) (<= .cse2 v_b_137_4) (or (< v_idx_379 v_b_134_4) (<= v_b_135_4 v_idx_379) (= 0 (select |c_#memory_int| v_idx_379))) (<= .cse1 v_b_137_4) (or (< v_idx_380 v_b_135_4) (= (select |c_#memory_int| v_idx_380) v_v_1148_4) (<= v_b_136_4 v_idx_380)) (or (= 0 (select |c_#memory_int| v_idx_383)) (< v_idx_383 v_b_138_4) (<= v_b_139_4 v_idx_383)) (<= .cse3 v_b_139_4) (<= (+ v_b_134_4 3) v_b_139_4) (<= 0 v_v_1149_4) (or (= (select |c_#memory_int| v_idx_384) v_v_1152_4) (< v_idx_384 v_b_139_4)) (<= .cse0 v_b_134_4) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_4) (<= v_b_135_4 v_b_136_4) (or (= (select |c_#memory_int| v_idx_381) v_v_1149_4) (< v_idx_381 v_b_136_4) (<= v_b_137_4 v_idx_381)) (<= .cse4 v_b_135_4) (<= v_b_135_4 .cse4) (<= .cse4 v_b_136_4) (<= .cse5 v_b_136_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_376) (= (select |c_#memory_int| v_idx_376) v_v_1144_4)) (<= v_b_137_4 .cse6) (<= .cse6 v_b_137_4) (<= v_b_139_4 .cse3) (<= (+ v_b_135_4 2) v_b_139_4) (<= 0 (* 2 v_v_1149_4)) (<= (+ v_b_136_4 2) v_b_139_4) (<= v_b_137_4 v_b_138_4) (<= .cse7 v_b_137_4) (<= .cse2 v_b_138_4) (<= .cse6 v_b_138_4) (<= .cse7 v_b_138_4) (or (= (select |c_#memory_int| v_idx_382) v_v_1150_4) (<= v_b_138_4 v_idx_382) (< v_idx_382 v_b_137_4)) (<= .cse5 v_b_135_4))))) is different from false [2019-01-11 11:44:04,759 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:44:04,759 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:44:04,760 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:44:04,760 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:44:04,760 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:44:04,760 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:44:04,760 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:44:04,761 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:44:04,761 INFO L87 Difference]: Start difference. First operand 12 states and 23 transitions. Second operand 4 states. [2019-01-11 11:44:07,309 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_379 Int) (v_idx_377 Int) (v_idx_378 Int) (v_idx_382 Int) (v_idx_383 Int) (v_idx_380 Int) (v_idx_381 Int) (v_idx_376 Int) (v_idx_384 Int)) (exists ((v_v_1149_4 Int) (v_v_1146_4 Int) (v_v_1148_4 Int) (v_b_135_4 Int) (v_v_1152_4 Int) (v_b_136_4 Int) (v_b_134_4 Int) (v_v_1144_4 Int) (v_b_139_4 Int) (v_b_137_4 Int) (v_v_1150_4 Int) (v_b_138_4 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse4 (+ v_b_134_4 1)) (.cse3 (+ v_b_138_4 1)) (.cse2 (+ v_b_134_4 2)) (.cse6 (+ v_b_136_4 1)) (.cse7 (+ v_b_135_4 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 2))) (and (or (<= v_b_134_4 v_idx_378) (< v_idx_378 .cse0) (= (select |c_#memory_int| v_idx_378) v_v_1146_4)) (or (<= .cse0 v_idx_377) (< v_idx_377 c_ULTIMATE.start_main_p1) (= 0 (select |c_#memory_int| v_idx_377))) (<= (+ v_b_137_4 1) v_b_139_4) (<= .cse1 v_b_138_4) (<= .cse2 v_b_137_4) (or (< v_idx_379 v_b_134_4) (<= v_b_135_4 v_idx_379) (= 0 (select |c_#memory_int| v_idx_379))) (<= .cse1 v_b_137_4) (or (< v_idx_380 v_b_135_4) (= (select |c_#memory_int| v_idx_380) v_v_1148_4) (<= v_b_136_4 v_idx_380)) (or (= 0 (select |c_#memory_int| v_idx_383)) (< v_idx_383 v_b_138_4) (<= v_b_139_4 v_idx_383)) (<= .cse3 v_b_139_4) (<= (+ v_b_134_4 3) v_b_139_4) (<= 0 v_v_1149_4) (or (= (select |c_#memory_int| v_idx_384) v_v_1152_4) (< v_idx_384 v_b_139_4)) (<= .cse0 v_b_134_4) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_4) (<= v_b_135_4 v_b_136_4) (or (= (select |c_#memory_int| v_idx_381) v_v_1149_4) (< v_idx_381 v_b_136_4) (<= v_b_137_4 v_idx_381)) (<= .cse4 v_b_135_4) (<= v_b_135_4 .cse4) (<= .cse4 v_b_136_4) (<= .cse5 v_b_136_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_376) (= (select |c_#memory_int| v_idx_376) v_v_1144_4)) (<= v_b_137_4 .cse6) (<= .cse6 v_b_137_4) (<= v_b_139_4 .cse3) (<= (+ v_b_135_4 2) v_b_139_4) (<= 0 (* 2 v_v_1149_4)) (<= (+ v_b_136_4 2) v_b_139_4) (<= v_b_137_4 v_b_138_4) (<= .cse7 v_b_137_4) (<= .cse2 v_b_138_4) (<= .cse6 v_b_138_4) (<= .cse7 v_b_138_4) (or (= (select |c_#memory_int| v_idx_382) v_v_1150_4) (<= v_b_138_4 v_idx_382) (< v_idx_382 v_b_137_4)) (<= .cse5 v_b_135_4))))) (forall ((v_idx_368 Int) (v_idx_369 Int) (v_idx_367 Int) (v_idx_371 Int) (v_idx_372 Int) (v_idx_370 Int) (v_idx_375 Int) (v_idx_373 Int) (v_idx_374 Int)) (exists ((v_v_1149_4 Int) (v_v_1146_4 Int) (v_v_1148_4 Int) (v_b_135_4 Int) (v_v_1152_4 Int) (v_b_134_4 Int) (v_v_1144_4 Int) (v_b_139_4 Int) (v_v_1150_4 Int) (v_b_138_4 Int)) (let ((.cse10 (+ c_ULTIMATE.start_main_p1 1)) (.cse9 (+ v_b_138_4 1)) (.cse12 (+ v_b_134_4 1)) (.cse8 (+ c_ULTIMATE.start_main_p3 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 2))) (and (or (<= c_ULTIMATE.start_main_p3 v_idx_371) (< v_idx_371 v_b_135_4) (= (select |c_#memory_int| v_idx_371) v_v_1148_4)) (<= (+ c_ULTIMATE.start_main_p3 2) v_b_139_4) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_138_4) (or (= (select |c_#memory_int| v_idx_372) v_v_1149_4) (< v_idx_372 c_ULTIMATE.start_main_p3) (<= .cse8 v_idx_372)) (<= v_b_135_4 c_ULTIMATE.start_main_p3) (<= .cse9 v_b_139_4) (or (<= v_b_139_4 v_idx_374) (= 0 (select |c_#memory_int| v_idx_374)) (< v_idx_374 v_b_138_4)) (<= (+ v_b_134_4 3) v_b_139_4) (<= 0 v_v_1149_4) (<= .cse10 v_b_134_4) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_139_4) (or (= (select |c_#memory_int| v_idx_373) v_v_1150_4) (< v_idx_373 .cse8) (<= v_b_138_4 v_idx_373)) (<= .cse11 c_ULTIMATE.start_main_p3) (<= .cse12 v_b_135_4) (<= v_b_135_4 .cse12) (or (<= v_b_135_4 v_idx_370) (< v_idx_370 v_b_134_4) (= 0 (select |c_#memory_int| v_idx_370))) (or (= (select |c_#memory_int| v_idx_369) v_v_1146_4) (< v_idx_369 .cse10) (<= v_b_134_4 v_idx_369)) (or (= 0 (select |c_#memory_int| v_idx_368)) (<= .cse10 v_idx_368) (< v_idx_368 c_ULTIMATE.start_main_p1)) (<= v_b_139_4 .cse9) (<= (+ v_b_135_4 2) v_b_139_4) (<= 0 (* 2 v_v_1149_4)) (<= (+ v_b_134_4 2) v_b_138_4) (<= .cse12 c_ULTIMATE.start_main_p3) (<= (+ v_b_135_4 1) v_b_138_4) (or (= (select |c_#memory_int| v_idx_375) v_v_1152_4) (< v_idx_375 v_b_139_4)) (or (<= c_ULTIMATE.start_main_p1 v_idx_367) (= (select |c_#memory_int| v_idx_367) v_v_1144_4)) (<= .cse8 v_b_138_4) (<= .cse11 v_b_135_4)))))) is different from false [2019-01-11 11:44:20,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:44:20,072 INFO L93 Difference]: Finished difference Result 14 states and 29 transitions. [2019-01-11 11:44:20,072 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:44:20,073 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:44:20,073 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:44:20,073 INFO L225 Difference]: With dead ends: 14 [2019-01-11 11:44:20,073 INFO L226 Difference]: Without dead ends: 13 [2019-01-11 11:44:20,074 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.7s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:44:20,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2019-01-11 11:44:20,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 12. [2019-01-11 11:44:20,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2019-01-11 11:44:20,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 23 transitions. [2019-01-11 11:44:20,083 INFO L78 Accepts]: Start accepts. Automaton has 12 states and 23 transitions. Word has length 3 [2019-01-11 11:44:20,083 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:44:20,084 INFO L480 AbstractCegarLoop]: Abstraction has 12 states and 23 transitions. [2019-01-11 11:44:20,084 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:44:20,084 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 23 transitions. [2019-01-11 11:44:20,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:44:20,084 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:44:20,084 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1] [2019-01-11 11:44:20,085 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:44:20,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:20,085 INFO L82 PathProgramCache]: Analyzing trace with hash 939412, now seen corresponding path program 2 times [2019-01-11 11:44:20,085 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:44:20,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:20,086 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:44:20,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:20,087 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:44:20,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:44:20,367 WARN L181 SmtUtils]: Spent 226.00 ms on a formula simplification. DAG size of input: 19 DAG size of output: 13 [2019-01-11 11:44:20,435 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-11 11:44:20,436 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:44:20,436 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:44:20,436 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:44:20,437 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:44:20,437 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:44:20,437 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:44:20,454 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-11 11:44:20,454 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-11 11:44:20,490 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-11 11:44:20,490 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:44:20,495 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:44:20,539 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 18 [2019-01-11 11:44:20,574 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:20,575 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 24 [2019-01-11 11:44:20,615 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:20,637 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:20,638 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 34 [2019-01-11 11:44:20,661 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:20,686 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:20,699 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:20,700 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 45 [2019-01-11 11:44:20,701 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2019-01-11 11:44:20,971 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:44:21,112 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:44:21,232 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:44:21,296 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:44:21,297 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:25, output treesize:30 [2019-01-11 11:44:21,336 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,337 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,338 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,339 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,340 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,341 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,343 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,344 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 45 [2019-01-11 11:44:21,346 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:44:21,528 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2019-01-11 11:44:21,530 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:40, output treesize:30 [2019-01-11 11:44:21,665 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,666 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,668 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,670 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,672 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,674 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,675 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,676 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,690 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:44:21,691 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 9 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 57 [2019-01-11 11:44:21,692 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:44:21,797 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2019-01-11 11:44:21,798 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 4 variables, input treesize:42, output treesize:30 [2019-01-11 11:44:21,853 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:44:21,854 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:44:21,880 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:44:21,901 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-11 11:44:21,901 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 3, 3] total 8 [2019-01-11 11:44:21,901 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-11 11:44:21,902 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-01-11 11:44:21,902 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-01-11 11:44:21,902 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=53, Unknown=0, NotChecked=0, Total=90 [2019-01-11 11:44:21,902 INFO L87 Difference]: Start difference. First operand 12 states and 23 transitions. Second operand 7 states. [2019-01-11 11:44:22,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:44:22,294 INFO L93 Difference]: Finished difference Result 37 states and 58 transitions. [2019-01-11 11:44:22,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-11 11:44:22,294 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 4 [2019-01-11 11:44:22,295 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:44:22,295 INFO L225 Difference]: With dead ends: 37 [2019-01-11 11:44:22,295 INFO L226 Difference]: Without dead ends: 33 [2019-01-11 11:44:22,296 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-01-11 11:44:22,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states. [2019-01-11 11:44:22,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 16. [2019-01-11 11:44:22,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2019-01-11 11:44:22,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 36 transitions. [2019-01-11 11:44:22,307 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 36 transitions. Word has length 4 [2019-01-11 11:44:22,307 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:44:22,307 INFO L480 AbstractCegarLoop]: Abstraction has 16 states and 36 transitions. [2019-01-11 11:44:22,307 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-01-11 11:44:22,307 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 36 transitions. [2019-01-11 11:44:22,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:44:22,308 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:44:22,308 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-11 11:44:22,308 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:44:22,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:22,309 INFO L82 PathProgramCache]: Analyzing trace with hash 939538, now seen corresponding path program 1 times [2019-01-11 11:44:22,309 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:44:22,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:22,310 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:44:22,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:22,310 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:44:22,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:44:22,394 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:44:22,394 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:44:22,394 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:44:22,395 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-11 11:44:22,395 INFO L207 CegarAbsIntRunner]: [0], [16], [20], [21] [2019-01-11 11:44:22,396 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:44:22,396 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:44:29,227 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:44:29,227 INFO L272 AbstractInterpreter]: Visited 4 different actions 16 times. Merged at 2 different actions 8 times. Widened at 1 different actions 2 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:44:29,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:29,228 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:44:29,584 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 62.5% of their original sizes. [2019-01-11 11:44:29,585 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:44:31,960 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_510 Int) (v_idx_504 Int) (v_idx_505 Int) (v_idx_502 Int) (v_idx_503 Int) (v_idx_508 Int) (v_idx_509 Int) (v_idx_506 Int) (v_idx_507 Int)) (exists ((v_b_142_5 Int) (v_v_1504_5 Int) (v_v_1496_5 Int) (v_v_1502_5 Int) (v_v_1503_5 Int) (v_b_143_5 Int) (v_v_1500_5 Int) (v_v_1498_5 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p4 1)) (.cse2 (+ c_ULTIMATE.start_main_p2 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ v_b_142_5 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 3)) (.cse4 (+ c_ULTIMATE.start_main_p2 2))) (and (<= .cse0 v_b_143_5) (or (< v_idx_504 .cse1) (= (select |c_#memory_int| v_idx_504) v_v_1498_5) (<= c_ULTIMATE.start_main_p2 v_idx_504)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_142_5) (<= .cse2 v_b_142_5) (<= v_v_1503_5 0) (or (= (select |c_#memory_int| v_idx_509) v_v_1503_5) (< v_idx_509 c_ULTIMATE.start_main_p4) (<= .cse3 v_idx_509)) (<= v_b_143_5 c_ULTIMATE.start_main_p4) (or (= (select |c_#memory_int| v_idx_502) v_v_1496_5) (<= c_ULTIMATE.start_main_p1 v_idx_502)) (or (< v_idx_510 .cse3) (= (select |c_#memory_int| v_idx_510) v_v_1504_5)) (<= .cse4 c_ULTIMATE.start_main_p4) (or (<= .cse1 v_idx_503) (= 0 (select |c_#memory_int| v_idx_503)) (< v_idx_503 c_ULTIMATE.start_main_p1)) (or (< v_idx_506 .cse2) (<= v_b_142_5 v_idx_506) (= (select |c_#memory_int| v_idx_506) v_v_1500_5)) (<= (* 2 v_v_1503_5) 0) (or (<= .cse2 v_idx_505) (= 0 (select |c_#memory_int| v_idx_505)) (< v_idx_505 c_ULTIMATE.start_main_p2)) (<= .cse5 v_b_143_5) (<= .cse0 c_ULTIMATE.start_main_p4) (or (< v_idx_508 v_b_143_5) (<= c_ULTIMATE.start_main_p4 v_idx_508) (= (select |c_#memory_int| v_idx_508) v_v_1502_5)) (or (< v_idx_507 v_b_142_5) (= 0 (select |c_#memory_int| v_idx_507)) (<= v_b_143_5 v_idx_507)) (<= .cse1 c_ULTIMATE.start_main_p2) (<= v_b_143_5 .cse0) (<= .cse5 c_ULTIMATE.start_main_p4) (<= .cse4 v_b_143_5))))) is different from false [2019-01-11 11:44:34,378 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_511 Int) (v_idx_512 Int) (v_idx_515 Int) (v_idx_516 Int) (v_idx_513 Int) (v_idx_514 Int) (v_idx_519 Int) (v_idx_517 Int) (v_idx_518 Int)) (exists ((v_b_142_5 Int) (v_v_1504_5 Int) (v_b_145_5 Int) (v_v_1502_5 Int) (v_v_1496_5 Int) (v_v_1503_5 Int) (v_b_143_5 Int) (v_v_1500_5 Int) (v_b_144_5 Int) (v_v_1498_5 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 3)) (.cse1 (+ c_ULTIMATE.start_main_p2 2)) (.cse2 (+ v_b_144_5 1)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse4 (+ v_b_142_5 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_514 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_514)) (<= .cse0 v_idx_514)) (or (< v_idx_518 v_b_144_5) (= (select |c_#memory_int| v_idx_518) v_v_1503_5) (<= v_b_145_5 v_idx_518)) (<= .cse1 v_b_144_5) (<= (* 2 v_v_1503_5) 0) (<= v_b_145_5 .cse2) (or (< v_idx_519 v_b_145_5) (= (select |c_#memory_int| v_idx_519) v_v_1504_5)) (<= (+ v_b_142_5 2) v_b_145_5) (<= .cse3 v_b_144_5) (<= .cse3 v_b_143_5) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_145_5) (<= v_b_143_5 .cse4) (<= v_b_143_5 v_b_144_5) (<= .cse1 v_b_143_5) (<= .cse4 v_b_143_5) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_142_5) (<= .cse0 v_b_142_5) (<= v_v_1503_5 0) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_145_5) (<= .cse2 v_b_145_5) (or (< v_idx_517 v_b_143_5) (= (select |c_#memory_int| v_idx_517) v_v_1502_5) (<= v_b_144_5 v_idx_517)) (or (= (select |c_#memory_int| v_idx_515) v_v_1500_5) (< v_idx_515 .cse0) (<= v_b_142_5 v_idx_515)) (or (= (select |c_#memory_int| v_idx_513) v_v_1498_5) (<= c_ULTIMATE.start_main_p2 v_idx_513) (< v_idx_513 .cse5)) (<= .cse4 v_b_144_5) (or (<= c_ULTIMATE.start_main_p1 v_idx_511) (= (select |c_#memory_int| v_idx_511) v_v_1496_5)) (or (<= .cse5 v_idx_512) (< v_idx_512 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_512) 0)) (or (< v_idx_516 v_b_142_5) (= (select |c_#memory_int| v_idx_516) 0) (<= v_b_143_5 v_idx_516)) (<= .cse5 c_ULTIMATE.start_main_p2) (<= (+ v_b_143_5 1) v_b_145_5))))) is different from false [2019-01-11 11:44:36,777 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_522 Int) (v_idx_523 Int) (v_idx_520 Int) (v_idx_521 Int) (v_idx_526 Int) (v_idx_527 Int) (v_idx_524 Int) (v_idx_525 Int) (v_idx_528 Int)) (exists ((v_b_160_5 Int) (v_b_142_5 Int) (v_v_1504_5 Int) (v_v_1502_5 Int) (v_b_145_5 Int) (v_v_1496_5 Int) (v_v_1503_5 Int) (v_v_1500_5 Int) (v_b_143_5 Int) (v_v_1498_5 Int) (v_b_144_5 Int) (v_b_139_5 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p2 2)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_160_5 1)) (.cse4 (+ v_b_144_5 1)) (.cse6 (+ v_b_139_5 2)) (.cse3 (+ v_b_160_5 3)) (.cse5 (+ v_b_142_5 1))) (and (<= .cse0 c_ULTIMATE.start_main_p2) (<= .cse0 v_b_139_5) (<= (+ v_b_160_5 2) v_b_142_5) (or (<= v_b_142_5 v_idx_524) (= (select |c_#memory_int| v_idx_524) v_v_1500_5) (< v_idx_524 .cse1)) (or (< v_idx_522 v_b_139_5) (<= c_ULTIMATE.start_main_p2 v_idx_522) (= (select |c_#memory_int| v_idx_522) v_v_1498_5)) (or (<= v_b_144_5 v_idx_526) (= (select |c_#memory_int| v_idx_526) v_v_1502_5) (< v_idx_526 v_b_143_5)) (<= .cse2 v_b_144_5) (<= (+ v_b_160_5 4) v_b_145_5) (<= (* 2 v_v_1503_5) 0) (<= .cse3 v_b_144_5) (<= v_b_145_5 .cse4) (<= (+ v_b_142_5 2) v_b_145_5) (or (< v_idx_521 v_b_160_5) (<= v_b_139_5 v_idx_521) (= (select |c_#memory_int| v_idx_521) 0)) (or (<= v_b_143_5 v_idx_525) (= (select |c_#memory_int| v_idx_525) 0) (< v_idx_525 v_b_142_5)) (or (<= .cse1 v_idx_523) (< v_idx_523 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_523) 0)) (<= v_b_143_5 .cse5) (<= v_b_143_5 v_b_144_5) (<= .cse2 v_b_143_5) (<= .cse5 v_b_143_5) (<= (+ v_b_139_5 3) v_b_145_5) (<= .cse1 v_b_142_5) (<= v_v_1503_5 0) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_145_5) (or (= (select |c_#memory_int| v_idx_520) v_v_1496_5) (<= v_b_160_5 v_idx_520)) (<= .cse6 v_b_144_5) (<= v_b_139_5 .cse0) (<= .cse4 v_b_145_5) (<= .cse6 v_b_143_5) (<= v_b_139_5 c_ULTIMATE.start_main_p2) (<= .cse3 v_b_143_5) (or (< v_idx_528 v_b_145_5) (= (select |c_#memory_int| v_idx_528) v_v_1504_5)) (or (<= v_b_145_5 v_idx_527) (< v_idx_527 v_b_144_5) (= (select |c_#memory_int| v_idx_527) v_v_1503_5)) (<= .cse5 v_b_144_5) (<= (+ v_b_139_5 1) v_b_142_5) (<= (+ v_b_143_5 1) v_b_145_5))))) is different from false [2019-01-11 11:44:36,863 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-11 11:44:36,863 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:44:36,863 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:44:36,863 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [2] total 5 [2019-01-11 11:44:36,863 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:44:36,864 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-11 11:44:36,864 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-11 11:44:36,864 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:44:36,864 INFO L87 Difference]: Start difference. First operand 16 states and 36 transitions. Second operand 5 states. [2019-01-11 11:44:39,558 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_522 Int) (v_idx_523 Int) (v_idx_520 Int) (v_idx_521 Int) (v_idx_526 Int) (v_idx_527 Int) (v_idx_524 Int) (v_idx_525 Int) (v_idx_528 Int)) (exists ((v_b_160_5 Int) (v_b_142_5 Int) (v_v_1504_5 Int) (v_v_1502_5 Int) (v_b_145_5 Int) (v_v_1496_5 Int) (v_v_1503_5 Int) (v_v_1500_5 Int) (v_b_143_5 Int) (v_v_1498_5 Int) (v_b_144_5 Int) (v_b_139_5 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p2 2)) (.cse1 (+ c_ULTIMATE.start_main_p2 1)) (.cse0 (+ v_b_160_5 1)) (.cse4 (+ v_b_144_5 1)) (.cse6 (+ v_b_139_5 2)) (.cse3 (+ v_b_160_5 3)) (.cse5 (+ v_b_142_5 1))) (and (<= .cse0 c_ULTIMATE.start_main_p2) (<= .cse0 v_b_139_5) (<= (+ v_b_160_5 2) v_b_142_5) (or (<= v_b_142_5 v_idx_524) (= (select |c_#memory_int| v_idx_524) v_v_1500_5) (< v_idx_524 .cse1)) (or (< v_idx_522 v_b_139_5) (<= c_ULTIMATE.start_main_p2 v_idx_522) (= (select |c_#memory_int| v_idx_522) v_v_1498_5)) (or (<= v_b_144_5 v_idx_526) (= (select |c_#memory_int| v_idx_526) v_v_1502_5) (< v_idx_526 v_b_143_5)) (<= .cse2 v_b_144_5) (<= (+ v_b_160_5 4) v_b_145_5) (<= (* 2 v_v_1503_5) 0) (<= .cse3 v_b_144_5) (<= v_b_145_5 .cse4) (<= (+ v_b_142_5 2) v_b_145_5) (or (< v_idx_521 v_b_160_5) (<= v_b_139_5 v_idx_521) (= (select |c_#memory_int| v_idx_521) 0)) (or (<= v_b_143_5 v_idx_525) (= (select |c_#memory_int| v_idx_525) 0) (< v_idx_525 v_b_142_5)) (or (<= .cse1 v_idx_523) (< v_idx_523 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_523) 0)) (<= v_b_143_5 .cse5) (<= v_b_143_5 v_b_144_5) (<= .cse2 v_b_143_5) (<= .cse5 v_b_143_5) (<= (+ v_b_139_5 3) v_b_145_5) (<= .cse1 v_b_142_5) (<= v_v_1503_5 0) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_145_5) (or (= (select |c_#memory_int| v_idx_520) v_v_1496_5) (<= v_b_160_5 v_idx_520)) (<= .cse6 v_b_144_5) (<= v_b_139_5 .cse0) (<= .cse4 v_b_145_5) (<= .cse6 v_b_143_5) (<= v_b_139_5 c_ULTIMATE.start_main_p2) (<= .cse3 v_b_143_5) (or (< v_idx_528 v_b_145_5) (= (select |c_#memory_int| v_idx_528) v_v_1504_5)) (or (<= v_b_145_5 v_idx_527) (< v_idx_527 v_b_144_5) (= (select |c_#memory_int| v_idx_527) v_v_1503_5)) (<= .cse5 v_b_144_5) (<= (+ v_b_139_5 1) v_b_142_5) (<= (+ v_b_143_5 1) v_b_145_5))))) (forall ((v_idx_510 Int) (v_idx_504 Int) (v_idx_505 Int) (v_idx_502 Int) (v_idx_503 Int) (v_idx_508 Int) (v_idx_509 Int) (v_idx_506 Int) (v_idx_507 Int)) (exists ((v_b_142_5 Int) (v_v_1504_5 Int) (v_v_1496_5 Int) (v_v_1502_5 Int) (v_v_1503_5 Int) (v_b_143_5 Int) (v_v_1500_5 Int) (v_v_1498_5 Int)) (let ((.cse10 (+ c_ULTIMATE.start_main_p4 1)) (.cse9 (+ c_ULTIMATE.start_main_p2 1)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ v_b_142_5 1)) (.cse12 (+ c_ULTIMATE.start_main_p1 3)) (.cse11 (+ c_ULTIMATE.start_main_p2 2))) (and (<= .cse7 v_b_143_5) (or (< v_idx_504 .cse8) (= (select |c_#memory_int| v_idx_504) v_v_1498_5) (<= c_ULTIMATE.start_main_p2 v_idx_504)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_142_5) (<= .cse9 v_b_142_5) (<= v_v_1503_5 0) (or (= (select |c_#memory_int| v_idx_509) v_v_1503_5) (< v_idx_509 c_ULTIMATE.start_main_p4) (<= .cse10 v_idx_509)) (<= v_b_143_5 c_ULTIMATE.start_main_p4) (or (= (select |c_#memory_int| v_idx_502) v_v_1496_5) (<= c_ULTIMATE.start_main_p1 v_idx_502)) (or (< v_idx_510 .cse10) (= (select |c_#memory_int| v_idx_510) v_v_1504_5)) (<= .cse11 c_ULTIMATE.start_main_p4) (or (<= .cse8 v_idx_503) (= 0 (select |c_#memory_int| v_idx_503)) (< v_idx_503 c_ULTIMATE.start_main_p1)) (or (< v_idx_506 .cse9) (<= v_b_142_5 v_idx_506) (= (select |c_#memory_int| v_idx_506) v_v_1500_5)) (<= (* 2 v_v_1503_5) 0) (or (<= .cse9 v_idx_505) (= 0 (select |c_#memory_int| v_idx_505)) (< v_idx_505 c_ULTIMATE.start_main_p2)) (<= .cse12 v_b_143_5) (<= .cse7 c_ULTIMATE.start_main_p4) (or (< v_idx_508 v_b_143_5) (<= c_ULTIMATE.start_main_p4 v_idx_508) (= (select |c_#memory_int| v_idx_508) v_v_1502_5)) (or (< v_idx_507 v_b_142_5) (= 0 (select |c_#memory_int| v_idx_507)) (<= v_b_143_5 v_idx_507)) (<= .cse8 c_ULTIMATE.start_main_p2) (<= v_b_143_5 .cse7) (<= .cse12 c_ULTIMATE.start_main_p4) (<= .cse11 v_b_143_5))))) (forall ((v_idx_511 Int) (v_idx_512 Int) (v_idx_515 Int) (v_idx_516 Int) (v_idx_513 Int) (v_idx_514 Int) (v_idx_519 Int) (v_idx_517 Int) (v_idx_518 Int)) (exists ((v_b_142_5 Int) (v_v_1504_5 Int) (v_b_145_5 Int) (v_v_1502_5 Int) (v_v_1496_5 Int) (v_v_1503_5 Int) (v_b_143_5 Int) (v_v_1500_5 Int) (v_b_144_5 Int) (v_v_1498_5 Int)) (let ((.cse16 (+ c_ULTIMATE.start_main_p1 3)) (.cse14 (+ c_ULTIMATE.start_main_p2 2)) (.cse15 (+ v_b_144_5 1)) (.cse13 (+ c_ULTIMATE.start_main_p2 1)) (.cse17 (+ v_b_142_5 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 1))) (and (or (< v_idx_514 c_ULTIMATE.start_main_p2) (= 0 (select |c_#memory_int| v_idx_514)) (<= .cse13 v_idx_514)) (or (< v_idx_518 v_b_144_5) (= (select |c_#memory_int| v_idx_518) v_v_1503_5) (<= v_b_145_5 v_idx_518)) (<= .cse14 v_b_144_5) (<= (* 2 v_v_1503_5) 0) (<= v_b_145_5 .cse15) (or (< v_idx_519 v_b_145_5) (= (select |c_#memory_int| v_idx_519) v_v_1504_5)) (<= (+ v_b_142_5 2) v_b_145_5) (<= .cse16 v_b_144_5) (<= .cse16 v_b_143_5) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_145_5) (<= v_b_143_5 .cse17) (<= v_b_143_5 v_b_144_5) (<= .cse14 v_b_143_5) (<= .cse17 v_b_143_5) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_142_5) (<= .cse13 v_b_142_5) (<= v_v_1503_5 0) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_145_5) (<= .cse15 v_b_145_5) (or (< v_idx_517 v_b_143_5) (= (select |c_#memory_int| v_idx_517) v_v_1502_5) (<= v_b_144_5 v_idx_517)) (or (= (select |c_#memory_int| v_idx_515) v_v_1500_5) (< v_idx_515 .cse13) (<= v_b_142_5 v_idx_515)) (or (= (select |c_#memory_int| v_idx_513) v_v_1498_5) (<= c_ULTIMATE.start_main_p2 v_idx_513) (< v_idx_513 .cse18)) (<= .cse17 v_b_144_5) (or (<= c_ULTIMATE.start_main_p1 v_idx_511) (= (select |c_#memory_int| v_idx_511) v_v_1496_5)) (or (<= .cse18 v_idx_512) (< v_idx_512 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_512) 0)) (or (< v_idx_516 v_b_142_5) (= (select |c_#memory_int| v_idx_516) 0) (<= v_b_143_5 v_idx_516)) (<= .cse18 c_ULTIMATE.start_main_p2) (<= (+ v_b_143_5 1) v_b_145_5)))))) is different from false [2019-01-11 11:45:06,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:45:06,462 INFO L93 Difference]: Finished difference Result 17 states and 36 transitions. [2019-01-11 11:45:06,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-11 11:45:06,462 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-11 11:45:06,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:45:06,462 INFO L225 Difference]: With dead ends: 17 [2019-01-11 11:45:06,462 INFO L226 Difference]: Without dead ends: 16 [2019-01-11 11:45:06,463 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 9.7s TimeCoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-11 11:45:06,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-11 11:45:06,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2019-01-11 11:45:06,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-11 11:45:06,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 34 transitions. [2019-01-11 11:45:06,474 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 34 transitions. Word has length 4 [2019-01-11 11:45:06,474 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:45:06,474 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 34 transitions. [2019-01-11 11:45:06,474 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-11 11:45:06,474 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 34 transitions. [2019-01-11 11:45:06,475 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:45:06,475 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:45:06,475 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-11 11:45:06,475 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:45:06,475 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:06,475 INFO L82 PathProgramCache]: Analyzing trace with hash 939102, now seen corresponding path program 1 times [2019-01-11 11:45:06,476 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:45:06,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:06,477 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:45:06,477 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:06,477 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:45:06,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:45:06,550 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:45:06,550 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:45:06,550 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:45:06,550 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-11 11:45:06,551 INFO L207 CegarAbsIntRunner]: [0], [6], [16], [19] [2019-01-11 11:45:06,553 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:45:06,553 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:45:20,570 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:45:20,571 INFO L272 AbstractInterpreter]: Visited 4 different actions 31 times. Merged at 2 different actions 9 times. Widened at 2 different actions 5 times. Found 11 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-11 11:45:20,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:20,571 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:45:21,061 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 70.83% of their original sizes. [2019-01-11 11:45:21,061 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:45:23,396 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_654 Int) (v_idx_652 Int) (v_idx_653 Int) (v_idx_647 Int) (v_idx_648 Int) (v_idx_646 Int) (v_idx_649 Int) (v_idx_650 Int) (v_idx_651 Int)) (exists ((v_v_4130_1 Int) (v_b_344_1 Int) (v_v_4129_1 Int) (v_v_4128_1 Int) (v_v_4136_1 Int) (v_v_4134_1 Int) (v_b_347_1 Int) (v_v_4135_1 Int) (v_b_346_1 Int) (v_v_4132_1 Int) (v_b_345_1 Int)) (let ((.cse0 (+ v_b_344_1 2)) (.cse3 (+ c_ULTIMATE.start_main_p1 3)) (.cse5 (+ v_b_345_1 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_344_1 1)) (.cse2 (+ v_b_346_1 1)) (.cse7 (+ c_ULTIMATE.start_main_p4 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 2))) (and (<= 0 v_v_4129_1) (<= .cse0 c_ULTIMATE.start_main_p4) (<= v_b_345_1 .cse1) (<= .cse2 c_ULTIMATE.start_main_p4) (<= .cse1 v_b_346_1) (<= .cse3 v_b_347_1) (or (<= v_b_344_1 v_idx_648) (< v_idx_648 .cse4) (= (select |c_#memory_int| v_idx_648) v_v_4130_1)) (<= v_b_345_1 v_b_346_1) (<= v_b_347_1 c_ULTIMATE.start_main_p4) (<= .cse0 v_b_347_1) (<= .cse5 v_b_347_1) (<= v_b_347_1 .cse2) (<= .cse3 c_ULTIMATE.start_main_p4) (<= 0 (* 2 v_v_4129_1)) (<= .cse5 c_ULTIMATE.start_main_p4) (<= .cse4 v_b_344_1) (or (< v_idx_649 v_b_344_1) (= (select |c_#memory_int| v_idx_649) 0) (<= v_b_345_1 v_idx_649)) (<= .cse6 v_b_346_1) (or (= (select |c_#memory_int| v_idx_647) v_v_4129_1) (<= .cse4 v_idx_647) (< v_idx_647 c_ULTIMATE.start_main_p1)) (or (= (select |c_#memory_int| v_idx_646) v_v_4128_1) (<= c_ULTIMATE.start_main_p1 v_idx_646)) (<= v_v_4135_1 v_v_4129_1) (or (<= .cse7 v_idx_653) (< v_idx_653 c_ULTIMATE.start_main_p4) (= (select |c_#memory_int| v_idx_653) v_v_4135_1)) (or (< v_idx_651 v_b_346_1) (= (select |c_#memory_int| v_idx_651) 0) (<= v_b_347_1 v_idx_651)) (<= .cse1 v_b_345_1) (<= .cse2 v_b_347_1) (<= (* 2 v_v_4135_1) 0) (or (= (select |c_#memory_int| v_idx_650) v_v_4132_1) (<= v_b_346_1 v_idx_650) (< v_idx_650 v_b_345_1)) (<= v_v_4135_1 0) (or (< v_idx_654 .cse7) (= (select |c_#memory_int| v_idx_654) v_v_4136_1)) (<= .cse6 v_b_345_1) (or (= (select |c_#memory_int| v_idx_652) v_v_4134_1) (< v_idx_652 v_b_347_1) (<= c_ULTIMATE.start_main_p4 v_idx_652)))))) is different from false [2019-01-11 11:45:25,955 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_655 Int) (v_idx_663 Int) (v_idx_658 Int) (v_idx_659 Int) (v_idx_656 Int) (v_idx_657 Int) (v_idx_661 Int) (v_idx_662 Int) (v_idx_660 Int)) (exists ((v_v_4129_1 Int) (v_v_4128_1 Int) (v_v_4136_1 Int) (v_b_349_1 Int) (v_v_4134_1 Int) (v_b_348_1 Int) (v_b_347_1 Int) (v_v_4135_1 Int) (v_b_346_1 Int) (v_v_4132_1 Int) (v_b_345_1 Int) (v_b_344_1 Int) (v_v_4130_1 Int)) (let ((.cse2 (+ v_b_345_1 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_344_1 1)) (.cse0 (+ v_b_346_1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 3)) (.cse7 (+ v_b_348_1 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 2)) (.cse5 (+ v_b_344_1 2))) (and (<= 0 v_v_4129_1) (<= .cse0 v_b_348_1) (<= v_b_345_1 .cse1) (<= .cse2 v_b_348_1) (<= .cse1 v_b_346_1) (<= .cse3 v_b_347_1) (or (< v_idx_661 v_b_347_1) (<= v_b_348_1 v_idx_661) (= (select |c_#memory_int| v_idx_661) v_v_4134_1)) (or (= (select |c_#memory_int| v_idx_656) v_v_4129_1) (<= .cse4 v_idx_656) (< v_idx_656 c_ULTIMATE.start_main_p1)) (<= v_b_345_1 v_b_346_1) (<= v_b_347_1 v_b_348_1) (<= .cse5 v_b_347_1) (<= .cse2 v_b_347_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_655) (= (select |c_#memory_int| v_idx_655) v_v_4128_1)) (<= (+ v_b_344_1 3) v_b_349_1) (or (= (select |c_#memory_int| v_idx_658) 0) (< v_idx_658 v_b_344_1) (<= v_b_345_1 v_idx_658)) (<= v_b_347_1 .cse0) (or (= (select |c_#memory_int| v_idx_660) 0) (< v_idx_660 v_b_346_1) (<= v_b_347_1 v_idx_660)) (<= 0 (* 2 v_v_4129_1)) (<= (+ v_b_346_1 2) v_b_349_1) (<= .cse4 v_b_344_1) (<= .cse6 v_b_346_1) (<= v_v_4135_1 v_v_4129_1) (<= v_b_349_1 .cse7) (or (= (select |c_#memory_int| v_idx_657) v_v_4130_1) (<= v_b_344_1 v_idx_657) (< v_idx_657 .cse4)) (<= (+ v_b_345_1 2) v_b_349_1) (<= .cse1 v_b_345_1) (or (= (select |c_#memory_int| v_idx_659) v_v_4132_1) (< v_idx_659 v_b_345_1) (<= v_b_346_1 v_idx_659)) (<= .cse0 v_b_347_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_349_1) (<= (* 2 v_v_4135_1) 0) (<= .cse3 v_b_348_1) (or (< v_idx_662 v_b_348_1) (= (select |c_#memory_int| v_idx_662) v_v_4135_1) (<= v_b_349_1 v_idx_662)) (<= (+ v_b_347_1 1) v_b_349_1) (<= .cse7 v_b_349_1) (<= v_v_4135_1 0) (or (< v_idx_663 v_b_349_1) (= (select |c_#memory_int| v_idx_663) v_v_4136_1)) (<= .cse6 v_b_345_1) (<= .cse5 v_b_348_1))))) is different from false [2019-01-11 11:45:28,670 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_665 Int) (v_idx_666 Int) (v_idx_664 Int) (v_idx_669 Int) (v_idx_667 Int) (v_idx_668 Int) (v_idx_672 Int) (v_idx_670 Int) (v_idx_671 Int)) (exists ((v_v_4129_1 Int) (v_v_4128_1 Int) (v_v_4136_1 Int) (v_b_349_1 Int) (v_b_348_1 Int) (v_v_4134_1 Int) (v_b_347_1 Int) (v_v_4135_1 Int) (v_v_4132_1 Int) (v_b_346_1 Int) (v_b_345_1 Int) (v_b_344_1 Int) (v_v_4130_1 Int)) (let ((.cse2 (+ v_b_345_1 1)) (.cse1 (+ v_b_344_1 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ v_b_346_1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 3)) (.cse7 (+ v_b_348_1 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 2)) (.cse4 (+ v_b_344_1 2))) (and (<= 0 v_v_4129_1) (<= .cse0 v_b_348_1) (<= v_b_345_1 .cse1) (or (= (select |c_#memory_int| v_idx_672) v_v_4136_1) (< v_idx_672 v_b_349_1)) (<= .cse2 v_b_348_1) (<= .cse1 v_b_346_1) (<= .cse3 v_b_347_1) (or (< v_idx_668 v_b_345_1) (= (select |c_#memory_int| v_idx_668) v_v_4132_1) (<= v_b_346_1 v_idx_668)) (or (= (select |c_#memory_int| v_idx_667) 0) (<= v_b_345_1 v_idx_667) (< v_idx_667 v_b_344_1)) (<= v_b_345_1 v_b_346_1) (<= v_b_347_1 v_b_348_1) (<= .cse4 v_b_347_1) (<= .cse2 v_b_347_1) (or (< v_idx_670 v_b_347_1) (<= v_b_348_1 v_idx_670) (= (select |c_#memory_int| v_idx_670) v_v_4134_1)) (<= (+ v_b_344_1 3) v_b_349_1) (<= v_b_347_1 .cse0) (or (= 0 (select |c_#memory_int| v_idx_669)) (< v_idx_669 v_b_346_1) (<= v_b_347_1 v_idx_669)) (or (<= .cse5 v_idx_665) (< v_idx_665 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_665) v_v_4129_1)) (<= 0 (* 2 v_v_4129_1)) (or (<= v_b_349_1 v_idx_671) (= (select |c_#memory_int| v_idx_671) v_v_4135_1) (< v_idx_671 v_b_348_1)) (<= (+ v_b_346_1 2) v_b_349_1) (<= .cse5 v_b_344_1) (<= .cse6 v_b_346_1) (<= v_v_4135_1 v_v_4129_1) (<= v_b_349_1 .cse7) (or (= (select |c_#memory_int| v_idx_664) v_v_4128_1) (<= c_ULTIMATE.start_main_p1 v_idx_664)) (<= (+ v_b_345_1 2) v_b_349_1) (<= .cse1 v_b_345_1) (or (< v_idx_666 .cse5) (<= v_b_344_1 v_idx_666) (= (select |c_#memory_int| v_idx_666) v_v_4130_1)) (<= .cse0 v_b_347_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_349_1) (<= (* 2 v_v_4135_1) 0) (<= .cse3 v_b_348_1) (<= (+ v_b_347_1 1) v_b_349_1) (<= .cse7 v_b_349_1) (<= v_v_4135_1 0) (<= .cse6 v_b_345_1) (<= .cse4 v_b_348_1))))) is different from false [2019-01-11 11:45:28,774 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-11 11:45:28,774 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:45:28,774 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:45:28,774 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 6 [2019-01-11 11:45:28,774 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:45:28,775 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-11 11:45:28,775 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-11 11:45:28,775 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:45:28,775 INFO L87 Difference]: Start difference. First operand 15 states and 34 transitions. Second operand 5 states. [2019-01-11 11:45:31,207 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_654 Int) (v_idx_652 Int) (v_idx_653 Int) (v_idx_647 Int) (v_idx_648 Int) (v_idx_646 Int) (v_idx_649 Int) (v_idx_650 Int) (v_idx_651 Int)) (exists ((v_v_4130_1 Int) (v_b_344_1 Int) (v_v_4129_1 Int) (v_v_4128_1 Int) (v_v_4136_1 Int) (v_v_4134_1 Int) (v_b_347_1 Int) (v_v_4135_1 Int) (v_b_346_1 Int) (v_v_4132_1 Int) (v_b_345_1 Int)) (let ((.cse0 (+ v_b_344_1 2)) (.cse3 (+ c_ULTIMATE.start_main_p1 3)) (.cse5 (+ v_b_345_1 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_344_1 1)) (.cse2 (+ v_b_346_1 1)) (.cse7 (+ c_ULTIMATE.start_main_p4 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 2))) (and (<= 0 v_v_4129_1) (<= .cse0 c_ULTIMATE.start_main_p4) (<= v_b_345_1 .cse1) (<= .cse2 c_ULTIMATE.start_main_p4) (<= .cse1 v_b_346_1) (<= .cse3 v_b_347_1) (or (<= v_b_344_1 v_idx_648) (< v_idx_648 .cse4) (= (select |c_#memory_int| v_idx_648) v_v_4130_1)) (<= v_b_345_1 v_b_346_1) (<= v_b_347_1 c_ULTIMATE.start_main_p4) (<= .cse0 v_b_347_1) (<= .cse5 v_b_347_1) (<= v_b_347_1 .cse2) (<= .cse3 c_ULTIMATE.start_main_p4) (<= 0 (* 2 v_v_4129_1)) (<= .cse5 c_ULTIMATE.start_main_p4) (<= .cse4 v_b_344_1) (or (< v_idx_649 v_b_344_1) (= (select |c_#memory_int| v_idx_649) 0) (<= v_b_345_1 v_idx_649)) (<= .cse6 v_b_346_1) (or (= (select |c_#memory_int| v_idx_647) v_v_4129_1) (<= .cse4 v_idx_647) (< v_idx_647 c_ULTIMATE.start_main_p1)) (or (= (select |c_#memory_int| v_idx_646) v_v_4128_1) (<= c_ULTIMATE.start_main_p1 v_idx_646)) (<= v_v_4135_1 v_v_4129_1) (or (<= .cse7 v_idx_653) (< v_idx_653 c_ULTIMATE.start_main_p4) (= (select |c_#memory_int| v_idx_653) v_v_4135_1)) (or (< v_idx_651 v_b_346_1) (= (select |c_#memory_int| v_idx_651) 0) (<= v_b_347_1 v_idx_651)) (<= .cse1 v_b_345_1) (<= .cse2 v_b_347_1) (<= (* 2 v_v_4135_1) 0) (or (= (select |c_#memory_int| v_idx_650) v_v_4132_1) (<= v_b_346_1 v_idx_650) (< v_idx_650 v_b_345_1)) (<= v_v_4135_1 0) (or (< v_idx_654 .cse7) (= (select |c_#memory_int| v_idx_654) v_v_4136_1)) (<= .cse6 v_b_345_1) (or (= (select |c_#memory_int| v_idx_652) v_v_4134_1) (< v_idx_652 v_b_347_1) (<= c_ULTIMATE.start_main_p4 v_idx_652)))))) (forall ((v_idx_655 Int) (v_idx_663 Int) (v_idx_658 Int) (v_idx_659 Int) (v_idx_656 Int) (v_idx_657 Int) (v_idx_661 Int) (v_idx_662 Int) (v_idx_660 Int)) (exists ((v_v_4129_1 Int) (v_v_4128_1 Int) (v_v_4136_1 Int) (v_b_349_1 Int) (v_v_4134_1 Int) (v_b_348_1 Int) (v_b_347_1 Int) (v_v_4135_1 Int) (v_b_346_1 Int) (v_v_4132_1 Int) (v_b_345_1 Int) (v_b_344_1 Int) (v_v_4130_1 Int)) (let ((.cse10 (+ v_b_345_1 1)) (.cse12 (+ c_ULTIMATE.start_main_p1 1)) (.cse9 (+ v_b_344_1 1)) (.cse8 (+ v_b_346_1 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 3)) (.cse15 (+ v_b_348_1 1)) (.cse14 (+ c_ULTIMATE.start_main_p1 2)) (.cse13 (+ v_b_344_1 2))) (and (<= 0 v_v_4129_1) (<= .cse8 v_b_348_1) (<= v_b_345_1 .cse9) (<= .cse10 v_b_348_1) (<= .cse9 v_b_346_1) (<= .cse11 v_b_347_1) (or (< v_idx_661 v_b_347_1) (<= v_b_348_1 v_idx_661) (= (select |c_#memory_int| v_idx_661) v_v_4134_1)) (or (= (select |c_#memory_int| v_idx_656) v_v_4129_1) (<= .cse12 v_idx_656) (< v_idx_656 c_ULTIMATE.start_main_p1)) (<= v_b_345_1 v_b_346_1) (<= v_b_347_1 v_b_348_1) (<= .cse13 v_b_347_1) (<= .cse10 v_b_347_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_655) (= (select |c_#memory_int| v_idx_655) v_v_4128_1)) (<= (+ v_b_344_1 3) v_b_349_1) (or (= (select |c_#memory_int| v_idx_658) 0) (< v_idx_658 v_b_344_1) (<= v_b_345_1 v_idx_658)) (<= v_b_347_1 .cse8) (or (= (select |c_#memory_int| v_idx_660) 0) (< v_idx_660 v_b_346_1) (<= v_b_347_1 v_idx_660)) (<= 0 (* 2 v_v_4129_1)) (<= (+ v_b_346_1 2) v_b_349_1) (<= .cse12 v_b_344_1) (<= .cse14 v_b_346_1) (<= v_v_4135_1 v_v_4129_1) (<= v_b_349_1 .cse15) (or (= (select |c_#memory_int| v_idx_657) v_v_4130_1) (<= v_b_344_1 v_idx_657) (< v_idx_657 .cse12)) (<= (+ v_b_345_1 2) v_b_349_1) (<= .cse9 v_b_345_1) (or (= (select |c_#memory_int| v_idx_659) v_v_4132_1) (< v_idx_659 v_b_345_1) (<= v_b_346_1 v_idx_659)) (<= .cse8 v_b_347_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_349_1) (<= (* 2 v_v_4135_1) 0) (<= .cse11 v_b_348_1) (or (< v_idx_662 v_b_348_1) (= (select |c_#memory_int| v_idx_662) v_v_4135_1) (<= v_b_349_1 v_idx_662)) (<= (+ v_b_347_1 1) v_b_349_1) (<= .cse15 v_b_349_1) (<= v_v_4135_1 0) (or (< v_idx_663 v_b_349_1) (= (select |c_#memory_int| v_idx_663) v_v_4136_1)) (<= .cse14 v_b_345_1) (<= .cse13 v_b_348_1))))) (forall ((v_idx_665 Int) (v_idx_666 Int) (v_idx_664 Int) (v_idx_669 Int) (v_idx_667 Int) (v_idx_668 Int) (v_idx_672 Int) (v_idx_670 Int) (v_idx_671 Int)) (exists ((v_v_4129_1 Int) (v_v_4128_1 Int) (v_v_4136_1 Int) (v_b_349_1 Int) (v_b_348_1 Int) (v_v_4134_1 Int) (v_b_347_1 Int) (v_v_4135_1 Int) (v_v_4132_1 Int) (v_b_346_1 Int) (v_b_345_1 Int) (v_b_344_1 Int) (v_v_4130_1 Int)) (let ((.cse18 (+ v_b_345_1 1)) (.cse17 (+ v_b_344_1 1)) (.cse21 (+ c_ULTIMATE.start_main_p1 1)) (.cse16 (+ v_b_346_1 1)) (.cse19 (+ c_ULTIMATE.start_main_p1 3)) (.cse23 (+ v_b_348_1 1)) (.cse22 (+ c_ULTIMATE.start_main_p1 2)) (.cse20 (+ v_b_344_1 2))) (and (<= 0 v_v_4129_1) (<= .cse16 v_b_348_1) (<= v_b_345_1 .cse17) (or (= (select |c_#memory_int| v_idx_672) v_v_4136_1) (< v_idx_672 v_b_349_1)) (<= .cse18 v_b_348_1) (<= .cse17 v_b_346_1) (<= .cse19 v_b_347_1) (or (< v_idx_668 v_b_345_1) (= (select |c_#memory_int| v_idx_668) v_v_4132_1) (<= v_b_346_1 v_idx_668)) (or (= (select |c_#memory_int| v_idx_667) 0) (<= v_b_345_1 v_idx_667) (< v_idx_667 v_b_344_1)) (<= v_b_345_1 v_b_346_1) (<= v_b_347_1 v_b_348_1) (<= .cse20 v_b_347_1) (<= .cse18 v_b_347_1) (or (< v_idx_670 v_b_347_1) (<= v_b_348_1 v_idx_670) (= (select |c_#memory_int| v_idx_670) v_v_4134_1)) (<= (+ v_b_344_1 3) v_b_349_1) (<= v_b_347_1 .cse16) (or (= 0 (select |c_#memory_int| v_idx_669)) (< v_idx_669 v_b_346_1) (<= v_b_347_1 v_idx_669)) (or (<= .cse21 v_idx_665) (< v_idx_665 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_665) v_v_4129_1)) (<= 0 (* 2 v_v_4129_1)) (or (<= v_b_349_1 v_idx_671) (= (select |c_#memory_int| v_idx_671) v_v_4135_1) (< v_idx_671 v_b_348_1)) (<= (+ v_b_346_1 2) v_b_349_1) (<= .cse21 v_b_344_1) (<= .cse22 v_b_346_1) (<= v_v_4135_1 v_v_4129_1) (<= v_b_349_1 .cse23) (or (= (select |c_#memory_int| v_idx_664) v_v_4128_1) (<= c_ULTIMATE.start_main_p1 v_idx_664)) (<= (+ v_b_345_1 2) v_b_349_1) (<= .cse17 v_b_345_1) (or (< v_idx_666 .cse21) (<= v_b_344_1 v_idx_666) (= (select |c_#memory_int| v_idx_666) v_v_4130_1)) (<= .cse16 v_b_347_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_349_1) (<= (* 2 v_v_4135_1) 0) (<= .cse19 v_b_348_1) (<= (+ v_b_347_1 1) v_b_349_1) (<= .cse23 v_b_349_1) (<= v_v_4135_1 0) (<= .cse22 v_b_345_1) (<= .cse20 v_b_348_1)))))) is different from false [2019-01-11 11:46:11,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:46:11,990 INFO L93 Difference]: Finished difference Result 18 states and 45 transitions. [2019-01-11 11:46:11,990 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-11 11:46:11,990 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-11 11:46:11,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:46:11,991 INFO L225 Difference]: With dead ends: 18 [2019-01-11 11:46:11,991 INFO L226 Difference]: Without dead ends: 17 [2019-01-11 11:46:11,991 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 9.9s TimeCoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-11 11:46:11,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2019-01-11 11:46:12,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 15. [2019-01-11 11:46:12,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-11 11:46:12,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 34 transitions. [2019-01-11 11:46:12,003 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 34 transitions. Word has length 4 [2019-01-11 11:46:12,004 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:46:12,004 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 34 transitions. [2019-01-11 11:46:12,004 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-11 11:46:12,004 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 34 transitions. [2019-01-11 11:46:12,004 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:46:12,004 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:46:12,004 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-11 11:46:12,005 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:46:12,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:46:12,005 INFO L82 PathProgramCache]: Analyzing trace with hash 939226, now seen corresponding path program 1 times [2019-01-11 11:46:12,005 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:46:12,007 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:46:12,007 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:46:12,007 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:46:12,007 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:46:12,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:46:12,108 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:46:12,108 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:46:12,108 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:46:12,108 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-11 11:46:12,109 INFO L207 CegarAbsIntRunner]: [0], [10], [16], [19] [2019-01-11 11:46:12,110 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:46:12,110 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:46:26,223 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:46:26,223 INFO L272 AbstractInterpreter]: Visited 4 different actions 31 times. Merged at 2 different actions 9 times. Widened at 2 different actions 5 times. Found 11 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-11 11:46:26,224 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:46:26,224 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:46:26,611 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 62.5% of their original sizes. [2019-01-11 11:46:26,612 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:46:29,300 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_797 Int) (v_idx_798 Int) (v_idx_795 Int) (v_idx_796 Int) (v_idx_790 Int) (v_idx_793 Int) (v_idx_794 Int) (v_idx_791 Int) (v_idx_792 Int)) (exists ((v_v_4162_2 Int) (v_b_370_2 Int) (v_b_371_2 Int) (v_v_4170_2 Int) (v_v_4169_2 Int) (v_v_4168_2 Int) (v_v_4166_2 Int) (v_v_4165_2 Int) (v_v_4164_2 Int)) (let ((.cse0 (+ v_b_370_2 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 3)) (.cse3 (+ c_ULTIMATE.start_main_p2 2)) (.cse1 (+ c_ULTIMATE.start_main_p4 1)) (.cse5 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_371_2 c_ULTIMATE.start_main_p4) (<= v_b_371_2 .cse0) (or (<= c_ULTIMATE.start_main_p1 v_idx_790) (= (select |c_#memory_int| v_idx_790) v_v_4162_2)) (<= .cse0 c_ULTIMATE.start_main_p4) (or (<= .cse1 v_idx_797) (= (select |c_#memory_int| v_idx_797) v_v_4169_2) (< v_idx_797 c_ULTIMATE.start_main_p4)) (or (<= c_ULTIMATE.start_main_p2 v_idx_792) (= (select |c_#memory_int| v_idx_792) v_v_4164_2) (< v_idx_792 .cse2)) (<= .cse3 v_b_371_2) (or (<= v_b_371_2 v_idx_795) (< v_idx_795 v_b_370_2) (= (select |c_#memory_int| v_idx_795) 0)) (<= .cse0 v_b_371_2) (<= .cse4 v_b_371_2) (<= .cse4 c_ULTIMATE.start_main_p4) (<= .cse5 v_b_370_2) (<= (* 2 v_v_4169_2) 0) (or (<= .cse2 v_idx_791) (< v_idx_791 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_791) 0)) (or (<= c_ULTIMATE.start_main_p4 v_idx_796) (= (select |c_#memory_int| v_idx_796) v_v_4168_2) (< v_idx_796 v_b_371_2)) (<= v_v_4169_2 0) (<= .cse3 c_ULTIMATE.start_main_p4) (<= v_v_4165_2 0) (or (< v_idx_798 .cse1) (= (select |c_#memory_int| v_idx_798) v_v_4170_2)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_370_2) (<= (* 2 v_v_4165_2) 0) (or (< v_idx_793 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_793) v_v_4165_2) (<= .cse5 v_idx_793)) (or (= (select |c_#memory_int| v_idx_794) v_v_4166_2) (<= v_b_370_2 v_idx_794) (< v_idx_794 .cse5)) (<= .cse2 c_ULTIMATE.start_main_p2) (<= (+ v_v_4169_2 v_v_4165_2) 0))))) is different from false [2019-01-11 11:46:31,744 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_801 Int) (v_idx_802 Int) (v_idx_799 Int) (v_idx_800 Int) (v_idx_805 Int) (v_idx_806 Int) (v_idx_803 Int) (v_idx_804 Int) (v_idx_807 Int)) (exists ((v_b_373_2 Int) (v_v_4162_2 Int) (v_b_370_2 Int) (v_b_371_2 Int) (v_b_372_2 Int) (v_v_4170_2 Int) (v_v_4169_2 Int) (v_v_4168_2 Int) (v_v_4166_2 Int) (v_v_4165_2 Int) (v_v_4164_2 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p2 2)) (.cse2 (+ c_ULTIMATE.start_main_p1 3)) (.cse1 (+ v_b_370_2 1)) (.cse5 (+ v_b_372_2 1)) (.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_799) (= (select |c_#memory_int| v_idx_799) v_v_4162_2)) (<= .cse0 v_b_372_2) (<= v_b_371_2 .cse1) (<= .cse2 v_b_372_2) (<= (+ v_b_370_2 2) v_b_373_2) (or (< v_idx_804 v_b_370_2) (= (select |c_#memory_int| v_idx_804) 0) (<= v_b_371_2 v_idx_804)) (or (< v_idx_801 .cse3) (<= c_ULTIMATE.start_main_p2 v_idx_801) (= (select |c_#memory_int| v_idx_801) v_v_4164_2)) (<= .cse0 v_b_371_2) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_373_2) (or (= (select |c_#memory_int| v_idx_800) 0) (<= .cse3 v_idx_800) (< v_idx_800 c_ULTIMATE.start_main_p1)) (or (<= v_b_370_2 v_idx_803) (= (select |c_#memory_int| v_idx_803) v_v_4166_2) (< v_idx_803 .cse4)) (<= .cse1 v_b_371_2) (or (< v_idx_807 v_b_373_2) (= (select |c_#memory_int| v_idx_807) v_v_4170_2)) (<= .cse2 v_b_371_2) (or (<= v_b_372_2 v_idx_805) (< v_idx_805 v_b_371_2) (= (select |c_#memory_int| v_idx_805) v_v_4168_2)) (<= .cse5 v_b_373_2) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_373_2) (or (= (select |c_#memory_int| v_idx_806) v_v_4169_2) (< v_idx_806 v_b_372_2) (<= v_b_373_2 v_idx_806)) (<= .cse4 v_b_370_2) (<= v_b_371_2 v_b_372_2) (<= (* 2 v_v_4169_2) 0) (<= v_v_4169_2 0) (<= .cse1 v_b_372_2) (<= v_b_373_2 .cse5) (or (= (select |c_#memory_int| v_idx_802) v_v_4165_2) (< v_idx_802 c_ULTIMATE.start_main_p2) (<= .cse4 v_idx_802)) (<= v_v_4165_2 0) (<= (+ v_b_371_2 1) v_b_373_2) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_370_2) (<= (* 2 v_v_4165_2) 0) (<= .cse3 c_ULTIMATE.start_main_p2) (<= (+ v_v_4169_2 v_v_4165_2) 0))))) is different from false [2019-01-11 11:46:34,404 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_812 Int) (v_idx_813 Int) (v_idx_810 Int) (v_idx_811 Int) (v_idx_816 Int) (v_idx_814 Int) (v_idx_815 Int) (v_idx_809 Int) (v_idx_808 Int)) (exists ((v_v_4169_2 Int) (v_v_4168_2 Int) (v_b_369_2 Int) (v_v_4166_2 Int) (v_b_368_2 Int) (v_v_4165_2 Int) (v_v_4164_2 Int) (v_b_373_2 Int) (v_v_4162_2 Int) (v_b_370_2 Int) (v_b_371_2 Int) (v_b_372_2 Int) (v_v_4170_2 Int)) (let ((.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse3 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ v_b_370_2 1)) (.cse5 (+ v_b_372_2 1)) (.cse4 (+ v_b_369_2 1)) (.cse6 (+ v_b_368_2 2)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ v_b_368_2 1))) (and (<= v_b_371_2 .cse0) (or (<= v_b_372_2 v_idx_814) (< v_idx_814 v_b_371_2) (= (select |c_#memory_int| v_idx_814) v_v_4168_2)) (or (<= v_b_370_2 v_idx_812) (= (select |c_#memory_int| v_idx_812) v_v_4166_2) (< v_idx_812 v_b_369_2)) (<= .cse1 v_b_372_2) (<= v_b_369_2 .cse2) (or (< v_idx_810 .cse3) (<= v_b_368_2 v_idx_810) (= (select |c_#memory_int| v_idx_810) v_v_4164_2)) (<= (+ v_b_370_2 2) v_b_373_2) (or (= (select |c_#memory_int| v_idx_816) v_v_4170_2) (< v_idx_816 v_b_373_2)) (<= (+ v_b_369_2 2) v_b_373_2) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_373_2) (<= .cse4 v_b_371_2) (<= .cse0 v_b_371_2) (or (< v_idx_813 v_b_370_2) (<= v_b_371_2 v_idx_813) (= (select |c_#memory_int| v_idx_813) 0)) (or (< v_idx_815 v_b_372_2) (= (select |c_#memory_int| v_idx_815) v_v_4169_2) (<= v_b_373_2 v_idx_815)) (<= .cse2 v_b_370_2) (<= .cse1 v_b_371_2) (<= .cse5 v_b_373_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_808) (= (select |c_#memory_int| v_idx_808) v_v_4162_2)) (or (< v_idx_811 v_b_368_2) (<= v_b_369_2 v_idx_811) (= (select |c_#memory_int| v_idx_811) v_v_4165_2)) (<= .cse3 v_b_368_2) (<= (+ v_b_368_2 3) v_b_373_2) (<= v_b_371_2 v_b_372_2) (<= (* 2 v_v_4169_2) 0) (<= .cse6 v_b_372_2) (or (= (select |c_#memory_int| v_idx_809) 0) (< v_idx_809 c_ULTIMATE.start_main_p1) (<= .cse3 v_idx_809)) (<= v_v_4169_2 0) (<= .cse7 v_b_369_2) (<= .cse0 v_b_372_2) (<= v_b_373_2 .cse5) (<= .cse4 v_b_372_2) (<= v_v_4165_2 0) (<= .cse6 v_b_371_2) (<= (+ v_b_371_2 1) v_b_373_2) (<= .cse7 v_b_370_2) (<= v_b_369_2 v_b_370_2) (<= (* 2 v_v_4165_2) 0) (<= (+ v_v_4169_2 v_v_4165_2) 0) (<= .cse2 v_b_369_2))))) is different from false [2019-01-11 11:46:34,542 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-11 11:46:34,542 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:46:34,543 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:46:34,543 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 6 [2019-01-11 11:46:34,543 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:46:34,543 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-11 11:46:34,543 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-11 11:46:34,543 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:46:34,544 INFO L87 Difference]: Start difference. First operand 15 states and 34 transitions. Second operand 5 states. [2019-01-11 11:46:37,355 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_797 Int) (v_idx_798 Int) (v_idx_795 Int) (v_idx_796 Int) (v_idx_790 Int) (v_idx_793 Int) (v_idx_794 Int) (v_idx_791 Int) (v_idx_792 Int)) (exists ((v_v_4162_2 Int) (v_b_370_2 Int) (v_b_371_2 Int) (v_v_4170_2 Int) (v_v_4169_2 Int) (v_v_4168_2 Int) (v_v_4166_2 Int) (v_v_4165_2 Int) (v_v_4164_2 Int)) (let ((.cse0 (+ v_b_370_2 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 3)) (.cse3 (+ c_ULTIMATE.start_main_p2 2)) (.cse1 (+ c_ULTIMATE.start_main_p4 1)) (.cse5 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 1))) (and (<= v_b_371_2 c_ULTIMATE.start_main_p4) (<= v_b_371_2 .cse0) (or (<= c_ULTIMATE.start_main_p1 v_idx_790) (= (select |c_#memory_int| v_idx_790) v_v_4162_2)) (<= .cse0 c_ULTIMATE.start_main_p4) (or (<= .cse1 v_idx_797) (= (select |c_#memory_int| v_idx_797) v_v_4169_2) (< v_idx_797 c_ULTIMATE.start_main_p4)) (or (<= c_ULTIMATE.start_main_p2 v_idx_792) (= (select |c_#memory_int| v_idx_792) v_v_4164_2) (< v_idx_792 .cse2)) (<= .cse3 v_b_371_2) (or (<= v_b_371_2 v_idx_795) (< v_idx_795 v_b_370_2) (= (select |c_#memory_int| v_idx_795) 0)) (<= .cse0 v_b_371_2) (<= .cse4 v_b_371_2) (<= .cse4 c_ULTIMATE.start_main_p4) (<= .cse5 v_b_370_2) (<= (* 2 v_v_4169_2) 0) (or (<= .cse2 v_idx_791) (< v_idx_791 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_791) 0)) (or (<= c_ULTIMATE.start_main_p4 v_idx_796) (= (select |c_#memory_int| v_idx_796) v_v_4168_2) (< v_idx_796 v_b_371_2)) (<= v_v_4169_2 0) (<= .cse3 c_ULTIMATE.start_main_p4) (<= v_v_4165_2 0) (or (< v_idx_798 .cse1) (= (select |c_#memory_int| v_idx_798) v_v_4170_2)) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_370_2) (<= (* 2 v_v_4165_2) 0) (or (< v_idx_793 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_793) v_v_4165_2) (<= .cse5 v_idx_793)) (or (= (select |c_#memory_int| v_idx_794) v_v_4166_2) (<= v_b_370_2 v_idx_794) (< v_idx_794 .cse5)) (<= .cse2 c_ULTIMATE.start_main_p2) (<= (+ v_v_4169_2 v_v_4165_2) 0))))) (forall ((v_idx_812 Int) (v_idx_813 Int) (v_idx_810 Int) (v_idx_811 Int) (v_idx_816 Int) (v_idx_814 Int) (v_idx_815 Int) (v_idx_809 Int) (v_idx_808 Int)) (exists ((v_v_4169_2 Int) (v_v_4168_2 Int) (v_b_369_2 Int) (v_v_4166_2 Int) (v_b_368_2 Int) (v_v_4165_2 Int) (v_v_4164_2 Int) (v_b_373_2 Int) (v_v_4162_2 Int) (v_b_370_2 Int) (v_b_371_2 Int) (v_b_372_2 Int) (v_v_4170_2 Int)) (let ((.cse7 (+ c_ULTIMATE.start_main_p1 3)) (.cse9 (+ c_ULTIMATE.start_main_p1 1)) (.cse6 (+ v_b_370_2 1)) (.cse11 (+ v_b_372_2 1)) (.cse10 (+ v_b_369_2 1)) (.cse12 (+ v_b_368_2 2)) (.cse13 (+ c_ULTIMATE.start_main_p1 2)) (.cse8 (+ v_b_368_2 1))) (and (<= v_b_371_2 .cse6) (or (<= v_b_372_2 v_idx_814) (< v_idx_814 v_b_371_2) (= (select |c_#memory_int| v_idx_814) v_v_4168_2)) (or (<= v_b_370_2 v_idx_812) (= (select |c_#memory_int| v_idx_812) v_v_4166_2) (< v_idx_812 v_b_369_2)) (<= .cse7 v_b_372_2) (<= v_b_369_2 .cse8) (or (< v_idx_810 .cse9) (<= v_b_368_2 v_idx_810) (= (select |c_#memory_int| v_idx_810) v_v_4164_2)) (<= (+ v_b_370_2 2) v_b_373_2) (or (= (select |c_#memory_int| v_idx_816) v_v_4170_2) (< v_idx_816 v_b_373_2)) (<= (+ v_b_369_2 2) v_b_373_2) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_373_2) (<= .cse10 v_b_371_2) (<= .cse6 v_b_371_2) (or (< v_idx_813 v_b_370_2) (<= v_b_371_2 v_idx_813) (= (select |c_#memory_int| v_idx_813) 0)) (or (< v_idx_815 v_b_372_2) (= (select |c_#memory_int| v_idx_815) v_v_4169_2) (<= v_b_373_2 v_idx_815)) (<= .cse8 v_b_370_2) (<= .cse7 v_b_371_2) (<= .cse11 v_b_373_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_808) (= (select |c_#memory_int| v_idx_808) v_v_4162_2)) (or (< v_idx_811 v_b_368_2) (<= v_b_369_2 v_idx_811) (= (select |c_#memory_int| v_idx_811) v_v_4165_2)) (<= .cse9 v_b_368_2) (<= (+ v_b_368_2 3) v_b_373_2) (<= v_b_371_2 v_b_372_2) (<= (* 2 v_v_4169_2) 0) (<= .cse12 v_b_372_2) (or (= (select |c_#memory_int| v_idx_809) 0) (< v_idx_809 c_ULTIMATE.start_main_p1) (<= .cse9 v_idx_809)) (<= v_v_4169_2 0) (<= .cse13 v_b_369_2) (<= .cse6 v_b_372_2) (<= v_b_373_2 .cse11) (<= .cse10 v_b_372_2) (<= v_v_4165_2 0) (<= .cse12 v_b_371_2) (<= (+ v_b_371_2 1) v_b_373_2) (<= .cse13 v_b_370_2) (<= v_b_369_2 v_b_370_2) (<= (* 2 v_v_4165_2) 0) (<= (+ v_v_4169_2 v_v_4165_2) 0) (<= .cse8 v_b_369_2))))) (forall ((v_idx_801 Int) (v_idx_802 Int) (v_idx_799 Int) (v_idx_800 Int) (v_idx_805 Int) (v_idx_806 Int) (v_idx_803 Int) (v_idx_804 Int) (v_idx_807 Int)) (exists ((v_b_373_2 Int) (v_v_4162_2 Int) (v_b_370_2 Int) (v_b_371_2 Int) (v_b_372_2 Int) (v_v_4170_2 Int) (v_v_4169_2 Int) (v_v_4168_2 Int) (v_v_4166_2 Int) (v_v_4165_2 Int) (v_v_4164_2 Int)) (let ((.cse14 (+ c_ULTIMATE.start_main_p2 2)) (.cse16 (+ c_ULTIMATE.start_main_p1 3)) (.cse15 (+ v_b_370_2 1)) (.cse19 (+ v_b_372_2 1)) (.cse18 (+ c_ULTIMATE.start_main_p2 1)) (.cse17 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= c_ULTIMATE.start_main_p1 v_idx_799) (= (select |c_#memory_int| v_idx_799) v_v_4162_2)) (<= .cse14 v_b_372_2) (<= v_b_371_2 .cse15) (<= .cse16 v_b_372_2) (<= (+ v_b_370_2 2) v_b_373_2) (or (< v_idx_804 v_b_370_2) (= (select |c_#memory_int| v_idx_804) 0) (<= v_b_371_2 v_idx_804)) (or (< v_idx_801 .cse17) (<= c_ULTIMATE.start_main_p2 v_idx_801) (= (select |c_#memory_int| v_idx_801) v_v_4164_2)) (<= .cse14 v_b_371_2) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_373_2) (or (= (select |c_#memory_int| v_idx_800) 0) (<= .cse17 v_idx_800) (< v_idx_800 c_ULTIMATE.start_main_p1)) (or (<= v_b_370_2 v_idx_803) (= (select |c_#memory_int| v_idx_803) v_v_4166_2) (< v_idx_803 .cse18)) (<= .cse15 v_b_371_2) (or (< v_idx_807 v_b_373_2) (= (select |c_#memory_int| v_idx_807) v_v_4170_2)) (<= .cse16 v_b_371_2) (or (<= v_b_372_2 v_idx_805) (< v_idx_805 v_b_371_2) (= (select |c_#memory_int| v_idx_805) v_v_4168_2)) (<= .cse19 v_b_373_2) (<= (+ c_ULTIMATE.start_main_p2 3) v_b_373_2) (or (= (select |c_#memory_int| v_idx_806) v_v_4169_2) (< v_idx_806 v_b_372_2) (<= v_b_373_2 v_idx_806)) (<= .cse18 v_b_370_2) (<= v_b_371_2 v_b_372_2) (<= (* 2 v_v_4169_2) 0) (<= v_v_4169_2 0) (<= .cse15 v_b_372_2) (<= v_b_373_2 .cse19) (or (= (select |c_#memory_int| v_idx_802) v_v_4165_2) (< v_idx_802 c_ULTIMATE.start_main_p2) (<= .cse18 v_idx_802)) (<= v_v_4165_2 0) (<= (+ v_b_371_2 1) v_b_373_2) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_370_2) (<= (* 2 v_v_4165_2) 0) (<= .cse17 c_ULTIMATE.start_main_p2) (<= (+ v_v_4169_2 v_v_4165_2) 0)))))) is different from false [2019-01-11 11:47:01,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:47:01,874 INFO L93 Difference]: Finished difference Result 18 states and 45 transitions. [2019-01-11 11:47:01,874 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-01-11 11:47:01,874 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2019-01-11 11:47:01,874 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:47:01,875 INFO L225 Difference]: With dead ends: 18 [2019-01-11 11:47:01,875 INFO L226 Difference]: Without dead ends: 17 [2019-01-11 11:47:01,876 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 10.4s TimeCoverageRelationStatistics Valid=9, Invalid=5, Unknown=4, NotChecked=12, Total=30 [2019-01-11 11:47:01,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2019-01-11 11:47:01,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 15. [2019-01-11 11:47:01,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-11 11:47:01,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 34 transitions. [2019-01-11 11:47:01,890 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 34 transitions. Word has length 4 [2019-01-11 11:47:01,891 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:47:01,891 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 34 transitions. [2019-01-11 11:47:01,891 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-01-11 11:47:01,891 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 34 transitions. [2019-01-11 11:47:01,891 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:47:01,891 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:47:01,892 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-11 11:47:01,892 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:47:01,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:01,892 INFO L82 PathProgramCache]: Analyzing trace with hash 939350, now seen corresponding path program 1 times [2019-01-11 11:47:01,892 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:47:01,893 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:01,893 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:47:01,893 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:01,893 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:47:01,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:47:02,046 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:47:02,046 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:47:02,047 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:47:02,047 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-11 11:47:02,047 INFO L207 CegarAbsIntRunner]: [0], [14], [16], [19] [2019-01-11 11:47:02,048 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:47:02,048 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:47:15,733 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:47:15,734 INFO L272 AbstractInterpreter]: Visited 4 different actions 31 times. Merged at 2 different actions 9 times. Widened at 2 different actions 5 times. Found 11 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-11 11:47:15,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:15,734 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:47:16,158 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 62.5% of their original sizes. [2019-01-11 11:47:16,158 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:47:18,544 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_940 Int) (v_idx_941 Int) (v_idx_934 Int) (v_idx_942 Int) (v_idx_937 Int) (v_idx_938 Int) (v_idx_935 Int) (v_idx_936 Int) (v_idx_939 Int)) (exists ((v_v_4151_3 Int) (v_v_4150_3 Int) (v_v_4149_3 Int) (v_v_4147_3 Int) (v_v_4145_3 Int) (v_b_357_3 Int) (v_b_356_3 Int) (v_v_4153_3 Int) (v_v_4152_3 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2)) (.cse1 (+ v_b_356_3 1)) (.cse2 (+ c_ULTIMATE.start_main_p3 1)) (.cse4 (+ c_ULTIMATE.start_main_p4 1))) (and (or (< v_idx_935 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_935) 0) (<= .cse0 v_idx_935)) (<= v_b_357_3 .cse1) (or (= (select |c_#memory_int| v_idx_934) v_v_4145_3) (<= c_ULTIMATE.start_main_p1 v_idx_934)) (<= v_b_357_3 c_ULTIMATE.start_main_p3) (<= v_v_4152_3 0) (or (<= v_b_356_3 v_idx_936) (= (select |c_#memory_int| v_idx_936) v_v_4147_3) (< v_idx_936 .cse0)) (or (<= v_b_357_3 v_idx_937) (< v_idx_937 v_b_356_3) (= (select |c_#memory_int| v_idx_937) 0)) (<= 0 v_v_4150_3) (or (<= c_ULTIMATE.start_main_p4 v_idx_940) (= (select |c_#memory_int| v_idx_940) v_v_4151_3) (< v_idx_940 .cse2)) (<= (+ c_ULTIMATE.start_main_p1 3) c_ULTIMATE.start_main_p4) (<= .cse0 v_b_356_3) (<= .cse3 c_ULTIMATE.start_main_p3) (or (<= .cse2 v_idx_939) (< v_idx_939 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_939) v_v_4150_3)) (<= v_v_4152_3 v_v_4150_3) (<= (+ v_b_357_3 1) c_ULTIMATE.start_main_p4) (<= 0 (* 2 v_v_4150_3)) (<= .cse1 v_b_357_3) (<= .cse3 v_b_357_3) (or (< v_idx_938 v_b_357_3) (= (select |c_#memory_int| v_idx_938) v_v_4149_3) (<= c_ULTIMATE.start_main_p3 v_idx_938)) (or (= (select |c_#memory_int| v_idx_942) v_v_4153_3) (< v_idx_942 .cse4)) (<= .cse1 c_ULTIMATE.start_main_p3) (<= .cse2 c_ULTIMATE.start_main_p4) (<= (+ v_b_356_3 2) c_ULTIMATE.start_main_p4) (or (< v_idx_941 c_ULTIMATE.start_main_p4) (= (select |c_#memory_int| v_idx_941) v_v_4152_3) (<= .cse4 v_idx_941)) (<= (* 2 v_v_4152_3) 0))))) is different from false [2019-01-11 11:47:21,002 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_951 Int) (v_idx_950 Int) (v_idx_944 Int) (v_idx_945 Int) (v_idx_943 Int) (v_idx_948 Int) (v_idx_949 Int) (v_idx_946 Int) (v_idx_947 Int)) (exists ((v_v_4151_3 Int) (v_v_4150_3 Int) (v_b_361_3 Int) (v_b_360_3 Int) (v_v_4149_3 Int) (v_v_4147_3 Int) (v_v_4145_3 Int) (v_b_357_3 Int) (v_b_356_3 Int) (v_v_4153_3 Int) (v_v_4152_3 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2)) (.cse4 (+ v_b_360_3 1)) (.cse2 (+ v_b_356_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= v_b_360_3 v_idx_949) (< v_idx_949 .cse0) (= (select |c_#memory_int| v_idx_949) v_v_4151_3)) (or (<= v_b_356_3 v_idx_945) (< v_idx_945 .cse1) (= (select |c_#memory_int| v_idx_945) v_v_4147_3)) (or (< v_idx_951 v_b_361_3) (= (select |c_#memory_int| v_idx_951) v_v_4153_3)) (<= v_b_357_3 .cse2) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_361_3) (<= (+ c_ULTIMATE.start_main_p3 2) v_b_361_3) (<= (+ v_b_356_3 2) v_b_360_3) (<= (+ v_b_356_3 3) v_b_361_3) (<= v_b_357_3 c_ULTIMATE.start_main_p3) (<= v_v_4152_3 0) (or (= 0 (select |c_#memory_int| v_idx_946)) (<= v_b_357_3 v_idx_946) (< v_idx_946 v_b_356_3)) (<= .cse0 v_b_360_3) (<= 0 v_v_4150_3) (or (= (select |c_#memory_int| v_idx_948) v_v_4150_3) (< v_idx_948 c_ULTIMATE.start_main_p3) (<= .cse0 v_idx_948)) (or (= (select |c_#memory_int| v_idx_950) v_v_4152_3) (<= v_b_361_3 v_idx_950) (< v_idx_950 v_b_360_3)) (or (= (select |c_#memory_int| v_idx_943) v_v_4145_3) (<= c_ULTIMATE.start_main_p1 v_idx_943)) (<= .cse1 v_b_356_3) (<= .cse3 c_ULTIMATE.start_main_p3) (<= v_v_4152_3 v_v_4150_3) (<= 0 (* 2 v_v_4150_3)) (<= .cse2 v_b_357_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_360_3) (or (= (select |c_#memory_int| v_idx_947) v_v_4149_3) (<= c_ULTIMATE.start_main_p3 v_idx_947) (< v_idx_947 v_b_357_3)) (<= (+ v_b_357_3 1) v_b_360_3) (<= .cse3 v_b_357_3) (<= v_b_361_3 .cse4) (<= .cse4 v_b_361_3) (<= .cse2 c_ULTIMATE.start_main_p3) (<= (+ v_b_357_3 2) v_b_361_3) (<= (* 2 v_v_4152_3) 0) (or (<= .cse1 v_idx_944) (= (select |c_#memory_int| v_idx_944) 0) (< v_idx_944 c_ULTIMATE.start_main_p1)))))) is different from false [2019-01-11 11:47:23,539 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_952 Int) (v_idx_960 Int) (v_idx_955 Int) (v_idx_956 Int) (v_idx_953 Int) (v_idx_954 Int) (v_idx_959 Int) (v_idx_957 Int) (v_idx_958 Int)) (exists ((v_v_4149_3 Int) (v_v_4147_3 Int) (v_b_359_3 Int) (v_v_4145_3 Int) (v_b_358_3 Int) (v_b_357_3 Int) (v_b_356_3 Int) (v_v_4153_3 Int) (v_v_4152_3 Int) (v_v_4151_3 Int) (v_v_4150_3 Int) (v_b_361_3 Int) (v_b_360_3 Int)) (let ((.cse0 (+ v_b_356_3 2)) (.cse4 (+ v_b_358_3 1)) (.cse5 (+ v_b_357_3 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ v_b_360_3 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 3)) (.cse1 (+ v_b_356_3 1))) (and (or (<= v_b_359_3 v_idx_957) (= (select |c_#memory_int| v_idx_957) v_v_4150_3) (< v_idx_957 v_b_358_3)) (<= .cse0 v_b_359_3) (<= (+ v_b_359_3 1) v_b_361_3) (<= v_b_359_3 v_b_360_3) (<= v_b_357_3 .cse1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_361_3) (<= .cse0 v_b_360_3) (<= (+ v_b_356_3 3) v_b_361_3) (<= v_v_4152_3 0) (<= (+ v_b_358_3 2) v_b_361_3) (<= 0 v_v_4150_3) (<= .cse2 v_b_358_3) (or (= (select |c_#memory_int| v_idx_954) v_v_4147_3) (< v_idx_954 .cse3) (<= v_b_356_3 v_idx_954)) (<= v_b_359_3 .cse4) (<= .cse5 v_b_359_3) (<= .cse3 v_b_356_3) (<= .cse4 v_b_359_3) (or (<= v_b_361_3 v_idx_959) (< v_idx_959 v_b_360_3) (= (select |c_#memory_int| v_idx_959) v_v_4152_3)) (<= v_v_4152_3 v_v_4150_3) (or (< v_idx_956 v_b_357_3) (<= v_b_358_3 v_idx_956) (= (select |c_#memory_int| v_idx_956) v_v_4149_3)) (<= 0 (* 2 v_v_4150_3)) (<= .cse1 v_b_357_3) (or (< v_idx_955 v_b_356_3) (<= v_b_357_3 v_idx_955) (= (select |c_#memory_int| v_idx_955) 0)) (or (<= v_b_360_3 v_idx_958) (< v_idx_958 v_b_359_3) (= (select |c_#memory_int| v_idx_958) v_v_4151_3)) (<= .cse6 v_b_360_3) (<= .cse4 v_b_360_3) (<= .cse5 v_b_360_3) (<= .cse2 v_b_357_3) (or (= (select |c_#memory_int| v_idx_960) v_v_4153_3) (< v_idx_960 v_b_361_3)) (<= v_b_361_3 .cse7) (<= .cse7 v_b_361_3) (<= v_b_357_3 v_b_358_3) (or (< v_idx_953 c_ULTIMATE.start_main_p1) (<= .cse3 v_idx_953) (= (select |c_#memory_int| v_idx_953) 0)) (<= (+ v_b_357_3 2) v_b_361_3) (<= (* 2 v_v_4152_3) 0) (<= .cse6 v_b_359_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_952) (= (select |c_#memory_int| v_idx_952) v_v_4145_3)) (<= .cse1 v_b_358_3))))) is different from false [2019-01-11 11:47:23,682 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-11 11:47:23,682 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:47:23,682 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:47:23,682 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 6 [2019-01-11 11:47:23,682 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:47:23,682 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-11 11:47:23,683 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-11 11:47:23,683 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:47:23,683 INFO L87 Difference]: Start difference. First operand 15 states and 34 transitions. Second operand 5 states. [2019-01-11 11:47:26,472 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_951 Int) (v_idx_950 Int) (v_idx_944 Int) (v_idx_945 Int) (v_idx_943 Int) (v_idx_948 Int) (v_idx_949 Int) (v_idx_946 Int) (v_idx_947 Int)) (exists ((v_v_4151_3 Int) (v_v_4150_3 Int) (v_b_361_3 Int) (v_b_360_3 Int) (v_v_4149_3 Int) (v_v_4147_3 Int) (v_v_4145_3 Int) (v_b_357_3 Int) (v_b_356_3 Int) (v_v_4153_3 Int) (v_v_4152_3 Int)) (let ((.cse0 (+ c_ULTIMATE.start_main_p3 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 2)) (.cse4 (+ v_b_360_3 1)) (.cse2 (+ v_b_356_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1))) (and (or (<= v_b_360_3 v_idx_949) (< v_idx_949 .cse0) (= (select |c_#memory_int| v_idx_949) v_v_4151_3)) (or (<= v_b_356_3 v_idx_945) (< v_idx_945 .cse1) (= (select |c_#memory_int| v_idx_945) v_v_4147_3)) (or (< v_idx_951 v_b_361_3) (= (select |c_#memory_int| v_idx_951) v_v_4153_3)) (<= v_b_357_3 .cse2) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_361_3) (<= (+ c_ULTIMATE.start_main_p3 2) v_b_361_3) (<= (+ v_b_356_3 2) v_b_360_3) (<= (+ v_b_356_3 3) v_b_361_3) (<= v_b_357_3 c_ULTIMATE.start_main_p3) (<= v_v_4152_3 0) (or (= 0 (select |c_#memory_int| v_idx_946)) (<= v_b_357_3 v_idx_946) (< v_idx_946 v_b_356_3)) (<= .cse0 v_b_360_3) (<= 0 v_v_4150_3) (or (= (select |c_#memory_int| v_idx_948) v_v_4150_3) (< v_idx_948 c_ULTIMATE.start_main_p3) (<= .cse0 v_idx_948)) (or (= (select |c_#memory_int| v_idx_950) v_v_4152_3) (<= v_b_361_3 v_idx_950) (< v_idx_950 v_b_360_3)) (or (= (select |c_#memory_int| v_idx_943) v_v_4145_3) (<= c_ULTIMATE.start_main_p1 v_idx_943)) (<= .cse1 v_b_356_3) (<= .cse3 c_ULTIMATE.start_main_p3) (<= v_v_4152_3 v_v_4150_3) (<= 0 (* 2 v_v_4150_3)) (<= .cse2 v_b_357_3) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_360_3) (or (= (select |c_#memory_int| v_idx_947) v_v_4149_3) (<= c_ULTIMATE.start_main_p3 v_idx_947) (< v_idx_947 v_b_357_3)) (<= (+ v_b_357_3 1) v_b_360_3) (<= .cse3 v_b_357_3) (<= v_b_361_3 .cse4) (<= .cse4 v_b_361_3) (<= .cse2 c_ULTIMATE.start_main_p3) (<= (+ v_b_357_3 2) v_b_361_3) (<= (* 2 v_v_4152_3) 0) (or (<= .cse1 v_idx_944) (= (select |c_#memory_int| v_idx_944) 0) (< v_idx_944 c_ULTIMATE.start_main_p1)))))) (forall ((v_idx_940 Int) (v_idx_941 Int) (v_idx_934 Int) (v_idx_942 Int) (v_idx_937 Int) (v_idx_938 Int) (v_idx_935 Int) (v_idx_936 Int) (v_idx_939 Int)) (exists ((v_v_4151_3 Int) (v_v_4150_3 Int) (v_v_4149_3 Int) (v_v_4147_3 Int) (v_v_4145_3 Int) (v_b_357_3 Int) (v_b_356_3 Int) (v_v_4153_3 Int) (v_v_4152_3 Int)) (let ((.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse8 (+ c_ULTIMATE.start_main_p1 2)) (.cse6 (+ v_b_356_3 1)) (.cse7 (+ c_ULTIMATE.start_main_p3 1)) (.cse9 (+ c_ULTIMATE.start_main_p4 1))) (and (or (< v_idx_935 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_935) 0) (<= .cse5 v_idx_935)) (<= v_b_357_3 .cse6) (or (= (select |c_#memory_int| v_idx_934) v_v_4145_3) (<= c_ULTIMATE.start_main_p1 v_idx_934)) (<= v_b_357_3 c_ULTIMATE.start_main_p3) (<= v_v_4152_3 0) (or (<= v_b_356_3 v_idx_936) (= (select |c_#memory_int| v_idx_936) v_v_4147_3) (< v_idx_936 .cse5)) (or (<= v_b_357_3 v_idx_937) (< v_idx_937 v_b_356_3) (= (select |c_#memory_int| v_idx_937) 0)) (<= 0 v_v_4150_3) (or (<= c_ULTIMATE.start_main_p4 v_idx_940) (= (select |c_#memory_int| v_idx_940) v_v_4151_3) (< v_idx_940 .cse7)) (<= (+ c_ULTIMATE.start_main_p1 3) c_ULTIMATE.start_main_p4) (<= .cse5 v_b_356_3) (<= .cse8 c_ULTIMATE.start_main_p3) (or (<= .cse7 v_idx_939) (< v_idx_939 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_939) v_v_4150_3)) (<= v_v_4152_3 v_v_4150_3) (<= (+ v_b_357_3 1) c_ULTIMATE.start_main_p4) (<= 0 (* 2 v_v_4150_3)) (<= .cse6 v_b_357_3) (<= .cse8 v_b_357_3) (or (< v_idx_938 v_b_357_3) (= (select |c_#memory_int| v_idx_938) v_v_4149_3) (<= c_ULTIMATE.start_main_p3 v_idx_938)) (or (= (select |c_#memory_int| v_idx_942) v_v_4153_3) (< v_idx_942 .cse9)) (<= .cse6 c_ULTIMATE.start_main_p3) (<= .cse7 c_ULTIMATE.start_main_p4) (<= (+ v_b_356_3 2) c_ULTIMATE.start_main_p4) (or (< v_idx_941 c_ULTIMATE.start_main_p4) (= (select |c_#memory_int| v_idx_941) v_v_4152_3) (<= .cse9 v_idx_941)) (<= (* 2 v_v_4152_3) 0))))) (forall ((v_idx_952 Int) (v_idx_960 Int) (v_idx_955 Int) (v_idx_956 Int) (v_idx_953 Int) (v_idx_954 Int) (v_idx_959 Int) (v_idx_957 Int) (v_idx_958 Int)) (exists ((v_v_4149_3 Int) (v_v_4147_3 Int) (v_b_359_3 Int) (v_v_4145_3 Int) (v_b_358_3 Int) (v_b_357_3 Int) (v_b_356_3 Int) (v_v_4153_3 Int) (v_v_4152_3 Int) (v_v_4151_3 Int) (v_v_4150_3 Int) (v_b_361_3 Int) (v_b_360_3 Int)) (let ((.cse10 (+ v_b_356_3 2)) (.cse14 (+ v_b_358_3 1)) (.cse15 (+ v_b_357_3 1)) (.cse12 (+ c_ULTIMATE.start_main_p1 2)) (.cse17 (+ v_b_360_3 1)) (.cse13 (+ c_ULTIMATE.start_main_p1 1)) (.cse16 (+ c_ULTIMATE.start_main_p1 3)) (.cse11 (+ v_b_356_3 1))) (and (or (<= v_b_359_3 v_idx_957) (= (select |c_#memory_int| v_idx_957) v_v_4150_3) (< v_idx_957 v_b_358_3)) (<= .cse10 v_b_359_3) (<= (+ v_b_359_3 1) v_b_361_3) (<= v_b_359_3 v_b_360_3) (<= v_b_357_3 .cse11) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_361_3) (<= .cse10 v_b_360_3) (<= (+ v_b_356_3 3) v_b_361_3) (<= v_v_4152_3 0) (<= (+ v_b_358_3 2) v_b_361_3) (<= 0 v_v_4150_3) (<= .cse12 v_b_358_3) (or (= (select |c_#memory_int| v_idx_954) v_v_4147_3) (< v_idx_954 .cse13) (<= v_b_356_3 v_idx_954)) (<= v_b_359_3 .cse14) (<= .cse15 v_b_359_3) (<= .cse13 v_b_356_3) (<= .cse14 v_b_359_3) (or (<= v_b_361_3 v_idx_959) (< v_idx_959 v_b_360_3) (= (select |c_#memory_int| v_idx_959) v_v_4152_3)) (<= v_v_4152_3 v_v_4150_3) (or (< v_idx_956 v_b_357_3) (<= v_b_358_3 v_idx_956) (= (select |c_#memory_int| v_idx_956) v_v_4149_3)) (<= 0 (* 2 v_v_4150_3)) (<= .cse11 v_b_357_3) (or (< v_idx_955 v_b_356_3) (<= v_b_357_3 v_idx_955) (= (select |c_#memory_int| v_idx_955) 0)) (or (<= v_b_360_3 v_idx_958) (< v_idx_958 v_b_359_3) (= (select |c_#memory_int| v_idx_958) v_v_4151_3)) (<= .cse16 v_b_360_3) (<= .cse14 v_b_360_3) (<= .cse15 v_b_360_3) (<= .cse12 v_b_357_3) (or (= (select |c_#memory_int| v_idx_960) v_v_4153_3) (< v_idx_960 v_b_361_3)) (<= v_b_361_3 .cse17) (<= .cse17 v_b_361_3) (<= v_b_357_3 v_b_358_3) (or (< v_idx_953 c_ULTIMATE.start_main_p1) (<= .cse13 v_idx_953) (= (select |c_#memory_int| v_idx_953) 0)) (<= (+ v_b_357_3 2) v_b_361_3) (<= (* 2 v_v_4152_3) 0) (<= .cse16 v_b_359_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_952) (= (select |c_#memory_int| v_idx_952) v_v_4145_3)) (<= .cse11 v_b_358_3)))))) is different from false