java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml -s ../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf -i ../../../trunk/examples/programs/heapseparator/speedup-poc-dd-5-limited.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.24-df3cc4e-m [2019-01-11 11:42:37,016 INFO L170 SettingsManager]: Resetting all preferences to default values... [2019-01-11 11:42:37,018 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2019-01-11 11:42:37,030 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-01-11 11:42:37,030 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-01-11 11:42:37,032 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-01-11 11:42:37,033 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-01-11 11:42:37,035 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2019-01-11 11:42:37,036 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-01-11 11:42:37,037 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-01-11 11:42:37,038 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... 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[2019-01-11 11:42:37,062 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf [2019-01-11 11:42:37,074 INFO L110 SettingsManager]: Loading preferences was successful [2019-01-11 11:42:37,075 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2019-01-11 11:42:37,076 INFO L131 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2019-01-11 11:42:37,076 INFO L133 SettingsManager]: * Show backtranslation warnings=false [2019-01-11 11:42:37,076 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-01-11 11:42:37,076 INFO L133 SettingsManager]: * User list type=DISABLED [2019-01-11 11:42:37,076 INFO L133 SettingsManager]: * Inline calls to unimplemented procedures=true [2019-01-11 11:42:37,077 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-01-11 11:42:37,077 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-01-11 11:42:37,077 INFO L133 SettingsManager]: * Underlying domain=OctagonDomain [2019-01-11 11:42:37,077 INFO L133 SettingsManager]: * Abstract domain=ArrayDomain [2019-01-11 11:42:37,077 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-01-11 11:42:37,078 INFO L133 SettingsManager]: * Interval Domain=false [2019-01-11 11:42:37,078 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-01-11 11:42:37,079 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2019-01-11 11:42:37,079 INFO L133 SettingsManager]: * Use SBE=true [2019-01-11 11:42:37,079 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-01-11 11:42:37,079 INFO L133 SettingsManager]: * sizeof long=4 [2019-01-11 11:42:37,079 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2019-01-11 11:42:37,080 INFO L133 SettingsManager]: * sizeof POINTER=4 [2019-01-11 11:42:37,080 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2019-01-11 11:42:37,080 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-01-11 11:42:37,080 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-01-11 11:42:37,080 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-01-11 11:42:37,081 INFO L133 SettingsManager]: * sizeof long double=12 [2019-01-11 11:42:37,081 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2019-01-11 11:42:37,081 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-01-11 11:42:37,081 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-01-11 11:42:37,081 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-01-11 11:42:37,082 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2019-01-11 11:42:37,082 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-11 11:42:37,082 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-01-11 11:42:37,082 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-01-11 11:42:37,083 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-01-11 11:42:37,083 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2019-01-11 11:42:37,083 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-01-11 11:42:37,083 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in [2019-01-11 11:42:37,083 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-01-11 11:42:37,084 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2019-01-11 11:42:37,119 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-01-11 11:42:37,132 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-01-11 11:42:37,136 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-01-11 11:42:37,138 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2019-01-11 11:42:37,138 INFO L276 PluginConnector]: Boogie PL CUP Parser initialized [2019-01-11 11:42:37,139 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-5-limited.bpl [2019-01-11 11:42:37,139 INFO L111 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-5-limited.bpl' [2019-01-11 11:42:37,183 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-01-11 11:42:37,185 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-01-11 11:42:37,186 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-01-11 11:42:37,186 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-01-11 11:42:37,187 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2019-01-11 11:42:37,204 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "speedup-poc-dd-5-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:37" (1/1) ... [2019-01-11 11:42:37,216 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "speedup-poc-dd-5-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:37" (1/1) ... [2019-01-11 11:42:37,241 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-01-11 11:42:37,242 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-01-11 11:42:37,242 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-01-11 11:42:37,242 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2019-01-11 11:42:37,254 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "speedup-poc-dd-5-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:37" (1/1) ... [2019-01-11 11:42:37,254 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "speedup-poc-dd-5-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:37" (1/1) ... [2019-01-11 11:42:37,256 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "speedup-poc-dd-5-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:37" (1/1) ... [2019-01-11 11:42:37,256 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "speedup-poc-dd-5-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:37" (1/1) ... [2019-01-11 11:42:37,260 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "speedup-poc-dd-5-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:37" (1/1) ... [2019-01-11 11:42:37,263 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "speedup-poc-dd-5-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:37" (1/1) ... [2019-01-11 11:42:37,264 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "speedup-poc-dd-5-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:37" (1/1) ... [2019-01-11 11:42:37,266 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-01-11 11:42:37,266 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-01-11 11:42:37,267 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-01-11 11:42:37,267 INFO L276 PluginConnector]: RCFGBuilder initialized [2019-01-11 11:42:37,268 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "speedup-poc-dd-5-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:37" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-11 11:42:37,336 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-01-11 11:42:37,336 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-01-11 11:42:37,613 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-01-11 11:42:37,613 INFO L286 CfgBuilder]: Removed 13 assue(true) statements. [2019-01-11 11:42:37,615 INFO L202 PluginConnector]: Adding new model speedup-poc-dd-5-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.01 11:42:37 BoogieIcfgContainer [2019-01-11 11:42:37,615 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-01-11 11:42:37,616 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-01-11 11:42:37,616 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-01-11 11:42:37,622 INFO L276 PluginConnector]: TraceAbstraction initialized [2019-01-11 11:42:37,622 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-5-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:42:37" (1/2) ... [2019-01-11 11:42:37,624 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4174576a and model type speedup-poc-dd-5-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.01 11:42:37, skipping insertion in model container [2019-01-11 11:42:37,624 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-5-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.01 11:42:37" (2/2) ... [2019-01-11 11:42:37,629 INFO L112 eAbstractionObserver]: Analyzing ICFG speedup-poc-dd-5-limited.bpl [2019-01-11 11:42:37,651 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-01-11 11:42:37,668 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 5 error locations. [2019-01-11 11:42:37,709 INFO L257 AbstractCegarLoop]: Starting to check reachability of 5 error locations. [2019-01-11 11:42:37,746 INFO L382 AbstractCegarLoop]: Interprodecural is true [2019-01-11 11:42:37,747 INFO L383 AbstractCegarLoop]: Hoare is true [2019-01-11 11:42:37,747 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-01-11 11:42:37,747 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-01-11 11:42:37,747 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-01-11 11:42:37,747 INFO L387 AbstractCegarLoop]: Difference is false [2019-01-11 11:42:37,748 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-01-11 11:42:37,748 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-01-11 11:42:37,787 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states. [2019-01-11 11:42:37,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3 [2019-01-11 11:42:37,796 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:42:37,797 INFO L402 BasicCegarLoop]: trace histogram [1, 1] [2019-01-11 11:42:37,800 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:42:37,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:42:37,814 INFO L82 PathProgramCache]: Analyzing trace with hash 984, now seen corresponding path program 1 times [2019-01-11 11:42:37,817 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:42:37,867 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:37,867 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:42:37,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:37,868 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:42:37,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:42:38,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:42:38,010 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-11 11:42:38,011 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-11 11:42:38,011 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:42:38,015 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-11 11:42:38,025 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-11 11:42:38,026 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:42:38,028 INFO L87 Difference]: Start difference. First operand 13 states. Second operand 3 states. [2019-01-11 11:42:38,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:42:38,218 INFO L93 Difference]: Finished difference Result 25 states and 33 transitions. [2019-01-11 11:42:38,218 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:42:38,220 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 2 [2019-01-11 11:42:38,220 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:42:38,242 INFO L225 Difference]: With dead ends: 25 [2019-01-11 11:42:38,242 INFO L226 Difference]: Without dead ends: 20 [2019-01-11 11:42:38,251 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:42:38,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-01-11 11:42:38,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 12. [2019-01-11 11:42:38,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2019-01-11 11:42:38,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 21 transitions. [2019-01-11 11:42:38,287 INFO L78 Accepts]: Start accepts. Automaton has 12 states and 21 transitions. Word has length 2 [2019-01-11 11:42:38,288 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:42:38,288 INFO L480 AbstractCegarLoop]: Abstraction has 12 states and 21 transitions. [2019-01-11 11:42:38,288 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-11 11:42:38,289 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 21 transitions. [2019-01-11 11:42:38,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:42:38,289 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:42:38,290 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:42:38,290 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:42:38,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:42:38,291 INFO L82 PathProgramCache]: Analyzing trace with hash 30372, now seen corresponding path program 1 times [2019-01-11 11:42:38,291 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:42:38,292 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:38,292 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:42:38,292 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:42:38,293 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:42:38,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:42:38,467 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:42:38,468 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:42:38,468 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:42:38,469 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:42:38,471 INFO L207 CegarAbsIntRunner]: [0], [18], [23] [2019-01-11 11:42:38,551 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:42:38,552 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:42:49,693 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:42:49,695 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:42:49,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:42:49,700 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:42:50,236 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 72.22% of their original sizes. [2019-01-11 11:42:50,236 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:42:52,494 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_98 Int) (v_idx_99 Int) (v_idx_96 Int) (v_idx_97 Int) (v_idx_94 Int) (v_idx_95 Int) (v_idx_92 Int) (v_idx_93 Int) (v_idx_100 Int) (v_idx_101 Int) (v_idx_91 Int)) (exists ((v_v_1451_1 Int) (v_v_1455_1 Int) (v_v_1454_1 Int) (v_v_1453_1 Int) (v_b_149_1 Int) (v_v_1447_1 Int) (v_v_1457_1 Int) (v_b_148_1 Int) (v_v_1449_1 Int) (v_b_151_1 Int) (v_b_150_1 Int) (v_b_155_1 Int) (v_b_154_1 Int)) (let ((.cse2 (+ v_b_149_1 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse5 (+ c_ULTIMATE.start_main_p1 3)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse6 (+ v_b_148_1 1)) (.cse0 (+ c_ULTIMATE.start_main_p4 1)) (.cse4 (+ v_b_150_1 1)) (.cse3 (+ v_b_148_1 2)) (.cse8 (+ v_b_154_1 1))) (and (or (= (select |c_#memory_int| v_idx_99) v_v_1455_1) (<= v_b_154_1 v_idx_99) (< v_idx_99 .cse0)) (<= .cse1 v_b_148_1) (<= .cse2 v_b_151_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_154_1) (<= .cse3 v_b_151_1) (or (< v_idx_96 v_b_150_1) (<= v_b_151_1 v_idx_96) (= (select |c_#memory_int| v_idx_96) 0)) (<= (+ v_b_148_1 4) v_b_155_1) (or (= (select |c_#memory_int| v_idx_93) v_v_1449_1) (< v_idx_93 .cse1) (<= v_b_148_1 v_idx_93)) (<= (* 2 v_v_1454_1) 0) (<= (+ v_b_148_1 3) v_b_154_1) (<= .cse4 v_b_151_1) (<= .cse5 v_b_151_1) (<= .cse2 c_ULTIMATE.start_main_p4) (<= (+ v_b_151_1 2) v_b_155_1) (<= .cse0 v_b_154_1) (or (<= v_b_149_1 v_idx_94) (< v_idx_94 v_b_148_1) (= (select |c_#memory_int| v_idx_94) 0)) (<= .cse6 v_b_149_1) (or (= (select |c_#memory_int| v_idx_101) v_v_1457_1) (< v_idx_101 v_b_155_1)) (<= (+ v_b_150_1 2) v_b_154_1) (<= .cse7 v_b_150_1) (<= .cse7 v_b_149_1) (<= .cse5 c_ULTIMATE.start_main_p4) (<= .cse4 c_ULTIMATE.start_main_p4) (or (< v_idx_95 v_b_149_1) (<= v_b_150_1 v_idx_95) (= (select |c_#memory_int| v_idx_95) v_v_1451_1)) (or (= (select |c_#memory_int| v_idx_97) v_v_1453_1) (<= c_ULTIMATE.start_main_p4 v_idx_97) (< v_idx_97 v_b_151_1)) (<= v_b_155_1 .cse8) (or (<= c_ULTIMATE.start_main_p1 v_idx_91) (= (select |c_#memory_int| v_idx_91) v_v_1447_1)) (<= v_v_1454_1 0) (<= v_b_149_1 v_b_150_1) (<= v_b_149_1 .cse6) (or (< v_idx_92 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_92) (= (select |c_#memory_int| v_idx_92) 0)) (<= .cse6 v_b_150_1) (or (= (select |c_#memory_int| v_idx_98) v_v_1454_1) (<= .cse0 v_idx_98) (< v_idx_98 c_ULTIMATE.start_main_p4)) (<= (+ v_b_149_1 2) v_b_154_1) (<= v_b_151_1 .cse4) (or (= (select |c_#memory_int| v_idx_100) 0) (< v_idx_100 v_b_154_1) (<= v_b_155_1 v_idx_100)) (<= .cse3 c_ULTIMATE.start_main_p4) (<= (+ v_b_151_1 1) v_b_154_1) (<= (+ v_b_149_1 3) v_b_155_1) (<= (+ c_ULTIMATE.start_main_p4 2) v_b_155_1) (<= .cse8 v_b_155_1) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_155_1) (<= v_b_151_1 c_ULTIMATE.start_main_p4) (<= (+ v_b_150_1 3) v_b_155_1))))) is different from false [2019-01-11 11:43:00,272 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_104 Int) (v_idx_105 Int) (v_idx_102 Int) (v_idx_103 Int) (v_idx_108 Int) (v_idx_109 Int) (v_idx_106 Int) (v_idx_107 Int) (v_idx_111 Int) (v_idx_112 Int) (v_idx_110 Int)) (exists ((v_v_1451_1 Int) (v_v_1455_1 Int) (v_v_1454_1 Int) (v_v_1453_1 Int) (v_b_149_1 Int) (v_v_1447_1 Int) (v_v_1457_1 Int) (v_b_148_1 Int) (v_v_1449_1 Int) (v_b_153_1 Int) (v_b_152_1 Int) (v_b_151_1 Int) (v_b_150_1 Int) (v_b_155_1 Int) (v_b_154_1 Int)) (let ((.cse6 (+ c_ULTIMATE.start_main_p1 2)) (.cse4 (+ v_b_148_1 1)) (.cse7 (+ v_b_151_1 1)) (.cse8 (+ v_b_149_1 1)) (.cse2 (+ v_b_150_1 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ v_b_148_1 3)) (.cse10 (+ c_ULTIMATE.start_main_p1 3)) (.cse0 (+ c_ULTIMATE.start_main_p1 4)) (.cse1 (+ v_b_148_1 2)) (.cse5 (+ v_b_150_1 2)) (.cse11 (+ v_b_149_1 2)) (.cse13 (+ v_b_154_1 1)) (.cse12 (+ v_b_152_1 1))) (and (or (= (select |c_#memory_int| v_idx_105) 0) (<= v_b_149_1 v_idx_105) (< v_idx_105 v_b_148_1)) (<= .cse0 v_b_154_1) (<= .cse1 v_b_151_1) (<= .cse2 v_b_151_1) (or (= (select |c_#memory_int| v_idx_106) v_v_1451_1) (< v_idx_106 v_b_149_1) (<= v_b_150_1 v_idx_106)) (or (= (select |c_#memory_int| v_idx_112) v_v_1457_1) (< v_idx_112 v_b_155_1)) (<= .cse3 v_b_153_1) (<= .cse4 v_b_149_1) (<= .cse5 v_b_154_1) (<= .cse6 v_b_150_1) (<= (+ v_b_152_1 2) v_b_155_1) (<= .cse6 v_b_149_1) (<= .cse7 v_b_153_1) (or (= (select |c_#memory_int| v_idx_108) v_v_1453_1) (<= v_b_152_1 v_idx_108) (< v_idx_108 v_b_151_1)) (<= v_b_149_1 v_b_150_1) (<= v_b_149_1 .cse4) (<= .cse8 v_b_152_1) (or (= (select |c_#memory_int| v_idx_104) v_v_1449_1) (< v_idx_104 .cse9) (<= v_b_148_1 v_idx_104)) (<= .cse4 v_b_150_1) (<= .cse10 v_b_152_1) (<= v_b_151_1 .cse2) (<= .cse7 v_b_154_1) (<= (+ v_b_149_1 3) v_b_155_1) (<= .cse11 v_b_153_1) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_155_1) (<= (+ v_b_150_1 3) v_b_155_1) (<= .cse9 v_b_148_1) (<= .cse8 v_b_151_1) (<= .cse2 v_b_152_1) (or (= (select |c_#memory_int| v_idx_102) v_v_1447_1) (<= c_ULTIMATE.start_main_p1 v_idx_102)) (<= (+ v_b_148_1 4) v_b_155_1) (or (= (select |c_#memory_int| v_idx_103) 0) (< v_idx_103 c_ULTIMATE.start_main_p1) (<= .cse9 v_idx_103)) (<= (* 2 v_v_1454_1) 0) (<= .cse3 v_b_154_1) (<= .cse12 v_b_153_1) (<= .cse10 v_b_151_1) (or (< v_idx_107 v_b_150_1) (<= v_b_151_1 v_idx_107) (= (select |c_#memory_int| v_idx_107) 0)) (<= (+ v_b_151_1 2) v_b_155_1) (or (= 0 (select |c_#memory_int| v_idx_111)) (< v_idx_111 v_b_154_1) (<= v_b_155_1 v_idx_111)) (or (<= v_b_154_1 v_idx_110) (= (select |c_#memory_int| v_idx_110) v_v_1455_1) (< v_idx_110 v_b_153_1)) (<= .cse0 v_b_153_1) (<= v_b_151_1 v_b_152_1) (<= v_b_155_1 .cse13) (<= .cse12 v_b_154_1) (<= v_v_1454_1 0) (<= .cse1 v_b_152_1) (<= .cse5 v_b_153_1) (or (<= v_b_153_1 v_idx_109) (< v_idx_109 v_b_152_1) (= (select |c_#memory_int| v_idx_109) v_v_1454_1)) (<= .cse11 v_b_154_1) (<= .cse13 v_b_155_1) (<= v_b_153_1 v_b_154_1) (<= v_b_153_1 .cse12) (<= (+ v_b_153_1 1) v_b_155_1))))) is different from false [2019-01-11 11:43:00,578 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:43:00,579 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:43:00,579 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:43:00,580 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:43:00,580 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:43:00,581 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:43:00,582 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:43:00,582 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:43:00,583 INFO L87 Difference]: Start difference. First operand 12 states and 21 transitions. Second operand 4 states. [2019-01-11 11:43:02,950 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_98 Int) (v_idx_99 Int) (v_idx_96 Int) (v_idx_97 Int) (v_idx_94 Int) (v_idx_95 Int) (v_idx_92 Int) (v_idx_93 Int) (v_idx_100 Int) (v_idx_101 Int) (v_idx_91 Int)) (exists ((v_v_1451_1 Int) (v_v_1455_1 Int) (v_v_1454_1 Int) (v_v_1453_1 Int) (v_b_149_1 Int) (v_v_1447_1 Int) (v_v_1457_1 Int) (v_b_148_1 Int) (v_v_1449_1 Int) (v_b_151_1 Int) (v_b_150_1 Int) (v_b_155_1 Int) (v_b_154_1 Int)) (let ((.cse2 (+ v_b_149_1 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse5 (+ c_ULTIMATE.start_main_p1 3)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse6 (+ v_b_148_1 1)) (.cse0 (+ c_ULTIMATE.start_main_p4 1)) (.cse4 (+ v_b_150_1 1)) (.cse3 (+ v_b_148_1 2)) (.cse8 (+ v_b_154_1 1))) (and (or (= (select |c_#memory_int| v_idx_99) v_v_1455_1) (<= v_b_154_1 v_idx_99) (< v_idx_99 .cse0)) (<= .cse1 v_b_148_1) (<= .cse2 v_b_151_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_154_1) (<= .cse3 v_b_151_1) (or (< v_idx_96 v_b_150_1) (<= v_b_151_1 v_idx_96) (= (select |c_#memory_int| v_idx_96) 0)) (<= (+ v_b_148_1 4) v_b_155_1) (or (= (select |c_#memory_int| v_idx_93) v_v_1449_1) (< v_idx_93 .cse1) (<= v_b_148_1 v_idx_93)) (<= (* 2 v_v_1454_1) 0) (<= (+ v_b_148_1 3) v_b_154_1) (<= .cse4 v_b_151_1) (<= .cse5 v_b_151_1) (<= .cse2 c_ULTIMATE.start_main_p4) (<= (+ v_b_151_1 2) v_b_155_1) (<= .cse0 v_b_154_1) (or (<= v_b_149_1 v_idx_94) (< v_idx_94 v_b_148_1) (= (select |c_#memory_int| v_idx_94) 0)) (<= .cse6 v_b_149_1) (or (= (select |c_#memory_int| v_idx_101) v_v_1457_1) (< v_idx_101 v_b_155_1)) (<= (+ v_b_150_1 2) v_b_154_1) (<= .cse7 v_b_150_1) (<= .cse7 v_b_149_1) (<= .cse5 c_ULTIMATE.start_main_p4) (<= .cse4 c_ULTIMATE.start_main_p4) (or (< v_idx_95 v_b_149_1) (<= v_b_150_1 v_idx_95) (= (select |c_#memory_int| v_idx_95) v_v_1451_1)) (or (= (select |c_#memory_int| v_idx_97) v_v_1453_1) (<= c_ULTIMATE.start_main_p4 v_idx_97) (< v_idx_97 v_b_151_1)) (<= v_b_155_1 .cse8) (or (<= c_ULTIMATE.start_main_p1 v_idx_91) (= (select |c_#memory_int| v_idx_91) v_v_1447_1)) (<= v_v_1454_1 0) (<= v_b_149_1 v_b_150_1) (<= v_b_149_1 .cse6) (or (< v_idx_92 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_92) (= (select |c_#memory_int| v_idx_92) 0)) (<= .cse6 v_b_150_1) (or (= (select |c_#memory_int| v_idx_98) v_v_1454_1) (<= .cse0 v_idx_98) (< v_idx_98 c_ULTIMATE.start_main_p4)) (<= (+ v_b_149_1 2) v_b_154_1) (<= v_b_151_1 .cse4) (or (= (select |c_#memory_int| v_idx_100) 0) (< v_idx_100 v_b_154_1) (<= v_b_155_1 v_idx_100)) (<= .cse3 c_ULTIMATE.start_main_p4) (<= (+ v_b_151_1 1) v_b_154_1) (<= (+ v_b_149_1 3) v_b_155_1) (<= (+ c_ULTIMATE.start_main_p4 2) v_b_155_1) (<= .cse8 v_b_155_1) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_155_1) (<= v_b_151_1 c_ULTIMATE.start_main_p4) (<= (+ v_b_150_1 3) v_b_155_1))))) (forall ((v_idx_104 Int) (v_idx_105 Int) (v_idx_102 Int) (v_idx_103 Int) (v_idx_108 Int) (v_idx_109 Int) (v_idx_106 Int) (v_idx_107 Int) (v_idx_111 Int) (v_idx_112 Int) (v_idx_110 Int)) (exists ((v_v_1451_1 Int) (v_v_1455_1 Int) (v_v_1454_1 Int) (v_v_1453_1 Int) (v_b_149_1 Int) (v_v_1447_1 Int) (v_v_1457_1 Int) (v_b_148_1 Int) (v_v_1449_1 Int) (v_b_153_1 Int) (v_b_152_1 Int) (v_b_151_1 Int) (v_b_150_1 Int) (v_b_155_1 Int) (v_b_154_1 Int)) (let ((.cse15 (+ c_ULTIMATE.start_main_p1 2)) (.cse13 (+ v_b_148_1 1)) (.cse16 (+ v_b_151_1 1)) (.cse17 (+ v_b_149_1 1)) (.cse11 (+ v_b_150_1 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 1)) (.cse12 (+ v_b_148_1 3)) (.cse19 (+ c_ULTIMATE.start_main_p1 3)) (.cse9 (+ c_ULTIMATE.start_main_p1 4)) (.cse10 (+ v_b_148_1 2)) (.cse14 (+ v_b_150_1 2)) (.cse20 (+ v_b_149_1 2)) (.cse22 (+ v_b_154_1 1)) (.cse21 (+ v_b_152_1 1))) (and (or (= (select |c_#memory_int| v_idx_105) 0) (<= v_b_149_1 v_idx_105) (< v_idx_105 v_b_148_1)) (<= .cse9 v_b_154_1) (<= .cse10 v_b_151_1) (<= .cse11 v_b_151_1) (or (= (select |c_#memory_int| v_idx_106) v_v_1451_1) (< v_idx_106 v_b_149_1) (<= v_b_150_1 v_idx_106)) (or (= (select |c_#memory_int| v_idx_112) v_v_1457_1) (< v_idx_112 v_b_155_1)) (<= .cse12 v_b_153_1) (<= .cse13 v_b_149_1) (<= .cse14 v_b_154_1) (<= .cse15 v_b_150_1) (<= (+ v_b_152_1 2) v_b_155_1) (<= .cse15 v_b_149_1) (<= .cse16 v_b_153_1) (or (= (select |c_#memory_int| v_idx_108) v_v_1453_1) (<= v_b_152_1 v_idx_108) (< v_idx_108 v_b_151_1)) (<= v_b_149_1 v_b_150_1) (<= v_b_149_1 .cse13) (<= .cse17 v_b_152_1) (or (= (select |c_#memory_int| v_idx_104) v_v_1449_1) (< v_idx_104 .cse18) (<= v_b_148_1 v_idx_104)) (<= .cse13 v_b_150_1) (<= .cse19 v_b_152_1) (<= v_b_151_1 .cse11) (<= .cse16 v_b_154_1) (<= (+ v_b_149_1 3) v_b_155_1) (<= .cse20 v_b_153_1) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_155_1) (<= (+ v_b_150_1 3) v_b_155_1) (<= .cse18 v_b_148_1) (<= .cse17 v_b_151_1) (<= .cse11 v_b_152_1) (or (= (select |c_#memory_int| v_idx_102) v_v_1447_1) (<= c_ULTIMATE.start_main_p1 v_idx_102)) (<= (+ v_b_148_1 4) v_b_155_1) (or (= (select |c_#memory_int| v_idx_103) 0) (< v_idx_103 c_ULTIMATE.start_main_p1) (<= .cse18 v_idx_103)) (<= (* 2 v_v_1454_1) 0) (<= .cse12 v_b_154_1) (<= .cse21 v_b_153_1) (<= .cse19 v_b_151_1) (or (< v_idx_107 v_b_150_1) (<= v_b_151_1 v_idx_107) (= (select |c_#memory_int| v_idx_107) 0)) (<= (+ v_b_151_1 2) v_b_155_1) (or (= 0 (select |c_#memory_int| v_idx_111)) (< v_idx_111 v_b_154_1) (<= v_b_155_1 v_idx_111)) (or (<= v_b_154_1 v_idx_110) (= (select |c_#memory_int| v_idx_110) v_v_1455_1) (< v_idx_110 v_b_153_1)) (<= .cse9 v_b_153_1) (<= v_b_151_1 v_b_152_1) (<= v_b_155_1 .cse22) (<= .cse21 v_b_154_1) (<= v_v_1454_1 0) (<= .cse10 v_b_152_1) (<= .cse14 v_b_153_1) (or (<= v_b_153_1 v_idx_109) (< v_idx_109 v_b_152_1) (= (select |c_#memory_int| v_idx_109) v_v_1454_1)) (<= .cse20 v_b_154_1) (<= .cse22 v_b_155_1) (<= v_b_153_1 v_b_154_1) (<= v_b_153_1 .cse21) (<= (+ v_b_153_1 1) v_b_155_1)))))) is different from false [2019-01-11 11:43:36,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:43:36,262 INFO L93 Difference]: Finished difference Result 14 states and 28 transitions. [2019-01-11 11:43:36,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:43:36,263 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:43:36,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:43:36,264 INFO L225 Difference]: With dead ends: 14 [2019-01-11 11:43:36,264 INFO L226 Difference]: Without dead ends: 13 [2019-01-11 11:43:36,265 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.6s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:43:36,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2019-01-11 11:43:36,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2019-01-11 11:43:36,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2019-01-11 11:43:36,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 27 transitions. [2019-01-11 11:43:36,271 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 27 transitions. Word has length 3 [2019-01-11 11:43:36,271 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:43:36,272 INFO L480 AbstractCegarLoop]: Abstraction has 13 states and 27 transitions. [2019-01-11 11:43:36,272 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:43:36,272 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 27 transitions. [2019-01-11 11:43:36,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:43:36,272 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:43:36,273 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:43:36,273 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:43:36,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:43:36,274 INFO L82 PathProgramCache]: Analyzing trace with hash 30434, now seen corresponding path program 1 times [2019-01-11 11:43:36,274 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:43:36,275 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:43:36,275 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:43:36,275 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:43:36,275 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:43:36,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:43:36,461 WARN L181 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 19 DAG size of output: 13 [2019-01-11 11:43:36,474 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:43:36,474 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:43:36,475 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:43:36,475 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:43:36,475 INFO L207 CegarAbsIntRunner]: [0], [20], [23] [2019-01-11 11:43:36,482 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:43:36,482 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:43:43,450 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:43:43,450 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:43:43,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:43:43,451 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:43:44,123 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 72.22% of their original sizes. [2019-01-11 11:43:44,124 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:43:46,684 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_203 Int) (v_idx_204 Int) (v_idx_212 Int) (v_idx_213 Int) (v_idx_207 Int) (v_idx_208 Int) (v_idx_205 Int) (v_idx_206 Int) (v_idx_209 Int) (v_idx_210 Int) (v_idx_211 Int)) (exists ((v_b_148_2 Int) (v_b_149_2 Int) (v_b_152_2 Int) (v_b_151_2 Int) (v_b_150_2 Int) (v_v_1259_2 Int) (v_b_153_2 Int) (v_v_1257_2 Int) (v_v_1267_2 Int) (v_v_1266_2 Int) (v_v_1265_2 Int) (v_v_1263_2 Int) (v_v_1261_2 Int)) (let ((.cse6 (+ c_ULTIMATE.start_main_p1 2)) (.cse8 (+ c_ULTIMATE.start_main_p1 3)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse5 (+ v_b_150_2 1)) (.cse11 (+ v_b_150_2 2)) (.cse3 (+ v_b_149_2 2)) (.cse12 (+ c_ULTIMATE.start_main_p1 4)) (.cse7 (+ v_b_148_2 2)) (.cse4 (+ v_b_148_2 3)) (.cse10 (+ c_ULTIMATE.start_main_p5 1)) (.cse9 (+ v_b_149_2 1)) (.cse0 (+ v_b_148_2 1)) (.cse2 (+ v_b_152_2 1)) (.cse13 (+ v_b_151_2 1))) (and (<= v_b_149_2 .cse0) (<= v_b_153_2 c_ULTIMATE.start_main_p5) (<= 0 v_v_1266_2) (<= .cse1 v_b_148_2) (<= .cse2 v_b_153_2) (or (< v_idx_206 v_b_148_2) (<= v_b_149_2 v_idx_206) (= 0 (select |c_#memory_int| v_idx_206))) (<= .cse0 v_b_150_2) (<= .cse3 v_b_153_2) (<= .cse4 v_b_153_2) (<= .cse5 v_b_151_2) (<= .cse6 v_b_150_2) (or (= (select |c_#memory_int| v_idx_207) v_v_1261_2) (< v_idx_207 v_b_149_2) (<= v_b_150_2 v_idx_207)) (<= .cse7 v_b_152_2) (or (<= v_b_152_2 v_idx_209) (= (select |c_#memory_int| v_idx_209) v_v_1263_2) (< v_idx_209 v_b_151_2)) (<= .cse6 v_b_149_2) (<= .cse8 v_b_151_2) (or (< v_idx_211 v_b_153_2) (<= c_ULTIMATE.start_main_p5 v_idx_211) (= (select |c_#memory_int| v_idx_211) v_v_1265_2)) (or (= 0 (select |c_#memory_int| v_idx_208)) (<= v_b_151_2 v_idx_208) (< v_idx_208 v_b_150_2)) (<= .cse5 v_b_152_2) (or (<= .cse1 v_idx_204) (= (select |c_#memory_int| v_idx_204) 0) (< v_idx_204 c_ULTIMATE.start_main_p1)) (<= .cse9 v_b_152_2) (<= .cse8 v_b_152_2) (or (< v_idx_205 .cse1) (<= v_b_148_2 v_idx_205) (= (select |c_#memory_int| v_idx_205) v_v_1259_2)) (<= v_b_151_2 .cse5) (or (< v_idx_213 .cse10) (= (select |c_#memory_int| v_idx_213) v_v_1267_2)) (<= .cse11 c_ULTIMATE.start_main_p5) (<= .cse11 v_b_153_2) (<= 0 (* 2 v_v_1266_2)) (or (< v_idx_210 v_b_152_2) (<= v_b_153_2 v_idx_210) (= 0 (select |c_#memory_int| v_idx_210))) (<= .cse3 c_ULTIMATE.start_main_p5) (<= .cse12 c_ULTIMATE.start_main_p5) (<= .cse12 v_b_153_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_203) (= (select |c_#memory_int| v_idx_203) v_v_1257_2)) (<= .cse7 v_b_151_2) (<= .cse13 v_b_153_2) (<= v_b_149_2 v_b_150_2) (<= .cse4 c_ULTIMATE.start_main_p5) (<= .cse2 c_ULTIMATE.start_main_p5) (<= v_b_151_2 v_b_152_2) (or (< v_idx_212 c_ULTIMATE.start_main_p5) (= (select |c_#memory_int| v_idx_212) v_v_1266_2) (<= .cse10 v_idx_212)) (<= .cse9 v_b_151_2) (<= .cse0 v_b_149_2) (<= v_b_153_2 .cse2) (<= .cse13 c_ULTIMATE.start_main_p5))))) is different from false [2019-01-11 11:43:50,624 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_214 Int) (v_idx_215 Int) (v_idx_223 Int) (v_idx_224 Int) (v_idx_218 Int) (v_idx_219 Int) (v_idx_216 Int) (v_idx_217 Int) (v_idx_221 Int) (v_idx_222 Int) (v_idx_220 Int)) (exists ((v_b_148_2 Int) (v_b_149_2 Int) (v_b_152_2 Int) (v_b_151_2 Int) (v_b_150_2 Int) (v_b_155_2 Int) (v_v_1259_2 Int) (v_b_154_2 Int) (v_b_153_2 Int) (v_v_1257_2 Int) (v_v_1267_2 Int) (v_v_1266_2 Int) (v_v_1265_2 Int) (v_v_1263_2 Int) (v_v_1261_2 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 2)) (.cse1 (+ v_b_148_2 1)) (.cse8 (+ v_b_148_2 3)) (.cse11 (+ v_b_149_2 2)) (.cse6 (+ v_b_148_2 2)) (.cse0 (+ v_b_152_2 1)) (.cse2 (+ v_b_150_2 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 3)) (.cse9 (+ c_ULTIMATE.start_main_p1 1)) (.cse12 (+ c_ULTIMATE.start_main_p1 4)) (.cse10 (+ v_b_154_2 1)) (.cse13 (+ v_b_150_2 2)) (.cse5 (+ v_b_149_2 1)) (.cse7 (+ v_b_151_2 1))) (and (or (<= v_b_152_2 v_idx_220) (< v_idx_220 v_b_151_2) (= (select |c_#memory_int| v_idx_220) v_v_1263_2)) (<= .cse0 v_b_153_2) (<= .cse1 v_b_150_2) (or (< v_idx_221 v_b_152_2) (<= v_b_153_2 v_idx_221) (= 0 (select |c_#memory_int| v_idx_221))) (<= .cse2 v_b_151_2) (<= .cse3 v_b_150_2) (<= (+ v_b_149_2 3) v_b_155_2) (or (= (select |c_#memory_int| v_idx_224) v_v_1267_2) (< v_idx_224 v_b_155_2)) (<= .cse3 v_b_149_2) (<= .cse4 v_b_151_2) (<= v_b_153_2 v_b_154_2) (or (= (select |c_#memory_int| v_idx_223) v_v_1266_2) (<= v_b_155_2 v_idx_223) (< v_idx_223 v_b_154_2)) (<= .cse5 v_b_152_2) (<= v_b_151_2 .cse2) (<= (+ v_b_148_2 4) v_b_155_2) (<= 0 (* 2 v_v_1266_2)) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_155_2) (or (< v_idx_219 v_b_150_2) (= 0 (select |c_#memory_int| v_idx_219)) (<= v_b_151_2 v_idx_219)) (<= .cse6 v_b_151_2) (<= .cse7 v_b_153_2) (<= .cse8 v_b_154_2) (<= .cse1 v_b_149_2) (<= v_b_153_2 .cse0) (or (< v_idx_218 v_b_149_2) (= (select |c_#memory_int| v_idx_218) v_v_1261_2) (<= v_b_150_2 v_idx_218)) (<= v_b_149_2 .cse1) (<= 0 v_v_1266_2) (<= .cse9 v_b_148_2) (<= .cse10 v_b_155_2) (<= (+ v_b_153_2 1) v_b_155_2) (<= .cse11 v_b_153_2) (or (= 0 (select |c_#memory_int| v_idx_217)) (<= v_b_149_2 v_idx_217) (< v_idx_217 v_b_148_2)) (<= .cse8 v_b_153_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_214) (= (select |c_#memory_int| v_idx_214) v_v_1257_2)) (<= (+ v_b_150_2 3) v_b_155_2) (<= .cse11 v_b_154_2) (or (< v_idx_216 .cse9) (= (select |c_#memory_int| v_idx_216) v_v_1259_2) (<= v_b_148_2 v_idx_216)) (<= .cse6 v_b_152_2) (<= (+ v_b_151_2 2) v_b_155_2) (<= .cse0 v_b_154_2) (or (< v_idx_222 v_b_153_2) (= (select |c_#memory_int| v_idx_222) v_v_1265_2) (<= v_b_154_2 v_idx_222)) (<= .cse2 v_b_152_2) (<= .cse12 v_b_154_2) (<= .cse4 v_b_152_2) (or (<= .cse9 v_idx_215) (= 0 (select |c_#memory_int| v_idx_215)) (< v_idx_215 c_ULTIMATE.start_main_p1)) (<= (+ v_b_152_2 2) v_b_155_2) (<= .cse13 v_b_153_2) (<= .cse12 v_b_153_2) (<= v_b_155_2 .cse10) (<= v_b_149_2 v_b_150_2) (<= .cse13 v_b_154_2) (<= v_b_151_2 v_b_152_2) (<= .cse5 v_b_151_2) (<= .cse7 v_b_154_2))))) is different from false [2019-01-11 11:43:50,884 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:43:50,884 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:43:50,885 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:43:50,885 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:43:50,885 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:43:50,886 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:43:50,886 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:43:50,886 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:43:50,887 INFO L87 Difference]: Start difference. First operand 13 states and 27 transitions. Second operand 4 states. [2019-01-11 11:43:53,633 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_203 Int) (v_idx_204 Int) (v_idx_212 Int) (v_idx_213 Int) (v_idx_207 Int) (v_idx_208 Int) (v_idx_205 Int) (v_idx_206 Int) (v_idx_209 Int) (v_idx_210 Int) (v_idx_211 Int)) (exists ((v_b_148_2 Int) (v_b_149_2 Int) (v_b_152_2 Int) (v_b_151_2 Int) (v_b_150_2 Int) (v_v_1259_2 Int) (v_b_153_2 Int) (v_v_1257_2 Int) (v_v_1267_2 Int) (v_v_1266_2 Int) (v_v_1265_2 Int) (v_v_1263_2 Int) (v_v_1261_2 Int)) (let ((.cse6 (+ c_ULTIMATE.start_main_p1 2)) (.cse8 (+ c_ULTIMATE.start_main_p1 3)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse5 (+ v_b_150_2 1)) (.cse11 (+ v_b_150_2 2)) (.cse3 (+ v_b_149_2 2)) (.cse12 (+ c_ULTIMATE.start_main_p1 4)) (.cse7 (+ v_b_148_2 2)) (.cse4 (+ v_b_148_2 3)) (.cse10 (+ c_ULTIMATE.start_main_p5 1)) (.cse9 (+ v_b_149_2 1)) (.cse0 (+ v_b_148_2 1)) (.cse2 (+ v_b_152_2 1)) (.cse13 (+ v_b_151_2 1))) (and (<= v_b_149_2 .cse0) (<= v_b_153_2 c_ULTIMATE.start_main_p5) (<= 0 v_v_1266_2) (<= .cse1 v_b_148_2) (<= .cse2 v_b_153_2) (or (< v_idx_206 v_b_148_2) (<= v_b_149_2 v_idx_206) (= 0 (select |c_#memory_int| v_idx_206))) (<= .cse0 v_b_150_2) (<= .cse3 v_b_153_2) (<= .cse4 v_b_153_2) (<= .cse5 v_b_151_2) (<= .cse6 v_b_150_2) (or (= (select |c_#memory_int| v_idx_207) v_v_1261_2) (< v_idx_207 v_b_149_2) (<= v_b_150_2 v_idx_207)) (<= .cse7 v_b_152_2) (or (<= v_b_152_2 v_idx_209) (= (select |c_#memory_int| v_idx_209) v_v_1263_2) (< v_idx_209 v_b_151_2)) (<= .cse6 v_b_149_2) (<= .cse8 v_b_151_2) (or (< v_idx_211 v_b_153_2) (<= c_ULTIMATE.start_main_p5 v_idx_211) (= (select |c_#memory_int| v_idx_211) v_v_1265_2)) (or (= 0 (select |c_#memory_int| v_idx_208)) (<= v_b_151_2 v_idx_208) (< v_idx_208 v_b_150_2)) (<= .cse5 v_b_152_2) (or (<= .cse1 v_idx_204) (= (select |c_#memory_int| v_idx_204) 0) (< v_idx_204 c_ULTIMATE.start_main_p1)) (<= .cse9 v_b_152_2) (<= .cse8 v_b_152_2) (or (< v_idx_205 .cse1) (<= v_b_148_2 v_idx_205) (= (select |c_#memory_int| v_idx_205) v_v_1259_2)) (<= v_b_151_2 .cse5) (or (< v_idx_213 .cse10) (= (select |c_#memory_int| v_idx_213) v_v_1267_2)) (<= .cse11 c_ULTIMATE.start_main_p5) (<= .cse11 v_b_153_2) (<= 0 (* 2 v_v_1266_2)) (or (< v_idx_210 v_b_152_2) (<= v_b_153_2 v_idx_210) (= 0 (select |c_#memory_int| v_idx_210))) (<= .cse3 c_ULTIMATE.start_main_p5) (<= .cse12 c_ULTIMATE.start_main_p5) (<= .cse12 v_b_153_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_203) (= (select |c_#memory_int| v_idx_203) v_v_1257_2)) (<= .cse7 v_b_151_2) (<= .cse13 v_b_153_2) (<= v_b_149_2 v_b_150_2) (<= .cse4 c_ULTIMATE.start_main_p5) (<= .cse2 c_ULTIMATE.start_main_p5) (<= v_b_151_2 v_b_152_2) (or (< v_idx_212 c_ULTIMATE.start_main_p5) (= (select |c_#memory_int| v_idx_212) v_v_1266_2) (<= .cse10 v_idx_212)) (<= .cse9 v_b_151_2) (<= .cse0 v_b_149_2) (<= v_b_153_2 .cse2) (<= .cse13 c_ULTIMATE.start_main_p5))))) (forall ((v_idx_214 Int) (v_idx_215 Int) (v_idx_223 Int) (v_idx_224 Int) (v_idx_218 Int) (v_idx_219 Int) (v_idx_216 Int) (v_idx_217 Int) (v_idx_221 Int) (v_idx_222 Int) (v_idx_220 Int)) (exists ((v_b_148_2 Int) (v_b_149_2 Int) (v_b_152_2 Int) (v_b_151_2 Int) (v_b_150_2 Int) (v_b_155_2 Int) (v_v_1259_2 Int) (v_b_154_2 Int) (v_b_153_2 Int) (v_v_1257_2 Int) (v_v_1267_2 Int) (v_v_1266_2 Int) (v_v_1265_2 Int) (v_v_1263_2 Int) (v_v_1261_2 Int)) (let ((.cse17 (+ c_ULTIMATE.start_main_p1 2)) (.cse15 (+ v_b_148_2 1)) (.cse22 (+ v_b_148_2 3)) (.cse25 (+ v_b_149_2 2)) (.cse20 (+ v_b_148_2 2)) (.cse14 (+ v_b_152_2 1)) (.cse16 (+ v_b_150_2 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 3)) (.cse23 (+ c_ULTIMATE.start_main_p1 1)) (.cse26 (+ c_ULTIMATE.start_main_p1 4)) (.cse24 (+ v_b_154_2 1)) (.cse27 (+ v_b_150_2 2)) (.cse19 (+ v_b_149_2 1)) (.cse21 (+ v_b_151_2 1))) (and (or (<= v_b_152_2 v_idx_220) (< v_idx_220 v_b_151_2) (= (select |c_#memory_int| v_idx_220) v_v_1263_2)) (<= .cse14 v_b_153_2) (<= .cse15 v_b_150_2) (or (< v_idx_221 v_b_152_2) (<= v_b_153_2 v_idx_221) (= 0 (select |c_#memory_int| v_idx_221))) (<= .cse16 v_b_151_2) (<= .cse17 v_b_150_2) (<= (+ v_b_149_2 3) v_b_155_2) (or (= (select |c_#memory_int| v_idx_224) v_v_1267_2) (< v_idx_224 v_b_155_2)) (<= .cse17 v_b_149_2) (<= .cse18 v_b_151_2) (<= v_b_153_2 v_b_154_2) (or (= (select |c_#memory_int| v_idx_223) v_v_1266_2) (<= v_b_155_2 v_idx_223) (< v_idx_223 v_b_154_2)) (<= .cse19 v_b_152_2) (<= v_b_151_2 .cse16) (<= (+ v_b_148_2 4) v_b_155_2) (<= 0 (* 2 v_v_1266_2)) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_155_2) (or (< v_idx_219 v_b_150_2) (= 0 (select |c_#memory_int| v_idx_219)) (<= v_b_151_2 v_idx_219)) (<= .cse20 v_b_151_2) (<= .cse21 v_b_153_2) (<= .cse22 v_b_154_2) (<= .cse15 v_b_149_2) (<= v_b_153_2 .cse14) (or (< v_idx_218 v_b_149_2) (= (select |c_#memory_int| v_idx_218) v_v_1261_2) (<= v_b_150_2 v_idx_218)) (<= v_b_149_2 .cse15) (<= 0 v_v_1266_2) (<= .cse23 v_b_148_2) (<= .cse24 v_b_155_2) (<= (+ v_b_153_2 1) v_b_155_2) (<= .cse25 v_b_153_2) (or (= 0 (select |c_#memory_int| v_idx_217)) (<= v_b_149_2 v_idx_217) (< v_idx_217 v_b_148_2)) (<= .cse22 v_b_153_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_214) (= (select |c_#memory_int| v_idx_214) v_v_1257_2)) (<= (+ v_b_150_2 3) v_b_155_2) (<= .cse25 v_b_154_2) (or (< v_idx_216 .cse23) (= (select |c_#memory_int| v_idx_216) v_v_1259_2) (<= v_b_148_2 v_idx_216)) (<= .cse20 v_b_152_2) (<= (+ v_b_151_2 2) v_b_155_2) (<= .cse14 v_b_154_2) (or (< v_idx_222 v_b_153_2) (= (select |c_#memory_int| v_idx_222) v_v_1265_2) (<= v_b_154_2 v_idx_222)) (<= .cse16 v_b_152_2) (<= .cse26 v_b_154_2) (<= .cse18 v_b_152_2) (or (<= .cse23 v_idx_215) (= 0 (select |c_#memory_int| v_idx_215)) (< v_idx_215 c_ULTIMATE.start_main_p1)) (<= (+ v_b_152_2 2) v_b_155_2) (<= .cse27 v_b_153_2) (<= .cse26 v_b_153_2) (<= v_b_155_2 .cse24) (<= v_b_149_2 v_b_150_2) (<= .cse27 v_b_154_2) (<= v_b_151_2 v_b_152_2) (<= .cse19 v_b_151_2) (<= .cse21 v_b_154_2)))))) is different from false [2019-01-11 11:44:11,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:44:11,604 INFO L93 Difference]: Finished difference Result 15 states and 34 transitions. [2019-01-11 11:44:11,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:44:11,604 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:44:11,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:44:11,605 INFO L225 Difference]: With dead ends: 15 [2019-01-11 11:44:11,605 INFO L226 Difference]: Without dead ends: 14 [2019-01-11 11:44:11,606 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 9.3s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:44:11,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states. [2019-01-11 11:44:11,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 13. [2019-01-11 11:44:11,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2019-01-11 11:44:11,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 27 transitions. [2019-01-11 11:44:11,617 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 27 transitions. Word has length 3 [2019-01-11 11:44:11,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:44:11,617 INFO L480 AbstractCegarLoop]: Abstraction has 13 states and 27 transitions. [2019-01-11 11:44:11,617 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:44:11,618 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 27 transitions. [2019-01-11 11:44:11,618 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:44:11,618 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:44:11,618 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:44:11,619 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:44:11,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:11,619 INFO L82 PathProgramCache]: Analyzing trace with hash 30000, now seen corresponding path program 1 times [2019-01-11 11:44:11,619 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:44:11,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:11,620 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:44:11,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:11,621 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:44:11,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:44:11,727 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:44:11,727 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:44:11,728 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:44:11,728 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:44:11,728 INFO L207 CegarAbsIntRunner]: [0], [6], [23] [2019-01-11 11:44:11,731 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:44:11,731 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:44:19,170 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:44:19,170 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:44:19,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:19,171 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:44:19,526 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 77.78% of their original sizes. [2019-01-11 11:44:19,526 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:44:21,842 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_324 Int) (v_idx_325 Int) (v_idx_322 Int) (v_idx_323 Int) (v_idx_317 Int) (v_idx_318 Int) (v_idx_315 Int) (v_idx_316 Int) (v_idx_319 Int) (v_idx_320 Int) (v_idx_321 Int)) (exists ((v_v_1453_3 Int) (v_v_1451_3 Int) (v_v_1457_3 Int) (v_b_148_3 Int) (v_v_1455_3 Int) (v_v_1449_3 Int) (v_b_149_3 Int) (v_v_1447_3 Int) (v_v_1448_3 Int) (v_b_151_3 Int) (v_b_150_3 Int) (v_b_155_3 Int) (v_b_154_3 Int) (v_b_153_3 Int) (v_b_152_3 Int)) (let ((.cse2 (+ c_ULTIMATE.start_main_p1 4)) (.cse3 (+ c_ULTIMATE.start_main_p1 3)) (.cse7 (+ v_b_148_3 2)) (.cse1 (+ v_b_150_3 2)) (.cse5 (+ v_b_148_3 3)) (.cse0 (+ c_ULTIMATE.start_main_p1 2)) (.cse9 (+ v_b_149_3 1)) (.cse8 (+ v_b_151_3 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse11 (+ v_b_152_3 1)) (.cse13 (+ v_b_149_3 2)) (.cse12 (+ v_b_148_3 1)) (.cse10 (+ v_b_150_3 1)) (.cse6 (+ v_b_154_3 1))) (and (<= (+ v_b_148_3 4) v_b_155_3) (<= .cse0 v_b_149_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_315) (= (select |c_#memory_int| v_idx_315) v_v_1447_3)) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_155_3) (<= .cse1 v_b_154_3) (<= .cse2 v_b_153_3) (<= .cse3 v_b_152_3) (<= 0 (* 2 v_v_1448_3)) (or (<= v_b_148_3 v_idx_317) (= (select |c_#memory_int| v_idx_317) v_v_1449_3) (< v_idx_317 .cse4)) (or (= (select |c_#memory_int| v_idx_325) v_v_1457_3) (< v_idx_325 v_b_155_3)) (<= .cse2 v_b_154_3) (or (< v_idx_318 v_b_148_3) (<= v_b_149_3 v_idx_318) (= (select |c_#memory_int| v_idx_318) 0)) (<= v_b_153_3 v_b_154_3) (<= .cse5 v_b_154_3) (or (< v_idx_316 c_ULTIMATE.start_main_p1) (<= .cse4 v_idx_316) (= (select |c_#memory_int| v_idx_316) v_v_1448_3)) (<= .cse3 v_b_151_3) (<= .cse6 v_b_155_3) (<= .cse7 v_b_151_3) (<= .cse8 v_b_153_3) (<= .cse9 v_b_151_3) (<= .cse10 v_b_152_3) (<= v_b_153_3 .cse11) (<= (+ v_b_150_3 3) v_b_155_3) (<= (+ v_b_153_3 1) v_b_155_3) (<= .cse12 v_b_150_3) (<= .cse7 v_b_152_3) (<= v_b_149_3 .cse12) (or (<= v_b_153_3 v_idx_322) (< v_idx_322 v_b_152_3) (= 0 (select |c_#memory_int| v_idx_322))) (<= .cse1 v_b_153_3) (<= .cse13 v_b_154_3) (<= .cse5 v_b_153_3) (<= .cse10 v_b_151_3) (<= .cse0 v_b_150_3) (<= .cse9 v_b_152_3) (<= v_b_151_3 v_b_152_3) (<= .cse11 v_b_153_3) (<= v_b_149_3 v_b_150_3) (<= .cse8 v_b_154_3) (<= .cse4 v_b_148_3) (<= .cse11 v_b_154_3) (<= (+ v_b_151_3 2) v_b_155_3) (<= .cse13 v_b_153_3) (or (<= v_b_154_3 v_idx_323) (= (select |c_#memory_int| v_idx_323) v_v_1455_3) (< v_idx_323 v_b_153_3)) (or (= 0 (select |c_#memory_int| v_idx_324)) (<= v_b_155_3 v_idx_324) (< v_idx_324 v_b_154_3)) (<= .cse12 v_b_149_3) (<= v_b_151_3 .cse10) (<= (+ v_b_152_3 2) v_b_155_3) (<= (+ v_b_149_3 3) v_b_155_3) (<= 0 v_v_1448_3) (or (< v_idx_320 v_b_150_3) (<= v_b_151_3 v_idx_320) (= (select |c_#memory_int| v_idx_320) 0)) (or (< v_idx_321 v_b_151_3) (<= v_b_152_3 v_idx_321) (= (select |c_#memory_int| v_idx_321) v_v_1453_3)) (or (< v_idx_319 v_b_149_3) (<= v_b_150_3 v_idx_319) (= (select |c_#memory_int| v_idx_319) v_v_1451_3)) (<= v_b_155_3 .cse6))))) is different from false [2019-01-11 11:44:24,959 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_335 Int) (v_idx_336 Int) (v_idx_333 Int) (v_idx_334 Int) (v_idx_328 Int) (v_idx_329 Int) (v_idx_326 Int) (v_idx_327 Int) (v_idx_331 Int) (v_idx_332 Int) (v_idx_330 Int)) (exists ((v_v_1453_3 Int) (v_v_1451_3 Int) (v_v_1457_3 Int) (v_b_148_3 Int) (v_v_1455_3 Int) (v_v_1449_3 Int) (v_b_149_3 Int) (v_v_1447_3 Int) (v_v_1448_3 Int) (v_b_151_3 Int) (v_b_150_3 Int) (v_b_155_3 Int) (v_b_154_3 Int) (v_b_153_3 Int) (v_b_152_3 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse4 (+ c_ULTIMATE.start_main_p1 3)) (.cse7 (+ v_b_148_3 2)) (.cse2 (+ v_b_150_3 2)) (.cse5 (+ v_b_148_3 3)) (.cse0 (+ c_ULTIMATE.start_main_p1 2)) (.cse9 (+ v_b_149_3 1)) (.cse8 (+ v_b_151_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse11 (+ v_b_152_3 1)) (.cse13 (+ v_b_149_3 2)) (.cse12 (+ v_b_148_3 1)) (.cse10 (+ v_b_150_3 1)) (.cse6 (+ v_b_154_3 1))) (and (<= (+ v_b_148_3 4) v_b_155_3) (<= .cse0 v_b_149_3) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_155_3) (or (< v_idx_327 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_327) (= (select |c_#memory_int| v_idx_327) v_v_1448_3)) (<= .cse2 v_b_154_3) (<= .cse3 v_b_153_3) (<= .cse4 v_b_152_3) (<= 0 (* 2 v_v_1448_3)) (<= .cse3 v_b_154_3) (<= v_b_153_3 v_b_154_3) (<= .cse5 v_b_154_3) (<= .cse4 v_b_151_3) (<= .cse6 v_b_155_3) (<= .cse7 v_b_151_3) (<= .cse8 v_b_153_3) (or (= (select |c_#memory_int| v_idx_326) v_v_1447_3) (<= c_ULTIMATE.start_main_p1 v_idx_326)) (<= .cse9 v_b_151_3) (<= .cse10 v_b_152_3) (or (= (select |c_#memory_int| v_idx_336) v_v_1457_3) (< v_idx_336 v_b_155_3)) (or (<= v_b_154_3 v_idx_334) (= (select |c_#memory_int| v_idx_334) v_v_1455_3) (< v_idx_334 v_b_153_3)) (<= v_b_153_3 .cse11) (<= (+ v_b_150_3 3) v_b_155_3) (or (<= v_b_150_3 v_idx_330) (< v_idx_330 v_b_149_3) (= (select |c_#memory_int| v_idx_330) v_v_1451_3)) (or (<= v_b_155_3 v_idx_335) (< v_idx_335 v_b_154_3) (= 0 (select |c_#memory_int| v_idx_335))) (<= (+ v_b_153_3 1) v_b_155_3) (<= .cse12 v_b_150_3) (<= .cse7 v_b_152_3) (<= v_b_149_3 .cse12) (<= .cse2 v_b_153_3) (<= .cse13 v_b_154_3) (<= .cse5 v_b_153_3) (<= .cse10 v_b_151_3) (<= .cse0 v_b_150_3) (<= .cse9 v_b_152_3) (<= v_b_151_3 v_b_152_3) (or (= 0 (select |c_#memory_int| v_idx_329)) (< v_idx_329 v_b_148_3) (<= v_b_149_3 v_idx_329)) (<= .cse11 v_b_153_3) (or (< v_idx_328 .cse1) (<= v_b_148_3 v_idx_328) (= (select |c_#memory_int| v_idx_328) v_v_1449_3)) (<= v_b_149_3 v_b_150_3) (<= .cse8 v_b_154_3) (<= .cse1 v_b_148_3) (or (<= v_b_153_3 v_idx_333) (= 0 (select |c_#memory_int| v_idx_333)) (< v_idx_333 v_b_152_3)) (<= .cse11 v_b_154_3) (<= (+ v_b_151_3 2) v_b_155_3) (or (<= v_b_152_3 v_idx_332) (< v_idx_332 v_b_151_3) (= (select |c_#memory_int| v_idx_332) v_v_1453_3)) (<= .cse13 v_b_153_3) (<= .cse12 v_b_149_3) (<= v_b_151_3 .cse10) (<= (+ v_b_152_3 2) v_b_155_3) (<= (+ v_b_149_3 3) v_b_155_3) (<= 0 v_v_1448_3) (or (< v_idx_331 v_b_150_3) (<= v_b_151_3 v_idx_331) (= 0 (select |c_#memory_int| v_idx_331))) (<= v_b_155_3 .cse6))))) is different from false [2019-01-11 11:44:25,078 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:44:25,078 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:44:25,079 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:44:25,079 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:44:25,079 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:44:25,079 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:44:25,079 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:44:25,080 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:44:25,080 INFO L87 Difference]: Start difference. First operand 13 states and 27 transitions. Second operand 4 states. [2019-01-11 11:44:27,719 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_335 Int) (v_idx_336 Int) (v_idx_333 Int) (v_idx_334 Int) (v_idx_328 Int) (v_idx_329 Int) (v_idx_326 Int) (v_idx_327 Int) (v_idx_331 Int) (v_idx_332 Int) (v_idx_330 Int)) (exists ((v_v_1453_3 Int) (v_v_1451_3 Int) (v_v_1457_3 Int) (v_b_148_3 Int) (v_v_1455_3 Int) (v_v_1449_3 Int) (v_b_149_3 Int) (v_v_1447_3 Int) (v_v_1448_3 Int) (v_b_151_3 Int) (v_b_150_3 Int) (v_b_155_3 Int) (v_b_154_3 Int) (v_b_153_3 Int) (v_b_152_3 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse4 (+ c_ULTIMATE.start_main_p1 3)) (.cse7 (+ v_b_148_3 2)) (.cse2 (+ v_b_150_3 2)) (.cse5 (+ v_b_148_3 3)) (.cse0 (+ c_ULTIMATE.start_main_p1 2)) (.cse9 (+ v_b_149_3 1)) (.cse8 (+ v_b_151_3 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse11 (+ v_b_152_3 1)) (.cse13 (+ v_b_149_3 2)) (.cse12 (+ v_b_148_3 1)) (.cse10 (+ v_b_150_3 1)) (.cse6 (+ v_b_154_3 1))) (and (<= (+ v_b_148_3 4) v_b_155_3) (<= .cse0 v_b_149_3) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_155_3) (or (< v_idx_327 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_327) (= (select |c_#memory_int| v_idx_327) v_v_1448_3)) (<= .cse2 v_b_154_3) (<= .cse3 v_b_153_3) (<= .cse4 v_b_152_3) (<= 0 (* 2 v_v_1448_3)) (<= .cse3 v_b_154_3) (<= v_b_153_3 v_b_154_3) (<= .cse5 v_b_154_3) (<= .cse4 v_b_151_3) (<= .cse6 v_b_155_3) (<= .cse7 v_b_151_3) (<= .cse8 v_b_153_3) (or (= (select |c_#memory_int| v_idx_326) v_v_1447_3) (<= c_ULTIMATE.start_main_p1 v_idx_326)) (<= .cse9 v_b_151_3) (<= .cse10 v_b_152_3) (or (= (select |c_#memory_int| v_idx_336) v_v_1457_3) (< v_idx_336 v_b_155_3)) (or (<= v_b_154_3 v_idx_334) (= (select |c_#memory_int| v_idx_334) v_v_1455_3) (< v_idx_334 v_b_153_3)) (<= v_b_153_3 .cse11) (<= (+ v_b_150_3 3) v_b_155_3) (or (<= v_b_150_3 v_idx_330) (< v_idx_330 v_b_149_3) (= (select |c_#memory_int| v_idx_330) v_v_1451_3)) (or (<= v_b_155_3 v_idx_335) (< v_idx_335 v_b_154_3) (= 0 (select |c_#memory_int| v_idx_335))) (<= (+ v_b_153_3 1) v_b_155_3) (<= .cse12 v_b_150_3) (<= .cse7 v_b_152_3) (<= v_b_149_3 .cse12) (<= .cse2 v_b_153_3) (<= .cse13 v_b_154_3) (<= .cse5 v_b_153_3) (<= .cse10 v_b_151_3) (<= .cse0 v_b_150_3) (<= .cse9 v_b_152_3) (<= v_b_151_3 v_b_152_3) (or (= 0 (select |c_#memory_int| v_idx_329)) (< v_idx_329 v_b_148_3) (<= v_b_149_3 v_idx_329)) (<= .cse11 v_b_153_3) (or (< v_idx_328 .cse1) (<= v_b_148_3 v_idx_328) (= (select |c_#memory_int| v_idx_328) v_v_1449_3)) (<= v_b_149_3 v_b_150_3) (<= .cse8 v_b_154_3) (<= .cse1 v_b_148_3) (or (<= v_b_153_3 v_idx_333) (= 0 (select |c_#memory_int| v_idx_333)) (< v_idx_333 v_b_152_3)) (<= .cse11 v_b_154_3) (<= (+ v_b_151_3 2) v_b_155_3) (or (<= v_b_152_3 v_idx_332) (< v_idx_332 v_b_151_3) (= (select |c_#memory_int| v_idx_332) v_v_1453_3)) (<= .cse13 v_b_153_3) (<= .cse12 v_b_149_3) (<= v_b_151_3 .cse10) (<= (+ v_b_152_3 2) v_b_155_3) (<= (+ v_b_149_3 3) v_b_155_3) (<= 0 v_v_1448_3) (or (< v_idx_331 v_b_150_3) (<= v_b_151_3 v_idx_331) (= 0 (select |c_#memory_int| v_idx_331))) (<= v_b_155_3 .cse6))))) (forall ((v_idx_324 Int) (v_idx_325 Int) (v_idx_322 Int) (v_idx_323 Int) (v_idx_317 Int) (v_idx_318 Int) (v_idx_315 Int) (v_idx_316 Int) (v_idx_319 Int) (v_idx_320 Int) (v_idx_321 Int)) (exists ((v_v_1453_3 Int) (v_v_1451_3 Int) (v_v_1457_3 Int) (v_b_148_3 Int) (v_v_1455_3 Int) (v_v_1449_3 Int) (v_b_149_3 Int) (v_v_1447_3 Int) (v_v_1448_3 Int) (v_b_151_3 Int) (v_b_150_3 Int) (v_b_155_3 Int) (v_b_154_3 Int) (v_b_153_3 Int) (v_b_152_3 Int)) (let ((.cse16 (+ c_ULTIMATE.start_main_p1 4)) (.cse17 (+ c_ULTIMATE.start_main_p1 3)) (.cse21 (+ v_b_148_3 2)) (.cse15 (+ v_b_150_3 2)) (.cse19 (+ v_b_148_3 3)) (.cse14 (+ c_ULTIMATE.start_main_p1 2)) (.cse23 (+ v_b_149_3 1)) (.cse22 (+ v_b_151_3 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 1)) (.cse25 (+ v_b_152_3 1)) (.cse27 (+ v_b_149_3 2)) (.cse26 (+ v_b_148_3 1)) (.cse24 (+ v_b_150_3 1)) (.cse20 (+ v_b_154_3 1))) (and (<= (+ v_b_148_3 4) v_b_155_3) (<= .cse14 v_b_149_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_315) (= (select |c_#memory_int| v_idx_315) v_v_1447_3)) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_155_3) (<= .cse15 v_b_154_3) (<= .cse16 v_b_153_3) (<= .cse17 v_b_152_3) (<= 0 (* 2 v_v_1448_3)) (or (<= v_b_148_3 v_idx_317) (= (select |c_#memory_int| v_idx_317) v_v_1449_3) (< v_idx_317 .cse18)) (or (= (select |c_#memory_int| v_idx_325) v_v_1457_3) (< v_idx_325 v_b_155_3)) (<= .cse16 v_b_154_3) (or (< v_idx_318 v_b_148_3) (<= v_b_149_3 v_idx_318) (= (select |c_#memory_int| v_idx_318) 0)) (<= v_b_153_3 v_b_154_3) (<= .cse19 v_b_154_3) (or (< v_idx_316 c_ULTIMATE.start_main_p1) (<= .cse18 v_idx_316) (= (select |c_#memory_int| v_idx_316) v_v_1448_3)) (<= .cse17 v_b_151_3) (<= .cse20 v_b_155_3) (<= .cse21 v_b_151_3) (<= .cse22 v_b_153_3) (<= .cse23 v_b_151_3) (<= .cse24 v_b_152_3) (<= v_b_153_3 .cse25) (<= (+ v_b_150_3 3) v_b_155_3) (<= (+ v_b_153_3 1) v_b_155_3) (<= .cse26 v_b_150_3) (<= .cse21 v_b_152_3) (<= v_b_149_3 .cse26) (or (<= v_b_153_3 v_idx_322) (< v_idx_322 v_b_152_3) (= 0 (select |c_#memory_int| v_idx_322))) (<= .cse15 v_b_153_3) (<= .cse27 v_b_154_3) (<= .cse19 v_b_153_3) (<= .cse24 v_b_151_3) (<= .cse14 v_b_150_3) (<= .cse23 v_b_152_3) (<= v_b_151_3 v_b_152_3) (<= .cse25 v_b_153_3) (<= v_b_149_3 v_b_150_3) (<= .cse22 v_b_154_3) (<= .cse18 v_b_148_3) (<= .cse25 v_b_154_3) (<= (+ v_b_151_3 2) v_b_155_3) (<= .cse27 v_b_153_3) (or (<= v_b_154_3 v_idx_323) (= (select |c_#memory_int| v_idx_323) v_v_1455_3) (< v_idx_323 v_b_153_3)) (or (= 0 (select |c_#memory_int| v_idx_324)) (<= v_b_155_3 v_idx_324) (< v_idx_324 v_b_154_3)) (<= .cse26 v_b_149_3) (<= v_b_151_3 .cse24) (<= (+ v_b_152_3 2) v_b_155_3) (<= (+ v_b_149_3 3) v_b_155_3) (<= 0 v_v_1448_3) (or (< v_idx_320 v_b_150_3) (<= v_b_151_3 v_idx_320) (= (select |c_#memory_int| v_idx_320) 0)) (or (< v_idx_321 v_b_151_3) (<= v_b_152_3 v_idx_321) (= (select |c_#memory_int| v_idx_321) v_v_1453_3)) (or (< v_idx_319 v_b_149_3) (<= v_b_150_3 v_idx_319) (= (select |c_#memory_int| v_idx_319) v_v_1451_3)) (<= v_b_155_3 .cse20)))))) is different from false [2019-01-11 11:44:43,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:44:43,829 INFO L93 Difference]: Finished difference Result 15 states and 34 transitions. [2019-01-11 11:44:43,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:44:43,830 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:44:43,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:44:43,831 INFO L225 Difference]: With dead ends: 15 [2019-01-11 11:44:43,831 INFO L226 Difference]: Without dead ends: 14 [2019-01-11 11:44:43,831 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 8.2s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:44:43,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states. [2019-01-11 11:44:43,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 13. [2019-01-11 11:44:43,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2019-01-11 11:44:43,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 27 transitions. [2019-01-11 11:44:43,841 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 27 transitions. Word has length 3 [2019-01-11 11:44:43,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:44:43,842 INFO L480 AbstractCegarLoop]: Abstraction has 13 states and 27 transitions. [2019-01-11 11:44:43,842 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:44:43,842 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 27 transitions. [2019-01-11 11:44:43,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:44:43,842 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:44:43,842 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:44:43,842 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:44:43,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:43,843 INFO L82 PathProgramCache]: Analyzing trace with hash 30560, now seen corresponding path program 1 times [2019-01-11 11:44:43,843 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:44:43,844 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:43,844 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:44:43,844 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:43,844 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:44:43,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:44:43,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:44:43,880 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-11 11:44:43,881 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-11 11:44:43,881 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:44:43,881 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-11 11:44:43,881 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-11 11:44:43,881 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:44:43,882 INFO L87 Difference]: Start difference. First operand 13 states and 27 transitions. Second operand 3 states. [2019-01-11 11:44:44,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:44:44,213 INFO L93 Difference]: Finished difference Result 21 states and 34 transitions. [2019-01-11 11:44:44,214 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:44:44,214 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-01-11 11:44:44,214 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:44:44,215 INFO L225 Difference]: With dead ends: 21 [2019-01-11 11:44:44,215 INFO L226 Difference]: Without dead ends: 20 [2019-01-11 11:44:44,215 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:44:44,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-01-11 11:44:44,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 14. [2019-01-11 11:44:44,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2019-01-11 11:44:44,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 28 transitions. [2019-01-11 11:44:44,225 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 28 transitions. Word has length 3 [2019-01-11 11:44:44,226 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:44:44,226 INFO L480 AbstractCegarLoop]: Abstraction has 14 states and 28 transitions. [2019-01-11 11:44:44,226 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-11 11:44:44,226 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 28 transitions. [2019-01-11 11:44:44,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:44:44,226 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:44:44,227 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:44:44,227 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:44:44,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:44,227 INFO L82 PathProgramCache]: Analyzing trace with hash 30124, now seen corresponding path program 1 times [2019-01-11 11:44:44,227 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:44:44,228 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:44,228 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:44:44,229 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:44,229 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:44:44,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:44:44,298 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:44:44,299 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:44:44,299 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:44:44,299 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:44:44,300 INFO L207 CegarAbsIntRunner]: [0], [10], [23] [2019-01-11 11:44:44,301 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:44:44,301 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:44:52,603 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:44:52,603 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:44:52,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:52,604 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:44:52,991 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 72.22% of their original sizes. [2019-01-11 11:44:52,992 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:44:55,278 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_434 Int) (v_idx_435 Int) (v_idx_432 Int) (v_idx_433 Int) (v_idx_427 Int) (v_idx_428 Int) (v_idx_436 Int) (v_idx_437 Int) (v_idx_429 Int) (v_idx_430 Int) (v_idx_431 Int)) (exists ((v_v_1691_4 Int) (v_v_1694_4 Int) (v_v_1693_4 Int) (v_b_158_4 Int) (v_b_157_4 Int) (v_v_1699_4 Int) (v_b_156_4 Int) (v_b_155_4 Int) (v_v_1695_4 Int) (v_v_1697_4 Int) (v_b_159_4 Int) (v_b_154_4 Int) (v_v_1701_4 Int)) (let ((.cse3 (+ v_b_155_4 1)) (.cse5 (+ v_b_158_4 1)) (.cse1 (+ v_b_154_4 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 3)) (.cse8 (+ v_b_156_4 1)) (.cse10 (+ v_b_154_4 2)) (.cse4 (+ c_ULTIMATE.start_main_p2 1)) (.cse2 (+ c_ULTIMATE.start_main_p1 4)) (.cse6 (+ c_ULTIMATE.start_main_p1 1)) (.cse9 (+ c_ULTIMATE.start_main_p2 2)) (.cse0 (+ c_ULTIMATE.start_main_p2 3))) (and (<= v_b_157_4 v_b_158_4) (<= .cse0 v_b_158_4) (<= .cse1 v_b_155_4) (<= .cse2 v_b_157_4) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_154_4) (<= v_v_1694_4 0) (<= .cse3 v_b_157_4) (<= (+ v_b_156_4 2) v_b_159_4) (or (<= .cse4 v_idx_430) (< v_idx_430 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_430) v_v_1694_4)) (<= v_b_159_4 .cse5) (<= v_b_155_4 v_b_156_4) (<= (+ c_ULTIMATE.start_main_p2 4) v_b_159_4) (<= .cse1 v_b_156_4) (or (<= v_b_156_4 v_idx_433) (= (select |c_#memory_int| v_idx_433) v_v_1697_4) (< v_idx_433 v_b_155_4)) (or (< v_idx_435 v_b_157_4) (<= v_b_158_4 v_idx_435) (= (select |c_#memory_int| v_idx_435) v_v_1699_4)) (<= (+ v_b_157_4 1) v_b_159_4) (or (= (select |c_#memory_int| v_idx_429) v_v_1693_4) (<= c_ULTIMATE.start_main_p2 v_idx_429) (< v_idx_429 .cse6)) (<= .cse7 v_b_155_4) (or (= (select |c_#memory_int| v_idx_436) 0) (< v_idx_436 v_b_158_4) (<= v_b_159_4 v_idx_436)) (<= .cse3 v_b_158_4) (<= (+ v_b_155_4 2) v_b_159_4) (<= (* 2 v_v_1694_4) 0) (<= .cse5 v_b_159_4) (<= v_b_155_4 .cse1) (or (<= c_ULTIMATE.start_main_p1 v_idx_427) (= (select |c_#memory_int| v_idx_427) v_v_1691_4)) (or (<= v_b_154_4 v_idx_431) (< v_idx_431 .cse4) (= (select |c_#memory_int| v_idx_431) v_v_1695_4)) (<= (+ v_b_154_4 3) v_b_159_4) (<= .cse8 v_b_158_4) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_159_4) (or (= (select |c_#memory_int| v_idx_432) 0) (<= v_b_155_4 v_idx_432) (< v_idx_432 v_b_154_4)) (<= .cse9 v_b_155_4) (or (<= v_b_157_4 v_idx_434) (= (select |c_#memory_int| v_idx_434) 0) (< v_idx_434 v_b_156_4)) (<= .cse10 v_b_157_4) (<= .cse7 v_b_156_4) (<= .cse8 v_b_157_4) (<= v_b_157_4 .cse8) (<= .cse10 v_b_158_4) (or (= (select |c_#memory_int| v_idx_428) 0) (< v_idx_428 c_ULTIMATE.start_main_p1) (<= .cse6 v_idx_428)) (or (= (select |c_#memory_int| v_idx_437) v_v_1701_4) (< v_idx_437 v_b_159_4)) (<= .cse4 v_b_154_4) (<= .cse2 v_b_158_4) (<= .cse6 c_ULTIMATE.start_main_p2) (<= .cse9 v_b_156_4) (<= .cse0 v_b_157_4))))) is different from false [2019-01-11 11:44:57,683 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_445 Int) (v_idx_446 Int) (v_idx_443 Int) (v_idx_444 Int) (v_idx_438 Int) (v_idx_439 Int) (v_idx_447 Int) (v_idx_448 Int) (v_idx_441 Int) (v_idx_442 Int) (v_idx_440 Int)) (exists ((v_v_1691_4 Int) (v_v_1694_4 Int) (v_v_1693_4 Int) (v_b_158_4 Int) (v_b_157_4 Int) (v_v_1699_4 Int) (v_b_156_4 Int) (v_b_155_4 Int) (v_v_1695_4 Int) (v_v_1697_4 Int) (v_b_159_4 Int) (v_b_154_4 Int) (v_b_153_4 Int) (v_v_1701_4 Int) (v_b_152_4 Int)) (let ((.cse2 (+ v_b_152_4 1)) (.cse4 (+ v_b_158_4 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ v_b_152_4 3)) (.cse10 (+ v_b_155_4 1)) (.cse8 (+ v_b_154_4 1)) (.cse12 (+ v_b_152_4 2)) (.cse9 (+ c_ULTIMATE.start_main_p1 2)) (.cse11 (+ c_ULTIMATE.start_main_p1 3)) (.cse6 (+ v_b_156_4 1)) (.cse5 (+ v_b_154_4 2)) (.cse1 (+ v_b_153_4 1)) (.cse13 (+ v_b_153_4 2)) (.cse0 (+ c_ULTIMATE.start_main_p1 4))) (and (<= v_b_157_4 v_b_158_4) (<= .cse0 v_b_157_4) (<= .cse1 v_b_156_4) (<= .cse2 v_b_154_4) (or (= (select |c_#memory_int| v_idx_444) v_v_1697_4) (<= v_b_156_4 v_idx_444) (< v_idx_444 v_b_155_4)) (<= v_b_155_4 v_b_156_4) (<= .cse3 v_b_152_4) (<= (+ v_b_157_4 1) v_b_159_4) (or (<= v_b_159_4 v_idx_447) (= (select |c_#memory_int| v_idx_447) 0) (< v_idx_447 v_b_158_4)) (<= (* 2 v_v_1694_4) 0) (<= .cse4 v_b_159_4) (<= (+ v_b_152_4 4) v_b_159_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_438) (= (select |c_#memory_int| v_idx_438) v_v_1691_4)) (<= v_b_153_4 .cse2) (or (= (select |c_#memory_int| v_idx_445) 0) (< v_idx_445 v_b_156_4) (<= v_b_157_4 v_idx_445)) (<= .cse5 v_b_157_4) (<= .cse2 v_b_153_4) (<= .cse6 v_b_157_4) (or (= (select |c_#memory_int| v_idx_439) 0) (<= .cse3 v_idx_439) (< v_idx_439 c_ULTIMATE.start_main_p1)) (<= .cse7 v_b_157_4) (or (= (select |c_#memory_int| v_idx_443) 0) (< v_idx_443 v_b_154_4) (<= v_b_155_4 v_idx_443)) (or (<= v_b_158_4 v_idx_446) (< v_idx_446 v_b_157_4) (= (select |c_#memory_int| v_idx_446) v_v_1699_4)) (or (<= v_b_153_4 v_idx_441) (= (select |c_#memory_int| v_idx_441) v_v_1694_4) (< v_idx_441 v_b_152_4)) (<= .cse8 v_b_155_4) (<= .cse9 v_b_154_4) (<= v_v_1694_4 0) (<= .cse10 v_b_157_4) (<= (+ v_b_156_4 2) v_b_159_4) (<= v_b_159_4 .cse4) (or (<= v_b_152_4 v_idx_440) (= (select |c_#memory_int| v_idx_440) v_v_1693_4) (< v_idx_440 .cse3)) (<= .cse8 v_b_156_4) (<= .cse7 v_b_158_4) (<= .cse11 v_b_155_4) (<= .cse12 v_b_155_4) (<= .cse10 v_b_158_4) (<= (+ v_b_155_4 2) v_b_159_4) (<= v_b_155_4 .cse8) (<= .cse12 v_b_156_4) (<= v_b_153_4 v_b_154_4) (<= (+ v_b_154_4 3) v_b_159_4) (<= .cse6 v_b_158_4) (<= .cse13 v_b_158_4) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_159_4) (<= .cse9 v_b_153_4) (or (= (select |c_#memory_int| v_idx_442) v_v_1695_4) (< v_idx_442 v_b_153_4) (<= v_b_154_4 v_idx_442)) (<= .cse11 v_b_156_4) (<= v_b_157_4 .cse6) (<= .cse5 v_b_158_4) (<= .cse1 v_b_155_4) (<= (+ v_b_153_4 3) v_b_159_4) (<= .cse13 v_b_157_4) (<= .cse0 v_b_158_4) (or (< v_idx_448 v_b_159_4) (= (select |c_#memory_int| v_idx_448) v_v_1701_4)))))) is different from false [2019-01-11 11:44:57,779 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:44:57,780 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:44:57,780 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:44:57,780 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:44:57,780 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:44:57,780 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:44:57,780 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:44:57,781 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:44:57,781 INFO L87 Difference]: Start difference. First operand 14 states and 28 transitions. Second operand 4 states. [2019-01-11 11:45:00,125 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_445 Int) (v_idx_446 Int) (v_idx_443 Int) (v_idx_444 Int) (v_idx_438 Int) (v_idx_439 Int) (v_idx_447 Int) (v_idx_448 Int) (v_idx_441 Int) (v_idx_442 Int) (v_idx_440 Int)) (exists ((v_v_1691_4 Int) (v_v_1694_4 Int) (v_v_1693_4 Int) (v_b_158_4 Int) (v_b_157_4 Int) (v_v_1699_4 Int) (v_b_156_4 Int) (v_b_155_4 Int) (v_v_1695_4 Int) (v_v_1697_4 Int) (v_b_159_4 Int) (v_b_154_4 Int) (v_b_153_4 Int) (v_v_1701_4 Int) (v_b_152_4 Int)) (let ((.cse2 (+ v_b_152_4 1)) (.cse4 (+ v_b_158_4 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ v_b_152_4 3)) (.cse10 (+ v_b_155_4 1)) (.cse8 (+ v_b_154_4 1)) (.cse12 (+ v_b_152_4 2)) (.cse9 (+ c_ULTIMATE.start_main_p1 2)) (.cse11 (+ c_ULTIMATE.start_main_p1 3)) (.cse6 (+ v_b_156_4 1)) (.cse5 (+ v_b_154_4 2)) (.cse1 (+ v_b_153_4 1)) (.cse13 (+ v_b_153_4 2)) (.cse0 (+ c_ULTIMATE.start_main_p1 4))) (and (<= v_b_157_4 v_b_158_4) (<= .cse0 v_b_157_4) (<= .cse1 v_b_156_4) (<= .cse2 v_b_154_4) (or (= (select |c_#memory_int| v_idx_444) v_v_1697_4) (<= v_b_156_4 v_idx_444) (< v_idx_444 v_b_155_4)) (<= v_b_155_4 v_b_156_4) (<= .cse3 v_b_152_4) (<= (+ v_b_157_4 1) v_b_159_4) (or (<= v_b_159_4 v_idx_447) (= (select |c_#memory_int| v_idx_447) 0) (< v_idx_447 v_b_158_4)) (<= (* 2 v_v_1694_4) 0) (<= .cse4 v_b_159_4) (<= (+ v_b_152_4 4) v_b_159_4) (or (<= c_ULTIMATE.start_main_p1 v_idx_438) (= (select |c_#memory_int| v_idx_438) v_v_1691_4)) (<= v_b_153_4 .cse2) (or (= (select |c_#memory_int| v_idx_445) 0) (< v_idx_445 v_b_156_4) (<= v_b_157_4 v_idx_445)) (<= .cse5 v_b_157_4) (<= .cse2 v_b_153_4) (<= .cse6 v_b_157_4) (or (= (select |c_#memory_int| v_idx_439) 0) (<= .cse3 v_idx_439) (< v_idx_439 c_ULTIMATE.start_main_p1)) (<= .cse7 v_b_157_4) (or (= (select |c_#memory_int| v_idx_443) 0) (< v_idx_443 v_b_154_4) (<= v_b_155_4 v_idx_443)) (or (<= v_b_158_4 v_idx_446) (< v_idx_446 v_b_157_4) (= (select |c_#memory_int| v_idx_446) v_v_1699_4)) (or (<= v_b_153_4 v_idx_441) (= (select |c_#memory_int| v_idx_441) v_v_1694_4) (< v_idx_441 v_b_152_4)) (<= .cse8 v_b_155_4) (<= .cse9 v_b_154_4) (<= v_v_1694_4 0) (<= .cse10 v_b_157_4) (<= (+ v_b_156_4 2) v_b_159_4) (<= v_b_159_4 .cse4) (or (<= v_b_152_4 v_idx_440) (= (select |c_#memory_int| v_idx_440) v_v_1693_4) (< v_idx_440 .cse3)) (<= .cse8 v_b_156_4) (<= .cse7 v_b_158_4) (<= .cse11 v_b_155_4) (<= .cse12 v_b_155_4) (<= .cse10 v_b_158_4) (<= (+ v_b_155_4 2) v_b_159_4) (<= v_b_155_4 .cse8) (<= .cse12 v_b_156_4) (<= v_b_153_4 v_b_154_4) (<= (+ v_b_154_4 3) v_b_159_4) (<= .cse6 v_b_158_4) (<= .cse13 v_b_158_4) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_159_4) (<= .cse9 v_b_153_4) (or (= (select |c_#memory_int| v_idx_442) v_v_1695_4) (< v_idx_442 v_b_153_4) (<= v_b_154_4 v_idx_442)) (<= .cse11 v_b_156_4) (<= v_b_157_4 .cse6) (<= .cse5 v_b_158_4) (<= .cse1 v_b_155_4) (<= (+ v_b_153_4 3) v_b_159_4) (<= .cse13 v_b_157_4) (<= .cse0 v_b_158_4) (or (< v_idx_448 v_b_159_4) (= (select |c_#memory_int| v_idx_448) v_v_1701_4)))))) (forall ((v_idx_434 Int) (v_idx_435 Int) (v_idx_432 Int) (v_idx_433 Int) (v_idx_427 Int) (v_idx_428 Int) (v_idx_436 Int) (v_idx_437 Int) (v_idx_429 Int) (v_idx_430 Int) (v_idx_431 Int)) (exists ((v_v_1691_4 Int) (v_v_1694_4 Int) (v_v_1693_4 Int) (v_b_158_4 Int) (v_b_157_4 Int) (v_v_1699_4 Int) (v_b_156_4 Int) (v_b_155_4 Int) (v_v_1695_4 Int) (v_v_1697_4 Int) (v_b_159_4 Int) (v_b_154_4 Int) (v_v_1701_4 Int)) (let ((.cse17 (+ v_b_155_4 1)) (.cse19 (+ v_b_158_4 1)) (.cse15 (+ v_b_154_4 1)) (.cse21 (+ c_ULTIMATE.start_main_p1 3)) (.cse22 (+ v_b_156_4 1)) (.cse24 (+ v_b_154_4 2)) (.cse18 (+ c_ULTIMATE.start_main_p2 1)) (.cse16 (+ c_ULTIMATE.start_main_p1 4)) (.cse20 (+ c_ULTIMATE.start_main_p1 1)) (.cse23 (+ c_ULTIMATE.start_main_p2 2)) (.cse14 (+ c_ULTIMATE.start_main_p2 3))) (and (<= v_b_157_4 v_b_158_4) (<= .cse14 v_b_158_4) (<= .cse15 v_b_155_4) (<= .cse16 v_b_157_4) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_154_4) (<= v_v_1694_4 0) (<= .cse17 v_b_157_4) (<= (+ v_b_156_4 2) v_b_159_4) (or (<= .cse18 v_idx_430) (< v_idx_430 c_ULTIMATE.start_main_p2) (= (select |c_#memory_int| v_idx_430) v_v_1694_4)) (<= v_b_159_4 .cse19) (<= v_b_155_4 v_b_156_4) (<= (+ c_ULTIMATE.start_main_p2 4) v_b_159_4) (<= .cse15 v_b_156_4) (or (<= v_b_156_4 v_idx_433) (= (select |c_#memory_int| v_idx_433) v_v_1697_4) (< v_idx_433 v_b_155_4)) (or (< v_idx_435 v_b_157_4) (<= v_b_158_4 v_idx_435) (= (select |c_#memory_int| v_idx_435) v_v_1699_4)) (<= (+ v_b_157_4 1) v_b_159_4) (or (= (select |c_#memory_int| v_idx_429) v_v_1693_4) (<= c_ULTIMATE.start_main_p2 v_idx_429) (< v_idx_429 .cse20)) (<= .cse21 v_b_155_4) (or (= (select |c_#memory_int| v_idx_436) 0) (< v_idx_436 v_b_158_4) (<= v_b_159_4 v_idx_436)) (<= .cse17 v_b_158_4) (<= (+ v_b_155_4 2) v_b_159_4) (<= (* 2 v_v_1694_4) 0) (<= .cse19 v_b_159_4) (<= v_b_155_4 .cse15) (or (<= c_ULTIMATE.start_main_p1 v_idx_427) (= (select |c_#memory_int| v_idx_427) v_v_1691_4)) (or (<= v_b_154_4 v_idx_431) (< v_idx_431 .cse18) (= (select |c_#memory_int| v_idx_431) v_v_1695_4)) (<= (+ v_b_154_4 3) v_b_159_4) (<= .cse22 v_b_158_4) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_159_4) (or (= (select |c_#memory_int| v_idx_432) 0) (<= v_b_155_4 v_idx_432) (< v_idx_432 v_b_154_4)) (<= .cse23 v_b_155_4) (or (<= v_b_157_4 v_idx_434) (= (select |c_#memory_int| v_idx_434) 0) (< v_idx_434 v_b_156_4)) (<= .cse24 v_b_157_4) (<= .cse21 v_b_156_4) (<= .cse22 v_b_157_4) (<= v_b_157_4 .cse22) (<= .cse24 v_b_158_4) (or (= (select |c_#memory_int| v_idx_428) 0) (< v_idx_428 c_ULTIMATE.start_main_p1) (<= .cse20 v_idx_428)) (or (= (select |c_#memory_int| v_idx_437) v_v_1701_4) (< v_idx_437 v_b_159_4)) (<= .cse18 v_b_154_4) (<= .cse16 v_b_158_4) (<= .cse20 c_ULTIMATE.start_main_p2) (<= .cse23 v_b_156_4) (<= .cse14 v_b_157_4)))))) is different from false [2019-01-11 11:45:17,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:45:17,768 INFO L93 Difference]: Finished difference Result 16 states and 35 transitions. [2019-01-11 11:45:17,768 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:45:17,769 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:45:17,769 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:45:17,769 INFO L225 Difference]: With dead ends: 16 [2019-01-11 11:45:17,769 INFO L226 Difference]: Without dead ends: 15 [2019-01-11 11:45:17,771 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.0s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:45:17,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states. [2019-01-11 11:45:17,780 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 14. [2019-01-11 11:45:17,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2019-01-11 11:45:17,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 28 transitions. [2019-01-11 11:45:17,781 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 28 transitions. Word has length 3 [2019-01-11 11:45:17,781 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:45:17,781 INFO L480 AbstractCegarLoop]: Abstraction has 14 states and 28 transitions. [2019-01-11 11:45:17,781 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:45:17,781 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 28 transitions. [2019-01-11 11:45:17,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:45:17,781 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:45:17,781 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:45:17,782 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:45:17,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:17,782 INFO L82 PathProgramCache]: Analyzing trace with hash 30248, now seen corresponding path program 1 times [2019-01-11 11:45:17,782 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:45:17,783 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:17,783 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:45:17,783 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:17,783 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:45:17,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:45:17,848 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:45:17,848 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:45:17,849 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:45:17,849 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:45:17,849 INFO L207 CegarAbsIntRunner]: [0], [14], [23] [2019-01-11 11:45:17,850 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:45:17,850 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:45:23,998 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:45:23,998 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:45:23,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:23,998 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:45:24,409 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 72.22% of their original sizes. [2019-01-11 11:45:24,409 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:45:26,800 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_544 Int) (v_idx_545 Int) (v_idx_542 Int) (v_idx_543 Int) (v_idx_548 Int) (v_idx_549 Int) (v_idx_546 Int) (v_idx_547 Int) (v_idx_539 Int) (v_idx_540 Int) (v_idx_541 Int)) (exists ((v_b_157_5 Int) (v_b_156_5 Int) (v_b_159_5 Int) (v_b_158_5 Int) (v_v_1279_5 Int) (v_b_153_5 Int) (v_b_152_5 Int) (v_v_1278_5 Int) (v_v_1277_5 Int) (v_v_1283_5 Int) (v_v_1275_5 Int) (v_v_1273_5 Int) (v_v_1281_5 Int)) (let ((.cse8 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ c_ULTIMATE.start_main_p3 1)) (.cse6 (+ v_b_152_5 1)) (.cse9 (+ v_b_152_5 3)) (.cse0 (+ v_b_153_5 2)) (.cse4 (+ v_b_158_5 1)) (.cse2 (+ v_b_156_5 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 4)) (.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ c_ULTIMATE.start_main_p3 2))) (and (<= .cse0 v_b_157_5) (<= .cse1 v_b_157_5) (or (= (select |c_#memory_int| v_idx_548) 0) (< v_idx_548 v_b_158_5) (<= v_b_159_5 v_idx_548)) (<= v_b_157_5 .cse2) (or (< v_idx_545 .cse3) (= (select |c_#memory_int| v_idx_545) v_v_1279_5) (<= v_b_156_5 v_idx_545)) (<= .cse4 v_b_159_5) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_156_5) (or (<= .cse5 v_idx_540) (= (select |c_#memory_int| v_idx_540) 0) (< v_idx_540 c_ULTIMATE.start_main_p1)) (<= v_b_153_5 c_ULTIMATE.start_main_p3) (<= v_b_153_5 .cse6) (<= v_b_157_5 v_b_158_5) (<= .cse5 v_b_152_5) (<= (+ c_ULTIMATE.start_main_p3 3) v_b_159_5) (<= .cse7 v_b_158_5) (<= (+ v_b_152_5 4) v_b_159_5) (or (< v_idx_547 v_b_157_5) (= (select |c_#memory_int| v_idx_547) v_v_1281_5) (<= v_b_158_5 v_idx_547)) (<= .cse3 v_b_156_5) (<= .cse2 v_b_158_5) (<= 0 (* 2 v_v_1278_5)) (<= (+ v_b_157_5 1) v_b_159_5) (<= .cse6 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_539) v_v_1273_5) (<= c_ULTIMATE.start_main_p1 v_idx_539)) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_159_5) (<= .cse8 c_ULTIMATE.start_main_p3) (or (< v_idx_542 v_b_152_5) (= (select |c_#memory_int| v_idx_542) 0) (<= v_b_153_5 v_idx_542)) (<= .cse8 v_b_153_5) (or (<= .cse3 v_idx_544) (< v_idx_544 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_544) v_v_1278_5)) (<= .cse6 v_b_153_5) (<= (+ v_b_153_5 1) v_b_156_5) (<= .cse9 v_b_157_5) (or (< v_idx_543 v_b_153_5) (<= c_ULTIMATE.start_main_p3 v_idx_543) (= v_v_1277_5 (select |c_#memory_int| v_idx_543))) (<= (+ v_b_156_5 2) v_b_159_5) (or (< v_idx_549 v_b_159_5) (= (select |c_#memory_int| v_idx_549) v_v_1283_5)) (or (= 0 (select |c_#memory_int| v_idx_546)) (< v_idx_546 v_b_156_5) (<= v_b_157_5 v_idx_546)) (<= .cse9 v_b_158_5) (<= (+ v_b_153_5 3) v_b_159_5) (<= .cse0 v_b_158_5) (<= (+ v_b_152_5 2) v_b_156_5) (<= v_b_159_5 .cse4) (<= 0 v_v_1278_5) (<= .cse2 v_b_157_5) (<= .cse1 v_b_158_5) (or (= (select |c_#memory_int| v_idx_541) v_v_1275_5) (< v_idx_541 .cse5) (<= v_b_152_5 v_idx_541)) (<= .cse7 v_b_157_5))))) is different from false [2019-01-11 11:45:29,254 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_555 Int) (v_idx_556 Int) (v_idx_553 Int) (v_idx_554 Int) (v_idx_559 Int) (v_idx_557 Int) (v_idx_558 Int) (v_idx_551 Int) (v_idx_552 Int) (v_idx_560 Int) (v_idx_550 Int)) (exists ((v_b_157_5 Int) (v_b_156_5 Int) (v_b_155_5 Int) (v_b_154_5 Int) (v_b_159_5 Int) (v_b_158_5 Int) (v_b_153_5 Int) (v_v_1279_5 Int) (v_b_152_5 Int) (v_v_1278_5 Int) (v_v_1277_5 Int) (v_v_1275_5 Int) (v_v_1283_5 Int) (v_v_1273_5 Int) (v_v_1281_5 Int)) (let ((.cse3 (+ v_b_153_5 1)) (.cse1 (+ v_b_154_5 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse10 (+ v_b_152_5 3)) (.cse2 (+ v_b_158_5 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 3)) (.cse9 (+ v_b_152_5 1)) (.cse6 (+ v_b_154_5 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 2)) (.cse5 (+ v_b_155_5 1)) (.cse0 (+ v_b_153_5 2)) (.cse13 (+ v_b_152_5 2)) (.cse8 (+ v_b_156_5 1)) (.cse12 (+ c_ULTIMATE.start_main_p1 4))) (and (<= .cse0 v_b_157_5) (<= .cse1 v_b_158_5) (or (< v_idx_560 v_b_159_5) (= (select |c_#memory_int| v_idx_560) v_v_1283_5)) (<= .cse2 v_b_159_5) (<= .cse3 v_b_155_5) (or (<= c_ULTIMATE.start_main_p1 v_idx_550) (= (select |c_#memory_int| v_idx_550) v_v_1273_5)) (or (= (select |c_#memory_int| v_idx_552) v_v_1275_5) (< v_idx_552 .cse4) (<= v_b_152_5 v_idx_552)) (<= .cse5 v_b_158_5) (<= .cse4 v_b_152_5) (<= (+ v_b_154_5 3) v_b_159_5) (<= (+ v_b_152_5 4) v_b_159_5) (<= v_b_155_5 .cse6) (<= .cse7 v_b_155_5) (<= .cse8 v_b_158_5) (or (< v_idx_558 v_b_157_5) (= (select |c_#memory_int| v_idx_558) v_v_1281_5) (<= v_b_158_5 v_idx_558)) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_159_5) (or (= (select |c_#memory_int| v_idx_555) v_v_1278_5) (< v_idx_555 v_b_154_5) (<= v_b_155_5 v_idx_555)) (<= .cse9 v_b_153_5) (<= .cse3 v_b_156_5) (<= .cse1 v_b_157_5) (<= .cse10 v_b_157_5) (<= .cse11 v_b_154_5) (or (<= .cse4 v_idx_551) (= (select |c_#memory_int| v_idx_551) 0) (< v_idx_551 c_ULTIMATE.start_main_p1)) (<= (+ v_b_156_5 2) v_b_159_5) (<= (+ v_b_155_5 2) v_b_159_5) (<= .cse10 v_b_158_5) (<= v_b_159_5 .cse2) (<= .cse12 v_b_157_5) (or (< v_idx_556 v_b_155_5) (= (select |c_#memory_int| v_idx_556) v_v_1279_5) (<= v_b_156_5 v_idx_556)) (<= v_b_157_5 .cse8) (<= .cse7 v_b_156_5) (<= v_b_153_5 .cse9) (<= v_b_157_5 v_b_158_5) (<= .cse13 v_b_155_5) (<= 0 (* 2 v_v_1278_5)) (<= v_b_153_5 v_b_154_5) (<= .cse6 v_b_156_5) (<= (+ v_b_157_5 1) v_b_159_5) (<= v_b_155_5 v_b_156_5) (<= .cse9 v_b_154_5) (<= .cse6 v_b_155_5) (<= .cse11 v_b_153_5) (<= .cse5 v_b_157_5) (or (< v_idx_554 v_b_153_5) (= (select |c_#memory_int| v_idx_554) v_v_1277_5) (<= v_b_154_5 v_idx_554)) (<= (+ v_b_153_5 3) v_b_159_5) (<= .cse0 v_b_158_5) (<= .cse13 v_b_156_5) (or (<= v_b_153_5 v_idx_553) (= (select |c_#memory_int| v_idx_553) 0) (< v_idx_553 v_b_152_5)) (<= 0 v_v_1278_5) (<= .cse8 v_b_157_5) (<= .cse12 v_b_158_5) (or (<= v_b_157_5 v_idx_557) (= (select |c_#memory_int| v_idx_557) 0) (< v_idx_557 v_b_156_5)) (or (< v_idx_559 v_b_158_5) (<= v_b_159_5 v_idx_559) (= (select |c_#memory_int| v_idx_559) 0)))))) is different from false [2019-01-11 11:45:29,353 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:45:29,353 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:45:29,353 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:45:29,353 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:45:29,353 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:45:29,354 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:45:29,354 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:45:29,354 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:45:29,354 INFO L87 Difference]: Start difference. First operand 14 states and 28 transitions. Second operand 4 states. [2019-01-11 11:45:31,678 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_555 Int) (v_idx_556 Int) (v_idx_553 Int) (v_idx_554 Int) (v_idx_559 Int) (v_idx_557 Int) (v_idx_558 Int) (v_idx_551 Int) (v_idx_552 Int) (v_idx_560 Int) (v_idx_550 Int)) (exists ((v_b_157_5 Int) (v_b_156_5 Int) (v_b_155_5 Int) (v_b_154_5 Int) (v_b_159_5 Int) (v_b_158_5 Int) (v_b_153_5 Int) (v_v_1279_5 Int) (v_b_152_5 Int) (v_v_1278_5 Int) (v_v_1277_5 Int) (v_v_1275_5 Int) (v_v_1283_5 Int) (v_v_1273_5 Int) (v_v_1281_5 Int)) (let ((.cse3 (+ v_b_153_5 1)) (.cse1 (+ v_b_154_5 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse10 (+ v_b_152_5 3)) (.cse2 (+ v_b_158_5 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 3)) (.cse9 (+ v_b_152_5 1)) (.cse6 (+ v_b_154_5 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 2)) (.cse5 (+ v_b_155_5 1)) (.cse0 (+ v_b_153_5 2)) (.cse13 (+ v_b_152_5 2)) (.cse8 (+ v_b_156_5 1)) (.cse12 (+ c_ULTIMATE.start_main_p1 4))) (and (<= .cse0 v_b_157_5) (<= .cse1 v_b_158_5) (or (< v_idx_560 v_b_159_5) (= (select |c_#memory_int| v_idx_560) v_v_1283_5)) (<= .cse2 v_b_159_5) (<= .cse3 v_b_155_5) (or (<= c_ULTIMATE.start_main_p1 v_idx_550) (= (select |c_#memory_int| v_idx_550) v_v_1273_5)) (or (= (select |c_#memory_int| v_idx_552) v_v_1275_5) (< v_idx_552 .cse4) (<= v_b_152_5 v_idx_552)) (<= .cse5 v_b_158_5) (<= .cse4 v_b_152_5) (<= (+ v_b_154_5 3) v_b_159_5) (<= (+ v_b_152_5 4) v_b_159_5) (<= v_b_155_5 .cse6) (<= .cse7 v_b_155_5) (<= .cse8 v_b_158_5) (or (< v_idx_558 v_b_157_5) (= (select |c_#memory_int| v_idx_558) v_v_1281_5) (<= v_b_158_5 v_idx_558)) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_159_5) (or (= (select |c_#memory_int| v_idx_555) v_v_1278_5) (< v_idx_555 v_b_154_5) (<= v_b_155_5 v_idx_555)) (<= .cse9 v_b_153_5) (<= .cse3 v_b_156_5) (<= .cse1 v_b_157_5) (<= .cse10 v_b_157_5) (<= .cse11 v_b_154_5) (or (<= .cse4 v_idx_551) (= (select |c_#memory_int| v_idx_551) 0) (< v_idx_551 c_ULTIMATE.start_main_p1)) (<= (+ v_b_156_5 2) v_b_159_5) (<= (+ v_b_155_5 2) v_b_159_5) (<= .cse10 v_b_158_5) (<= v_b_159_5 .cse2) (<= .cse12 v_b_157_5) (or (< v_idx_556 v_b_155_5) (= (select |c_#memory_int| v_idx_556) v_v_1279_5) (<= v_b_156_5 v_idx_556)) (<= v_b_157_5 .cse8) (<= .cse7 v_b_156_5) (<= v_b_153_5 .cse9) (<= v_b_157_5 v_b_158_5) (<= .cse13 v_b_155_5) (<= 0 (* 2 v_v_1278_5)) (<= v_b_153_5 v_b_154_5) (<= .cse6 v_b_156_5) (<= (+ v_b_157_5 1) v_b_159_5) (<= v_b_155_5 v_b_156_5) (<= .cse9 v_b_154_5) (<= .cse6 v_b_155_5) (<= .cse11 v_b_153_5) (<= .cse5 v_b_157_5) (or (< v_idx_554 v_b_153_5) (= (select |c_#memory_int| v_idx_554) v_v_1277_5) (<= v_b_154_5 v_idx_554)) (<= (+ v_b_153_5 3) v_b_159_5) (<= .cse0 v_b_158_5) (<= .cse13 v_b_156_5) (or (<= v_b_153_5 v_idx_553) (= (select |c_#memory_int| v_idx_553) 0) (< v_idx_553 v_b_152_5)) (<= 0 v_v_1278_5) (<= .cse8 v_b_157_5) (<= .cse12 v_b_158_5) (or (<= v_b_157_5 v_idx_557) (= (select |c_#memory_int| v_idx_557) 0) (< v_idx_557 v_b_156_5)) (or (< v_idx_559 v_b_158_5) (<= v_b_159_5 v_idx_559) (= (select |c_#memory_int| v_idx_559) 0)))))) (forall ((v_idx_544 Int) (v_idx_545 Int) (v_idx_542 Int) (v_idx_543 Int) (v_idx_548 Int) (v_idx_549 Int) (v_idx_546 Int) (v_idx_547 Int) (v_idx_539 Int) (v_idx_540 Int) (v_idx_541 Int)) (exists ((v_b_157_5 Int) (v_b_156_5 Int) (v_b_159_5 Int) (v_b_158_5 Int) (v_v_1279_5 Int) (v_b_153_5 Int) (v_b_152_5 Int) (v_v_1278_5 Int) (v_v_1277_5 Int) (v_v_1283_5 Int) (v_v_1275_5 Int) (v_v_1273_5 Int) (v_v_1281_5 Int)) (let ((.cse22 (+ c_ULTIMATE.start_main_p1 2)) (.cse17 (+ c_ULTIMATE.start_main_p3 1)) (.cse20 (+ v_b_152_5 1)) (.cse23 (+ v_b_152_5 3)) (.cse14 (+ v_b_153_5 2)) (.cse18 (+ v_b_158_5 1)) (.cse16 (+ v_b_156_5 1)) (.cse15 (+ c_ULTIMATE.start_main_p1 4)) (.cse19 (+ c_ULTIMATE.start_main_p1 1)) (.cse21 (+ c_ULTIMATE.start_main_p3 2))) (and (<= .cse14 v_b_157_5) (<= .cse15 v_b_157_5) (or (= (select |c_#memory_int| v_idx_548) 0) (< v_idx_548 v_b_158_5) (<= v_b_159_5 v_idx_548)) (<= v_b_157_5 .cse16) (or (< v_idx_545 .cse17) (= (select |c_#memory_int| v_idx_545) v_v_1279_5) (<= v_b_156_5 v_idx_545)) (<= .cse18 v_b_159_5) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_156_5) (or (<= .cse19 v_idx_540) (= (select |c_#memory_int| v_idx_540) 0) (< v_idx_540 c_ULTIMATE.start_main_p1)) (<= v_b_153_5 c_ULTIMATE.start_main_p3) (<= v_b_153_5 .cse20) (<= v_b_157_5 v_b_158_5) (<= .cse19 v_b_152_5) (<= (+ c_ULTIMATE.start_main_p3 3) v_b_159_5) (<= .cse21 v_b_158_5) (<= (+ v_b_152_5 4) v_b_159_5) (or (< v_idx_547 v_b_157_5) (= (select |c_#memory_int| v_idx_547) v_v_1281_5) (<= v_b_158_5 v_idx_547)) (<= .cse17 v_b_156_5) (<= .cse16 v_b_158_5) (<= 0 (* 2 v_v_1278_5)) (<= (+ v_b_157_5 1) v_b_159_5) (<= .cse20 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_539) v_v_1273_5) (<= c_ULTIMATE.start_main_p1 v_idx_539)) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_159_5) (<= .cse22 c_ULTIMATE.start_main_p3) (or (< v_idx_542 v_b_152_5) (= (select |c_#memory_int| v_idx_542) 0) (<= v_b_153_5 v_idx_542)) (<= .cse22 v_b_153_5) (or (<= .cse17 v_idx_544) (< v_idx_544 c_ULTIMATE.start_main_p3) (= (select |c_#memory_int| v_idx_544) v_v_1278_5)) (<= .cse20 v_b_153_5) (<= (+ v_b_153_5 1) v_b_156_5) (<= .cse23 v_b_157_5) (or (< v_idx_543 v_b_153_5) (<= c_ULTIMATE.start_main_p3 v_idx_543) (= v_v_1277_5 (select |c_#memory_int| v_idx_543))) (<= (+ v_b_156_5 2) v_b_159_5) (or (< v_idx_549 v_b_159_5) (= (select |c_#memory_int| v_idx_549) v_v_1283_5)) (or (= 0 (select |c_#memory_int| v_idx_546)) (< v_idx_546 v_b_156_5) (<= v_b_157_5 v_idx_546)) (<= .cse23 v_b_158_5) (<= (+ v_b_153_5 3) v_b_159_5) (<= .cse14 v_b_158_5) (<= (+ v_b_152_5 2) v_b_156_5) (<= v_b_159_5 .cse18) (<= 0 v_v_1278_5) (<= .cse16 v_b_157_5) (<= .cse15 v_b_158_5) (or (= (select |c_#memory_int| v_idx_541) v_v_1275_5) (< v_idx_541 .cse19) (<= v_b_152_5 v_idx_541)) (<= .cse21 v_b_157_5)))))) is different from false [2019-01-11 11:45:48,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:45:48,507 INFO L93 Difference]: Finished difference Result 16 states and 35 transitions. [2019-01-11 11:45:48,507 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:45:48,507 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:45:48,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:45:48,508 INFO L225 Difference]: With dead ends: 16 [2019-01-11 11:45:48,508 INFO L226 Difference]: Without dead ends: 15 [2019-01-11 11:45:48,509 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.1s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:45:48,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states. [2019-01-11 11:45:48,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 14. [2019-01-11 11:45:48,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2019-01-11 11:45:48,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 28 transitions. [2019-01-11 11:45:48,519 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 28 transitions. Word has length 3 [2019-01-11 11:45:48,519 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:45:48,519 INFO L480 AbstractCegarLoop]: Abstraction has 14 states and 28 transitions. [2019-01-11 11:45:48,520 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:45:48,520 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 28 transitions. [2019-01-11 11:45:48,520 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:45:48,520 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:45:48,520 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1] [2019-01-11 11:45:48,520 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:45:48,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:48,521 INFO L82 PathProgramCache]: Analyzing trace with hash 941400, now seen corresponding path program 2 times [2019-01-11 11:45:48,521 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:45:48,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:48,522 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:45:48,522 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:48,522 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:45:48,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:45:48,589 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-11 11:45:48,590 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:45:48,590 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:45:48,590 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:45:48,591 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:45:48,591 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:45:48,591 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:45:48,601 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-11 11:45:48,601 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-11 11:45:48,616 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-11 11:45:48,616 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:45:48,622 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:45:48,673 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 21 [2019-01-11 11:45:48,692 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,693 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 27 [2019-01-11 11:45:48,700 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,702 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,703 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 37 [2019-01-11 11:45:48,709 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,711 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,715 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,716 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 51 [2019-01-11 11:45:48,736 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,738 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,741 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,750 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,751 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 66 [2019-01-11 11:45:48,753 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2019-01-11 11:45:48,794 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:45:48,814 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:45:48,832 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:45:48,845 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:45:48,871 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2019-01-11 11:45:48,872 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 4 variables, input treesize:31, output treesize:38 [2019-01-11 11:45:48,964 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,966 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,968 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,969 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,974 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,975 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,977 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,979 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,982 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,984 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,988 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:48,990 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 11 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 66 [2019-01-11 11:45:48,992 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:45:49,131 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2019-01-11 11:45:49,132 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 4 variables, input treesize:48, output treesize:38 [2019-01-11 11:45:49,191 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:49,200 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:49,205 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:49,206 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:49,207 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:49,208 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:49,209 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:49,209 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:49,211 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:49,212 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:49,213 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:49,215 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:49,216 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:45:49,218 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 13 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 78 [2019-01-11 11:45:49,219 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:45:49,304 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-1 vars, End of recursive call: 4 dim-0 vars, and 1 xjuncts. [2019-01-11 11:45:49,305 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 5 variables, input treesize:50, output treesize:38 [2019-01-11 11:45:49,335 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:45:49,335 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:45:49,364 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:45:49,383 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-11 11:45:49,383 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 3, 3] total 8 [2019-01-11 11:45:49,383 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-11 11:45:49,383 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-01-11 11:45:49,384 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-01-11 11:45:49,384 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=53, Unknown=0, NotChecked=0, Total=90 [2019-01-11 11:45:49,384 INFO L87 Difference]: Start difference. First operand 14 states and 28 transitions. Second operand 7 states. [2019-01-11 11:45:50,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:45:50,063 INFO L93 Difference]: Finished difference Result 47 states and 74 transitions. [2019-01-11 11:45:50,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-11 11:45:50,065 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 4 [2019-01-11 11:45:50,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:45:50,066 INFO L225 Difference]: With dead ends: 47 [2019-01-11 11:45:50,067 INFO L226 Difference]: Without dead ends: 45 [2019-01-11 11:45:50,067 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-01-11 11:45:50,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2019-01-11 11:45:50,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 19. [2019-01-11 11:45:50,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2019-01-11 11:45:50,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 45 transitions. [2019-01-11 11:45:50,083 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 45 transitions. Word has length 4 [2019-01-11 11:45:50,083 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:45:50,083 INFO L480 AbstractCegarLoop]: Abstraction has 19 states and 45 transitions. [2019-01-11 11:45:50,083 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-01-11 11:45:50,083 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 45 transitions. [2019-01-11 11:45:50,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:45:50,084 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:45:50,084 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-11 11:45:50,084 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:45:50,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:50,085 INFO L82 PathProgramCache]: Analyzing trace with hash 941462, now seen corresponding path program 1 times [2019-01-11 11:45:50,085 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:45:50,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:50,086 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:45:50,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:50,086 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:45:50,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:45:50,227 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:45:50,227 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:45:50,227 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:45:50,227 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-11 11:45:50,228 INFO L207 CegarAbsIntRunner]: [0], [18], [20], [23] [2019-01-11 11:45:50,230 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:45:50,230 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:46:10,346 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:46:10,347 INFO L272 AbstractInterpreter]: Visited 4 different actions 31 times. Merged at 2 different actions 9 times. Widened at 2 different actions 5 times. Found 11 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-11 11:46:10,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:46:10,347 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:46:10,936 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 66.67% of their original sizes. [2019-01-11 11:46:10,937 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:46:13,854 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_698 Int) (v_idx_699 Int) (v_idx_696 Int) (v_idx_697 Int) (v_idx_702 Int) (v_idx_703 Int) (v_idx_700 Int) (v_idx_701 Int) (v_idx_706 Int) (v_idx_704 Int) (v_idx_705 Int)) (exists ((v_v_4433_1 Int) (v_v_4434_1 Int) (v_v_4435_1 Int) (v_v_4436_1 Int) (v_v_4431_1 Int) (v_b_359_1 Int) (v_v_4437_1 Int) (v_b_358_1 Int) (v_v_4427_1 Int) (v_b_357_1 Int) (v_v_4429_1 Int) (v_b_356_1 Int)) (let ((.cse5 (+ v_b_357_1 1)) (.cse2 (+ v_b_356_1 2)) (.cse3 (+ v_b_356_1 1)) (.cse6 (+ c_ULTIMATE.start_main_p5 1)) (.cse4 (+ c_ULTIMATE.start_main_p4 1)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse8 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ c_ULTIMATE.start_main_p1 3)) (.cse0 (+ v_b_358_1 1))) (and (<= v_b_359_1 .cse0) (or (< v_idx_698 .cse1) (<= v_b_356_1 v_idx_698) (= (select |c_#memory_int| v_idx_698) v_v_4429_1)) (<= .cse2 c_ULTIMATE.start_main_p4) (<= .cse3 v_b_358_1) (or (<= c_ULTIMATE.start_main_p5 v_idx_704) (= (select |c_#memory_int| v_idx_704) v_v_4435_1) (< v_idx_704 .cse4)) (<= v_b_357_1 .cse3) (<= .cse5 v_b_359_1) (<= v_v_4434_1 v_v_4436_1) (<= (+ v_b_358_1 2) c_ULTIMATE.start_main_p5) (<= .cse5 c_ULTIMATE.start_main_p4) (or (<= v_b_357_1 v_idx_699) (< v_idx_699 v_b_356_1) (= (select |c_#memory_int| v_idx_699) 0)) (<= .cse4 c_ULTIMATE.start_main_p5) (<= (* 2 v_v_4434_1) 0) (<= .cse2 v_b_359_1) (<= .cse0 c_ULTIMATE.start_main_p4) (<= .cse3 v_b_357_1) (or (= (select |c_#memory_int| v_idx_706) v_v_4437_1) (< v_idx_706 .cse6)) (or (<= v_b_358_1 v_idx_700) (= (select |c_#memory_int| v_idx_700) v_v_4431_1) (< v_idx_700 v_b_357_1)) (<= v_b_357_1 v_b_358_1) (<= .cse7 c_ULTIMATE.start_main_p4) (or (= (select |c_#memory_int| v_idx_697) 0) (< v_idx_697 c_ULTIMATE.start_main_p1) (<= .cse1 v_idx_697)) (or (<= .cse6 v_idx_705) (= (select |c_#memory_int| v_idx_705) v_v_4436_1) (< v_idx_705 c_ULTIMATE.start_main_p5)) (or (<= .cse4 v_idx_703) (< v_idx_703 c_ULTIMATE.start_main_p4) (= (select |c_#memory_int| v_idx_703) v_v_4434_1)) (<= .cse8 v_b_357_1) (<= v_b_359_1 c_ULTIMATE.start_main_p4) (<= .cse1 v_b_356_1) (<= (+ v_b_356_1 3) c_ULTIMATE.start_main_p5) (or (< v_idx_702 v_b_359_1) (<= c_ULTIMATE.start_main_p4 v_idx_702) (= (select |c_#memory_int| v_idx_702) v_v_4433_1)) (or (= (select |c_#memory_int| v_idx_701) 0) (< v_idx_701 v_b_358_1) (<= v_b_359_1 v_idx_701)) (<= (+ c_ULTIMATE.start_main_p1 4) c_ULTIMATE.start_main_p5) (<= v_v_4434_1 0) (<= 0 v_v_4436_1) (<= 0 (* 2 v_v_4436_1)) (<= (+ v_b_359_1 1) c_ULTIMATE.start_main_p5) (<= .cse8 v_b_358_1) (<= .cse7 v_b_359_1) (<= .cse0 v_b_359_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_696) (= (select |c_#memory_int| v_idx_696) v_v_4427_1)) (<= (+ v_b_357_1 2) c_ULTIMATE.start_main_p5))))) is different from false [2019-01-11 11:46:16,493 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_710 Int) (v_idx_713 Int) (v_idx_714 Int) (v_idx_711 Int) (v_idx_712 Int) (v_idx_717 Int) (v_idx_707 Int) (v_idx_715 Int) (v_idx_716 Int) (v_idx_708 Int) (v_idx_709 Int)) (exists ((v_v_4433_1 Int) (v_v_4434_1 Int) (v_v_4435_1 Int) (v_v_4436_1 Int) (v_v_4431_1 Int) (v_b_359_1 Int) (v_v_4437_1 Int) (v_b_358_1 Int) (v_v_4427_1 Int) (v_b_357_1 Int) (v_b_356_1 Int) (v_v_4429_1 Int) (v_b_361_1 Int) (v_b_360_1 Int)) (let ((.cse1 (+ v_b_357_1 1)) (.cse2 (+ v_b_356_1 1)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse12 (+ v_b_356_1 3)) (.cse5 (+ v_b_360_1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse10 (+ v_b_359_1 1)) (.cse4 (+ v_b_358_1 2)) (.cse7 (+ c_ULTIMATE.start_main_p5 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 2)) (.cse9 (+ c_ULTIMATE.start_main_p1 3)) (.cse0 (+ v_b_358_1 1)) (.cse13 (+ v_b_357_1 2)) (.cse6 (+ v_b_356_1 2))) (and (<= v_b_359_1 .cse0) (<= .cse1 v_b_360_1) (<= .cse2 v_b_358_1) (or (< v_idx_715 v_b_361_1) (<= c_ULTIMATE.start_main_p5 v_idx_715) (= (select |c_#memory_int| v_idx_715) v_v_4435_1)) (<= v_b_357_1 .cse2) (<= .cse1 v_b_359_1) (<= v_v_4434_1 v_v_4436_1) (<= .cse3 v_b_361_1) (<= .cse4 c_ULTIMATE.start_main_p5) (<= .cse5 v_b_361_1) (or (<= v_b_361_1 v_idx_714) (= (select |c_#memory_int| v_idx_714) v_v_4434_1) (< v_idx_714 v_b_360_1)) (or (< v_idx_710 v_b_356_1) (<= v_b_357_1 v_idx_710) (= (select |c_#memory_int| v_idx_710) 0)) (or (< v_idx_711 v_b_357_1) (<= v_b_358_1 v_idx_711) (= (select |c_#memory_int| v_idx_711) v_v_4431_1)) (or (<= v_b_360_1 v_idx_713) (< v_idx_713 v_b_359_1) (= (select |c_#memory_int| v_idx_713) v_v_4433_1)) (<= .cse5 c_ULTIMATE.start_main_p5) (<= (* 2 v_v_4434_1) 0) (<= .cse6 v_b_359_1) (<= .cse2 v_b_357_1) (or (= (select |c_#memory_int| v_idx_717) v_v_4437_1) (< v_idx_717 .cse7)) (or (= (select |c_#memory_int| v_idx_709) v_v_4429_1) (<= v_b_356_1 v_idx_709) (< v_idx_709 .cse8)) (<= v_b_357_1 v_b_358_1) (or (<= v_b_359_1 v_idx_712) (= (select |c_#memory_int| v_idx_712) 0) (< v_idx_712 v_b_358_1)) (<= .cse0 v_b_360_1) (<= .cse9 v_b_360_1) (<= .cse10 v_b_361_1) (or (= (select |c_#memory_int| v_idx_707) v_v_4427_1) (<= c_ULTIMATE.start_main_p1 v_idx_707)) (<= v_b_361_1 c_ULTIMATE.start_main_p5) (<= .cse11 v_b_357_1) (<= v_b_359_1 v_b_360_1) (or (= (select |c_#memory_int| v_idx_708) 0) (<= .cse8 v_idx_708) (< v_idx_708 c_ULTIMATE.start_main_p1)) (<= .cse8 v_b_356_1) (<= .cse12 c_ULTIMATE.start_main_p5) (<= .cse12 v_b_361_1) (<= v_b_361_1 .cse5) (<= .cse3 c_ULTIMATE.start_main_p5) (<= v_v_4434_1 0) (<= 0 v_v_4436_1) (<= 0 (* 2 v_v_4436_1)) (<= .cse13 v_b_361_1) (<= .cse10 c_ULTIMATE.start_main_p5) (<= .cse4 v_b_361_1) (or (<= .cse7 v_idx_716) (= (select |c_#memory_int| v_idx_716) v_v_4436_1) (< v_idx_716 c_ULTIMATE.start_main_p5)) (<= .cse11 v_b_358_1) (<= .cse9 v_b_359_1) (<= .cse0 v_b_359_1) (<= .cse13 c_ULTIMATE.start_main_p5) (<= .cse6 v_b_360_1))))) is different from false [2019-01-11 11:46:20,954 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_720 Int) (v_idx_721 Int) (v_idx_724 Int) (v_idx_725 Int) (v_idx_722 Int) (v_idx_723 Int) (v_idx_728 Int) (v_idx_718 Int) (v_idx_726 Int) (v_idx_727 Int) (v_idx_719 Int)) (exists ((v_v_4433_1 Int) (v_v_4434_1 Int) (v_v_4435_1 Int) (v_v_4436_1 Int) (v_v_4431_1 Int) (v_b_359_1 Int) (v_v_4437_1 Int) (v_b_358_1 Int) (v_v_4427_1 Int) (v_b_357_1 Int) (v_b_356_1 Int) (v_v_4429_1 Int) (v_b_363_1 Int) (v_b_362_1 Int) (v_b_361_1 Int) (v_b_360_1 Int)) (let ((.cse1 (+ v_b_357_1 1)) (.cse6 (+ v_b_359_1 1)) (.cse2 (+ v_b_356_1 1)) (.cse11 (+ v_b_362_1 1)) (.cse0 (+ v_b_358_1 1)) (.cse10 (+ c_ULTIMATE.start_main_p1 3)) (.cse4 (+ v_b_356_1 3)) (.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse9 (+ v_b_360_1 1)) (.cse13 (+ v_b_357_1 2)) (.cse12 (+ v_b_358_1 2)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse5 (+ v_b_356_1 2))) (and (<= v_b_359_1 .cse0) (<= .cse1 v_b_360_1) (<= v_b_357_1 .cse2) (<= .cse1 v_b_359_1) (<= .cse3 v_b_361_1) (<= .cse4 v_b_362_1) (<= (* 2 v_v_4434_1) 0) (<= .cse5 v_b_359_1) (<= .cse2 v_b_357_1) (or (= (select |c_#memory_int| v_idx_725) v_v_4434_1) (<= v_b_361_1 v_idx_725) (< v_idx_725 v_b_360_1)) (<= v_b_357_1 v_b_358_1) (<= .cse6 v_b_362_1) (<= .cse6 v_b_361_1) (<= (+ v_b_360_1 2) v_b_363_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_718) (= (select |c_#memory_int| v_idx_718) v_v_4427_1)) (<= .cse7 v_b_357_1) (<= .cse8 v_b_356_1) (<= v_b_361_1 .cse9) (<= v_v_4434_1 0) (or (< v_idx_727 v_b_362_1) (= (select |c_#memory_int| v_idx_727) v_v_4436_1) (<= v_b_363_1 v_idx_727)) (<= 0 v_v_4436_1) (<= (+ v_b_356_1 4) v_b_363_1) (<= 0 (* 2 v_v_4436_1)) (or (<= v_b_359_1 v_idx_723) (< v_idx_723 v_b_358_1) (= (select |c_#memory_int| v_idx_723) 0)) (<= .cse10 v_b_359_1) (<= .cse0 v_b_359_1) (or (= (select |c_#memory_int| v_idx_728) v_v_4437_1) (< v_idx_728 v_b_363_1)) (<= .cse2 v_b_358_1) (or (<= v_b_360_1 v_idx_724) (= (select |c_#memory_int| v_idx_724) v_v_4433_1) (< v_idx_724 v_b_359_1)) (<= v_v_4434_1 v_v_4436_1) (<= .cse11 v_b_363_1) (<= .cse9 v_b_361_1) (or (< v_idx_721 v_b_356_1) (<= v_b_357_1 v_idx_721) (= (select |c_#memory_int| v_idx_721) 0)) (<= v_b_363_1 .cse11) (<= (+ v_b_361_1 1) v_b_363_1) (or (= (select |c_#memory_int| v_idx_726) v_v_4435_1) (< v_idx_726 v_b_361_1) (<= v_b_362_1 v_idx_726)) (<= (+ v_b_358_1 3) v_b_363_1) (<= .cse0 v_b_360_1) (<= .cse10 v_b_360_1) (<= .cse12 v_b_362_1) (<= v_b_359_1 v_b_360_1) (<= .cse4 v_b_361_1) (<= v_b_361_1 v_b_362_1) (or (< v_idx_722 v_b_357_1) (= (select |c_#memory_int| v_idx_722) v_v_4431_1) (<= v_b_358_1 v_idx_722)) (or (= (select |c_#memory_int| v_idx_719) 0) (<= .cse8 v_idx_719) (< v_idx_719 c_ULTIMATE.start_main_p1)) (<= (+ v_b_357_1 3) v_b_363_1) (<= .cse3 v_b_362_1) (<= .cse9 v_b_362_1) (<= .cse13 v_b_361_1) (<= .cse13 v_b_362_1) (<= (+ v_b_359_1 2) v_b_363_1) (<= .cse12 v_b_361_1) (<= .cse7 v_b_358_1) (or (<= v_b_356_1 v_idx_720) (< v_idx_720 .cse8) (= (select |c_#memory_int| v_idx_720) v_v_4429_1)) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_363_1) (<= .cse5 v_b_360_1))))) is different from false [2019-01-11 11:46:21,125 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-11 11:46:21,125 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:46:21,125 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:46:21,125 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 6 [2019-01-11 11:46:21,125 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:46:21,126 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-11 11:46:21,126 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-11 11:46:21,126 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:46:21,126 INFO L87 Difference]: Start difference. First operand 19 states and 45 transitions. Second operand 5 states. [2019-01-11 11:46:24,408 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_710 Int) (v_idx_713 Int) (v_idx_714 Int) (v_idx_711 Int) (v_idx_712 Int) (v_idx_717 Int) (v_idx_707 Int) (v_idx_715 Int) (v_idx_716 Int) (v_idx_708 Int) (v_idx_709 Int)) (exists ((v_v_4433_1 Int) (v_v_4434_1 Int) (v_v_4435_1 Int) (v_v_4436_1 Int) (v_v_4431_1 Int) (v_b_359_1 Int) (v_v_4437_1 Int) (v_b_358_1 Int) (v_v_4427_1 Int) (v_b_357_1 Int) (v_b_356_1 Int) (v_v_4429_1 Int) (v_b_361_1 Int) (v_b_360_1 Int)) (let ((.cse1 (+ v_b_357_1 1)) (.cse2 (+ v_b_356_1 1)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse12 (+ v_b_356_1 3)) (.cse5 (+ v_b_360_1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse10 (+ v_b_359_1 1)) (.cse4 (+ v_b_358_1 2)) (.cse7 (+ c_ULTIMATE.start_main_p5 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 2)) (.cse9 (+ c_ULTIMATE.start_main_p1 3)) (.cse0 (+ v_b_358_1 1)) (.cse13 (+ v_b_357_1 2)) (.cse6 (+ v_b_356_1 2))) (and (<= v_b_359_1 .cse0) (<= .cse1 v_b_360_1) (<= .cse2 v_b_358_1) (or (< v_idx_715 v_b_361_1) (<= c_ULTIMATE.start_main_p5 v_idx_715) (= (select |c_#memory_int| v_idx_715) v_v_4435_1)) (<= v_b_357_1 .cse2) (<= .cse1 v_b_359_1) (<= v_v_4434_1 v_v_4436_1) (<= .cse3 v_b_361_1) (<= .cse4 c_ULTIMATE.start_main_p5) (<= .cse5 v_b_361_1) (or (<= v_b_361_1 v_idx_714) (= (select |c_#memory_int| v_idx_714) v_v_4434_1) (< v_idx_714 v_b_360_1)) (or (< v_idx_710 v_b_356_1) (<= v_b_357_1 v_idx_710) (= (select |c_#memory_int| v_idx_710) 0)) (or (< v_idx_711 v_b_357_1) (<= v_b_358_1 v_idx_711) (= (select |c_#memory_int| v_idx_711) v_v_4431_1)) (or (<= v_b_360_1 v_idx_713) (< v_idx_713 v_b_359_1) (= (select |c_#memory_int| v_idx_713) v_v_4433_1)) (<= .cse5 c_ULTIMATE.start_main_p5) (<= (* 2 v_v_4434_1) 0) (<= .cse6 v_b_359_1) (<= .cse2 v_b_357_1) (or (= (select |c_#memory_int| v_idx_717) v_v_4437_1) (< v_idx_717 .cse7)) (or (= (select |c_#memory_int| v_idx_709) v_v_4429_1) (<= v_b_356_1 v_idx_709) (< v_idx_709 .cse8)) (<= v_b_357_1 v_b_358_1) (or (<= v_b_359_1 v_idx_712) (= (select |c_#memory_int| v_idx_712) 0) (< v_idx_712 v_b_358_1)) (<= .cse0 v_b_360_1) (<= .cse9 v_b_360_1) (<= .cse10 v_b_361_1) (or (= (select |c_#memory_int| v_idx_707) v_v_4427_1) (<= c_ULTIMATE.start_main_p1 v_idx_707)) (<= v_b_361_1 c_ULTIMATE.start_main_p5) (<= .cse11 v_b_357_1) (<= v_b_359_1 v_b_360_1) (or (= (select |c_#memory_int| v_idx_708) 0) (<= .cse8 v_idx_708) (< v_idx_708 c_ULTIMATE.start_main_p1)) (<= .cse8 v_b_356_1) (<= .cse12 c_ULTIMATE.start_main_p5) (<= .cse12 v_b_361_1) (<= v_b_361_1 .cse5) (<= .cse3 c_ULTIMATE.start_main_p5) (<= v_v_4434_1 0) (<= 0 v_v_4436_1) (<= 0 (* 2 v_v_4436_1)) (<= .cse13 v_b_361_1) (<= .cse10 c_ULTIMATE.start_main_p5) (<= .cse4 v_b_361_1) (or (<= .cse7 v_idx_716) (= (select |c_#memory_int| v_idx_716) v_v_4436_1) (< v_idx_716 c_ULTIMATE.start_main_p5)) (<= .cse11 v_b_358_1) (<= .cse9 v_b_359_1) (<= .cse0 v_b_359_1) (<= .cse13 c_ULTIMATE.start_main_p5) (<= .cse6 v_b_360_1))))) (forall ((v_idx_698 Int) (v_idx_699 Int) (v_idx_696 Int) (v_idx_697 Int) (v_idx_702 Int) (v_idx_703 Int) (v_idx_700 Int) (v_idx_701 Int) (v_idx_706 Int) (v_idx_704 Int) (v_idx_705 Int)) (exists ((v_v_4433_1 Int) (v_v_4434_1 Int) (v_v_4435_1 Int) (v_v_4436_1 Int) (v_v_4431_1 Int) (v_b_359_1 Int) (v_v_4437_1 Int) (v_b_358_1 Int) (v_v_4427_1 Int) (v_b_357_1 Int) (v_v_4429_1 Int) (v_b_356_1 Int)) (let ((.cse19 (+ v_b_357_1 1)) (.cse16 (+ v_b_356_1 2)) (.cse17 (+ v_b_356_1 1)) (.cse20 (+ c_ULTIMATE.start_main_p5 1)) (.cse18 (+ c_ULTIMATE.start_main_p4 1)) (.cse15 (+ c_ULTIMATE.start_main_p1 1)) (.cse22 (+ c_ULTIMATE.start_main_p1 2)) (.cse21 (+ c_ULTIMATE.start_main_p1 3)) (.cse14 (+ v_b_358_1 1))) (and (<= v_b_359_1 .cse14) (or (< v_idx_698 .cse15) (<= v_b_356_1 v_idx_698) (= (select |c_#memory_int| v_idx_698) v_v_4429_1)) (<= .cse16 c_ULTIMATE.start_main_p4) (<= .cse17 v_b_358_1) (or (<= c_ULTIMATE.start_main_p5 v_idx_704) (= (select |c_#memory_int| v_idx_704) v_v_4435_1) (< v_idx_704 .cse18)) (<= v_b_357_1 .cse17) (<= .cse19 v_b_359_1) (<= v_v_4434_1 v_v_4436_1) (<= (+ v_b_358_1 2) c_ULTIMATE.start_main_p5) (<= .cse19 c_ULTIMATE.start_main_p4) (or (<= v_b_357_1 v_idx_699) (< v_idx_699 v_b_356_1) (= (select |c_#memory_int| v_idx_699) 0)) (<= .cse18 c_ULTIMATE.start_main_p5) (<= (* 2 v_v_4434_1) 0) (<= .cse16 v_b_359_1) (<= .cse14 c_ULTIMATE.start_main_p4) (<= .cse17 v_b_357_1) (or (= (select |c_#memory_int| v_idx_706) v_v_4437_1) (< v_idx_706 .cse20)) (or (<= v_b_358_1 v_idx_700) (= (select |c_#memory_int| v_idx_700) v_v_4431_1) (< v_idx_700 v_b_357_1)) (<= v_b_357_1 v_b_358_1) (<= .cse21 c_ULTIMATE.start_main_p4) (or (= (select |c_#memory_int| v_idx_697) 0) (< v_idx_697 c_ULTIMATE.start_main_p1) (<= .cse15 v_idx_697)) (or (<= .cse20 v_idx_705) (= (select |c_#memory_int| v_idx_705) v_v_4436_1) (< v_idx_705 c_ULTIMATE.start_main_p5)) (or (<= .cse18 v_idx_703) (< v_idx_703 c_ULTIMATE.start_main_p4) (= (select |c_#memory_int| v_idx_703) v_v_4434_1)) (<= .cse22 v_b_357_1) (<= v_b_359_1 c_ULTIMATE.start_main_p4) (<= .cse15 v_b_356_1) (<= (+ v_b_356_1 3) c_ULTIMATE.start_main_p5) (or (< v_idx_702 v_b_359_1) (<= c_ULTIMATE.start_main_p4 v_idx_702) (= (select |c_#memory_int| v_idx_702) v_v_4433_1)) (or (= (select |c_#memory_int| v_idx_701) 0) (< v_idx_701 v_b_358_1) (<= v_b_359_1 v_idx_701)) (<= (+ c_ULTIMATE.start_main_p1 4) c_ULTIMATE.start_main_p5) (<= v_v_4434_1 0) (<= 0 v_v_4436_1) (<= 0 (* 2 v_v_4436_1)) (<= (+ v_b_359_1 1) c_ULTIMATE.start_main_p5) (<= .cse22 v_b_358_1) (<= .cse21 v_b_359_1) (<= .cse14 v_b_359_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_696) (= (select |c_#memory_int| v_idx_696) v_v_4427_1)) (<= (+ v_b_357_1 2) c_ULTIMATE.start_main_p5))))) (forall ((v_idx_720 Int) (v_idx_721 Int) (v_idx_724 Int) (v_idx_725 Int) (v_idx_722 Int) (v_idx_723 Int) (v_idx_728 Int) (v_idx_718 Int) (v_idx_726 Int) (v_idx_727 Int) (v_idx_719 Int)) (exists ((v_v_4433_1 Int) (v_v_4434_1 Int) (v_v_4435_1 Int) (v_v_4436_1 Int) (v_v_4431_1 Int) (v_b_359_1 Int) (v_v_4437_1 Int) (v_b_358_1 Int) (v_v_4427_1 Int) (v_b_357_1 Int) (v_b_356_1 Int) (v_v_4429_1 Int) (v_b_363_1 Int) (v_b_362_1 Int) (v_b_361_1 Int) (v_b_360_1 Int)) (let ((.cse24 (+ v_b_357_1 1)) (.cse29 (+ v_b_359_1 1)) (.cse25 (+ v_b_356_1 1)) (.cse34 (+ v_b_362_1 1)) (.cse23 (+ v_b_358_1 1)) (.cse33 (+ c_ULTIMATE.start_main_p1 3)) (.cse27 (+ v_b_356_1 3)) (.cse26 (+ c_ULTIMATE.start_main_p1 4)) (.cse32 (+ v_b_360_1 1)) (.cse36 (+ v_b_357_1 2)) (.cse35 (+ v_b_358_1 2)) (.cse30 (+ c_ULTIMATE.start_main_p1 2)) (.cse31 (+ c_ULTIMATE.start_main_p1 1)) (.cse28 (+ v_b_356_1 2))) (and (<= v_b_359_1 .cse23) (<= .cse24 v_b_360_1) (<= v_b_357_1 .cse25) (<= .cse24 v_b_359_1) (<= .cse26 v_b_361_1) (<= .cse27 v_b_362_1) (<= (* 2 v_v_4434_1) 0) (<= .cse28 v_b_359_1) (<= .cse25 v_b_357_1) (or (= (select |c_#memory_int| v_idx_725) v_v_4434_1) (<= v_b_361_1 v_idx_725) (< v_idx_725 v_b_360_1)) (<= v_b_357_1 v_b_358_1) (<= .cse29 v_b_362_1) (<= .cse29 v_b_361_1) (<= (+ v_b_360_1 2) v_b_363_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_718) (= (select |c_#memory_int| v_idx_718) v_v_4427_1)) (<= .cse30 v_b_357_1) (<= .cse31 v_b_356_1) (<= v_b_361_1 .cse32) (<= v_v_4434_1 0) (or (< v_idx_727 v_b_362_1) (= (select |c_#memory_int| v_idx_727) v_v_4436_1) (<= v_b_363_1 v_idx_727)) (<= 0 v_v_4436_1) (<= (+ v_b_356_1 4) v_b_363_1) (<= 0 (* 2 v_v_4436_1)) (or (<= v_b_359_1 v_idx_723) (< v_idx_723 v_b_358_1) (= (select |c_#memory_int| v_idx_723) 0)) (<= .cse33 v_b_359_1) (<= .cse23 v_b_359_1) (or (= (select |c_#memory_int| v_idx_728) v_v_4437_1) (< v_idx_728 v_b_363_1)) (<= .cse25 v_b_358_1) (or (<= v_b_360_1 v_idx_724) (= (select |c_#memory_int| v_idx_724) v_v_4433_1) (< v_idx_724 v_b_359_1)) (<= v_v_4434_1 v_v_4436_1) (<= .cse34 v_b_363_1) (<= .cse32 v_b_361_1) (or (< v_idx_721 v_b_356_1) (<= v_b_357_1 v_idx_721) (= (select |c_#memory_int| v_idx_721) 0)) (<= v_b_363_1 .cse34) (<= (+ v_b_361_1 1) v_b_363_1) (or (= (select |c_#memory_int| v_idx_726) v_v_4435_1) (< v_idx_726 v_b_361_1) (<= v_b_362_1 v_idx_726)) (<= (+ v_b_358_1 3) v_b_363_1) (<= .cse23 v_b_360_1) (<= .cse33 v_b_360_1) (<= .cse35 v_b_362_1) (<= v_b_359_1 v_b_360_1) (<= .cse27 v_b_361_1) (<= v_b_361_1 v_b_362_1) (or (< v_idx_722 v_b_357_1) (= (select |c_#memory_int| v_idx_722) v_v_4431_1) (<= v_b_358_1 v_idx_722)) (or (= (select |c_#memory_int| v_idx_719) 0) (<= .cse31 v_idx_719) (< v_idx_719 c_ULTIMATE.start_main_p1)) (<= (+ v_b_357_1 3) v_b_363_1) (<= .cse26 v_b_362_1) (<= .cse32 v_b_362_1) (<= .cse36 v_b_361_1) (<= .cse36 v_b_362_1) (<= (+ v_b_359_1 2) v_b_363_1) (<= .cse35 v_b_361_1) (<= .cse30 v_b_358_1) (or (<= v_b_356_1 v_idx_720) (< v_idx_720 .cse31) (= (select |c_#memory_int| v_idx_720) v_v_4429_1)) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_363_1) (<= .cse28 v_b_360_1)))))) is different from false