java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml -s ../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf -i ../../../trunk/examples/programs/heapseparator/speedup-poc-dd-6-limited.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.24-df3cc4e-m [2019-01-11 11:44:34,257 INFO L170 SettingsManager]: Resetting all preferences to default values... [2019-01-11 11:44:34,259 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2019-01-11 11:44:34,271 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-01-11 11:44:34,271 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-01-11 11:44:34,272 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-01-11 11:44:34,274 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-01-11 11:44:34,276 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2019-01-11 11:44:34,278 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-01-11 11:44:34,281 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-01-11 11:44:34,284 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-01-11 11:44:34,284 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-01-11 11:44:34,286 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-01-11 11:44:34,287 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-01-11 11:44:34,292 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-01-11 11:44:34,293 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-01-11 11:44:34,293 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-01-11 11:44:34,300 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-01-11 11:44:34,303 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2019-01-11 11:44:34,306 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-01-11 11:44:34,307 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-01-11 11:44:34,312 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-01-11 11:44:34,316 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-01-11 11:44:34,316 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-01-11 11:44:34,316 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2019-01-11 11:44:34,317 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2019-01-11 11:44:34,320 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-01-11 11:44:34,321 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-01-11 11:44:34,321 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2019-01-11 11:44:34,325 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-01-11 11:44:34,325 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2019-01-11 11:44:34,326 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-01-11 11:44:34,326 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-01-11 11:44:34,326 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2019-01-11 11:44:34,329 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2019-01-11 11:44:34,329 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2019-01-11 11:44:34,330 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf [2019-01-11 11:44:34,352 INFO L110 SettingsManager]: Loading preferences was successful [2019-01-11 11:44:34,352 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2019-01-11 11:44:34,353 INFO L131 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2019-01-11 11:44:34,353 INFO L133 SettingsManager]: * Show backtranslation warnings=false [2019-01-11 11:44:34,353 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-01-11 11:44:34,353 INFO L133 SettingsManager]: * User list type=DISABLED [2019-01-11 11:44:34,354 INFO L133 SettingsManager]: * Inline calls to unimplemented procedures=true [2019-01-11 11:44:34,354 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-01-11 11:44:34,354 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-01-11 11:44:34,354 INFO L133 SettingsManager]: * Underlying domain=OctagonDomain [2019-01-11 11:44:34,354 INFO L133 SettingsManager]: * Abstract domain=ArrayDomain [2019-01-11 11:44:34,355 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-01-11 11:44:34,355 INFO L133 SettingsManager]: * Interval Domain=false [2019-01-11 11:44:34,356 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-01-11 11:44:34,356 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2019-01-11 11:44:34,356 INFO L133 SettingsManager]: * Use SBE=true [2019-01-11 11:44:34,356 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-01-11 11:44:34,357 INFO L133 SettingsManager]: * sizeof long=4 [2019-01-11 11:44:34,357 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2019-01-11 11:44:34,357 INFO L133 SettingsManager]: * sizeof POINTER=4 [2019-01-11 11:44:34,357 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2019-01-11 11:44:34,357 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-01-11 11:44:34,357 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-01-11 11:44:34,359 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-01-11 11:44:34,359 INFO L133 SettingsManager]: * sizeof long double=12 [2019-01-11 11:44:34,360 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2019-01-11 11:44:34,360 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-01-11 11:44:34,360 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-01-11 11:44:34,360 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-01-11 11:44:34,360 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2019-01-11 11:44:34,361 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-11 11:44:34,362 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-01-11 11:44:34,362 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-01-11 11:44:34,362 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-01-11 11:44:34,362 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2019-01-11 11:44:34,362 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-01-11 11:44:34,362 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in [2019-01-11 11:44:34,363 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-01-11 11:44:34,363 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2019-01-11 11:44:34,395 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-01-11 11:44:34,408 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-01-11 11:44:34,411 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-01-11 11:44:34,413 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2019-01-11 11:44:34,413 INFO L276 PluginConnector]: Boogie PL CUP Parser initialized [2019-01-11 11:44:34,414 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-6-limited.bpl [2019-01-11 11:44:34,414 INFO L111 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-6-limited.bpl' [2019-01-11 11:44:34,448 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-01-11 11:44:34,449 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-01-11 11:44:34,450 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-01-11 11:44:34,450 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-01-11 11:44:34,450 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2019-01-11 11:44:34,466 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:34" (1/1) ... [2019-01-11 11:44:34,478 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:34" (1/1) ... [2019-01-11 11:44:34,504 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-01-11 11:44:34,505 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-01-11 11:44:34,505 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-01-11 11:44:34,505 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2019-01-11 11:44:34,516 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:34" (1/1) ... [2019-01-11 11:44:34,516 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:34" (1/1) ... [2019-01-11 11:44:34,518 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:34" (1/1) ... [2019-01-11 11:44:34,518 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:34" (1/1) ... [2019-01-11 11:44:34,522 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:34" (1/1) ... [2019-01-11 11:44:34,526 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:34" (1/1) ... [2019-01-11 11:44:34,527 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:34" (1/1) ... [2019-01-11 11:44:34,529 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-01-11 11:44:34,529 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-01-11 11:44:34,529 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-01-11 11:44:34,529 INFO L276 PluginConnector]: RCFGBuilder initialized [2019-01-11 11:44:34,530 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:34" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-11 11:44:34,594 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-01-11 11:44:34,594 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-01-11 11:44:34,920 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-01-11 11:44:34,920 INFO L286 CfgBuilder]: Removed 15 assue(true) statements. [2019-01-11 11:44:34,921 INFO L202 PluginConnector]: Adding new model speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.01 11:44:34 BoogieIcfgContainer [2019-01-11 11:44:34,922 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-01-11 11:44:34,923 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-01-11 11:44:34,923 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-01-11 11:44:34,937 INFO L276 PluginConnector]: TraceAbstraction initialized [2019-01-11 11:44:34,938 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:34" (1/2) ... [2019-01-11 11:44:34,939 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@210edaed and model type speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.01 11:44:34, skipping insertion in model container [2019-01-11 11:44:34,939 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-6-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.01 11:44:34" (2/2) ... [2019-01-11 11:44:34,942 INFO L112 eAbstractionObserver]: Analyzing ICFG speedup-poc-dd-6-limited.bpl [2019-01-11 11:44:34,961 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-01-11 11:44:34,969 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 6 error locations. [2019-01-11 11:44:34,986 INFO L257 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2019-01-11 11:44:35,019 INFO L382 AbstractCegarLoop]: Interprodecural is true [2019-01-11 11:44:35,019 INFO L383 AbstractCegarLoop]: Hoare is true [2019-01-11 11:44:35,019 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-01-11 11:44:35,020 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-01-11 11:44:35,020 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-01-11 11:44:35,020 INFO L387 AbstractCegarLoop]: Difference is false [2019-01-11 11:44:35,020 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-01-11 11:44:35,020 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-01-11 11:44:35,036 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states. [2019-01-11 11:44:35,042 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3 [2019-01-11 11:44:35,043 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:44:35,044 INFO L402 BasicCegarLoop]: trace histogram [1, 1] [2019-01-11 11:44:35,047 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:44:35,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:35,053 INFO L82 PathProgramCache]: Analyzing trace with hash 988, now seen corresponding path program 1 times [2019-01-11 11:44:35,055 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:44:35,102 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:35,103 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:44:35,103 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:35,103 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:44:35,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:44:35,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:44:35,225 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-11 11:44:35,226 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-11 11:44:35,226 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:44:35,229 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-11 11:44:35,239 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-11 11:44:35,240 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:44:35,242 INFO L87 Difference]: Start difference. First operand 15 states. Second operand 3 states. [2019-01-11 11:44:35,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:44:35,486 INFO L93 Difference]: Finished difference Result 29 states and 39 transitions. [2019-01-11 11:44:35,487 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:44:35,488 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 2 [2019-01-11 11:44:35,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:44:35,502 INFO L225 Difference]: With dead ends: 29 [2019-01-11 11:44:35,502 INFO L226 Difference]: Without dead ends: 24 [2019-01-11 11:44:35,505 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:44:35,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2019-01-11 11:44:35,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 14. [2019-01-11 11:44:35,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2019-01-11 11:44:35,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 25 transitions. [2019-01-11 11:44:35,542 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 25 transitions. Word has length 2 [2019-01-11 11:44:35,543 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:44:35,543 INFO L480 AbstractCegarLoop]: Abstraction has 14 states and 25 transitions. [2019-01-11 11:44:35,543 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-11 11:44:35,544 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 25 transitions. [2019-01-11 11:44:35,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:44:35,544 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:44:35,545 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:44:35,545 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:44:35,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:35,546 INFO L82 PathProgramCache]: Analyzing trace with hash 30376, now seen corresponding path program 1 times [2019-01-11 11:44:35,546 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:44:35,547 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:35,547 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:44:35,547 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:35,547 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:44:35,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:44:35,706 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:44:35,707 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:44:35,707 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:44:35,708 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:44:35,710 INFO L207 CegarAbsIntRunner]: [0], [18], [27] [2019-01-11 11:44:35,761 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:44:35,761 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:44:49,007 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:44:49,009 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:44:49,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:49,014 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:44:49,688 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 75% of their original sizes. [2019-01-11 11:44:49,688 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:44:52,041 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_104 Int) (v_idx_115 Int) (v_idx_105 Int) (v_idx_113 Int) (v_idx_103 Int) (v_idx_114 Int) (v_idx_108 Int) (v_idx_109 Int) (v_idx_106 Int) (v_idx_107 Int) (v_idx_111 Int) (v_idx_112 Int) (v_idx_110 Int)) (exists ((v_v_1411_1 Int) (v_v_1417_1 Int) (v_b_159_1 Int) (v_v_1407_1 Int) (v_v_1419_1 Int) (v_b_158_1 Int) (v_v_1413_1 Int) (v_v_1415_1 Int) (v_v_1414_1 Int) (v_b_153_1 Int) (v_b_152_1 Int) (v_b_151_1 Int) (v_b_150_1 Int) (v_b_157_1 Int) (v_v_1409_1 Int) (v_b_156_1 Int)) (let ((.cse7 (+ v_b_150_1 4)) (.cse0 (+ c_ULTIMATE.start_main_p4 2)) (.cse8 (+ v_b_152_1 3)) (.cse6 (+ c_ULTIMATE.start_main_p1 1)) (.cse9 (+ v_b_158_1 1)) (.cse1 (+ v_b_153_1 2)) (.cse4 (+ v_b_150_1 1)) (.cse11 (+ v_b_151_1 1)) (.cse12 (+ c_ULTIMATE.start_main_p1 5)) (.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse15 (+ c_ULTIMATE.start_main_p1 3)) (.cse5 (+ v_b_156_1 1)) (.cse13 (+ v_b_150_1 2)) (.cse10 (+ v_b_151_1 3)) (.cse3 (+ c_ULTIMATE.start_main_p4 1)) (.cse14 (+ v_b_152_1 1))) (and (<= .cse0 v_b_157_1) (<= (+ v_b_151_1 4) v_b_159_1) (<= .cse1 v_b_158_1) (<= (+ v_b_152_1 2) v_b_156_1) (<= (+ c_ULTIMATE.start_main_p4 3) v_b_159_1) (or (= (select |c_#memory_int| v_idx_113) v_v_1417_1) (< v_idx_113 v_b_157_1) (<= v_b_158_1 v_idx_113)) (<= .cse2 v_b_152_1) (or (< v_idx_110 c_ULTIMATE.start_main_p4) (= (select |c_#memory_int| v_idx_110) v_v_1414_1) (<= .cse3 v_idx_110)) (<= (+ v_b_150_1 3) v_b_156_1) (<= v_v_1414_1 0) (or (= v_v_1415_1 (select |c_#memory_int| v_idx_111)) (< v_idx_111 .cse3) (<= v_b_156_1 v_idx_111)) (<= .cse4 v_b_151_1) (<= .cse5 v_b_158_1) (<= .cse6 v_b_150_1) (<= v_b_153_1 c_ULTIMATE.start_main_p4) (<= (+ v_b_152_1 4) v_b_159_1) (or (= (select |c_#memory_int| v_idx_105) v_v_1409_1) (< v_idx_105 .cse6) (<= v_b_150_1 v_idx_105)) (or (< v_idx_106 v_b_150_1) (<= v_b_151_1 v_idx_106) (= (select |c_#memory_int| v_idx_106) 0)) (<= .cse7 v_b_158_1) (<= (+ v_b_153_1 1) v_b_156_1) (or (= (select |c_#memory_int| v_idx_114) 0) (<= v_b_159_1 v_idx_114) (< v_idx_114 v_b_158_1)) (<= .cse8 v_b_158_1) (<= v_b_159_1 .cse9) (or (<= c_ULTIMATE.start_main_p1 v_idx_103) (= (select |c_#memory_int| v_idx_103) v_v_1407_1)) (<= .cse10 v_b_158_1) (<= .cse11 v_b_153_1) (<= v_b_157_1 .cse5) (<= .cse12 v_b_157_1) (<= .cse13 c_ULTIMATE.start_main_p4) (<= .cse7 v_b_157_1) (<= .cse0 v_b_158_1) (or (<= c_ULTIMATE.start_main_p4 v_idx_109) (< v_idx_109 v_b_153_1) (= (select |c_#memory_int| v_idx_109) v_v_1413_1)) (<= .cse8 v_b_157_1) (<= v_b_151_1 .cse4) (or (= (select |c_#memory_int| v_idx_107) v_v_1411_1) (<= v_b_152_1 v_idx_107) (< v_idx_107 v_b_151_1)) (or (< v_idx_108 v_b_152_1) (= (select |c_#memory_int| v_idx_108) 0) (<= v_b_153_1 v_idx_108)) (or (= (select |c_#memory_int| v_idx_112) 0) (< v_idx_112 v_b_156_1) (<= v_b_157_1 v_idx_112)) (or (= (select |c_#memory_int| v_idx_104) 0) (<= .cse6 v_idx_104) (< v_idx_104 c_ULTIMATE.start_main_p1)) (<= (+ v_b_157_1 1) v_b_159_1) (<= .cse9 v_b_159_1) (<= .cse1 v_b_157_1) (<= v_b_157_1 v_b_158_1) (<= .cse4 v_b_152_1) (<= .cse11 c_ULTIMATE.start_main_p4) (<= .cse12 v_b_158_1) (<= .cse14 v_b_153_1) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_1) (<= (+ v_b_153_1 3) v_b_159_1) (<= .cse2 v_b_151_1) (<= (+ v_b_151_1 2) v_b_156_1) (<= .cse15 c_ULTIMATE.start_main_p4) (or (< v_idx_115 v_b_159_1) (= (select |c_#memory_int| v_idx_115) v_v_1419_1)) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_156_1) (<= .cse15 v_b_153_1) (<= v_b_151_1 v_b_152_1) (<= (+ v_b_150_1 5) v_b_159_1) (<= .cse5 v_b_157_1) (<= (+ v_b_156_1 2) v_b_159_1) (<= .cse14 c_ULTIMATE.start_main_p4) (<= .cse13 v_b_153_1) (<= .cse10 v_b_157_1) (<= .cse3 v_b_156_1) (<= (* 2 v_v_1414_1) 0) (<= v_b_153_1 .cse14))))) is different from false [2019-01-11 11:44:54,430 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_126 Int) (v_idx_127 Int) (v_idx_116 Int) (v_idx_124 Int) (v_idx_125 Int) (v_idx_119 Int) (v_idx_128 Int) (v_idx_117 Int) (v_idx_118 Int) (v_idx_122 Int) (v_idx_123 Int) (v_idx_120 Int) (v_idx_121 Int)) (exists ((v_v_1411_1 Int) (v_v_1417_1 Int) (v_b_159_1 Int) (v_v_1407_1 Int) (v_v_1419_1 Int) (v_b_158_1 Int) (v_v_1413_1 Int) (v_v_1415_1 Int) (v_v_1414_1 Int) (v_b_153_1 Int) (v_b_152_1 Int) (v_b_151_1 Int) (v_b_150_1 Int) (v_b_157_1 Int) (v_v_1409_1 Int) (v_b_156_1 Int) (v_b_155_1 Int) (v_b_154_1 Int)) (let ((.cse1 (+ v_b_152_1 2)) (.cse11 (+ v_b_150_1 4)) (.cse13 (+ v_b_152_1 3)) (.cse16 (+ v_b_151_1 1)) (.cse5 (+ v_b_150_1 3)) (.cse14 (+ v_b_158_1 1)) (.cse0 (+ v_b_153_1 2)) (.cse7 (+ v_b_150_1 1)) (.cse17 (+ c_ULTIMATE.start_main_p1 5)) (.cse3 (+ v_b_154_1 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 2)) (.cse9 (+ c_ULTIMATE.start_main_p1 1)) (.cse18 (+ v_b_155_1 1)) (.cse20 (+ v_b_151_1 2)) (.cse2 (+ c_ULTIMATE.start_main_p1 4)) (.cse8 (+ v_b_156_1 1)) (.cse10 (+ v_b_150_1 2)) (.cse15 (+ v_b_151_1 3)) (.cse21 (+ c_ULTIMATE.start_main_p1 3)) (.cse6 (+ v_b_154_1 1)) (.cse19 (+ v_b_152_1 1)) (.cse12 (+ v_b_153_1 1))) (and (<= (+ v_b_151_1 4) v_b_159_1) (<= .cse0 v_b_158_1) (<= .cse1 v_b_156_1) (or (= (select |c_#memory_int| v_idx_119) 0) (<= v_b_151_1 v_idx_119) (< v_idx_119 v_b_150_1)) (<= .cse2 v_b_155_1) (<= .cse3 v_b_157_1) (<= .cse4 v_b_152_1) (<= .cse5 v_b_156_1) (<= v_v_1414_1 0) (<= .cse6 v_b_156_1) (<= .cse7 v_b_151_1) (<= .cse8 v_b_158_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_116) (= (select |c_#memory_int| v_idx_116) v_v_1407_1)) (or (< v_idx_117 c_ULTIMATE.start_main_p1) (<= .cse9 v_idx_117) (= (select |c_#memory_int| v_idx_117) 0)) (<= .cse9 v_b_150_1) (<= (+ v_b_152_1 4) v_b_159_1) (<= .cse10 v_b_154_1) (<= .cse1 v_b_155_1) (<= .cse11 v_b_158_1) (<= .cse12 v_b_156_1) (<= .cse13 v_b_158_1) (<= v_b_159_1 .cse14) (<= .cse15 v_b_158_1) (<= .cse16 v_b_153_1) (<= v_b_157_1 .cse8) (<= .cse17 v_b_157_1) (<= .cse11 v_b_157_1) (or (< v_idx_126 v_b_157_1) (<= v_b_158_1 v_idx_126) (= (select |c_#memory_int| v_idx_126) v_v_1417_1)) (or (< v_idx_127 v_b_158_1) (= (select |c_#memory_int| v_idx_127) 0) (<= v_b_159_1 v_idx_127)) (<= (+ v_b_155_1 2) v_b_159_1) (<= .cse13 v_b_157_1) (<= v_b_151_1 .cse7) (<= .cse16 v_b_154_1) (<= .cse5 v_b_155_1) (<= (+ v_b_157_1 1) v_b_159_1) (<= .cse14 v_b_159_1) (<= .cse0 v_b_157_1) (<= v_b_157_1 v_b_158_1) (<= .cse7 v_b_152_1) (<= .cse18 v_b_157_1) (or (< v_idx_128 v_b_159_1) (= (select |c_#memory_int| v_idx_128) v_v_1419_1)) (<= .cse17 v_b_158_1) (<= .cse3 v_b_158_1) (or (= (select |c_#memory_int| v_idx_120) v_v_1411_1) (<= v_b_152_1 v_idx_120) (< v_idx_120 v_b_151_1)) (<= .cse19 v_b_153_1) (<= (+ v_b_154_1 3) v_b_159_1) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_1) (<= .cse20 v_b_155_1) (<= (+ v_b_153_1 3) v_b_159_1) (<= .cse4 v_b_151_1) (or (< v_idx_118 .cse9) (= (select |c_#memory_int| v_idx_118) v_v_1409_1) (<= v_b_150_1 v_idx_118)) (<= .cse18 v_b_158_1) (<= .cse20 v_b_156_1) (or (= (select |c_#memory_int| v_idx_124) v_v_1415_1) (<= v_b_156_1 v_idx_124) (< v_idx_124 v_b_155_1)) (or (= (select |c_#memory_int| v_idx_122) v_v_1413_1) (< v_idx_122 v_b_153_1) (<= v_b_154_1 v_idx_122)) (<= .cse2 v_b_156_1) (<= .cse21 v_b_153_1) (<= v_b_151_1 v_b_152_1) (<= v_b_155_1 .cse6) (<= (+ v_b_150_1 5) v_b_159_1) (<= .cse8 v_b_157_1) (<= (+ v_b_156_1 2) v_b_159_1) (<= .cse19 v_b_154_1) (or (< v_idx_125 v_b_156_1) (<= v_b_157_1 v_idx_125) (= 0 (select |c_#memory_int| v_idx_125))) (or (<= v_b_153_1 v_idx_121) (< v_idx_121 v_b_152_1) (= 0 (select |c_#memory_int| v_idx_121))) (<= .cse10 v_b_153_1) (<= .cse15 v_b_157_1) (<= (* 2 v_v_1414_1) 0) (<= .cse21 v_b_154_1) (or (= (select |c_#memory_int| v_idx_123) v_v_1414_1) (<= v_b_155_1 v_idx_123) (< v_idx_123 v_b_154_1)) (<= .cse6 v_b_155_1) (<= v_b_155_1 v_b_156_1) (<= v_b_153_1 v_b_154_1) (<= v_b_153_1 .cse19) (<= .cse12 v_b_155_1))))) is different from false [2019-01-11 11:44:55,084 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:44:55,084 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:44:55,085 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:44:55,085 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:44:55,085 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:44:55,087 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:44:55,087 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:44:55,087 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:44:55,088 INFO L87 Difference]: Start difference. First operand 14 states and 25 transitions. Second operand 4 states. [2019-01-11 11:44:57,653 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_104 Int) (v_idx_115 Int) (v_idx_105 Int) (v_idx_113 Int) (v_idx_103 Int) (v_idx_114 Int) (v_idx_108 Int) (v_idx_109 Int) (v_idx_106 Int) (v_idx_107 Int) (v_idx_111 Int) (v_idx_112 Int) (v_idx_110 Int)) (exists ((v_v_1411_1 Int) (v_v_1417_1 Int) (v_b_159_1 Int) (v_v_1407_1 Int) (v_v_1419_1 Int) (v_b_158_1 Int) (v_v_1413_1 Int) (v_v_1415_1 Int) (v_v_1414_1 Int) (v_b_153_1 Int) (v_b_152_1 Int) (v_b_151_1 Int) (v_b_150_1 Int) (v_b_157_1 Int) (v_v_1409_1 Int) (v_b_156_1 Int)) (let ((.cse7 (+ v_b_150_1 4)) (.cse0 (+ c_ULTIMATE.start_main_p4 2)) (.cse8 (+ v_b_152_1 3)) (.cse6 (+ c_ULTIMATE.start_main_p1 1)) (.cse9 (+ v_b_158_1 1)) (.cse1 (+ v_b_153_1 2)) (.cse4 (+ v_b_150_1 1)) (.cse11 (+ v_b_151_1 1)) (.cse12 (+ c_ULTIMATE.start_main_p1 5)) (.cse2 (+ c_ULTIMATE.start_main_p1 2)) (.cse15 (+ c_ULTIMATE.start_main_p1 3)) (.cse5 (+ v_b_156_1 1)) (.cse13 (+ v_b_150_1 2)) (.cse10 (+ v_b_151_1 3)) (.cse3 (+ c_ULTIMATE.start_main_p4 1)) (.cse14 (+ v_b_152_1 1))) (and (<= .cse0 v_b_157_1) (<= (+ v_b_151_1 4) v_b_159_1) (<= .cse1 v_b_158_1) (<= (+ v_b_152_1 2) v_b_156_1) (<= (+ c_ULTIMATE.start_main_p4 3) v_b_159_1) (or (= (select |c_#memory_int| v_idx_113) v_v_1417_1) (< v_idx_113 v_b_157_1) (<= v_b_158_1 v_idx_113)) (<= .cse2 v_b_152_1) (or (< v_idx_110 c_ULTIMATE.start_main_p4) (= (select |c_#memory_int| v_idx_110) v_v_1414_1) (<= .cse3 v_idx_110)) (<= (+ v_b_150_1 3) v_b_156_1) (<= v_v_1414_1 0) (or (= v_v_1415_1 (select |c_#memory_int| v_idx_111)) (< v_idx_111 .cse3) (<= v_b_156_1 v_idx_111)) (<= .cse4 v_b_151_1) (<= .cse5 v_b_158_1) (<= .cse6 v_b_150_1) (<= v_b_153_1 c_ULTIMATE.start_main_p4) (<= (+ v_b_152_1 4) v_b_159_1) (or (= (select |c_#memory_int| v_idx_105) v_v_1409_1) (< v_idx_105 .cse6) (<= v_b_150_1 v_idx_105)) (or (< v_idx_106 v_b_150_1) (<= v_b_151_1 v_idx_106) (= (select |c_#memory_int| v_idx_106) 0)) (<= .cse7 v_b_158_1) (<= (+ v_b_153_1 1) v_b_156_1) (or (= (select |c_#memory_int| v_idx_114) 0) (<= v_b_159_1 v_idx_114) (< v_idx_114 v_b_158_1)) (<= .cse8 v_b_158_1) (<= v_b_159_1 .cse9) (or (<= c_ULTIMATE.start_main_p1 v_idx_103) (= (select |c_#memory_int| v_idx_103) v_v_1407_1)) (<= .cse10 v_b_158_1) (<= .cse11 v_b_153_1) (<= v_b_157_1 .cse5) (<= .cse12 v_b_157_1) (<= .cse13 c_ULTIMATE.start_main_p4) (<= .cse7 v_b_157_1) (<= .cse0 v_b_158_1) (or (<= c_ULTIMATE.start_main_p4 v_idx_109) (< v_idx_109 v_b_153_1) (= (select |c_#memory_int| v_idx_109) v_v_1413_1)) (<= .cse8 v_b_157_1) (<= v_b_151_1 .cse4) (or (= (select |c_#memory_int| v_idx_107) v_v_1411_1) (<= v_b_152_1 v_idx_107) (< v_idx_107 v_b_151_1)) (or (< v_idx_108 v_b_152_1) (= (select |c_#memory_int| v_idx_108) 0) (<= v_b_153_1 v_idx_108)) (or (= (select |c_#memory_int| v_idx_112) 0) (< v_idx_112 v_b_156_1) (<= v_b_157_1 v_idx_112)) (or (= (select |c_#memory_int| v_idx_104) 0) (<= .cse6 v_idx_104) (< v_idx_104 c_ULTIMATE.start_main_p1)) (<= (+ v_b_157_1 1) v_b_159_1) (<= .cse9 v_b_159_1) (<= .cse1 v_b_157_1) (<= v_b_157_1 v_b_158_1) (<= .cse4 v_b_152_1) (<= .cse11 c_ULTIMATE.start_main_p4) (<= .cse12 v_b_158_1) (<= .cse14 v_b_153_1) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_1) (<= (+ v_b_153_1 3) v_b_159_1) (<= .cse2 v_b_151_1) (<= (+ v_b_151_1 2) v_b_156_1) (<= .cse15 c_ULTIMATE.start_main_p4) (or (< v_idx_115 v_b_159_1) (= (select |c_#memory_int| v_idx_115) v_v_1419_1)) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_156_1) (<= .cse15 v_b_153_1) (<= v_b_151_1 v_b_152_1) (<= (+ v_b_150_1 5) v_b_159_1) (<= .cse5 v_b_157_1) (<= (+ v_b_156_1 2) v_b_159_1) (<= .cse14 c_ULTIMATE.start_main_p4) (<= .cse13 v_b_153_1) (<= .cse10 v_b_157_1) (<= .cse3 v_b_156_1) (<= (* 2 v_v_1414_1) 0) (<= v_b_153_1 .cse14))))) (forall ((v_idx_126 Int) (v_idx_127 Int) (v_idx_116 Int) (v_idx_124 Int) (v_idx_125 Int) (v_idx_119 Int) (v_idx_128 Int) (v_idx_117 Int) (v_idx_118 Int) (v_idx_122 Int) (v_idx_123 Int) (v_idx_120 Int) (v_idx_121 Int)) (exists ((v_v_1411_1 Int) (v_v_1417_1 Int) (v_b_159_1 Int) (v_v_1407_1 Int) (v_v_1419_1 Int) (v_b_158_1 Int) (v_v_1413_1 Int) (v_v_1415_1 Int) (v_v_1414_1 Int) (v_b_153_1 Int) (v_b_152_1 Int) (v_b_151_1 Int) (v_b_150_1 Int) (v_b_157_1 Int) (v_v_1409_1 Int) (v_b_156_1 Int) (v_b_155_1 Int) (v_b_154_1 Int)) (let ((.cse17 (+ v_b_152_1 2)) (.cse27 (+ v_b_150_1 4)) (.cse29 (+ v_b_152_1 3)) (.cse32 (+ v_b_151_1 1)) (.cse21 (+ v_b_150_1 3)) (.cse30 (+ v_b_158_1 1)) (.cse16 (+ v_b_153_1 2)) (.cse23 (+ v_b_150_1 1)) (.cse33 (+ c_ULTIMATE.start_main_p1 5)) (.cse19 (+ v_b_154_1 2)) (.cse20 (+ c_ULTIMATE.start_main_p1 2)) (.cse25 (+ c_ULTIMATE.start_main_p1 1)) (.cse34 (+ v_b_155_1 1)) (.cse36 (+ v_b_151_1 2)) (.cse18 (+ c_ULTIMATE.start_main_p1 4)) (.cse24 (+ v_b_156_1 1)) (.cse26 (+ v_b_150_1 2)) (.cse31 (+ v_b_151_1 3)) (.cse37 (+ c_ULTIMATE.start_main_p1 3)) (.cse22 (+ v_b_154_1 1)) (.cse35 (+ v_b_152_1 1)) (.cse28 (+ v_b_153_1 1))) (and (<= (+ v_b_151_1 4) v_b_159_1) (<= .cse16 v_b_158_1) (<= .cse17 v_b_156_1) (or (= (select |c_#memory_int| v_idx_119) 0) (<= v_b_151_1 v_idx_119) (< v_idx_119 v_b_150_1)) (<= .cse18 v_b_155_1) (<= .cse19 v_b_157_1) (<= .cse20 v_b_152_1) (<= .cse21 v_b_156_1) (<= v_v_1414_1 0) (<= .cse22 v_b_156_1) (<= .cse23 v_b_151_1) (<= .cse24 v_b_158_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_116) (= (select |c_#memory_int| v_idx_116) v_v_1407_1)) (or (< v_idx_117 c_ULTIMATE.start_main_p1) (<= .cse25 v_idx_117) (= (select |c_#memory_int| v_idx_117) 0)) (<= .cse25 v_b_150_1) (<= (+ v_b_152_1 4) v_b_159_1) (<= .cse26 v_b_154_1) (<= .cse17 v_b_155_1) (<= .cse27 v_b_158_1) (<= .cse28 v_b_156_1) (<= .cse29 v_b_158_1) (<= v_b_159_1 .cse30) (<= .cse31 v_b_158_1) (<= .cse32 v_b_153_1) (<= v_b_157_1 .cse24) (<= .cse33 v_b_157_1) (<= .cse27 v_b_157_1) (or (< v_idx_126 v_b_157_1) (<= v_b_158_1 v_idx_126) (= (select |c_#memory_int| v_idx_126) v_v_1417_1)) (or (< v_idx_127 v_b_158_1) (= (select |c_#memory_int| v_idx_127) 0) (<= v_b_159_1 v_idx_127)) (<= (+ v_b_155_1 2) v_b_159_1) (<= .cse29 v_b_157_1) (<= v_b_151_1 .cse23) (<= .cse32 v_b_154_1) (<= .cse21 v_b_155_1) (<= (+ v_b_157_1 1) v_b_159_1) (<= .cse30 v_b_159_1) (<= .cse16 v_b_157_1) (<= v_b_157_1 v_b_158_1) (<= .cse23 v_b_152_1) (<= .cse34 v_b_157_1) (or (< v_idx_128 v_b_159_1) (= (select |c_#memory_int| v_idx_128) v_v_1419_1)) (<= .cse33 v_b_158_1) (<= .cse19 v_b_158_1) (or (= (select |c_#memory_int| v_idx_120) v_v_1411_1) (<= v_b_152_1 v_idx_120) (< v_idx_120 v_b_151_1)) (<= .cse35 v_b_153_1) (<= (+ v_b_154_1 3) v_b_159_1) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_1) (<= .cse36 v_b_155_1) (<= (+ v_b_153_1 3) v_b_159_1) (<= .cse20 v_b_151_1) (or (< v_idx_118 .cse25) (= (select |c_#memory_int| v_idx_118) v_v_1409_1) (<= v_b_150_1 v_idx_118)) (<= .cse34 v_b_158_1) (<= .cse36 v_b_156_1) (or (= (select |c_#memory_int| v_idx_124) v_v_1415_1) (<= v_b_156_1 v_idx_124) (< v_idx_124 v_b_155_1)) (or (= (select |c_#memory_int| v_idx_122) v_v_1413_1) (< v_idx_122 v_b_153_1) (<= v_b_154_1 v_idx_122)) (<= .cse18 v_b_156_1) (<= .cse37 v_b_153_1) (<= v_b_151_1 v_b_152_1) (<= v_b_155_1 .cse22) (<= (+ v_b_150_1 5) v_b_159_1) (<= .cse24 v_b_157_1) (<= (+ v_b_156_1 2) v_b_159_1) (<= .cse35 v_b_154_1) (or (< v_idx_125 v_b_156_1) (<= v_b_157_1 v_idx_125) (= 0 (select |c_#memory_int| v_idx_125))) (or (<= v_b_153_1 v_idx_121) (< v_idx_121 v_b_152_1) (= 0 (select |c_#memory_int| v_idx_121))) (<= .cse26 v_b_153_1) (<= .cse31 v_b_157_1) (<= (* 2 v_v_1414_1) 0) (<= .cse37 v_b_154_1) (or (= (select |c_#memory_int| v_idx_123) v_v_1414_1) (<= v_b_155_1 v_idx_123) (< v_idx_123 v_b_154_1)) (<= .cse22 v_b_155_1) (<= v_b_155_1 v_b_156_1) (<= v_b_153_1 v_b_154_1) (<= v_b_153_1 .cse35) (<= .cse28 v_b_155_1)))))) is different from false [2019-01-11 11:45:37,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:45:37,130 INFO L93 Difference]: Finished difference Result 16 states and 33 transitions. [2019-01-11 11:45:37,131 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:45:37,131 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:45:37,131 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:45:37,132 INFO L225 Difference]: With dead ends: 16 [2019-01-11 11:45:37,132 INFO L226 Difference]: Without dead ends: 15 [2019-01-11 11:45:37,133 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.7s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:45:37,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states. [2019-01-11 11:45:37,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2019-01-11 11:45:37,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-11 11:45:37,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 32 transitions. [2019-01-11 11:45:37,140 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 32 transitions. Word has length 3 [2019-01-11 11:45:37,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:45:37,141 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 32 transitions. [2019-01-11 11:45:37,141 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:45:37,141 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 32 transitions. [2019-01-11 11:45:37,142 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:45:37,142 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:45:37,142 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:45:37,143 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:45:37,143 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:37,143 INFO L82 PathProgramCache]: Analyzing trace with hash 30004, now seen corresponding path program 1 times [2019-01-11 11:45:37,144 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:45:37,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:37,145 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:45:37,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:37,145 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:45:37,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:45:37,339 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:45:37,339 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:45:37,340 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:45:37,340 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:45:37,340 INFO L207 CegarAbsIntRunner]: [0], [6], [27] [2019-01-11 11:45:37,343 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:45:37,343 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:45:46,846 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:45:46,846 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:45:46,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:46,847 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:45:47,486 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 80% of their original sizes. [2019-01-11 11:45:47,486 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:45:49,999 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_236 Int) (v_idx_237 Int) (v_idx_234 Int) (v_idx_235 Int) (v_idx_238 Int) (v_idx_239 Int) (v_idx_240 Int) (v_idx_243 Int) (v_idx_232 Int) (v_idx_233 Int) (v_idx_241 Int) (v_idx_242 Int) (v_idx_231 Int)) (exists ((v_v_1387_2 Int) (v_v_1398_2 Int) (v_v_1388_2 Int) (v_b_169_2 Int) (v_v_1396_2 Int) (v_b_168_2 Int) (v_v_1386_2 Int) (v_v_1394_2 Int) (v_v_1392_2 Int) (v_b_171_2 Int) (v_v_1390_2 Int) (v_b_172_2 Int) (v_b_173_2 Int) (v_b_174_2 Int) (v_b_175_2 Int) (v_b_167_2 Int) (v_b_166_2 Int) (v_b_170_2 Int)) (let ((.cse0 (+ v_b_170_2 2)) (.cse4 (+ v_b_166_2 3)) (.cse3 (+ v_b_168_2 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse5 (+ v_b_166_2 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse12 (+ v_b_174_2 1)) (.cse14 (+ v_b_171_2 1)) (.cse8 (+ v_b_166_2 4)) (.cse11 (+ v_b_168_2 3)) (.cse2 (+ v_b_169_2 2)) (.cse10 (+ v_b_166_2 2)) (.cse17 (+ v_b_167_2 1)) (.cse19 (+ c_ULTIMATE.start_main_p1 3)) (.cse13 (+ v_b_167_2 3)) (.cse18 (+ v_b_169_2 1)) (.cse6 (+ v_b_168_2 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 5)) (.cse15 (+ v_b_167_2 2)) (.cse21 (+ v_b_172_2 1)) (.cse20 (+ c_ULTIMATE.start_main_p1 4)) (.cse16 (+ v_b_170_2 1))) (and (<= (+ v_b_166_2 5) v_b_175_2) (<= (+ v_b_167_2 4) v_b_175_2) (<= v_b_167_2 v_b_168_2) (<= .cse0 v_b_174_2) (<= 0 v_v_1387_2) (or (= 0 (select |c_#memory_int| v_idx_242)) (<= v_b_175_2 v_idx_242) (< v_idx_242 v_b_174_2)) (<= .cse1 v_b_166_2) (or (<= v_b_166_2 v_idx_233) (= (select |c_#memory_int| v_idx_233) v_v_1388_2) (< v_idx_233 .cse1)) (<= .cse2 v_b_174_2) (or (< v_idx_237 v_b_169_2) (= (select |c_#memory_int| v_idx_237) v_v_1392_2) (<= v_b_170_2 v_idx_237)) (<= .cse3 v_b_171_2) (<= .cse4 v_b_172_2) (<= .cse0 v_b_173_2) (<= v_b_167_2 .cse5) (or (< v_idx_240 v_b_172_2) (<= v_b_173_2 v_idx_240) (= 0 (select |c_#memory_int| v_idx_240))) (or (< v_idx_243 v_b_175_2) (= (select |c_#memory_int| v_idx_243) v_v_1398_2)) (<= v_b_171_2 v_b_172_2) (<= .cse5 v_b_168_2) (<= 0 (* 2 v_v_1387_2)) (<= (+ v_b_170_2 3) v_b_175_2) (<= .cse4 v_b_171_2) (<= .cse6 v_b_170_2) (or (<= v_b_169_2 v_idx_236) (= (select |c_#memory_int| v_idx_236) 0) (< v_idx_236 v_b_168_2)) (or (<= v_b_167_2 v_idx_234) (< v_idx_234 v_b_166_2) (= 0 (select |c_#memory_int| v_idx_234))) (<= .cse7 v_b_168_2) (<= .cse3 v_b_172_2) (<= .cse8 v_b_173_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_231) (= (select |c_#memory_int| v_idx_231) v_v_1386_2)) (<= (+ v_b_169_2 3) v_b_175_2) (or (< v_idx_232 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_232) v_v_1387_2) (<= .cse1 v_idx_232)) (or (= 0 (select |c_#memory_int| v_idx_238)) (< v_idx_238 v_b_170_2) (<= v_b_171_2 v_idx_238)) (or (< v_idx_235 v_b_167_2) (= (select |c_#memory_int| v_idx_235) v_v_1390_2) (<= v_b_168_2 v_idx_235)) (<= .cse9 v_b_173_2) (<= .cse5 v_b_167_2) (<= .cse10 v_b_170_2) (<= v_b_173_2 v_b_174_2) (<= .cse11 v_b_173_2) (<= .cse12 v_b_175_2) (<= .cse7 v_b_167_2) (<= .cse13 v_b_174_2) (<= v_b_175_2 .cse12) (<= .cse14 v_b_174_2) (<= .cse15 v_b_171_2) (<= .cse16 v_b_172_2) (<= .cse14 v_b_173_2) (<= .cse17 v_b_169_2) (<= .cse18 v_b_171_2) (<= .cse19 v_b_169_2) (<= .cse8 v_b_174_2) (<= .cse20 v_b_172_2) (<= (+ v_b_168_2 4) v_b_175_2) (<= (+ v_b_171_2 2) v_b_175_2) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_2) (<= .cse21 v_b_173_2) (<= (+ v_b_172_2 2) v_b_175_2) (<= .cse11 v_b_174_2) (<= .cse2 v_b_173_2) (<= v_b_173_2 .cse21) (<= .cse10 v_b_169_2) (<= .cse17 v_b_170_2) (<= v_b_169_2 .cse6) (or (= (select |c_#memory_int| v_idx_239) v_v_1394_2) (<= v_b_172_2 v_idx_239) (< v_idx_239 v_b_171_2)) (<= (+ v_b_173_2 1) v_b_175_2) (or (<= v_b_174_2 v_idx_241) (< v_idx_241 v_b_173_2) (= (select |c_#memory_int| v_idx_241) v_v_1396_2)) (<= .cse19 v_b_170_2) (<= .cse13 v_b_173_2) (<= .cse18 v_b_172_2) (<= .cse6 v_b_169_2) (<= .cse9 v_b_174_2) (<= .cse15 v_b_172_2) (<= v_b_169_2 v_b_170_2) (<= v_b_171_2 .cse16) (<= .cse21 v_b_174_2) (<= .cse20 v_b_171_2) (<= .cse16 v_b_171_2))))) is different from false [2019-01-11 11:45:52,703 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_247 Int) (v_idx_248 Int) (v_idx_245 Int) (v_idx_256 Int) (v_idx_246 Int) (v_idx_249 Int) (v_idx_250 Int) (v_idx_251 Int) (v_idx_254 Int) (v_idx_244 Int) (v_idx_255 Int) (v_idx_252 Int) (v_idx_253 Int)) (exists ((v_v_1387_2 Int) (v_v_1398_2 Int) (v_v_1388_2 Int) (v_b_169_2 Int) (v_v_1396_2 Int) (v_b_168_2 Int) (v_v_1386_2 Int) (v_v_1394_2 Int) (v_v_1392_2 Int) (v_b_171_2 Int) (v_v_1390_2 Int) (v_b_172_2 Int) (v_b_173_2 Int) (v_b_174_2 Int) (v_b_175_2 Int) (v_b_167_2 Int) (v_b_166_2 Int) (v_b_170_2 Int)) (let ((.cse0 (+ v_b_170_2 2)) (.cse4 (+ v_b_166_2 3)) (.cse3 (+ v_b_168_2 2)) (.cse5 (+ v_b_166_2 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse12 (+ v_b_174_2 1)) (.cse14 (+ v_b_171_2 1)) (.cse8 (+ v_b_166_2 4)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse11 (+ v_b_168_2 3)) (.cse2 (+ v_b_169_2 2)) (.cse10 (+ v_b_166_2 2)) (.cse17 (+ v_b_167_2 1)) (.cse19 (+ c_ULTIMATE.start_main_p1 3)) (.cse13 (+ v_b_167_2 3)) (.cse18 (+ v_b_169_2 1)) (.cse6 (+ v_b_168_2 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 5)) (.cse15 (+ v_b_167_2 2)) (.cse21 (+ v_b_172_2 1)) (.cse20 (+ c_ULTIMATE.start_main_p1 4)) (.cse16 (+ v_b_170_2 1))) (and (or (= 0 (select |c_#memory_int| v_idx_253)) (<= v_b_173_2 v_idx_253) (< v_idx_253 v_b_172_2)) (<= (+ v_b_166_2 5) v_b_175_2) (<= (+ v_b_167_2 4) v_b_175_2) (<= v_b_167_2 v_b_168_2) (<= .cse0 v_b_174_2) (<= 0 v_v_1387_2) (<= .cse1 v_b_166_2) (<= .cse2 v_b_174_2) (<= .cse3 v_b_171_2) (<= .cse4 v_b_172_2) (<= .cse0 v_b_173_2) (<= v_b_167_2 .cse5) (or (= v_v_1388_2 (select |c_#memory_int| v_idx_246)) (< v_idx_246 .cse1) (<= v_b_166_2 v_idx_246)) (<= v_b_171_2 v_b_172_2) (or (= 0 (select |c_#memory_int| v_idx_255)) (<= v_b_175_2 v_idx_255) (< v_idx_255 v_b_174_2)) (<= .cse5 v_b_168_2) (or (< v_idx_256 v_b_175_2) (= (select |c_#memory_int| v_idx_256) v_v_1398_2)) (<= 0 (* 2 v_v_1387_2)) (<= (+ v_b_170_2 3) v_b_175_2) (<= .cse4 v_b_171_2) (<= .cse6 v_b_170_2) (<= .cse7 v_b_168_2) (<= .cse3 v_b_172_2) (<= .cse8 v_b_173_2) (or (<= v_b_167_2 v_idx_247) (= 0 (select |c_#memory_int| v_idx_247)) (< v_idx_247 v_b_166_2)) (or (< v_idx_252 v_b_171_2) (<= v_b_172_2 v_idx_252) (= (select |c_#memory_int| v_idx_252) v_v_1394_2)) (<= (+ v_b_169_2 3) v_b_175_2) (<= .cse9 v_b_173_2) (<= .cse5 v_b_167_2) (<= .cse10 v_b_170_2) (<= v_b_173_2 v_b_174_2) (<= .cse11 v_b_173_2) (<= .cse12 v_b_175_2) (<= .cse7 v_b_167_2) (<= .cse13 v_b_174_2) (<= v_b_175_2 .cse12) (or (= (select |c_#memory_int| v_idx_244) v_v_1386_2) (<= c_ULTIMATE.start_main_p1 v_idx_244)) (<= .cse14 v_b_174_2) (<= .cse15 v_b_171_2) (<= .cse16 v_b_172_2) (<= .cse14 v_b_173_2) (or (= (select |c_#memory_int| v_idx_254) v_v_1396_2) (< v_idx_254 v_b_173_2) (<= v_b_174_2 v_idx_254)) (<= .cse17 v_b_169_2) (<= .cse18 v_b_171_2) (or (<= v_b_169_2 v_idx_249) (< v_idx_249 v_b_168_2) (= 0 (select |c_#memory_int| v_idx_249))) (or (< v_idx_248 v_b_167_2) (<= v_b_168_2 v_idx_248) (= (select |c_#memory_int| v_idx_248) v_v_1390_2)) (<= .cse19 v_b_169_2) (<= .cse8 v_b_174_2) (<= .cse20 v_b_172_2) (or (<= v_b_171_2 v_idx_251) (= (select |c_#memory_int| v_idx_251) 0) (< v_idx_251 v_b_170_2)) (<= (+ v_b_168_2 4) v_b_175_2) (<= (+ v_b_171_2 2) v_b_175_2) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_2) (<= .cse21 v_b_173_2) (or (< v_idx_245 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_245) v_v_1387_2) (<= .cse1 v_idx_245)) (or (= (select |c_#memory_int| v_idx_250) v_v_1392_2) (<= v_b_170_2 v_idx_250) (< v_idx_250 v_b_169_2)) (<= (+ v_b_172_2 2) v_b_175_2) (<= .cse11 v_b_174_2) (<= .cse2 v_b_173_2) (<= v_b_173_2 .cse21) (<= .cse10 v_b_169_2) (<= .cse17 v_b_170_2) (<= v_b_169_2 .cse6) (<= (+ v_b_173_2 1) v_b_175_2) (<= .cse19 v_b_170_2) (<= .cse13 v_b_173_2) (<= .cse18 v_b_172_2) (<= .cse6 v_b_169_2) (<= .cse9 v_b_174_2) (<= .cse15 v_b_172_2) (<= v_b_169_2 v_b_170_2) (<= v_b_171_2 .cse16) (<= .cse21 v_b_174_2) (<= .cse20 v_b_171_2) (<= .cse16 v_b_171_2))))) is different from false [2019-01-11 11:45:54,759 WARN L860 $PredicateComparison]: unable to prove that (forall ((v_idx_247 Int) (v_idx_248 Int) (v_idx_245 Int) (v_idx_256 Int) (v_idx_246 Int) (v_idx_249 Int) (v_idx_250 Int) (v_idx_251 Int) (v_idx_254 Int) (v_idx_244 Int) (v_idx_255 Int) (v_idx_252 Int) (v_idx_253 Int)) (exists ((v_v_1387_2 Int) (v_v_1398_2 Int) (v_v_1388_2 Int) (v_b_169_2 Int) (v_v_1396_2 Int) (v_b_168_2 Int) (v_v_1386_2 Int) (v_v_1394_2 Int) (v_v_1392_2 Int) (v_b_171_2 Int) (v_v_1390_2 Int) (v_b_172_2 Int) (v_b_173_2 Int) (v_b_174_2 Int) (v_b_175_2 Int) (v_b_167_2 Int) (v_b_166_2 Int) (v_b_170_2 Int)) (let ((.cse0 (+ v_b_170_2 2)) (.cse4 (+ v_b_166_2 3)) (.cse3 (+ v_b_168_2 2)) (.cse5 (+ v_b_166_2 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse12 (+ v_b_174_2 1)) (.cse14 (+ v_b_171_2 1)) (.cse8 (+ v_b_166_2 4)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse11 (+ v_b_168_2 3)) (.cse2 (+ v_b_169_2 2)) (.cse10 (+ v_b_166_2 2)) (.cse17 (+ v_b_167_2 1)) (.cse19 (+ c_ULTIMATE.start_main_p1 3)) (.cse13 (+ v_b_167_2 3)) (.cse18 (+ v_b_169_2 1)) (.cse6 (+ v_b_168_2 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 5)) (.cse15 (+ v_b_167_2 2)) (.cse21 (+ v_b_172_2 1)) (.cse20 (+ c_ULTIMATE.start_main_p1 4)) (.cse16 (+ v_b_170_2 1))) (and (or (= 0 (select |c_#memory_int| v_idx_253)) (<= v_b_173_2 v_idx_253) (< v_idx_253 v_b_172_2)) (<= (+ v_b_166_2 5) v_b_175_2) (<= (+ v_b_167_2 4) v_b_175_2) (<= v_b_167_2 v_b_168_2) (<= .cse0 v_b_174_2) (<= 0 v_v_1387_2) (<= .cse1 v_b_166_2) (<= .cse2 v_b_174_2) (<= .cse3 v_b_171_2) (<= .cse4 v_b_172_2) (<= .cse0 v_b_173_2) (<= v_b_167_2 .cse5) (or (= v_v_1388_2 (select |c_#memory_int| v_idx_246)) (< v_idx_246 .cse1) (<= v_b_166_2 v_idx_246)) (<= v_b_171_2 v_b_172_2) (or (= 0 (select |c_#memory_int| v_idx_255)) (<= v_b_175_2 v_idx_255) (< v_idx_255 v_b_174_2)) (<= .cse5 v_b_168_2) (or (< v_idx_256 v_b_175_2) (= (select |c_#memory_int| v_idx_256) v_v_1398_2)) (<= 0 (* 2 v_v_1387_2)) (<= (+ v_b_170_2 3) v_b_175_2) (<= .cse4 v_b_171_2) (<= .cse6 v_b_170_2) (<= .cse7 v_b_168_2) (<= .cse3 v_b_172_2) (<= .cse8 v_b_173_2) (or (<= v_b_167_2 v_idx_247) (= 0 (select |c_#memory_int| v_idx_247)) (< v_idx_247 v_b_166_2)) (or (< v_idx_252 v_b_171_2) (<= v_b_172_2 v_idx_252) (= (select |c_#memory_int| v_idx_252) v_v_1394_2)) (<= (+ v_b_169_2 3) v_b_175_2) (<= .cse9 v_b_173_2) (<= .cse5 v_b_167_2) (<= .cse10 v_b_170_2) (<= v_b_173_2 v_b_174_2) (<= .cse11 v_b_173_2) (<= .cse12 v_b_175_2) (<= .cse7 v_b_167_2) (<= .cse13 v_b_174_2) (<= v_b_175_2 .cse12) (or (= (select |c_#memory_int| v_idx_244) v_v_1386_2) (<= c_ULTIMATE.start_main_p1 v_idx_244)) (<= .cse14 v_b_174_2) (<= .cse15 v_b_171_2) (<= .cse16 v_b_172_2) (<= .cse14 v_b_173_2) (or (= (select |c_#memory_int| v_idx_254) v_v_1396_2) (< v_idx_254 v_b_173_2) (<= v_b_174_2 v_idx_254)) (<= .cse17 v_b_169_2) (<= .cse18 v_b_171_2) (or (<= v_b_169_2 v_idx_249) (< v_idx_249 v_b_168_2) (= 0 (select |c_#memory_int| v_idx_249))) (or (< v_idx_248 v_b_167_2) (<= v_b_168_2 v_idx_248) (= (select |c_#memory_int| v_idx_248) v_v_1390_2)) (<= .cse19 v_b_169_2) (<= .cse8 v_b_174_2) (<= .cse20 v_b_172_2) (or (<= v_b_171_2 v_idx_251) (= (select |c_#memory_int| v_idx_251) 0) (< v_idx_251 v_b_170_2)) (<= (+ v_b_168_2 4) v_b_175_2) (<= (+ v_b_171_2 2) v_b_175_2) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_2) (<= .cse21 v_b_173_2) (or (< v_idx_245 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_245) v_v_1387_2) (<= .cse1 v_idx_245)) (or (= (select |c_#memory_int| v_idx_250) v_v_1392_2) (<= v_b_170_2 v_idx_250) (< v_idx_250 v_b_169_2)) (<= (+ v_b_172_2 2) v_b_175_2) (<= .cse11 v_b_174_2) (<= .cse2 v_b_173_2) (<= v_b_173_2 .cse21) (<= .cse10 v_b_169_2) (<= .cse17 v_b_170_2) (<= v_b_169_2 .cse6) (<= (+ v_b_173_2 1) v_b_175_2) (<= .cse19 v_b_170_2) (<= .cse13 v_b_173_2) (<= .cse18 v_b_172_2) (<= .cse6 v_b_169_2) (<= .cse9 v_b_174_2) (<= .cse15 v_b_172_2) (<= v_b_169_2 v_b_170_2) (<= v_b_171_2 .cse16) (<= .cse21 v_b_174_2) (<= .cse20 v_b_171_2) (<= .cse16 v_b_171_2))))) is different from true [2019-01-11 11:45:54,760 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:45:54,760 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:45:54,760 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:45:54,760 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:45:54,761 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:45:54,761 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:45:54,761 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:45:54,762 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=2, Unknown=3, NotChecked=2, Total=12 [2019-01-11 11:45:54,762 INFO L87 Difference]: Start difference. First operand 15 states and 32 transitions. Second operand 4 states. [2019-01-11 11:45:57,431 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_236 Int) (v_idx_237 Int) (v_idx_234 Int) (v_idx_235 Int) (v_idx_238 Int) (v_idx_239 Int) (v_idx_240 Int) (v_idx_243 Int) (v_idx_232 Int) (v_idx_233 Int) (v_idx_241 Int) (v_idx_242 Int) (v_idx_231 Int)) (exists ((v_v_1387_2 Int) (v_v_1398_2 Int) (v_v_1388_2 Int) (v_b_169_2 Int) (v_v_1396_2 Int) (v_b_168_2 Int) (v_v_1386_2 Int) (v_v_1394_2 Int) (v_v_1392_2 Int) (v_b_171_2 Int) (v_v_1390_2 Int) (v_b_172_2 Int) (v_b_173_2 Int) (v_b_174_2 Int) (v_b_175_2 Int) (v_b_167_2 Int) (v_b_166_2 Int) (v_b_170_2 Int)) (let ((.cse0 (+ v_b_170_2 2)) (.cse4 (+ v_b_166_2 3)) (.cse3 (+ v_b_168_2 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 1)) (.cse5 (+ v_b_166_2 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse12 (+ v_b_174_2 1)) (.cse14 (+ v_b_171_2 1)) (.cse8 (+ v_b_166_2 4)) (.cse11 (+ v_b_168_2 3)) (.cse2 (+ v_b_169_2 2)) (.cse10 (+ v_b_166_2 2)) (.cse17 (+ v_b_167_2 1)) (.cse19 (+ c_ULTIMATE.start_main_p1 3)) (.cse13 (+ v_b_167_2 3)) (.cse18 (+ v_b_169_2 1)) (.cse6 (+ v_b_168_2 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 5)) (.cse15 (+ v_b_167_2 2)) (.cse21 (+ v_b_172_2 1)) (.cse20 (+ c_ULTIMATE.start_main_p1 4)) (.cse16 (+ v_b_170_2 1))) (and (<= (+ v_b_166_2 5) v_b_175_2) (<= (+ v_b_167_2 4) v_b_175_2) (<= v_b_167_2 v_b_168_2) (<= .cse0 v_b_174_2) (<= 0 v_v_1387_2) (or (= 0 (select |c_#memory_int| v_idx_242)) (<= v_b_175_2 v_idx_242) (< v_idx_242 v_b_174_2)) (<= .cse1 v_b_166_2) (or (<= v_b_166_2 v_idx_233) (= (select |c_#memory_int| v_idx_233) v_v_1388_2) (< v_idx_233 .cse1)) (<= .cse2 v_b_174_2) (or (< v_idx_237 v_b_169_2) (= (select |c_#memory_int| v_idx_237) v_v_1392_2) (<= v_b_170_2 v_idx_237)) (<= .cse3 v_b_171_2) (<= .cse4 v_b_172_2) (<= .cse0 v_b_173_2) (<= v_b_167_2 .cse5) (or (< v_idx_240 v_b_172_2) (<= v_b_173_2 v_idx_240) (= 0 (select |c_#memory_int| v_idx_240))) (or (< v_idx_243 v_b_175_2) (= (select |c_#memory_int| v_idx_243) v_v_1398_2)) (<= v_b_171_2 v_b_172_2) (<= .cse5 v_b_168_2) (<= 0 (* 2 v_v_1387_2)) (<= (+ v_b_170_2 3) v_b_175_2) (<= .cse4 v_b_171_2) (<= .cse6 v_b_170_2) (or (<= v_b_169_2 v_idx_236) (= (select |c_#memory_int| v_idx_236) 0) (< v_idx_236 v_b_168_2)) (or (<= v_b_167_2 v_idx_234) (< v_idx_234 v_b_166_2) (= 0 (select |c_#memory_int| v_idx_234))) (<= .cse7 v_b_168_2) (<= .cse3 v_b_172_2) (<= .cse8 v_b_173_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_231) (= (select |c_#memory_int| v_idx_231) v_v_1386_2)) (<= (+ v_b_169_2 3) v_b_175_2) (or (< v_idx_232 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_232) v_v_1387_2) (<= .cse1 v_idx_232)) (or (= 0 (select |c_#memory_int| v_idx_238)) (< v_idx_238 v_b_170_2) (<= v_b_171_2 v_idx_238)) (or (< v_idx_235 v_b_167_2) (= (select |c_#memory_int| v_idx_235) v_v_1390_2) (<= v_b_168_2 v_idx_235)) (<= .cse9 v_b_173_2) (<= .cse5 v_b_167_2) (<= .cse10 v_b_170_2) (<= v_b_173_2 v_b_174_2) (<= .cse11 v_b_173_2) (<= .cse12 v_b_175_2) (<= .cse7 v_b_167_2) (<= .cse13 v_b_174_2) (<= v_b_175_2 .cse12) (<= .cse14 v_b_174_2) (<= .cse15 v_b_171_2) (<= .cse16 v_b_172_2) (<= .cse14 v_b_173_2) (<= .cse17 v_b_169_2) (<= .cse18 v_b_171_2) (<= .cse19 v_b_169_2) (<= .cse8 v_b_174_2) (<= .cse20 v_b_172_2) (<= (+ v_b_168_2 4) v_b_175_2) (<= (+ v_b_171_2 2) v_b_175_2) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_2) (<= .cse21 v_b_173_2) (<= (+ v_b_172_2 2) v_b_175_2) (<= .cse11 v_b_174_2) (<= .cse2 v_b_173_2) (<= v_b_173_2 .cse21) (<= .cse10 v_b_169_2) (<= .cse17 v_b_170_2) (<= v_b_169_2 .cse6) (or (= (select |c_#memory_int| v_idx_239) v_v_1394_2) (<= v_b_172_2 v_idx_239) (< v_idx_239 v_b_171_2)) (<= (+ v_b_173_2 1) v_b_175_2) (or (<= v_b_174_2 v_idx_241) (< v_idx_241 v_b_173_2) (= (select |c_#memory_int| v_idx_241) v_v_1396_2)) (<= .cse19 v_b_170_2) (<= .cse13 v_b_173_2) (<= .cse18 v_b_172_2) (<= .cse6 v_b_169_2) (<= .cse9 v_b_174_2) (<= .cse15 v_b_172_2) (<= v_b_169_2 v_b_170_2) (<= v_b_171_2 .cse16) (<= .cse21 v_b_174_2) (<= .cse20 v_b_171_2) (<= .cse16 v_b_171_2))))) (forall ((v_idx_247 Int) (v_idx_248 Int) (v_idx_245 Int) (v_idx_256 Int) (v_idx_246 Int) (v_idx_249 Int) (v_idx_250 Int) (v_idx_251 Int) (v_idx_254 Int) (v_idx_244 Int) (v_idx_255 Int) (v_idx_252 Int) (v_idx_253 Int)) (exists ((v_v_1387_2 Int) (v_v_1398_2 Int) (v_v_1388_2 Int) (v_b_169_2 Int) (v_v_1396_2 Int) (v_b_168_2 Int) (v_v_1386_2 Int) (v_v_1394_2 Int) (v_v_1392_2 Int) (v_b_171_2 Int) (v_v_1390_2 Int) (v_b_172_2 Int) (v_b_173_2 Int) (v_b_174_2 Int) (v_b_175_2 Int) (v_b_167_2 Int) (v_b_166_2 Int) (v_b_170_2 Int)) (let ((.cse22 (+ v_b_170_2 2)) (.cse26 (+ v_b_166_2 3)) (.cse25 (+ v_b_168_2 2)) (.cse27 (+ v_b_166_2 1)) (.cse29 (+ c_ULTIMATE.start_main_p1 2)) (.cse34 (+ v_b_174_2 1)) (.cse36 (+ v_b_171_2 1)) (.cse30 (+ v_b_166_2 4)) (.cse23 (+ c_ULTIMATE.start_main_p1 1)) (.cse33 (+ v_b_168_2 3)) (.cse24 (+ v_b_169_2 2)) (.cse32 (+ v_b_166_2 2)) (.cse39 (+ v_b_167_2 1)) (.cse41 (+ c_ULTIMATE.start_main_p1 3)) (.cse35 (+ v_b_167_2 3)) (.cse40 (+ v_b_169_2 1)) (.cse28 (+ v_b_168_2 1)) (.cse31 (+ c_ULTIMATE.start_main_p1 5)) (.cse37 (+ v_b_167_2 2)) (.cse43 (+ v_b_172_2 1)) (.cse42 (+ c_ULTIMATE.start_main_p1 4)) (.cse38 (+ v_b_170_2 1))) (and (or (= 0 (select |c_#memory_int| v_idx_253)) (<= v_b_173_2 v_idx_253) (< v_idx_253 v_b_172_2)) (<= (+ v_b_166_2 5) v_b_175_2) (<= (+ v_b_167_2 4) v_b_175_2) (<= v_b_167_2 v_b_168_2) (<= .cse22 v_b_174_2) (<= 0 v_v_1387_2) (<= .cse23 v_b_166_2) (<= .cse24 v_b_174_2) (<= .cse25 v_b_171_2) (<= .cse26 v_b_172_2) (<= .cse22 v_b_173_2) (<= v_b_167_2 .cse27) (or (= v_v_1388_2 (select |c_#memory_int| v_idx_246)) (< v_idx_246 .cse23) (<= v_b_166_2 v_idx_246)) (<= v_b_171_2 v_b_172_2) (or (= 0 (select |c_#memory_int| v_idx_255)) (<= v_b_175_2 v_idx_255) (< v_idx_255 v_b_174_2)) (<= .cse27 v_b_168_2) (or (< v_idx_256 v_b_175_2) (= (select |c_#memory_int| v_idx_256) v_v_1398_2)) (<= 0 (* 2 v_v_1387_2)) (<= (+ v_b_170_2 3) v_b_175_2) (<= .cse26 v_b_171_2) (<= .cse28 v_b_170_2) (<= .cse29 v_b_168_2) (<= .cse25 v_b_172_2) (<= .cse30 v_b_173_2) (or (<= v_b_167_2 v_idx_247) (= 0 (select |c_#memory_int| v_idx_247)) (< v_idx_247 v_b_166_2)) (or (< v_idx_252 v_b_171_2) (<= v_b_172_2 v_idx_252) (= (select |c_#memory_int| v_idx_252) v_v_1394_2)) (<= (+ v_b_169_2 3) v_b_175_2) (<= .cse31 v_b_173_2) (<= .cse27 v_b_167_2) (<= .cse32 v_b_170_2) (<= v_b_173_2 v_b_174_2) (<= .cse33 v_b_173_2) (<= .cse34 v_b_175_2) (<= .cse29 v_b_167_2) (<= .cse35 v_b_174_2) (<= v_b_175_2 .cse34) (or (= (select |c_#memory_int| v_idx_244) v_v_1386_2) (<= c_ULTIMATE.start_main_p1 v_idx_244)) (<= .cse36 v_b_174_2) (<= .cse37 v_b_171_2) (<= .cse38 v_b_172_2) (<= .cse36 v_b_173_2) (or (= (select |c_#memory_int| v_idx_254) v_v_1396_2) (< v_idx_254 v_b_173_2) (<= v_b_174_2 v_idx_254)) (<= .cse39 v_b_169_2) (<= .cse40 v_b_171_2) (or (<= v_b_169_2 v_idx_249) (< v_idx_249 v_b_168_2) (= 0 (select |c_#memory_int| v_idx_249))) (or (< v_idx_248 v_b_167_2) (<= v_b_168_2 v_idx_248) (= (select |c_#memory_int| v_idx_248) v_v_1390_2)) (<= .cse41 v_b_169_2) (<= .cse30 v_b_174_2) (<= .cse42 v_b_172_2) (or (<= v_b_171_2 v_idx_251) (= (select |c_#memory_int| v_idx_251) 0) (< v_idx_251 v_b_170_2)) (<= (+ v_b_168_2 4) v_b_175_2) (<= (+ v_b_171_2 2) v_b_175_2) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_2) (<= .cse43 v_b_173_2) (or (< v_idx_245 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_245) v_v_1387_2) (<= .cse23 v_idx_245)) (or (= (select |c_#memory_int| v_idx_250) v_v_1392_2) (<= v_b_170_2 v_idx_250) (< v_idx_250 v_b_169_2)) (<= (+ v_b_172_2 2) v_b_175_2) (<= .cse33 v_b_174_2) (<= .cse24 v_b_173_2) (<= v_b_173_2 .cse43) (<= .cse32 v_b_169_2) (<= .cse39 v_b_170_2) (<= v_b_169_2 .cse28) (<= (+ v_b_173_2 1) v_b_175_2) (<= .cse41 v_b_170_2) (<= .cse35 v_b_173_2) (<= .cse40 v_b_172_2) (<= .cse28 v_b_169_2) (<= .cse31 v_b_174_2) (<= .cse37 v_b_172_2) (<= v_b_169_2 v_b_170_2) (<= v_b_171_2 .cse38) (<= .cse43 v_b_174_2) (<= .cse42 v_b_171_2) (<= .cse38 v_b_171_2)))))) is different from false [2019-01-11 11:46:29,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:46:29,390 INFO L93 Difference]: Finished difference Result 17 states and 40 transitions. [2019-01-11 11:46:29,390 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:46:29,390 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:46:29,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:46:29,390 INFO L225 Difference]: With dead ends: 17 [2019-01-11 11:46:29,391 INFO L226 Difference]: Without dead ends: 16 [2019-01-11 11:46:29,391 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 9.9s TimeCoverageRelationStatistics Valid=7, Invalid=3, Unknown=4, NotChecked=6, Total=20 [2019-01-11 11:46:29,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-11 11:46:29,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2019-01-11 11:46:29,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-11 11:46:29,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 32 transitions. [2019-01-11 11:46:29,399 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 32 transitions. Word has length 3 [2019-01-11 11:46:29,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:46:29,400 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 32 transitions. [2019-01-11 11:46:29,400 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:46:29,400 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 32 transitions. [2019-01-11 11:46:29,400 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:46:29,401 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:46:29,401 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:46:29,401 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:46:29,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:46:29,401 INFO L82 PathProgramCache]: Analyzing trace with hash 30500, now seen corresponding path program 1 times [2019-01-11 11:46:29,402 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:46:29,402 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:46:29,402 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:46:29,402 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:46:29,403 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:46:29,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:46:29,596 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:46:29,597 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:46:29,597 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:46:29,597 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:46:29,597 INFO L207 CegarAbsIntRunner]: [0], [22], [27] [2019-01-11 11:46:29,601 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:46:29,601 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:46:39,448 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:46:39,448 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:46:39,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:46:39,448 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:46:39,944 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 75% of their original sizes. [2019-01-11 11:46:39,945 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:46:42,287 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_368 Int) (v_idx_369 Int) (v_idx_366 Int) (v_idx_367 Int) (v_idx_359 Int) (v_idx_360 Int) (v_idx_371 Int) (v_idx_361 Int) (v_idx_370 Int) (v_idx_364 Int) (v_idx_365 Int) (v_idx_362 Int) (v_idx_363 Int)) (exists ((v_v_1621_3 Int) (v_v_1623_3 Int) (v_v_1626_3 Int) (v_v_1625_3 Int) (v_b_159_3 Int) (v_b_158_3 Int) (v_b_151_3 Int) (v_b_150_3 Int) (v_b_155_3 Int) (v_v_1629_3 Int) (v_b_154_3 Int) (v_v_1627_3 Int) (v_b_153_3 Int) (v_b_152_3 Int) (v_v_1617_3 Int) (v_v_1619_3 Int)) (let ((.cse4 (+ c_ULTIMATE.start_main_p1 2)) (.cse9 (+ c_ULTIMATE.start_main_p1 4)) (.cse2 (+ v_b_158_3 1)) (.cse5 (+ v_b_150_3 3)) (.cse1 (+ v_b_153_3 1)) (.cse3 (+ v_b_150_3 2)) (.cse8 (+ v_b_151_3 1)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse12 (+ v_b_152_3 1)) (.cse14 (+ v_b_151_3 2)) (.cse11 (+ c_ULTIMATE.start_main_p5 1)) (.cse10 (+ v_b_150_3 1)) (.cse13 (+ v_b_152_3 2)) (.cse7 (+ c_ULTIMATE.start_main_p1 3)) (.cse6 (+ v_b_154_3 1))) (and (or (<= .cse0 v_idx_360) (= (select |c_#memory_int| v_idx_360) 0) (< v_idx_360 c_ULTIMATE.start_main_p1)) (<= .cse1 c_ULTIMATE.start_main_p5) (or (< v_idx_366 v_b_154_3) (<= v_b_155_3 v_idx_366) (= 0 (select |c_#memory_int| v_idx_366))) (<= .cse2 v_b_159_3) (or (<= v_b_151_3 v_idx_362) (< v_idx_362 v_b_150_3) (= 0 (select |c_#memory_int| v_idx_362))) (<= .cse0 v_b_150_3) (<= .cse3 v_b_154_3) (<= (+ v_b_155_3 1) v_b_158_3) (<= .cse4 v_b_152_3) (<= .cse5 c_ULTIMATE.start_main_p5) (<= v_b_153_3 v_b_154_3) (<= .cse6 v_b_155_3) (<= (+ v_b_152_3 3) v_b_158_3) (<= (+ v_b_152_3 4) v_b_159_3) (<= .cse7 v_b_153_3) (<= 0 (* 2 v_v_1626_3)) (<= .cse8 v_b_153_3) (<= .cse4 v_b_151_3) (<= .cse9 v_b_155_3) (<= .cse9 c_ULTIMATE.start_main_p5) (<= (+ v_b_155_3 2) v_b_159_3) (<= .cse10 v_b_152_3) (or (<= v_b_158_3 v_idx_369) (< v_idx_369 .cse11) (= (select |c_#memory_int| v_idx_369) v_v_1627_3)) (or (= (select |c_#memory_int| v_idx_363) v_v_1621_3) (<= v_b_152_3 v_idx_363) (< v_idx_363 v_b_151_3)) (<= v_b_153_3 .cse12) (<= v_b_159_3 .cse2) (<= (+ c_ULTIMATE.start_main_p5 2) v_b_159_3) (<= .cse6 c_ULTIMATE.start_main_p5) (<= .cse5 v_b_155_3) (<= .cse1 v_b_155_3) (<= (+ v_b_150_3 4) v_b_158_3) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_158_3) (<= .cse3 v_b_153_3) (or (<= v_b_154_3 v_idx_365) (< v_idx_365 v_b_153_3) (= (select |c_#memory_int| v_idx_365) v_v_1623_3)) (or (= (select |c_#memory_int| v_idx_367) v_v_1625_3) (<= c_ULTIMATE.start_main_p5 v_idx_367) (< v_idx_367 v_b_155_3)) (<= .cse10 v_b_151_3) (or (<= .cse11 v_idx_368) (< v_idx_368 c_ULTIMATE.start_main_p5) (= v_v_1626_3 (select |c_#memory_int| v_idx_368))) (<= .cse13 c_ULTIMATE.start_main_p5) (<= v_b_151_3 v_b_152_3) (or (<= v_b_153_3 v_idx_364) (< v_idx_364 v_b_152_3) (= (select |c_#memory_int| v_idx_364) 0)) (or (< v_idx_371 v_b_159_3) (= (select |c_#memory_int| v_idx_371) v_v_1629_3)) (<= .cse12 v_b_153_3) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_3) (<= (+ v_b_151_3 3) v_b_158_3) (<= (+ v_b_153_3 3) v_b_159_3) (<= .cse8 v_b_154_3) (<= .cse14 c_ULTIMATE.start_main_p5) (or (<= v_b_150_3 v_idx_361) (< v_idx_361 .cse0) (= (select |c_#memory_int| v_idx_361) v_v_1619_3)) (<= .cse12 v_b_154_3) (<= v_b_155_3 c_ULTIMATE.start_main_p5) (<= (+ v_b_150_3 5) v_b_159_3) (<= .cse14 v_b_155_3) (<= (+ v_b_151_3 4) v_b_159_3) (<= (+ v_b_154_3 3) v_b_159_3) (<= (+ v_b_154_3 2) v_b_158_3) (<= 0 v_v_1626_3) (<= .cse11 v_b_158_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_359) (= (select |c_#memory_int| v_idx_359) v_v_1617_3)) (<= v_b_151_3 .cse10) (<= .cse13 v_b_155_3) (<= (+ v_b_153_3 2) v_b_158_3) (<= .cse7 v_b_154_3) (or (<= v_b_159_3 v_idx_370) (= 0 (select |c_#memory_int| v_idx_370)) (< v_idx_370 v_b_158_3)) (<= v_b_155_3 .cse6))))) is different from false [2019-01-11 11:46:44,733 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_379 Int) (v_idx_377 Int) (v_idx_378 Int) (v_idx_382 Int) (v_idx_383 Int) (v_idx_372 Int) (v_idx_380 Int) (v_idx_381 Int) (v_idx_375 Int) (v_idx_376 Int) (v_idx_384 Int) (v_idx_373 Int) (v_idx_374 Int)) (exists ((v_v_1621_3 Int) (v_v_1623_3 Int) (v_v_1626_3 Int) (v_v_1625_3 Int) (v_b_159_3 Int) (v_b_158_3 Int) (v_b_157_3 Int) (v_b_156_3 Int) (v_b_151_3 Int) (v_b_150_3 Int) (v_b_155_3 Int) (v_v_1629_3 Int) (v_b_154_3 Int) (v_v_1627_3 Int) (v_b_153_3 Int) (v_b_152_3 Int) (v_v_1617_3 Int) (v_v_1619_3 Int)) (let ((.cse0 (+ v_b_155_3 1)) (.cse6 (+ v_b_152_3 3)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse10 (+ c_ULTIMATE.start_main_p1 4)) (.cse2 (+ v_b_158_3 1)) (.cse1 (+ v_b_150_3 3)) (.cse17 (+ v_b_150_3 4)) (.cse5 (+ v_b_150_3 2)) (.cse19 (+ c_ULTIMATE.start_main_p1 5)) (.cse20 (+ v_b_156_3 1)) (.cse16 (+ v_b_151_3 3)) (.cse12 (+ v_b_151_3 1)) (.cse15 (+ v_b_152_3 1)) (.cse9 (+ v_b_151_3 2)) (.cse3 (+ v_b_154_3 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse13 (+ v_b_150_3 1)) (.cse18 (+ v_b_153_3 1)) (.cse21 (+ v_b_152_3 2)) (.cse14 (+ v_b_153_3 2)) (.cse11 (+ c_ULTIMATE.start_main_p1 3)) (.cse8 (+ v_b_154_3 1))) (and (<= .cse0 v_b_157_3) (<= .cse1 v_b_156_3) (<= .cse2 v_b_159_3) (or (< v_idx_382 v_b_157_3) (= (select |c_#memory_int| v_idx_382) v_v_1627_3) (<= v_b_158_3 v_idx_382)) (or (<= v_b_153_3 v_idx_377) (< v_idx_377 v_b_152_3) (= 0 (select |c_#memory_int| v_idx_377))) (<= (+ v_b_157_3 1) v_b_159_3) (or (= (select |c_#memory_int| v_idx_372) v_v_1617_3) (<= c_ULTIMATE.start_main_p1 v_idx_372)) (<= .cse3 v_b_157_3) (<= .cse4 v_b_150_3) (or (= (select |c_#memory_int| v_idx_376) v_v_1621_3) (< v_idx_376 v_b_151_3) (<= v_b_152_3 v_idx_376)) (or (= (select |c_#memory_int| v_idx_384) v_v_1629_3) (< v_idx_384 v_b_159_3)) (<= .cse5 v_b_154_3) (<= .cse6 v_b_157_3) (<= .cse0 v_b_158_3) (<= .cse7 v_b_152_3) (or (= 0 (select |c_#memory_int| v_idx_383)) (< v_idx_383 v_b_158_3) (<= v_b_159_3 v_idx_383)) (or (< v_idx_380 v_b_155_3) (<= v_b_156_3 v_idx_380) (= (select |c_#memory_int| v_idx_380) v_v_1625_3)) (<= v_b_153_3 v_b_154_3) (<= .cse8 v_b_155_3) (<= .cse6 v_b_158_3) (<= .cse9 v_b_156_3) (<= (+ v_b_152_3 4) v_b_159_3) (<= .cse10 v_b_156_3) (<= .cse11 v_b_153_3) (<= 0 (* 2 v_v_1626_3)) (<= .cse12 v_b_153_3) (<= v_b_157_3 v_b_158_3) (<= .cse7 v_b_151_3) (<= .cse10 v_b_155_3) (<= (+ v_b_155_3 2) v_b_159_3) (<= v_b_155_3 v_b_156_3) (<= .cse13 v_b_152_3) (<= .cse14 v_b_157_3) (<= v_b_153_3 .cse15) (<= v_b_159_3 .cse2) (<= .cse16 v_b_157_3) (<= .cse17 v_b_157_3) (<= .cse1 v_b_155_3) (or (= 0 (select |c_#memory_int| v_idx_373)) (<= .cse4 v_idx_373) (< v_idx_373 c_ULTIMATE.start_main_p1)) (or (< v_idx_381 v_b_156_3) (<= v_b_157_3 v_idx_381) (= (select |c_#memory_int| v_idx_381) v_v_1626_3)) (<= .cse18 v_b_155_3) (<= (+ v_b_156_3 2) v_b_159_3) (<= .cse17 v_b_158_3) (<= .cse19 v_b_158_3) (<= .cse5 v_b_153_3) (<= v_b_157_3 .cse20) (<= .cse13 v_b_151_3) (<= .cse21 v_b_156_3) (or (< v_idx_375 v_b_150_3) (<= v_b_151_3 v_idx_375) (= 0 (select |c_#memory_int| v_idx_375))) (<= v_b_151_3 v_b_152_3) (<= .cse19 v_b_157_3) (<= .cse20 v_b_157_3) (<= .cse15 v_b_153_3) (<= .cse20 v_b_158_3) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_3) (<= .cse16 v_b_158_3) (<= (+ v_b_153_3 3) v_b_159_3) (<= .cse12 v_b_154_3) (<= .cse15 v_b_154_3) (<= (+ v_b_150_3 5) v_b_159_3) (<= .cse9 v_b_155_3) (<= (+ v_b_151_3 4) v_b_159_3) (<= (+ v_b_154_3 3) v_b_159_3) (or (< v_idx_379 v_b_154_3) (= 0 (select |c_#memory_int| v_idx_379)) (<= v_b_155_3 v_idx_379)) (<= .cse3 v_b_158_3) (<= 0 v_v_1626_3) (or (<= v_b_154_3 v_idx_378) (< v_idx_378 v_b_153_3) (= (select |c_#memory_int| v_idx_378) v_v_1623_3)) (or (= (select |c_#memory_int| v_idx_374) v_v_1619_3) (< v_idx_374 .cse4) (<= v_b_150_3 v_idx_374)) (<= v_b_151_3 .cse13) (<= .cse18 v_b_156_3) (<= .cse21 v_b_155_3) (<= .cse14 v_b_158_3) (<= .cse8 v_b_156_3) (<= .cse11 v_b_154_3) (<= v_b_155_3 .cse8))))) is different from false [2019-01-11 11:46:45,106 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:46:45,106 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:46:45,106 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:46:45,106 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:46:45,107 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:46:45,107 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:46:45,107 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:46:45,107 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:46:45,107 INFO L87 Difference]: Start difference. First operand 15 states and 32 transitions. Second operand 4 states. [2019-01-11 11:46:47,604 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_379 Int) (v_idx_377 Int) (v_idx_378 Int) (v_idx_382 Int) (v_idx_383 Int) (v_idx_372 Int) (v_idx_380 Int) (v_idx_381 Int) (v_idx_375 Int) (v_idx_376 Int) (v_idx_384 Int) (v_idx_373 Int) (v_idx_374 Int)) (exists ((v_v_1621_3 Int) (v_v_1623_3 Int) (v_v_1626_3 Int) (v_v_1625_3 Int) (v_b_159_3 Int) (v_b_158_3 Int) (v_b_157_3 Int) (v_b_156_3 Int) (v_b_151_3 Int) (v_b_150_3 Int) (v_b_155_3 Int) (v_v_1629_3 Int) (v_b_154_3 Int) (v_v_1627_3 Int) (v_b_153_3 Int) (v_b_152_3 Int) (v_v_1617_3 Int) (v_v_1619_3 Int)) (let ((.cse0 (+ v_b_155_3 1)) (.cse6 (+ v_b_152_3 3)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse10 (+ c_ULTIMATE.start_main_p1 4)) (.cse2 (+ v_b_158_3 1)) (.cse1 (+ v_b_150_3 3)) (.cse17 (+ v_b_150_3 4)) (.cse5 (+ v_b_150_3 2)) (.cse19 (+ c_ULTIMATE.start_main_p1 5)) (.cse20 (+ v_b_156_3 1)) (.cse16 (+ v_b_151_3 3)) (.cse12 (+ v_b_151_3 1)) (.cse15 (+ v_b_152_3 1)) (.cse9 (+ v_b_151_3 2)) (.cse3 (+ v_b_154_3 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse13 (+ v_b_150_3 1)) (.cse18 (+ v_b_153_3 1)) (.cse21 (+ v_b_152_3 2)) (.cse14 (+ v_b_153_3 2)) (.cse11 (+ c_ULTIMATE.start_main_p1 3)) (.cse8 (+ v_b_154_3 1))) (and (<= .cse0 v_b_157_3) (<= .cse1 v_b_156_3) (<= .cse2 v_b_159_3) (or (< v_idx_382 v_b_157_3) (= (select |c_#memory_int| v_idx_382) v_v_1627_3) (<= v_b_158_3 v_idx_382)) (or (<= v_b_153_3 v_idx_377) (< v_idx_377 v_b_152_3) (= 0 (select |c_#memory_int| v_idx_377))) (<= (+ v_b_157_3 1) v_b_159_3) (or (= (select |c_#memory_int| v_idx_372) v_v_1617_3) (<= c_ULTIMATE.start_main_p1 v_idx_372)) (<= .cse3 v_b_157_3) (<= .cse4 v_b_150_3) (or (= (select |c_#memory_int| v_idx_376) v_v_1621_3) (< v_idx_376 v_b_151_3) (<= v_b_152_3 v_idx_376)) (or (= (select |c_#memory_int| v_idx_384) v_v_1629_3) (< v_idx_384 v_b_159_3)) (<= .cse5 v_b_154_3) (<= .cse6 v_b_157_3) (<= .cse0 v_b_158_3) (<= .cse7 v_b_152_3) (or (= 0 (select |c_#memory_int| v_idx_383)) (< v_idx_383 v_b_158_3) (<= v_b_159_3 v_idx_383)) (or (< v_idx_380 v_b_155_3) (<= v_b_156_3 v_idx_380) (= (select |c_#memory_int| v_idx_380) v_v_1625_3)) (<= v_b_153_3 v_b_154_3) (<= .cse8 v_b_155_3) (<= .cse6 v_b_158_3) (<= .cse9 v_b_156_3) (<= (+ v_b_152_3 4) v_b_159_3) (<= .cse10 v_b_156_3) (<= .cse11 v_b_153_3) (<= 0 (* 2 v_v_1626_3)) (<= .cse12 v_b_153_3) (<= v_b_157_3 v_b_158_3) (<= .cse7 v_b_151_3) (<= .cse10 v_b_155_3) (<= (+ v_b_155_3 2) v_b_159_3) (<= v_b_155_3 v_b_156_3) (<= .cse13 v_b_152_3) (<= .cse14 v_b_157_3) (<= v_b_153_3 .cse15) (<= v_b_159_3 .cse2) (<= .cse16 v_b_157_3) (<= .cse17 v_b_157_3) (<= .cse1 v_b_155_3) (or (= 0 (select |c_#memory_int| v_idx_373)) (<= .cse4 v_idx_373) (< v_idx_373 c_ULTIMATE.start_main_p1)) (or (< v_idx_381 v_b_156_3) (<= v_b_157_3 v_idx_381) (= (select |c_#memory_int| v_idx_381) v_v_1626_3)) (<= .cse18 v_b_155_3) (<= (+ v_b_156_3 2) v_b_159_3) (<= .cse17 v_b_158_3) (<= .cse19 v_b_158_3) (<= .cse5 v_b_153_3) (<= v_b_157_3 .cse20) (<= .cse13 v_b_151_3) (<= .cse21 v_b_156_3) (or (< v_idx_375 v_b_150_3) (<= v_b_151_3 v_idx_375) (= 0 (select |c_#memory_int| v_idx_375))) (<= v_b_151_3 v_b_152_3) (<= .cse19 v_b_157_3) (<= .cse20 v_b_157_3) (<= .cse15 v_b_153_3) (<= .cse20 v_b_158_3) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_3) (<= .cse16 v_b_158_3) (<= (+ v_b_153_3 3) v_b_159_3) (<= .cse12 v_b_154_3) (<= .cse15 v_b_154_3) (<= (+ v_b_150_3 5) v_b_159_3) (<= .cse9 v_b_155_3) (<= (+ v_b_151_3 4) v_b_159_3) (<= (+ v_b_154_3 3) v_b_159_3) (or (< v_idx_379 v_b_154_3) (= 0 (select |c_#memory_int| v_idx_379)) (<= v_b_155_3 v_idx_379)) (<= .cse3 v_b_158_3) (<= 0 v_v_1626_3) (or (<= v_b_154_3 v_idx_378) (< v_idx_378 v_b_153_3) (= (select |c_#memory_int| v_idx_378) v_v_1623_3)) (or (= (select |c_#memory_int| v_idx_374) v_v_1619_3) (< v_idx_374 .cse4) (<= v_b_150_3 v_idx_374)) (<= v_b_151_3 .cse13) (<= .cse18 v_b_156_3) (<= .cse21 v_b_155_3) (<= .cse14 v_b_158_3) (<= .cse8 v_b_156_3) (<= .cse11 v_b_154_3) (<= v_b_155_3 .cse8))))) (forall ((v_idx_368 Int) (v_idx_369 Int) (v_idx_366 Int) (v_idx_367 Int) (v_idx_359 Int) (v_idx_360 Int) (v_idx_371 Int) (v_idx_361 Int) (v_idx_370 Int) (v_idx_364 Int) (v_idx_365 Int) (v_idx_362 Int) (v_idx_363 Int)) (exists ((v_v_1621_3 Int) (v_v_1623_3 Int) (v_v_1626_3 Int) (v_v_1625_3 Int) (v_b_159_3 Int) (v_b_158_3 Int) (v_b_151_3 Int) (v_b_150_3 Int) (v_b_155_3 Int) (v_v_1629_3 Int) (v_b_154_3 Int) (v_v_1627_3 Int) (v_b_153_3 Int) (v_b_152_3 Int) (v_v_1617_3 Int) (v_v_1619_3 Int)) (let ((.cse26 (+ c_ULTIMATE.start_main_p1 2)) (.cse31 (+ c_ULTIMATE.start_main_p1 4)) (.cse24 (+ v_b_158_3 1)) (.cse27 (+ v_b_150_3 3)) (.cse23 (+ v_b_153_3 1)) (.cse25 (+ v_b_150_3 2)) (.cse30 (+ v_b_151_3 1)) (.cse22 (+ c_ULTIMATE.start_main_p1 1)) (.cse34 (+ v_b_152_3 1)) (.cse36 (+ v_b_151_3 2)) (.cse33 (+ c_ULTIMATE.start_main_p5 1)) (.cse32 (+ v_b_150_3 1)) (.cse35 (+ v_b_152_3 2)) (.cse29 (+ c_ULTIMATE.start_main_p1 3)) (.cse28 (+ v_b_154_3 1))) (and (or (<= .cse22 v_idx_360) (= (select |c_#memory_int| v_idx_360) 0) (< v_idx_360 c_ULTIMATE.start_main_p1)) (<= .cse23 c_ULTIMATE.start_main_p5) (or (< v_idx_366 v_b_154_3) (<= v_b_155_3 v_idx_366) (= 0 (select |c_#memory_int| v_idx_366))) (<= .cse24 v_b_159_3) (or (<= v_b_151_3 v_idx_362) (< v_idx_362 v_b_150_3) (= 0 (select |c_#memory_int| v_idx_362))) (<= .cse22 v_b_150_3) (<= .cse25 v_b_154_3) (<= (+ v_b_155_3 1) v_b_158_3) (<= .cse26 v_b_152_3) (<= .cse27 c_ULTIMATE.start_main_p5) (<= v_b_153_3 v_b_154_3) (<= .cse28 v_b_155_3) (<= (+ v_b_152_3 3) v_b_158_3) (<= (+ v_b_152_3 4) v_b_159_3) (<= .cse29 v_b_153_3) (<= 0 (* 2 v_v_1626_3)) (<= .cse30 v_b_153_3) (<= .cse26 v_b_151_3) (<= .cse31 v_b_155_3) (<= .cse31 c_ULTIMATE.start_main_p5) (<= (+ v_b_155_3 2) v_b_159_3) (<= .cse32 v_b_152_3) (or (<= v_b_158_3 v_idx_369) (< v_idx_369 .cse33) (= (select |c_#memory_int| v_idx_369) v_v_1627_3)) (or (= (select |c_#memory_int| v_idx_363) v_v_1621_3) (<= v_b_152_3 v_idx_363) (< v_idx_363 v_b_151_3)) (<= v_b_153_3 .cse34) (<= v_b_159_3 .cse24) (<= (+ c_ULTIMATE.start_main_p5 2) v_b_159_3) (<= .cse28 c_ULTIMATE.start_main_p5) (<= .cse27 v_b_155_3) (<= .cse23 v_b_155_3) (<= (+ v_b_150_3 4) v_b_158_3) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_158_3) (<= .cse25 v_b_153_3) (or (<= v_b_154_3 v_idx_365) (< v_idx_365 v_b_153_3) (= (select |c_#memory_int| v_idx_365) v_v_1623_3)) (or (= (select |c_#memory_int| v_idx_367) v_v_1625_3) (<= c_ULTIMATE.start_main_p5 v_idx_367) (< v_idx_367 v_b_155_3)) (<= .cse32 v_b_151_3) (or (<= .cse33 v_idx_368) (< v_idx_368 c_ULTIMATE.start_main_p5) (= v_v_1626_3 (select |c_#memory_int| v_idx_368))) (<= .cse35 c_ULTIMATE.start_main_p5) (<= v_b_151_3 v_b_152_3) (or (<= v_b_153_3 v_idx_364) (< v_idx_364 v_b_152_3) (= (select |c_#memory_int| v_idx_364) 0)) (or (< v_idx_371 v_b_159_3) (= (select |c_#memory_int| v_idx_371) v_v_1629_3)) (<= .cse34 v_b_153_3) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_159_3) (<= (+ v_b_151_3 3) v_b_158_3) (<= (+ v_b_153_3 3) v_b_159_3) (<= .cse30 v_b_154_3) (<= .cse36 c_ULTIMATE.start_main_p5) (or (<= v_b_150_3 v_idx_361) (< v_idx_361 .cse22) (= (select |c_#memory_int| v_idx_361) v_v_1619_3)) (<= .cse34 v_b_154_3) (<= v_b_155_3 c_ULTIMATE.start_main_p5) (<= (+ v_b_150_3 5) v_b_159_3) (<= .cse36 v_b_155_3) (<= (+ v_b_151_3 4) v_b_159_3) (<= (+ v_b_154_3 3) v_b_159_3) (<= (+ v_b_154_3 2) v_b_158_3) (<= 0 v_v_1626_3) (<= .cse33 v_b_158_3) (or (<= c_ULTIMATE.start_main_p1 v_idx_359) (= (select |c_#memory_int| v_idx_359) v_v_1617_3)) (<= v_b_151_3 .cse32) (<= .cse35 v_b_155_3) (<= (+ v_b_153_3 2) v_b_158_3) (<= .cse29 v_b_154_3) (or (<= v_b_159_3 v_idx_370) (= 0 (select |c_#memory_int| v_idx_370)) (< v_idx_370 v_b_158_3)) (<= v_b_155_3 .cse28)))))) is different from false [2019-01-11 11:47:06,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:47:06,075 INFO L93 Difference]: Finished difference Result 17 states and 40 transitions. [2019-01-11 11:47:06,075 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:47:06,075 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:47:06,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:47:06,076 INFO L225 Difference]: With dead ends: 17 [2019-01-11 11:47:06,076 INFO L226 Difference]: Without dead ends: 16 [2019-01-11 11:47:06,076 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.4s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:47:06,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-11 11:47:06,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2019-01-11 11:47:06,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-11 11:47:06,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 32 transitions. [2019-01-11 11:47:06,086 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 32 transitions. Word has length 3 [2019-01-11 11:47:06,087 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:47:06,087 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 32 transitions. [2019-01-11 11:47:06,087 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:47:06,087 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 32 transitions. [2019-01-11 11:47:06,087 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:47:06,087 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:47:06,088 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:47:06,088 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:47:06,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:06,088 INFO L82 PathProgramCache]: Analyzing trace with hash 30562, now seen corresponding path program 1 times [2019-01-11 11:47:06,088 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:47:06,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:06,090 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:47:06,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:06,090 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:47:06,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:47:06,162 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:47:06,163 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:47:06,163 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:47:06,163 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:47:06,163 INFO L207 CegarAbsIntRunner]: [0], [24], [27] [2019-01-11 11:47:06,165 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:47:06,165 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:47:15,898 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:47:15,898 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:47:15,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:15,899 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:47:16,373 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 75% of their original sizes. [2019-01-11 11:47:16,374 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:47:19,265 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_489 Int) (v_idx_487 Int) (v_idx_498 Int) (v_idx_488 Int) (v_idx_499 Int) (v_idx_492 Int) (v_idx_493 Int) (v_idx_490 Int) (v_idx_491 Int) (v_idx_496 Int) (v_idx_497 Int) (v_idx_494 Int) (v_idx_495 Int)) (exists ((v_v_1600_4 Int) (v_v_1602_4 Int) (v_b_169_4 Int) (v_b_168_4 Int) (v_b_167_4 Int) (v_b_166_4 Int) (v_b_170_4 Int) (v_b_171_4 Int) (v_b_172_4 Int) (v_b_173_4 Int) (v_v_1604_4 Int) (v_v_1598_4 Int) (v_v_1607_4 Int) (v_v_1596_4 Int) (v_v_1606_4 Int) (v_v_1608_4 Int)) (let ((.cse3 (+ v_b_169_4 2)) (.cse6 (+ v_b_166_4 3)) (.cse4 (+ v_b_171_4 1)) (.cse5 (+ v_b_166_4 2)) (.cse13 (+ v_b_167_4 3)) (.cse0 (+ v_b_166_4 1)) (.cse10 (+ v_b_166_4 4)) (.cse8 (+ v_b_170_4 1)) (.cse19 (+ c_ULTIMATE.start_main_p1 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse17 (+ v_b_167_4 2)) (.cse12 (+ c_ULTIMATE.start_main_p6 1)) (.cse18 (+ v_b_169_4 1)) (.cse15 (+ c_ULTIMATE.start_main_p1 5)) (.cse2 (+ v_b_168_4 1)) (.cse11 (+ v_b_172_4 1)) (.cse7 (+ v_b_168_4 2)) (.cse21 (+ v_b_170_4 2)) (.cse14 (+ c_ULTIMATE.start_main_p1 1)) (.cse20 (+ c_ULTIMATE.start_main_p1 4)) (.cse16 (+ v_b_167_4 1)) (.cse9 (+ v_b_168_4 3))) (and (<= .cse0 v_b_168_4) (or (= (select |c_#memory_int| v_idx_490) 0) (<= v_b_167_4 v_idx_490) (< v_idx_490 v_b_166_4)) (<= v_v_1607_4 0) (<= .cse1 v_b_169_4) (or (<= v_b_170_4 v_idx_493) (< v_idx_493 v_b_169_4) (= (select |c_#memory_int| v_idx_493) v_v_1602_4)) (<= v_b_169_4 .cse2) (<= .cse3 v_b_173_4) (<= .cse4 c_ULTIMATE.start_main_p6) (or (<= v_b_169_4 v_idx_492) (< v_idx_492 v_b_168_4) (= (select |c_#memory_int| v_idx_492) 0)) (<= v_b_173_4 c_ULTIMATE.start_main_p6) (<= v_b_171_4 v_b_172_4) (<= .cse5 v_b_169_4) (<= v_b_169_4 v_b_170_4) (<= .cse2 v_b_170_4) (<= .cse6 v_b_171_4) (<= .cse7 v_b_172_4) (<= .cse3 c_ULTIMATE.start_main_p6) (<= v_b_171_4 .cse8) (<= .cse9 v_b_173_4) (<= .cse6 v_b_172_4) (<= .cse10 v_b_173_4) (or (= (select |c_#memory_int| v_idx_487) v_v_1596_4) (<= c_ULTIMATE.start_main_p1 v_idx_487)) (<= .cse11 c_ULTIMATE.start_main_p6) (<= .cse4 v_b_173_4) (or (<= v_b_172_4 v_idx_495) (< v_idx_495 v_b_171_4) (= (select |c_#memory_int| v_idx_495) v_v_1604_4)) (or (= (select |c_#memory_int| v_idx_498) v_v_1607_4) (< v_idx_498 c_ULTIMATE.start_main_p6) (<= .cse12 v_idx_498)) (<= .cse13 c_ULTIMATE.start_main_p6) (<= (* 2 v_v_1607_4) 0) (<= .cse5 v_b_170_4) (<= .cse14 v_b_166_4) (<= .cse0 v_b_167_4) (<= .cse8 v_b_171_4) (<= .cse13 v_b_173_4) (<= v_b_167_4 .cse0) (<= .cse15 v_b_173_4) (<= .cse16 v_b_169_4) (<= .cse10 c_ULTIMATE.start_main_p6) (<= .cse17 v_b_171_4) (<= .cse8 v_b_172_4) (<= .cse18 v_b_171_4) (<= .cse19 v_b_168_4) (or (<= .cse14 v_idx_488) (< v_idx_488 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_488) 0)) (or (<= c_ULTIMATE.start_main_p6 v_idx_497) (= (select |c_#memory_int| v_idx_497) v_v_1606_4) (< v_idx_497 v_b_173_4)) (<= .cse19 v_b_167_4) (<= .cse1 v_b_170_4) (or (< v_idx_491 v_b_167_4) (<= v_b_168_4 v_idx_491) (= (select |c_#memory_int| v_idx_491) v_v_1600_4)) (<= .cse17 v_b_172_4) (or (= (select |c_#memory_int| v_idx_499) v_v_1608_4) (< v_idx_499 .cse12)) (<= .cse20 v_b_172_4) (<= .cse18 v_b_172_4) (<= .cse15 c_ULTIMATE.start_main_p6) (<= v_b_173_4 .cse11) (<= .cse2 v_b_169_4) (<= .cse21 c_ULTIMATE.start_main_p6) (or (<= v_b_171_4 v_idx_494) (< v_idx_494 v_b_170_4) (= (select |c_#memory_int| v_idx_494) 0)) (or (<= v_b_173_4 v_idx_496) (= (select |c_#memory_int| v_idx_496) 0) (< v_idx_496 v_b_172_4)) (<= v_b_167_4 v_b_168_4) (<= .cse11 v_b_173_4) (<= .cse7 v_b_171_4) (<= .cse21 v_b_173_4) (or (< v_idx_489 .cse14) (= (select |c_#memory_int| v_idx_489) v_v_1598_4) (<= v_b_166_4 v_idx_489)) (<= .cse20 v_b_171_4) (<= .cse16 v_b_170_4) (<= .cse9 c_ULTIMATE.start_main_p6))))) is different from false [2019-01-11 11:47:21,688 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_508 Int) (v_idx_509 Int) (v_idx_506 Int) (v_idx_507 Int) (v_idx_500 Int) (v_idx_511 Int) (v_idx_501 Int) (v_idx_512 Int) (v_idx_510 Int) (v_idx_504 Int) (v_idx_505 Int) (v_idx_502 Int) (v_idx_503 Int)) (exists ((v_v_1600_4 Int) (v_v_1602_4 Int) (v_b_169_4 Int) (v_b_168_4 Int) (v_b_167_4 Int) (v_b_166_4 Int) (v_b_170_4 Int) (v_b_171_4 Int) (v_b_172_4 Int) (v_b_173_4 Int) (v_b_174_4 Int) (v_b_175_4 Int) (v_v_1604_4 Int) (v_v_1598_4 Int) (v_v_1607_4 Int) (v_v_1596_4 Int) (v_v_1606_4 Int) (v_v_1608_4 Int)) (let ((.cse2 (+ v_b_169_4 2)) (.cse6 (+ v_b_166_4 3)) (.cse7 (+ v_b_171_4 1)) (.cse5 (+ v_b_166_4 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ v_b_166_4 1)) (.cse10 (+ v_b_170_4 1)) (.cse19 (+ c_ULTIMATE.start_main_p1 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse15 (+ c_ULTIMATE.start_main_p1 5)) (.cse17 (+ v_b_167_4 2)) (.cse18 (+ v_b_169_4 1)) (.cse14 (+ v_b_167_4 3)) (.cse3 (+ v_b_168_4 1)) (.cse12 (+ v_b_166_4 4)) (.cse8 (+ v_b_174_4 1)) (.cse13 (+ v_b_172_4 1)) (.cse9 (+ v_b_168_4 2)) (.cse20 (+ v_b_170_4 2)) (.cse21 (+ c_ULTIMATE.start_main_p1 4)) (.cse16 (+ v_b_167_4 1)) (.cse11 (+ v_b_168_4 3))) (and (<= .cse0 v_b_168_4) (<= v_v_1607_4 0) (or (<= c_ULTIMATE.start_main_p1 v_idx_500) (= (select |c_#memory_int| v_idx_500) v_v_1596_4)) (<= .cse1 v_b_169_4) (<= .cse2 v_b_174_4) (or (< v_idx_508 v_b_171_4) (= (select |c_#memory_int| v_idx_508) v_v_1604_4) (<= v_b_172_4 v_idx_508)) (<= v_b_169_4 .cse3) (<= (+ v_b_171_4 2) v_b_175_4) (<= .cse2 v_b_173_4) (or (= (select |c_#memory_int| v_idx_510) v_v_1606_4) (<= v_b_174_4 v_idx_510) (< v_idx_510 v_b_173_4)) (or (< v_idx_502 .cse4) (<= v_b_166_4 v_idx_502) (= (select |c_#memory_int| v_idx_502) v_v_1598_4)) (or (< v_idx_506 v_b_169_4) (<= v_b_170_4 v_idx_506) (= (select |c_#memory_int| v_idx_506) v_v_1602_4)) (<= (+ v_b_170_4 3) v_b_175_4) (<= v_b_171_4 v_b_172_4) (<= .cse5 v_b_169_4) (<= v_b_169_4 v_b_170_4) (<= v_b_173_4 v_b_174_4) (<= .cse3 v_b_170_4) (<= .cse6 v_b_171_4) (<= .cse7 v_b_174_4) (<= .cse8 v_b_175_4) (<= .cse9 v_b_172_4) (or (= 0 (select |c_#memory_int| v_idx_501)) (<= .cse4 v_idx_501) (< v_idx_501 c_ULTIMATE.start_main_p1)) (<= v_b_171_4 .cse10) (or (<= v_b_167_4 v_idx_503) (< v_idx_503 v_b_166_4) (= 0 (select |c_#memory_int| v_idx_503))) (<= .cse11 v_b_173_4) (<= .cse6 v_b_172_4) (<= .cse12 v_b_173_4) (or (<= v_b_169_4 v_idx_505) (= 0 (select |c_#memory_int| v_idx_505)) (< v_idx_505 v_b_168_4)) (<= .cse7 v_b_173_4) (<= (* 2 v_v_1607_4) 0) (<= .cse13 v_b_174_4) (<= .cse5 v_b_170_4) (<= .cse4 v_b_166_4) (<= .cse0 v_b_167_4) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_4) (<= .cse10 v_b_171_4) (<= .cse14 v_b_173_4) (<= v_b_167_4 .cse0) (<= .cse15 v_b_173_4) (or (< v_idx_504 v_b_167_4) (<= v_b_168_4 v_idx_504) (= (select |c_#memory_int| v_idx_504) v_v_1600_4)) (<= .cse16 v_b_169_4) (<= .cse17 v_b_171_4) (<= .cse10 v_b_172_4) (<= .cse18 v_b_171_4) (<= .cse19 v_b_168_4) (<= .cse19 v_b_167_4) (<= .cse1 v_b_170_4) (<= .cse15 v_b_174_4) (<= .cse17 v_b_172_4) (<= .cse20 v_b_174_4) (<= .cse21 v_b_172_4) (<= .cse18 v_b_172_4) (<= (+ v_b_172_4 2) v_b_175_4) (<= v_b_173_4 .cse13) (<= .cse14 v_b_174_4) (<= (+ v_b_173_4 1) v_b_175_4) (<= .cse3 v_b_169_4) (<= .cse12 v_b_174_4) (<= v_b_175_4 .cse8) (<= v_b_167_4 v_b_168_4) (<= .cse13 v_b_173_4) (<= .cse9 v_b_171_4) (<= (+ v_b_169_4 3) v_b_175_4) (<= .cse20 v_b_173_4) (<= (+ v_b_167_4 4) v_b_175_4) (<= (+ v_b_166_4 5) v_b_175_4) (<= (+ v_b_168_4 4) v_b_175_4) (or (= (select |c_#memory_int| v_idx_512) v_v_1608_4) (< v_idx_512 v_b_175_4)) (or (<= v_b_173_4 v_idx_509) (= 0 (select |c_#memory_int| v_idx_509)) (< v_idx_509 v_b_172_4)) (or (< v_idx_511 v_b_174_4) (<= v_b_175_4 v_idx_511) (= (select |c_#memory_int| v_idx_511) v_v_1607_4)) (<= .cse21 v_b_171_4) (<= .cse16 v_b_170_4) (<= .cse11 v_b_174_4) (or (= 0 (select |c_#memory_int| v_idx_507)) (< v_idx_507 v_b_170_4) (<= v_b_171_4 v_idx_507)))))) is different from false [2019-01-11 11:47:21,892 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:47:21,893 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:47:21,893 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:47:21,893 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:47:21,893 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:47:21,893 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:47:21,894 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:47:21,894 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:47:21,894 INFO L87 Difference]: Start difference. First operand 15 states and 32 transitions. Second operand 4 states. [2019-01-11 11:47:24,686 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_508 Int) (v_idx_509 Int) (v_idx_506 Int) (v_idx_507 Int) (v_idx_500 Int) (v_idx_511 Int) (v_idx_501 Int) (v_idx_512 Int) (v_idx_510 Int) (v_idx_504 Int) (v_idx_505 Int) (v_idx_502 Int) (v_idx_503 Int)) (exists ((v_v_1600_4 Int) (v_v_1602_4 Int) (v_b_169_4 Int) (v_b_168_4 Int) (v_b_167_4 Int) (v_b_166_4 Int) (v_b_170_4 Int) (v_b_171_4 Int) (v_b_172_4 Int) (v_b_173_4 Int) (v_b_174_4 Int) (v_b_175_4 Int) (v_v_1604_4 Int) (v_v_1598_4 Int) (v_v_1607_4 Int) (v_v_1596_4 Int) (v_v_1606_4 Int) (v_v_1608_4 Int)) (let ((.cse2 (+ v_b_169_4 2)) (.cse6 (+ v_b_166_4 3)) (.cse7 (+ v_b_171_4 1)) (.cse5 (+ v_b_166_4 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ v_b_166_4 1)) (.cse10 (+ v_b_170_4 1)) (.cse19 (+ c_ULTIMATE.start_main_p1 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 3)) (.cse15 (+ c_ULTIMATE.start_main_p1 5)) (.cse17 (+ v_b_167_4 2)) (.cse18 (+ v_b_169_4 1)) (.cse14 (+ v_b_167_4 3)) (.cse3 (+ v_b_168_4 1)) (.cse12 (+ v_b_166_4 4)) (.cse8 (+ v_b_174_4 1)) (.cse13 (+ v_b_172_4 1)) (.cse9 (+ v_b_168_4 2)) (.cse20 (+ v_b_170_4 2)) (.cse21 (+ c_ULTIMATE.start_main_p1 4)) (.cse16 (+ v_b_167_4 1)) (.cse11 (+ v_b_168_4 3))) (and (<= .cse0 v_b_168_4) (<= v_v_1607_4 0) (or (<= c_ULTIMATE.start_main_p1 v_idx_500) (= (select |c_#memory_int| v_idx_500) v_v_1596_4)) (<= .cse1 v_b_169_4) (<= .cse2 v_b_174_4) (or (< v_idx_508 v_b_171_4) (= (select |c_#memory_int| v_idx_508) v_v_1604_4) (<= v_b_172_4 v_idx_508)) (<= v_b_169_4 .cse3) (<= (+ v_b_171_4 2) v_b_175_4) (<= .cse2 v_b_173_4) (or (= (select |c_#memory_int| v_idx_510) v_v_1606_4) (<= v_b_174_4 v_idx_510) (< v_idx_510 v_b_173_4)) (or (< v_idx_502 .cse4) (<= v_b_166_4 v_idx_502) (= (select |c_#memory_int| v_idx_502) v_v_1598_4)) (or (< v_idx_506 v_b_169_4) (<= v_b_170_4 v_idx_506) (= (select |c_#memory_int| v_idx_506) v_v_1602_4)) (<= (+ v_b_170_4 3) v_b_175_4) (<= v_b_171_4 v_b_172_4) (<= .cse5 v_b_169_4) (<= v_b_169_4 v_b_170_4) (<= v_b_173_4 v_b_174_4) (<= .cse3 v_b_170_4) (<= .cse6 v_b_171_4) (<= .cse7 v_b_174_4) (<= .cse8 v_b_175_4) (<= .cse9 v_b_172_4) (or (= 0 (select |c_#memory_int| v_idx_501)) (<= .cse4 v_idx_501) (< v_idx_501 c_ULTIMATE.start_main_p1)) (<= v_b_171_4 .cse10) (or (<= v_b_167_4 v_idx_503) (< v_idx_503 v_b_166_4) (= 0 (select |c_#memory_int| v_idx_503))) (<= .cse11 v_b_173_4) (<= .cse6 v_b_172_4) (<= .cse12 v_b_173_4) (or (<= v_b_169_4 v_idx_505) (= 0 (select |c_#memory_int| v_idx_505)) (< v_idx_505 v_b_168_4)) (<= .cse7 v_b_173_4) (<= (* 2 v_v_1607_4) 0) (<= .cse13 v_b_174_4) (<= .cse5 v_b_170_4) (<= .cse4 v_b_166_4) (<= .cse0 v_b_167_4) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_4) (<= .cse10 v_b_171_4) (<= .cse14 v_b_173_4) (<= v_b_167_4 .cse0) (<= .cse15 v_b_173_4) (or (< v_idx_504 v_b_167_4) (<= v_b_168_4 v_idx_504) (= (select |c_#memory_int| v_idx_504) v_v_1600_4)) (<= .cse16 v_b_169_4) (<= .cse17 v_b_171_4) (<= .cse10 v_b_172_4) (<= .cse18 v_b_171_4) (<= .cse19 v_b_168_4) (<= .cse19 v_b_167_4) (<= .cse1 v_b_170_4) (<= .cse15 v_b_174_4) (<= .cse17 v_b_172_4) (<= .cse20 v_b_174_4) (<= .cse21 v_b_172_4) (<= .cse18 v_b_172_4) (<= (+ v_b_172_4 2) v_b_175_4) (<= v_b_173_4 .cse13) (<= .cse14 v_b_174_4) (<= (+ v_b_173_4 1) v_b_175_4) (<= .cse3 v_b_169_4) (<= .cse12 v_b_174_4) (<= v_b_175_4 .cse8) (<= v_b_167_4 v_b_168_4) (<= .cse13 v_b_173_4) (<= .cse9 v_b_171_4) (<= (+ v_b_169_4 3) v_b_175_4) (<= .cse20 v_b_173_4) (<= (+ v_b_167_4 4) v_b_175_4) (<= (+ v_b_166_4 5) v_b_175_4) (<= (+ v_b_168_4 4) v_b_175_4) (or (= (select |c_#memory_int| v_idx_512) v_v_1608_4) (< v_idx_512 v_b_175_4)) (or (<= v_b_173_4 v_idx_509) (= 0 (select |c_#memory_int| v_idx_509)) (< v_idx_509 v_b_172_4)) (or (< v_idx_511 v_b_174_4) (<= v_b_175_4 v_idx_511) (= (select |c_#memory_int| v_idx_511) v_v_1607_4)) (<= .cse21 v_b_171_4) (<= .cse16 v_b_170_4) (<= .cse11 v_b_174_4) (or (= 0 (select |c_#memory_int| v_idx_507)) (< v_idx_507 v_b_170_4) (<= v_b_171_4 v_idx_507)))))) (forall ((v_idx_489 Int) (v_idx_487 Int) (v_idx_498 Int) (v_idx_488 Int) (v_idx_499 Int) (v_idx_492 Int) (v_idx_493 Int) (v_idx_490 Int) (v_idx_491 Int) (v_idx_496 Int) (v_idx_497 Int) (v_idx_494 Int) (v_idx_495 Int)) (exists ((v_v_1600_4 Int) (v_v_1602_4 Int) (v_b_169_4 Int) (v_b_168_4 Int) (v_b_167_4 Int) (v_b_166_4 Int) (v_b_170_4 Int) (v_b_171_4 Int) (v_b_172_4 Int) (v_b_173_4 Int) (v_v_1604_4 Int) (v_v_1598_4 Int) (v_v_1607_4 Int) (v_v_1596_4 Int) (v_v_1606_4 Int) (v_v_1608_4 Int)) (let ((.cse25 (+ v_b_169_4 2)) (.cse28 (+ v_b_166_4 3)) (.cse26 (+ v_b_171_4 1)) (.cse27 (+ v_b_166_4 2)) (.cse35 (+ v_b_167_4 3)) (.cse22 (+ v_b_166_4 1)) (.cse32 (+ v_b_166_4 4)) (.cse30 (+ v_b_170_4 1)) (.cse41 (+ c_ULTIMATE.start_main_p1 2)) (.cse23 (+ c_ULTIMATE.start_main_p1 3)) (.cse39 (+ v_b_167_4 2)) (.cse34 (+ c_ULTIMATE.start_main_p6 1)) (.cse40 (+ v_b_169_4 1)) (.cse37 (+ c_ULTIMATE.start_main_p1 5)) (.cse24 (+ v_b_168_4 1)) (.cse33 (+ v_b_172_4 1)) (.cse29 (+ v_b_168_4 2)) (.cse43 (+ v_b_170_4 2)) (.cse36 (+ c_ULTIMATE.start_main_p1 1)) (.cse42 (+ c_ULTIMATE.start_main_p1 4)) (.cse38 (+ v_b_167_4 1)) (.cse31 (+ v_b_168_4 3))) (and (<= .cse22 v_b_168_4) (or (= (select |c_#memory_int| v_idx_490) 0) (<= v_b_167_4 v_idx_490) (< v_idx_490 v_b_166_4)) (<= v_v_1607_4 0) (<= .cse23 v_b_169_4) (or (<= v_b_170_4 v_idx_493) (< v_idx_493 v_b_169_4) (= (select |c_#memory_int| v_idx_493) v_v_1602_4)) (<= v_b_169_4 .cse24) (<= .cse25 v_b_173_4) (<= .cse26 c_ULTIMATE.start_main_p6) (or (<= v_b_169_4 v_idx_492) (< v_idx_492 v_b_168_4) (= (select |c_#memory_int| v_idx_492) 0)) (<= v_b_173_4 c_ULTIMATE.start_main_p6) (<= v_b_171_4 v_b_172_4) (<= .cse27 v_b_169_4) (<= v_b_169_4 v_b_170_4) (<= .cse24 v_b_170_4) (<= .cse28 v_b_171_4) (<= .cse29 v_b_172_4) (<= .cse25 c_ULTIMATE.start_main_p6) (<= v_b_171_4 .cse30) (<= .cse31 v_b_173_4) (<= .cse28 v_b_172_4) (<= .cse32 v_b_173_4) (or (= (select |c_#memory_int| v_idx_487) v_v_1596_4) (<= c_ULTIMATE.start_main_p1 v_idx_487)) (<= .cse33 c_ULTIMATE.start_main_p6) (<= .cse26 v_b_173_4) (or (<= v_b_172_4 v_idx_495) (< v_idx_495 v_b_171_4) (= (select |c_#memory_int| v_idx_495) v_v_1604_4)) (or (= (select |c_#memory_int| v_idx_498) v_v_1607_4) (< v_idx_498 c_ULTIMATE.start_main_p6) (<= .cse34 v_idx_498)) (<= .cse35 c_ULTIMATE.start_main_p6) (<= (* 2 v_v_1607_4) 0) (<= .cse27 v_b_170_4) (<= .cse36 v_b_166_4) (<= .cse22 v_b_167_4) (<= .cse30 v_b_171_4) (<= .cse35 v_b_173_4) (<= v_b_167_4 .cse22) (<= .cse37 v_b_173_4) (<= .cse38 v_b_169_4) (<= .cse32 c_ULTIMATE.start_main_p6) (<= .cse39 v_b_171_4) (<= .cse30 v_b_172_4) (<= .cse40 v_b_171_4) (<= .cse41 v_b_168_4) (or (<= .cse36 v_idx_488) (< v_idx_488 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_488) 0)) (or (<= c_ULTIMATE.start_main_p6 v_idx_497) (= (select |c_#memory_int| v_idx_497) v_v_1606_4) (< v_idx_497 v_b_173_4)) (<= .cse41 v_b_167_4) (<= .cse23 v_b_170_4) (or (< v_idx_491 v_b_167_4) (<= v_b_168_4 v_idx_491) (= (select |c_#memory_int| v_idx_491) v_v_1600_4)) (<= .cse39 v_b_172_4) (or (= (select |c_#memory_int| v_idx_499) v_v_1608_4) (< v_idx_499 .cse34)) (<= .cse42 v_b_172_4) (<= .cse40 v_b_172_4) (<= .cse37 c_ULTIMATE.start_main_p6) (<= v_b_173_4 .cse33) (<= .cse24 v_b_169_4) (<= .cse43 c_ULTIMATE.start_main_p6) (or (<= v_b_171_4 v_idx_494) (< v_idx_494 v_b_170_4) (= (select |c_#memory_int| v_idx_494) 0)) (or (<= v_b_173_4 v_idx_496) (= (select |c_#memory_int| v_idx_496) 0) (< v_idx_496 v_b_172_4)) (<= v_b_167_4 v_b_168_4) (<= .cse33 v_b_173_4) (<= .cse29 v_b_171_4) (<= .cse43 v_b_173_4) (or (< v_idx_489 .cse36) (= (select |c_#memory_int| v_idx_489) v_v_1598_4) (<= v_b_166_4 v_idx_489)) (<= .cse42 v_b_171_4) (<= .cse38 v_b_170_4) (<= .cse31 c_ULTIMATE.start_main_p6)))))) is different from false [2019-01-11 11:47:43,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:47:43,870 INFO L93 Difference]: Finished difference Result 17 states and 40 transitions. [2019-01-11 11:47:43,870 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:47:43,870 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:47:43,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:47:43,871 INFO L225 Difference]: With dead ends: 17 [2019-01-11 11:47:43,871 INFO L226 Difference]: Without dead ends: 16 [2019-01-11 11:47:43,871 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 8.1s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:47:43,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-11 11:47:43,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2019-01-11 11:47:43,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-11 11:47:43,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 32 transitions. [2019-01-11 11:47:43,883 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 32 transitions. Word has length 3 [2019-01-11 11:47:43,883 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:47:43,883 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 32 transitions. [2019-01-11 11:47:43,884 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:47:43,884 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 32 transitions. [2019-01-11 11:47:43,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:47:43,884 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:47:43,884 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:47:43,885 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:47:43,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:43,885 INFO L82 PathProgramCache]: Analyzing trace with hash 30128, now seen corresponding path program 1 times [2019-01-11 11:47:43,885 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:47:43,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:43,886 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:47:43,886 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:43,887 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:47:43,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:47:43,959 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:47:43,959 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:47:43,960 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:47:43,960 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:47:43,960 INFO L207 CegarAbsIntRunner]: [0], [10], [27] [2019-01-11 11:47:43,961 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:47:43,961 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:47:52,515 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:47:52,516 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:47:52,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:52,516 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:47:52,977 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 75% of their original sizes. [2019-01-11 11:47:52,978 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:47:55,397 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_618 Int) (v_idx_619 Int) (v_idx_627 Int) (v_idx_616 Int) (v_idx_617 Int) (v_idx_621 Int) (v_idx_622 Int) (v_idx_620 Int) (v_idx_625 Int) (v_idx_626 Int) (v_idx_615 Int) (v_idx_623 Int) (v_idx_624 Int)) (exists ((v_v_1388_5 Int) (v_v_1389_5 Int) (v_v_1386_5 Int) (v_v_1398_5 Int) (v_b_168_5 Int) (v_v_1396_5 Int) (v_v_1394_5 Int) (v_v_1392_5 Int) (v_v_1390_5 Int) (v_b_169_5 Int) (v_b_170_5 Int) (v_b_171_5 Int) (v_b_172_5 Int) (v_b_173_5 Int) (v_b_174_5 Int) (v_b_175_5 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 3)) (.cse7 (+ c_ULTIMATE.start_main_p2 4)) (.cse2 (+ v_b_170_5 2)) (.cse12 (+ v_b_169_5 1)) (.cse9 (+ v_b_168_5 2)) (.cse11 (+ c_ULTIMATE.start_main_p2 3)) (.cse6 (+ v_b_171_5 1)) (.cse4 (+ v_b_169_5 2)) (.cse0 (+ c_ULTIMATE.start_main_p2 1)) (.cse5 (+ c_ULTIMATE.start_main_p2 2)) (.cse8 (+ v_b_168_5 1)) (.cse14 (+ v_b_168_5 3)) (.cse13 (+ v_b_170_5 1)) (.cse1 (+ v_b_174_5 1)) (.cse16 (+ c_ULTIMATE.start_main_p1 4)) (.cse10 (+ v_b_172_5 1)) (.cse17 (+ c_ULTIMATE.start_main_p1 1)) (.cse15 (+ c_ULTIMATE.start_main_p1 5))) (and (<= (* 2 v_v_1389_5) 0) (or (< v_idx_620 v_b_168_5) (<= v_b_169_5 v_idx_620) (= (select |c_#memory_int| v_idx_620) 0)) (or (= (select |c_#memory_int| v_idx_619) v_v_1390_5) (< v_idx_619 .cse0) (<= v_b_168_5 v_idx_619)) (<= (+ v_b_169_5 3) v_b_175_5) (<= .cse1 v_b_175_5) (<= .cse2 v_b_173_5) (<= .cse3 v_b_170_5) (<= .cse4 v_b_173_5) (<= .cse5 v_b_169_5) (or (< v_idx_627 v_b_175_5) (= (select |c_#memory_int| v_idx_627) v_v_1398_5)) (<= .cse6 v_b_173_5) (<= .cse3 v_b_169_5) (<= .cse7 v_b_173_5) (or (< v_idx_621 v_b_169_5) (= (select |c_#memory_int| v_idx_621) v_v_1392_5) (<= v_b_170_5 v_idx_621)) (or (<= v_b_171_5 v_idx_622) (< v_idx_622 v_b_170_5) (= (select |c_#memory_int| v_idx_622) 0)) (<= v_b_173_5 v_b_174_5) (<= .cse8 v_b_169_5) (<= (+ v_b_170_5 3) v_b_175_5) (<= .cse9 v_b_172_5) (<= .cse10 v_b_174_5) (<= .cse7 v_b_174_5) (<= .cse11 v_b_171_5) (<= .cse2 v_b_174_5) (<= .cse12 v_b_172_5) (<= .cse12 v_b_171_5) (or (= (select |c_#memory_int| v_idx_615) v_v_1386_5) (<= c_ULTIMATE.start_main_p1 v_idx_615)) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_5) (<= .cse9 v_b_171_5) (or (< v_idx_623 v_b_171_5) (<= v_b_172_5 v_idx_623) (= (select |c_#memory_int| v_idx_623) v_v_1394_5)) (<= .cse11 v_b_172_5) (or (<= v_b_174_5 v_idx_625) (< v_idx_625 v_b_173_5) (= (select |c_#memory_int| v_idx_625) v_v_1396_5)) (<= .cse13 v_b_171_5) (or (= (select |c_#memory_int| v_idx_618) v_v_1389_5) (< v_idx_618 c_ULTIMATE.start_main_p2) (<= .cse0 v_idx_618)) (<= (+ v_b_168_5 4) v_b_175_5) (<= v_v_1389_5 0) (<= .cse6 v_b_174_5) (<= v_b_171_5 v_b_172_5) (<= .cse10 v_b_173_5) (<= (+ c_ULTIMATE.start_main_p2 5) v_b_175_5) (<= .cse4 v_b_174_5) (<= .cse0 v_b_168_5) (<= .cse13 v_b_172_5) (<= (+ v_b_171_5 2) v_b_175_5) (<= .cse8 v_b_170_5) (<= .cse14 v_b_174_5) (<= .cse5 v_b_170_5) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_168_5) (<= .cse15 v_b_173_5) (<= .cse16 v_b_172_5) (<= v_b_169_5 .cse8) (<= v_b_169_5 v_b_170_5) (<= .cse14 v_b_173_5) (or (<= .cse17 v_idx_616) (= (select |c_#memory_int| v_idx_616) 0) (< v_idx_616 c_ULTIMATE.start_main_p1)) (or (= (select |c_#memory_int| v_idx_626) 0) (< v_idx_626 v_b_174_5) (<= v_b_175_5 v_idx_626)) (<= (+ v_b_172_5 2) v_b_175_5) (<= v_b_171_5 .cse13) (or (<= v_b_173_5 v_idx_624) (< v_idx_624 v_b_172_5) (= (select |c_#memory_int| v_idx_624) 0)) (<= (+ v_b_173_5 1) v_b_175_5) (<= v_b_175_5 .cse1) (or (< v_idx_617 .cse17) (= (select |c_#memory_int| v_idx_617) v_v_1388_5) (<= c_ULTIMATE.start_main_p2 v_idx_617)) (<= .cse16 v_b_171_5) (<= v_b_173_5 .cse10) (<= .cse17 c_ULTIMATE.start_main_p2) (<= .cse15 v_b_174_5))))) is different from false [2019-01-11 11:47:58,033 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_629 Int) (v_idx_638 Int) (v_idx_628 Int) (v_idx_639 Int) (v_idx_632 Int) (v_idx_633 Int) (v_idx_630 Int) (v_idx_631 Int) (v_idx_636 Int) (v_idx_637 Int) (v_idx_634 Int) (v_idx_635 Int) (v_idx_640 Int)) (exists ((v_v_1388_5 Int) (v_v_1389_5 Int) (v_v_1386_5 Int) (v_v_1398_5 Int) (v_b_168_5 Int) (v_b_167_5 Int) (v_v_1396_5 Int) (v_b_166_5 Int) (v_v_1394_5 Int) (v_v_1392_5 Int) (v_v_1390_5 Int) (v_b_169_5 Int) (v_b_170_5 Int) (v_b_171_5 Int) (v_b_172_5 Int) (v_b_173_5 Int) (v_b_174_5 Int) (v_b_175_5 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 3)) (.cse5 (+ v_b_167_5 3)) (.cse2 (+ v_b_170_5 2)) (.cse16 (+ v_b_169_5 1)) (.cse11 (+ v_b_168_5 2)) (.cse0 (+ v_b_167_5 2)) (.cse7 (+ v_b_171_5 1)) (.cse4 (+ v_b_169_5 2)) (.cse15 (+ v_b_166_5 2)) (.cse9 (+ v_b_166_5 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 2)) (.cse10 (+ v_b_168_5 1)) (.cse18 (+ v_b_168_5 3)) (.cse17 (+ v_b_170_5 1)) (.cse1 (+ v_b_174_5 1)) (.cse21 (+ c_ULTIMATE.start_main_p1 4)) (.cse13 (+ v_b_172_5 1)) (.cse20 (+ c_ULTIMATE.start_main_p1 5)) (.cse19 (+ v_b_166_5 3)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse12 (+ v_b_166_5 4)) (.cse14 (+ v_b_167_5 1))) (and (<= (* 2 v_v_1389_5) 0) (<= .cse0 v_b_171_5) (<= (+ v_b_169_5 3) v_b_175_5) (<= .cse1 v_b_175_5) (or (<= v_b_169_5 v_idx_633) (< v_idx_633 v_b_168_5) (= 0 (select |c_#memory_int| v_idx_633))) (<= .cse2 v_b_173_5) (<= .cse3 v_b_170_5) (<= .cse4 v_b_173_5) (<= .cse5 v_b_173_5) (<= .cse6 v_b_167_5) (<= .cse7 v_b_173_5) (<= .cse3 v_b_169_5) (<= .cse5 v_b_174_5) (or (= (select |c_#memory_int| v_idx_629) 0) (<= .cse8 v_idx_629) (< v_idx_629 c_ULTIMATE.start_main_p1)) (<= .cse9 v_b_168_5) (<= (+ v_b_166_5 5) v_b_175_5) (<= v_b_173_5 v_b_174_5) (<= .cse10 v_b_169_5) (or (< v_idx_632 v_b_167_5) (<= v_b_168_5 v_idx_632) (= (select |c_#memory_int| v_idx_632) v_v_1390_5)) (<= (+ v_b_170_5 3) v_b_175_5) (<= .cse11 v_b_172_5) (<= .cse12 v_b_173_5) (<= .cse13 v_b_174_5) (<= .cse14 v_b_170_5) (<= .cse15 v_b_170_5) (or (<= v_b_171_5 v_idx_635) (= (select |c_#memory_int| v_idx_635) 0) (< v_idx_635 v_b_170_5)) (<= .cse2 v_b_174_5) (<= .cse16 v_b_172_5) (<= .cse16 v_b_171_5) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_5) (<= .cse11 v_b_171_5) (<= .cse0 v_b_172_5) (<= .cse8 v_b_166_5) (<= .cse9 v_b_167_5) (<= .cse17 v_b_171_5) (<= (+ v_b_168_5 4) v_b_175_5) (<= v_v_1389_5 0) (<= .cse7 v_b_174_5) (<= v_b_171_5 v_b_172_5) (<= .cse13 v_b_173_5) (<= .cse4 v_b_174_5) (<= .cse15 v_b_169_5) (<= .cse17 v_b_172_5) (<= (+ v_b_171_5 2) v_b_175_5) (<= .cse10 v_b_170_5) (<= .cse18 v_b_174_5) (<= .cse19 v_b_172_5) (<= v_b_167_5 .cse9) (<= .cse6 v_b_168_5) (<= .cse20 v_b_173_5) (<= .cse21 v_b_172_5) (or (<= c_ULTIMATE.start_main_p1 v_idx_628) (= (select |c_#memory_int| v_idx_628) v_v_1386_5)) (or (< v_idx_636 v_b_171_5) (= (select |c_#memory_int| v_idx_636) v_v_1394_5) (<= v_b_172_5 v_idx_636)) (or (<= v_b_167_5 v_idx_631) (< v_idx_631 v_b_166_5) (= (select |c_#memory_int| v_idx_631) v_v_1389_5)) (or (<= v_b_175_5 v_idx_639) (= 0 (select |c_#memory_int| v_idx_639)) (< v_idx_639 v_b_174_5)) (<= v_b_169_5 .cse10) (<= v_b_169_5 v_b_170_5) (or (= (select |c_#memory_int| v_idx_640) v_v_1398_5) (< v_idx_640 v_b_175_5)) (<= .cse18 v_b_173_5) (or (<= v_b_174_5 v_idx_638) (= (select |c_#memory_int| v_idx_638) v_v_1396_5) (< v_idx_638 v_b_173_5)) (or (= (select |c_#memory_int| v_idx_634) v_v_1392_5) (< v_idx_634 v_b_169_5) (<= v_b_170_5 v_idx_634)) (<= (+ v_b_167_5 4) v_b_175_5) (<= (+ v_b_172_5 2) v_b_175_5) (<= v_b_171_5 .cse17) (<= (+ v_b_173_5 1) v_b_175_5) (<= v_b_175_5 .cse1) (<= .cse21 v_b_171_5) (<= v_b_173_5 .cse13) (or (= 0 (select |c_#memory_int| v_idx_637)) (< v_idx_637 v_b_172_5) (<= v_b_173_5 v_idx_637)) (<= .cse20 v_b_174_5) (<= .cse19 v_b_171_5) (<= v_b_167_5 v_b_168_5) (or (< v_idx_630 .cse8) (= (select |c_#memory_int| v_idx_630) v_v_1388_5) (<= v_b_166_5 v_idx_630)) (<= .cse12 v_b_174_5) (<= .cse14 v_b_169_5))))) is different from false [2019-01-11 11:47:58,385 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:47:58,386 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:47:58,386 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:47:58,386 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:47:58,386 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:47:58,386 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:47:58,386 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:47:58,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:47:58,387 INFO L87 Difference]: Start difference. First operand 15 states and 32 transitions. Second operand 4 states. [2019-01-11 11:48:00,921 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_629 Int) (v_idx_638 Int) (v_idx_628 Int) (v_idx_639 Int) (v_idx_632 Int) (v_idx_633 Int) (v_idx_630 Int) (v_idx_631 Int) (v_idx_636 Int) (v_idx_637 Int) (v_idx_634 Int) (v_idx_635 Int) (v_idx_640 Int)) (exists ((v_v_1388_5 Int) (v_v_1389_5 Int) (v_v_1386_5 Int) (v_v_1398_5 Int) (v_b_168_5 Int) (v_b_167_5 Int) (v_v_1396_5 Int) (v_b_166_5 Int) (v_v_1394_5 Int) (v_v_1392_5 Int) (v_v_1390_5 Int) (v_b_169_5 Int) (v_b_170_5 Int) (v_b_171_5 Int) (v_b_172_5 Int) (v_b_173_5 Int) (v_b_174_5 Int) (v_b_175_5 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 3)) (.cse5 (+ v_b_167_5 3)) (.cse2 (+ v_b_170_5 2)) (.cse16 (+ v_b_169_5 1)) (.cse11 (+ v_b_168_5 2)) (.cse0 (+ v_b_167_5 2)) (.cse7 (+ v_b_171_5 1)) (.cse4 (+ v_b_169_5 2)) (.cse15 (+ v_b_166_5 2)) (.cse9 (+ v_b_166_5 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 2)) (.cse10 (+ v_b_168_5 1)) (.cse18 (+ v_b_168_5 3)) (.cse17 (+ v_b_170_5 1)) (.cse1 (+ v_b_174_5 1)) (.cse21 (+ c_ULTIMATE.start_main_p1 4)) (.cse13 (+ v_b_172_5 1)) (.cse20 (+ c_ULTIMATE.start_main_p1 5)) (.cse19 (+ v_b_166_5 3)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse12 (+ v_b_166_5 4)) (.cse14 (+ v_b_167_5 1))) (and (<= (* 2 v_v_1389_5) 0) (<= .cse0 v_b_171_5) (<= (+ v_b_169_5 3) v_b_175_5) (<= .cse1 v_b_175_5) (or (<= v_b_169_5 v_idx_633) (< v_idx_633 v_b_168_5) (= 0 (select |c_#memory_int| v_idx_633))) (<= .cse2 v_b_173_5) (<= .cse3 v_b_170_5) (<= .cse4 v_b_173_5) (<= .cse5 v_b_173_5) (<= .cse6 v_b_167_5) (<= .cse7 v_b_173_5) (<= .cse3 v_b_169_5) (<= .cse5 v_b_174_5) (or (= (select |c_#memory_int| v_idx_629) 0) (<= .cse8 v_idx_629) (< v_idx_629 c_ULTIMATE.start_main_p1)) (<= .cse9 v_b_168_5) (<= (+ v_b_166_5 5) v_b_175_5) (<= v_b_173_5 v_b_174_5) (<= .cse10 v_b_169_5) (or (< v_idx_632 v_b_167_5) (<= v_b_168_5 v_idx_632) (= (select |c_#memory_int| v_idx_632) v_v_1390_5)) (<= (+ v_b_170_5 3) v_b_175_5) (<= .cse11 v_b_172_5) (<= .cse12 v_b_173_5) (<= .cse13 v_b_174_5) (<= .cse14 v_b_170_5) (<= .cse15 v_b_170_5) (or (<= v_b_171_5 v_idx_635) (= (select |c_#memory_int| v_idx_635) 0) (< v_idx_635 v_b_170_5)) (<= .cse2 v_b_174_5) (<= .cse16 v_b_172_5) (<= .cse16 v_b_171_5) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_5) (<= .cse11 v_b_171_5) (<= .cse0 v_b_172_5) (<= .cse8 v_b_166_5) (<= .cse9 v_b_167_5) (<= .cse17 v_b_171_5) (<= (+ v_b_168_5 4) v_b_175_5) (<= v_v_1389_5 0) (<= .cse7 v_b_174_5) (<= v_b_171_5 v_b_172_5) (<= .cse13 v_b_173_5) (<= .cse4 v_b_174_5) (<= .cse15 v_b_169_5) (<= .cse17 v_b_172_5) (<= (+ v_b_171_5 2) v_b_175_5) (<= .cse10 v_b_170_5) (<= .cse18 v_b_174_5) (<= .cse19 v_b_172_5) (<= v_b_167_5 .cse9) (<= .cse6 v_b_168_5) (<= .cse20 v_b_173_5) (<= .cse21 v_b_172_5) (or (<= c_ULTIMATE.start_main_p1 v_idx_628) (= (select |c_#memory_int| v_idx_628) v_v_1386_5)) (or (< v_idx_636 v_b_171_5) (= (select |c_#memory_int| v_idx_636) v_v_1394_5) (<= v_b_172_5 v_idx_636)) (or (<= v_b_167_5 v_idx_631) (< v_idx_631 v_b_166_5) (= (select |c_#memory_int| v_idx_631) v_v_1389_5)) (or (<= v_b_175_5 v_idx_639) (= 0 (select |c_#memory_int| v_idx_639)) (< v_idx_639 v_b_174_5)) (<= v_b_169_5 .cse10) (<= v_b_169_5 v_b_170_5) (or (= (select |c_#memory_int| v_idx_640) v_v_1398_5) (< v_idx_640 v_b_175_5)) (<= .cse18 v_b_173_5) (or (<= v_b_174_5 v_idx_638) (= (select |c_#memory_int| v_idx_638) v_v_1396_5) (< v_idx_638 v_b_173_5)) (or (= (select |c_#memory_int| v_idx_634) v_v_1392_5) (< v_idx_634 v_b_169_5) (<= v_b_170_5 v_idx_634)) (<= (+ v_b_167_5 4) v_b_175_5) (<= (+ v_b_172_5 2) v_b_175_5) (<= v_b_171_5 .cse17) (<= (+ v_b_173_5 1) v_b_175_5) (<= v_b_175_5 .cse1) (<= .cse21 v_b_171_5) (<= v_b_173_5 .cse13) (or (= 0 (select |c_#memory_int| v_idx_637)) (< v_idx_637 v_b_172_5) (<= v_b_173_5 v_idx_637)) (<= .cse20 v_b_174_5) (<= .cse19 v_b_171_5) (<= v_b_167_5 v_b_168_5) (or (< v_idx_630 .cse8) (= (select |c_#memory_int| v_idx_630) v_v_1388_5) (<= v_b_166_5 v_idx_630)) (<= .cse12 v_b_174_5) (<= .cse14 v_b_169_5))))) (forall ((v_idx_618 Int) (v_idx_619 Int) (v_idx_627 Int) (v_idx_616 Int) (v_idx_617 Int) (v_idx_621 Int) (v_idx_622 Int) (v_idx_620 Int) (v_idx_625 Int) (v_idx_626 Int) (v_idx_615 Int) (v_idx_623 Int) (v_idx_624 Int)) (exists ((v_v_1388_5 Int) (v_v_1389_5 Int) (v_v_1386_5 Int) (v_v_1398_5 Int) (v_b_168_5 Int) (v_v_1396_5 Int) (v_v_1394_5 Int) (v_v_1392_5 Int) (v_v_1390_5 Int) (v_b_169_5 Int) (v_b_170_5 Int) (v_b_171_5 Int) (v_b_172_5 Int) (v_b_173_5 Int) (v_b_174_5 Int) (v_b_175_5 Int)) (let ((.cse25 (+ c_ULTIMATE.start_main_p1 3)) (.cse29 (+ c_ULTIMATE.start_main_p2 4)) (.cse24 (+ v_b_170_5 2)) (.cse34 (+ v_b_169_5 1)) (.cse31 (+ v_b_168_5 2)) (.cse33 (+ c_ULTIMATE.start_main_p2 3)) (.cse28 (+ v_b_171_5 1)) (.cse26 (+ v_b_169_5 2)) (.cse22 (+ c_ULTIMATE.start_main_p2 1)) (.cse27 (+ c_ULTIMATE.start_main_p2 2)) (.cse30 (+ v_b_168_5 1)) (.cse36 (+ v_b_168_5 3)) (.cse35 (+ v_b_170_5 1)) (.cse23 (+ v_b_174_5 1)) (.cse38 (+ c_ULTIMATE.start_main_p1 4)) (.cse32 (+ v_b_172_5 1)) (.cse39 (+ c_ULTIMATE.start_main_p1 1)) (.cse37 (+ c_ULTIMATE.start_main_p1 5))) (and (<= (* 2 v_v_1389_5) 0) (or (< v_idx_620 v_b_168_5) (<= v_b_169_5 v_idx_620) (= (select |c_#memory_int| v_idx_620) 0)) (or (= (select |c_#memory_int| v_idx_619) v_v_1390_5) (< v_idx_619 .cse22) (<= v_b_168_5 v_idx_619)) (<= (+ v_b_169_5 3) v_b_175_5) (<= .cse23 v_b_175_5) (<= .cse24 v_b_173_5) (<= .cse25 v_b_170_5) (<= .cse26 v_b_173_5) (<= .cse27 v_b_169_5) (or (< v_idx_627 v_b_175_5) (= (select |c_#memory_int| v_idx_627) v_v_1398_5)) (<= .cse28 v_b_173_5) (<= .cse25 v_b_169_5) (<= .cse29 v_b_173_5) (or (< v_idx_621 v_b_169_5) (= (select |c_#memory_int| v_idx_621) v_v_1392_5) (<= v_b_170_5 v_idx_621)) (or (<= v_b_171_5 v_idx_622) (< v_idx_622 v_b_170_5) (= (select |c_#memory_int| v_idx_622) 0)) (<= v_b_173_5 v_b_174_5) (<= .cse30 v_b_169_5) (<= (+ v_b_170_5 3) v_b_175_5) (<= .cse31 v_b_172_5) (<= .cse32 v_b_174_5) (<= .cse29 v_b_174_5) (<= .cse33 v_b_171_5) (<= .cse24 v_b_174_5) (<= .cse34 v_b_172_5) (<= .cse34 v_b_171_5) (or (= (select |c_#memory_int| v_idx_615) v_v_1386_5) (<= c_ULTIMATE.start_main_p1 v_idx_615)) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_175_5) (<= .cse31 v_b_171_5) (or (< v_idx_623 v_b_171_5) (<= v_b_172_5 v_idx_623) (= (select |c_#memory_int| v_idx_623) v_v_1394_5)) (<= .cse33 v_b_172_5) (or (<= v_b_174_5 v_idx_625) (< v_idx_625 v_b_173_5) (= (select |c_#memory_int| v_idx_625) v_v_1396_5)) (<= .cse35 v_b_171_5) (or (= (select |c_#memory_int| v_idx_618) v_v_1389_5) (< v_idx_618 c_ULTIMATE.start_main_p2) (<= .cse22 v_idx_618)) (<= (+ v_b_168_5 4) v_b_175_5) (<= v_v_1389_5 0) (<= .cse28 v_b_174_5) (<= v_b_171_5 v_b_172_5) (<= .cse32 v_b_173_5) (<= (+ c_ULTIMATE.start_main_p2 5) v_b_175_5) (<= .cse26 v_b_174_5) (<= .cse22 v_b_168_5) (<= .cse35 v_b_172_5) (<= (+ v_b_171_5 2) v_b_175_5) (<= .cse30 v_b_170_5) (<= .cse36 v_b_174_5) (<= .cse27 v_b_170_5) (<= (+ c_ULTIMATE.start_main_p1 2) v_b_168_5) (<= .cse37 v_b_173_5) (<= .cse38 v_b_172_5) (<= v_b_169_5 .cse30) (<= v_b_169_5 v_b_170_5) (<= .cse36 v_b_173_5) (or (<= .cse39 v_idx_616) (= (select |c_#memory_int| v_idx_616) 0) (< v_idx_616 c_ULTIMATE.start_main_p1)) (or (= (select |c_#memory_int| v_idx_626) 0) (< v_idx_626 v_b_174_5) (<= v_b_175_5 v_idx_626)) (<= (+ v_b_172_5 2) v_b_175_5) (<= v_b_171_5 .cse35) (or (<= v_b_173_5 v_idx_624) (< v_idx_624 v_b_172_5) (= (select |c_#memory_int| v_idx_624) 0)) (<= (+ v_b_173_5 1) v_b_175_5) (<= v_b_175_5 .cse23) (or (< v_idx_617 .cse39) (= (select |c_#memory_int| v_idx_617) v_v_1388_5) (<= c_ULTIMATE.start_main_p2 v_idx_617)) (<= .cse38 v_b_171_5) (<= v_b_173_5 .cse32) (<= .cse39 c_ULTIMATE.start_main_p2) (<= .cse37 v_b_174_5)))))) is different from false [2019-01-11 11:48:22,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:48:22,847 INFO L93 Difference]: Finished difference Result 17 states and 40 transitions. [2019-01-11 11:48:22,847 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:48:22,848 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:48:22,848 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:48:22,848 INFO L225 Difference]: With dead ends: 17 [2019-01-11 11:48:22,848 INFO L226 Difference]: Without dead ends: 16 [2019-01-11 11:48:22,849 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.7s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:48:22,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2019-01-11 11:48:22,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2019-01-11 11:48:22,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2019-01-11 11:48:22,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 32 transitions. [2019-01-11 11:48:22,861 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 32 transitions. Word has length 3 [2019-01-11 11:48:22,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:48:22,861 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 32 transitions. [2019-01-11 11:48:22,861 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:48:22,861 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 32 transitions. [2019-01-11 11:48:22,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:48:22,862 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:48:22,862 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:48:22,862 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:48:22,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:48:22,863 INFO L82 PathProgramCache]: Analyzing trace with hash 30688, now seen corresponding path program 1 times [2019-01-11 11:48:22,863 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:48:22,863 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:48:22,864 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:48:22,864 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:48:22,864 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:48:22,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:48:22,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:48:22,891 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-11 11:48:22,891 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-11 11:48:22,891 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:48:22,892 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-11 11:48:22,892 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-11 11:48:22,892 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:48:22,892 INFO L87 Difference]: Start difference. First operand 15 states and 32 transitions. Second operand 3 states. [2019-01-11 11:48:22,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:48:22,954 INFO L93 Difference]: Finished difference Result 25 states and 41 transitions. [2019-01-11 11:48:22,954 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:48:22,954 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-01-11 11:48:22,954 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:48:22,955 INFO L225 Difference]: With dead ends: 25 [2019-01-11 11:48:22,955 INFO L226 Difference]: Without dead ends: 24 [2019-01-11 11:48:22,956 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:48:22,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2019-01-11 11:48:22,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 16. [2019-01-11 11:48:22,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2019-01-11 11:48:22,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 33 transitions. [2019-01-11 11:48:22,969 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 33 transitions. Word has length 3 [2019-01-11 11:48:22,969 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:48:22,970 INFO L480 AbstractCegarLoop]: Abstraction has 16 states and 33 transitions. [2019-01-11 11:48:22,970 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-11 11:48:22,970 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 33 transitions. [2019-01-11 11:48:22,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:48:22,970 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:48:22,970 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:48:22,971 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:48:22,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:48:22,971 INFO L82 PathProgramCache]: Analyzing trace with hash 30252, now seen corresponding path program 1 times [2019-01-11 11:48:22,971 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:48:22,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:48:22,972 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:48:22,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:48:22,972 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:48:22,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:48:23,028 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:48:23,028 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:48:23,028 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:48:23,028 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:48:23,029 INFO L207 CegarAbsIntRunner]: [0], [14], [27] [2019-01-11 11:48:23,030 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:48:23,030 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:48:31,359 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:48:31,360 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:48:31,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:48:31,360 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:48:31,773 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 75% of their original sizes. [2019-01-11 11:48:31,774 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:48:34,151 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_748 Int) (v_idx_749 Int) (v_idx_753 Int) (v_idx_743 Int) (v_idx_754 Int) (v_idx_751 Int) (v_idx_752 Int) (v_idx_746 Int) (v_idx_747 Int) (v_idx_744 Int) (v_idx_755 Int) (v_idx_745 Int) (v_idx_750 Int)) (exists ((v_b_175_6 Int) (v_v_1412_6 Int) (v_b_176_6 Int) (v_v_1402_6 Int) (v_b_177_6 Int) (v_v_1414_6 Int) (v_b_178_6 Int) (v_b_179_6 Int) (v_v_1410_6 Int) (v_v_1408_6 Int) (v_b_170_6 Int) (v_v_1404_6 Int) (v_b_171_6 Int) (v_v_1406_6 Int) (v_b_174_6 Int) (v_v_1407_6 Int)) (let ((.cse0 (+ v_b_170_6 3)) (.cse2 (+ v_b_176_6 1)) (.cse5 (+ v_b_175_6 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse11 (+ v_b_174_6 1)) (.cse10 (+ v_b_174_6 2)) (.cse12 (+ c_ULTIMATE.start_main_p3 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_171_6 2)) (.cse9 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ v_b_171_6 3)) (.cse14 (+ c_ULTIMATE.start_main_p1 5)) (.cse13 (+ v_b_178_6 1)) (.cse8 (+ v_b_170_6 1)) (.cse15 (+ c_ULTIMATE.start_main_p3 1)) (.cse16 (+ v_b_170_6 4)) (.cse6 (+ c_ULTIMATE.start_main_p3 3))) (and (<= .cse0 v_b_175_6) (<= .cse1 v_b_175_6) (or (<= c_ULTIMATE.start_main_p1 v_idx_743) (= (select |c_#memory_int| v_idx_743) v_v_1402_6)) (<= v_b_177_6 .cse2) (<= (+ c_ULTIMATE.start_main_p3 4) v_b_179_6) (<= .cse3 v_b_175_6) (<= .cse2 v_b_177_6) (<= v_b_175_6 v_b_176_6) (or (<= v_b_170_6 v_idx_745) (< v_idx_745 .cse4) (= (select |c_#memory_int| v_idx_745) v_v_1404_6)) (<= .cse5 v_b_178_6) (<= .cse0 v_b_176_6) (<= .cse6 v_b_177_6) (<= .cse7 v_b_178_6) (<= .cse2 v_b_178_6) (or (<= v_b_177_6 v_idx_752) (= (select |c_#memory_int| v_idx_752) 0) (< v_idx_752 v_b_176_6)) (<= .cse8 v_b_171_6) (<= .cse9 c_ULTIMATE.start_main_p3) (<= (+ v_b_175_6 2) v_b_179_6) (or (= (select |c_#memory_int| v_idx_744) 0) (< v_idx_744 c_ULTIMATE.start_main_p1) (<= .cse4 v_idx_744)) (<= .cse10 v_b_177_6) (<= .cse11 v_b_176_6) (<= .cse5 v_b_177_6) (<= v_b_175_6 .cse11) (or (< v_idx_746 v_b_170_6) (<= v_b_171_6 v_idx_746) (= (select |c_#memory_int| v_idx_746) 0)) (<= .cse3 v_b_176_6) (<= v_b_171_6 .cse8) (<= (+ v_b_176_6 2) v_b_179_6) (<= (+ v_b_171_6 4) v_b_179_6) (or (= (select |c_#memory_int| v_idx_755) v_v_1414_6) (< v_idx_755 v_b_179_6)) (or (<= v_b_176_6 v_idx_751) (= (select |c_#memory_int| v_idx_751) v_v_1410_6) (< v_idx_751 v_b_175_6)) (<= .cse11 v_b_175_6) (<= 0 v_v_1407_6) (or (= (select |c_#memory_int| v_idx_753) v_v_1412_6) (<= v_b_178_6 v_idx_753) (< v_idx_753 v_b_177_6)) (<= .cse12 v_b_175_6) (<= (+ v_b_170_6 5) v_b_179_6) (<= (+ v_b_170_6 2) v_b_174_6) (<= .cse10 v_b_178_6) (<= v_b_177_6 v_b_178_6) (<= .cse13 v_b_179_6) (or (= (select |c_#memory_int| v_idx_750) 0) (<= v_b_175_6 v_idx_750) (< v_idx_750 v_b_174_6)) (<= .cse14 v_b_178_6) (or (<= c_ULTIMATE.start_main_p3 v_idx_747) (< v_idx_747 v_b_171_6) (= (select |c_#memory_int| v_idx_747) v_v_1406_6)) (<= (+ v_b_174_6 3) v_b_179_6) (<= .cse12 v_b_176_6) (<= .cse4 v_b_170_6) (<= .cse15 v_b_174_6) (or (<= .cse15 v_idx_748) (= (select |c_#memory_int| v_idx_748) v_v_1407_6) (< v_idx_748 c_ULTIMATE.start_main_p3)) (<= (+ v_b_177_6 1) v_b_179_6) (or (<= v_b_179_6 v_idx_754) (< v_idx_754 v_b_178_6) (= (select |c_#memory_int| v_idx_754) 0)) (<= .cse1 v_b_176_6) (<= .cse16 v_b_177_6) (<= .cse9 v_b_171_6) (<= .cse7 v_b_177_6) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_174_6) (<= .cse14 v_b_177_6) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_179_6) (<= v_b_179_6 .cse13) (<= (+ v_b_171_6 1) v_b_174_6) (<= .cse8 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_749) v_v_1408_6) (< v_idx_749 .cse15) (<= v_b_174_6 v_idx_749)) (<= .cse16 v_b_178_6) (<= .cse6 v_b_178_6) (<= 0 (* 2 v_v_1407_6)) (<= v_b_171_6 c_ULTIMATE.start_main_p3))))) is different from false [2019-01-11 11:48:36,596 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_759 Int) (v_idx_764 Int) (v_idx_765 Int) (v_idx_762 Int) (v_idx_763 Int) (v_idx_768 Int) (v_idx_757 Int) (v_idx_758 Int) (v_idx_766 Int) (v_idx_767 Int) (v_idx_756 Int) (v_idx_760 Int) (v_idx_761 Int)) (exists ((v_b_175_6 Int) (v_v_1412_6 Int) (v_b_176_6 Int) (v_b_177_6 Int) (v_v_1414_6 Int) (v_v_1402_6 Int) (v_b_178_6 Int) (v_b_179_6 Int) (v_v_1410_6 Int) (v_v_1408_6 Int) (v_b_170_6 Int) (v_b_171_6 Int) (v_v_1404_6 Int) (v_b_172_6 Int) (v_b_173_6 Int) (v_v_1406_6 Int) (v_b_174_6 Int) (v_v_1407_6 Int)) (let ((.cse0 (+ v_b_170_6 3)) (.cse4 (+ v_b_176_6 1)) (.cse1 (+ v_b_172_6 1)) (.cse6 (+ v_b_175_6 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 4)) (.cse10 (+ v_b_174_6 1)) (.cse13 (+ v_b_170_6 2)) (.cse9 (+ v_b_174_6 2)) (.cse11 (+ v_b_172_6 2)) (.cse18 (+ v_b_173_6 2)) (.cse3 (+ v_b_171_6 2)) (.cse20 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ v_b_171_6 3)) (.cse15 (+ c_ULTIMATE.start_main_p1 5)) (.cse12 (+ c_ULTIMATE.start_main_p1 1)) (.cse17 (+ v_b_172_6 3)) (.cse14 (+ v_b_178_6 1)) (.cse21 (+ c_ULTIMATE.start_main_p1 3)) (.cse16 (+ v_b_171_6 1)) (.cse2 (+ v_b_173_6 1)) (.cse8 (+ v_b_170_6 1)) (.cse19 (+ v_b_170_6 4))) (and (<= .cse0 v_b_175_6) (<= .cse1 v_b_174_6) (<= .cse2 v_b_175_6) (<= .cse3 v_b_175_6) (<= v_b_177_6 .cse4) (<= .cse5 v_b_175_6) (<= .cse4 v_b_177_6) (<= v_b_175_6 v_b_176_6) (<= .cse6 v_b_178_6) (<= .cse0 v_b_176_6) (or (< v_idx_764 v_b_175_6) (<= v_b_176_6 v_idx_764) (= (select |c_#memory_int| v_idx_764) v_v_1410_6)) (or (< v_idx_768 v_b_179_6) (= (select |c_#memory_int| v_idx_768) v_v_1414_6)) (<= .cse7 v_b_178_6) (<= v_b_173_6 .cse1) (<= .cse4 v_b_178_6) (or (< v_idx_759 v_b_170_6) (<= v_b_171_6 v_idx_759) (= (select |c_#memory_int| v_idx_759) 0)) (<= .cse8 v_b_171_6) (<= (+ v_b_175_6 2) v_b_179_6) (<= .cse1 v_b_173_6) (<= .cse9 v_b_177_6) (<= .cse10 v_b_176_6) (<= .cse6 v_b_177_6) (<= v_b_175_6 .cse10) (<= .cse5 v_b_176_6) (<= v_b_171_6 v_b_172_6) (<= .cse11 v_b_175_6) (<= v_b_171_6 .cse8) (or (<= v_b_179_6 v_idx_767) (< v_idx_767 v_b_178_6) (= (select |c_#memory_int| v_idx_767) 0)) (<= (+ v_b_176_6 2) v_b_179_6) (or (< v_idx_758 .cse12) (<= v_b_170_6 v_idx_758) (= (select |c_#memory_int| v_idx_758) v_v_1404_6)) (<= (+ v_b_171_6 4) v_b_179_6) (<= .cse10 v_b_175_6) (<= 0 v_v_1407_6) (<= .cse13 v_b_173_6) (or (= (select |c_#memory_int| v_idx_762) v_v_1408_6) (< v_idx_762 v_b_173_6) (<= v_b_174_6 v_idx_762)) (<= (+ v_b_170_6 5) v_b_179_6) (<= .cse13 v_b_174_6) (<= .cse9 v_b_178_6) (<= v_b_177_6 v_b_178_6) (<= .cse14 v_b_179_6) (or (<= c_ULTIMATE.start_main_p1 v_idx_756) (= (select |c_#memory_int| v_idx_756) v_v_1402_6)) (<= .cse15 v_b_178_6) (<= .cse16 v_b_173_6) (<= (+ v_b_174_6 3) v_b_179_6) (or (< v_idx_766 v_b_177_6) (<= v_b_178_6 v_idx_766) (= (select |c_#memory_int| v_idx_766) v_v_1412_6)) (<= (+ v_b_173_6 3) v_b_179_6) (<= .cse17 v_b_177_6) (or (<= v_b_173_6 v_idx_761) (< v_idx_761 v_b_172_6) (= (select |c_#memory_int| v_idx_761) v_v_1407_6)) (<= .cse18 v_b_178_6) (or (= (select |c_#memory_int| v_idx_760) v_v_1406_6) (< v_idx_760 v_b_171_6) (<= v_b_172_6 v_idx_760)) (<= .cse12 v_b_170_6) (<= .cse11 v_b_176_6) (<= .cse18 v_b_177_6) (<= (+ v_b_177_6 1) v_b_179_6) (<= .cse3 v_b_176_6) (<= .cse19 v_b_177_6) (<= .cse20 v_b_172_6) (<= .cse20 v_b_171_6) (<= .cse7 v_b_177_6) (<= .cse21 v_b_174_6) (<= .cse15 v_b_177_6) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_179_6) (or (<= .cse12 v_idx_757) (< v_idx_757 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_757) 0)) (<= .cse17 v_b_178_6) (<= v_b_179_6 .cse14) (<= .cse21 v_b_173_6) (or (< v_idx_765 v_b_176_6) (= (select |c_#memory_int| v_idx_765) 0) (<= v_b_177_6 v_idx_765)) (<= .cse16 v_b_174_6) (<= .cse2 v_b_176_6) (<= .cse8 v_b_172_6) (<= .cse19 v_b_178_6) (<= (+ v_b_172_6 4) v_b_179_6) (or (< v_idx_763 v_b_174_6) (= (select |c_#memory_int| v_idx_763) 0) (<= v_b_175_6 v_idx_763)) (<= v_b_173_6 v_b_174_6) (<= 0 (* 2 v_v_1407_6)))))) is different from false [2019-01-11 11:48:36,744 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:48:36,745 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:48:36,745 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:48:36,745 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:48:36,745 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:48:36,745 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:48:36,745 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:48:36,746 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:48:36,746 INFO L87 Difference]: Start difference. First operand 16 states and 33 transitions. Second operand 4 states. [2019-01-11 11:48:39,267 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_748 Int) (v_idx_749 Int) (v_idx_753 Int) (v_idx_743 Int) (v_idx_754 Int) (v_idx_751 Int) (v_idx_752 Int) (v_idx_746 Int) (v_idx_747 Int) (v_idx_744 Int) (v_idx_755 Int) (v_idx_745 Int) (v_idx_750 Int)) (exists ((v_b_175_6 Int) (v_v_1412_6 Int) (v_b_176_6 Int) (v_v_1402_6 Int) (v_b_177_6 Int) (v_v_1414_6 Int) (v_b_178_6 Int) (v_b_179_6 Int) (v_v_1410_6 Int) (v_v_1408_6 Int) (v_b_170_6 Int) (v_v_1404_6 Int) (v_b_171_6 Int) (v_v_1406_6 Int) (v_b_174_6 Int) (v_v_1407_6 Int)) (let ((.cse0 (+ v_b_170_6 3)) (.cse2 (+ v_b_176_6 1)) (.cse5 (+ v_b_175_6 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse11 (+ v_b_174_6 1)) (.cse10 (+ v_b_174_6 2)) (.cse12 (+ c_ULTIMATE.start_main_p3 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse1 (+ v_b_171_6 2)) (.cse9 (+ c_ULTIMATE.start_main_p1 2)) (.cse7 (+ v_b_171_6 3)) (.cse14 (+ c_ULTIMATE.start_main_p1 5)) (.cse13 (+ v_b_178_6 1)) (.cse8 (+ v_b_170_6 1)) (.cse15 (+ c_ULTIMATE.start_main_p3 1)) (.cse16 (+ v_b_170_6 4)) (.cse6 (+ c_ULTIMATE.start_main_p3 3))) (and (<= .cse0 v_b_175_6) (<= .cse1 v_b_175_6) (or (<= c_ULTIMATE.start_main_p1 v_idx_743) (= (select |c_#memory_int| v_idx_743) v_v_1402_6)) (<= v_b_177_6 .cse2) (<= (+ c_ULTIMATE.start_main_p3 4) v_b_179_6) (<= .cse3 v_b_175_6) (<= .cse2 v_b_177_6) (<= v_b_175_6 v_b_176_6) (or (<= v_b_170_6 v_idx_745) (< v_idx_745 .cse4) (= (select |c_#memory_int| v_idx_745) v_v_1404_6)) (<= .cse5 v_b_178_6) (<= .cse0 v_b_176_6) (<= .cse6 v_b_177_6) (<= .cse7 v_b_178_6) (<= .cse2 v_b_178_6) (or (<= v_b_177_6 v_idx_752) (= (select |c_#memory_int| v_idx_752) 0) (< v_idx_752 v_b_176_6)) (<= .cse8 v_b_171_6) (<= .cse9 c_ULTIMATE.start_main_p3) (<= (+ v_b_175_6 2) v_b_179_6) (or (= (select |c_#memory_int| v_idx_744) 0) (< v_idx_744 c_ULTIMATE.start_main_p1) (<= .cse4 v_idx_744)) (<= .cse10 v_b_177_6) (<= .cse11 v_b_176_6) (<= .cse5 v_b_177_6) (<= v_b_175_6 .cse11) (or (< v_idx_746 v_b_170_6) (<= v_b_171_6 v_idx_746) (= (select |c_#memory_int| v_idx_746) 0)) (<= .cse3 v_b_176_6) (<= v_b_171_6 .cse8) (<= (+ v_b_176_6 2) v_b_179_6) (<= (+ v_b_171_6 4) v_b_179_6) (or (= (select |c_#memory_int| v_idx_755) v_v_1414_6) (< v_idx_755 v_b_179_6)) (or (<= v_b_176_6 v_idx_751) (= (select |c_#memory_int| v_idx_751) v_v_1410_6) (< v_idx_751 v_b_175_6)) (<= .cse11 v_b_175_6) (<= 0 v_v_1407_6) (or (= (select |c_#memory_int| v_idx_753) v_v_1412_6) (<= v_b_178_6 v_idx_753) (< v_idx_753 v_b_177_6)) (<= .cse12 v_b_175_6) (<= (+ v_b_170_6 5) v_b_179_6) (<= (+ v_b_170_6 2) v_b_174_6) (<= .cse10 v_b_178_6) (<= v_b_177_6 v_b_178_6) (<= .cse13 v_b_179_6) (or (= (select |c_#memory_int| v_idx_750) 0) (<= v_b_175_6 v_idx_750) (< v_idx_750 v_b_174_6)) (<= .cse14 v_b_178_6) (or (<= c_ULTIMATE.start_main_p3 v_idx_747) (< v_idx_747 v_b_171_6) (= (select |c_#memory_int| v_idx_747) v_v_1406_6)) (<= (+ v_b_174_6 3) v_b_179_6) (<= .cse12 v_b_176_6) (<= .cse4 v_b_170_6) (<= .cse15 v_b_174_6) (or (<= .cse15 v_idx_748) (= (select |c_#memory_int| v_idx_748) v_v_1407_6) (< v_idx_748 c_ULTIMATE.start_main_p3)) (<= (+ v_b_177_6 1) v_b_179_6) (or (<= v_b_179_6 v_idx_754) (< v_idx_754 v_b_178_6) (= (select |c_#memory_int| v_idx_754) 0)) (<= .cse1 v_b_176_6) (<= .cse16 v_b_177_6) (<= .cse9 v_b_171_6) (<= .cse7 v_b_177_6) (<= (+ c_ULTIMATE.start_main_p1 3) v_b_174_6) (<= .cse14 v_b_177_6) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_179_6) (<= v_b_179_6 .cse13) (<= (+ v_b_171_6 1) v_b_174_6) (<= .cse8 c_ULTIMATE.start_main_p3) (or (= (select |c_#memory_int| v_idx_749) v_v_1408_6) (< v_idx_749 .cse15) (<= v_b_174_6 v_idx_749)) (<= .cse16 v_b_178_6) (<= .cse6 v_b_178_6) (<= 0 (* 2 v_v_1407_6)) (<= v_b_171_6 c_ULTIMATE.start_main_p3))))) (forall ((v_idx_759 Int) (v_idx_764 Int) (v_idx_765 Int) (v_idx_762 Int) (v_idx_763 Int) (v_idx_768 Int) (v_idx_757 Int) (v_idx_758 Int) (v_idx_766 Int) (v_idx_767 Int) (v_idx_756 Int) (v_idx_760 Int) (v_idx_761 Int)) (exists ((v_b_175_6 Int) (v_v_1412_6 Int) (v_b_176_6 Int) (v_b_177_6 Int) (v_v_1414_6 Int) (v_v_1402_6 Int) (v_b_178_6 Int) (v_b_179_6 Int) (v_v_1410_6 Int) (v_v_1408_6 Int) (v_b_170_6 Int) (v_b_171_6 Int) (v_v_1404_6 Int) (v_b_172_6 Int) (v_b_173_6 Int) (v_v_1406_6 Int) (v_b_174_6 Int) (v_v_1407_6 Int)) (let ((.cse17 (+ v_b_170_6 3)) (.cse21 (+ v_b_176_6 1)) (.cse18 (+ v_b_172_6 1)) (.cse23 (+ v_b_175_6 1)) (.cse22 (+ c_ULTIMATE.start_main_p1 4)) (.cse27 (+ v_b_174_6 1)) (.cse30 (+ v_b_170_6 2)) (.cse26 (+ v_b_174_6 2)) (.cse28 (+ v_b_172_6 2)) (.cse35 (+ v_b_173_6 2)) (.cse20 (+ v_b_171_6 2)) (.cse37 (+ c_ULTIMATE.start_main_p1 2)) (.cse24 (+ v_b_171_6 3)) (.cse32 (+ c_ULTIMATE.start_main_p1 5)) (.cse29 (+ c_ULTIMATE.start_main_p1 1)) (.cse34 (+ v_b_172_6 3)) (.cse31 (+ v_b_178_6 1)) (.cse38 (+ c_ULTIMATE.start_main_p1 3)) (.cse33 (+ v_b_171_6 1)) (.cse19 (+ v_b_173_6 1)) (.cse25 (+ v_b_170_6 1)) (.cse36 (+ v_b_170_6 4))) (and (<= .cse17 v_b_175_6) (<= .cse18 v_b_174_6) (<= .cse19 v_b_175_6) (<= .cse20 v_b_175_6) (<= v_b_177_6 .cse21) (<= .cse22 v_b_175_6) (<= .cse21 v_b_177_6) (<= v_b_175_6 v_b_176_6) (<= .cse23 v_b_178_6) (<= .cse17 v_b_176_6) (or (< v_idx_764 v_b_175_6) (<= v_b_176_6 v_idx_764) (= (select |c_#memory_int| v_idx_764) v_v_1410_6)) (or (< v_idx_768 v_b_179_6) (= (select |c_#memory_int| v_idx_768) v_v_1414_6)) (<= .cse24 v_b_178_6) (<= v_b_173_6 .cse18) (<= .cse21 v_b_178_6) (or (< v_idx_759 v_b_170_6) (<= v_b_171_6 v_idx_759) (= (select |c_#memory_int| v_idx_759) 0)) (<= .cse25 v_b_171_6) (<= (+ v_b_175_6 2) v_b_179_6) (<= .cse18 v_b_173_6) (<= .cse26 v_b_177_6) (<= .cse27 v_b_176_6) (<= .cse23 v_b_177_6) (<= v_b_175_6 .cse27) (<= .cse22 v_b_176_6) (<= v_b_171_6 v_b_172_6) (<= .cse28 v_b_175_6) (<= v_b_171_6 .cse25) (or (<= v_b_179_6 v_idx_767) (< v_idx_767 v_b_178_6) (= (select |c_#memory_int| v_idx_767) 0)) (<= (+ v_b_176_6 2) v_b_179_6) (or (< v_idx_758 .cse29) (<= v_b_170_6 v_idx_758) (= (select |c_#memory_int| v_idx_758) v_v_1404_6)) (<= (+ v_b_171_6 4) v_b_179_6) (<= .cse27 v_b_175_6) (<= 0 v_v_1407_6) (<= .cse30 v_b_173_6) (or (= (select |c_#memory_int| v_idx_762) v_v_1408_6) (< v_idx_762 v_b_173_6) (<= v_b_174_6 v_idx_762)) (<= (+ v_b_170_6 5) v_b_179_6) (<= .cse30 v_b_174_6) (<= .cse26 v_b_178_6) (<= v_b_177_6 v_b_178_6) (<= .cse31 v_b_179_6) (or (<= c_ULTIMATE.start_main_p1 v_idx_756) (= (select |c_#memory_int| v_idx_756) v_v_1402_6)) (<= .cse32 v_b_178_6) (<= .cse33 v_b_173_6) (<= (+ v_b_174_6 3) v_b_179_6) (or (< v_idx_766 v_b_177_6) (<= v_b_178_6 v_idx_766) (= (select |c_#memory_int| v_idx_766) v_v_1412_6)) (<= (+ v_b_173_6 3) v_b_179_6) (<= .cse34 v_b_177_6) (or (<= v_b_173_6 v_idx_761) (< v_idx_761 v_b_172_6) (= (select |c_#memory_int| v_idx_761) v_v_1407_6)) (<= .cse35 v_b_178_6) (or (= (select |c_#memory_int| v_idx_760) v_v_1406_6) (< v_idx_760 v_b_171_6) (<= v_b_172_6 v_idx_760)) (<= .cse29 v_b_170_6) (<= .cse28 v_b_176_6) (<= .cse35 v_b_177_6) (<= (+ v_b_177_6 1) v_b_179_6) (<= .cse20 v_b_176_6) (<= .cse36 v_b_177_6) (<= .cse37 v_b_172_6) (<= .cse37 v_b_171_6) (<= .cse24 v_b_177_6) (<= .cse38 v_b_174_6) (<= .cse32 v_b_177_6) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_179_6) (or (<= .cse29 v_idx_757) (< v_idx_757 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_757) 0)) (<= .cse34 v_b_178_6) (<= v_b_179_6 .cse31) (<= .cse38 v_b_173_6) (or (< v_idx_765 v_b_176_6) (= (select |c_#memory_int| v_idx_765) 0) (<= v_b_177_6 v_idx_765)) (<= .cse33 v_b_174_6) (<= .cse19 v_b_176_6) (<= .cse25 v_b_172_6) (<= .cse36 v_b_178_6) (<= (+ v_b_172_6 4) v_b_179_6) (or (< v_idx_763 v_b_174_6) (= (select |c_#memory_int| v_idx_763) 0) (<= v_b_175_6 v_idx_763)) (<= v_b_173_6 v_b_174_6) (<= 0 (* 2 v_v_1407_6))))))) is different from false [2019-01-11 11:49:01,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:49:01,800 INFO L93 Difference]: Finished difference Result 18 states and 41 transitions. [2019-01-11 11:49:01,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:49:01,801 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:49:01,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:49:01,801 INFO L225 Difference]: With dead ends: 18 [2019-01-11 11:49:01,801 INFO L226 Difference]: Without dead ends: 17 [2019-01-11 11:49:01,802 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.3s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:49:01,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2019-01-11 11:49:01,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 16. [2019-01-11 11:49:01,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2019-01-11 11:49:01,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 33 transitions. [2019-01-11 11:49:01,815 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 33 transitions. Word has length 3 [2019-01-11 11:49:01,815 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:49:01,815 INFO L480 AbstractCegarLoop]: Abstraction has 16 states and 33 transitions. [2019-01-11 11:49:01,815 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:49:01,815 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 33 transitions. [2019-01-11 11:49:01,815 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:49:01,815 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:49:01,816 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1] [2019-01-11 11:49:01,816 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:49:01,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:49:01,816 INFO L82 PathProgramCache]: Analyzing trace with hash 941404, now seen corresponding path program 2 times [2019-01-11 11:49:01,816 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:49:01,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:49:01,817 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:49:01,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:49:01,817 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:49:01,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:49:01,877 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2019-01-11 11:49:01,878 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:49:01,878 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:49:01,878 INFO L189 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2019-01-11 11:49:01,880 INFO L422 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2019-01-11 11:49:01,880 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:49:01,880 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2019-01-11 11:49:01,890 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2019-01-11 11:49:01,891 INFO L289 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2019-01-11 11:49:01,902 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2019-01-11 11:49:01,902 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2019-01-11 11:49:01,908 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2019-01-11 11:49:01,991 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2019-01-11 11:49:01,992 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:49:02,032 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 24 [2019-01-11 11:49:02,059 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,060 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 30 [2019-01-11 11:49:02,064 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,067 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,068 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 40 [2019-01-11 11:49:02,084 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,086 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,088 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,089 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 54 [2019-01-11 11:49:02,100 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,102 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,105 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,108 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,109 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 72 [2019-01-11 11:49:02,147 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,170 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,191 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,209 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,211 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,212 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 91 [2019-01-11 11:49:02,213 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2019-01-11 11:49:02,298 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:49:02,345 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:49:02,363 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:49:02,415 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:49:02,441 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2019-01-11 11:49:02,489 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-1 vars, End of recursive call: 4 dim-0 vars, and 1 xjuncts. [2019-01-11 11:49:02,490 INFO L202 ElimStorePlain]: Needed 8 recursive calls to eliminate 6 variables, input treesize:45, output treesize:46 [2019-01-11 11:49:02,514 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,515 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,516 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,517 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,517 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,519 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,520 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,521 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,523 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,524 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,525 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,527 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,528 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,529 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,530 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,545 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,546 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 16 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 91 [2019-01-11 11:49:02,547 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:49:02,617 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-1 vars, End of recursive call: 4 dim-0 vars, and 1 xjuncts. [2019-01-11 11:49:02,618 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 5 variables, input treesize:56, output treesize:46 [2019-01-11 11:49:02,683 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,684 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,689 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,690 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,691 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,692 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,693 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,694 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,695 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,697 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,698 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,700 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,701 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,703 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,704 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,706 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,707 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,708 INFO L701 Elim1Store]: detected not equals via solver [2019-01-11 11:49:02,710 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 18 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 103 [2019-01-11 11:49:02,712 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2019-01-11 11:49:02,800 INFO L267 ElimStorePlain]: Start of recursive call 1: 5 dim-0 vars, 1 dim-1 vars, End of recursive call: 5 dim-0 vars, and 1 xjuncts. [2019-01-11 11:49:02,801 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 6 variables, input treesize:58, output treesize:46 [2019-01-11 11:49:02,949 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:49:02,950 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2019-01-11 11:49:02,970 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:49:02,990 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 3 imperfect interpolant sequences. [2019-01-11 11:49:02,990 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 3, 3] total 8 [2019-01-11 11:49:02,990 INFO L250 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2019-01-11 11:49:02,991 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-01-11 11:49:02,991 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-01-11 11:49:02,991 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=53, Unknown=0, NotChecked=0, Total=90 [2019-01-11 11:49:02,991 INFO L87 Difference]: Start difference. First operand 16 states and 33 transitions. Second operand 7 states. [2019-01-11 11:49:03,401 WARN L181 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 37 DAG size of output: 35 [2019-01-11 11:49:06,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:49:06,414 INFO L93 Difference]: Finished difference Result 57 states and 90 transitions. [2019-01-11 11:49:06,416 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-01-11 11:49:06,416 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 4 [2019-01-11 11:49:06,416 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:49:06,417 INFO L225 Difference]: With dead ends: 57 [2019-01-11 11:49:06,417 INFO L226 Difference]: Without dead ends: 55 [2019-01-11 11:49:06,418 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2019-01-11 11:49:06,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2019-01-11 11:49:06,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 21. [2019-01-11 11:49:06,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2019-01-11 11:49:06,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 52 transitions. [2019-01-11 11:49:06,440 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 52 transitions. Word has length 4 [2019-01-11 11:49:06,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:49:06,440 INFO L480 AbstractCegarLoop]: Abstraction has 21 states and 52 transitions. [2019-01-11 11:49:06,440 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-01-11 11:49:06,440 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 52 transitions. [2019-01-11 11:49:06,440 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2019-01-11 11:49:06,440 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:49:06,440 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2019-01-11 11:49:06,441 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:49:06,441 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:49:06,441 INFO L82 PathProgramCache]: Analyzing trace with hash 941032, now seen corresponding path program 1 times [2019-01-11 11:49:06,441 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:49:06,442 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:49:06,442 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2019-01-11 11:49:06,442 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:49:06,442 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:49:06,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:49:06,513 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:49:06,513 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:49:06,513 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:49:06,513 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 5 with the following transitions: [2019-01-11 11:49:06,514 INFO L207 CegarAbsIntRunner]: [0], [6], [18], [27] [2019-01-11 11:49:06,515 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:49:06,515 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:49:32,544 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:49:32,544 INFO L272 AbstractInterpreter]: Visited 4 different actions 31 times. Merged at 2 different actions 9 times. Widened at 2 different actions 5 times. Found 11 fixpoints after 2 different actions. Largest state had 0 variables. [2019-01-11 11:49:32,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:49:32,544 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:49:33,247 INFO L227 lantSequenceWeakener]: Weakened 3 states. On average, predicates are now at 76.67% of their original sizes. [2019-01-11 11:49:33,248 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:49:35,620 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_926 Int) (v_idx_927 Int) (v_idx_924 Int) (v_idx_925 Int) (v_idx_928 Int) (v_idx_929 Int) (v_idx_930 Int) (v_idx_922 Int) (v_idx_933 Int) (v_idx_923 Int) (v_idx_934 Int) (v_idx_931 Int) (v_idx_932 Int)) (exists ((v_b_463_1 Int) (v_v_5058_1 Int) (v_v_5056_1 Int) (v_v_5046_1 Int) (v_v_5048_1 Int) (v_v_5047_1 Int) (v_v_5054_1 Int) (v_v_5052_1 Int) (v_b_461_1 Int) (v_b_460_1 Int) (v_v_5053_1 Int) (v_b_468_1 Int) (v_v_5050_1 Int) (v_b_469_1 Int) (v_b_462_1 Int) (v_b_466_1 Int) (v_b_467_1 Int)) (let ((.cse9 (+ v_b_460_1 2)) (.cse11 (+ v_b_461_1 1)) (.cse5 (+ c_ULTIMATE.start_main_p4 2)) (.cse6 (+ v_b_460_1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 5)) (.cse14 (+ v_b_460_1 4)) (.cse7 (+ c_ULTIMATE.start_main_p1 3)) (.cse13 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ v_b_462_1 3)) (.cse4 (+ c_ULTIMATE.start_main_p1 1)) (.cse0 (+ c_ULTIMATE.start_main_p4 1)) (.cse10 (+ v_b_466_1 1)) (.cse15 (+ v_b_468_1 1)) (.cse1 (+ v_b_463_1 2)) (.cse12 (+ v_b_462_1 1)) (.cse8 (+ v_b_461_1 3))) (and (<= (+ v_b_461_1 4) v_b_469_1) (<= .cse0 v_b_466_1) (or (= (select |c_#memory_int| v_idx_933) 0) (< v_idx_933 v_b_468_1) (<= v_b_469_1 v_idx_933)) (<= .cse1 v_b_467_1) (<= .cse2 v_b_468_1) (or (<= c_ULTIMATE.start_main_p4 v_idx_928) (= (select |c_#memory_int| v_idx_928) v_v_5052_1) (< v_idx_928 v_b_463_1)) (or (= (select |c_#memory_int| v_idx_925) 0) (< v_idx_925 v_b_460_1) (<= v_b_461_1 v_idx_925)) (<= .cse3 v_b_467_1) (or (< v_idx_927 v_b_462_1) (= 0 (select |c_#memory_int| v_idx_927)) (<= v_b_463_1 v_idx_927)) (or (<= c_ULTIMATE.start_main_p1 v_idx_922) (= (select |c_#memory_int| v_idx_922) v_v_5046_1)) (or (<= .cse4 v_idx_923) (< v_idx_923 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_923) v_v_5047_1)) (<= (+ v_b_462_1 2) v_b_466_1) (<= .cse5 v_b_468_1) (<= (+ v_b_463_1 1) v_b_466_1) (<= .cse6 v_b_461_1) (<= .cse7 v_b_463_1) (<= .cse8 v_b_467_1) (<= 0 v_v_5047_1) (<= v_b_461_1 .cse6) (<= .cse9 v_b_463_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_466_1) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_469_1) (<= v_b_467_1 .cse10) (<= .cse11 v_b_463_1) (<= v_b_463_1 c_ULTIMATE.start_main_p4) (<= .cse9 c_ULTIMATE.start_main_p4) (<= v_b_463_1 .cse12) (or (= (select |c_#memory_int| v_idx_930) v_v_5054_1) (<= v_b_466_1 v_idx_930) (< v_idx_930 .cse0)) (<= .cse4 v_b_460_1) (<= (+ v_b_466_1 2) v_b_469_1) (<= .cse11 c_ULTIMATE.start_main_p4) (<= (+ v_b_462_1 4) v_b_469_1) (<= .cse13 v_b_461_1) (<= .cse14 v_b_467_1) (<= .cse5 v_b_467_1) (or (< v_idx_931 v_b_466_1) (<= v_b_467_1 v_idx_931) (= (select |c_#memory_int| v_idx_931) 0)) (<= v_b_467_1 v_b_468_1) (<= (* 2 v_v_5053_1) 0) (<= .cse6 v_b_462_1) (<= .cse3 v_b_468_1) (<= .cse10 v_b_467_1) (<= (+ v_b_460_1 3) v_b_466_1) (<= v_v_5053_1 0) (<= 0 (* 2 v_v_5047_1)) (<= (+ c_ULTIMATE.start_main_p4 3) v_b_469_1) (<= .cse14 v_b_468_1) (<= .cse7 c_ULTIMATE.start_main_p4) (<= v_v_5053_1 v_v_5047_1) (<= v_b_461_1 v_b_462_1) (<= (+ v_b_467_1 1) v_b_469_1) (or (< v_idx_926 v_b_461_1) (<= v_b_462_1 v_idx_926) (= (select |c_#memory_int| v_idx_926) v_v_5050_1)) (<= .cse13 v_b_462_1) (<= .cse2 v_b_467_1) (or (= (select |c_#memory_int| v_idx_924) v_v_5048_1) (<= v_b_460_1 v_idx_924) (< v_idx_924 .cse4)) (or (= (select |c_#memory_int| v_idx_932) v_v_5056_1) (< v_idx_932 v_b_467_1) (<= v_b_468_1 v_idx_932)) (<= (+ v_b_463_1 3) v_b_469_1) (or (< v_idx_929 c_ULTIMATE.start_main_p4) (<= .cse0 v_idx_929) (= (select |c_#memory_int| v_idx_929) v_v_5053_1)) (<= .cse10 v_b_468_1) (<= v_b_469_1 .cse15) (<= .cse15 v_b_469_1) (<= .cse12 v_b_463_1) (<= .cse1 v_b_468_1) (<= .cse12 c_ULTIMATE.start_main_p4) (or (= (select |c_#memory_int| v_idx_934) v_v_5058_1) (< v_idx_934 v_b_469_1)) (<= (+ v_b_460_1 5) v_b_469_1) (<= .cse8 v_b_468_1) (<= (+ v_b_461_1 2) v_b_466_1))))) is different from false [2019-01-11 11:49:38,080 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_937 Int) (v_idx_938 Int) (v_idx_946 Int) (v_idx_935 Int) (v_idx_947 Int) (v_idx_936 Int) (v_idx_939 Int) (v_idx_940 Int) (v_idx_941 Int) (v_idx_944 Int) (v_idx_945 Int) (v_idx_942 Int) (v_idx_943 Int)) (exists ((v_b_464_1 Int) (v_b_465_1 Int) (v_b_463_1 Int) (v_v_5058_1 Int) (v_v_5056_1 Int) (v_v_5046_1 Int) (v_v_5048_1 Int) (v_v_5047_1 Int) (v_v_5054_1 Int) (v_b_461_1 Int) (v_v_5052_1 Int) (v_b_460_1 Int) (v_v_5053_1 Int) (v_b_468_1 Int) (v_v_5050_1 Int) (v_b_469_1 Int) (v_b_462_1 Int) (v_b_466_1 Int) (v_b_467_1 Int)) (let ((.cse5 (+ v_b_463_1 1)) (.cse11 (+ c_ULTIMATE.start_main_p1 3)) (.cse9 (+ v_b_460_1 2)) (.cse3 (+ v_b_461_1 1)) (.cse12 (+ v_b_464_1 2)) (.cse0 (+ c_ULTIMATE.start_main_p1 1)) (.cse7 (+ v_b_462_1 2)) (.cse10 (+ v_b_460_1 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 5)) (.cse1 (+ v_b_464_1 1)) (.cse19 (+ v_b_460_1 4)) (.cse18 (+ c_ULTIMATE.start_main_p1 2)) (.cse4 (+ v_b_462_1 3)) (.cse15 (+ v_b_466_1 1)) (.cse21 (+ v_b_468_1 1)) (.cse17 (+ v_b_462_1 1)) (.cse2 (+ v_b_463_1 2)) (.cse14 (+ c_ULTIMATE.start_main_p1 4)) (.cse20 (+ v_b_460_1 3)) (.cse16 (+ v_b_465_1 1)) (.cse13 (+ v_b_461_1 3)) (.cse8 (+ v_b_461_1 2))) (and (<= (+ v_b_461_1 4) v_b_469_1) (or (< v_idx_947 v_b_469_1) (= (select |c_#memory_int| v_idx_947) v_v_5058_1)) (or (< v_idx_936 c_ULTIMATE.start_main_p1) (<= .cse0 v_idx_936) (= (select |c_#memory_int| v_idx_936) v_v_5047_1)) (<= .cse1 v_b_465_1) (<= .cse2 v_b_467_1) (or (< v_idx_938 v_b_460_1) (<= v_b_461_1 v_idx_938) (= 0 (select |c_#memory_int| v_idx_938))) (or (= (select |c_#memory_int| v_idx_943) v_v_5054_1) (< v_idx_943 v_b_465_1) (<= v_b_466_1 v_idx_943)) (<= .cse3 v_b_464_1) (or (= (select |c_#memory_int| v_idx_940) 0) (< v_idx_940 v_b_462_1) (<= v_b_463_1 v_idx_940)) (or (<= v_b_460_1 v_idx_937) (= (select |c_#memory_int| v_idx_937) v_v_5048_1) (< v_idx_937 .cse0)) (<= .cse4 v_b_468_1) (<= .cse5 v_b_465_1) (<= .cse6 v_b_467_1) (<= .cse7 v_b_466_1) (<= .cse8 v_b_465_1) (or (<= v_b_464_1 v_idx_941) (= (select |c_#memory_int| v_idx_941) v_v_5052_1) (< v_idx_941 v_b_463_1)) (or (= (select |c_#memory_int| v_idx_945) v_v_5056_1) (< v_idx_945 v_b_467_1) (<= v_b_468_1 v_idx_945)) (<= .cse9 v_b_464_1) (<= .cse5 v_b_466_1) (<= .cse10 v_b_461_1) (<= .cse11 v_b_464_1) (<= .cse11 v_b_463_1) (<= .cse12 v_b_468_1) (or (= 0 (select |c_#memory_int| v_idx_946)) (<= v_b_469_1 v_idx_946) (< v_idx_946 v_b_468_1)) (<= .cse13 v_b_467_1) (<= 0 v_v_5047_1) (<= v_b_461_1 .cse10) (<= .cse9 v_b_463_1) (<= .cse1 v_b_466_1) (<= .cse14 v_b_466_1) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_469_1) (<= v_b_467_1 .cse15) (<= .cse3 v_b_463_1) (or (< v_idx_944 v_b_466_1) (<= v_b_467_1 v_idx_944) (= (select |c_#memory_int| v_idx_944) 0)) (<= .cse12 v_b_467_1) (<= .cse16 v_b_467_1) (<= v_b_463_1 .cse17) (or (< v_idx_942 v_b_464_1) (<= v_b_465_1 v_idx_942) (= (select |c_#memory_int| v_idx_942) v_v_5053_1)) (<= .cse0 v_b_460_1) (<= .cse17 v_b_464_1) (<= v_b_463_1 v_b_464_1) (<= (+ v_b_466_1 2) v_b_469_1) (<= (+ v_b_462_1 4) v_b_469_1) (<= .cse18 v_b_461_1) (<= .cse19 v_b_467_1) (<= v_b_465_1 v_b_466_1) (<= v_b_467_1 v_b_468_1) (<= .cse7 v_b_465_1) (<= (* 2 v_v_5053_1) 0) (<= .cse10 v_b_462_1) (<= .cse6 v_b_468_1) (or (= (select |c_#memory_int| v_idx_939) v_v_5050_1) (< v_idx_939 v_b_461_1) (<= v_b_462_1 v_idx_939)) (<= .cse15 v_b_467_1) (<= .cse20 v_b_466_1) (<= v_v_5053_1 0) (<= 0 (* 2 v_v_5047_1)) (<= v_b_465_1 .cse1) (<= .cse19 v_b_468_1) (<= v_v_5053_1 v_v_5047_1) (<= v_b_461_1 v_b_462_1) (<= (+ v_b_467_1 1) v_b_469_1) (<= (+ v_b_464_1 3) v_b_469_1) (<= .cse18 v_b_462_1) (<= .cse4 v_b_467_1) (<= (+ v_b_463_1 3) v_b_469_1) (<= .cse15 v_b_468_1) (<= v_b_469_1 .cse21) (<= .cse21 v_b_469_1) (<= .cse17 v_b_463_1) (<= .cse2 v_b_468_1) (<= .cse14 v_b_465_1) (<= .cse20 v_b_465_1) (<= (+ v_b_465_1 2) v_b_469_1) (<= .cse16 v_b_468_1) (or (= (select |c_#memory_int| v_idx_935) v_v_5046_1) (<= c_ULTIMATE.start_main_p1 v_idx_935)) (<= (+ v_b_460_1 5) v_b_469_1) (<= .cse13 v_b_468_1) (<= .cse8 v_b_466_1))))) is different from false [2019-01-11 11:49:40,719 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_948 Int) (v_idx_959 Int) (v_idx_949 Int) (v_idx_957 Int) (v_idx_958 Int) (v_idx_951 Int) (v_idx_952 Int) (v_idx_960 Int) (v_idx_950 Int) (v_idx_955 Int) (v_idx_956 Int) (v_idx_953 Int) (v_idx_954 Int)) (exists ((v_b_464_1 Int) (v_b_465_1 Int) (v_b_463_1 Int) (v_v_5058_1 Int) (v_v_5056_1 Int) (v_v_5046_1 Int) (v_v_5048_1 Int) (v_v_5047_1 Int) (v_v_5054_1 Int) (v_b_461_1 Int) (v_v_5052_1 Int) (v_b_460_1 Int) (v_v_5053_1 Int) (v_v_5050_1 Int) (v_b_468_1 Int) (v_b_462_1 Int) (v_b_469_1 Int) (v_b_466_1 Int) (v_b_467_1 Int)) (let ((.cse4 (+ v_b_463_1 1)) (.cse10 (+ c_ULTIMATE.start_main_p1 3)) (.cse8 (+ v_b_460_1 2)) (.cse2 (+ v_b_461_1 1)) (.cse11 (+ v_b_464_1 2)) (.cse17 (+ c_ULTIMATE.start_main_p1 1)) (.cse6 (+ v_b_462_1 2)) (.cse9 (+ v_b_460_1 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 5)) (.cse0 (+ v_b_464_1 1)) (.cse19 (+ v_b_460_1 4)) (.cse18 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ v_b_462_1 3)) (.cse14 (+ v_b_466_1 1)) (.cse21 (+ v_b_468_1 1)) (.cse16 (+ v_b_462_1 1)) (.cse1 (+ v_b_463_1 2)) (.cse13 (+ c_ULTIMATE.start_main_p1 4)) (.cse20 (+ v_b_460_1 3)) (.cse15 (+ v_b_465_1 1)) (.cse12 (+ v_b_461_1 3)) (.cse7 (+ v_b_461_1 2))) (and (or (= (select |c_#memory_int| v_idx_952) v_v_5050_1) (<= v_b_462_1 v_idx_952) (< v_idx_952 v_b_461_1)) (<= (+ v_b_461_1 4) v_b_469_1) (or (<= v_b_463_1 v_idx_953) (< v_idx_953 v_b_462_1) (= (select |c_#memory_int| v_idx_953) 0)) (or (<= v_b_461_1 v_idx_951) (= (select |c_#memory_int| v_idx_951) 0) (< v_idx_951 v_b_460_1)) (<= .cse0 v_b_465_1) (<= .cse1 v_b_467_1) (<= .cse2 v_b_464_1) (<= .cse3 v_b_468_1) (<= .cse4 v_b_465_1) (<= .cse5 v_b_467_1) (<= .cse6 v_b_466_1) (<= .cse7 v_b_465_1) (or (= (select |c_#memory_int| v_idx_954) v_v_5052_1) (<= v_b_464_1 v_idx_954) (< v_idx_954 v_b_463_1)) (<= .cse8 v_b_464_1) (<= .cse4 v_b_466_1) (<= .cse9 v_b_461_1) (<= .cse10 v_b_464_1) (<= .cse10 v_b_463_1) (<= .cse11 v_b_468_1) (<= .cse12 v_b_467_1) (<= 0 v_v_5047_1) (<= v_b_461_1 .cse9) (<= .cse8 v_b_463_1) (<= .cse0 v_b_466_1) (<= .cse13 v_b_466_1) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_469_1) (<= v_b_467_1 .cse14) (<= .cse2 v_b_463_1) (<= .cse11 v_b_467_1) (<= .cse15 v_b_467_1) (<= v_b_463_1 .cse16) (or (<= v_b_460_1 v_idx_950) (= (select |c_#memory_int| v_idx_950) v_v_5048_1) (< v_idx_950 .cse17)) (<= .cse17 v_b_460_1) (or (<= v_b_469_1 v_idx_959) (= 0 (select |c_#memory_int| v_idx_959)) (< v_idx_959 v_b_468_1)) (<= .cse16 v_b_464_1) (<= v_b_463_1 v_b_464_1) (<= (+ v_b_466_1 2) v_b_469_1) (or (< v_idx_949 c_ULTIMATE.start_main_p1) (<= .cse17 v_idx_949) (= (select |c_#memory_int| v_idx_949) v_v_5047_1)) (<= (+ v_b_462_1 4) v_b_469_1) (<= .cse18 v_b_461_1) (<= .cse19 v_b_467_1) (<= v_b_465_1 v_b_466_1) (<= v_b_467_1 v_b_468_1) (<= .cse6 v_b_465_1) (<= (* 2 v_v_5053_1) 0) (<= .cse9 v_b_462_1) (<= .cse5 v_b_468_1) (<= .cse14 v_b_467_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_948) (= (select |c_#memory_int| v_idx_948) v_v_5046_1)) (<= .cse20 v_b_466_1) (<= v_v_5053_1 0) (<= 0 (* 2 v_v_5047_1)) (or (< v_idx_958 v_b_467_1) (= (select |c_#memory_int| v_idx_958) v_v_5056_1) (<= v_b_468_1 v_idx_958)) (<= v_b_465_1 .cse0) (or (<= v_b_466_1 v_idx_956) (= (select |c_#memory_int| v_idx_956) v_v_5054_1) (< v_idx_956 v_b_465_1)) (<= .cse19 v_b_468_1) (<= v_v_5053_1 v_v_5047_1) (<= v_b_461_1 v_b_462_1) (<= (+ v_b_467_1 1) v_b_469_1) (<= (+ v_b_464_1 3) v_b_469_1) (<= .cse18 v_b_462_1) (<= .cse3 v_b_467_1) (<= (+ v_b_463_1 3) v_b_469_1) (<= .cse14 v_b_468_1) (<= v_b_469_1 .cse21) (<= .cse21 v_b_469_1) (<= .cse16 v_b_463_1) (or (< v_idx_955 v_b_464_1) (<= v_b_465_1 v_idx_955) (= (select |c_#memory_int| v_idx_955) v_v_5053_1)) (<= .cse1 v_b_468_1) (<= .cse13 v_b_465_1) (<= .cse20 v_b_465_1) (or (= (select |c_#memory_int| v_idx_957) 0) (<= v_b_467_1 v_idx_957) (< v_idx_957 v_b_466_1)) (<= (+ v_b_465_1 2) v_b_469_1) (or (< v_idx_960 v_b_469_1) (= (select |c_#memory_int| v_idx_960) v_v_5058_1)) (<= .cse15 v_b_468_1) (<= (+ v_b_460_1 5) v_b_469_1) (<= .cse12 v_b_468_1) (<= .cse7 v_b_466_1))))) is different from false [2019-01-11 11:49:40,873 INFO L420 sIntCurrentIteration]: We unified 3 AI predicates to 3 [2019-01-11 11:49:40,874 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:49:40,874 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:49:40,874 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [3] total 6 [2019-01-11 11:49:40,874 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:49:40,874 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-01-11 11:49:40,874 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-01-11 11:49:40,875 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:49:40,875 INFO L87 Difference]: Start difference. First operand 21 states and 52 transitions. Second operand 5 states. [2019-01-11 11:49:43,614 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_948 Int) (v_idx_959 Int) (v_idx_949 Int) (v_idx_957 Int) (v_idx_958 Int) (v_idx_951 Int) (v_idx_952 Int) (v_idx_960 Int) (v_idx_950 Int) (v_idx_955 Int) (v_idx_956 Int) (v_idx_953 Int) (v_idx_954 Int)) (exists ((v_b_464_1 Int) (v_b_465_1 Int) (v_b_463_1 Int) (v_v_5058_1 Int) (v_v_5056_1 Int) (v_v_5046_1 Int) (v_v_5048_1 Int) (v_v_5047_1 Int) (v_v_5054_1 Int) (v_b_461_1 Int) (v_v_5052_1 Int) (v_b_460_1 Int) (v_v_5053_1 Int) (v_v_5050_1 Int) (v_b_468_1 Int) (v_b_462_1 Int) (v_b_469_1 Int) (v_b_466_1 Int) (v_b_467_1 Int)) (let ((.cse4 (+ v_b_463_1 1)) (.cse10 (+ c_ULTIMATE.start_main_p1 3)) (.cse8 (+ v_b_460_1 2)) (.cse2 (+ v_b_461_1 1)) (.cse11 (+ v_b_464_1 2)) (.cse17 (+ c_ULTIMATE.start_main_p1 1)) (.cse6 (+ v_b_462_1 2)) (.cse9 (+ v_b_460_1 1)) (.cse5 (+ c_ULTIMATE.start_main_p1 5)) (.cse0 (+ v_b_464_1 1)) (.cse19 (+ v_b_460_1 4)) (.cse18 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ v_b_462_1 3)) (.cse14 (+ v_b_466_1 1)) (.cse21 (+ v_b_468_1 1)) (.cse16 (+ v_b_462_1 1)) (.cse1 (+ v_b_463_1 2)) (.cse13 (+ c_ULTIMATE.start_main_p1 4)) (.cse20 (+ v_b_460_1 3)) (.cse15 (+ v_b_465_1 1)) (.cse12 (+ v_b_461_1 3)) (.cse7 (+ v_b_461_1 2))) (and (or (= (select |c_#memory_int| v_idx_952) v_v_5050_1) (<= v_b_462_1 v_idx_952) (< v_idx_952 v_b_461_1)) (<= (+ v_b_461_1 4) v_b_469_1) (or (<= v_b_463_1 v_idx_953) (< v_idx_953 v_b_462_1) (= (select |c_#memory_int| v_idx_953) 0)) (or (<= v_b_461_1 v_idx_951) (= (select |c_#memory_int| v_idx_951) 0) (< v_idx_951 v_b_460_1)) (<= .cse0 v_b_465_1) (<= .cse1 v_b_467_1) (<= .cse2 v_b_464_1) (<= .cse3 v_b_468_1) (<= .cse4 v_b_465_1) (<= .cse5 v_b_467_1) (<= .cse6 v_b_466_1) (<= .cse7 v_b_465_1) (or (= (select |c_#memory_int| v_idx_954) v_v_5052_1) (<= v_b_464_1 v_idx_954) (< v_idx_954 v_b_463_1)) (<= .cse8 v_b_464_1) (<= .cse4 v_b_466_1) (<= .cse9 v_b_461_1) (<= .cse10 v_b_464_1) (<= .cse10 v_b_463_1) (<= .cse11 v_b_468_1) (<= .cse12 v_b_467_1) (<= 0 v_v_5047_1) (<= v_b_461_1 .cse9) (<= .cse8 v_b_463_1) (<= .cse0 v_b_466_1) (<= .cse13 v_b_466_1) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_469_1) (<= v_b_467_1 .cse14) (<= .cse2 v_b_463_1) (<= .cse11 v_b_467_1) (<= .cse15 v_b_467_1) (<= v_b_463_1 .cse16) (or (<= v_b_460_1 v_idx_950) (= (select |c_#memory_int| v_idx_950) v_v_5048_1) (< v_idx_950 .cse17)) (<= .cse17 v_b_460_1) (or (<= v_b_469_1 v_idx_959) (= 0 (select |c_#memory_int| v_idx_959)) (< v_idx_959 v_b_468_1)) (<= .cse16 v_b_464_1) (<= v_b_463_1 v_b_464_1) (<= (+ v_b_466_1 2) v_b_469_1) (or (< v_idx_949 c_ULTIMATE.start_main_p1) (<= .cse17 v_idx_949) (= (select |c_#memory_int| v_idx_949) v_v_5047_1)) (<= (+ v_b_462_1 4) v_b_469_1) (<= .cse18 v_b_461_1) (<= .cse19 v_b_467_1) (<= v_b_465_1 v_b_466_1) (<= v_b_467_1 v_b_468_1) (<= .cse6 v_b_465_1) (<= (* 2 v_v_5053_1) 0) (<= .cse9 v_b_462_1) (<= .cse5 v_b_468_1) (<= .cse14 v_b_467_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_948) (= (select |c_#memory_int| v_idx_948) v_v_5046_1)) (<= .cse20 v_b_466_1) (<= v_v_5053_1 0) (<= 0 (* 2 v_v_5047_1)) (or (< v_idx_958 v_b_467_1) (= (select |c_#memory_int| v_idx_958) v_v_5056_1) (<= v_b_468_1 v_idx_958)) (<= v_b_465_1 .cse0) (or (<= v_b_466_1 v_idx_956) (= (select |c_#memory_int| v_idx_956) v_v_5054_1) (< v_idx_956 v_b_465_1)) (<= .cse19 v_b_468_1) (<= v_v_5053_1 v_v_5047_1) (<= v_b_461_1 v_b_462_1) (<= (+ v_b_467_1 1) v_b_469_1) (<= (+ v_b_464_1 3) v_b_469_1) (<= .cse18 v_b_462_1) (<= .cse3 v_b_467_1) (<= (+ v_b_463_1 3) v_b_469_1) (<= .cse14 v_b_468_1) (<= v_b_469_1 .cse21) (<= .cse21 v_b_469_1) (<= .cse16 v_b_463_1) (or (< v_idx_955 v_b_464_1) (<= v_b_465_1 v_idx_955) (= (select |c_#memory_int| v_idx_955) v_v_5053_1)) (<= .cse1 v_b_468_1) (<= .cse13 v_b_465_1) (<= .cse20 v_b_465_1) (or (= (select |c_#memory_int| v_idx_957) 0) (<= v_b_467_1 v_idx_957) (< v_idx_957 v_b_466_1)) (<= (+ v_b_465_1 2) v_b_469_1) (or (< v_idx_960 v_b_469_1) (= (select |c_#memory_int| v_idx_960) v_v_5058_1)) (<= .cse15 v_b_468_1) (<= (+ v_b_460_1 5) v_b_469_1) (<= .cse12 v_b_468_1) (<= .cse7 v_b_466_1))))) (forall ((v_idx_926 Int) (v_idx_927 Int) (v_idx_924 Int) (v_idx_925 Int) (v_idx_928 Int) (v_idx_929 Int) (v_idx_930 Int) (v_idx_922 Int) (v_idx_933 Int) (v_idx_923 Int) (v_idx_934 Int) (v_idx_931 Int) (v_idx_932 Int)) (exists ((v_b_463_1 Int) (v_v_5058_1 Int) (v_v_5056_1 Int) (v_v_5046_1 Int) (v_v_5048_1 Int) (v_v_5047_1 Int) (v_v_5054_1 Int) (v_v_5052_1 Int) (v_b_461_1 Int) (v_b_460_1 Int) (v_v_5053_1 Int) (v_b_468_1 Int) (v_v_5050_1 Int) (v_b_469_1 Int) (v_b_462_1 Int) (v_b_466_1 Int) (v_b_467_1 Int)) (let ((.cse31 (+ v_b_460_1 2)) (.cse33 (+ v_b_461_1 1)) (.cse27 (+ c_ULTIMATE.start_main_p4 2)) (.cse28 (+ v_b_460_1 1)) (.cse25 (+ c_ULTIMATE.start_main_p1 5)) (.cse36 (+ v_b_460_1 4)) (.cse29 (+ c_ULTIMATE.start_main_p1 3)) (.cse35 (+ c_ULTIMATE.start_main_p1 2)) (.cse24 (+ v_b_462_1 3)) (.cse26 (+ c_ULTIMATE.start_main_p1 1)) (.cse22 (+ c_ULTIMATE.start_main_p4 1)) (.cse32 (+ v_b_466_1 1)) (.cse37 (+ v_b_468_1 1)) (.cse23 (+ v_b_463_1 2)) (.cse34 (+ v_b_462_1 1)) (.cse30 (+ v_b_461_1 3))) (and (<= (+ v_b_461_1 4) v_b_469_1) (<= .cse22 v_b_466_1) (or (= (select |c_#memory_int| v_idx_933) 0) (< v_idx_933 v_b_468_1) (<= v_b_469_1 v_idx_933)) (<= .cse23 v_b_467_1) (<= .cse24 v_b_468_1) (or (<= c_ULTIMATE.start_main_p4 v_idx_928) (= (select |c_#memory_int| v_idx_928) v_v_5052_1) (< v_idx_928 v_b_463_1)) (or (= (select |c_#memory_int| v_idx_925) 0) (< v_idx_925 v_b_460_1) (<= v_b_461_1 v_idx_925)) (<= .cse25 v_b_467_1) (or (< v_idx_927 v_b_462_1) (= 0 (select |c_#memory_int| v_idx_927)) (<= v_b_463_1 v_idx_927)) (or (<= c_ULTIMATE.start_main_p1 v_idx_922) (= (select |c_#memory_int| v_idx_922) v_v_5046_1)) (or (<= .cse26 v_idx_923) (< v_idx_923 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_923) v_v_5047_1)) (<= (+ v_b_462_1 2) v_b_466_1) (<= .cse27 v_b_468_1) (<= (+ v_b_463_1 1) v_b_466_1) (<= .cse28 v_b_461_1) (<= .cse29 v_b_463_1) (<= .cse30 v_b_467_1) (<= 0 v_v_5047_1) (<= v_b_461_1 .cse28) (<= .cse31 v_b_463_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_466_1) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_469_1) (<= v_b_467_1 .cse32) (<= .cse33 v_b_463_1) (<= v_b_463_1 c_ULTIMATE.start_main_p4) (<= .cse31 c_ULTIMATE.start_main_p4) (<= v_b_463_1 .cse34) (or (= (select |c_#memory_int| v_idx_930) v_v_5054_1) (<= v_b_466_1 v_idx_930) (< v_idx_930 .cse22)) (<= .cse26 v_b_460_1) (<= (+ v_b_466_1 2) v_b_469_1) (<= .cse33 c_ULTIMATE.start_main_p4) (<= (+ v_b_462_1 4) v_b_469_1) (<= .cse35 v_b_461_1) (<= .cse36 v_b_467_1) (<= .cse27 v_b_467_1) (or (< v_idx_931 v_b_466_1) (<= v_b_467_1 v_idx_931) (= (select |c_#memory_int| v_idx_931) 0)) (<= v_b_467_1 v_b_468_1) (<= (* 2 v_v_5053_1) 0) (<= .cse28 v_b_462_1) (<= .cse25 v_b_468_1) (<= .cse32 v_b_467_1) (<= (+ v_b_460_1 3) v_b_466_1) (<= v_v_5053_1 0) (<= 0 (* 2 v_v_5047_1)) (<= (+ c_ULTIMATE.start_main_p4 3) v_b_469_1) (<= .cse36 v_b_468_1) (<= .cse29 c_ULTIMATE.start_main_p4) (<= v_v_5053_1 v_v_5047_1) (<= v_b_461_1 v_b_462_1) (<= (+ v_b_467_1 1) v_b_469_1) (or (< v_idx_926 v_b_461_1) (<= v_b_462_1 v_idx_926) (= (select |c_#memory_int| v_idx_926) v_v_5050_1)) (<= .cse35 v_b_462_1) (<= .cse24 v_b_467_1) (or (= (select |c_#memory_int| v_idx_924) v_v_5048_1) (<= v_b_460_1 v_idx_924) (< v_idx_924 .cse26)) (or (= (select |c_#memory_int| v_idx_932) v_v_5056_1) (< v_idx_932 v_b_467_1) (<= v_b_468_1 v_idx_932)) (<= (+ v_b_463_1 3) v_b_469_1) (or (< v_idx_929 c_ULTIMATE.start_main_p4) (<= .cse22 v_idx_929) (= (select |c_#memory_int| v_idx_929) v_v_5053_1)) (<= .cse32 v_b_468_1) (<= v_b_469_1 .cse37) (<= .cse37 v_b_469_1) (<= .cse34 v_b_463_1) (<= .cse23 v_b_468_1) (<= .cse34 c_ULTIMATE.start_main_p4) (or (= (select |c_#memory_int| v_idx_934) v_v_5058_1) (< v_idx_934 v_b_469_1)) (<= (+ v_b_460_1 5) v_b_469_1) (<= .cse30 v_b_468_1) (<= (+ v_b_461_1 2) v_b_466_1))))) (forall ((v_idx_937 Int) (v_idx_938 Int) (v_idx_946 Int) (v_idx_935 Int) (v_idx_947 Int) (v_idx_936 Int) (v_idx_939 Int) (v_idx_940 Int) (v_idx_941 Int) (v_idx_944 Int) (v_idx_945 Int) (v_idx_942 Int) (v_idx_943 Int)) (exists ((v_b_464_1 Int) (v_b_465_1 Int) (v_b_463_1 Int) (v_v_5058_1 Int) (v_v_5056_1 Int) (v_v_5046_1 Int) (v_v_5048_1 Int) (v_v_5047_1 Int) (v_v_5054_1 Int) (v_b_461_1 Int) (v_v_5052_1 Int) (v_b_460_1 Int) (v_v_5053_1 Int) (v_b_468_1 Int) (v_v_5050_1 Int) (v_b_469_1 Int) (v_b_462_1 Int) (v_b_466_1 Int) (v_b_467_1 Int)) (let ((.cse43 (+ v_b_463_1 1)) (.cse49 (+ c_ULTIMATE.start_main_p1 3)) (.cse47 (+ v_b_460_1 2)) (.cse41 (+ v_b_461_1 1)) (.cse50 (+ v_b_464_1 2)) (.cse38 (+ c_ULTIMATE.start_main_p1 1)) (.cse45 (+ v_b_462_1 2)) (.cse48 (+ v_b_460_1 1)) (.cse44 (+ c_ULTIMATE.start_main_p1 5)) (.cse39 (+ v_b_464_1 1)) (.cse57 (+ v_b_460_1 4)) (.cse56 (+ c_ULTIMATE.start_main_p1 2)) (.cse42 (+ v_b_462_1 3)) (.cse53 (+ v_b_466_1 1)) (.cse59 (+ v_b_468_1 1)) (.cse55 (+ v_b_462_1 1)) (.cse40 (+ v_b_463_1 2)) (.cse52 (+ c_ULTIMATE.start_main_p1 4)) (.cse58 (+ v_b_460_1 3)) (.cse54 (+ v_b_465_1 1)) (.cse51 (+ v_b_461_1 3)) (.cse46 (+ v_b_461_1 2))) (and (<= (+ v_b_461_1 4) v_b_469_1) (or (< v_idx_947 v_b_469_1) (= (select |c_#memory_int| v_idx_947) v_v_5058_1)) (or (< v_idx_936 c_ULTIMATE.start_main_p1) (<= .cse38 v_idx_936) (= (select |c_#memory_int| v_idx_936) v_v_5047_1)) (<= .cse39 v_b_465_1) (<= .cse40 v_b_467_1) (or (< v_idx_938 v_b_460_1) (<= v_b_461_1 v_idx_938) (= 0 (select |c_#memory_int| v_idx_938))) (or (= (select |c_#memory_int| v_idx_943) v_v_5054_1) (< v_idx_943 v_b_465_1) (<= v_b_466_1 v_idx_943)) (<= .cse41 v_b_464_1) (or (= (select |c_#memory_int| v_idx_940) 0) (< v_idx_940 v_b_462_1) (<= v_b_463_1 v_idx_940)) (or (<= v_b_460_1 v_idx_937) (= (select |c_#memory_int| v_idx_937) v_v_5048_1) (< v_idx_937 .cse38)) (<= .cse42 v_b_468_1) (<= .cse43 v_b_465_1) (<= .cse44 v_b_467_1) (<= .cse45 v_b_466_1) (<= .cse46 v_b_465_1) (or (<= v_b_464_1 v_idx_941) (= (select |c_#memory_int| v_idx_941) v_v_5052_1) (< v_idx_941 v_b_463_1)) (or (= (select |c_#memory_int| v_idx_945) v_v_5056_1) (< v_idx_945 v_b_467_1) (<= v_b_468_1 v_idx_945)) (<= .cse47 v_b_464_1) (<= .cse43 v_b_466_1) (<= .cse48 v_b_461_1) (<= .cse49 v_b_464_1) (<= .cse49 v_b_463_1) (<= .cse50 v_b_468_1) (or (= 0 (select |c_#memory_int| v_idx_946)) (<= v_b_469_1 v_idx_946) (< v_idx_946 v_b_468_1)) (<= .cse51 v_b_467_1) (<= 0 v_v_5047_1) (<= v_b_461_1 .cse48) (<= .cse47 v_b_463_1) (<= .cse39 v_b_466_1) (<= .cse52 v_b_466_1) (<= (+ c_ULTIMATE.start_main_p1 6) v_b_469_1) (<= v_b_467_1 .cse53) (<= .cse41 v_b_463_1) (or (< v_idx_944 v_b_466_1) (<= v_b_467_1 v_idx_944) (= (select |c_#memory_int| v_idx_944) 0)) (<= .cse50 v_b_467_1) (<= .cse54 v_b_467_1) (<= v_b_463_1 .cse55) (or (< v_idx_942 v_b_464_1) (<= v_b_465_1 v_idx_942) (= (select |c_#memory_int| v_idx_942) v_v_5053_1)) (<= .cse38 v_b_460_1) (<= .cse55 v_b_464_1) (<= v_b_463_1 v_b_464_1) (<= (+ v_b_466_1 2) v_b_469_1) (<= (+ v_b_462_1 4) v_b_469_1) (<= .cse56 v_b_461_1) (<= .cse57 v_b_467_1) (<= v_b_465_1 v_b_466_1) (<= v_b_467_1 v_b_468_1) (<= .cse45 v_b_465_1) (<= (* 2 v_v_5053_1) 0) (<= .cse48 v_b_462_1) (<= .cse44 v_b_468_1) (or (= (select |c_#memory_int| v_idx_939) v_v_5050_1) (< v_idx_939 v_b_461_1) (<= v_b_462_1 v_idx_939)) (<= .cse53 v_b_467_1) (<= .cse58 v_b_466_1) (<= v_v_5053_1 0) (<= 0 (* 2 v_v_5047_1)) (<= v_b_465_1 .cse39) (<= .cse57 v_b_468_1) (<= v_v_5053_1 v_v_5047_1) (<= v_b_461_1 v_b_462_1) (<= (+ v_b_467_1 1) v_b_469_1) (<= (+ v_b_464_1 3) v_b_469_1) (<= .cse56 v_b_462_1) (<= .cse42 v_b_467_1) (<= (+ v_b_463_1 3) v_b_469_1) (<= .cse53 v_b_468_1) (<= v_b_469_1 .cse59) (<= .cse59 v_b_469_1) (<= .cse55 v_b_463_1) (<= .cse40 v_b_468_1) (<= .cse52 v_b_465_1) (<= .cse58 v_b_465_1) (<= (+ v_b_465_1 2) v_b_469_1) (<= .cse54 v_b_468_1) (or (= (select |c_#memory_int| v_idx_935) v_v_5046_1) (<= c_ULTIMATE.start_main_p1 v_idx_935)) (<= (+ v_b_460_1 5) v_b_469_1) (<= .cse51 v_b_468_1) (<= .cse46 v_b_466_1)))))) is different from false [2019-01-11 11:49:43,778 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:49:43,779 FATAL L265 ToolchainWalker]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: line 9040 column 7: Overflow encountered when expanding vector at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser$Action$.CUP$do_action(Parser.java:1420) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser.do_action(Parser.java:630) at com.github.jhoenicke.javacup.runtime.LRParser.parse(LRParser.java:419) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:205) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parseSuccess(Executor.java:221) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Scriptor.push(Scriptor.java:133) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.arrays.DiffWrapperScript.push(DiffWrapperScript.java:93) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.managedscript.ManagedScript.push(ManagedScript.java:126) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.hoaretriple.IncrementalHoareTripleChecker.assertPostcondInternal(IncrementalHoareTripleChecker.java:525) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.hoaretriple.IncrementalHoareTripleChecker.assertPostcond(IncrementalHoareTripleChecker.java:244) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.hoaretriple.IncrementalHoareTripleChecker.prepareAssertionStackAndAddPostcond(IncrementalHoareTripleChecker.java:236) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.hoaretriple.IncrementalHoareTripleChecker.checkInternal(IncrementalHoareTripleChecker.java:127) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.AbsIntHoareTripleChecker.checkInternal(AbsIntHoareTripleChecker.java:186) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.CachingHoareTripleChecker.checkInternal(CachingHoareTripleChecker.java:98) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.AbstractInterpolantAutomaton$InternalSuccessorComputationHelper.computeSuccWithSolver(AbstractInterpolantAutomaton.java:359) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.BasicAbstractInterpolantAutomaton.chooseFalseSuccessor2(BasicAbstractInterpolantAutomaton.java:106) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.BasicAbstractInterpolantAutomaton.computeSuccs(BasicAbstractInterpolantAutomaton.java:72) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.BasicAbstractInterpolantAutomaton.computeSuccs(BasicAbstractInterpolantAutomaton.java:1) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.AbstractInterpolantAutomaton.internalSuccessors(AbstractInterpolantAutomaton.java:234) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.AbstractInterpolantAutomaton.internalSuccessors(AbstractInterpolantAutomaton.java:1) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.TotalizeNwa.internalSuccessors(TotalizeNwa.java:213) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ComplementDeterministicNwa.internalSuccessors(ComplementDeterministicNwa.java:121) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ProductNwa.internalSuccessors(ProductNwa.java:216) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ProductNwa.internalSuccessors(ProductNwa.java:208) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates$ReachableStatesComputation.addInternalsAndSuccessors(NestedWordAutomatonReachableStates.java:1066) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates$ReachableStatesComputation.(NestedWordAutomatonReachableStates.java:968) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates.(NestedWordAutomatonReachableStates.java:188) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.Difference.computeDifference(Difference.java:137) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.Difference.(Difference.java:90) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.computeAutomataDifference(BasicCegarLoop.java:699) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.refineAbstraction(BasicCegarLoop.java:628) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:472) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:376) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:334) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:174) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:126) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:123) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:316) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) [2019-01-11 11:49:43,782 INFO L168 Benchmark]: Toolchain (without parser) took 309333.87 ms. Allocated memory was 141.6 MB in the beginning and 2.6 GB in the end (delta: 2.5 GB). Free memory was 107.8 MB in the beginning and 241.1 MB in the end (delta: -133.3 MB). Peak memory consumption was 2.4 GB. Max. memory is 7.1 GB. [2019-01-11 11:49:43,784 INFO L168 Benchmark]: Boogie PL CUP Parser took 0.19 ms. Allocated memory is still 141.6 MB. Free memory is still 109.1 MB. There was no memory consumed. Max. memory is 7.1 GB. [2019-01-11 11:49:43,784 INFO L168 Benchmark]: Boogie Procedure Inliner took 54.55 ms. Allocated memory is still 141.6 MB. Free memory was 107.6 MB in the beginning and 105.2 MB in the end (delta: 2.3 MB). Peak memory consumption was 2.3 MB. Max. memory is 7.1 GB. [2019-01-11 11:49:43,785 INFO L168 Benchmark]: Boogie Preprocessor took 24.23 ms. Allocated memory is still 141.6 MB. Free memory was 105.2 MB in the beginning and 104.1 MB in the end (delta: 1.1 MB). Peak memory consumption was 1.1 MB. Max. memory is 7.1 GB. [2019-01-11 11:49:43,786 INFO L168 Benchmark]: RCFGBuilder took 392.65 ms. Allocated memory is still 141.6 MB. Free memory was 104.1 MB in the beginning and 92.3 MB in the end (delta: 11.8 MB). Peak memory consumption was 11.8 MB. Max. memory is 7.1 GB. [2019-01-11 11:49:43,786 INFO L168 Benchmark]: TraceAbstraction took 308859.29 ms. Allocated memory was 141.6 MB in the beginning and 2.6 GB in the end (delta: 2.5 GB). Free memory was 92.1 MB in the beginning and 241.1 MB in the end (delta: -149.0 MB). Peak memory consumption was 2.3 GB. Max. memory is 7.1 GB. [2019-01-11 11:49:43,800 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.19 ms. Allocated memory is still 141.6 MB. Free memory is still 109.1 MB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 54.55 ms. Allocated memory is still 141.6 MB. Free memory was 107.6 MB in the beginning and 105.2 MB in the end (delta: 2.3 MB). Peak memory consumption was 2.3 MB. Max. memory is 7.1 GB. * Boogie Preprocessor took 24.23 ms. Allocated memory is still 141.6 MB. Free memory was 105.2 MB in the beginning and 104.1 MB in the end (delta: 1.1 MB). Peak memory consumption was 1.1 MB. Max. memory is 7.1 GB. * RCFGBuilder took 392.65 ms. Allocated memory is still 141.6 MB. Free memory was 104.1 MB in the beginning and 92.3 MB in the end (delta: 11.8 MB). Peak memory consumption was 11.8 MB. Max. memory is 7.1 GB. * TraceAbstraction took 308859.29 ms. Allocated memory was 141.6 MB in the beginning and 2.6 GB in the end (delta: 2.5 GB). Free memory was 92.1 MB in the beginning and 241.1 MB in the end (delta: -149.0 MB). Peak memory consumption was 2.3 GB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: line 9040 column 7: Overflow encountered when expanding vector de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: line 9040 column 7: Overflow encountered when expanding vector: de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser$Action$.CUP$do_action(Parser.java:1420) RESULT: Ultimate could not prove your program: Toolchain returned no result. [MP z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 (1)] Forcibly destroying the process Received shutdown request...