java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml -s ../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf -i ../../../trunk/examples/programs/heapseparator/speedup-poc-dd-7-limited.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.24-df3cc4e-m [2019-01-11 11:44:38,211 INFO L170 SettingsManager]: Resetting all preferences to default values... [2019-01-11 11:44:38,214 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2019-01-11 11:44:38,231 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2019-01-11 11:44:38,276 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf [2019-01-11 11:44:38,288 INFO L110 SettingsManager]: Loading preferences was successful [2019-01-11 11:44:38,288 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2019-01-11 11:44:38,289 INFO L131 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2019-01-11 11:44:38,289 INFO L133 SettingsManager]: * Show backtranslation warnings=false [2019-01-11 11:44:38,289 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-01-11 11:44:38,290 INFO L133 SettingsManager]: * User list type=DISABLED [2019-01-11 11:44:38,290 INFO L133 SettingsManager]: * Inline calls to unimplemented procedures=true [2019-01-11 11:44:38,290 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-01-11 11:44:38,290 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-01-11 11:44:38,290 INFO L133 SettingsManager]: * Underlying domain=OctagonDomain [2019-01-11 11:44:38,291 INFO L133 SettingsManager]: * Abstract domain=ArrayDomain [2019-01-11 11:44:38,291 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-01-11 11:44:38,291 INFO L133 SettingsManager]: * Interval Domain=false [2019-01-11 11:44:38,292 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-01-11 11:44:38,292 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2019-01-11 11:44:38,292 INFO L133 SettingsManager]: * Use SBE=true [2019-01-11 11:44:38,292 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-01-11 11:44:38,293 INFO L133 SettingsManager]: * sizeof long=4 [2019-01-11 11:44:38,293 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2019-01-11 11:44:38,293 INFO L133 SettingsManager]: * sizeof POINTER=4 [2019-01-11 11:44:38,293 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2019-01-11 11:44:38,293 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-01-11 11:44:38,293 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-01-11 11:44:38,294 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-01-11 11:44:38,294 INFO L133 SettingsManager]: * sizeof long double=12 [2019-01-11 11:44:38,294 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2019-01-11 11:44:38,294 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-01-11 11:44:38,294 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-01-11 11:44:38,295 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-01-11 11:44:38,295 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2019-01-11 11:44:38,295 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-11 11:44:38,295 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-01-11 11:44:38,295 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-01-11 11:44:38,296 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-01-11 11:44:38,296 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2019-01-11 11:44:38,296 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-01-11 11:44:38,296 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in [2019-01-11 11:44:38,296 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-01-11 11:44:38,297 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2019-01-11 11:44:38,332 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-01-11 11:44:38,344 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-01-11 11:44:38,347 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-01-11 11:44:38,348 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2019-01-11 11:44:38,348 INFO L276 PluginConnector]: Boogie PL CUP Parser initialized [2019-01-11 11:44:38,349 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-7-limited.bpl [2019-01-11 11:44:38,349 INFO L111 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-7-limited.bpl' [2019-01-11 11:44:38,398 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-01-11 11:44:38,400 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-01-11 11:44:38,400 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-01-11 11:44:38,400 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-01-11 11:44:38,401 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2019-01-11 11:44:38,417 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:38" (1/1) ... [2019-01-11 11:44:38,429 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:38" (1/1) ... [2019-01-11 11:44:38,454 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-01-11 11:44:38,455 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-01-11 11:44:38,455 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-01-11 11:44:38,455 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2019-01-11 11:44:38,466 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:38" (1/1) ... [2019-01-11 11:44:38,466 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:38" (1/1) ... [2019-01-11 11:44:38,469 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:38" (1/1) ... [2019-01-11 11:44:38,469 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:38" (1/1) ... [2019-01-11 11:44:38,473 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:38" (1/1) ... [2019-01-11 11:44:38,477 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:38" (1/1) ... [2019-01-11 11:44:38,478 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:38" (1/1) ... [2019-01-11 11:44:38,480 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-01-11 11:44:38,481 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-01-11 11:44:38,481 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-01-11 11:44:38,481 INFO L276 PluginConnector]: RCFGBuilder initialized [2019-01-11 11:44:38,482 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:38" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-11 11:44:38,552 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-01-11 11:44:38,552 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-01-11 11:44:39,019 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-01-11 11:44:39,019 INFO L286 CfgBuilder]: Removed 17 assue(true) statements. [2019-01-11 11:44:39,020 INFO L202 PluginConnector]: Adding new model speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.01 11:44:39 BoogieIcfgContainer [2019-01-11 11:44:39,020 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-01-11 11:44:39,021 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-01-11 11:44:39,022 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-01-11 11:44:39,025 INFO L276 PluginConnector]: TraceAbstraction initialized [2019-01-11 11:44:39,025 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:44:38" (1/2) ... [2019-01-11 11:44:39,026 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@fe16f41 and model type speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.01 11:44:39, skipping insertion in model container [2019-01-11 11:44:39,026 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-7-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.01 11:44:39" (2/2) ... [2019-01-11 11:44:39,028 INFO L112 eAbstractionObserver]: Analyzing ICFG speedup-poc-dd-7-limited.bpl [2019-01-11 11:44:39,036 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-01-11 11:44:39,042 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 7 error locations. [2019-01-11 11:44:39,054 INFO L257 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2019-01-11 11:44:39,086 INFO L382 AbstractCegarLoop]: Interprodecural is true [2019-01-11 11:44:39,086 INFO L383 AbstractCegarLoop]: Hoare is true [2019-01-11 11:44:39,086 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-01-11 11:44:39,086 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-01-11 11:44:39,087 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-01-11 11:44:39,087 INFO L387 AbstractCegarLoop]: Difference is false [2019-01-11 11:44:39,088 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-01-11 11:44:39,088 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-01-11 11:44:39,101 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states. [2019-01-11 11:44:39,106 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3 [2019-01-11 11:44:39,107 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:44:39,108 INFO L402 BasicCegarLoop]: trace histogram [1, 1] [2019-01-11 11:44:39,111 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:44:39,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:39,117 INFO L82 PathProgramCache]: Analyzing trace with hash 992, now seen corresponding path program 1 times [2019-01-11 11:44:39,120 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:44:39,166 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:39,167 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:44:39,167 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:39,167 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:44:39,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:44:39,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:44:39,324 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-11 11:44:39,324 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-11 11:44:39,325 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:44:39,329 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-11 11:44:39,340 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-11 11:44:39,341 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:44:39,343 INFO L87 Difference]: Start difference. First operand 17 states. Second operand 3 states. [2019-01-11 11:44:39,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:44:39,617 INFO L93 Difference]: Finished difference Result 33 states and 45 transitions. [2019-01-11 11:44:39,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:44:39,619 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 2 [2019-01-11 11:44:39,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:44:39,633 INFO L225 Difference]: With dead ends: 33 [2019-01-11 11:44:39,633 INFO L226 Difference]: Without dead ends: 28 [2019-01-11 11:44:39,637 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:44:39,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2019-01-11 11:44:39,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 16. [2019-01-11 11:44:39,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2019-01-11 11:44:39,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 29 transitions. [2019-01-11 11:44:39,676 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 29 transitions. Word has length 2 [2019-01-11 11:44:39,678 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:44:39,678 INFO L480 AbstractCegarLoop]: Abstraction has 16 states and 29 transitions. [2019-01-11 11:44:39,678 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-11 11:44:39,678 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 29 transitions. [2019-01-11 11:44:39,679 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:44:39,679 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:44:39,679 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:44:39,680 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:44:39,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:39,680 INFO L82 PathProgramCache]: Analyzing trace with hash 30816, now seen corresponding path program 1 times [2019-01-11 11:44:39,680 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:44:39,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:39,682 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:44:39,682 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:39,682 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:44:39,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:44:39,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:44:39,743 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-11 11:44:39,743 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-11 11:44:39,743 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:44:39,745 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-11 11:44:39,746 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-11 11:44:39,746 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:44:39,746 INFO L87 Difference]: Start difference. First operand 16 states and 29 transitions. Second operand 3 states. [2019-01-11 11:44:40,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:44:40,020 INFO L93 Difference]: Finished difference Result 28 states and 40 transitions. [2019-01-11 11:44:40,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:44:40,021 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-01-11 11:44:40,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:44:40,022 INFO L225 Difference]: With dead ends: 28 [2019-01-11 11:44:40,022 INFO L226 Difference]: Without dead ends: 27 [2019-01-11 11:44:40,023 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:44:40,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2019-01-11 11:44:40,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 17. [2019-01-11 11:44:40,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2019-01-11 11:44:40,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 30 transitions. [2019-01-11 11:44:40,028 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 30 transitions. Word has length 3 [2019-01-11 11:44:40,028 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:44:40,029 INFO L480 AbstractCegarLoop]: Abstraction has 17 states and 30 transitions. [2019-01-11 11:44:40,029 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-11 11:44:40,029 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 30 transitions. [2019-01-11 11:44:40,029 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:44:40,029 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:44:40,030 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:44:40,030 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:44:40,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:40,031 INFO L82 PathProgramCache]: Analyzing trace with hash 30380, now seen corresponding path program 1 times [2019-01-11 11:44:40,031 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:44:40,032 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:40,032 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:44:40,032 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:44:40,032 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:44:40,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:44:40,191 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:44:40,191 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:44:40,192 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:44:40,192 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:44:40,194 INFO L207 CegarAbsIntRunner]: [0], [18], [31] [2019-01-11 11:44:40,242 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:44:40,242 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:44:57,185 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:44:57,187 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:44:57,191 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:44:57,191 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:44:58,047 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 77.27% of their original sizes. [2019-01-11 11:44:58,047 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:45:00,715 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_126 Int) (v_idx_115 Int) (v_idx_127 Int) (v_idx_116 Int) (v_idx_124 Int) (v_idx_125 Int) (v_idx_119 Int) (v_idx_128 Int) (v_idx_117 Int) (v_idx_129 Int) (v_idx_118 Int) (v_idx_122 Int) (v_idx_123 Int) (v_idx_120 Int) (v_idx_121 Int)) (exists ((v_b_195_1 Int) (v_b_194_1 Int) (v_b_184_1 Int) (v_v_1753_1 Int) (v_b_185_1 Int) (v_v_1755_1 Int) (v_b_186_1 Int) (v_v_1745_1 Int) (v_b_187_1 Int) (v_v_1747_1 Int) (v_v_1757_1 Int) (v_v_1749_1 Int) (v_v_1759_1 Int) (v_b_191_1 Int) (v_b_190_1 Int) (v_b_193_1 Int) (v_v_1752_1 Int) (v_b_192_1 Int) (v_v_1751_1 Int)) (let ((.cse15 (+ v_b_184_1 4)) (.cse5 (+ c_ULTIMATE.start_main_p4 2)) (.cse13 (+ v_b_184_1 2)) (.cse9 (+ c_ULTIMATE.start_main_p1 6)) (.cse11 (+ v_b_186_1 4)) (.cse0 (+ v_b_184_1 5)) (.cse2 (+ c_ULTIMATE.start_main_p4 1)) (.cse10 (+ v_b_185_1 1)) (.cse4 (+ v_b_190_1 2)) (.cse3 (+ v_b_192_1 1)) (.cse20 (+ v_b_187_1 2)) (.cse14 (+ c_ULTIMATE.start_main_p1 3)) (.cse17 (+ v_b_185_1 4)) (.cse19 (+ c_ULTIMATE.start_main_p1 2)) (.cse22 (+ v_b_191_1 1)) (.cse16 (+ v_b_187_1 3)) (.cse18 (+ v_b_185_1 3)) (.cse1 (+ v_b_190_1 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 1)) (.cse24 (+ c_ULTIMATE.start_main_p4 3)) (.cse21 (+ v_b_186_1 3)) (.cse8 (+ v_b_184_1 1)) (.cse23 (+ v_b_194_1 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 5)) (.cse12 (+ v_b_186_1 1))) (and (<= (* 2 v_v_1752_1) 0) (<= .cse0 v_b_193_1) (or (= (select |c_#memory_int| v_idx_127) v_v_1757_1) (< v_idx_127 v_b_193_1) (<= v_b_194_1 v_idx_127)) (<= (+ v_b_184_1 6) v_b_195_1) (<= .cse1 v_b_192_1) (or (<= v_b_192_1 v_idx_125) (= (select |c_#memory_int| v_idx_125) v_v_1755_1) (< v_idx_125 v_b_191_1)) (<= (+ v_b_191_1 2) v_b_195_1) (or (< v_idx_123 .cse2) (<= v_b_190_1 v_idx_123) (= (select |c_#memory_int| v_idx_123) v_v_1753_1)) (<= (+ v_b_185_1 5) v_b_195_1) (<= v_b_187_1 c_ULTIMATE.start_main_p4) (or (<= v_b_185_1 v_idx_118) (< v_idx_118 v_b_184_1) (= (select |c_#memory_int| v_idx_118) 0)) (<= v_b_193_1 .cse3) (<= (+ v_b_186_1 2) v_b_190_1) (<= v_b_193_1 v_b_194_1) (<= (+ v_b_184_1 3) v_b_190_1) (<= .cse4 v_b_193_1) (<= .cse5 v_b_191_1) (or (= (select |c_#memory_int| v_idx_116) 0) (< v_idx_116 c_ULTIMATE.start_main_p1) (<= .cse6 v_idx_116)) (or (< v_idx_124 v_b_190_1) (<= v_b_191_1 v_idx_124) (= (select |c_#memory_int| v_idx_124) 0)) (<= (+ v_b_187_1 1) v_b_190_1) (<= .cse7 v_b_191_1) (<= .cse8 v_b_186_1) (<= .cse9 v_b_194_1) (<= v_b_185_1 .cse8) (<= .cse10 v_b_187_1) (<= .cse11 v_b_193_1) (<= .cse3 v_b_194_1) (<= v_b_187_1 .cse12) (<= .cse13 c_ULTIMATE.start_main_p4) (<= (+ v_b_187_1 4) v_b_195_1) (<= .cse14 v_b_187_1) (<= v_b_191_1 .cse1) (<= .cse15 v_b_191_1) (or (= (select |c_#memory_int| v_idx_120) 0) (<= v_b_187_1 v_idx_120) (< v_idx_120 v_b_186_1)) (<= (+ v_b_186_1 5) v_b_195_1) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_1) (<= (+ v_b_193_1 1) v_b_195_1) (or (< v_idx_129 v_b_195_1) (= (select |c_#memory_int| v_idx_129) v_v_1759_1)) (<= .cse15 v_b_192_1) (<= .cse5 v_b_192_1) (<= .cse16 v_b_194_1) (<= .cse2 v_b_190_1) (<= .cse13 v_b_187_1) (<= .cse9 v_b_193_1) (<= (+ v_b_185_1 2) v_b_190_1) (<= (+ v_b_190_1 3) v_b_195_1) (<= .cse11 v_b_194_1) (<= .cse0 v_b_194_1) (<= .cse17 v_b_194_1) (<= .cse18 v_b_192_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_190_1) (or (= (select |c_#memory_int| v_idx_122) v_v_1752_1) (< v_idx_122 c_ULTIMATE.start_main_p4) (<= .cse2 v_idx_122)) (<= .cse10 c_ULTIMATE.start_main_p4) (<= .cse19 v_b_186_1) (or (< v_idx_128 v_b_194_1) (<= v_b_195_1 v_idx_128) (= (select |c_#memory_int| v_idx_128) 0)) (<= .cse4 v_b_194_1) (<= .cse3 v_b_193_1) (<= .cse20 v_b_191_1) (or (= (select |c_#memory_int| v_idx_121) v_v_1751_1) (< v_idx_121 v_b_187_1) (<= c_ULTIMATE.start_main_p4 v_idx_121)) (<= .cse20 v_b_192_1) (<= .cse21 v_b_191_1) (<= .cse22 v_b_194_1) (<= .cse14 c_ULTIMATE.start_main_p4) (<= .cse17 v_b_193_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_115) (= (select |c_#memory_int| v_idx_115) v_v_1745_1)) (or (= (select |c_#memory_int| v_idx_117) v_v_1747_1) (< v_idx_117 .cse6) (<= v_b_184_1 v_idx_117)) (<= .cse12 v_b_187_1) (<= .cse19 v_b_185_1) (<= v_b_195_1 .cse23) (<= v_v_1752_1 0) (<= .cse22 v_b_193_1) (<= (+ v_b_192_1 2) v_b_195_1) (<= .cse16 v_b_193_1) (or (< v_idx_126 v_b_192_1) (= 0 (select |c_#memory_int| v_idx_126)) (<= v_b_193_1 v_idx_126)) (<= .cse18 v_b_191_1) (<= .cse24 v_b_194_1) (<= .cse1 v_b_191_1) (<= .cse6 v_b_184_1) (<= .cse24 v_b_193_1) (<= .cse21 v_b_192_1) (<= .cse8 v_b_185_1) (<= v_b_185_1 v_b_186_1) (<= .cse23 v_b_195_1) (<= .cse7 v_b_192_1) (<= .cse12 c_ULTIMATE.start_main_p4) (<= v_b_191_1 v_b_192_1) (or (<= v_b_186_1 v_idx_119) (< v_idx_119 v_b_185_1) (= (select |c_#memory_int| v_idx_119) v_v_1749_1)) (<= (+ c_ULTIMATE.start_main_p4 4) v_b_195_1))))) is different from false [2019-01-11 11:45:03,069 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_137 Int) (v_idx_138 Int) (v_idx_135 Int) (v_idx_136 Int) (v_idx_139 Int) (v_idx_140 Int) (v_idx_141 Int) (v_idx_130 Int) (v_idx_144 Int) (v_idx_133 Int) (v_idx_134 Int) (v_idx_142 Int) (v_idx_131 Int) (v_idx_143 Int) (v_idx_132 Int)) (exists ((v_b_195_1 Int) (v_b_184_1 Int) (v_b_194_1 Int) (v_v_1753_1 Int) (v_b_185_1 Int) (v_b_186_1 Int) (v_v_1745_1 Int) (v_v_1755_1 Int) (v_b_187_1 Int) (v_v_1747_1 Int) (v_b_188_1 Int) (v_v_1757_1 Int) (v_b_189_1 Int) (v_v_1749_1 Int) (v_v_1759_1 Int) (v_b_191_1 Int) (v_b_190_1 Int) (v_v_1752_1 Int) (v_b_193_1 Int) (v_b_192_1 Int) (v_v_1751_1 Int)) (let ((.cse4 (+ v_b_189_1 2)) (.cse11 (+ c_ULTIMATE.start_main_p1 3)) (.cse15 (+ v_b_184_1 2)) (.cse18 (+ v_b_184_1 5)) (.cse16 (+ v_b_185_1 2)) (.cse7 (+ v_b_189_1 1)) (.cse17 (+ v_b_188_1 1)) (.cse1 (+ v_b_186_1 2)) (.cse2 (+ v_b_184_1 3)) (.cse19 (+ v_b_190_1 2)) (.cse20 (+ v_b_187_1 1)) (.cse3 (+ v_b_188_1 3)) (.cse13 (+ v_b_185_1 1)) (.cse28 (+ v_b_184_1 4)) (.cse27 (+ c_ULTIMATE.start_main_p1 6)) (.cse8 (+ v_b_186_1 4)) (.cse21 (+ v_b_185_1 4)) (.cse23 (+ v_b_185_1 3)) (.cse25 (+ c_ULTIMATE.start_main_p1 4)) (.cse0 (+ v_b_188_1 2)) (.cse5 (+ v_b_192_1 1)) (.cse30 (+ v_b_187_1 2)) (.cse22 (+ v_b_191_1 1)) (.cse29 (+ c_ULTIMATE.start_main_p1 2)) (.cse24 (+ v_b_194_1 1)) (.cse14 (+ v_b_187_1 3)) (.cse12 (+ v_b_190_1 1)) (.cse31 (+ v_b_186_1 3)) (.cse26 (+ v_b_184_1 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 5)) (.cse10 (+ v_b_186_1 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 1))) (and (<= .cse0 v_b_191_1) (<= .cse1 v_b_189_1) (<= .cse2 v_b_189_1) (<= (+ v_b_184_1 6) v_b_195_1) (<= (+ v_b_191_1 2) v_b_195_1) (or (< v_idx_137 v_b_188_1) (<= v_b_189_1 v_idx_137) (= (select |c_#memory_int| v_idx_137) v_v_1752_1)) (<= .cse3 v_b_193_1) (<= .cse4 v_b_193_1) (<= .cse4 v_b_194_1) (<= v_b_193_1 .cse5) (<= v_b_193_1 v_b_194_1) (<= .cse6 v_b_191_1) (<= .cse7 v_b_191_1) (or (<= v_b_185_1 v_idx_133) (= (select |c_#memory_int| v_idx_133) 0) (< v_idx_133 v_b_184_1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_130) (= (select |c_#memory_int| v_idx_130) v_v_1745_1)) (<= .cse8 v_b_193_1) (<= .cse5 v_b_194_1) (or (< v_idx_131 c_ULTIMATE.start_main_p1) (<= .cse9 v_idx_131) (= (select |c_#memory_int| v_idx_131) 0)) (<= v_b_187_1 .cse10) (<= (+ v_b_187_1 4) v_b_195_1) (<= .cse11 v_b_187_1) (<= v_b_191_1 .cse12) (<= (+ v_b_186_1 5) v_b_195_1) (<= (+ v_b_193_1 1) v_b_195_1) (or (<= v_b_186_1 v_idx_134) (= (select |c_#memory_int| v_idx_134) v_v_1749_1) (< v_idx_134 v_b_185_1)) (<= .cse13 v_b_188_1) (<= .cse14 v_b_194_1) (<= .cse15 v_b_187_1) (<= .cse16 v_b_190_1) (<= (+ v_b_190_1 3) v_b_195_1) (<= v_b_189_1 .cse17) (<= .cse18 v_b_194_1) (<= .cse19 v_b_194_1) (<= .cse20 v_b_189_1) (<= .cse11 v_b_188_1) (<= .cse15 v_b_188_1) (<= .cse21 v_b_193_1) (or (<= v_b_194_1 v_idx_142) (< v_idx_142 v_b_193_1) (= (select |c_#memory_int| v_idx_142) v_v_1757_1)) (<= v_v_1752_1 0) (<= .cse22 v_b_193_1) (<= (+ v_b_192_1 2) v_b_195_1) (<= .cse23 v_b_191_1) (<= .cse9 v_b_184_1) (<= v_b_185_1 v_b_186_1) (<= .cse24 v_b_195_1) (<= .cse17 v_b_189_1) (<= (* 2 v_v_1752_1) 0) (<= .cse18 v_b_193_1) (or (= (select |c_#memory_int| v_idx_136) v_v_1751_1) (< v_idx_136 v_b_187_1) (<= v_b_188_1 v_idx_136)) (<= .cse16 v_b_189_1) (or (= 0 (select |c_#memory_int| v_idx_141)) (< v_idx_141 v_b_192_1) (<= v_b_193_1 v_idx_141)) (<= (+ v_b_188_1 4) v_b_195_1) (<= .cse12 v_b_192_1) (<= (+ v_b_185_1 5) v_b_195_1) (<= .cse7 v_b_192_1) (<= .cse17 v_b_190_1) (<= .cse1 v_b_190_1) (<= (+ v_b_189_1 3) v_b_195_1) (<= .cse2 v_b_190_1) (<= .cse19 v_b_193_1) (<= .cse25 v_b_189_1) (<= .cse20 v_b_190_1) (or (<= v_b_190_1 v_idx_138) (= (select |c_#memory_int| v_idx_138) v_v_1753_1) (< v_idx_138 v_b_189_1)) (<= .cse26 v_b_186_1) (<= .cse27 v_b_194_1) (<= .cse3 v_b_194_1) (<= v_b_185_1 .cse26) (<= .cse13 v_b_187_1) (<= .cse28 v_b_191_1) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_1) (<= .cse28 v_b_192_1) (or (<= v_b_192_1 v_idx_140) (< v_idx_140 v_b_191_1) (= (select |c_#memory_int| v_idx_140) v_v_1755_1)) (<= .cse27 v_b_193_1) (or (< v_idx_143 v_b_194_1) (= (select |c_#memory_int| v_idx_143) 0) (<= v_b_195_1 v_idx_143)) (<= .cse8 v_b_194_1) (or (< v_idx_139 v_b_190_1) (= (select |c_#memory_int| v_idx_139) 0) (<= v_b_191_1 v_idx_139)) (<= .cse21 v_b_194_1) (<= .cse23 v_b_192_1) (<= .cse25 v_b_190_1) (<= .cse29 v_b_186_1) (<= .cse0 v_b_192_1) (<= .cse5 v_b_193_1) (<= .cse30 v_b_191_1) (or (<= v_b_187_1 v_idx_135) (< v_idx_135 v_b_186_1) (= (select |c_#memory_int| v_idx_135) 0)) (<= .cse30 v_b_192_1) (<= .cse31 v_b_191_1) (<= v_b_187_1 v_b_188_1) (<= .cse22 v_b_194_1) (or (< v_idx_144 v_b_195_1) (= (select |c_#memory_int| v_idx_144) v_v_1759_1)) (<= .cse10 v_b_187_1) (<= .cse29 v_b_185_1) (<= v_b_195_1 .cse24) (<= .cse14 v_b_193_1) (<= .cse12 v_b_191_1) (<= v_b_189_1 v_b_190_1) (<= .cse31 v_b_192_1) (<= .cse26 v_b_185_1) (<= .cse6 v_b_192_1) (<= .cse10 v_b_188_1) (<= v_b_191_1 v_b_192_1) (or (< v_idx_132 .cse9) (= (select |c_#memory_int| v_idx_132) v_v_1747_1) (<= v_b_184_1 v_idx_132)))))) is different from false [2019-01-11 11:45:03,316 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:45:03,317 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:45:03,317 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:45:03,318 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:45:03,318 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:45:03,318 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:45:03,318 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:45:03,319 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:45:03,319 INFO L87 Difference]: Start difference. First operand 17 states and 30 transitions. Second operand 4 states. [2019-01-11 11:45:06,333 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_137 Int) (v_idx_138 Int) (v_idx_135 Int) (v_idx_136 Int) (v_idx_139 Int) (v_idx_140 Int) (v_idx_141 Int) (v_idx_130 Int) (v_idx_144 Int) (v_idx_133 Int) (v_idx_134 Int) (v_idx_142 Int) (v_idx_131 Int) (v_idx_143 Int) (v_idx_132 Int)) (exists ((v_b_195_1 Int) (v_b_184_1 Int) (v_b_194_1 Int) (v_v_1753_1 Int) (v_b_185_1 Int) (v_b_186_1 Int) (v_v_1745_1 Int) (v_v_1755_1 Int) (v_b_187_1 Int) (v_v_1747_1 Int) (v_b_188_1 Int) (v_v_1757_1 Int) (v_b_189_1 Int) (v_v_1749_1 Int) (v_v_1759_1 Int) (v_b_191_1 Int) (v_b_190_1 Int) (v_v_1752_1 Int) (v_b_193_1 Int) (v_b_192_1 Int) (v_v_1751_1 Int)) (let ((.cse4 (+ v_b_189_1 2)) (.cse11 (+ c_ULTIMATE.start_main_p1 3)) (.cse15 (+ v_b_184_1 2)) (.cse18 (+ v_b_184_1 5)) (.cse16 (+ v_b_185_1 2)) (.cse7 (+ v_b_189_1 1)) (.cse17 (+ v_b_188_1 1)) (.cse1 (+ v_b_186_1 2)) (.cse2 (+ v_b_184_1 3)) (.cse19 (+ v_b_190_1 2)) (.cse20 (+ v_b_187_1 1)) (.cse3 (+ v_b_188_1 3)) (.cse13 (+ v_b_185_1 1)) (.cse28 (+ v_b_184_1 4)) (.cse27 (+ c_ULTIMATE.start_main_p1 6)) (.cse8 (+ v_b_186_1 4)) (.cse21 (+ v_b_185_1 4)) (.cse23 (+ v_b_185_1 3)) (.cse25 (+ c_ULTIMATE.start_main_p1 4)) (.cse0 (+ v_b_188_1 2)) (.cse5 (+ v_b_192_1 1)) (.cse30 (+ v_b_187_1 2)) (.cse22 (+ v_b_191_1 1)) (.cse29 (+ c_ULTIMATE.start_main_p1 2)) (.cse24 (+ v_b_194_1 1)) (.cse14 (+ v_b_187_1 3)) (.cse12 (+ v_b_190_1 1)) (.cse31 (+ v_b_186_1 3)) (.cse26 (+ v_b_184_1 1)) (.cse6 (+ c_ULTIMATE.start_main_p1 5)) (.cse10 (+ v_b_186_1 1)) (.cse9 (+ c_ULTIMATE.start_main_p1 1))) (and (<= .cse0 v_b_191_1) (<= .cse1 v_b_189_1) (<= .cse2 v_b_189_1) (<= (+ v_b_184_1 6) v_b_195_1) (<= (+ v_b_191_1 2) v_b_195_1) (or (< v_idx_137 v_b_188_1) (<= v_b_189_1 v_idx_137) (= (select |c_#memory_int| v_idx_137) v_v_1752_1)) (<= .cse3 v_b_193_1) (<= .cse4 v_b_193_1) (<= .cse4 v_b_194_1) (<= v_b_193_1 .cse5) (<= v_b_193_1 v_b_194_1) (<= .cse6 v_b_191_1) (<= .cse7 v_b_191_1) (or (<= v_b_185_1 v_idx_133) (= (select |c_#memory_int| v_idx_133) 0) (< v_idx_133 v_b_184_1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_130) (= (select |c_#memory_int| v_idx_130) v_v_1745_1)) (<= .cse8 v_b_193_1) (<= .cse5 v_b_194_1) (or (< v_idx_131 c_ULTIMATE.start_main_p1) (<= .cse9 v_idx_131) (= (select |c_#memory_int| v_idx_131) 0)) (<= v_b_187_1 .cse10) (<= (+ v_b_187_1 4) v_b_195_1) (<= .cse11 v_b_187_1) (<= v_b_191_1 .cse12) (<= (+ v_b_186_1 5) v_b_195_1) (<= (+ v_b_193_1 1) v_b_195_1) (or (<= v_b_186_1 v_idx_134) (= (select |c_#memory_int| v_idx_134) v_v_1749_1) (< v_idx_134 v_b_185_1)) (<= .cse13 v_b_188_1) (<= .cse14 v_b_194_1) (<= .cse15 v_b_187_1) (<= .cse16 v_b_190_1) (<= (+ v_b_190_1 3) v_b_195_1) (<= v_b_189_1 .cse17) (<= .cse18 v_b_194_1) (<= .cse19 v_b_194_1) (<= .cse20 v_b_189_1) (<= .cse11 v_b_188_1) (<= .cse15 v_b_188_1) (<= .cse21 v_b_193_1) (or (<= v_b_194_1 v_idx_142) (< v_idx_142 v_b_193_1) (= (select |c_#memory_int| v_idx_142) v_v_1757_1)) (<= v_v_1752_1 0) (<= .cse22 v_b_193_1) (<= (+ v_b_192_1 2) v_b_195_1) (<= .cse23 v_b_191_1) (<= .cse9 v_b_184_1) (<= v_b_185_1 v_b_186_1) (<= .cse24 v_b_195_1) (<= .cse17 v_b_189_1) (<= (* 2 v_v_1752_1) 0) (<= .cse18 v_b_193_1) (or (= (select |c_#memory_int| v_idx_136) v_v_1751_1) (< v_idx_136 v_b_187_1) (<= v_b_188_1 v_idx_136)) (<= .cse16 v_b_189_1) (or (= 0 (select |c_#memory_int| v_idx_141)) (< v_idx_141 v_b_192_1) (<= v_b_193_1 v_idx_141)) (<= (+ v_b_188_1 4) v_b_195_1) (<= .cse12 v_b_192_1) (<= (+ v_b_185_1 5) v_b_195_1) (<= .cse7 v_b_192_1) (<= .cse17 v_b_190_1) (<= .cse1 v_b_190_1) (<= (+ v_b_189_1 3) v_b_195_1) (<= .cse2 v_b_190_1) (<= .cse19 v_b_193_1) (<= .cse25 v_b_189_1) (<= .cse20 v_b_190_1) (or (<= v_b_190_1 v_idx_138) (= (select |c_#memory_int| v_idx_138) v_v_1753_1) (< v_idx_138 v_b_189_1)) (<= .cse26 v_b_186_1) (<= .cse27 v_b_194_1) (<= .cse3 v_b_194_1) (<= v_b_185_1 .cse26) (<= .cse13 v_b_187_1) (<= .cse28 v_b_191_1) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_1) (<= .cse28 v_b_192_1) (or (<= v_b_192_1 v_idx_140) (< v_idx_140 v_b_191_1) (= (select |c_#memory_int| v_idx_140) v_v_1755_1)) (<= .cse27 v_b_193_1) (or (< v_idx_143 v_b_194_1) (= (select |c_#memory_int| v_idx_143) 0) (<= v_b_195_1 v_idx_143)) (<= .cse8 v_b_194_1) (or (< v_idx_139 v_b_190_1) (= (select |c_#memory_int| v_idx_139) 0) (<= v_b_191_1 v_idx_139)) (<= .cse21 v_b_194_1) (<= .cse23 v_b_192_1) (<= .cse25 v_b_190_1) (<= .cse29 v_b_186_1) (<= .cse0 v_b_192_1) (<= .cse5 v_b_193_1) (<= .cse30 v_b_191_1) (or (<= v_b_187_1 v_idx_135) (< v_idx_135 v_b_186_1) (= (select |c_#memory_int| v_idx_135) 0)) (<= .cse30 v_b_192_1) (<= .cse31 v_b_191_1) (<= v_b_187_1 v_b_188_1) (<= .cse22 v_b_194_1) (or (< v_idx_144 v_b_195_1) (= (select |c_#memory_int| v_idx_144) v_v_1759_1)) (<= .cse10 v_b_187_1) (<= .cse29 v_b_185_1) (<= v_b_195_1 .cse24) (<= .cse14 v_b_193_1) (<= .cse12 v_b_191_1) (<= v_b_189_1 v_b_190_1) (<= .cse31 v_b_192_1) (<= .cse26 v_b_185_1) (<= .cse6 v_b_192_1) (<= .cse10 v_b_188_1) (<= v_b_191_1 v_b_192_1) (or (< v_idx_132 .cse9) (= (select |c_#memory_int| v_idx_132) v_v_1747_1) (<= v_b_184_1 v_idx_132)))))) (forall ((v_idx_126 Int) (v_idx_115 Int) (v_idx_127 Int) (v_idx_116 Int) (v_idx_124 Int) (v_idx_125 Int) (v_idx_119 Int) (v_idx_128 Int) (v_idx_117 Int) (v_idx_129 Int) (v_idx_118 Int) (v_idx_122 Int) (v_idx_123 Int) (v_idx_120 Int) (v_idx_121 Int)) (exists ((v_b_195_1 Int) (v_b_194_1 Int) (v_b_184_1 Int) (v_v_1753_1 Int) (v_b_185_1 Int) (v_v_1755_1 Int) (v_b_186_1 Int) (v_v_1745_1 Int) (v_b_187_1 Int) (v_v_1747_1 Int) (v_v_1757_1 Int) (v_v_1749_1 Int) (v_v_1759_1 Int) (v_b_191_1 Int) (v_b_190_1 Int) (v_b_193_1 Int) (v_v_1752_1 Int) (v_b_192_1 Int) (v_v_1751_1 Int)) (let ((.cse47 (+ v_b_184_1 4)) (.cse37 (+ c_ULTIMATE.start_main_p4 2)) (.cse45 (+ v_b_184_1 2)) (.cse41 (+ c_ULTIMATE.start_main_p1 6)) (.cse43 (+ v_b_186_1 4)) (.cse32 (+ v_b_184_1 5)) (.cse34 (+ c_ULTIMATE.start_main_p4 1)) (.cse42 (+ v_b_185_1 1)) (.cse36 (+ v_b_190_1 2)) (.cse35 (+ v_b_192_1 1)) (.cse52 (+ v_b_187_1 2)) (.cse46 (+ c_ULTIMATE.start_main_p1 3)) (.cse49 (+ v_b_185_1 4)) (.cse51 (+ c_ULTIMATE.start_main_p1 2)) (.cse54 (+ v_b_191_1 1)) (.cse48 (+ v_b_187_1 3)) (.cse50 (+ v_b_185_1 3)) (.cse33 (+ v_b_190_1 1)) (.cse38 (+ c_ULTIMATE.start_main_p1 1)) (.cse56 (+ c_ULTIMATE.start_main_p4 3)) (.cse53 (+ v_b_186_1 3)) (.cse40 (+ v_b_184_1 1)) (.cse55 (+ v_b_194_1 1)) (.cse39 (+ c_ULTIMATE.start_main_p1 5)) (.cse44 (+ v_b_186_1 1))) (and (<= (* 2 v_v_1752_1) 0) (<= .cse32 v_b_193_1) (or (= (select |c_#memory_int| v_idx_127) v_v_1757_1) (< v_idx_127 v_b_193_1) (<= v_b_194_1 v_idx_127)) (<= (+ v_b_184_1 6) v_b_195_1) (<= .cse33 v_b_192_1) (or (<= v_b_192_1 v_idx_125) (= (select |c_#memory_int| v_idx_125) v_v_1755_1) (< v_idx_125 v_b_191_1)) (<= (+ v_b_191_1 2) v_b_195_1) (or (< v_idx_123 .cse34) (<= v_b_190_1 v_idx_123) (= (select |c_#memory_int| v_idx_123) v_v_1753_1)) (<= (+ v_b_185_1 5) v_b_195_1) (<= v_b_187_1 c_ULTIMATE.start_main_p4) (or (<= v_b_185_1 v_idx_118) (< v_idx_118 v_b_184_1) (= (select |c_#memory_int| v_idx_118) 0)) (<= v_b_193_1 .cse35) (<= (+ v_b_186_1 2) v_b_190_1) (<= v_b_193_1 v_b_194_1) (<= (+ v_b_184_1 3) v_b_190_1) (<= .cse36 v_b_193_1) (<= .cse37 v_b_191_1) (or (= (select |c_#memory_int| v_idx_116) 0) (< v_idx_116 c_ULTIMATE.start_main_p1) (<= .cse38 v_idx_116)) (or (< v_idx_124 v_b_190_1) (<= v_b_191_1 v_idx_124) (= (select |c_#memory_int| v_idx_124) 0)) (<= (+ v_b_187_1 1) v_b_190_1) (<= .cse39 v_b_191_1) (<= .cse40 v_b_186_1) (<= .cse41 v_b_194_1) (<= v_b_185_1 .cse40) (<= .cse42 v_b_187_1) (<= .cse43 v_b_193_1) (<= .cse35 v_b_194_1) (<= v_b_187_1 .cse44) (<= .cse45 c_ULTIMATE.start_main_p4) (<= (+ v_b_187_1 4) v_b_195_1) (<= .cse46 v_b_187_1) (<= v_b_191_1 .cse33) (<= .cse47 v_b_191_1) (or (= (select |c_#memory_int| v_idx_120) 0) (<= v_b_187_1 v_idx_120) (< v_idx_120 v_b_186_1)) (<= (+ v_b_186_1 5) v_b_195_1) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_1) (<= (+ v_b_193_1 1) v_b_195_1) (or (< v_idx_129 v_b_195_1) (= (select |c_#memory_int| v_idx_129) v_v_1759_1)) (<= .cse47 v_b_192_1) (<= .cse37 v_b_192_1) (<= .cse48 v_b_194_1) (<= .cse34 v_b_190_1) (<= .cse45 v_b_187_1) (<= .cse41 v_b_193_1) (<= (+ v_b_185_1 2) v_b_190_1) (<= (+ v_b_190_1 3) v_b_195_1) (<= .cse43 v_b_194_1) (<= .cse32 v_b_194_1) (<= .cse49 v_b_194_1) (<= .cse50 v_b_192_1) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_190_1) (or (= (select |c_#memory_int| v_idx_122) v_v_1752_1) (< v_idx_122 c_ULTIMATE.start_main_p4) (<= .cse34 v_idx_122)) (<= .cse42 c_ULTIMATE.start_main_p4) (<= .cse51 v_b_186_1) (or (< v_idx_128 v_b_194_1) (<= v_b_195_1 v_idx_128) (= (select |c_#memory_int| v_idx_128) 0)) (<= .cse36 v_b_194_1) (<= .cse35 v_b_193_1) (<= .cse52 v_b_191_1) (or (= (select |c_#memory_int| v_idx_121) v_v_1751_1) (< v_idx_121 v_b_187_1) (<= c_ULTIMATE.start_main_p4 v_idx_121)) (<= .cse52 v_b_192_1) (<= .cse53 v_b_191_1) (<= .cse54 v_b_194_1) (<= .cse46 c_ULTIMATE.start_main_p4) (<= .cse49 v_b_193_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_115) (= (select |c_#memory_int| v_idx_115) v_v_1745_1)) (or (= (select |c_#memory_int| v_idx_117) v_v_1747_1) (< v_idx_117 .cse38) (<= v_b_184_1 v_idx_117)) (<= .cse44 v_b_187_1) (<= .cse51 v_b_185_1) (<= v_b_195_1 .cse55) (<= v_v_1752_1 0) (<= .cse54 v_b_193_1) (<= (+ v_b_192_1 2) v_b_195_1) (<= .cse48 v_b_193_1) (or (< v_idx_126 v_b_192_1) (= 0 (select |c_#memory_int| v_idx_126)) (<= v_b_193_1 v_idx_126)) (<= .cse50 v_b_191_1) (<= .cse56 v_b_194_1) (<= .cse33 v_b_191_1) (<= .cse38 v_b_184_1) (<= .cse56 v_b_193_1) (<= .cse53 v_b_192_1) (<= .cse40 v_b_185_1) (<= v_b_185_1 v_b_186_1) (<= .cse55 v_b_195_1) (<= .cse39 v_b_192_1) (<= .cse44 c_ULTIMATE.start_main_p4) (<= v_b_191_1 v_b_192_1) (or (<= v_b_186_1 v_idx_119) (< v_idx_119 v_b_185_1) (= (select |c_#memory_int| v_idx_119) v_v_1749_1)) (<= (+ c_ULTIMATE.start_main_p4 4) v_b_195_1)))))) is different from false [2019-01-11 11:45:53,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:45:53,412 INFO L93 Difference]: Finished difference Result 19 states and 39 transitions. [2019-01-11 11:45:53,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:45:53,412 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:45:53,412 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:45:53,413 INFO L225 Difference]: With dead ends: 19 [2019-01-11 11:45:53,413 INFO L226 Difference]: Without dead ends: 18 [2019-01-11 11:45:53,414 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 8.0s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:45:53,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states. [2019-01-11 11:45:53,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2019-01-11 11:45:53,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2019-01-11 11:45:53,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 38 transitions. [2019-01-11 11:45:53,421 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 38 transitions. Word has length 3 [2019-01-11 11:45:53,421 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:45:53,422 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 38 transitions. [2019-01-11 11:45:53,422 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:45:53,422 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 38 transitions. [2019-01-11 11:45:53,422 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:45:53,423 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:45:53,423 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:45:53,424 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:45:53,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:53,424 INFO L82 PathProgramCache]: Analyzing trace with hash 30008, now seen corresponding path program 1 times [2019-01-11 11:45:53,424 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:45:53,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:53,426 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:45:53,426 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:53,426 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:45:53,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:45:53,517 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:45:53,517 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:45:53,518 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:45:53,518 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:45:53,518 INFO L207 CegarAbsIntRunner]: [0], [6], [31] [2019-01-11 11:45:53,520 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:45:53,520 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:46:08,220 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:46:08,220 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:46:08,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:46:08,221 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:46:08,834 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 81.82% of their original sizes. [2019-01-11 11:46:08,835 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:46:11,257 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_269 Int) (v_idx_259 Int) (v_idx_267 Int) (v_idx_268 Int) (v_idx_261 Int) (v_idx_272 Int) (v_idx_262 Int) (v_idx_273 Int) (v_idx_270 Int) (v_idx_260 Int) (v_idx_271 Int) (v_idx_265 Int) (v_idx_266 Int) (v_idx_263 Int) (v_idx_264 Int)) (exists ((v_v_1929_2 Int) (v_v_1937_2 Int) (v_v_1939_2 Int) (v_b_194_2 Int) (v_v_1933_2 Int) (v_b_193_2 Int) (v_v_1943_2 Int) (v_b_184_2 Int) (v_b_185_2 Int) (v_b_195_2 Int) (v_v_1935_2 Int) (v_b_186_2 Int) (v_b_187_2 Int) (v_v_1930_2 Int) (v_b_188_2 Int) (v_b_189_2 Int) (v_v_1941_2 Int) (v_v_1931_2 Int) (v_b_190_2 Int) (v_b_192_2 Int) (v_b_191_2 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse5 (+ v_b_185_2 4)) (.cse8 (+ c_ULTIMATE.start_main_p1 6)) (.cse10 (+ v_b_187_2 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 3)) (.cse16 (+ v_b_185_2 3)) (.cse14 (+ v_b_188_2 2)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse22 (+ v_b_184_2 3)) (.cse15 (+ v_b_186_2 2)) (.cse17 (+ v_b_187_2 3)) (.cse13 (+ c_ULTIMATE.start_main_p1 1)) (.cse9 (+ v_b_184_2 4)) (.cse28 (+ v_b_185_2 1)) (.cse11 (+ v_b_190_2 2)) (.cse19 (+ v_b_186_2 1)) (.cse23 (+ v_b_184_2 5)) (.cse31 (+ v_b_189_2 2)) (.cse30 (+ v_b_194_2 1)) (.cse12 (+ v_b_190_2 1)) (.cse26 (+ v_b_186_2 4)) (.cse6 (+ v_b_187_2 2)) (.cse25 (+ v_b_184_2 2)) (.cse20 (+ v_b_188_2 3)) (.cse2 (+ v_b_192_2 1)) (.cse1 (+ v_b_191_2 1)) (.cse21 (+ v_b_186_2 3)) (.cse29 (+ v_b_188_2 1)) (.cse4 (+ v_b_185_2 2)) (.cse27 (+ c_ULTIMATE.start_main_p1 5)) (.cse24 (+ v_b_189_2 1)) (.cse0 (+ v_b_184_2 1))) (and (<= v_b_185_2 .cse0) (<= .cse1 v_b_193_2) (<= .cse2 v_b_193_2) (<= .cse3 v_b_189_2) (<= .cse4 v_b_190_2) (or (< v_idx_270 v_b_192_2) (= 0 (select |c_#memory_int| v_idx_270)) (<= v_b_193_2 v_idx_270)) (or (= (select |c_#memory_int| v_idx_263) v_v_1933_2) (<= v_b_186_2 v_idx_263) (< v_idx_263 v_b_185_2)) (<= .cse5 v_b_194_2) (<= 0 (* 2 v_v_1930_2)) (<= .cse6 v_b_192_2) (<= .cse7 v_b_186_2) (<= .cse8 v_b_194_2) (<= .cse9 v_b_191_2) (<= .cse10 v_b_190_2) (<= .cse11 v_b_194_2) (<= .cse12 v_b_192_2) (<= .cse13 v_b_184_2) (<= .cse14 v_b_191_2) (<= (+ v_b_185_2 5) v_b_195_2) (<= .cse15 v_b_190_2) (<= .cse16 v_b_191_2) (or (= (select |c_#memory_int| v_idx_260) v_v_1930_2) (< v_idx_260 c_ULTIMATE.start_main_p1) (<= .cse13 v_idx_260)) (or (< v_idx_264 v_b_186_2) (= 0 (select |c_#memory_int| v_idx_264)) (<= v_b_187_2 v_idx_264)) (<= .cse3 v_b_190_2) (<= (+ v_b_190_2 3) v_b_195_2) (<= .cse5 v_b_193_2) (<= .cse8 v_b_193_2) (<= 0 v_v_1930_2) (<= .cse17 v_b_193_2) (<= .cse0 v_b_186_2) (or (= 0 (select |c_#memory_int| v_idx_262)) (< v_idx_262 v_b_184_2) (<= v_b_185_2 v_idx_262)) (<= .cse10 v_b_189_2) (<= (+ v_b_189_2 3) v_b_195_2) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_2) (or (< v_idx_266 v_b_188_2) (<= v_b_189_2 v_idx_266) (= 0 (select |c_#memory_int| v_idx_266))) (<= .cse18 v_b_187_2) (<= .cse18 v_b_188_2) (<= .cse16 v_b_192_2) (<= .cse19 v_b_188_2) (<= .cse20 v_b_193_2) (or (< v_idx_271 v_b_193_2) (<= v_b_194_2 v_idx_271) (= (select |c_#memory_int| v_idx_271) v_v_1941_2)) (<= .cse14 v_b_192_2) (<= (+ v_b_184_2 6) v_b_195_2) (<= .cse21 v_b_192_2) (or (<= v_b_192_2 v_idx_269) (= v_v_1939_2 (select |c_#memory_int| v_idx_269)) (< v_idx_269 v_b_191_2)) (or (< v_idx_265 v_b_187_2) (<= v_b_188_2 v_idx_265) (= (select |c_#memory_int| v_idx_265) v_v_1935_2)) (<= .cse22 v_b_189_2) (<= .cse7 v_b_185_2) (<= .cse23 v_b_194_2) (<= .cse24 v_b_192_2) (<= (+ v_b_192_2 2) v_b_195_2) (<= v_b_189_2 v_b_190_2) (<= .cse22 v_b_190_2) (<= v_b_187_2 v_b_188_2) (<= .cse25 v_b_187_2) (<= (+ v_b_191_2 2) v_b_195_2) (<= .cse2 v_b_194_2) (<= (+ v_b_188_2 4) v_b_195_2) (<= .cse26 v_b_194_2) (<= .cse27 v_b_191_2) (<= .cse15 v_b_189_2) (or (< v_idx_268 v_b_190_2) (= 0 (select |c_#memory_int| v_idx_268)) (<= v_b_191_2 v_idx_268)) (<= (+ v_b_193_2 1) v_b_195_2) (<= .cse28 v_b_187_2) (<= v_b_187_2 .cse19) (or (= (select |c_#memory_int| v_idx_259) v_v_1929_2) (<= c_ULTIMATE.start_main_p1 v_idx_259)) (<= .cse17 v_b_194_2) (or (< v_idx_261 .cse13) (= (select |c_#memory_int| v_idx_261) v_v_1931_2) (<= v_b_184_2 v_idx_261)) (<= .cse9 v_b_192_2) (<= .cse28 v_b_188_2) (<= .cse11 v_b_193_2) (<= v_b_193_2 v_b_194_2) (<= (+ v_b_186_2 5) v_b_195_2) (<= v_b_189_2 .cse29) (<= .cse19 v_b_187_2) (<= (+ v_b_187_2 4) v_b_195_2) (<= v_b_195_2 .cse30) (<= .cse31 v_b_193_2) (<= v_b_191_2 v_b_192_2) (<= .cse23 v_b_193_2) (<= v_b_191_2 .cse12) (<= .cse31 v_b_194_2) (or (< v_idx_272 v_b_194_2) (<= v_b_195_2 v_idx_272) (= (select |c_#memory_int| v_idx_272) 0)) (<= .cse30 v_b_195_2) (<= .cse12 v_b_191_2) (<= .cse26 v_b_193_2) (or (= (select |c_#memory_int| v_idx_267) v_v_1937_2) (<= v_b_190_2 v_idx_267) (< v_idx_267 v_b_189_2)) (<= .cse6 v_b_191_2) (<= .cse25 v_b_188_2) (<= .cse20 v_b_194_2) (<= v_b_193_2 .cse2) (<= .cse1 v_b_194_2) (<= v_b_185_2 v_b_186_2) (or (= (select |c_#memory_int| v_idx_273) v_v_1943_2) (< v_idx_273 v_b_195_2)) (<= .cse29 v_b_190_2) (<= .cse21 v_b_191_2) (<= .cse29 v_b_189_2) (<= .cse4 v_b_189_2) (<= .cse27 v_b_192_2) (<= .cse24 v_b_191_2) (<= .cse0 v_b_185_2))))) is different from false [2019-01-11 11:46:13,276 WARN L860 $PredicateComparison]: unable to prove that (forall ((v_idx_269 Int) (v_idx_259 Int) (v_idx_267 Int) (v_idx_268 Int) (v_idx_261 Int) (v_idx_272 Int) (v_idx_262 Int) (v_idx_273 Int) (v_idx_270 Int) (v_idx_260 Int) (v_idx_271 Int) (v_idx_265 Int) (v_idx_266 Int) (v_idx_263 Int) (v_idx_264 Int)) (exists ((v_v_1929_2 Int) (v_v_1937_2 Int) (v_v_1939_2 Int) (v_b_194_2 Int) (v_v_1933_2 Int) (v_b_193_2 Int) (v_v_1943_2 Int) (v_b_184_2 Int) (v_b_185_2 Int) (v_b_195_2 Int) (v_v_1935_2 Int) (v_b_186_2 Int) (v_b_187_2 Int) (v_v_1930_2 Int) (v_b_188_2 Int) (v_b_189_2 Int) (v_v_1941_2 Int) (v_v_1931_2 Int) (v_b_190_2 Int) (v_b_192_2 Int) (v_b_191_2 Int)) (let ((.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse5 (+ v_b_185_2 4)) (.cse8 (+ c_ULTIMATE.start_main_p1 6)) (.cse10 (+ v_b_187_2 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 3)) (.cse16 (+ v_b_185_2 3)) (.cse14 (+ v_b_188_2 2)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse22 (+ v_b_184_2 3)) (.cse15 (+ v_b_186_2 2)) (.cse17 (+ v_b_187_2 3)) (.cse13 (+ c_ULTIMATE.start_main_p1 1)) (.cse9 (+ v_b_184_2 4)) (.cse28 (+ v_b_185_2 1)) (.cse11 (+ v_b_190_2 2)) (.cse19 (+ v_b_186_2 1)) (.cse23 (+ v_b_184_2 5)) (.cse31 (+ v_b_189_2 2)) (.cse30 (+ v_b_194_2 1)) (.cse12 (+ v_b_190_2 1)) (.cse26 (+ v_b_186_2 4)) (.cse6 (+ v_b_187_2 2)) (.cse25 (+ v_b_184_2 2)) (.cse20 (+ v_b_188_2 3)) (.cse2 (+ v_b_192_2 1)) (.cse1 (+ v_b_191_2 1)) (.cse21 (+ v_b_186_2 3)) (.cse29 (+ v_b_188_2 1)) (.cse4 (+ v_b_185_2 2)) (.cse27 (+ c_ULTIMATE.start_main_p1 5)) (.cse24 (+ v_b_189_2 1)) (.cse0 (+ v_b_184_2 1))) (and (<= v_b_185_2 .cse0) (<= .cse1 v_b_193_2) (<= .cse2 v_b_193_2) (<= .cse3 v_b_189_2) (<= .cse4 v_b_190_2) (or (< v_idx_270 v_b_192_2) (= 0 (select |c_#memory_int| v_idx_270)) (<= v_b_193_2 v_idx_270)) (or (= (select |c_#memory_int| v_idx_263) v_v_1933_2) (<= v_b_186_2 v_idx_263) (< v_idx_263 v_b_185_2)) (<= .cse5 v_b_194_2) (<= 0 (* 2 v_v_1930_2)) (<= .cse6 v_b_192_2) (<= .cse7 v_b_186_2) (<= .cse8 v_b_194_2) (<= .cse9 v_b_191_2) (<= .cse10 v_b_190_2) (<= .cse11 v_b_194_2) (<= .cse12 v_b_192_2) (<= .cse13 v_b_184_2) (<= .cse14 v_b_191_2) (<= (+ v_b_185_2 5) v_b_195_2) (<= .cse15 v_b_190_2) (<= .cse16 v_b_191_2) (or (= (select |c_#memory_int| v_idx_260) v_v_1930_2) (< v_idx_260 c_ULTIMATE.start_main_p1) (<= .cse13 v_idx_260)) (or (< v_idx_264 v_b_186_2) (= 0 (select |c_#memory_int| v_idx_264)) (<= v_b_187_2 v_idx_264)) (<= .cse3 v_b_190_2) (<= (+ v_b_190_2 3) v_b_195_2) (<= .cse5 v_b_193_2) (<= .cse8 v_b_193_2) (<= 0 v_v_1930_2) (<= .cse17 v_b_193_2) (<= .cse0 v_b_186_2) (or (= 0 (select |c_#memory_int| v_idx_262)) (< v_idx_262 v_b_184_2) (<= v_b_185_2 v_idx_262)) (<= .cse10 v_b_189_2) (<= (+ v_b_189_2 3) v_b_195_2) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_2) (or (< v_idx_266 v_b_188_2) (<= v_b_189_2 v_idx_266) (= 0 (select |c_#memory_int| v_idx_266))) (<= .cse18 v_b_187_2) (<= .cse18 v_b_188_2) (<= .cse16 v_b_192_2) (<= .cse19 v_b_188_2) (<= .cse20 v_b_193_2) (or (< v_idx_271 v_b_193_2) (<= v_b_194_2 v_idx_271) (= (select |c_#memory_int| v_idx_271) v_v_1941_2)) (<= .cse14 v_b_192_2) (<= (+ v_b_184_2 6) v_b_195_2) (<= .cse21 v_b_192_2) (or (<= v_b_192_2 v_idx_269) (= v_v_1939_2 (select |c_#memory_int| v_idx_269)) (< v_idx_269 v_b_191_2)) (or (< v_idx_265 v_b_187_2) (<= v_b_188_2 v_idx_265) (= (select |c_#memory_int| v_idx_265) v_v_1935_2)) (<= .cse22 v_b_189_2) (<= .cse7 v_b_185_2) (<= .cse23 v_b_194_2) (<= .cse24 v_b_192_2) (<= (+ v_b_192_2 2) v_b_195_2) (<= v_b_189_2 v_b_190_2) (<= .cse22 v_b_190_2) (<= v_b_187_2 v_b_188_2) (<= .cse25 v_b_187_2) (<= (+ v_b_191_2 2) v_b_195_2) (<= .cse2 v_b_194_2) (<= (+ v_b_188_2 4) v_b_195_2) (<= .cse26 v_b_194_2) (<= .cse27 v_b_191_2) (<= .cse15 v_b_189_2) (or (< v_idx_268 v_b_190_2) (= 0 (select |c_#memory_int| v_idx_268)) (<= v_b_191_2 v_idx_268)) (<= (+ v_b_193_2 1) v_b_195_2) (<= .cse28 v_b_187_2) (<= v_b_187_2 .cse19) (or (= (select |c_#memory_int| v_idx_259) v_v_1929_2) (<= c_ULTIMATE.start_main_p1 v_idx_259)) (<= .cse17 v_b_194_2) (or (< v_idx_261 .cse13) (= (select |c_#memory_int| v_idx_261) v_v_1931_2) (<= v_b_184_2 v_idx_261)) (<= .cse9 v_b_192_2) (<= .cse28 v_b_188_2) (<= .cse11 v_b_193_2) (<= v_b_193_2 v_b_194_2) (<= (+ v_b_186_2 5) v_b_195_2) (<= v_b_189_2 .cse29) (<= .cse19 v_b_187_2) (<= (+ v_b_187_2 4) v_b_195_2) (<= v_b_195_2 .cse30) (<= .cse31 v_b_193_2) (<= v_b_191_2 v_b_192_2) (<= .cse23 v_b_193_2) (<= v_b_191_2 .cse12) (<= .cse31 v_b_194_2) (or (< v_idx_272 v_b_194_2) (<= v_b_195_2 v_idx_272) (= (select |c_#memory_int| v_idx_272) 0)) (<= .cse30 v_b_195_2) (<= .cse12 v_b_191_2) (<= .cse26 v_b_193_2) (or (= (select |c_#memory_int| v_idx_267) v_v_1937_2) (<= v_b_190_2 v_idx_267) (< v_idx_267 v_b_189_2)) (<= .cse6 v_b_191_2) (<= .cse25 v_b_188_2) (<= .cse20 v_b_194_2) (<= v_b_193_2 .cse2) (<= .cse1 v_b_194_2) (<= v_b_185_2 v_b_186_2) (or (= (select |c_#memory_int| v_idx_273) v_v_1943_2) (< v_idx_273 v_b_195_2)) (<= .cse29 v_b_190_2) (<= .cse21 v_b_191_2) (<= .cse29 v_b_189_2) (<= .cse4 v_b_189_2) (<= .cse27 v_b_192_2) (<= .cse24 v_b_191_2) (<= .cse0 v_b_185_2))))) is different from true [2019-01-11 11:46:15,728 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_280 Int) (v_idx_278 Int) (v_idx_279 Int) (v_idx_283 Int) (v_idx_284 Int) (v_idx_281 Int) (v_idx_282 Int) (v_idx_287 Int) (v_idx_276 Int) (v_idx_288 Int) (v_idx_277 Int) (v_idx_285 Int) (v_idx_274 Int) (v_idx_286 Int) (v_idx_275 Int)) (exists ((v_v_1929_2 Int) (v_v_1937_2 Int) (v_v_1939_2 Int) (v_b_194_2 Int) (v_b_193_2 Int) (v_v_1933_2 Int) (v_v_1943_2 Int) (v_b_184_2 Int) (v_b_185_2 Int) (v_b_195_2 Int) (v_v_1935_2 Int) (v_b_186_2 Int) (v_b_187_2 Int) (v_b_188_2 Int) (v_v_1930_2 Int) (v_v_1931_2 Int) (v_b_189_2 Int) (v_v_1941_2 Int) (v_b_190_2 Int) (v_b_192_2 Int) (v_b_191_2 Int)) (let ((.cse13 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse5 (+ v_b_185_2 4)) (.cse8 (+ c_ULTIMATE.start_main_p1 6)) (.cse10 (+ v_b_187_2 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 3)) (.cse16 (+ v_b_185_2 3)) (.cse14 (+ v_b_188_2 2)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse22 (+ v_b_184_2 3)) (.cse15 (+ v_b_186_2 2)) (.cse17 (+ v_b_187_2 3)) (.cse9 (+ v_b_184_2 4)) (.cse28 (+ v_b_185_2 1)) (.cse11 (+ v_b_190_2 2)) (.cse19 (+ v_b_186_2 1)) (.cse23 (+ v_b_184_2 5)) (.cse31 (+ v_b_189_2 2)) (.cse30 (+ v_b_194_2 1)) (.cse12 (+ v_b_190_2 1)) (.cse26 (+ v_b_186_2 4)) (.cse6 (+ v_b_187_2 2)) (.cse25 (+ v_b_184_2 2)) (.cse20 (+ v_b_188_2 3)) (.cse2 (+ v_b_192_2 1)) (.cse1 (+ v_b_191_2 1)) (.cse21 (+ v_b_186_2 3)) (.cse29 (+ v_b_188_2 1)) (.cse4 (+ v_b_185_2 2)) (.cse27 (+ c_ULTIMATE.start_main_p1 5)) (.cse24 (+ v_b_189_2 1)) (.cse0 (+ v_b_184_2 1))) (and (<= v_b_185_2 .cse0) (<= .cse1 v_b_193_2) (<= .cse2 v_b_193_2) (<= .cse3 v_b_189_2) (or (<= v_b_189_2 v_idx_281) (< v_idx_281 v_b_188_2) (= 0 (select |c_#memory_int| v_idx_281))) (<= .cse4 v_b_190_2) (<= .cse5 v_b_194_2) (<= 0 (* 2 v_v_1930_2)) (<= .cse6 v_b_192_2) (<= .cse7 v_b_186_2) (<= .cse8 v_b_194_2) (<= .cse9 v_b_191_2) (<= .cse10 v_b_190_2) (<= .cse11 v_b_194_2) (<= .cse12 v_b_192_2) (or (< v_idx_275 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_275) v_v_1930_2) (<= .cse13 v_idx_275)) (<= .cse13 v_b_184_2) (<= .cse14 v_b_191_2) (<= (+ v_b_185_2 5) v_b_195_2) (<= .cse15 v_b_190_2) (<= .cse16 v_b_191_2) (or (= (select |c_#memory_int| v_idx_276) v_v_1931_2) (<= v_b_184_2 v_idx_276) (< v_idx_276 .cse13)) (<= .cse3 v_b_190_2) (or (< v_idx_280 v_b_187_2) (<= v_b_188_2 v_idx_280) (= (select |c_#memory_int| v_idx_280) v_v_1935_2)) (<= (+ v_b_190_2 3) v_b_195_2) (<= .cse5 v_b_193_2) (<= .cse8 v_b_193_2) (<= 0 v_v_1930_2) (<= .cse17 v_b_193_2) (<= .cse0 v_b_186_2) (or (= (select |c_#memory_int| v_idx_278) v_v_1933_2) (<= v_b_186_2 v_idx_278) (< v_idx_278 v_b_185_2)) (<= .cse10 v_b_189_2) (<= (+ v_b_189_2 3) v_b_195_2) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_2) (<= .cse18 v_b_187_2) (<= .cse18 v_b_188_2) (<= .cse16 v_b_192_2) (<= .cse19 v_b_188_2) (or (<= v_b_185_2 v_idx_277) (< v_idx_277 v_b_184_2) (= 0 (select |c_#memory_int| v_idx_277))) (<= .cse20 v_b_193_2) (<= .cse14 v_b_192_2) (<= (+ v_b_184_2 6) v_b_195_2) (<= .cse21 v_b_192_2) (<= .cse22 v_b_189_2) (<= .cse7 v_b_185_2) (<= .cse23 v_b_194_2) (<= .cse24 v_b_192_2) (<= (+ v_b_192_2 2) v_b_195_2) (<= v_b_189_2 v_b_190_2) (or (<= v_b_187_2 v_idx_279) (< v_idx_279 v_b_186_2) (= (select |c_#memory_int| v_idx_279) 0)) (<= .cse22 v_b_190_2) (<= v_b_187_2 v_b_188_2) (<= .cse25 v_b_187_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_274) (= (select |c_#memory_int| v_idx_274) v_v_1929_2)) (or (= (select |c_#memory_int| v_idx_282) v_v_1937_2) (< v_idx_282 v_b_189_2) (<= v_b_190_2 v_idx_282)) (<= (+ v_b_191_2 2) v_b_195_2) (<= .cse2 v_b_194_2) (or (= (select |c_#memory_int| v_idx_284) v_v_1939_2) (< v_idx_284 v_b_191_2) (<= v_b_192_2 v_idx_284)) (<= (+ v_b_188_2 4) v_b_195_2) (<= .cse26 v_b_194_2) (<= .cse27 v_b_191_2) (<= .cse15 v_b_189_2) (<= (+ v_b_193_2 1) v_b_195_2) (<= .cse28 v_b_187_2) (<= v_b_187_2 .cse19) (or (= 0 (select |c_#memory_int| v_idx_287)) (< v_idx_287 v_b_194_2) (<= v_b_195_2 v_idx_287)) (<= .cse17 v_b_194_2) (<= .cse9 v_b_192_2) (or (< v_idx_288 v_b_195_2) (= (select |c_#memory_int| v_idx_288) v_v_1943_2)) (<= .cse28 v_b_188_2) (<= .cse11 v_b_193_2) (<= v_b_193_2 v_b_194_2) (<= (+ v_b_186_2 5) v_b_195_2) (<= v_b_189_2 .cse29) (<= .cse19 v_b_187_2) (<= (+ v_b_187_2 4) v_b_195_2) (<= v_b_195_2 .cse30) (<= .cse31 v_b_193_2) (<= v_b_191_2 v_b_192_2) (<= .cse23 v_b_193_2) (<= v_b_191_2 .cse12) (<= .cse31 v_b_194_2) (or (<= v_b_193_2 v_idx_285) (= 0 (select |c_#memory_int| v_idx_285)) (< v_idx_285 v_b_192_2)) (or (< v_idx_286 v_b_193_2) (= (select |c_#memory_int| v_idx_286) v_v_1941_2) (<= v_b_194_2 v_idx_286)) (<= .cse30 v_b_195_2) (<= .cse12 v_b_191_2) (<= .cse26 v_b_193_2) (<= .cse6 v_b_191_2) (<= .cse25 v_b_188_2) (<= .cse20 v_b_194_2) (<= v_b_193_2 .cse2) (<= .cse1 v_b_194_2) (<= v_b_185_2 v_b_186_2) (<= .cse29 v_b_190_2) (or (< v_idx_283 v_b_190_2) (= 0 (select |c_#memory_int| v_idx_283)) (<= v_b_191_2 v_idx_283)) (<= .cse21 v_b_191_2) (<= .cse29 v_b_189_2) (<= .cse4 v_b_189_2) (<= .cse27 v_b_192_2) (<= .cse24 v_b_191_2) (<= .cse0 v_b_185_2))))) is different from false [2019-01-11 11:46:16,813 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:46:16,813 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:46:16,814 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:46:16,814 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:46:16,814 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:46:16,814 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:46:16,814 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:46:16,814 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=2, Unknown=3, NotChecked=2, Total=12 [2019-01-11 11:46:16,815 INFO L87 Difference]: Start difference. First operand 18 states and 38 transitions. Second operand 4 states. [2019-01-11 11:46:19,549 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_280 Int) (v_idx_278 Int) (v_idx_279 Int) (v_idx_283 Int) (v_idx_284 Int) (v_idx_281 Int) (v_idx_282 Int) (v_idx_287 Int) (v_idx_276 Int) (v_idx_288 Int) (v_idx_277 Int) (v_idx_285 Int) (v_idx_274 Int) (v_idx_286 Int) (v_idx_275 Int)) (exists ((v_v_1929_2 Int) (v_v_1937_2 Int) (v_v_1939_2 Int) (v_b_194_2 Int) (v_b_193_2 Int) (v_v_1933_2 Int) (v_v_1943_2 Int) (v_b_184_2 Int) (v_b_185_2 Int) (v_b_195_2 Int) (v_v_1935_2 Int) (v_b_186_2 Int) (v_b_187_2 Int) (v_b_188_2 Int) (v_v_1930_2 Int) (v_v_1931_2 Int) (v_b_189_2 Int) (v_v_1941_2 Int) (v_b_190_2 Int) (v_b_192_2 Int) (v_b_191_2 Int)) (let ((.cse13 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse5 (+ v_b_185_2 4)) (.cse8 (+ c_ULTIMATE.start_main_p1 6)) (.cse10 (+ v_b_187_2 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 3)) (.cse16 (+ v_b_185_2 3)) (.cse14 (+ v_b_188_2 2)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse22 (+ v_b_184_2 3)) (.cse15 (+ v_b_186_2 2)) (.cse17 (+ v_b_187_2 3)) (.cse9 (+ v_b_184_2 4)) (.cse28 (+ v_b_185_2 1)) (.cse11 (+ v_b_190_2 2)) (.cse19 (+ v_b_186_2 1)) (.cse23 (+ v_b_184_2 5)) (.cse31 (+ v_b_189_2 2)) (.cse30 (+ v_b_194_2 1)) (.cse12 (+ v_b_190_2 1)) (.cse26 (+ v_b_186_2 4)) (.cse6 (+ v_b_187_2 2)) (.cse25 (+ v_b_184_2 2)) (.cse20 (+ v_b_188_2 3)) (.cse2 (+ v_b_192_2 1)) (.cse1 (+ v_b_191_2 1)) (.cse21 (+ v_b_186_2 3)) (.cse29 (+ v_b_188_2 1)) (.cse4 (+ v_b_185_2 2)) (.cse27 (+ c_ULTIMATE.start_main_p1 5)) (.cse24 (+ v_b_189_2 1)) (.cse0 (+ v_b_184_2 1))) (and (<= v_b_185_2 .cse0) (<= .cse1 v_b_193_2) (<= .cse2 v_b_193_2) (<= .cse3 v_b_189_2) (or (<= v_b_189_2 v_idx_281) (< v_idx_281 v_b_188_2) (= 0 (select |c_#memory_int| v_idx_281))) (<= .cse4 v_b_190_2) (<= .cse5 v_b_194_2) (<= 0 (* 2 v_v_1930_2)) (<= .cse6 v_b_192_2) (<= .cse7 v_b_186_2) (<= .cse8 v_b_194_2) (<= .cse9 v_b_191_2) (<= .cse10 v_b_190_2) (<= .cse11 v_b_194_2) (<= .cse12 v_b_192_2) (or (< v_idx_275 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_275) v_v_1930_2) (<= .cse13 v_idx_275)) (<= .cse13 v_b_184_2) (<= .cse14 v_b_191_2) (<= (+ v_b_185_2 5) v_b_195_2) (<= .cse15 v_b_190_2) (<= .cse16 v_b_191_2) (or (= (select |c_#memory_int| v_idx_276) v_v_1931_2) (<= v_b_184_2 v_idx_276) (< v_idx_276 .cse13)) (<= .cse3 v_b_190_2) (or (< v_idx_280 v_b_187_2) (<= v_b_188_2 v_idx_280) (= (select |c_#memory_int| v_idx_280) v_v_1935_2)) (<= (+ v_b_190_2 3) v_b_195_2) (<= .cse5 v_b_193_2) (<= .cse8 v_b_193_2) (<= 0 v_v_1930_2) (<= .cse17 v_b_193_2) (<= .cse0 v_b_186_2) (or (= (select |c_#memory_int| v_idx_278) v_v_1933_2) (<= v_b_186_2 v_idx_278) (< v_idx_278 v_b_185_2)) (<= .cse10 v_b_189_2) (<= (+ v_b_189_2 3) v_b_195_2) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_2) (<= .cse18 v_b_187_2) (<= .cse18 v_b_188_2) (<= .cse16 v_b_192_2) (<= .cse19 v_b_188_2) (or (<= v_b_185_2 v_idx_277) (< v_idx_277 v_b_184_2) (= 0 (select |c_#memory_int| v_idx_277))) (<= .cse20 v_b_193_2) (<= .cse14 v_b_192_2) (<= (+ v_b_184_2 6) v_b_195_2) (<= .cse21 v_b_192_2) (<= .cse22 v_b_189_2) (<= .cse7 v_b_185_2) (<= .cse23 v_b_194_2) (<= .cse24 v_b_192_2) (<= (+ v_b_192_2 2) v_b_195_2) (<= v_b_189_2 v_b_190_2) (or (<= v_b_187_2 v_idx_279) (< v_idx_279 v_b_186_2) (= (select |c_#memory_int| v_idx_279) 0)) (<= .cse22 v_b_190_2) (<= v_b_187_2 v_b_188_2) (<= .cse25 v_b_187_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_274) (= (select |c_#memory_int| v_idx_274) v_v_1929_2)) (or (= (select |c_#memory_int| v_idx_282) v_v_1937_2) (< v_idx_282 v_b_189_2) (<= v_b_190_2 v_idx_282)) (<= (+ v_b_191_2 2) v_b_195_2) (<= .cse2 v_b_194_2) (or (= (select |c_#memory_int| v_idx_284) v_v_1939_2) (< v_idx_284 v_b_191_2) (<= v_b_192_2 v_idx_284)) (<= (+ v_b_188_2 4) v_b_195_2) (<= .cse26 v_b_194_2) (<= .cse27 v_b_191_2) (<= .cse15 v_b_189_2) (<= (+ v_b_193_2 1) v_b_195_2) (<= .cse28 v_b_187_2) (<= v_b_187_2 .cse19) (or (= 0 (select |c_#memory_int| v_idx_287)) (< v_idx_287 v_b_194_2) (<= v_b_195_2 v_idx_287)) (<= .cse17 v_b_194_2) (<= .cse9 v_b_192_2) (or (< v_idx_288 v_b_195_2) (= (select |c_#memory_int| v_idx_288) v_v_1943_2)) (<= .cse28 v_b_188_2) (<= .cse11 v_b_193_2) (<= v_b_193_2 v_b_194_2) (<= (+ v_b_186_2 5) v_b_195_2) (<= v_b_189_2 .cse29) (<= .cse19 v_b_187_2) (<= (+ v_b_187_2 4) v_b_195_2) (<= v_b_195_2 .cse30) (<= .cse31 v_b_193_2) (<= v_b_191_2 v_b_192_2) (<= .cse23 v_b_193_2) (<= v_b_191_2 .cse12) (<= .cse31 v_b_194_2) (or (<= v_b_193_2 v_idx_285) (= 0 (select |c_#memory_int| v_idx_285)) (< v_idx_285 v_b_192_2)) (or (< v_idx_286 v_b_193_2) (= (select |c_#memory_int| v_idx_286) v_v_1941_2) (<= v_b_194_2 v_idx_286)) (<= .cse30 v_b_195_2) (<= .cse12 v_b_191_2) (<= .cse26 v_b_193_2) (<= .cse6 v_b_191_2) (<= .cse25 v_b_188_2) (<= .cse20 v_b_194_2) (<= v_b_193_2 .cse2) (<= .cse1 v_b_194_2) (<= v_b_185_2 v_b_186_2) (<= .cse29 v_b_190_2) (or (< v_idx_283 v_b_190_2) (= 0 (select |c_#memory_int| v_idx_283)) (<= v_b_191_2 v_idx_283)) (<= .cse21 v_b_191_2) (<= .cse29 v_b_189_2) (<= .cse4 v_b_189_2) (<= .cse27 v_b_192_2) (<= .cse24 v_b_191_2) (<= .cse0 v_b_185_2))))) (forall ((v_idx_269 Int) (v_idx_259 Int) (v_idx_267 Int) (v_idx_268 Int) (v_idx_261 Int) (v_idx_272 Int) (v_idx_262 Int) (v_idx_273 Int) (v_idx_270 Int) (v_idx_260 Int) (v_idx_271 Int) (v_idx_265 Int) (v_idx_266 Int) (v_idx_263 Int) (v_idx_264 Int)) (exists ((v_v_1929_2 Int) (v_v_1937_2 Int) (v_v_1939_2 Int) (v_b_194_2 Int) (v_v_1933_2 Int) (v_b_193_2 Int) (v_v_1943_2 Int) (v_b_184_2 Int) (v_b_185_2 Int) (v_b_195_2 Int) (v_v_1935_2 Int) (v_b_186_2 Int) (v_b_187_2 Int) (v_v_1930_2 Int) (v_b_188_2 Int) (v_b_189_2 Int) (v_v_1941_2 Int) (v_v_1931_2 Int) (v_b_190_2 Int) (v_b_192_2 Int) (v_b_191_2 Int)) (let ((.cse35 (+ c_ULTIMATE.start_main_p1 4)) (.cse37 (+ v_b_185_2 4)) (.cse40 (+ c_ULTIMATE.start_main_p1 6)) (.cse42 (+ v_b_187_2 1)) (.cse50 (+ c_ULTIMATE.start_main_p1 3)) (.cse48 (+ v_b_185_2 3)) (.cse46 (+ v_b_188_2 2)) (.cse39 (+ c_ULTIMATE.start_main_p1 2)) (.cse54 (+ v_b_184_2 3)) (.cse47 (+ v_b_186_2 2)) (.cse49 (+ v_b_187_2 3)) (.cse45 (+ c_ULTIMATE.start_main_p1 1)) (.cse41 (+ v_b_184_2 4)) (.cse60 (+ v_b_185_2 1)) (.cse43 (+ v_b_190_2 2)) (.cse51 (+ v_b_186_2 1)) (.cse55 (+ v_b_184_2 5)) (.cse63 (+ v_b_189_2 2)) (.cse62 (+ v_b_194_2 1)) (.cse44 (+ v_b_190_2 1)) (.cse58 (+ v_b_186_2 4)) (.cse38 (+ v_b_187_2 2)) (.cse57 (+ v_b_184_2 2)) (.cse52 (+ v_b_188_2 3)) (.cse34 (+ v_b_192_2 1)) (.cse33 (+ v_b_191_2 1)) (.cse53 (+ v_b_186_2 3)) (.cse61 (+ v_b_188_2 1)) (.cse36 (+ v_b_185_2 2)) (.cse59 (+ c_ULTIMATE.start_main_p1 5)) (.cse56 (+ v_b_189_2 1)) (.cse32 (+ v_b_184_2 1))) (and (<= v_b_185_2 .cse32) (<= .cse33 v_b_193_2) (<= .cse34 v_b_193_2) (<= .cse35 v_b_189_2) (<= .cse36 v_b_190_2) (or (< v_idx_270 v_b_192_2) (= 0 (select |c_#memory_int| v_idx_270)) (<= v_b_193_2 v_idx_270)) (or (= (select |c_#memory_int| v_idx_263) v_v_1933_2) (<= v_b_186_2 v_idx_263) (< v_idx_263 v_b_185_2)) (<= .cse37 v_b_194_2) (<= 0 (* 2 v_v_1930_2)) (<= .cse38 v_b_192_2) (<= .cse39 v_b_186_2) (<= .cse40 v_b_194_2) (<= .cse41 v_b_191_2) (<= .cse42 v_b_190_2) (<= .cse43 v_b_194_2) (<= .cse44 v_b_192_2) (<= .cse45 v_b_184_2) (<= .cse46 v_b_191_2) (<= (+ v_b_185_2 5) v_b_195_2) (<= .cse47 v_b_190_2) (<= .cse48 v_b_191_2) (or (= (select |c_#memory_int| v_idx_260) v_v_1930_2) (< v_idx_260 c_ULTIMATE.start_main_p1) (<= .cse45 v_idx_260)) (or (< v_idx_264 v_b_186_2) (= 0 (select |c_#memory_int| v_idx_264)) (<= v_b_187_2 v_idx_264)) (<= .cse35 v_b_190_2) (<= (+ v_b_190_2 3) v_b_195_2) (<= .cse37 v_b_193_2) (<= .cse40 v_b_193_2) (<= 0 v_v_1930_2) (<= .cse49 v_b_193_2) (<= .cse32 v_b_186_2) (or (= 0 (select |c_#memory_int| v_idx_262)) (< v_idx_262 v_b_184_2) (<= v_b_185_2 v_idx_262)) (<= .cse42 v_b_189_2) (<= (+ v_b_189_2 3) v_b_195_2) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_2) (or (< v_idx_266 v_b_188_2) (<= v_b_189_2 v_idx_266) (= 0 (select |c_#memory_int| v_idx_266))) (<= .cse50 v_b_187_2) (<= .cse50 v_b_188_2) (<= .cse48 v_b_192_2) (<= .cse51 v_b_188_2) (<= .cse52 v_b_193_2) (or (< v_idx_271 v_b_193_2) (<= v_b_194_2 v_idx_271) (= (select |c_#memory_int| v_idx_271) v_v_1941_2)) (<= .cse46 v_b_192_2) (<= (+ v_b_184_2 6) v_b_195_2) (<= .cse53 v_b_192_2) (or (<= v_b_192_2 v_idx_269) (= v_v_1939_2 (select |c_#memory_int| v_idx_269)) (< v_idx_269 v_b_191_2)) (or (< v_idx_265 v_b_187_2) (<= v_b_188_2 v_idx_265) (= (select |c_#memory_int| v_idx_265) v_v_1935_2)) (<= .cse54 v_b_189_2) (<= .cse39 v_b_185_2) (<= .cse55 v_b_194_2) (<= .cse56 v_b_192_2) (<= (+ v_b_192_2 2) v_b_195_2) (<= v_b_189_2 v_b_190_2) (<= .cse54 v_b_190_2) (<= v_b_187_2 v_b_188_2) (<= .cse57 v_b_187_2) (<= (+ v_b_191_2 2) v_b_195_2) (<= .cse34 v_b_194_2) (<= (+ v_b_188_2 4) v_b_195_2) (<= .cse58 v_b_194_2) (<= .cse59 v_b_191_2) (<= .cse47 v_b_189_2) (or (< v_idx_268 v_b_190_2) (= 0 (select |c_#memory_int| v_idx_268)) (<= v_b_191_2 v_idx_268)) (<= (+ v_b_193_2 1) v_b_195_2) (<= .cse60 v_b_187_2) (<= v_b_187_2 .cse51) (or (= (select |c_#memory_int| v_idx_259) v_v_1929_2) (<= c_ULTIMATE.start_main_p1 v_idx_259)) (<= .cse49 v_b_194_2) (or (< v_idx_261 .cse45) (= (select |c_#memory_int| v_idx_261) v_v_1931_2) (<= v_b_184_2 v_idx_261)) (<= .cse41 v_b_192_2) (<= .cse60 v_b_188_2) (<= .cse43 v_b_193_2) (<= v_b_193_2 v_b_194_2) (<= (+ v_b_186_2 5) v_b_195_2) (<= v_b_189_2 .cse61) (<= .cse51 v_b_187_2) (<= (+ v_b_187_2 4) v_b_195_2) (<= v_b_195_2 .cse62) (<= .cse63 v_b_193_2) (<= v_b_191_2 v_b_192_2) (<= .cse55 v_b_193_2) (<= v_b_191_2 .cse44) (<= .cse63 v_b_194_2) (or (< v_idx_272 v_b_194_2) (<= v_b_195_2 v_idx_272) (= (select |c_#memory_int| v_idx_272) 0)) (<= .cse62 v_b_195_2) (<= .cse44 v_b_191_2) (<= .cse58 v_b_193_2) (or (= (select |c_#memory_int| v_idx_267) v_v_1937_2) (<= v_b_190_2 v_idx_267) (< v_idx_267 v_b_189_2)) (<= .cse38 v_b_191_2) (<= .cse57 v_b_188_2) (<= .cse52 v_b_194_2) (<= v_b_193_2 .cse34) (<= .cse33 v_b_194_2) (<= v_b_185_2 v_b_186_2) (or (= (select |c_#memory_int| v_idx_273) v_v_1943_2) (< v_idx_273 v_b_195_2)) (<= .cse61 v_b_190_2) (<= .cse53 v_b_191_2) (<= .cse61 v_b_189_2) (<= .cse36 v_b_189_2) (<= .cse59 v_b_192_2) (<= .cse56 v_b_191_2) (<= .cse32 v_b_185_2)))))) is different from false [2019-01-11 11:46:21,588 WARN L860 $PredicateComparison]: unable to prove that (and (forall ((v_idx_280 Int) (v_idx_278 Int) (v_idx_279 Int) (v_idx_283 Int) (v_idx_284 Int) (v_idx_281 Int) (v_idx_282 Int) (v_idx_287 Int) (v_idx_276 Int) (v_idx_288 Int) (v_idx_277 Int) (v_idx_285 Int) (v_idx_274 Int) (v_idx_286 Int) (v_idx_275 Int)) (exists ((v_v_1929_2 Int) (v_v_1937_2 Int) (v_v_1939_2 Int) (v_b_194_2 Int) (v_b_193_2 Int) (v_v_1933_2 Int) (v_v_1943_2 Int) (v_b_184_2 Int) (v_b_185_2 Int) (v_b_195_2 Int) (v_v_1935_2 Int) (v_b_186_2 Int) (v_b_187_2 Int) (v_b_188_2 Int) (v_v_1930_2 Int) (v_v_1931_2 Int) (v_b_189_2 Int) (v_v_1941_2 Int) (v_b_190_2 Int) (v_b_192_2 Int) (v_b_191_2 Int)) (let ((.cse13 (+ c_ULTIMATE.start_main_p1 1)) (.cse3 (+ c_ULTIMATE.start_main_p1 4)) (.cse5 (+ v_b_185_2 4)) (.cse8 (+ c_ULTIMATE.start_main_p1 6)) (.cse10 (+ v_b_187_2 1)) (.cse18 (+ c_ULTIMATE.start_main_p1 3)) (.cse16 (+ v_b_185_2 3)) (.cse14 (+ v_b_188_2 2)) (.cse7 (+ c_ULTIMATE.start_main_p1 2)) (.cse22 (+ v_b_184_2 3)) (.cse15 (+ v_b_186_2 2)) (.cse17 (+ v_b_187_2 3)) (.cse9 (+ v_b_184_2 4)) (.cse28 (+ v_b_185_2 1)) (.cse11 (+ v_b_190_2 2)) (.cse19 (+ v_b_186_2 1)) (.cse23 (+ v_b_184_2 5)) (.cse31 (+ v_b_189_2 2)) (.cse30 (+ v_b_194_2 1)) (.cse12 (+ v_b_190_2 1)) (.cse26 (+ v_b_186_2 4)) (.cse6 (+ v_b_187_2 2)) (.cse25 (+ v_b_184_2 2)) (.cse20 (+ v_b_188_2 3)) (.cse2 (+ v_b_192_2 1)) (.cse1 (+ v_b_191_2 1)) (.cse21 (+ v_b_186_2 3)) (.cse29 (+ v_b_188_2 1)) (.cse4 (+ v_b_185_2 2)) (.cse27 (+ c_ULTIMATE.start_main_p1 5)) (.cse24 (+ v_b_189_2 1)) (.cse0 (+ v_b_184_2 1))) (and (<= v_b_185_2 .cse0) (<= .cse1 v_b_193_2) (<= .cse2 v_b_193_2) (<= .cse3 v_b_189_2) (or (<= v_b_189_2 v_idx_281) (< v_idx_281 v_b_188_2) (= 0 (select |c_#memory_int| v_idx_281))) (<= .cse4 v_b_190_2) (<= .cse5 v_b_194_2) (<= 0 (* 2 v_v_1930_2)) (<= .cse6 v_b_192_2) (<= .cse7 v_b_186_2) (<= .cse8 v_b_194_2) (<= .cse9 v_b_191_2) (<= .cse10 v_b_190_2) (<= .cse11 v_b_194_2) (<= .cse12 v_b_192_2) (or (< v_idx_275 c_ULTIMATE.start_main_p1) (= (select |c_#memory_int| v_idx_275) v_v_1930_2) (<= .cse13 v_idx_275)) (<= .cse13 v_b_184_2) (<= .cse14 v_b_191_2) (<= (+ v_b_185_2 5) v_b_195_2) (<= .cse15 v_b_190_2) (<= .cse16 v_b_191_2) (or (= (select |c_#memory_int| v_idx_276) v_v_1931_2) (<= v_b_184_2 v_idx_276) (< v_idx_276 .cse13)) (<= .cse3 v_b_190_2) (or (< v_idx_280 v_b_187_2) (<= v_b_188_2 v_idx_280) (= (select |c_#memory_int| v_idx_280) v_v_1935_2)) (<= (+ v_b_190_2 3) v_b_195_2) (<= .cse5 v_b_193_2) (<= .cse8 v_b_193_2) (<= 0 v_v_1930_2) (<= .cse17 v_b_193_2) (<= .cse0 v_b_186_2) (or (= (select |c_#memory_int| v_idx_278) v_v_1933_2) (<= v_b_186_2 v_idx_278) (< v_idx_278 v_b_185_2)) (<= .cse10 v_b_189_2) (<= (+ v_b_189_2 3) v_b_195_2) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_2) (<= .cse18 v_b_187_2) (<= .cse18 v_b_188_2) (<= .cse16 v_b_192_2) (<= .cse19 v_b_188_2) (or (<= v_b_185_2 v_idx_277) (< v_idx_277 v_b_184_2) (= 0 (select |c_#memory_int| v_idx_277))) (<= .cse20 v_b_193_2) (<= .cse14 v_b_192_2) (<= (+ v_b_184_2 6) v_b_195_2) (<= .cse21 v_b_192_2) (<= .cse22 v_b_189_2) (<= .cse7 v_b_185_2) (<= .cse23 v_b_194_2) (<= .cse24 v_b_192_2) (<= (+ v_b_192_2 2) v_b_195_2) (<= v_b_189_2 v_b_190_2) (or (<= v_b_187_2 v_idx_279) (< v_idx_279 v_b_186_2) (= (select |c_#memory_int| v_idx_279) 0)) (<= .cse22 v_b_190_2) (<= v_b_187_2 v_b_188_2) (<= .cse25 v_b_187_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_274) (= (select |c_#memory_int| v_idx_274) v_v_1929_2)) (or (= (select |c_#memory_int| v_idx_282) v_v_1937_2) (< v_idx_282 v_b_189_2) (<= v_b_190_2 v_idx_282)) (<= (+ v_b_191_2 2) v_b_195_2) (<= .cse2 v_b_194_2) (or (= (select |c_#memory_int| v_idx_284) v_v_1939_2) (< v_idx_284 v_b_191_2) (<= v_b_192_2 v_idx_284)) (<= (+ v_b_188_2 4) v_b_195_2) (<= .cse26 v_b_194_2) (<= .cse27 v_b_191_2) (<= .cse15 v_b_189_2) (<= (+ v_b_193_2 1) v_b_195_2) (<= .cse28 v_b_187_2) (<= v_b_187_2 .cse19) (or (= 0 (select |c_#memory_int| v_idx_287)) (< v_idx_287 v_b_194_2) (<= v_b_195_2 v_idx_287)) (<= .cse17 v_b_194_2) (<= .cse9 v_b_192_2) (or (< v_idx_288 v_b_195_2) (= (select |c_#memory_int| v_idx_288) v_v_1943_2)) (<= .cse28 v_b_188_2) (<= .cse11 v_b_193_2) (<= v_b_193_2 v_b_194_2) (<= (+ v_b_186_2 5) v_b_195_2) (<= v_b_189_2 .cse29) (<= .cse19 v_b_187_2) (<= (+ v_b_187_2 4) v_b_195_2) (<= v_b_195_2 .cse30) (<= .cse31 v_b_193_2) (<= v_b_191_2 v_b_192_2) (<= .cse23 v_b_193_2) (<= v_b_191_2 .cse12) (<= .cse31 v_b_194_2) (or (<= v_b_193_2 v_idx_285) (= 0 (select |c_#memory_int| v_idx_285)) (< v_idx_285 v_b_192_2)) (or (< v_idx_286 v_b_193_2) (= (select |c_#memory_int| v_idx_286) v_v_1941_2) (<= v_b_194_2 v_idx_286)) (<= .cse30 v_b_195_2) (<= .cse12 v_b_191_2) (<= .cse26 v_b_193_2) (<= .cse6 v_b_191_2) (<= .cse25 v_b_188_2) (<= .cse20 v_b_194_2) (<= v_b_193_2 .cse2) (<= .cse1 v_b_194_2) (<= v_b_185_2 v_b_186_2) (<= .cse29 v_b_190_2) (or (< v_idx_283 v_b_190_2) (= 0 (select |c_#memory_int| v_idx_283)) (<= v_b_191_2 v_idx_283)) (<= .cse21 v_b_191_2) (<= .cse29 v_b_189_2) (<= .cse4 v_b_189_2) (<= .cse27 v_b_192_2) (<= .cse24 v_b_191_2) (<= .cse0 v_b_185_2))))) (forall ((v_idx_269 Int) (v_idx_259 Int) (v_idx_267 Int) (v_idx_268 Int) (v_idx_261 Int) (v_idx_272 Int) (v_idx_262 Int) (v_idx_273 Int) (v_idx_270 Int) (v_idx_260 Int) (v_idx_271 Int) (v_idx_265 Int) (v_idx_266 Int) (v_idx_263 Int) (v_idx_264 Int)) (exists ((v_v_1929_2 Int) (v_v_1937_2 Int) (v_v_1939_2 Int) (v_b_194_2 Int) (v_v_1933_2 Int) (v_b_193_2 Int) (v_v_1943_2 Int) (v_b_184_2 Int) (v_b_185_2 Int) (v_b_195_2 Int) (v_v_1935_2 Int) (v_b_186_2 Int) (v_b_187_2 Int) (v_v_1930_2 Int) (v_b_188_2 Int) (v_b_189_2 Int) (v_v_1941_2 Int) (v_v_1931_2 Int) (v_b_190_2 Int) (v_b_192_2 Int) (v_b_191_2 Int)) (let ((.cse35 (+ c_ULTIMATE.start_main_p1 4)) (.cse37 (+ v_b_185_2 4)) (.cse40 (+ c_ULTIMATE.start_main_p1 6)) (.cse42 (+ v_b_187_2 1)) (.cse50 (+ c_ULTIMATE.start_main_p1 3)) (.cse48 (+ v_b_185_2 3)) (.cse46 (+ v_b_188_2 2)) (.cse39 (+ c_ULTIMATE.start_main_p1 2)) (.cse54 (+ v_b_184_2 3)) (.cse47 (+ v_b_186_2 2)) (.cse49 (+ v_b_187_2 3)) (.cse45 (+ c_ULTIMATE.start_main_p1 1)) (.cse41 (+ v_b_184_2 4)) (.cse60 (+ v_b_185_2 1)) (.cse43 (+ v_b_190_2 2)) (.cse51 (+ v_b_186_2 1)) (.cse55 (+ v_b_184_2 5)) (.cse63 (+ v_b_189_2 2)) (.cse62 (+ v_b_194_2 1)) (.cse44 (+ v_b_190_2 1)) (.cse58 (+ v_b_186_2 4)) (.cse38 (+ v_b_187_2 2)) (.cse57 (+ v_b_184_2 2)) (.cse52 (+ v_b_188_2 3)) (.cse34 (+ v_b_192_2 1)) (.cse33 (+ v_b_191_2 1)) (.cse53 (+ v_b_186_2 3)) (.cse61 (+ v_b_188_2 1)) (.cse36 (+ v_b_185_2 2)) (.cse59 (+ c_ULTIMATE.start_main_p1 5)) (.cse56 (+ v_b_189_2 1)) (.cse32 (+ v_b_184_2 1))) (and (<= v_b_185_2 .cse32) (<= .cse33 v_b_193_2) (<= .cse34 v_b_193_2) (<= .cse35 v_b_189_2) (<= .cse36 v_b_190_2) (or (< v_idx_270 v_b_192_2) (= 0 (select |c_#memory_int| v_idx_270)) (<= v_b_193_2 v_idx_270)) (or (= (select |c_#memory_int| v_idx_263) v_v_1933_2) (<= v_b_186_2 v_idx_263) (< v_idx_263 v_b_185_2)) (<= .cse37 v_b_194_2) (<= 0 (* 2 v_v_1930_2)) (<= .cse38 v_b_192_2) (<= .cse39 v_b_186_2) (<= .cse40 v_b_194_2) (<= .cse41 v_b_191_2) (<= .cse42 v_b_190_2) (<= .cse43 v_b_194_2) (<= .cse44 v_b_192_2) (<= .cse45 v_b_184_2) (<= .cse46 v_b_191_2) (<= (+ v_b_185_2 5) v_b_195_2) (<= .cse47 v_b_190_2) (<= .cse48 v_b_191_2) (or (= (select |c_#memory_int| v_idx_260) v_v_1930_2) (< v_idx_260 c_ULTIMATE.start_main_p1) (<= .cse45 v_idx_260)) (or (< v_idx_264 v_b_186_2) (= 0 (select |c_#memory_int| v_idx_264)) (<= v_b_187_2 v_idx_264)) (<= .cse35 v_b_190_2) (<= (+ v_b_190_2 3) v_b_195_2) (<= .cse37 v_b_193_2) (<= .cse40 v_b_193_2) (<= 0 v_v_1930_2) (<= .cse49 v_b_193_2) (<= .cse32 v_b_186_2) (or (= 0 (select |c_#memory_int| v_idx_262)) (< v_idx_262 v_b_184_2) (<= v_b_185_2 v_idx_262)) (<= .cse42 v_b_189_2) (<= (+ v_b_189_2 3) v_b_195_2) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_195_2) (or (< v_idx_266 v_b_188_2) (<= v_b_189_2 v_idx_266) (= 0 (select |c_#memory_int| v_idx_266))) (<= .cse50 v_b_187_2) (<= .cse50 v_b_188_2) (<= .cse48 v_b_192_2) (<= .cse51 v_b_188_2) (<= .cse52 v_b_193_2) (or (< v_idx_271 v_b_193_2) (<= v_b_194_2 v_idx_271) (= (select |c_#memory_int| v_idx_271) v_v_1941_2)) (<= .cse46 v_b_192_2) (<= (+ v_b_184_2 6) v_b_195_2) (<= .cse53 v_b_192_2) (or (<= v_b_192_2 v_idx_269) (= v_v_1939_2 (select |c_#memory_int| v_idx_269)) (< v_idx_269 v_b_191_2)) (or (< v_idx_265 v_b_187_2) (<= v_b_188_2 v_idx_265) (= (select |c_#memory_int| v_idx_265) v_v_1935_2)) (<= .cse54 v_b_189_2) (<= .cse39 v_b_185_2) (<= .cse55 v_b_194_2) (<= .cse56 v_b_192_2) (<= (+ v_b_192_2 2) v_b_195_2) (<= v_b_189_2 v_b_190_2) (<= .cse54 v_b_190_2) (<= v_b_187_2 v_b_188_2) (<= .cse57 v_b_187_2) (<= (+ v_b_191_2 2) v_b_195_2) (<= .cse34 v_b_194_2) (<= (+ v_b_188_2 4) v_b_195_2) (<= .cse58 v_b_194_2) (<= .cse59 v_b_191_2) (<= .cse47 v_b_189_2) (or (< v_idx_268 v_b_190_2) (= 0 (select |c_#memory_int| v_idx_268)) (<= v_b_191_2 v_idx_268)) (<= (+ v_b_193_2 1) v_b_195_2) (<= .cse60 v_b_187_2) (<= v_b_187_2 .cse51) (or (= (select |c_#memory_int| v_idx_259) v_v_1929_2) (<= c_ULTIMATE.start_main_p1 v_idx_259)) (<= .cse49 v_b_194_2) (or (< v_idx_261 .cse45) (= (select |c_#memory_int| v_idx_261) v_v_1931_2) (<= v_b_184_2 v_idx_261)) (<= .cse41 v_b_192_2) (<= .cse60 v_b_188_2) (<= .cse43 v_b_193_2) (<= v_b_193_2 v_b_194_2) (<= (+ v_b_186_2 5) v_b_195_2) (<= v_b_189_2 .cse61) (<= .cse51 v_b_187_2) (<= (+ v_b_187_2 4) v_b_195_2) (<= v_b_195_2 .cse62) (<= .cse63 v_b_193_2) (<= v_b_191_2 v_b_192_2) (<= .cse55 v_b_193_2) (<= v_b_191_2 .cse44) (<= .cse63 v_b_194_2) (or (< v_idx_272 v_b_194_2) (<= v_b_195_2 v_idx_272) (= (select |c_#memory_int| v_idx_272) 0)) (<= .cse62 v_b_195_2) (<= .cse44 v_b_191_2) (<= .cse58 v_b_193_2) (or (= (select |c_#memory_int| v_idx_267) v_v_1937_2) (<= v_b_190_2 v_idx_267) (< v_idx_267 v_b_189_2)) (<= .cse38 v_b_191_2) (<= .cse57 v_b_188_2) (<= .cse52 v_b_194_2) (<= v_b_193_2 .cse34) (<= .cse33 v_b_194_2) (<= v_b_185_2 v_b_186_2) (or (= (select |c_#memory_int| v_idx_273) v_v_1943_2) (< v_idx_273 v_b_195_2)) (<= .cse61 v_b_190_2) (<= .cse53 v_b_191_2) (<= .cse61 v_b_189_2) (<= .cse36 v_b_189_2) (<= .cse59 v_b_192_2) (<= .cse56 v_b_191_2) (<= .cse32 v_b_185_2)))))) is different from true [2019-01-11 11:46:59,894 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:46:59,894 INFO L93 Difference]: Finished difference Result 20 states and 47 transitions. [2019-01-11 11:46:59,894 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:46:59,894 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:46:59,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:46:59,895 INFO L225 Difference]: With dead ends: 20 [2019-01-11 11:46:59,895 INFO L226 Difference]: Without dead ends: 19 [2019-01-11 11:46:59,896 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 12.4s TimeCoverageRelationStatistics Valid=7, Invalid=2, Unknown=5, NotChecked=6, Total=20 [2019-01-11 11:46:59,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2019-01-11 11:46:59,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 18. [2019-01-11 11:46:59,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2019-01-11 11:46:59,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 38 transitions. [2019-01-11 11:46:59,908 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 38 transitions. Word has length 3 [2019-01-11 11:46:59,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:46:59,908 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 38 transitions. [2019-01-11 11:46:59,908 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:46:59,908 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 38 transitions. [2019-01-11 11:46:59,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:46:59,909 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:46:59,909 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:46:59,909 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:46:59,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:46:59,910 INFO L82 PathProgramCache]: Analyzing trace with hash 30504, now seen corresponding path program 1 times [2019-01-11 11:46:59,910 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:46:59,911 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:46:59,911 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:46:59,912 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:46:59,912 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:46:59,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:47:00,006 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:47:00,006 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:47:00,006 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:47:00,006 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:47:00,007 INFO L207 CegarAbsIntRunner]: [0], [22], [31] [2019-01-11 11:47:00,008 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:47:00,008 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:47:14,796 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:47:14,796 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:47:14,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:14,797 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:47:15,390 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 77.27% of their original sizes. [2019-01-11 11:47:15,390 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:47:18,012 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_409 Int) (v_idx_407 Int) (v_idx_408 Int) (v_idx_412 Int) (v_idx_413 Int) (v_idx_410 Int) (v_idx_411 Int) (v_idx_405 Int) (v_idx_416 Int) (v_idx_406 Int) (v_idx_417 Int) (v_idx_403 Int) (v_idx_414 Int) (v_idx_404 Int) (v_idx_415 Int)) (exists ((v_v_2058_3 Int) (v_v_2046_3 Int) (v_v_2056_3 Int) (v_v_2044_3 Int) (v_v_2054_3 Int) (v_v_2053_3 Int) (v_v_2052_3 Int) (v_b_169_3 Int) (v_b_168_3 Int) (v_b_167_3 Int) (v_v_2048_3 Int) (v_b_170_3 Int) (v_b_171_3 Int) (v_b_166_3 Int) (v_b_174_3 Int) (v_b_175_3 Int) (v_b_176_3 Int) (v_b_177_3 Int) (v_v_2050_3 Int)) (let ((.cse8 (+ v_b_167_3 1)) (.cse7 (+ c_ULTIMATE.start_main_p1 3)) (.cse11 (+ v_b_169_3 3)) (.cse12 (+ v_b_168_3 4)) (.cse9 (+ c_ULTIMATE.start_main_p5 2)) (.cse6 (+ v_b_174_3 1)) (.cse4 (+ c_ULTIMATE.start_main_p1 2)) (.cse1 (+ v_b_169_3 1)) (.cse2 (+ v_b_168_3 1)) (.cse5 (+ v_b_166_3 1)) (.cse16 (+ v_b_170_3 3)) (.cse3 (+ v_b_168_3 2)) (.cse0 (+ v_b_166_3 5)) (.cse10 (+ v_b_170_3 1)) (.cse19 (+ c_ULTIMATE.start_main_p1 1)) (.cse13 (+ v_b_171_3 2)) (.cse15 (+ c_ULTIMATE.start_main_p1 6)) (.cse18 (+ c_ULTIMATE.start_main_p5 1)) (.cse21 (+ v_b_167_3 4)) (.cse20 (+ v_b_176_3 1)) (.cse22 (+ v_b_166_3 3)) (.cse17 (+ c_ULTIMATE.start_main_p1 4)) (.cse14 (+ v_b_167_3 2)) (.cse23 (+ v_b_166_3 2))) (and (<= .cse0 v_b_176_3) (<= .cse1 v_b_171_3) (<= .cse2 v_b_169_3) (or (= (select |c_#memory_int| v_idx_410) 0) (<= v_b_171_3 v_idx_410) (< v_idx_410 v_b_170_3)) (or (= (select |c_#memory_int| v_idx_403) v_v_2044_3) (<= c_ULTIMATE.start_main_p1 v_idx_403)) (<= .cse3 v_b_171_3) (<= .cse4 v_b_167_3) (<= .cse5 v_b_167_3) (<= v_b_175_3 .cse6) (<= .cse7 v_b_169_3) (<= v_b_167_3 .cse5) (<= .cse8 v_b_169_3) (<= (+ v_b_167_3 3) v_b_174_3) (<= .cse9 v_b_175_3) (<= .cse10 v_b_171_3) (<= .cse11 v_b_175_3) (<= 0 v_v_2053_3) (<= .cse12 v_b_175_3) (<= .cse8 v_b_170_3) (<= .cse2 v_b_170_3) (<= .cse6 v_b_176_3) (<= .cse7 v_b_170_3) (or (<= v_b_167_3 v_idx_406) (< v_idx_406 v_b_166_3) (= (select |c_#memory_int| v_idx_406) 0)) (<= .cse13 v_b_176_3) (<= (+ v_b_174_3 2) v_b_177_3) (<= .cse14 v_b_171_3) (<= (+ v_b_166_3 6) v_b_177_3) (<= .cse15 v_b_175_3) (or (= (select |c_#memory_int| v_idx_411) v_v_2052_3) (<= c_ULTIMATE.start_main_p5 v_idx_411) (< v_idx_411 v_b_171_3)) (<= .cse11 v_b_176_3) (<= .cse12 v_b_176_3) (<= .cse9 v_b_176_3) (<= 0 (* 2 v_v_2053_3)) (<= .cse6 v_b_175_3) (<= (+ v_b_171_3 1) v_b_174_3) (<= .cse4 v_b_168_3) (<= .cse16 v_b_176_3) (<= .cse10 c_ULTIMATE.start_main_p5) (or (< v_idx_416 v_b_176_3) (= (select |c_#memory_int| v_idx_416) 0) (<= v_b_177_3 v_idx_416)) (<= (+ v_b_168_3 5) v_b_177_3) (<= .cse17 c_ULTIMATE.start_main_p5) (or (= (select |c_#memory_int| v_idx_407) v_v_2048_3) (< v_idx_407 v_b_167_3) (<= v_b_168_3 v_idx_407)) (or (<= .cse18 v_idx_412) (= (select |c_#memory_int| v_idx_412) v_v_2053_3) (< v_idx_412 c_ULTIMATE.start_main_p5)) (<= (+ v_b_166_3 4) v_b_174_3) (<= .cse19 v_b_166_3) (<= .cse1 c_ULTIMATE.start_main_p5) (<= (+ v_b_170_3 2) v_b_174_3) (<= v_b_169_3 .cse2) (<= .cse5 v_b_168_3) (<= .cse16 v_b_175_3) (<= .cse3 c_ULTIMATE.start_main_p5) (<= .cse0 v_b_175_3) (<= (+ v_b_175_3 1) v_b_177_3) (<= v_b_171_3 .cse10) (or (< v_idx_405 .cse19) (<= v_b_166_3 v_idx_405) (= (select |c_#memory_int| v_idx_405) v_v_2046_3)) (or (= (select |c_#memory_int| v_idx_413) v_v_2054_3) (<= v_b_174_3 v_idx_413) (< v_idx_413 .cse18)) (or (< v_idx_404 c_ULTIMATE.start_main_p1) (<= .cse19 v_idx_404) (= (select |c_#memory_int| v_idx_404) 0)) (<= .cse13 v_b_175_3) (<= (+ v_b_169_3 4) v_b_177_3) (<= v_b_177_3 .cse20) (<= v_b_171_3 c_ULTIMATE.start_main_p5) (<= .cse15 v_b_176_3) (<= .cse21 v_b_176_3) (<= (+ v_b_170_3 4) v_b_177_3) (<= .cse22 v_b_171_3) (<= v_b_167_3 v_b_168_3) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_177_3) (<= .cse18 v_b_174_3) (<= .cse21 v_b_175_3) (<= (+ c_ULTIMATE.start_main_p5 3) v_b_177_3) (or (= (select |c_#memory_int| v_idx_408) 0) (< v_idx_408 v_b_168_3) (<= v_b_169_3 v_idx_408)) (<= v_b_169_3 v_b_170_3) (or (<= v_b_176_3 v_idx_415) (< v_idx_415 v_b_175_3) (= (select |c_#memory_int| v_idx_415) v_v_2056_3)) (<= .cse20 v_b_177_3) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_174_3) (<= (+ v_b_171_3 3) v_b_177_3) (or (< v_idx_417 v_b_177_3) (= (select |c_#memory_int| v_idx_417) v_v_2058_3)) (<= (+ v_b_168_3 3) v_b_174_3) (<= .cse22 c_ULTIMATE.start_main_p5) (<= v_b_175_3 v_b_176_3) (<= (+ v_b_167_3 5) v_b_177_3) (<= .cse23 v_b_170_3) (<= .cse17 v_b_171_3) (<= (+ v_b_169_3 2) v_b_174_3) (<= .cse14 c_ULTIMATE.start_main_p5) (or (= (select |c_#memory_int| v_idx_414) 0) (< v_idx_414 v_b_174_3) (<= v_b_175_3 v_idx_414)) (<= .cse23 v_b_169_3) (or (< v_idx_409 v_b_169_3) (= (select |c_#memory_int| v_idx_409) v_v_2050_3) (<= v_b_170_3 v_idx_409)))))) is different from false [2019-01-11 11:47:20,414 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_429 Int) (v_idx_418 Int) (v_idx_419 Int) (v_idx_423 Int) (v_idx_424 Int) (v_idx_421 Int) (v_idx_432 Int) (v_idx_422 Int) (v_idx_427 Int) (v_idx_428 Int) (v_idx_425 Int) (v_idx_426 Int) (v_idx_430 Int) (v_idx_420 Int) (v_idx_431 Int)) (exists ((v_v_2058_3 Int) (v_v_2046_3 Int) (v_v_2056_3 Int) (v_v_2044_3 Int) (v_v_2054_3 Int) (v_v_2053_3 Int) (v_v_2052_3 Int) (v_b_169_3 Int) (v_b_168_3 Int) (v_b_167_3 Int) (v_v_2048_3 Int) (v_b_170_3 Int) (v_b_171_3 Int) (v_b_172_3 Int) (v_b_173_3 Int) (v_b_174_3 Int) (v_b_166_3 Int) (v_b_175_3 Int) (v_b_176_3 Int) (v_b_177_3 Int) (v_v_2050_3 Int)) (let ((.cse8 (+ v_b_173_3 1)) (.cse7 (+ v_b_170_3 3)) (.cse3 (+ v_b_172_3 2)) (.cse15 (+ v_b_168_3 3)) (.cse17 (+ v_b_168_3 2)) (.cse9 (+ v_b_166_3 1)) (.cse24 (+ v_b_167_3 1)) (.cse23 (+ c_ULTIMATE.start_main_p1 3)) (.cse11 (+ c_ULTIMATE.start_main_p1 6)) (.cse26 (+ v_b_169_3 3)) (.cse27 (+ v_b_168_3 4)) (.cse22 (+ v_b_174_3 1)) (.cse5 (+ v_b_171_3 1)) (.cse21 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ v_b_172_3 1)) (.cse10 (+ v_b_170_3 1)) (.cse28 (+ v_b_167_3 2)) (.cse1 (+ v_b_168_3 1)) (.cse0 (+ v_b_169_3 1)) (.cse20 (+ v_b_166_3 5)) (.cse4 (+ v_b_171_3 2)) (.cse6 (+ c_ULTIMATE.start_main_p1 1)) (.cse13 (+ v_b_176_3 1)) (.cse12 (+ v_b_167_3 4)) (.cse14 (+ c_ULTIMATE.start_main_p1 5)) (.cse31 (+ v_b_166_3 3)) (.cse18 (+ c_ULTIMATE.start_main_p1 4)) (.cse19 (+ v_b_169_3 2)) (.cse29 (+ v_b_166_3 4)) (.cse30 (+ v_b_170_3 2)) (.cse25 (+ v_b_167_3 3)) (.cse16 (+ v_b_166_3 2))) (and (<= .cse0 v_b_171_3) (<= .cse1 v_b_169_3) (<= .cse2 v_b_173_3) (<= .cse3 v_b_175_3) (<= v_b_171_3 v_b_172_3) (<= 0 v_v_2053_3) (<= .cse1 v_b_170_3) (<= .cse4 v_b_176_3) (<= .cse5 v_b_173_3) (or (< v_idx_419 c_ULTIMATE.start_main_p1) (<= .cse6 v_idx_419) (= (select |c_#memory_int| v_idx_419) 0)) (or (<= v_b_174_3 v_idx_428) (= (select |c_#memory_int| v_idx_428) v_v_2054_3) (< v_idx_428 v_b_173_3)) (<= .cse7 v_b_176_3) (<= .cse8 v_b_176_3) (<= (+ v_b_168_3 5) v_b_177_3) (<= .cse8 v_b_175_3) (<= .cse6 v_b_166_3) (or (< v_idx_431 v_b_176_3) (<= v_b_177_3 v_idx_431) (= (select |c_#memory_int| v_idx_431) 0)) (<= .cse9 v_b_168_3) (<= .cse7 v_b_175_3) (or (<= v_b_168_3 v_idx_422) (< v_idx_422 v_b_167_3) (= (select |c_#memory_int| v_idx_422) v_v_2048_3)) (<= v_b_171_3 .cse10) (<= .cse3 v_b_176_3) (<= .cse11 v_b_176_3) (<= (+ v_b_170_3 4) v_b_177_3) (<= v_b_167_3 v_b_168_3) (<= .cse12 v_b_175_3) (<= v_b_169_3 v_b_170_3) (<= .cse13 v_b_177_3) (<= .cse14 v_b_174_3) (<= (+ v_b_171_3 3) v_b_177_3) (or (= (select |c_#memory_int| v_idx_429) 0) (< v_idx_429 v_b_174_3) (<= v_b_175_3 v_idx_429)) (<= .cse15 v_b_173_3) (<= .cse15 v_b_174_3) (<= v_b_175_3 v_b_176_3) (<= (+ v_b_167_3 5) v_b_177_3) (or (= (select |c_#memory_int| v_idx_430) v_v_2056_3) (<= v_b_176_3 v_idx_430) (< v_idx_430 v_b_175_3)) (<= .cse16 v_b_170_3) (<= .cse17 v_b_172_3) (<= .cse18 v_b_171_3) (<= .cse19 v_b_174_3) (<= .cse20 v_b_176_3) (<= .cse17 v_b_171_3) (<= .cse21 v_b_167_3) (<= .cse9 v_b_167_3) (<= v_b_175_3 .cse22) (<= .cse23 v_b_169_3) (<= (+ v_b_173_3 2) v_b_177_3) (or (<= v_b_173_3 v_idx_427) (= (select |c_#memory_int| v_idx_427) v_v_2053_3) (< v_idx_427 v_b_172_3)) (<= v_b_167_3 .cse9) (<= .cse24 v_b_169_3) (<= .cse25 v_b_174_3) (<= .cse10 v_b_171_3) (<= .cse26 v_b_175_3) (<= .cse27 v_b_175_3) (<= .cse24 v_b_170_3) (<= .cse22 v_b_176_3) (or (< v_idx_424 v_b_169_3) (= (select |c_#memory_int| v_idx_424) v_v_2050_3) (<= v_b_170_3 v_idx_424)) (<= .cse23 v_b_170_3) (<= (+ v_b_174_3 2) v_b_177_3) (<= .cse28 v_b_171_3) (<= (+ v_b_166_3 6) v_b_177_3) (<= .cse11 v_b_175_3) (<= .cse26 v_b_176_3) (<= .cse27 v_b_176_3) (<= .cse2 v_b_174_3) (<= 0 (* 2 v_v_2053_3)) (<= .cse22 v_b_175_3) (<= .cse5 v_b_174_3) (<= .cse21 v_b_168_3) (<= v_b_173_3 .cse2) (<= v_b_173_3 v_b_174_3) (<= .cse10 v_b_172_3) (<= .cse29 v_b_174_3) (<= .cse28 v_b_172_3) (<= .cse30 v_b_174_3) (<= v_b_169_3 .cse1) (<= .cse0 v_b_172_3) (<= .cse20 v_b_175_3) (<= (+ v_b_175_3 1) v_b_177_3) (or (= (select |c_#memory_int| v_idx_432) v_v_2058_3) (< v_idx_432 v_b_177_3)) (or (< v_idx_426 v_b_171_3) (<= v_b_172_3 v_idx_426) (= (select |c_#memory_int| v_idx_426) v_v_2052_3)) (<= .cse4 v_b_175_3) (<= (+ v_b_169_3 4) v_b_177_3) (or (= (select |c_#memory_int| v_idx_420) v_v_2046_3) (<= v_b_166_3 v_idx_420) (< v_idx_420 .cse6)) (<= v_b_177_3 .cse13) (<= (+ v_b_172_3 3) v_b_177_3) (<= .cse12 v_b_176_3) (<= .cse31 v_b_172_3) (<= .cse14 v_b_173_3) (<= .cse31 v_b_171_3) (or (< v_idx_423 v_b_168_3) (<= v_b_169_3 v_idx_423) (= (select |c_#memory_int| v_idx_423) 0)) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_177_3) (or (<= v_b_171_3 v_idx_425) (= (select |c_#memory_int| v_idx_425) 0) (< v_idx_425 v_b_170_3)) (<= .cse18 v_b_172_3) (<= .cse19 v_b_173_3) (<= .cse29 v_b_173_3) (or (<= v_b_167_3 v_idx_421) (< v_idx_421 v_b_166_3) (= (select |c_#memory_int| v_idx_421) 0)) (or (<= c_ULTIMATE.start_main_p1 v_idx_418) (= (select |c_#memory_int| v_idx_418) v_v_2044_3)) (<= .cse30 v_b_173_3) (<= .cse25 v_b_173_3) (<= .cse16 v_b_169_3))))) is different from false [2019-01-11 11:47:20,548 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:47:20,549 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:47:20,549 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:47:20,549 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:47:20,549 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:47:20,549 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:47:20,550 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:47:20,550 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:47:20,550 INFO L87 Difference]: Start difference. First operand 18 states and 38 transitions. Second operand 4 states. [2019-01-11 11:47:23,594 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_429 Int) (v_idx_418 Int) (v_idx_419 Int) (v_idx_423 Int) (v_idx_424 Int) (v_idx_421 Int) (v_idx_432 Int) (v_idx_422 Int) (v_idx_427 Int) (v_idx_428 Int) (v_idx_425 Int) (v_idx_426 Int) (v_idx_430 Int) (v_idx_420 Int) (v_idx_431 Int)) (exists ((v_v_2058_3 Int) (v_v_2046_3 Int) (v_v_2056_3 Int) (v_v_2044_3 Int) (v_v_2054_3 Int) (v_v_2053_3 Int) (v_v_2052_3 Int) (v_b_169_3 Int) (v_b_168_3 Int) (v_b_167_3 Int) (v_v_2048_3 Int) (v_b_170_3 Int) (v_b_171_3 Int) (v_b_172_3 Int) (v_b_173_3 Int) (v_b_174_3 Int) (v_b_166_3 Int) (v_b_175_3 Int) (v_b_176_3 Int) (v_b_177_3 Int) (v_v_2050_3 Int)) (let ((.cse8 (+ v_b_173_3 1)) (.cse7 (+ v_b_170_3 3)) (.cse3 (+ v_b_172_3 2)) (.cse15 (+ v_b_168_3 3)) (.cse17 (+ v_b_168_3 2)) (.cse9 (+ v_b_166_3 1)) (.cse24 (+ v_b_167_3 1)) (.cse23 (+ c_ULTIMATE.start_main_p1 3)) (.cse11 (+ c_ULTIMATE.start_main_p1 6)) (.cse26 (+ v_b_169_3 3)) (.cse27 (+ v_b_168_3 4)) (.cse22 (+ v_b_174_3 1)) (.cse5 (+ v_b_171_3 1)) (.cse21 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ v_b_172_3 1)) (.cse10 (+ v_b_170_3 1)) (.cse28 (+ v_b_167_3 2)) (.cse1 (+ v_b_168_3 1)) (.cse0 (+ v_b_169_3 1)) (.cse20 (+ v_b_166_3 5)) (.cse4 (+ v_b_171_3 2)) (.cse6 (+ c_ULTIMATE.start_main_p1 1)) (.cse13 (+ v_b_176_3 1)) (.cse12 (+ v_b_167_3 4)) (.cse14 (+ c_ULTIMATE.start_main_p1 5)) (.cse31 (+ v_b_166_3 3)) (.cse18 (+ c_ULTIMATE.start_main_p1 4)) (.cse19 (+ v_b_169_3 2)) (.cse29 (+ v_b_166_3 4)) (.cse30 (+ v_b_170_3 2)) (.cse25 (+ v_b_167_3 3)) (.cse16 (+ v_b_166_3 2))) (and (<= .cse0 v_b_171_3) (<= .cse1 v_b_169_3) (<= .cse2 v_b_173_3) (<= .cse3 v_b_175_3) (<= v_b_171_3 v_b_172_3) (<= 0 v_v_2053_3) (<= .cse1 v_b_170_3) (<= .cse4 v_b_176_3) (<= .cse5 v_b_173_3) (or (< v_idx_419 c_ULTIMATE.start_main_p1) (<= .cse6 v_idx_419) (= (select |c_#memory_int| v_idx_419) 0)) (or (<= v_b_174_3 v_idx_428) (= (select |c_#memory_int| v_idx_428) v_v_2054_3) (< v_idx_428 v_b_173_3)) (<= .cse7 v_b_176_3) (<= .cse8 v_b_176_3) (<= (+ v_b_168_3 5) v_b_177_3) (<= .cse8 v_b_175_3) (<= .cse6 v_b_166_3) (or (< v_idx_431 v_b_176_3) (<= v_b_177_3 v_idx_431) (= (select |c_#memory_int| v_idx_431) 0)) (<= .cse9 v_b_168_3) (<= .cse7 v_b_175_3) (or (<= v_b_168_3 v_idx_422) (< v_idx_422 v_b_167_3) (= (select |c_#memory_int| v_idx_422) v_v_2048_3)) (<= v_b_171_3 .cse10) (<= .cse3 v_b_176_3) (<= .cse11 v_b_176_3) (<= (+ v_b_170_3 4) v_b_177_3) (<= v_b_167_3 v_b_168_3) (<= .cse12 v_b_175_3) (<= v_b_169_3 v_b_170_3) (<= .cse13 v_b_177_3) (<= .cse14 v_b_174_3) (<= (+ v_b_171_3 3) v_b_177_3) (or (= (select |c_#memory_int| v_idx_429) 0) (< v_idx_429 v_b_174_3) (<= v_b_175_3 v_idx_429)) (<= .cse15 v_b_173_3) (<= .cse15 v_b_174_3) (<= v_b_175_3 v_b_176_3) (<= (+ v_b_167_3 5) v_b_177_3) (or (= (select |c_#memory_int| v_idx_430) v_v_2056_3) (<= v_b_176_3 v_idx_430) (< v_idx_430 v_b_175_3)) (<= .cse16 v_b_170_3) (<= .cse17 v_b_172_3) (<= .cse18 v_b_171_3) (<= .cse19 v_b_174_3) (<= .cse20 v_b_176_3) (<= .cse17 v_b_171_3) (<= .cse21 v_b_167_3) (<= .cse9 v_b_167_3) (<= v_b_175_3 .cse22) (<= .cse23 v_b_169_3) (<= (+ v_b_173_3 2) v_b_177_3) (or (<= v_b_173_3 v_idx_427) (= (select |c_#memory_int| v_idx_427) v_v_2053_3) (< v_idx_427 v_b_172_3)) (<= v_b_167_3 .cse9) (<= .cse24 v_b_169_3) (<= .cse25 v_b_174_3) (<= .cse10 v_b_171_3) (<= .cse26 v_b_175_3) (<= .cse27 v_b_175_3) (<= .cse24 v_b_170_3) (<= .cse22 v_b_176_3) (or (< v_idx_424 v_b_169_3) (= (select |c_#memory_int| v_idx_424) v_v_2050_3) (<= v_b_170_3 v_idx_424)) (<= .cse23 v_b_170_3) (<= (+ v_b_174_3 2) v_b_177_3) (<= .cse28 v_b_171_3) (<= (+ v_b_166_3 6) v_b_177_3) (<= .cse11 v_b_175_3) (<= .cse26 v_b_176_3) (<= .cse27 v_b_176_3) (<= .cse2 v_b_174_3) (<= 0 (* 2 v_v_2053_3)) (<= .cse22 v_b_175_3) (<= .cse5 v_b_174_3) (<= .cse21 v_b_168_3) (<= v_b_173_3 .cse2) (<= v_b_173_3 v_b_174_3) (<= .cse10 v_b_172_3) (<= .cse29 v_b_174_3) (<= .cse28 v_b_172_3) (<= .cse30 v_b_174_3) (<= v_b_169_3 .cse1) (<= .cse0 v_b_172_3) (<= .cse20 v_b_175_3) (<= (+ v_b_175_3 1) v_b_177_3) (or (= (select |c_#memory_int| v_idx_432) v_v_2058_3) (< v_idx_432 v_b_177_3)) (or (< v_idx_426 v_b_171_3) (<= v_b_172_3 v_idx_426) (= (select |c_#memory_int| v_idx_426) v_v_2052_3)) (<= .cse4 v_b_175_3) (<= (+ v_b_169_3 4) v_b_177_3) (or (= (select |c_#memory_int| v_idx_420) v_v_2046_3) (<= v_b_166_3 v_idx_420) (< v_idx_420 .cse6)) (<= v_b_177_3 .cse13) (<= (+ v_b_172_3 3) v_b_177_3) (<= .cse12 v_b_176_3) (<= .cse31 v_b_172_3) (<= .cse14 v_b_173_3) (<= .cse31 v_b_171_3) (or (< v_idx_423 v_b_168_3) (<= v_b_169_3 v_idx_423) (= (select |c_#memory_int| v_idx_423) 0)) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_177_3) (or (<= v_b_171_3 v_idx_425) (= (select |c_#memory_int| v_idx_425) 0) (< v_idx_425 v_b_170_3)) (<= .cse18 v_b_172_3) (<= .cse19 v_b_173_3) (<= .cse29 v_b_173_3) (or (<= v_b_167_3 v_idx_421) (< v_idx_421 v_b_166_3) (= (select |c_#memory_int| v_idx_421) 0)) (or (<= c_ULTIMATE.start_main_p1 v_idx_418) (= (select |c_#memory_int| v_idx_418) v_v_2044_3)) (<= .cse30 v_b_173_3) (<= .cse25 v_b_173_3) (<= .cse16 v_b_169_3))))) (forall ((v_idx_409 Int) (v_idx_407 Int) (v_idx_408 Int) (v_idx_412 Int) (v_idx_413 Int) (v_idx_410 Int) (v_idx_411 Int) (v_idx_405 Int) (v_idx_416 Int) (v_idx_406 Int) (v_idx_417 Int) (v_idx_403 Int) (v_idx_414 Int) (v_idx_404 Int) (v_idx_415 Int)) (exists ((v_v_2058_3 Int) (v_v_2046_3 Int) (v_v_2056_3 Int) (v_v_2044_3 Int) (v_v_2054_3 Int) (v_v_2053_3 Int) (v_v_2052_3 Int) (v_b_169_3 Int) (v_b_168_3 Int) (v_b_167_3 Int) (v_v_2048_3 Int) (v_b_170_3 Int) (v_b_171_3 Int) (v_b_166_3 Int) (v_b_174_3 Int) (v_b_175_3 Int) (v_b_176_3 Int) (v_b_177_3 Int) (v_v_2050_3 Int)) (let ((.cse40 (+ v_b_167_3 1)) (.cse39 (+ c_ULTIMATE.start_main_p1 3)) (.cse43 (+ v_b_169_3 3)) (.cse44 (+ v_b_168_3 4)) (.cse41 (+ c_ULTIMATE.start_main_p5 2)) (.cse38 (+ v_b_174_3 1)) (.cse36 (+ c_ULTIMATE.start_main_p1 2)) (.cse33 (+ v_b_169_3 1)) (.cse34 (+ v_b_168_3 1)) (.cse37 (+ v_b_166_3 1)) (.cse48 (+ v_b_170_3 3)) (.cse35 (+ v_b_168_3 2)) (.cse32 (+ v_b_166_3 5)) (.cse42 (+ v_b_170_3 1)) (.cse51 (+ c_ULTIMATE.start_main_p1 1)) (.cse45 (+ v_b_171_3 2)) (.cse47 (+ c_ULTIMATE.start_main_p1 6)) (.cse50 (+ c_ULTIMATE.start_main_p5 1)) (.cse53 (+ v_b_167_3 4)) (.cse52 (+ v_b_176_3 1)) (.cse54 (+ v_b_166_3 3)) (.cse49 (+ c_ULTIMATE.start_main_p1 4)) (.cse46 (+ v_b_167_3 2)) (.cse55 (+ v_b_166_3 2))) (and (<= .cse32 v_b_176_3) (<= .cse33 v_b_171_3) (<= .cse34 v_b_169_3) (or (= (select |c_#memory_int| v_idx_410) 0) (<= v_b_171_3 v_idx_410) (< v_idx_410 v_b_170_3)) (or (= (select |c_#memory_int| v_idx_403) v_v_2044_3) (<= c_ULTIMATE.start_main_p1 v_idx_403)) (<= .cse35 v_b_171_3) (<= .cse36 v_b_167_3) (<= .cse37 v_b_167_3) (<= v_b_175_3 .cse38) (<= .cse39 v_b_169_3) (<= v_b_167_3 .cse37) (<= .cse40 v_b_169_3) (<= (+ v_b_167_3 3) v_b_174_3) (<= .cse41 v_b_175_3) (<= .cse42 v_b_171_3) (<= .cse43 v_b_175_3) (<= 0 v_v_2053_3) (<= .cse44 v_b_175_3) (<= .cse40 v_b_170_3) (<= .cse34 v_b_170_3) (<= .cse38 v_b_176_3) (<= .cse39 v_b_170_3) (or (<= v_b_167_3 v_idx_406) (< v_idx_406 v_b_166_3) (= (select |c_#memory_int| v_idx_406) 0)) (<= .cse45 v_b_176_3) (<= (+ v_b_174_3 2) v_b_177_3) (<= .cse46 v_b_171_3) (<= (+ v_b_166_3 6) v_b_177_3) (<= .cse47 v_b_175_3) (or (= (select |c_#memory_int| v_idx_411) v_v_2052_3) (<= c_ULTIMATE.start_main_p5 v_idx_411) (< v_idx_411 v_b_171_3)) (<= .cse43 v_b_176_3) (<= .cse44 v_b_176_3) (<= .cse41 v_b_176_3) (<= 0 (* 2 v_v_2053_3)) (<= .cse38 v_b_175_3) (<= (+ v_b_171_3 1) v_b_174_3) (<= .cse36 v_b_168_3) (<= .cse48 v_b_176_3) (<= .cse42 c_ULTIMATE.start_main_p5) (or (< v_idx_416 v_b_176_3) (= (select |c_#memory_int| v_idx_416) 0) (<= v_b_177_3 v_idx_416)) (<= (+ v_b_168_3 5) v_b_177_3) (<= .cse49 c_ULTIMATE.start_main_p5) (or (= (select |c_#memory_int| v_idx_407) v_v_2048_3) (< v_idx_407 v_b_167_3) (<= v_b_168_3 v_idx_407)) (or (<= .cse50 v_idx_412) (= (select |c_#memory_int| v_idx_412) v_v_2053_3) (< v_idx_412 c_ULTIMATE.start_main_p5)) (<= (+ v_b_166_3 4) v_b_174_3) (<= .cse51 v_b_166_3) (<= .cse33 c_ULTIMATE.start_main_p5) (<= (+ v_b_170_3 2) v_b_174_3) (<= v_b_169_3 .cse34) (<= .cse37 v_b_168_3) (<= .cse48 v_b_175_3) (<= .cse35 c_ULTIMATE.start_main_p5) (<= .cse32 v_b_175_3) (<= (+ v_b_175_3 1) v_b_177_3) (<= v_b_171_3 .cse42) (or (< v_idx_405 .cse51) (<= v_b_166_3 v_idx_405) (= (select |c_#memory_int| v_idx_405) v_v_2046_3)) (or (= (select |c_#memory_int| v_idx_413) v_v_2054_3) (<= v_b_174_3 v_idx_413) (< v_idx_413 .cse50)) (or (< v_idx_404 c_ULTIMATE.start_main_p1) (<= .cse51 v_idx_404) (= (select |c_#memory_int| v_idx_404) 0)) (<= .cse45 v_b_175_3) (<= (+ v_b_169_3 4) v_b_177_3) (<= v_b_177_3 .cse52) (<= v_b_171_3 c_ULTIMATE.start_main_p5) (<= .cse47 v_b_176_3) (<= .cse53 v_b_176_3) (<= (+ v_b_170_3 4) v_b_177_3) (<= .cse54 v_b_171_3) (<= v_b_167_3 v_b_168_3) (<= (+ c_ULTIMATE.start_main_p1 7) v_b_177_3) (<= .cse50 v_b_174_3) (<= .cse53 v_b_175_3) (<= (+ c_ULTIMATE.start_main_p5 3) v_b_177_3) (or (= (select |c_#memory_int| v_idx_408) 0) (< v_idx_408 v_b_168_3) (<= v_b_169_3 v_idx_408)) (<= v_b_169_3 v_b_170_3) (or (<= v_b_176_3 v_idx_415) (< v_idx_415 v_b_175_3) (= (select |c_#memory_int| v_idx_415) v_v_2056_3)) (<= .cse52 v_b_177_3) (<= (+ c_ULTIMATE.start_main_p1 5) v_b_174_3) (<= (+ v_b_171_3 3) v_b_177_3) (or (< v_idx_417 v_b_177_3) (= (select |c_#memory_int| v_idx_417) v_v_2058_3)) (<= (+ v_b_168_3 3) v_b_174_3) (<= .cse54 c_ULTIMATE.start_main_p5) (<= v_b_175_3 v_b_176_3) (<= (+ v_b_167_3 5) v_b_177_3) (<= .cse55 v_b_170_3) (<= .cse49 v_b_171_3) (<= (+ v_b_169_3 2) v_b_174_3) (<= .cse46 c_ULTIMATE.start_main_p5) (or (= (select |c_#memory_int| v_idx_414) 0) (< v_idx_414 v_b_174_3) (<= v_b_175_3 v_idx_414)) (<= .cse55 v_b_169_3) (or (< v_idx_409 v_b_169_3) (= (select |c_#memory_int| v_idx_409) v_v_2050_3) (<= v_b_170_3 v_idx_409))))))) is different from false [2019-01-11 11:47:46,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:47:46,559 INFO L93 Difference]: Finished difference Result 20 states and 47 transitions. [2019-01-11 11:47:46,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:47:46,560 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:47:46,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:47:46,560 INFO L225 Difference]: With dead ends: 20 [2019-01-11 11:47:46,561 INFO L226 Difference]: Without dead ends: 19 [2019-01-11 11:47:46,561 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.9s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:47:46,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2019-01-11 11:47:46,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 18. [2019-01-11 11:47:46,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2019-01-11 11:47:46,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 38 transitions. [2019-01-11 11:47:46,573 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 38 transitions. Word has length 3 [2019-01-11 11:47:46,574 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:47:46,574 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 38 transitions. [2019-01-11 11:47:46,574 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:47:46,574 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 38 transitions. [2019-01-11 11:47:46,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:47:46,574 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:47:46,575 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:47:46,575 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:47:46,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:46,575 INFO L82 PathProgramCache]: Analyzing trace with hash 30132, now seen corresponding path program 1 times [2019-01-11 11:47:46,575 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:47:46,576 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:46,576 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:47:46,576 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:46,577 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:47:46,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:47:46,775 WARN L181 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 20 DAG size of output: 13 [2019-01-11 11:47:46,849 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:47:46,849 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:47:46,849 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:47:46,849 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:47:46,850 INFO L207 CegarAbsIntRunner]: [0], [10], [31] [2019-01-11 11:47:46,851 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:47:46,851 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:47:59,235 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:47:59,235 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:47:59,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:59,236 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:47:59,832 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 77.27% of their original sizes. [2019-01-11 11:47:59,832 INFO L418 sIntCurrentIteration]: Unifying AI predicates