java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml -s ../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf -i ../../../trunk/examples/programs/heapseparator/speedup-poc-dd-8-limited.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.24-df3cc4e-m [2019-01-11 11:45:01,231 INFO L170 SettingsManager]: Resetting all preferences to default values... [2019-01-11 11:45:01,233 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2019-01-11 11:45:01,250 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2019-01-11 11:45:01,308 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/array-bench/reach_32bit_array_oct.epf [2019-01-11 11:45:01,333 INFO L110 SettingsManager]: Loading preferences was successful [2019-01-11 11:45:01,334 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2019-01-11 11:45:01,334 INFO L131 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2019-01-11 11:45:01,335 INFO L133 SettingsManager]: * Show backtranslation warnings=false [2019-01-11 11:45:01,335 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2019-01-11 11:45:01,335 INFO L133 SettingsManager]: * User list type=DISABLED [2019-01-11 11:45:01,335 INFO L133 SettingsManager]: * Inline calls to unimplemented procedures=true [2019-01-11 11:45:01,335 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2019-01-11 11:45:01,338 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2019-01-11 11:45:01,338 INFO L133 SettingsManager]: * Underlying domain=OctagonDomain [2019-01-11 11:45:01,338 INFO L133 SettingsManager]: * Abstract domain=ArrayDomain [2019-01-11 11:45:01,338 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2019-01-11 11:45:01,338 INFO L133 SettingsManager]: * Interval Domain=false [2019-01-11 11:45:01,339 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-01-11 11:45:01,340 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2019-01-11 11:45:01,340 INFO L133 SettingsManager]: * Use SBE=true [2019-01-11 11:45:01,340 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-01-11 11:45:01,340 INFO L133 SettingsManager]: * sizeof long=4 [2019-01-11 11:45:01,340 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2019-01-11 11:45:01,340 INFO L133 SettingsManager]: * sizeof POINTER=4 [2019-01-11 11:45:01,341 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2019-01-11 11:45:01,341 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-01-11 11:45:01,341 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-01-11 11:45:01,341 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-01-11 11:45:01,341 INFO L133 SettingsManager]: * sizeof long double=12 [2019-01-11 11:45:01,342 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2019-01-11 11:45:01,342 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-01-11 11:45:01,342 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-01-11 11:45:01,342 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-01-11 11:45:01,342 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2019-01-11 11:45:01,343 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-11 11:45:01,343 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-01-11 11:45:01,343 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-01-11 11:45:01,343 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-01-11 11:45:01,343 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2019-01-11 11:45:01,344 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-01-11 11:45:01,344 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in [2019-01-11 11:45:01,344 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-01-11 11:45:01,344 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2019-01-11 11:45:01,373 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-01-11 11:45:01,385 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-01-11 11:45:01,388 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-01-11 11:45:01,390 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2019-01-11 11:45:01,390 INFO L276 PluginConnector]: Boogie PL CUP Parser initialized [2019-01-11 11:45:01,391 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-8-limited.bpl [2019-01-11 11:45:01,391 INFO L111 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/heapseparator/speedup-poc-dd-8-limited.bpl' [2019-01-11 11:45:01,430 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-01-11 11:45:01,432 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2019-01-11 11:45:01,433 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-01-11 11:45:01,433 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-01-11 11:45:01,433 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2019-01-11 11:45:01,448 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "speedup-poc-dd-8-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:45:01" (1/1) ... [2019-01-11 11:45:01,460 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "speedup-poc-dd-8-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:45:01" (1/1) ... [2019-01-11 11:45:01,487 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-01-11 11:45:01,488 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-01-11 11:45:01,488 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-01-11 11:45:01,488 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2019-01-11 11:45:01,499 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "speedup-poc-dd-8-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:45:01" (1/1) ... [2019-01-11 11:45:01,499 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "speedup-poc-dd-8-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:45:01" (1/1) ... [2019-01-11 11:45:01,501 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "speedup-poc-dd-8-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:45:01" (1/1) ... [2019-01-11 11:45:01,501 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "speedup-poc-dd-8-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:45:01" (1/1) ... [2019-01-11 11:45:01,505 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "speedup-poc-dd-8-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:45:01" (1/1) ... [2019-01-11 11:45:01,508 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "speedup-poc-dd-8-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:45:01" (1/1) ... [2019-01-11 11:45:01,510 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "speedup-poc-dd-8-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:45:01" (1/1) ... [2019-01-11 11:45:01,512 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-01-11 11:45:01,512 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-01-11 11:45:01,512 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-01-11 11:45:01,513 INFO L276 PluginConnector]: RCFGBuilder initialized [2019-01-11 11:45:01,514 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "speedup-poc-dd-8-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:45:01" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:8192 -smt2 -in -t:2000 [2019-01-11 11:45:01,577 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-01-11 11:45:01,577 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-01-11 11:45:02,155 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-01-11 11:45:02,155 INFO L286 CfgBuilder]: Removed 19 assue(true) statements. [2019-01-11 11:45:02,162 INFO L202 PluginConnector]: Adding new model speedup-poc-dd-8-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.01 11:45:02 BoogieIcfgContainer [2019-01-11 11:45:02,162 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-01-11 11:45:02,163 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-01-11 11:45:02,163 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-01-11 11:45:02,166 INFO L276 PluginConnector]: TraceAbstraction initialized [2019-01-11 11:45:02,167 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-8-limited.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 11.01 11:45:01" (1/2) ... [2019-01-11 11:45:02,168 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@11b13a3c and model type speedup-poc-dd-8-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.01 11:45:02, skipping insertion in model container [2019-01-11 11:45:02,168 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "speedup-poc-dd-8-limited.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.01 11:45:02" (2/2) ... [2019-01-11 11:45:02,170 INFO L112 eAbstractionObserver]: Analyzing ICFG speedup-poc-dd-8-limited.bpl [2019-01-11 11:45:02,179 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-01-11 11:45:02,188 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 8 error locations. [2019-01-11 11:45:02,207 INFO L257 AbstractCegarLoop]: Starting to check reachability of 8 error locations. [2019-01-11 11:45:02,243 INFO L382 AbstractCegarLoop]: Interprodecural is true [2019-01-11 11:45:02,244 INFO L383 AbstractCegarLoop]: Hoare is true [2019-01-11 11:45:02,244 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-01-11 11:45:02,244 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2019-01-11 11:45:02,244 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-01-11 11:45:02,244 INFO L387 AbstractCegarLoop]: Difference is false [2019-01-11 11:45:02,245 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-01-11 11:45:02,245 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-01-11 11:45:02,258 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states. [2019-01-11 11:45:02,264 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3 [2019-01-11 11:45:02,265 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:45:02,266 INFO L402 BasicCegarLoop]: trace histogram [1, 1] [2019-01-11 11:45:02,268 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr7ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:45:02,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:02,274 INFO L82 PathProgramCache]: Analyzing trace with hash 996, now seen corresponding path program 1 times [2019-01-11 11:45:02,276 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:45:02,321 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:02,321 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:45:02,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:02,322 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:45:02,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:45:02,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:45:02,479 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-11 11:45:02,479 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-11 11:45:02,479 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:45:02,484 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-11 11:45:02,498 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-11 11:45:02,499 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:45:02,502 INFO L87 Difference]: Start difference. First operand 19 states. Second operand 3 states. [2019-01-11 11:45:02,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:45:02,697 INFO L93 Difference]: Finished difference Result 37 states and 51 transitions. [2019-01-11 11:45:02,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:45:02,699 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 2 [2019-01-11 11:45:02,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:45:02,713 INFO L225 Difference]: With dead ends: 37 [2019-01-11 11:45:02,714 INFO L226 Difference]: Without dead ends: 32 [2019-01-11 11:45:02,717 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:45:02,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2019-01-11 11:45:02,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 18. [2019-01-11 11:45:02,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2019-01-11 11:45:02,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 33 transitions. [2019-01-11 11:45:02,755 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 33 transitions. Word has length 2 [2019-01-11 11:45:02,756 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:45:02,757 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 33 transitions. [2019-01-11 11:45:02,757 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-11 11:45:02,757 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 33 transitions. [2019-01-11 11:45:02,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:45:02,758 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:45:02,758 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:45:02,759 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr7ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:45:02,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:02,761 INFO L82 PathProgramCache]: Analyzing trace with hash 30818, now seen corresponding path program 1 times [2019-01-11 11:45:02,761 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:45:02,762 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:02,763 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:45:02,763 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:45:02,763 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:45:02,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:45:03,163 WARN L181 SmtUtils]: Spent 282.00 ms on a formula simplification. DAG size of input: 19 DAG size of output: 13 [2019-01-11 11:45:03,237 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:45:03,238 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:45:03,238 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:45:03,239 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:45:03,241 INFO L207 CegarAbsIntRunner]: [0], [32], [35] [2019-01-11 11:45:03,300 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:45:03,300 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:45:23,765 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:45:23,767 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:45:23,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:45:23,773 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:45:24,925 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 79.17% of their original sizes. [2019-01-11 11:45:24,926 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:45:27,612 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_137 Int) (v_idx_127 Int) (v_idx_138 Int) (v_idx_135 Int) (v_idx_136 Int) (v_idx_128 Int) (v_idx_139 Int) (v_idx_129 Int) (v_idx_140 Int) (v_idx_141 Int) (v_idx_130 Int) (v_idx_133 Int) (v_idx_134 Int) (v_idx_142 Int) (v_idx_131 Int) (v_idx_143 Int) (v_idx_132 Int)) (exists ((v_b_212_1 Int) (v_v_1844_1 Int) (v_b_211_1 Int) (v_v_1854_1 Int) (v_b_210_1 Int) (v_v_1852_1 Int) (v_v_1848_1 Int) (v_v_1859_1 Int) (v_v_1858_1 Int) (v_v_1846_1 Int) (v_v_1856_1 Int) (v_v_1850_1 Int) (v_v_1860_1 Int) (v_b_209_1 Int) (v_b_208_1 Int) (v_b_207_1 Int) (v_b_206_1 Int) (v_b_205_1 Int) (v_b_204_1 Int) (v_b_203_1 Int) (v_b_213_1 Int) (v_b_202_1 Int)) (let ((.cse11 (+ v_b_207_1 2)) (.cse10 (+ v_b_202_1 2)) (.cse7 (+ v_b_208_1 2)) (.cse24 (+ v_b_205_1 4)) (.cse4 (+ v_b_206_1 3)) (.cse27 (+ v_b_202_1 3)) (.cse2 (+ v_b_204_1 1)) (.cse8 (+ c_ULTIMATE.start_main_p1 5)) (.cse19 (+ c_ULTIMATE.start_main_p1 2)) (.cse1 (+ c_ULTIMATE.start_main_p1 6)) (.cse36 (+ v_b_205_1 1)) (.cse35 (+ v_b_206_1 2)) (.cse25 (+ v_b_202_1 6)) (.cse32 (+ v_b_202_1 5)) (.cse29 (+ v_b_209_1 2)) (.cse23 (+ v_b_210_1 1)) (.cse31 (+ v_b_206_1 4)) (.cse21 (+ v_b_204_1 5)) (.cse0 (+ v_b_207_1 3)) (.cse14 (+ v_b_203_1 3)) (.cse22 (+ v_b_203_1 1)) (.cse38 (+ v_b_209_1 1)) (.cse6 (+ v_b_202_1 1)) (.cse15 (+ v_b_207_1 1)) (.cse26 (+ v_b_210_1 2)) (.cse17 (+ c_ULTIMATE.start_main_p1 7)) (.cse12 (+ v_b_212_1 1)) (.cse20 (+ v_b_203_1 5)) (.cse3 (+ v_b_203_1 4)) (.cse33 (+ c_ULTIMATE.start_main_p1 4)) (.cse39 (+ v_b_204_1 3)) (.cse18 (+ v_b_205_1 2)) (.cse13 (+ v_b_206_1 1)) (.cse28 (+ v_b_205_1 3)) (.cse9 (+ v_b_202_1 4)) (.cse5 (+ c_ULTIMATE.start_main_p1 1)) (.cse43 (+ v_b_208_1 3)) (.cse34 (+ v_b_204_1 2)) (.cse40 (+ c_ULTIMATE.start_main_p1 3)) (.cse42 (+ c_ULTIMATE.start_main_p8 1)) (.cse37 (+ v_b_208_1 1)) (.cse30 (+ v_b_203_1 2)) (.cse16 (+ v_b_204_1 4)) (.cse41 (+ v_b_211_1 1))) (and (<= v_b_213_1 c_ULTIMATE.start_main_p8) (or (= (select |c_#memory_int| v_idx_139) v_v_1856_1) (<= v_b_212_1 v_idx_139) (< v_idx_139 v_b_211_1)) (<= .cse0 v_b_213_1) (<= .cse1 v_b_212_1) (<= .cse2 v_b_206_1) (<= .cse3 v_b_212_1) (<= .cse2 v_b_205_1) (<= .cse4 v_b_211_1) (<= .cse5 v_b_202_1) (or (< v_idx_132 v_b_204_1) (<= v_b_205_1 v_idx_132) (= (select |c_#memory_int| v_idx_132) 0)) (<= .cse6 v_b_203_1) (<= .cse7 v_b_211_1) (<= v_b_207_1 v_b_208_1) (<= .cse8 v_b_210_1) (<= .cse9 v_b_210_1) (<= .cse10 v_b_206_1) (or (< v_idx_131 v_b_203_1) (<= v_b_204_1 v_idx_131) (= (select |c_#memory_int| v_idx_131) v_v_1848_1)) (<= .cse11 v_b_212_1) (<= .cse11 v_b_211_1) (<= .cse12 v_b_213_1) (or (<= v_b_210_1 v_idx_137) (= (select |c_#memory_int| v_idx_137) v_v_1854_1) (< v_idx_137 v_b_209_1)) (<= .cse13 v_b_208_1) (<= .cse14 v_b_210_1) (or (<= v_b_207_1 v_idx_134) (< v_idx_134 v_b_206_1) (= (select |c_#memory_int| v_idx_134) 0)) (<= .cse15 v_b_209_1) (<= .cse16 v_b_211_1) (<= .cse17 v_b_213_1) (<= .cse18 v_b_209_1) (<= .cse10 v_b_205_1) (<= .cse19 v_b_203_1) (<= .cse20 v_b_213_1) (<= v_b_203_1 .cse6) (<= .cse21 c_ULTIMATE.start_main_p8) (<= .cse22 v_b_206_1) (<= v_b_211_1 .cse23) (<= .cse24 c_ULTIMATE.start_main_p8) (<= .cse25 c_ULTIMATE.start_main_p8) (or (= (select |c_#memory_int| v_idx_141) v_v_1858_1) (<= c_ULTIMATE.start_main_p8 v_idx_141) (< v_idx_141 v_b_213_1)) (<= .cse26 v_b_213_1) (<= .cse7 v_b_212_1) (<= .cse27 v_b_207_1) (<= .cse24 v_b_213_1) (<= .cse4 v_b_212_1) (<= .cse28 v_b_212_1) (<= .cse27 v_b_208_1) (<= .cse29 c_ULTIMATE.start_main_p8) (<= v_v_1859_1 0) (<= .cse30 v_b_208_1) (<= .cse31 v_b_213_1) (<= v_b_205_1 .cse2) (or (< v_idx_135 v_b_207_1) (= (select |c_#memory_int| v_idx_135) v_v_1852_1) (<= v_b_208_1 v_idx_135)) (<= .cse13 v_b_207_1) (<= .cse8 v_b_209_1) (<= .cse32 v_b_211_1) (<= .cse33 v_b_208_1) (<= .cse34 v_b_208_1) (<= .cse35 v_b_210_1) (<= .cse19 v_b_204_1) (<= .cse1 v_b_211_1) (<= .cse23 v_b_212_1) (<= .cse36 v_b_207_1) (<= .cse36 v_b_208_1) (<= .cse35 v_b_209_1) (<= v_b_209_1 .cse37) (or (< v_idx_138 v_b_210_1) (= (select |c_#memory_int| v_idx_138) 0) (<= v_b_211_1 v_idx_138)) (<= .cse25 v_b_213_1) (<= .cse32 v_b_212_1) (<= .cse29 v_b_213_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_127) (= (select |c_#memory_int| v_idx_127) v_v_1844_1)) (or (= 0 (select |c_#memory_int| v_idx_140)) (< v_idx_140 v_b_212_1) (<= v_b_213_1 v_idx_140)) (<= .cse38 v_b_211_1) (<= .cse39 v_b_210_1) (<= .cse23 v_b_211_1) (<= .cse31 c_ULTIMATE.start_main_p8) (<= .cse21 v_b_213_1) (<= .cse40 v_b_206_1) (<= .cse0 c_ULTIMATE.start_main_p8) (<= .cse14 v_b_209_1) (<= .cse22 v_b_205_1) (or (<= .cse5 v_idx_128) (= (select |c_#memory_int| v_idx_128) 0) (< v_idx_128 c_ULTIMATE.start_main_p1)) (<= .cse41 v_b_213_1) (<= .cse38 v_b_212_1) (<= .cse6 v_b_204_1) (<= .cse15 v_b_210_1) (<= .cse26 c_ULTIMATE.start_main_p8) (or (<= v_b_203_1 v_idx_130) (= (select |c_#memory_int| v_idx_130) 0) (< v_idx_130 v_b_202_1)) (<= .cse17 c_ULTIMATE.start_main_p8) (<= v_b_211_1 v_b_212_1) (<= .cse12 c_ULTIMATE.start_main_p8) (<= v_b_213_1 .cse12) (<= v_b_203_1 v_b_204_1) (<= .cse20 c_ULTIMATE.start_main_p8) (<= .cse3 v_b_211_1) (<= (* 2 v_v_1859_1) 0) (or (<= v_b_206_1 v_idx_133) (= (select |c_#memory_int| v_idx_133) v_v_1850_1) (< v_idx_133 v_b_205_1)) (<= v_b_205_1 v_b_206_1) (<= .cse33 v_b_207_1) (<= .cse39 v_b_209_1) (or (< v_idx_142 c_ULTIMATE.start_main_p8) (<= .cse42 v_idx_142) (= (select |c_#memory_int| v_idx_142) v_v_1859_1)) (<= .cse18 v_b_210_1) (<= v_b_207_1 .cse13) (<= .cse43 c_ULTIMATE.start_main_p8) (<= .cse28 v_b_211_1) (<= .cse37 v_b_210_1) (<= .cse9 v_b_209_1) (or (<= v_b_209_1 v_idx_136) (= (select |c_#memory_int| v_idx_136) 0) (< v_idx_136 v_b_208_1)) (or (<= v_b_202_1 v_idx_129) (= (select |c_#memory_int| v_idx_129) v_v_1846_1) (< v_idx_129 .cse5)) (<= .cse43 v_b_213_1) (<= v_b_209_1 v_b_210_1) (<= .cse34 v_b_207_1) (<= .cse40 v_b_205_1) (or (= (select |c_#memory_int| v_idx_143) v_v_1860_1) (< v_idx_143 .cse42)) (<= .cse37 v_b_209_1) (<= .cse30 v_b_207_1) (<= .cse16 v_b_212_1) (<= .cse41 c_ULTIMATE.start_main_p8))))) is different from false [2019-01-11 11:45:29,853 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_148 Int) (v_idx_159 Int) (v_idx_149 Int) (v_idx_146 Int) (v_idx_157 Int) (v_idx_147 Int) (v_idx_158 Int) (v_idx_151 Int) (v_idx_152 Int) (v_idx_160 Int) (v_idx_150 Int) (v_idx_144 Int) (v_idx_155 Int) (v_idx_145 Int) (v_idx_156 Int) (v_idx_153 Int) (v_idx_154 Int)) (exists ((v_b_212_1 Int) (v_v_1844_1 Int) (v_b_211_1 Int) (v_v_1854_1 Int) (v_b_210_1 Int) (v_v_1852_1 Int) (v_v_1859_1 Int) (v_v_1848_1 Int) (v_v_1858_1 Int) (v_v_1846_1 Int) (v_v_1856_1 Int) (v_v_1850_1 Int) (v_v_1860_1 Int) (v_b_209_1 Int) (v_b_208_1 Int) (v_b_207_1 Int) (v_b_206_1 Int) (v_b_205_1 Int) (v_b_204_1 Int) (v_b_215_1 Int) (v_b_214_1 Int) (v_b_203_1 Int) (v_b_213_1 Int) (v_b_202_1 Int)) (let ((.cse16 (+ v_b_207_1 2)) (.cse15 (+ v_b_202_1 2)) (.cse3 (+ v_b_203_1 5)) (.cse11 (+ v_b_208_1 2)) (.cse7 (+ v_b_206_1 3)) (.cse30 (+ v_b_202_1 3)) (.cse32 (+ v_b_206_1 4)) (.cse5 (+ v_b_204_1 1)) (.cse12 (+ c_ULTIMATE.start_main_p1 5)) (.cse14 (+ v_b_214_1 1)) (.cse24 (+ c_ULTIMATE.start_main_p1 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 6)) (.cse39 (+ v_b_205_1 1)) (.cse38 (+ v_b_206_1 2)) (.cse25 (+ v_b_202_1 6)) (.cse35 (+ v_b_202_1 5)) (.cse2 (+ v_b_209_1 2)) (.cse1 (+ v_b_207_1 3)) (.cse27 (+ v_b_210_1 1)) (.cse9 (+ v_b_204_1 5)) (.cse31 (+ v_b_205_1 4)) (.cse19 (+ v_b_203_1 3)) (.cse26 (+ v_b_203_1 1)) (.cse29 (+ v_b_211_1 1)) (.cse41 (+ v_b_209_1 1)) (.cse10 (+ v_b_202_1 1)) (.cse20 (+ v_b_207_1 1)) (.cse28 (+ v_b_210_1 2)) (.cse17 (+ v_b_212_1 1)) (.cse6 (+ v_b_203_1 4)) (.cse36 (+ c_ULTIMATE.start_main_p1 4)) (.cse42 (+ v_b_204_1 3)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse23 (+ v_b_205_1 2)) (.cse18 (+ v_b_206_1 1)) (.cse33 (+ v_b_205_1 3)) (.cse13 (+ v_b_202_1 4)) (.cse22 (+ c_ULTIMATE.start_main_p1 7)) (.cse0 (+ v_b_208_1 3)) (.cse37 (+ v_b_204_1 2)) (.cse43 (+ c_ULTIMATE.start_main_p1 3)) (.cse40 (+ v_b_208_1 1)) (.cse34 (+ v_b_203_1 2)) (.cse21 (+ v_b_204_1 4))) (and (or (<= v_b_207_1 v_idx_151) (< v_idx_151 v_b_206_1) (= 0 (select |c_#memory_int| v_idx_151))) (or (= (select |c_#memory_int| v_idx_153) 0) (<= v_b_209_1 v_idx_153) (< v_idx_153 v_b_208_1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_144) (= (select |c_#memory_int| v_idx_144) v_v_1844_1)) (<= .cse0 v_b_214_1) (<= .cse1 v_b_213_1) (or (<= v_b_205_1 v_idx_149) (< v_idx_149 v_b_204_1) (= (select |c_#memory_int| v_idx_149) 0)) (<= .cse2 v_b_214_1) (<= .cse3 v_b_214_1) (<= .cse4 v_b_212_1) (<= (+ v_b_208_1 4) v_b_215_1) (<= .cse5 v_b_206_1) (<= .cse6 v_b_212_1) (<= (+ v_b_205_1 5) v_b_215_1) (<= .cse5 v_b_205_1) (<= .cse7 v_b_211_1) (<= .cse8 v_b_202_1) (<= .cse9 v_b_214_1) (<= .cse10 v_b_203_1) (<= .cse11 v_b_211_1) (<= (+ v_b_203_1 6) v_b_215_1) (<= v_b_207_1 v_b_208_1) (<= .cse12 v_b_210_1) (<= .cse13 v_b_210_1) (<= v_b_215_1 .cse14) (<= .cse15 v_b_206_1) (<= .cse16 v_b_212_1) (<= .cse16 v_b_211_1) (<= .cse17 v_b_213_1) (<= .cse18 v_b_208_1) (<= .cse19 v_b_210_1) (<= .cse20 v_b_209_1) (<= .cse21 v_b_211_1) (<= .cse22 v_b_213_1) (<= .cse23 v_b_209_1) (<= .cse15 v_b_205_1) (<= .cse24 v_b_203_1) (<= .cse3 v_b_213_1) (<= v_b_203_1 .cse10) (or (<= v_b_212_1 v_idx_156) (< v_idx_156 v_b_211_1) (= (select |c_#memory_int| v_idx_156) v_v_1856_1)) (<= (+ v_b_202_1 7) v_b_215_1) (or (<= .cse8 v_idx_145) (= 0 (select |c_#memory_int| v_idx_145)) (< v_idx_145 c_ULTIMATE.start_main_p1)) (<= .cse25 v_b_214_1) (<= .cse26 v_b_206_1) (<= v_b_211_1 .cse27) (<= .cse28 v_b_213_1) (<= .cse11 v_b_212_1) (<= .cse29 v_b_214_1) (or (< v_idx_150 v_b_205_1) (= (select |c_#memory_int| v_idx_150) v_v_1850_1) (<= v_b_206_1 v_idx_150)) (<= .cse30 v_b_207_1) (<= .cse31 v_b_213_1) (<= .cse7 v_b_212_1) (<= v_b_213_1 v_b_214_1) (<= .cse32 v_b_214_1) (<= .cse33 v_b_212_1) (<= (+ v_b_212_1 2) v_b_215_1) (<= .cse30 v_b_208_1) (<= v_v_1859_1 0) (<= .cse34 v_b_208_1) (<= (+ c_ULTIMATE.start_main_p1 8) v_b_215_1) (<= .cse32 v_b_213_1) (<= v_b_205_1 .cse5) (<= .cse18 v_b_207_1) (<= .cse12 v_b_209_1) (<= .cse14 v_b_215_1) (<= .cse35 v_b_211_1) (<= .cse36 v_b_208_1) (<= .cse37 v_b_208_1) (<= .cse38 v_b_210_1) (or (= (select |c_#memory_int| v_idx_147) 0) (< v_idx_147 v_b_202_1) (<= v_b_203_1 v_idx_147)) (<= (+ v_b_207_1 4) v_b_215_1) (<= .cse24 v_b_204_1) (<= .cse4 v_b_211_1) (<= .cse27 v_b_212_1) (<= .cse39 v_b_207_1) (<= .cse39 v_b_208_1) (<= .cse17 v_b_214_1) (<= .cse38 v_b_209_1) (<= v_b_209_1 .cse40) (<= .cse25 v_b_213_1) (<= .cse35 v_b_212_1) (or (< v_idx_154 v_b_209_1) (= (select |c_#memory_int| v_idx_154) v_v_1854_1) (<= v_b_210_1 v_idx_154)) (<= .cse2 v_b_213_1) (<= .cse1 v_b_214_1) (<= .cse41 v_b_211_1) (<= .cse42 v_b_210_1) (<= .cse27 v_b_211_1) (<= (+ v_b_211_1 2) v_b_215_1) (<= .cse9 v_b_213_1) (<= .cse31 v_b_214_1) (<= .cse43 v_b_206_1) (or (<= v_b_214_1 v_idx_158) (< v_idx_158 v_b_213_1) (= (select |c_#memory_int| v_idx_158) v_v_1858_1)) (<= (+ v_b_204_1 6) v_b_215_1) (or (< v_idx_157 v_b_212_1) (<= v_b_213_1 v_idx_157) (= (select |c_#memory_int| v_idx_157) 0)) (<= .cse19 v_b_209_1) (<= .cse26 v_b_205_1) (or (<= v_b_215_1 v_idx_159) (= (select |c_#memory_int| v_idx_159) v_v_1859_1) (< v_idx_159 v_b_214_1)) (or (<= v_b_204_1 v_idx_148) (= (select |c_#memory_int| v_idx_148) v_v_1848_1) (< v_idx_148 v_b_203_1)) (<= .cse29 v_b_213_1) (<= .cse41 v_b_212_1) (<= .cse10 v_b_204_1) (<= .cse20 v_b_210_1) (<= .cse28 v_b_214_1) (<= (+ v_b_206_1 5) v_b_215_1) (or (< v_idx_160 v_b_215_1) (= (select |c_#memory_int| v_idx_160) v_v_1860_1)) (<= v_b_211_1 v_b_212_1) (<= v_b_213_1 .cse17) (<= v_b_203_1 v_b_204_1) (<= .cse6 v_b_211_1) (<= (* 2 v_v_1859_1) 0) (<= v_b_205_1 v_b_206_1) (<= .cse36 v_b_207_1) (<= (+ v_b_210_1 3) v_b_215_1) (<= .cse42 v_b_209_1) (or (<= v_b_202_1 v_idx_146) (= (select |c_#memory_int| v_idx_146) v_v_1846_1) (< v_idx_146 .cse8)) (<= .cse23 v_b_210_1) (or (< v_idx_155 v_b_210_1) (<= v_b_211_1 v_idx_155) (= 0 (select |c_#memory_int| v_idx_155))) (<= v_b_207_1 .cse18) (<= .cse33 v_b_211_1) (<= (+ v_b_209_1 3) v_b_215_1) (<= .cse40 v_b_210_1) (<= .cse13 v_b_209_1) (<= .cse22 v_b_214_1) (<= .cse0 v_b_213_1) (<= v_b_209_1 v_b_210_1) (<= .cse37 v_b_207_1) (or (< v_idx_152 v_b_207_1) (<= v_b_208_1 v_idx_152) (= (select |c_#memory_int| v_idx_152) v_v_1852_1)) (<= (+ v_b_213_1 1) v_b_215_1) (<= .cse43 v_b_205_1) (<= .cse40 v_b_209_1) (<= .cse34 v_b_207_1) (<= .cse21 v_b_212_1))))) is different from false [2019-01-11 11:45:31,878 WARN L860 $PredicateComparison]: unable to prove that (forall ((v_idx_148 Int) (v_idx_159 Int) (v_idx_149 Int) (v_idx_146 Int) (v_idx_157 Int) (v_idx_147 Int) (v_idx_158 Int) (v_idx_151 Int) (v_idx_152 Int) (v_idx_160 Int) (v_idx_150 Int) (v_idx_144 Int) (v_idx_155 Int) (v_idx_145 Int) (v_idx_156 Int) (v_idx_153 Int) (v_idx_154 Int)) (exists ((v_b_212_1 Int) (v_v_1844_1 Int) (v_b_211_1 Int) (v_v_1854_1 Int) (v_b_210_1 Int) (v_v_1852_1 Int) (v_v_1859_1 Int) (v_v_1848_1 Int) (v_v_1858_1 Int) (v_v_1846_1 Int) (v_v_1856_1 Int) (v_v_1850_1 Int) (v_v_1860_1 Int) (v_b_209_1 Int) (v_b_208_1 Int) (v_b_207_1 Int) (v_b_206_1 Int) (v_b_205_1 Int) (v_b_204_1 Int) (v_b_215_1 Int) (v_b_214_1 Int) (v_b_203_1 Int) (v_b_213_1 Int) (v_b_202_1 Int)) (let ((.cse16 (+ v_b_207_1 2)) (.cse15 (+ v_b_202_1 2)) (.cse3 (+ v_b_203_1 5)) (.cse11 (+ v_b_208_1 2)) (.cse7 (+ v_b_206_1 3)) (.cse30 (+ v_b_202_1 3)) (.cse32 (+ v_b_206_1 4)) (.cse5 (+ v_b_204_1 1)) (.cse12 (+ c_ULTIMATE.start_main_p1 5)) (.cse14 (+ v_b_214_1 1)) (.cse24 (+ c_ULTIMATE.start_main_p1 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 6)) (.cse39 (+ v_b_205_1 1)) (.cse38 (+ v_b_206_1 2)) (.cse25 (+ v_b_202_1 6)) (.cse35 (+ v_b_202_1 5)) (.cse2 (+ v_b_209_1 2)) (.cse1 (+ v_b_207_1 3)) (.cse27 (+ v_b_210_1 1)) (.cse9 (+ v_b_204_1 5)) (.cse31 (+ v_b_205_1 4)) (.cse19 (+ v_b_203_1 3)) (.cse26 (+ v_b_203_1 1)) (.cse29 (+ v_b_211_1 1)) (.cse41 (+ v_b_209_1 1)) (.cse10 (+ v_b_202_1 1)) (.cse20 (+ v_b_207_1 1)) (.cse28 (+ v_b_210_1 2)) (.cse17 (+ v_b_212_1 1)) (.cse6 (+ v_b_203_1 4)) (.cse36 (+ c_ULTIMATE.start_main_p1 4)) (.cse42 (+ v_b_204_1 3)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse23 (+ v_b_205_1 2)) (.cse18 (+ v_b_206_1 1)) (.cse33 (+ v_b_205_1 3)) (.cse13 (+ v_b_202_1 4)) (.cse22 (+ c_ULTIMATE.start_main_p1 7)) (.cse0 (+ v_b_208_1 3)) (.cse37 (+ v_b_204_1 2)) (.cse43 (+ c_ULTIMATE.start_main_p1 3)) (.cse40 (+ v_b_208_1 1)) (.cse34 (+ v_b_203_1 2)) (.cse21 (+ v_b_204_1 4))) (and (or (<= v_b_207_1 v_idx_151) (< v_idx_151 v_b_206_1) (= 0 (select |c_#memory_int| v_idx_151))) (or (= (select |c_#memory_int| v_idx_153) 0) (<= v_b_209_1 v_idx_153) (< v_idx_153 v_b_208_1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_144) (= (select |c_#memory_int| v_idx_144) v_v_1844_1)) (<= .cse0 v_b_214_1) (<= .cse1 v_b_213_1) (or (<= v_b_205_1 v_idx_149) (< v_idx_149 v_b_204_1) (= (select |c_#memory_int| v_idx_149) 0)) (<= .cse2 v_b_214_1) (<= .cse3 v_b_214_1) (<= .cse4 v_b_212_1) (<= (+ v_b_208_1 4) v_b_215_1) (<= .cse5 v_b_206_1) (<= .cse6 v_b_212_1) (<= (+ v_b_205_1 5) v_b_215_1) (<= .cse5 v_b_205_1) (<= .cse7 v_b_211_1) (<= .cse8 v_b_202_1) (<= .cse9 v_b_214_1) (<= .cse10 v_b_203_1) (<= .cse11 v_b_211_1) (<= (+ v_b_203_1 6) v_b_215_1) (<= v_b_207_1 v_b_208_1) (<= .cse12 v_b_210_1) (<= .cse13 v_b_210_1) (<= v_b_215_1 .cse14) (<= .cse15 v_b_206_1) (<= .cse16 v_b_212_1) (<= .cse16 v_b_211_1) (<= .cse17 v_b_213_1) (<= .cse18 v_b_208_1) (<= .cse19 v_b_210_1) (<= .cse20 v_b_209_1) (<= .cse21 v_b_211_1) (<= .cse22 v_b_213_1) (<= .cse23 v_b_209_1) (<= .cse15 v_b_205_1) (<= .cse24 v_b_203_1) (<= .cse3 v_b_213_1) (<= v_b_203_1 .cse10) (or (<= v_b_212_1 v_idx_156) (< v_idx_156 v_b_211_1) (= (select |c_#memory_int| v_idx_156) v_v_1856_1)) (<= (+ v_b_202_1 7) v_b_215_1) (or (<= .cse8 v_idx_145) (= 0 (select |c_#memory_int| v_idx_145)) (< v_idx_145 c_ULTIMATE.start_main_p1)) (<= .cse25 v_b_214_1) (<= .cse26 v_b_206_1) (<= v_b_211_1 .cse27) (<= .cse28 v_b_213_1) (<= .cse11 v_b_212_1) (<= .cse29 v_b_214_1) (or (< v_idx_150 v_b_205_1) (= (select |c_#memory_int| v_idx_150) v_v_1850_1) (<= v_b_206_1 v_idx_150)) (<= .cse30 v_b_207_1) (<= .cse31 v_b_213_1) (<= .cse7 v_b_212_1) (<= v_b_213_1 v_b_214_1) (<= .cse32 v_b_214_1) (<= .cse33 v_b_212_1) (<= (+ v_b_212_1 2) v_b_215_1) (<= .cse30 v_b_208_1) (<= v_v_1859_1 0) (<= .cse34 v_b_208_1) (<= (+ c_ULTIMATE.start_main_p1 8) v_b_215_1) (<= .cse32 v_b_213_1) (<= v_b_205_1 .cse5) (<= .cse18 v_b_207_1) (<= .cse12 v_b_209_1) (<= .cse14 v_b_215_1) (<= .cse35 v_b_211_1) (<= .cse36 v_b_208_1) (<= .cse37 v_b_208_1) (<= .cse38 v_b_210_1) (or (= (select |c_#memory_int| v_idx_147) 0) (< v_idx_147 v_b_202_1) (<= v_b_203_1 v_idx_147)) (<= (+ v_b_207_1 4) v_b_215_1) (<= .cse24 v_b_204_1) (<= .cse4 v_b_211_1) (<= .cse27 v_b_212_1) (<= .cse39 v_b_207_1) (<= .cse39 v_b_208_1) (<= .cse17 v_b_214_1) (<= .cse38 v_b_209_1) (<= v_b_209_1 .cse40) (<= .cse25 v_b_213_1) (<= .cse35 v_b_212_1) (or (< v_idx_154 v_b_209_1) (= (select |c_#memory_int| v_idx_154) v_v_1854_1) (<= v_b_210_1 v_idx_154)) (<= .cse2 v_b_213_1) (<= .cse1 v_b_214_1) (<= .cse41 v_b_211_1) (<= .cse42 v_b_210_1) (<= .cse27 v_b_211_1) (<= (+ v_b_211_1 2) v_b_215_1) (<= .cse9 v_b_213_1) (<= .cse31 v_b_214_1) (<= .cse43 v_b_206_1) (or (<= v_b_214_1 v_idx_158) (< v_idx_158 v_b_213_1) (= (select |c_#memory_int| v_idx_158) v_v_1858_1)) (<= (+ v_b_204_1 6) v_b_215_1) (or (< v_idx_157 v_b_212_1) (<= v_b_213_1 v_idx_157) (= (select |c_#memory_int| v_idx_157) 0)) (<= .cse19 v_b_209_1) (<= .cse26 v_b_205_1) (or (<= v_b_215_1 v_idx_159) (= (select |c_#memory_int| v_idx_159) v_v_1859_1) (< v_idx_159 v_b_214_1)) (or (<= v_b_204_1 v_idx_148) (= (select |c_#memory_int| v_idx_148) v_v_1848_1) (< v_idx_148 v_b_203_1)) (<= .cse29 v_b_213_1) (<= .cse41 v_b_212_1) (<= .cse10 v_b_204_1) (<= .cse20 v_b_210_1) (<= .cse28 v_b_214_1) (<= (+ v_b_206_1 5) v_b_215_1) (or (< v_idx_160 v_b_215_1) (= (select |c_#memory_int| v_idx_160) v_v_1860_1)) (<= v_b_211_1 v_b_212_1) (<= v_b_213_1 .cse17) (<= v_b_203_1 v_b_204_1) (<= .cse6 v_b_211_1) (<= (* 2 v_v_1859_1) 0) (<= v_b_205_1 v_b_206_1) (<= .cse36 v_b_207_1) (<= (+ v_b_210_1 3) v_b_215_1) (<= .cse42 v_b_209_1) (or (<= v_b_202_1 v_idx_146) (= (select |c_#memory_int| v_idx_146) v_v_1846_1) (< v_idx_146 .cse8)) (<= .cse23 v_b_210_1) (or (< v_idx_155 v_b_210_1) (<= v_b_211_1 v_idx_155) (= 0 (select |c_#memory_int| v_idx_155))) (<= v_b_207_1 .cse18) (<= .cse33 v_b_211_1) (<= (+ v_b_209_1 3) v_b_215_1) (<= .cse40 v_b_210_1) (<= .cse13 v_b_209_1) (<= .cse22 v_b_214_1) (<= .cse0 v_b_213_1) (<= v_b_209_1 v_b_210_1) (<= .cse37 v_b_207_1) (or (< v_idx_152 v_b_207_1) (<= v_b_208_1 v_idx_152) (= (select |c_#memory_int| v_idx_152) v_v_1852_1)) (<= (+ v_b_213_1 1) v_b_215_1) (<= .cse43 v_b_205_1) (<= .cse40 v_b_209_1) (<= .cse34 v_b_207_1) (<= .cse21 v_b_212_1))))) is different from true [2019-01-11 11:45:31,880 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:45:31,881 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:45:31,882 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:45:31,882 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:45:31,882 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:45:31,884 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:45:31,884 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:45:31,884 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=2, Unknown=3, NotChecked=2, Total=12 [2019-01-11 11:45:31,885 INFO L87 Difference]: Start difference. First operand 18 states and 33 transitions. Second operand 4 states. [2019-01-11 11:45:35,157 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_148 Int) (v_idx_159 Int) (v_idx_149 Int) (v_idx_146 Int) (v_idx_157 Int) (v_idx_147 Int) (v_idx_158 Int) (v_idx_151 Int) (v_idx_152 Int) (v_idx_160 Int) (v_idx_150 Int) (v_idx_144 Int) (v_idx_155 Int) (v_idx_145 Int) (v_idx_156 Int) (v_idx_153 Int) (v_idx_154 Int)) (exists ((v_b_212_1 Int) (v_v_1844_1 Int) (v_b_211_1 Int) (v_v_1854_1 Int) (v_b_210_1 Int) (v_v_1852_1 Int) (v_v_1859_1 Int) (v_v_1848_1 Int) (v_v_1858_1 Int) (v_v_1846_1 Int) (v_v_1856_1 Int) (v_v_1850_1 Int) (v_v_1860_1 Int) (v_b_209_1 Int) (v_b_208_1 Int) (v_b_207_1 Int) (v_b_206_1 Int) (v_b_205_1 Int) (v_b_204_1 Int) (v_b_215_1 Int) (v_b_214_1 Int) (v_b_203_1 Int) (v_b_213_1 Int) (v_b_202_1 Int)) (let ((.cse16 (+ v_b_207_1 2)) (.cse15 (+ v_b_202_1 2)) (.cse3 (+ v_b_203_1 5)) (.cse11 (+ v_b_208_1 2)) (.cse7 (+ v_b_206_1 3)) (.cse30 (+ v_b_202_1 3)) (.cse32 (+ v_b_206_1 4)) (.cse5 (+ v_b_204_1 1)) (.cse12 (+ c_ULTIMATE.start_main_p1 5)) (.cse14 (+ v_b_214_1 1)) (.cse24 (+ c_ULTIMATE.start_main_p1 2)) (.cse4 (+ c_ULTIMATE.start_main_p1 6)) (.cse39 (+ v_b_205_1 1)) (.cse38 (+ v_b_206_1 2)) (.cse25 (+ v_b_202_1 6)) (.cse35 (+ v_b_202_1 5)) (.cse2 (+ v_b_209_1 2)) (.cse1 (+ v_b_207_1 3)) (.cse27 (+ v_b_210_1 1)) (.cse9 (+ v_b_204_1 5)) (.cse31 (+ v_b_205_1 4)) (.cse19 (+ v_b_203_1 3)) (.cse26 (+ v_b_203_1 1)) (.cse29 (+ v_b_211_1 1)) (.cse41 (+ v_b_209_1 1)) (.cse10 (+ v_b_202_1 1)) (.cse20 (+ v_b_207_1 1)) (.cse28 (+ v_b_210_1 2)) (.cse17 (+ v_b_212_1 1)) (.cse6 (+ v_b_203_1 4)) (.cse36 (+ c_ULTIMATE.start_main_p1 4)) (.cse42 (+ v_b_204_1 3)) (.cse8 (+ c_ULTIMATE.start_main_p1 1)) (.cse23 (+ v_b_205_1 2)) (.cse18 (+ v_b_206_1 1)) (.cse33 (+ v_b_205_1 3)) (.cse13 (+ v_b_202_1 4)) (.cse22 (+ c_ULTIMATE.start_main_p1 7)) (.cse0 (+ v_b_208_1 3)) (.cse37 (+ v_b_204_1 2)) (.cse43 (+ c_ULTIMATE.start_main_p1 3)) (.cse40 (+ v_b_208_1 1)) (.cse34 (+ v_b_203_1 2)) (.cse21 (+ v_b_204_1 4))) (and (or (<= v_b_207_1 v_idx_151) (< v_idx_151 v_b_206_1) (= 0 (select |c_#memory_int| v_idx_151))) (or (= (select |c_#memory_int| v_idx_153) 0) (<= v_b_209_1 v_idx_153) (< v_idx_153 v_b_208_1)) (or (<= c_ULTIMATE.start_main_p1 v_idx_144) (= (select |c_#memory_int| v_idx_144) v_v_1844_1)) (<= .cse0 v_b_214_1) (<= .cse1 v_b_213_1) (or (<= v_b_205_1 v_idx_149) (< v_idx_149 v_b_204_1) (= (select |c_#memory_int| v_idx_149) 0)) (<= .cse2 v_b_214_1) (<= .cse3 v_b_214_1) (<= .cse4 v_b_212_1) (<= (+ v_b_208_1 4) v_b_215_1) (<= .cse5 v_b_206_1) (<= .cse6 v_b_212_1) (<= (+ v_b_205_1 5) v_b_215_1) (<= .cse5 v_b_205_1) (<= .cse7 v_b_211_1) (<= .cse8 v_b_202_1) (<= .cse9 v_b_214_1) (<= .cse10 v_b_203_1) (<= .cse11 v_b_211_1) (<= (+ v_b_203_1 6) v_b_215_1) (<= v_b_207_1 v_b_208_1) (<= .cse12 v_b_210_1) (<= .cse13 v_b_210_1) (<= v_b_215_1 .cse14) (<= .cse15 v_b_206_1) (<= .cse16 v_b_212_1) (<= .cse16 v_b_211_1) (<= .cse17 v_b_213_1) (<= .cse18 v_b_208_1) (<= .cse19 v_b_210_1) (<= .cse20 v_b_209_1) (<= .cse21 v_b_211_1) (<= .cse22 v_b_213_1) (<= .cse23 v_b_209_1) (<= .cse15 v_b_205_1) (<= .cse24 v_b_203_1) (<= .cse3 v_b_213_1) (<= v_b_203_1 .cse10) (or (<= v_b_212_1 v_idx_156) (< v_idx_156 v_b_211_1) (= (select |c_#memory_int| v_idx_156) v_v_1856_1)) (<= (+ v_b_202_1 7) v_b_215_1) (or (<= .cse8 v_idx_145) (= 0 (select |c_#memory_int| v_idx_145)) (< v_idx_145 c_ULTIMATE.start_main_p1)) (<= .cse25 v_b_214_1) (<= .cse26 v_b_206_1) (<= v_b_211_1 .cse27) (<= .cse28 v_b_213_1) (<= .cse11 v_b_212_1) (<= .cse29 v_b_214_1) (or (< v_idx_150 v_b_205_1) (= (select |c_#memory_int| v_idx_150) v_v_1850_1) (<= v_b_206_1 v_idx_150)) (<= .cse30 v_b_207_1) (<= .cse31 v_b_213_1) (<= .cse7 v_b_212_1) (<= v_b_213_1 v_b_214_1) (<= .cse32 v_b_214_1) (<= .cse33 v_b_212_1) (<= (+ v_b_212_1 2) v_b_215_1) (<= .cse30 v_b_208_1) (<= v_v_1859_1 0) (<= .cse34 v_b_208_1) (<= (+ c_ULTIMATE.start_main_p1 8) v_b_215_1) (<= .cse32 v_b_213_1) (<= v_b_205_1 .cse5) (<= .cse18 v_b_207_1) (<= .cse12 v_b_209_1) (<= .cse14 v_b_215_1) (<= .cse35 v_b_211_1) (<= .cse36 v_b_208_1) (<= .cse37 v_b_208_1) (<= .cse38 v_b_210_1) (or (= (select |c_#memory_int| v_idx_147) 0) (< v_idx_147 v_b_202_1) (<= v_b_203_1 v_idx_147)) (<= (+ v_b_207_1 4) v_b_215_1) (<= .cse24 v_b_204_1) (<= .cse4 v_b_211_1) (<= .cse27 v_b_212_1) (<= .cse39 v_b_207_1) (<= .cse39 v_b_208_1) (<= .cse17 v_b_214_1) (<= .cse38 v_b_209_1) (<= v_b_209_1 .cse40) (<= .cse25 v_b_213_1) (<= .cse35 v_b_212_1) (or (< v_idx_154 v_b_209_1) (= (select |c_#memory_int| v_idx_154) v_v_1854_1) (<= v_b_210_1 v_idx_154)) (<= .cse2 v_b_213_1) (<= .cse1 v_b_214_1) (<= .cse41 v_b_211_1) (<= .cse42 v_b_210_1) (<= .cse27 v_b_211_1) (<= (+ v_b_211_1 2) v_b_215_1) (<= .cse9 v_b_213_1) (<= .cse31 v_b_214_1) (<= .cse43 v_b_206_1) (or (<= v_b_214_1 v_idx_158) (< v_idx_158 v_b_213_1) (= (select |c_#memory_int| v_idx_158) v_v_1858_1)) (<= (+ v_b_204_1 6) v_b_215_1) (or (< v_idx_157 v_b_212_1) (<= v_b_213_1 v_idx_157) (= (select |c_#memory_int| v_idx_157) 0)) (<= .cse19 v_b_209_1) (<= .cse26 v_b_205_1) (or (<= v_b_215_1 v_idx_159) (= (select |c_#memory_int| v_idx_159) v_v_1859_1) (< v_idx_159 v_b_214_1)) (or (<= v_b_204_1 v_idx_148) (= (select |c_#memory_int| v_idx_148) v_v_1848_1) (< v_idx_148 v_b_203_1)) (<= .cse29 v_b_213_1) (<= .cse41 v_b_212_1) (<= .cse10 v_b_204_1) (<= .cse20 v_b_210_1) (<= .cse28 v_b_214_1) (<= (+ v_b_206_1 5) v_b_215_1) (or (< v_idx_160 v_b_215_1) (= (select |c_#memory_int| v_idx_160) v_v_1860_1)) (<= v_b_211_1 v_b_212_1) (<= v_b_213_1 .cse17) (<= v_b_203_1 v_b_204_1) (<= .cse6 v_b_211_1) (<= (* 2 v_v_1859_1) 0) (<= v_b_205_1 v_b_206_1) (<= .cse36 v_b_207_1) (<= (+ v_b_210_1 3) v_b_215_1) (<= .cse42 v_b_209_1) (or (<= v_b_202_1 v_idx_146) (= (select |c_#memory_int| v_idx_146) v_v_1846_1) (< v_idx_146 .cse8)) (<= .cse23 v_b_210_1) (or (< v_idx_155 v_b_210_1) (<= v_b_211_1 v_idx_155) (= 0 (select |c_#memory_int| v_idx_155))) (<= v_b_207_1 .cse18) (<= .cse33 v_b_211_1) (<= (+ v_b_209_1 3) v_b_215_1) (<= .cse40 v_b_210_1) (<= .cse13 v_b_209_1) (<= .cse22 v_b_214_1) (<= .cse0 v_b_213_1) (<= v_b_209_1 v_b_210_1) (<= .cse37 v_b_207_1) (or (< v_idx_152 v_b_207_1) (<= v_b_208_1 v_idx_152) (= (select |c_#memory_int| v_idx_152) v_v_1852_1)) (<= (+ v_b_213_1 1) v_b_215_1) (<= .cse43 v_b_205_1) (<= .cse40 v_b_209_1) (<= .cse34 v_b_207_1) (<= .cse21 v_b_212_1))))) (forall ((v_idx_137 Int) (v_idx_127 Int) (v_idx_138 Int) (v_idx_135 Int) (v_idx_136 Int) (v_idx_128 Int) (v_idx_139 Int) (v_idx_129 Int) (v_idx_140 Int) (v_idx_141 Int) (v_idx_130 Int) (v_idx_133 Int) (v_idx_134 Int) (v_idx_142 Int) (v_idx_131 Int) (v_idx_143 Int) (v_idx_132 Int)) (exists ((v_b_212_1 Int) (v_v_1844_1 Int) (v_b_211_1 Int) (v_v_1854_1 Int) (v_b_210_1 Int) (v_v_1852_1 Int) (v_v_1848_1 Int) (v_v_1859_1 Int) (v_v_1858_1 Int) (v_v_1846_1 Int) (v_v_1856_1 Int) (v_v_1850_1 Int) (v_v_1860_1 Int) (v_b_209_1 Int) (v_b_208_1 Int) (v_b_207_1 Int) (v_b_206_1 Int) (v_b_205_1 Int) (v_b_204_1 Int) (v_b_203_1 Int) (v_b_213_1 Int) (v_b_202_1 Int)) (let ((.cse55 (+ v_b_207_1 2)) (.cse54 (+ v_b_202_1 2)) (.cse51 (+ v_b_208_1 2)) (.cse68 (+ v_b_205_1 4)) (.cse48 (+ v_b_206_1 3)) (.cse71 (+ v_b_202_1 3)) (.cse46 (+ v_b_204_1 1)) (.cse52 (+ c_ULTIMATE.start_main_p1 5)) (.cse63 (+ c_ULTIMATE.start_main_p1 2)) (.cse45 (+ c_ULTIMATE.start_main_p1 6)) (.cse80 (+ v_b_205_1 1)) (.cse79 (+ v_b_206_1 2)) (.cse69 (+ v_b_202_1 6)) (.cse76 (+ v_b_202_1 5)) (.cse73 (+ v_b_209_1 2)) (.cse67 (+ v_b_210_1 1)) (.cse75 (+ v_b_206_1 4)) (.cse65 (+ v_b_204_1 5)) (.cse44 (+ v_b_207_1 3)) (.cse58 (+ v_b_203_1 3)) (.cse66 (+ v_b_203_1 1)) (.cse82 (+ v_b_209_1 1)) (.cse50 (+ v_b_202_1 1)) (.cse59 (+ v_b_207_1 1)) (.cse70 (+ v_b_210_1 2)) (.cse61 (+ c_ULTIMATE.start_main_p1 7)) (.cse56 (+ v_b_212_1 1)) (.cse64 (+ v_b_203_1 5)) (.cse47 (+ v_b_203_1 4)) (.cse77 (+ c_ULTIMATE.start_main_p1 4)) (.cse83 (+ v_b_204_1 3)) (.cse62 (+ v_b_205_1 2)) (.cse57 (+ v_b_206_1 1)) (.cse72 (+ v_b_205_1 3)) (.cse53 (+ v_b_202_1 4)) (.cse49 (+ c_ULTIMATE.start_main_p1 1)) (.cse87 (+ v_b_208_1 3)) (.cse78 (+ v_b_204_1 2)) (.cse84 (+ c_ULTIMATE.start_main_p1 3)) (.cse86 (+ c_ULTIMATE.start_main_p8 1)) (.cse81 (+ v_b_208_1 1)) (.cse74 (+ v_b_203_1 2)) (.cse60 (+ v_b_204_1 4)) (.cse85 (+ v_b_211_1 1))) (and (<= v_b_213_1 c_ULTIMATE.start_main_p8) (or (= (select |c_#memory_int| v_idx_139) v_v_1856_1) (<= v_b_212_1 v_idx_139) (< v_idx_139 v_b_211_1)) (<= .cse44 v_b_213_1) (<= .cse45 v_b_212_1) (<= .cse46 v_b_206_1) (<= .cse47 v_b_212_1) (<= .cse46 v_b_205_1) (<= .cse48 v_b_211_1) (<= .cse49 v_b_202_1) (or (< v_idx_132 v_b_204_1) (<= v_b_205_1 v_idx_132) (= (select |c_#memory_int| v_idx_132) 0)) (<= .cse50 v_b_203_1) (<= .cse51 v_b_211_1) (<= v_b_207_1 v_b_208_1) (<= .cse52 v_b_210_1) (<= .cse53 v_b_210_1) (<= .cse54 v_b_206_1) (or (< v_idx_131 v_b_203_1) (<= v_b_204_1 v_idx_131) (= (select |c_#memory_int| v_idx_131) v_v_1848_1)) (<= .cse55 v_b_212_1) (<= .cse55 v_b_211_1) (<= .cse56 v_b_213_1) (or (<= v_b_210_1 v_idx_137) (= (select |c_#memory_int| v_idx_137) v_v_1854_1) (< v_idx_137 v_b_209_1)) (<= .cse57 v_b_208_1) (<= .cse58 v_b_210_1) (or (<= v_b_207_1 v_idx_134) (< v_idx_134 v_b_206_1) (= (select |c_#memory_int| v_idx_134) 0)) (<= .cse59 v_b_209_1) (<= .cse60 v_b_211_1) (<= .cse61 v_b_213_1) (<= .cse62 v_b_209_1) (<= .cse54 v_b_205_1) (<= .cse63 v_b_203_1) (<= .cse64 v_b_213_1) (<= v_b_203_1 .cse50) (<= .cse65 c_ULTIMATE.start_main_p8) (<= .cse66 v_b_206_1) (<= v_b_211_1 .cse67) (<= .cse68 c_ULTIMATE.start_main_p8) (<= .cse69 c_ULTIMATE.start_main_p8) (or (= (select |c_#memory_int| v_idx_141) v_v_1858_1) (<= c_ULTIMATE.start_main_p8 v_idx_141) (< v_idx_141 v_b_213_1)) (<= .cse70 v_b_213_1) (<= .cse51 v_b_212_1) (<= .cse71 v_b_207_1) (<= .cse68 v_b_213_1) (<= .cse48 v_b_212_1) (<= .cse72 v_b_212_1) (<= .cse71 v_b_208_1) (<= .cse73 c_ULTIMATE.start_main_p8) (<= v_v_1859_1 0) (<= .cse74 v_b_208_1) (<= .cse75 v_b_213_1) (<= v_b_205_1 .cse46) (or (< v_idx_135 v_b_207_1) (= (select |c_#memory_int| v_idx_135) v_v_1852_1) (<= v_b_208_1 v_idx_135)) (<= .cse57 v_b_207_1) (<= .cse52 v_b_209_1) (<= .cse76 v_b_211_1) (<= .cse77 v_b_208_1) (<= .cse78 v_b_208_1) (<= .cse79 v_b_210_1) (<= .cse63 v_b_204_1) (<= .cse45 v_b_211_1) (<= .cse67 v_b_212_1) (<= .cse80 v_b_207_1) (<= .cse80 v_b_208_1) (<= .cse79 v_b_209_1) (<= v_b_209_1 .cse81) (or (< v_idx_138 v_b_210_1) (= (select |c_#memory_int| v_idx_138) 0) (<= v_b_211_1 v_idx_138)) (<= .cse69 v_b_213_1) (<= .cse76 v_b_212_1) (<= .cse73 v_b_213_1) (or (<= c_ULTIMATE.start_main_p1 v_idx_127) (= (select |c_#memory_int| v_idx_127) v_v_1844_1)) (or (= 0 (select |c_#memory_int| v_idx_140)) (< v_idx_140 v_b_212_1) (<= v_b_213_1 v_idx_140)) (<= .cse82 v_b_211_1) (<= .cse83 v_b_210_1) (<= .cse67 v_b_211_1) (<= .cse75 c_ULTIMATE.start_main_p8) (<= .cse65 v_b_213_1) (<= .cse84 v_b_206_1) (<= .cse44 c_ULTIMATE.start_main_p8) (<= .cse58 v_b_209_1) (<= .cse66 v_b_205_1) (or (<= .cse49 v_idx_128) (= (select |c_#memory_int| v_idx_128) 0) (< v_idx_128 c_ULTIMATE.start_main_p1)) (<= .cse85 v_b_213_1) (<= .cse82 v_b_212_1) (<= .cse50 v_b_204_1) (<= .cse59 v_b_210_1) (<= .cse70 c_ULTIMATE.start_main_p8) (or (<= v_b_203_1 v_idx_130) (= (select |c_#memory_int| v_idx_130) 0) (< v_idx_130 v_b_202_1)) (<= .cse61 c_ULTIMATE.start_main_p8) (<= v_b_211_1 v_b_212_1) (<= .cse56 c_ULTIMATE.start_main_p8) (<= v_b_213_1 .cse56) (<= v_b_203_1 v_b_204_1) (<= .cse64 c_ULTIMATE.start_main_p8) (<= .cse47 v_b_211_1) (<= (* 2 v_v_1859_1) 0) (or (<= v_b_206_1 v_idx_133) (= (select |c_#memory_int| v_idx_133) v_v_1850_1) (< v_idx_133 v_b_205_1)) (<= v_b_205_1 v_b_206_1) (<= .cse77 v_b_207_1) (<= .cse83 v_b_209_1) (or (< v_idx_142 c_ULTIMATE.start_main_p8) (<= .cse86 v_idx_142) (= (select |c_#memory_int| v_idx_142) v_v_1859_1)) (<= .cse62 v_b_210_1) (<= v_b_207_1 .cse57) (<= .cse87 c_ULTIMATE.start_main_p8) (<= .cse72 v_b_211_1) (<= .cse81 v_b_210_1) (<= .cse53 v_b_209_1) (or (<= v_b_209_1 v_idx_136) (= (select |c_#memory_int| v_idx_136) 0) (< v_idx_136 v_b_208_1)) (or (<= v_b_202_1 v_idx_129) (= (select |c_#memory_int| v_idx_129) v_v_1846_1) (< v_idx_129 .cse49)) (<= .cse87 v_b_213_1) (<= v_b_209_1 v_b_210_1) (<= .cse78 v_b_207_1) (<= .cse84 v_b_205_1) (or (= (select |c_#memory_int| v_idx_143) v_v_1860_1) (< v_idx_143 .cse86)) (<= .cse81 v_b_209_1) (<= .cse74 v_b_207_1) (<= .cse60 v_b_212_1) (<= .cse85 c_ULTIMATE.start_main_p8)))))) is different from false [2019-01-11 11:46:32,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:46:32,770 INFO L93 Difference]: Finished difference Result 20 states and 43 transitions. [2019-01-11 11:46:32,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:46:32,771 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:46:32,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:46:32,772 INFO L225 Difference]: With dead ends: 20 [2019-01-11 11:46:32,772 INFO L226 Difference]: Without dead ends: 19 [2019-01-11 11:46:32,773 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 9.7s TimeCoverageRelationStatistics Valid=7, Invalid=3, Unknown=4, NotChecked=6, Total=20 [2019-01-11 11:46:32,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2019-01-11 11:46:32,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2019-01-11 11:46:32,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2019-01-11 11:46:32,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 42 transitions. [2019-01-11 11:46:32,782 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 42 transitions. Word has length 3 [2019-01-11 11:46:32,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:46:32,783 INFO L480 AbstractCegarLoop]: Abstraction has 19 states and 42 transitions. [2019-01-11 11:46:32,783 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:46:32,783 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 42 transitions. [2019-01-11 11:46:32,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:46:32,784 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:46:32,784 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:46:32,785 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr7ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:46:32,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:46:32,785 INFO L82 PathProgramCache]: Analyzing trace with hash 30384, now seen corresponding path program 1 times [2019-01-11 11:46:32,786 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:46:32,787 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:46:32,787 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:46:32,787 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:46:32,787 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:46:32,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:46:32,943 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:46:32,943 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:46:32,943 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:46:32,943 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:46:32,944 INFO L207 CegarAbsIntRunner]: [0], [18], [35] [2019-01-11 11:46:32,946 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:46:32,946 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:46:50,828 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:46:50,829 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:46:50,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:46:50,829 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:46:51,596 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 79.17% of their original sizes. [2019-01-11 11:46:51,596 INFO L418 sIntCurrentIteration]: Unifying AI predicates [2019-01-11 11:46:54,443 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_290 Int) (v_idx_291 Int) (v_idx_302 Int) (v_idx_303 Int) (v_idx_300 Int) (v_idx_289 Int) (v_idx_301 Int) (v_idx_294 Int) (v_idx_295 Int) (v_idx_292 Int) (v_idx_293 Int) (v_idx_287 Int) (v_idx_298 Int) (v_idx_288 Int) (v_idx_299 Int) (v_idx_296 Int) (v_idx_297 Int)) (exists ((v_b_211_2 Int) (v_v_1896_2 Int) (v_b_210_2 Int) (v_v_1898_2 Int) (v_v_1908_2 Int) (v_v_1906_2 Int) (v_v_1904_2 Int) (v_v_1894_2 Int) (v_v_1902_2 Int) (v_v_1901_2 Int) (v_v_1900_2 Int) (v_v_1910_2 Int) (v_b_209_2 Int) (v_b_208_2 Int) (v_b_205_2 Int) (v_b_215_2 Int) (v_b_204_2 Int) (v_b_203_2 Int) (v_b_214_2 Int) (v_b_213_2 Int) (v_b_202_2 Int) (v_b_212_2 Int)) (let ((.cse0 (+ v_b_203_2 1)) (.cse5 (+ v_b_204_2 5)) (.cse12 (+ v_b_202_2 2)) (.cse10 (+ c_ULTIMATE.start_main_p4 2)) (.cse15 (+ v_b_208_2 3)) (.cse17 (+ c_ULTIMATE.start_main_p1 2)) (.cse3 (+ v_b_205_2 2)) (.cse1 (+ c_ULTIMATE.start_main_p4 4)) (.cse14 (+ v_b_203_2 3)) (.cse9 (+ v_b_210_2 1)) (.cse11 (+ v_b_212_2 1)) (.cse26 (+ v_b_205_2 4)) (.cse21 (+ v_b_202_2 6)) (.cse29 (+ v_b_204_2 4)) (.cse18 (+ c_ULTIMATE.start_main_p1 3)) (.cse8 (+ v_b_202_2 4)) (.cse30 (+ v_b_209_2 2)) (.cse2 (+ v_b_202_2 1)) (.cse13 (+ c_ULTIMATE.start_main_p1 6)) (.cse22 (+ v_b_203_2 5)) (.cse6 (+ v_b_203_2 4)) (.cse19 (+ c_ULTIMATE.start_main_p1 7)) (.cse7 (+ v_b_205_2 3)) (.cse20 (+ v_b_202_2 5)) (.cse24 (+ c_ULTIMATE.start_main_p4 1)) (.cse32 (+ v_b_209_2 1)) (.cse33 (+ v_b_204_2 3)) (.cse16 (+ c_ULTIMATE.start_main_p4 3)) (.cse25 (+ c_ULTIMATE.start_main_p1 1)) (.cse28 (+ v_b_208_2 1)) (.cse31 (+ c_ULTIMATE.start_main_p1 5)) (.cse23 (+ v_b_204_2 1)) (.cse35 (+ v_b_211_2 1)) (.cse34 (+ v_b_208_2 2)) (.cse27 (+ v_b_210_2 2)) (.cse4 (+ v_b_214_2 1))) (and (<= .cse0 c_ULTIMATE.start_main_p4) (<= .cse1 v_b_213_2) (<= v_b_203_2 .cse2) (<= (+ v_b_205_2 5) v_b_215_2) (<= .cse3 v_b_210_2) (<= (+ v_b_203_2 2) v_b_208_2) (<= v_b_215_2 .cse4) (<= .cse5 v_b_213_2) (<= .cse6 v_b_211_2) (<= .cse7 v_b_211_2) (or (= 0 (select |c_#memory_int| v_idx_290)) (<= v_b_203_2 v_idx_290) (< v_idx_290 v_b_202_2)) (<= .cse8 v_b_210_2) (<= .cse9 v_b_211_2) (<= .cse10 v_b_209_2) (<= .cse11 v_b_214_2) (<= v_b_211_2 .cse9) (<= (+ v_b_202_2 3) v_b_208_2) (<= .cse0 v_b_205_2) (<= .cse12 v_b_205_2) (<= .cse13 v_b_211_2) (or (<= v_b_205_2 v_idx_292) (< v_idx_292 v_b_204_2) (= 0 (select |c_#memory_int| v_idx_292))) (<= .cse14 v_b_210_2) (<= (+ c_ULTIMATE.start_main_p1 8) v_b_215_2) (<= .cse15 v_b_213_2) (<= .cse16 v_b_211_2) (<= v_b_203_2 v_b_204_2) (<= (+ v_b_202_2 7) v_b_215_2) (<= .cse17 v_b_203_2) (or (< v_idx_299 v_b_211_2) (<= v_b_212_2 v_idx_299) (= (select |c_#memory_int| v_idx_299) v_v_1906_2)) (<= (+ v_b_203_2 6) v_b_215_2) (<= v_b_213_2 .cse11) (<= .cse18 c_ULTIMATE.start_main_p4) (<= .cse5 v_b_214_2) (<= .cse19 v_b_213_2) (<= .cse20 v_b_211_2) (<= .cse12 c_ULTIMATE.start_main_p4) (<= .cse10 v_b_210_2) (<= .cse21 v_b_214_2) (<= .cse22 v_b_213_2) (or (= (select |c_#memory_int| v_idx_301) v_v_1908_2) (< v_idx_301 v_b_213_2) (<= v_b_214_2 v_idx_301)) (<= (+ v_b_211_2 2) v_b_215_2) (<= .cse15 v_b_214_2) (<= .cse17 v_b_204_2) (<= (+ c_ULTIMATE.start_main_p4 5) v_b_215_2) (<= (+ v_b_204_2 2) v_b_208_2) (<= .cse23 c_ULTIMATE.start_main_p4) (or (<= v_b_208_2 v_idx_295) (= (select |c_#memory_int| v_idx_295) v_v_1902_2) (< v_idx_295 .cse24)) (<= .cse3 v_b_209_2) (<= .cse25 v_b_202_2) (<= .cse26 v_b_214_2) (<= v_v_1901_2 0) (<= .cse1 v_b_214_2) (<= .cse23 v_b_205_2) (<= v_b_209_2 v_b_210_2) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_208_2) (<= v_b_213_2 v_b_214_2) (<= (+ v_b_204_2 6) v_b_215_2) (<= (+ v_b_210_2 3) v_b_215_2) (<= .cse27 v_b_213_2) (<= v_b_209_2 .cse28) (<= .cse29 v_b_211_2) (or (= (select |c_#memory_int| v_idx_297) v_v_1904_2) (< v_idx_297 v_b_209_2) (<= v_b_210_2 v_idx_297)) (<= .cse30 v_b_213_2) (<= .cse14 v_b_209_2) (<= .cse2 v_b_204_2) (or (= (select |c_#memory_int| v_idx_303) v_v_1910_2) (< v_idx_303 v_b_215_2)) (<= .cse9 v_b_212_2) (<= (+ v_b_212_2 2) v_b_215_2) (or (< v_idx_302 v_b_214_2) (<= v_b_215_2 v_idx_302) (= 0 (select |c_#memory_int| v_idx_302))) (or (= (select |c_#memory_int| v_idx_300) 0) (< v_idx_300 v_b_212_2) (<= v_b_213_2 v_idx_300)) (<= .cse11 v_b_213_2) (or (= (select |c_#memory_int| v_idx_294) v_v_1901_2) (< v_idx_294 c_ULTIMATE.start_main_p4) (<= .cse24 v_idx_294)) (<= .cse28 v_b_210_2) (<= .cse26 v_b_213_2) (<= .cse31 v_b_210_2) (<= .cse21 v_b_213_2) (<= .cse32 v_b_211_2) (<= .cse29 v_b_212_2) (<= .cse18 v_b_205_2) (<= .cse8 v_b_209_2) (or (= (select |c_#memory_int| v_idx_289) v_v_1896_2) (< v_idx_289 .cse25) (<= v_b_202_2 v_idx_289)) (<= .cse30 v_b_214_2) (<= v_b_205_2 c_ULTIMATE.start_main_p4) (<= .cse33 v_b_210_2) (<= .cse2 v_b_203_2) (or (= (select |c_#memory_int| v_idx_291) v_v_1898_2) (<= v_b_204_2 v_idx_291) (< v_idx_291 v_b_203_2)) (or (= 0 (select |c_#memory_int| v_idx_296)) (<= v_b_209_2 v_idx_296) (< v_idx_296 v_b_208_2)) (<= (* 2 v_v_1901_2) 0) (<= .cse13 v_b_212_2) (<= .cse22 v_b_214_2) (<= .cse6 v_b_212_2) (<= v_b_211_2 v_b_212_2) (<= .cse19 v_b_214_2) (<= .cse34 v_b_211_2) (<= (+ v_b_209_2 3) v_b_215_2) (<= .cse7 v_b_212_2) (<= .cse20 v_b_212_2) (<= .cse24 v_b_208_2) (<= .cse32 v_b_212_2) (<= .cse33 v_b_209_2) (<= .cse16 v_b_212_2) (or (<= v_b_211_2 v_idx_298) (< v_idx_298 v_b_210_2) (= (select |c_#memory_int| v_idx_298) 0)) (or (= 0 (select |c_#memory_int| v_idx_288)) (<= .cse25 v_idx_288) (< v_idx_288 c_ULTIMATE.start_main_p1)) (<= .cse28 v_b_209_2) (<= .cse31 v_b_209_2) (or (= (select |c_#memory_int| v_idx_293) v_v_1900_2) (<= c_ULTIMATE.start_main_p4 v_idx_293) (< v_idx_293 v_b_205_2)) (<= (+ v_b_205_2 1) v_b_208_2) (<= .cse35 v_b_213_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_287) (= (select |c_#memory_int| v_idx_287) v_v_1894_2)) (<= v_b_205_2 .cse23) (<= .cse35 v_b_214_2) (<= (+ v_b_213_2 1) v_b_215_2) (<= .cse34 v_b_212_2) (<= .cse27 v_b_214_2) (<= .cse4 v_b_215_2) (<= (+ v_b_208_2 4) v_b_215_2))))) is different from false [2019-01-11 11:46:56,691 WARN L838 $PredicateComparison]: unable to prove that (forall ((v_idx_308 Int) (v_idx_319 Int) (v_idx_309 Int) (v_idx_313 Int) (v_idx_314 Int) (v_idx_311 Int) (v_idx_312 Int) (v_idx_306 Int) (v_idx_317 Int) (v_idx_307 Int) (v_idx_318 Int) (v_idx_304 Int) (v_idx_315 Int) (v_idx_305 Int) (v_idx_316 Int) (v_idx_320 Int) (v_idx_310 Int)) (exists ((v_b_211_2 Int) (v_v_1896_2 Int) (v_b_210_2 Int) (v_v_1898_2 Int) (v_v_1908_2 Int) (v_v_1906_2 Int) (v_v_1904_2 Int) (v_v_1894_2 Int) (v_v_1902_2 Int) (v_v_1901_2 Int) (v_v_1900_2 Int) (v_v_1910_2 Int) (v_b_209_2 Int) (v_b_208_2 Int) (v_b_207_2 Int) (v_b_206_2 Int) (v_b_205_2 Int) (v_b_215_2 Int) (v_b_204_2 Int) (v_b_203_2 Int) (v_b_214_2 Int) (v_b_202_2 Int) (v_b_213_2 Int) (v_b_212_2 Int)) (let ((.cse5 (+ v_b_204_2 5)) (.cse18 (+ v_b_208_2 3)) (.cse20 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ v_b_205_2 2)) (.cse1 (+ v_b_207_2 1)) (.cse28 (+ c_ULTIMATE.start_main_p1 4)) (.cse17 (+ v_b_203_2 3)) (.cse9 (+ v_b_210_2 1)) (.cse16 (+ v_b_206_2 1)) (.cse30 (+ v_b_206_2 2)) (.cse10 (+ v_b_212_2 1)) (.cse27 (+ v_b_205_2 4)) (.cse23 (+ v_b_202_2 6)) (.cse3 (+ v_b_203_2 2)) (.cse13 (+ v_b_203_2 1)) (.cse33 (+ v_b_204_2 4)) (.cse8 (+ v_b_202_2 4)) (.cse11 (+ v_b_202_2 3)) (.cse34 (+ v_b_209_2 2)) (.cse0 (+ v_b_202_2 1)) (.cse15 (+ c_ULTIMATE.start_main_p1 6)) (.cse25 (+ v_b_203_2 5)) (.cse36 (+ v_b_206_2 4)) (.cse6 (+ v_b_203_2 4)) (.cse21 (+ c_ULTIMATE.start_main_p1 7)) (.cse14 (+ v_b_202_2 2)) (.cse7 (+ v_b_205_2 3)) (.cse22 (+ v_b_202_2 5)) (.cse37 (+ v_b_209_2 1)) (.cse39 (+ v_b_204_2 3)) (.cse24 (+ v_b_207_2 2)) (.cse12 (+ v_b_207_2 3)) (.cse32 (+ v_b_208_2 1)) (.cse35 (+ c_ULTIMATE.start_main_p1 5)) (.cse42 (+ v_b_205_2 1)) (.cse29 (+ v_b_204_2 1)) (.cse26 (+ v_b_204_2 2)) (.cse43 (+ v_b_211_2 1)) (.cse40 (+ v_b_206_2 3)) (.cse19 (+ c_ULTIMATE.start_main_p1 1)) (.cse38 (+ c_ULTIMATE.start_main_p1 3)) (.cse41 (+ v_b_208_2 2)) (.cse31 (+ v_b_210_2 2)) (.cse4 (+ v_b_214_2 1))) (and (<= v_b_203_2 .cse0) (<= v_b_207_2 v_b_208_2) (<= (+ v_b_205_2 5) v_b_215_2) (<= .cse1 v_b_209_2) (<= .cse2 v_b_210_2) (or (<= v_b_215_2 v_idx_319) (= 0 (select |c_#memory_int| v_idx_319)) (< v_idx_319 v_b_214_2)) (<= .cse3 v_b_208_2) (<= v_b_215_2 .cse4) (<= .cse5 v_b_213_2) (<= .cse6 v_b_211_2) (<= .cse7 v_b_211_2) (or (= 0 (select |c_#memory_int| v_idx_313)) (<= v_b_209_2 v_idx_313) (< v_idx_313 v_b_208_2)) (or (= (select |c_#memory_int| v_idx_320) v_v_1910_2) (< v_idx_320 v_b_215_2)) (<= .cse8 v_b_210_2) (<= .cse9 v_b_211_2) (<= .cse10 v_b_214_2) (<= v_b_211_2 .cse9) (<= .cse11 v_b_208_2) (<= .cse12 v_b_213_2) (or (<= v_b_208_2 v_idx_312) (< v_idx_312 v_b_207_2) (= (select |c_#memory_int| v_idx_312) v_v_1902_2)) (<= .cse13 v_b_205_2) (<= .cse14 v_b_205_2) (<= .cse15 v_b_211_2) (<= .cse16 v_b_208_2) (or (< v_idx_310 v_b_205_2) (= (select |c_#memory_int| v_idx_310) v_v_1900_2) (<= v_b_206_2 v_idx_310)) (<= (+ v_b_207_2 4) v_b_215_2) (<= .cse17 v_b_210_2) (<= (+ c_ULTIMATE.start_main_p1 8) v_b_215_2) (<= .cse18 v_b_213_2) (or (= (select |c_#memory_int| v_idx_306) v_v_1896_2) (<= v_b_202_2 v_idx_306) (< v_idx_306 .cse19)) (<= v_b_203_2 v_b_204_2) (<= (+ v_b_202_2 7) v_b_215_2) (<= v_b_207_2 .cse16) (<= .cse20 v_b_203_2) (<= (+ v_b_203_2 6) v_b_215_2) (<= v_b_213_2 .cse10) (<= .cse5 v_b_214_2) (<= .cse21 v_b_213_2) (<= .cse22 v_b_211_2) (<= .cse23 v_b_214_2) (<= .cse24 v_b_211_2) (<= .cse25 v_b_213_2) (<= (+ v_b_211_2 2) v_b_215_2) (<= .cse18 v_b_214_2) (<= .cse20 v_b_204_2) (<= .cse26 v_b_208_2) (<= .cse2 v_b_209_2) (<= .cse19 v_b_202_2) (<= .cse1 v_b_210_2) (<= .cse27 v_b_214_2) (<= v_v_1901_2 0) (<= v_b_205_2 v_b_206_2) (<= .cse28 v_b_207_2) (<= .cse29 v_b_205_2) (or (= (select |c_#memory_int| v_idx_311) v_v_1901_2) (< v_idx_311 v_b_206_2) (<= v_b_207_2 v_idx_311)) (<= v_b_209_2 v_b_210_2) (<= (+ v_b_206_2 5) v_b_215_2) (<= .cse28 v_b_208_2) (<= .cse30 v_b_210_2) (<= v_b_213_2 v_b_214_2) (<= (+ v_b_204_2 6) v_b_215_2) (<= (+ v_b_210_2 3) v_b_215_2) (<= .cse31 v_b_213_2) (<= v_b_209_2 .cse32) (<= .cse33 v_b_211_2) (<= .cse34 v_b_213_2) (<= .cse17 v_b_209_2) (<= .cse0 v_b_204_2) (<= .cse9 v_b_212_2) (<= .cse16 v_b_207_2) (<= .cse30 v_b_209_2) (<= (+ v_b_212_2 2) v_b_215_2) (<= .cse10 v_b_213_2) (<= .cse32 v_b_210_2) (<= .cse27 v_b_213_2) (or (<= v_b_212_2 v_idx_316) (< v_idx_316 v_b_211_2) (= (select |c_#memory_int| v_idx_316) v_v_1906_2)) (or (<= v_b_213_2 v_idx_317) (= 0 (select |c_#memory_int| v_idx_317)) (< v_idx_317 v_b_212_2)) (<= .cse35 v_b_210_2) (<= .cse36 v_b_214_2) (<= .cse23 v_b_213_2) (<= .cse37 v_b_211_2) (<= .cse3 v_b_207_2) (<= .cse13 v_b_206_2) (<= .cse33 v_b_212_2) (or (= 0 (select |c_#memory_int| v_idx_307)) (< v_idx_307 v_b_202_2) (<= v_b_203_2 v_idx_307)) (<= .cse38 v_b_205_2) (<= .cse8 v_b_209_2) (<= .cse11 v_b_207_2) (<= .cse34 v_b_214_2) (<= .cse39 v_b_210_2) (<= .cse0 v_b_203_2) (<= .cse29 v_b_206_2) (<= (* 2 v_v_1901_2) 0) (<= .cse15 v_b_212_2) (<= .cse25 v_b_214_2) (<= .cse36 v_b_213_2) (<= .cse6 v_b_212_2) (<= v_b_211_2 v_b_212_2) (<= .cse40 v_b_211_2) (<= .cse21 v_b_214_2) (<= .cse14 v_b_206_2) (<= .cse41 v_b_211_2) (<= (+ v_b_209_2 3) v_b_215_2) (or (< v_idx_314 v_b_209_2) (= (select |c_#memory_int| v_idx_314) v_v_1904_2) (<= v_b_210_2 v_idx_314)) (<= .cse7 v_b_212_2) (or (= (select |c_#memory_int| v_idx_315) 0) (< v_idx_315 v_b_210_2) (<= v_b_211_2 v_idx_315)) (<= .cse22 v_b_212_2) (<= .cse37 v_b_212_2) (<= .cse39 v_b_209_2) (<= .cse42 v_b_207_2) (<= .cse24 v_b_212_2) (<= .cse12 v_b_214_2) (or (< v_idx_308 v_b_203_2) (<= v_b_204_2 v_idx_308) (= (select |c_#memory_int| v_idx_308) v_v_1898_2)) (<= .cse32 v_b_209_2) (<= .cse35 v_b_209_2) (<= .cse42 v_b_208_2) (<= .cse43 v_b_213_2) (<= v_b_205_2 .cse29) (<= .cse26 v_b_207_2) (<= .cse43 v_b_214_2) (or (= (select |c_#memory_int| v_idx_318) v_v_1908_2) (< v_idx_318 v_b_213_2) (<= v_b_214_2 v_idx_318)) (<= .cse40 v_b_212_2) (or (= (select |c_#memory_int| v_idx_309) 0) (<= v_b_205_2 v_idx_309) (< v_idx_309 v_b_204_2)) (or (= (select |c_#memory_int| v_idx_305) 0) (< v_idx_305 c_ULTIMATE.start_main_p1) (<= .cse19 v_idx_305)) (<= (+ v_b_213_2 1) v_b_215_2) (<= .cse38 v_b_206_2) (<= .cse41 v_b_212_2) (<= .cse31 v_b_214_2) (<= .cse4 v_b_215_2) (or (= (select |c_#memory_int| v_idx_304) v_v_1894_2) (<= c_ULTIMATE.start_main_p1 v_idx_304)) (<= (+ v_b_208_2 4) v_b_215_2))))) is different from false [2019-01-11 11:46:56,771 INFO L420 sIntCurrentIteration]: We unified 2 AI predicates to 2 [2019-01-11 11:46:56,772 INFO L429 sIntCurrentIteration]: Finished generation of AbsInt predicates [2019-01-11 11:46:56,772 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2019-01-11 11:46:56,772 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 4 [2019-01-11 11:46:56,772 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:46:56,773 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-01-11 11:46:56,773 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-01-11 11:46:56,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=3, Unknown=2, NotChecked=2, Total=12 [2019-01-11 11:46:56,774 INFO L87 Difference]: Start difference. First operand 19 states and 42 transitions. Second operand 4 states. [2019-01-11 11:46:59,778 WARN L838 $PredicateComparison]: unable to prove that (and (forall ((v_idx_308 Int) (v_idx_319 Int) (v_idx_309 Int) (v_idx_313 Int) (v_idx_314 Int) (v_idx_311 Int) (v_idx_312 Int) (v_idx_306 Int) (v_idx_317 Int) (v_idx_307 Int) (v_idx_318 Int) (v_idx_304 Int) (v_idx_315 Int) (v_idx_305 Int) (v_idx_316 Int) (v_idx_320 Int) (v_idx_310 Int)) (exists ((v_b_211_2 Int) (v_v_1896_2 Int) (v_b_210_2 Int) (v_v_1898_2 Int) (v_v_1908_2 Int) (v_v_1906_2 Int) (v_v_1904_2 Int) (v_v_1894_2 Int) (v_v_1902_2 Int) (v_v_1901_2 Int) (v_v_1900_2 Int) (v_v_1910_2 Int) (v_b_209_2 Int) (v_b_208_2 Int) (v_b_207_2 Int) (v_b_206_2 Int) (v_b_205_2 Int) (v_b_215_2 Int) (v_b_204_2 Int) (v_b_203_2 Int) (v_b_214_2 Int) (v_b_202_2 Int) (v_b_213_2 Int) (v_b_212_2 Int)) (let ((.cse5 (+ v_b_204_2 5)) (.cse18 (+ v_b_208_2 3)) (.cse20 (+ c_ULTIMATE.start_main_p1 2)) (.cse2 (+ v_b_205_2 2)) (.cse1 (+ v_b_207_2 1)) (.cse28 (+ c_ULTIMATE.start_main_p1 4)) (.cse17 (+ v_b_203_2 3)) (.cse9 (+ v_b_210_2 1)) (.cse16 (+ v_b_206_2 1)) (.cse30 (+ v_b_206_2 2)) (.cse10 (+ v_b_212_2 1)) (.cse27 (+ v_b_205_2 4)) (.cse23 (+ v_b_202_2 6)) (.cse3 (+ v_b_203_2 2)) (.cse13 (+ v_b_203_2 1)) (.cse33 (+ v_b_204_2 4)) (.cse8 (+ v_b_202_2 4)) (.cse11 (+ v_b_202_2 3)) (.cse34 (+ v_b_209_2 2)) (.cse0 (+ v_b_202_2 1)) (.cse15 (+ c_ULTIMATE.start_main_p1 6)) (.cse25 (+ v_b_203_2 5)) (.cse36 (+ v_b_206_2 4)) (.cse6 (+ v_b_203_2 4)) (.cse21 (+ c_ULTIMATE.start_main_p1 7)) (.cse14 (+ v_b_202_2 2)) (.cse7 (+ v_b_205_2 3)) (.cse22 (+ v_b_202_2 5)) (.cse37 (+ v_b_209_2 1)) (.cse39 (+ v_b_204_2 3)) (.cse24 (+ v_b_207_2 2)) (.cse12 (+ v_b_207_2 3)) (.cse32 (+ v_b_208_2 1)) (.cse35 (+ c_ULTIMATE.start_main_p1 5)) (.cse42 (+ v_b_205_2 1)) (.cse29 (+ v_b_204_2 1)) (.cse26 (+ v_b_204_2 2)) (.cse43 (+ v_b_211_2 1)) (.cse40 (+ v_b_206_2 3)) (.cse19 (+ c_ULTIMATE.start_main_p1 1)) (.cse38 (+ c_ULTIMATE.start_main_p1 3)) (.cse41 (+ v_b_208_2 2)) (.cse31 (+ v_b_210_2 2)) (.cse4 (+ v_b_214_2 1))) (and (<= v_b_203_2 .cse0) (<= v_b_207_2 v_b_208_2) (<= (+ v_b_205_2 5) v_b_215_2) (<= .cse1 v_b_209_2) (<= .cse2 v_b_210_2) (or (<= v_b_215_2 v_idx_319) (= 0 (select |c_#memory_int| v_idx_319)) (< v_idx_319 v_b_214_2)) (<= .cse3 v_b_208_2) (<= v_b_215_2 .cse4) (<= .cse5 v_b_213_2) (<= .cse6 v_b_211_2) (<= .cse7 v_b_211_2) (or (= 0 (select |c_#memory_int| v_idx_313)) (<= v_b_209_2 v_idx_313) (< v_idx_313 v_b_208_2)) (or (= (select |c_#memory_int| v_idx_320) v_v_1910_2) (< v_idx_320 v_b_215_2)) (<= .cse8 v_b_210_2) (<= .cse9 v_b_211_2) (<= .cse10 v_b_214_2) (<= v_b_211_2 .cse9) (<= .cse11 v_b_208_2) (<= .cse12 v_b_213_2) (or (<= v_b_208_2 v_idx_312) (< v_idx_312 v_b_207_2) (= (select |c_#memory_int| v_idx_312) v_v_1902_2)) (<= .cse13 v_b_205_2) (<= .cse14 v_b_205_2) (<= .cse15 v_b_211_2) (<= .cse16 v_b_208_2) (or (< v_idx_310 v_b_205_2) (= (select |c_#memory_int| v_idx_310) v_v_1900_2) (<= v_b_206_2 v_idx_310)) (<= (+ v_b_207_2 4) v_b_215_2) (<= .cse17 v_b_210_2) (<= (+ c_ULTIMATE.start_main_p1 8) v_b_215_2) (<= .cse18 v_b_213_2) (or (= (select |c_#memory_int| v_idx_306) v_v_1896_2) (<= v_b_202_2 v_idx_306) (< v_idx_306 .cse19)) (<= v_b_203_2 v_b_204_2) (<= (+ v_b_202_2 7) v_b_215_2) (<= v_b_207_2 .cse16) (<= .cse20 v_b_203_2) (<= (+ v_b_203_2 6) v_b_215_2) (<= v_b_213_2 .cse10) (<= .cse5 v_b_214_2) (<= .cse21 v_b_213_2) (<= .cse22 v_b_211_2) (<= .cse23 v_b_214_2) (<= .cse24 v_b_211_2) (<= .cse25 v_b_213_2) (<= (+ v_b_211_2 2) v_b_215_2) (<= .cse18 v_b_214_2) (<= .cse20 v_b_204_2) (<= .cse26 v_b_208_2) (<= .cse2 v_b_209_2) (<= .cse19 v_b_202_2) (<= .cse1 v_b_210_2) (<= .cse27 v_b_214_2) (<= v_v_1901_2 0) (<= v_b_205_2 v_b_206_2) (<= .cse28 v_b_207_2) (<= .cse29 v_b_205_2) (or (= (select |c_#memory_int| v_idx_311) v_v_1901_2) (< v_idx_311 v_b_206_2) (<= v_b_207_2 v_idx_311)) (<= v_b_209_2 v_b_210_2) (<= (+ v_b_206_2 5) v_b_215_2) (<= .cse28 v_b_208_2) (<= .cse30 v_b_210_2) (<= v_b_213_2 v_b_214_2) (<= (+ v_b_204_2 6) v_b_215_2) (<= (+ v_b_210_2 3) v_b_215_2) (<= .cse31 v_b_213_2) (<= v_b_209_2 .cse32) (<= .cse33 v_b_211_2) (<= .cse34 v_b_213_2) (<= .cse17 v_b_209_2) (<= .cse0 v_b_204_2) (<= .cse9 v_b_212_2) (<= .cse16 v_b_207_2) (<= .cse30 v_b_209_2) (<= (+ v_b_212_2 2) v_b_215_2) (<= .cse10 v_b_213_2) (<= .cse32 v_b_210_2) (<= .cse27 v_b_213_2) (or (<= v_b_212_2 v_idx_316) (< v_idx_316 v_b_211_2) (= (select |c_#memory_int| v_idx_316) v_v_1906_2)) (or (<= v_b_213_2 v_idx_317) (= 0 (select |c_#memory_int| v_idx_317)) (< v_idx_317 v_b_212_2)) (<= .cse35 v_b_210_2) (<= .cse36 v_b_214_2) (<= .cse23 v_b_213_2) (<= .cse37 v_b_211_2) (<= .cse3 v_b_207_2) (<= .cse13 v_b_206_2) (<= .cse33 v_b_212_2) (or (= 0 (select |c_#memory_int| v_idx_307)) (< v_idx_307 v_b_202_2) (<= v_b_203_2 v_idx_307)) (<= .cse38 v_b_205_2) (<= .cse8 v_b_209_2) (<= .cse11 v_b_207_2) (<= .cse34 v_b_214_2) (<= .cse39 v_b_210_2) (<= .cse0 v_b_203_2) (<= .cse29 v_b_206_2) (<= (* 2 v_v_1901_2) 0) (<= .cse15 v_b_212_2) (<= .cse25 v_b_214_2) (<= .cse36 v_b_213_2) (<= .cse6 v_b_212_2) (<= v_b_211_2 v_b_212_2) (<= .cse40 v_b_211_2) (<= .cse21 v_b_214_2) (<= .cse14 v_b_206_2) (<= .cse41 v_b_211_2) (<= (+ v_b_209_2 3) v_b_215_2) (or (< v_idx_314 v_b_209_2) (= (select |c_#memory_int| v_idx_314) v_v_1904_2) (<= v_b_210_2 v_idx_314)) (<= .cse7 v_b_212_2) (or (= (select |c_#memory_int| v_idx_315) 0) (< v_idx_315 v_b_210_2) (<= v_b_211_2 v_idx_315)) (<= .cse22 v_b_212_2) (<= .cse37 v_b_212_2) (<= .cse39 v_b_209_2) (<= .cse42 v_b_207_2) (<= .cse24 v_b_212_2) (<= .cse12 v_b_214_2) (or (< v_idx_308 v_b_203_2) (<= v_b_204_2 v_idx_308) (= (select |c_#memory_int| v_idx_308) v_v_1898_2)) (<= .cse32 v_b_209_2) (<= .cse35 v_b_209_2) (<= .cse42 v_b_208_2) (<= .cse43 v_b_213_2) (<= v_b_205_2 .cse29) (<= .cse26 v_b_207_2) (<= .cse43 v_b_214_2) (or (= (select |c_#memory_int| v_idx_318) v_v_1908_2) (< v_idx_318 v_b_213_2) (<= v_b_214_2 v_idx_318)) (<= .cse40 v_b_212_2) (or (= (select |c_#memory_int| v_idx_309) 0) (<= v_b_205_2 v_idx_309) (< v_idx_309 v_b_204_2)) (or (= (select |c_#memory_int| v_idx_305) 0) (< v_idx_305 c_ULTIMATE.start_main_p1) (<= .cse19 v_idx_305)) (<= (+ v_b_213_2 1) v_b_215_2) (<= .cse38 v_b_206_2) (<= .cse41 v_b_212_2) (<= .cse31 v_b_214_2) (<= .cse4 v_b_215_2) (or (= (select |c_#memory_int| v_idx_304) v_v_1894_2) (<= c_ULTIMATE.start_main_p1 v_idx_304)) (<= (+ v_b_208_2 4) v_b_215_2))))) (forall ((v_idx_290 Int) (v_idx_291 Int) (v_idx_302 Int) (v_idx_303 Int) (v_idx_300 Int) (v_idx_289 Int) (v_idx_301 Int) (v_idx_294 Int) (v_idx_295 Int) (v_idx_292 Int) (v_idx_293 Int) (v_idx_287 Int) (v_idx_298 Int) (v_idx_288 Int) (v_idx_299 Int) (v_idx_296 Int) (v_idx_297 Int)) (exists ((v_b_211_2 Int) (v_v_1896_2 Int) (v_b_210_2 Int) (v_v_1898_2 Int) (v_v_1908_2 Int) (v_v_1906_2 Int) (v_v_1904_2 Int) (v_v_1894_2 Int) (v_v_1902_2 Int) (v_v_1901_2 Int) (v_v_1900_2 Int) (v_v_1910_2 Int) (v_b_209_2 Int) (v_b_208_2 Int) (v_b_205_2 Int) (v_b_215_2 Int) (v_b_204_2 Int) (v_b_203_2 Int) (v_b_214_2 Int) (v_b_213_2 Int) (v_b_202_2 Int) (v_b_212_2 Int)) (let ((.cse44 (+ v_b_203_2 1)) (.cse49 (+ v_b_204_2 5)) (.cse56 (+ v_b_202_2 2)) (.cse54 (+ c_ULTIMATE.start_main_p4 2)) (.cse59 (+ v_b_208_2 3)) (.cse61 (+ c_ULTIMATE.start_main_p1 2)) (.cse47 (+ v_b_205_2 2)) (.cse45 (+ c_ULTIMATE.start_main_p4 4)) (.cse58 (+ v_b_203_2 3)) (.cse53 (+ v_b_210_2 1)) (.cse55 (+ v_b_212_2 1)) (.cse70 (+ v_b_205_2 4)) (.cse65 (+ v_b_202_2 6)) (.cse73 (+ v_b_204_2 4)) (.cse62 (+ c_ULTIMATE.start_main_p1 3)) (.cse52 (+ v_b_202_2 4)) (.cse74 (+ v_b_209_2 2)) (.cse46 (+ v_b_202_2 1)) (.cse57 (+ c_ULTIMATE.start_main_p1 6)) (.cse66 (+ v_b_203_2 5)) (.cse50 (+ v_b_203_2 4)) (.cse63 (+ c_ULTIMATE.start_main_p1 7)) (.cse51 (+ v_b_205_2 3)) (.cse64 (+ v_b_202_2 5)) (.cse68 (+ c_ULTIMATE.start_main_p4 1)) (.cse76 (+ v_b_209_2 1)) (.cse77 (+ v_b_204_2 3)) (.cse60 (+ c_ULTIMATE.start_main_p4 3)) (.cse69 (+ c_ULTIMATE.start_main_p1 1)) (.cse72 (+ v_b_208_2 1)) (.cse75 (+ c_ULTIMATE.start_main_p1 5)) (.cse67 (+ v_b_204_2 1)) (.cse79 (+ v_b_211_2 1)) (.cse78 (+ v_b_208_2 2)) (.cse71 (+ v_b_210_2 2)) (.cse48 (+ v_b_214_2 1))) (and (<= .cse44 c_ULTIMATE.start_main_p4) (<= .cse45 v_b_213_2) (<= v_b_203_2 .cse46) (<= (+ v_b_205_2 5) v_b_215_2) (<= .cse47 v_b_210_2) (<= (+ v_b_203_2 2) v_b_208_2) (<= v_b_215_2 .cse48) (<= .cse49 v_b_213_2) (<= .cse50 v_b_211_2) (<= .cse51 v_b_211_2) (or (= 0 (select |c_#memory_int| v_idx_290)) (<= v_b_203_2 v_idx_290) (< v_idx_290 v_b_202_2)) (<= .cse52 v_b_210_2) (<= .cse53 v_b_211_2) (<= .cse54 v_b_209_2) (<= .cse55 v_b_214_2) (<= v_b_211_2 .cse53) (<= (+ v_b_202_2 3) v_b_208_2) (<= .cse44 v_b_205_2) (<= .cse56 v_b_205_2) (<= .cse57 v_b_211_2) (or (<= v_b_205_2 v_idx_292) (< v_idx_292 v_b_204_2) (= 0 (select |c_#memory_int| v_idx_292))) (<= .cse58 v_b_210_2) (<= (+ c_ULTIMATE.start_main_p1 8) v_b_215_2) (<= .cse59 v_b_213_2) (<= .cse60 v_b_211_2) (<= v_b_203_2 v_b_204_2) (<= (+ v_b_202_2 7) v_b_215_2) (<= .cse61 v_b_203_2) (or (< v_idx_299 v_b_211_2) (<= v_b_212_2 v_idx_299) (= (select |c_#memory_int| v_idx_299) v_v_1906_2)) (<= (+ v_b_203_2 6) v_b_215_2) (<= v_b_213_2 .cse55) (<= .cse62 c_ULTIMATE.start_main_p4) (<= .cse49 v_b_214_2) (<= .cse63 v_b_213_2) (<= .cse64 v_b_211_2) (<= .cse56 c_ULTIMATE.start_main_p4) (<= .cse54 v_b_210_2) (<= .cse65 v_b_214_2) (<= .cse66 v_b_213_2) (or (= (select |c_#memory_int| v_idx_301) v_v_1908_2) (< v_idx_301 v_b_213_2) (<= v_b_214_2 v_idx_301)) (<= (+ v_b_211_2 2) v_b_215_2) (<= .cse59 v_b_214_2) (<= .cse61 v_b_204_2) (<= (+ c_ULTIMATE.start_main_p4 5) v_b_215_2) (<= (+ v_b_204_2 2) v_b_208_2) (<= .cse67 c_ULTIMATE.start_main_p4) (or (<= v_b_208_2 v_idx_295) (= (select |c_#memory_int| v_idx_295) v_v_1902_2) (< v_idx_295 .cse68)) (<= .cse47 v_b_209_2) (<= .cse69 v_b_202_2) (<= .cse70 v_b_214_2) (<= v_v_1901_2 0) (<= .cse45 v_b_214_2) (<= .cse67 v_b_205_2) (<= v_b_209_2 v_b_210_2) (<= (+ c_ULTIMATE.start_main_p1 4) v_b_208_2) (<= v_b_213_2 v_b_214_2) (<= (+ v_b_204_2 6) v_b_215_2) (<= (+ v_b_210_2 3) v_b_215_2) (<= .cse71 v_b_213_2) (<= v_b_209_2 .cse72) (<= .cse73 v_b_211_2) (or (= (select |c_#memory_int| v_idx_297) v_v_1904_2) (< v_idx_297 v_b_209_2) (<= v_b_210_2 v_idx_297)) (<= .cse74 v_b_213_2) (<= .cse58 v_b_209_2) (<= .cse46 v_b_204_2) (or (= (select |c_#memory_int| v_idx_303) v_v_1910_2) (< v_idx_303 v_b_215_2)) (<= .cse53 v_b_212_2) (<= (+ v_b_212_2 2) v_b_215_2) (or (< v_idx_302 v_b_214_2) (<= v_b_215_2 v_idx_302) (= 0 (select |c_#memory_int| v_idx_302))) (or (= (select |c_#memory_int| v_idx_300) 0) (< v_idx_300 v_b_212_2) (<= v_b_213_2 v_idx_300)) (<= .cse55 v_b_213_2) (or (= (select |c_#memory_int| v_idx_294) v_v_1901_2) (< v_idx_294 c_ULTIMATE.start_main_p4) (<= .cse68 v_idx_294)) (<= .cse72 v_b_210_2) (<= .cse70 v_b_213_2) (<= .cse75 v_b_210_2) (<= .cse65 v_b_213_2) (<= .cse76 v_b_211_2) (<= .cse73 v_b_212_2) (<= .cse62 v_b_205_2) (<= .cse52 v_b_209_2) (or (= (select |c_#memory_int| v_idx_289) v_v_1896_2) (< v_idx_289 .cse69) (<= v_b_202_2 v_idx_289)) (<= .cse74 v_b_214_2) (<= v_b_205_2 c_ULTIMATE.start_main_p4) (<= .cse77 v_b_210_2) (<= .cse46 v_b_203_2) (or (= (select |c_#memory_int| v_idx_291) v_v_1898_2) (<= v_b_204_2 v_idx_291) (< v_idx_291 v_b_203_2)) (or (= 0 (select |c_#memory_int| v_idx_296)) (<= v_b_209_2 v_idx_296) (< v_idx_296 v_b_208_2)) (<= (* 2 v_v_1901_2) 0) (<= .cse57 v_b_212_2) (<= .cse66 v_b_214_2) (<= .cse50 v_b_212_2) (<= v_b_211_2 v_b_212_2) (<= .cse63 v_b_214_2) (<= .cse78 v_b_211_2) (<= (+ v_b_209_2 3) v_b_215_2) (<= .cse51 v_b_212_2) (<= .cse64 v_b_212_2) (<= .cse68 v_b_208_2) (<= .cse76 v_b_212_2) (<= .cse77 v_b_209_2) (<= .cse60 v_b_212_2) (or (<= v_b_211_2 v_idx_298) (< v_idx_298 v_b_210_2) (= (select |c_#memory_int| v_idx_298) 0)) (or (= 0 (select |c_#memory_int| v_idx_288)) (<= .cse69 v_idx_288) (< v_idx_288 c_ULTIMATE.start_main_p1)) (<= .cse72 v_b_209_2) (<= .cse75 v_b_209_2) (or (= (select |c_#memory_int| v_idx_293) v_v_1900_2) (<= c_ULTIMATE.start_main_p4 v_idx_293) (< v_idx_293 v_b_205_2)) (<= (+ v_b_205_2 1) v_b_208_2) (<= .cse79 v_b_213_2) (or (<= c_ULTIMATE.start_main_p1 v_idx_287) (= (select |c_#memory_int| v_idx_287) v_v_1894_2)) (<= v_b_205_2 .cse67) (<= .cse79 v_b_214_2) (<= (+ v_b_213_2 1) v_b_215_2) (<= .cse78 v_b_212_2) (<= .cse71 v_b_214_2) (<= .cse48 v_b_215_2) (<= (+ v_b_208_2 4) v_b_215_2)))))) is different from false [2019-01-11 11:47:26,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:47:26,529 INFO L93 Difference]: Finished difference Result 21 states and 52 transitions. [2019-01-11 11:47:26,529 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-01-11 11:47:26,529 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 3 [2019-01-11 11:47:26,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:47:26,530 INFO L225 Difference]: With dead ends: 21 [2019-01-11 11:47:26,530 INFO L226 Difference]: Without dead ends: 20 [2019-01-11 11:47:26,531 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.8s TimeCoverageRelationStatistics Valid=7, Invalid=4, Unknown=3, NotChecked=6, Total=20 [2019-01-11 11:47:26,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2019-01-11 11:47:26,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 19. [2019-01-11 11:47:26,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2019-01-11 11:47:26,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 42 transitions. [2019-01-11 11:47:26,543 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 42 transitions. Word has length 3 [2019-01-11 11:47:26,543 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:47:26,543 INFO L480 AbstractCegarLoop]: Abstraction has 19 states and 42 transitions. [2019-01-11 11:47:26,543 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-01-11 11:47:26,543 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 42 transitions. [2019-01-11 11:47:26,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:47:26,544 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:47:26,544 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:47:26,544 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr7ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:47:26,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:26,545 INFO L82 PathProgramCache]: Analyzing trace with hash 30944, now seen corresponding path program 1 times [2019-01-11 11:47:26,545 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:47:26,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:26,546 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:47:26,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:26,546 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:47:26,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:47:26,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:47:26,602 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-01-11 11:47:26,603 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2019-01-11 11:47:26,603 INFO L257 anRefinementStrategy]: Using the first perfect interpolant sequence [2019-01-11 11:47:26,603 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-01-11 11:47:26,603 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-01-11 11:47:26,604 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:47:26,604 INFO L87 Difference]: Start difference. First operand 19 states and 42 transitions. Second operand 3 states. [2019-01-11 11:47:26,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-01-11 11:47:26,689 INFO L93 Difference]: Finished difference Result 33 states and 55 transitions. [2019-01-11 11:47:26,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-01-11 11:47:26,692 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2019-01-11 11:47:26,692 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-01-11 11:47:26,693 INFO L225 Difference]: With dead ends: 33 [2019-01-11 11:47:26,693 INFO L226 Difference]: Without dead ends: 32 [2019-01-11 11:47:26,694 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 1 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-01-11 11:47:26,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2019-01-11 11:47:26,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 20. [2019-01-11 11:47:26,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2019-01-11 11:47:26,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 43 transitions. [2019-01-11 11:47:26,706 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 43 transitions. Word has length 3 [2019-01-11 11:47:26,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-01-11 11:47:26,706 INFO L480 AbstractCegarLoop]: Abstraction has 20 states and 43 transitions. [2019-01-11 11:47:26,706 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-01-11 11:47:26,707 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 43 transitions. [2019-01-11 11:47:26,707 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2019-01-11 11:47:26,707 INFO L394 BasicCegarLoop]: Found error trace [2019-01-11 11:47:26,707 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1] [2019-01-11 11:47:26,708 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr2ASSERT_VIOLATIONASSERT, ULTIMATE.startErr1ASSERT_VIOLATIONASSERT, ULTIMATE.startErr6ASSERT_VIOLATIONASSERT, ULTIMATE.startErr5ASSERT_VIOLATIONASSERT, ULTIMATE.startErr4ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr3ASSERT_VIOLATIONASSERT, ULTIMATE.startErr7ASSERT_VIOLATIONASSERT]=== [2019-01-11 11:47:26,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:26,708 INFO L82 PathProgramCache]: Analyzing trace with hash 30012, now seen corresponding path program 1 times [2019-01-11 11:47:26,708 INFO L69 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2019-01-11 11:47:26,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:26,709 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-01-11 11:47:26,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2019-01-11 11:47:26,710 INFO L289 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2019-01-11 11:47:26,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-01-11 11:47:26,775 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-01-11 11:47:26,775 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2019-01-11 11:47:26,775 INFO L193 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2019-01-11 11:47:26,776 INFO L205 CegarAbsIntRunner]: Running AI on error trace of length 4 with the following transitions: [2019-01-11 11:47:26,776 INFO L207 CegarAbsIntRunner]: [0], [6], [35] [2019-01-11 11:47:26,777 INFO L148 AbstractInterpreter]: Using domain ArrayDomain [2019-01-11 11:47:26,777 INFO L101 FixpointEngine]: Starting fixpoint engine with domain ArrayDomain (maxUnwinding=3, maxParallelStates=2) [2019-01-11 11:47:45,881 INFO L266 AbstractInterpreter]: Error location(s) were unreachable [2019-01-11 11:47:45,881 INFO L272 AbstractInterpreter]: Visited 3 different actions 13 times. Merged at 1 different actions 5 times. Widened at 1 different actions 1 times. Found 1 fixpoints after 1 different actions. Largest state had 0 variables. [2019-01-11 11:47:45,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-01-11 11:47:45,882 INFO L403 sIntCurrentIteration]: Generating AbsInt predicates [2019-01-11 11:47:46,662 INFO L227 lantSequenceWeakener]: Weakened 2 states. On average, predicates are now at 83.33% of their original sizes. [2019-01-11 11:47:46,662 INFO L418 sIntCurrentIteration]: Unifying AI predicates