/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml -s ../../../trunk/examples/settings/automizer/concurrent/svcomp-Reach-32bit-Automizer_Default-noMmResRef-FA-NoLbe-MCR.epf -i ../../../trunk/examples/svcomp/pthread-wmm/thin001_rmo.opt.i -------------------------------------------------------------------------------- This is Ultimate 0.1.25-4336eb1 [2019-12-28 05:32:37,371 INFO L177 SettingsManager]: Resetting all preferences to default values... [2019-12-28 05:32:37,374 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2019-12-28 05:32:37,389 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-12-28 05:32:37,390 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2019-12-28 05:32:37,391 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2019-12-28 05:32:37,392 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2019-12-28 05:32:37,394 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2019-12-28 05:32:37,396 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2019-12-28 05:32:37,397 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2019-12-28 05:32:37,398 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2019-12-28 05:32:37,399 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2019-12-28 05:32:37,399 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2019-12-28 05:32:37,400 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2019-12-28 05:32:37,401 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2019-12-28 05:32:37,402 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2019-12-28 05:32:37,403 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2019-12-28 05:32:37,404 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2019-12-28 05:32:37,406 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2019-12-28 05:32:37,408 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2019-12-28 05:32:37,410 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2019-12-28 05:32:37,414 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2019-12-28 05:32:37,415 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2019-12-28 05:32:37,416 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2019-12-28 05:32:37,422 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2019-12-28 05:32:37,426 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2019-12-28 05:32:37,426 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2019-12-28 05:32:37,427 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2019-12-28 05:32:37,428 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2019-12-28 05:32:37,429 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-12-28 05:32:37,429 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2019-12-28 05:32:37,430 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2019-12-28 05:32:37,430 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2019-12-28 05:32:37,430 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2019-12-28 05:32:37,431 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2019-12-28 05:32:37,432 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2019-12-28 05:32:37,432 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/concurrent/svcomp-Reach-32bit-Automizer_Default-noMmResRef-FA-NoLbe-MCR.epf [2019-12-28 05:32:37,447 INFO L113 SettingsManager]: Loading preferences was successful [2019-12-28 05:32:37,447 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2019-12-28 05:32:37,448 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2019-12-28 05:32:37,448 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2019-12-28 05:32:37,448 INFO L138 SettingsManager]: * Use SBE=true [2019-12-28 05:32:37,449 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2019-12-28 05:32:37,449 INFO L138 SettingsManager]: * sizeof long=4 [2019-12-28 05:32:37,449 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2019-12-28 05:32:37,449 INFO L138 SettingsManager]: * sizeof POINTER=4 [2019-12-28 05:32:37,450 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2019-12-28 05:32:37,450 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2019-12-28 05:32:37,450 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2019-12-28 05:32:37,450 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2019-12-28 05:32:37,450 INFO L138 SettingsManager]: * sizeof long double=12 [2019-12-28 05:32:37,451 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2019-12-28 05:32:37,451 INFO L138 SettingsManager]: * Use constant arrays=true [2019-12-28 05:32:37,451 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2019-12-28 05:32:37,451 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2019-12-28 05:32:37,451 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2019-12-28 05:32:37,452 INFO L138 SettingsManager]: * To the following directory=./dump/ [2019-12-28 05:32:37,452 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2019-12-28 05:32:37,452 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-28 05:32:37,452 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2019-12-28 05:32:37,452 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2019-12-28 05:32:37,453 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2019-12-28 05:32:37,453 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2019-12-28 05:32:37,453 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2019-12-28 05:32:37,453 INFO L138 SettingsManager]: * Override the interpolant automaton setting of the refinement strategy=true [2019-12-28 05:32:37,453 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2019-12-28 05:32:37,454 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2019-12-28 05:32:37,454 INFO L138 SettingsManager]: * Interpolant automaton=MCR [2019-12-28 05:32:37,454 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2019-12-28 05:32:37,725 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2019-12-28 05:32:37,740 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-12-28 05:32:37,743 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2019-12-28 05:32:37,744 INFO L271 PluginConnector]: Initializing CDTParser... [2019-12-28 05:32:37,744 INFO L275 PluginConnector]: CDTParser initialized [2019-12-28 05:32:37,745 INFO L428 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/pthread-wmm/thin001_rmo.opt.i [2019-12-28 05:32:37,806 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a4aeeeaec/e1887a213a8944c7a90b14454b930399/FLAG59b3ebef8 [2019-12-28 05:32:38,377 INFO L306 CDTParser]: Found 1 translation units. [2019-12-28 05:32:38,378 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/pthread-wmm/thin001_rmo.opt.i [2019-12-28 05:32:38,397 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a4aeeeaec/e1887a213a8944c7a90b14454b930399/FLAG59b3ebef8 [2019-12-28 05:32:38,652 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a4aeeeaec/e1887a213a8944c7a90b14454b930399 [2019-12-28 05:32:38,662 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2019-12-28 05:32:38,664 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2019-12-28 05:32:38,665 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2019-12-28 05:32:38,666 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2019-12-28 05:32:38,669 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2019-12-28 05:32:38,670 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.12 05:32:38" (1/1) ... [2019-12-28 05:32:38,673 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1fdaac8e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 05:32:38, skipping insertion in model container [2019-12-28 05:32:38,673 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.12 05:32:38" (1/1) ... [2019-12-28 05:32:38,681 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2019-12-28 05:32:38,739 INFO L178 MainTranslator]: Built tables and reachable declarations [2019-12-28 05:32:39,221 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-28 05:32:39,234 INFO L203 MainTranslator]: Completed pre-run [2019-12-28 05:32:39,307 INFO L206 PostProcessor]: Analyzing one entry point: main [2019-12-28 05:32:39,381 INFO L208 MainTranslator]: Completed translation [2019-12-28 05:32:39,382 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 05:32:39 WrapperNode [2019-12-28 05:32:39,382 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2019-12-28 05:32:39,383 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2019-12-28 05:32:39,383 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2019-12-28 05:32:39,383 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2019-12-28 05:32:39,392 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 05:32:39" (1/1) ... [2019-12-28 05:32:39,413 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 05:32:39" (1/1) ... [2019-12-28 05:32:39,447 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-12-28 05:32:39,447 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2019-12-28 05:32:39,447 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2019-12-28 05:32:39,447 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2019-12-28 05:32:39,457 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 05:32:39" (1/1) ... [2019-12-28 05:32:39,458 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 05:32:39" (1/1) ... [2019-12-28 05:32:39,462 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 05:32:39" (1/1) ... [2019-12-28 05:32:39,463 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 05:32:39" (1/1) ... [2019-12-28 05:32:39,474 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 05:32:39" (1/1) ... [2019-12-28 05:32:39,478 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 05:32:39" (1/1) ... [2019-12-28 05:32:39,481 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 05:32:39" (1/1) ... [2019-12-28 05:32:39,487 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2019-12-28 05:32:39,487 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2019-12-28 05:32:39,487 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2019-12-28 05:32:39,488 INFO L275 PluginConnector]: RCFGBuilder initialized [2019-12-28 05:32:39,489 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 05:32:39" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2019-12-28 05:32:39,558 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2019-12-28 05:32:39,559 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2019-12-28 05:32:39,559 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2019-12-28 05:32:39,559 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2019-12-28 05:32:39,559 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2019-12-28 05:32:39,559 INFO L130 BoogieDeclarations]: Found specification of procedure P0 [2019-12-28 05:32:39,559 INFO L138 BoogieDeclarations]: Found implementation of procedure P0 [2019-12-28 05:32:39,560 INFO L130 BoogieDeclarations]: Found specification of procedure P1 [2019-12-28 05:32:39,560 INFO L138 BoogieDeclarations]: Found implementation of procedure P1 [2019-12-28 05:32:39,560 INFO L130 BoogieDeclarations]: Found specification of procedure P2 [2019-12-28 05:32:39,560 INFO L138 BoogieDeclarations]: Found implementation of procedure P2 [2019-12-28 05:32:39,560 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2019-12-28 05:32:39,560 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2019-12-28 05:32:39,561 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2019-12-28 05:32:39,561 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2019-12-28 05:32:39,563 WARN L205 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2019-12-28 05:32:40,307 INFO L282 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2019-12-28 05:32:40,308 INFO L287 CfgBuilder]: Removed 6 assume(true) statements. [2019-12-28 05:32:40,309 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.12 05:32:40 BoogieIcfgContainer [2019-12-28 05:32:40,310 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2019-12-28 05:32:40,311 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2019-12-28 05:32:40,311 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2019-12-28 05:32:40,315 INFO L275 PluginConnector]: TraceAbstraction initialized [2019-12-28 05:32:40,315 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.12 05:32:38" (1/3) ... [2019-12-28 05:32:40,316 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4467e0a1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.12 05:32:40, skipping insertion in model container [2019-12-28 05:32:40,316 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 05:32:39" (2/3) ... [2019-12-28 05:32:40,317 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4467e0a1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.12 05:32:40, skipping insertion in model container [2019-12-28 05:32:40,317 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.12 05:32:40" (3/3) ... [2019-12-28 05:32:40,319 INFO L109 eAbstractionObserver]: Analyzing ICFG thin001_rmo.opt.i [2019-12-28 05:32:40,330 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2019-12-28 05:32:40,330 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2019-12-28 05:32:40,338 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2019-12-28 05:32:40,339 INFO L340 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2019-12-28 05:32:40,391 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,391 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~nondet3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,392 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~nondet4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,392 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,392 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~mem5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,392 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,393 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~nondet3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,393 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~nondet4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,393 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,399 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,399 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~mem6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,400 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,400 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,401 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,401 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~mem6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,401 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,402 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,402 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,402 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,402 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,403 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,403 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,403 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,404 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,404 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,405 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,405 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,405 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,406 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,406 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,406 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,406 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,407 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,408 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,408 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,409 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,410 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,411 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,411 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,412 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,412 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,412 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,412 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,413 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,413 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,413 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,413 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,414 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,414 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,414 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,415 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,415 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,416 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,416 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,416 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,417 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,417 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,417 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,417 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,417 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,418 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,418 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,419 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,419 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,419 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,419 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,420 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,420 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,420 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,420 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,420 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,421 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,421 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,421 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,422 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,422 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,422 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,423 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,423 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,424 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~mem27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,424 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,425 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,425 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,426 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,427 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,427 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,427 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,427 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~mem28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,428 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,428 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,428 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,428 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,429 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,430 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,431 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~mem28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,431 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,432 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,432 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,436 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,436 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,439 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,439 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,447 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,447 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,463 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,463 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,464 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,464 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#in~arg.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,465 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,465 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,465 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,465 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,465 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,465 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,466 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,466 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,466 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,466 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,466 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,467 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,467 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,467 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,467 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,467 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,467 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,468 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,468 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,468 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,468 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,469 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,469 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,469 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,469 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,469 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,470 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,470 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,470 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,470 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,474 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite36| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,474 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,474 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,474 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite33| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,475 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite32| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,475 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite35| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,475 WARN L315 ript$VariableManager]: TermVariabe P2Thread1of1ForFork0_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,475 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite34| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,475 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~ite31| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,476 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,476 WARN L315 ript$VariableManager]: TermVariabe |P2Thread1of1ForFork0_#t~mem30| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,478 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite10| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,479 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,479 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,479 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~mem5| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,479 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,479 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~mem6| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,480 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite19| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,480 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite18| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,480 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite17| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,480 WARN L315 ript$VariableManager]: TermVariabe P0Thread1of1ForFork1_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,480 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite16| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,480 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite15| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,481 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite14| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,481 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite13| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,481 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite12| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,481 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite11| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,481 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite21| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,482 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite20| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,482 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite25| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,482 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite26| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,482 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite29| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,482 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~mem28| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,483 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~mem27| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,483 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite8| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,483 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite9| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,483 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite7| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,483 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~nondet3| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,484 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite24| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,484 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~nondet4| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,484 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite23| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,484 WARN L315 ript$VariableManager]: TermVariabe |P0Thread1of1ForFork1_#t~ite22| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,488 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.offset not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,488 WARN L315 ript$VariableManager]: TermVariabe P1Thread1of1ForFork2_~arg.base not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,489 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.offset| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,489 WARN L315 ript$VariableManager]: TermVariabe |P1Thread1of1ForFork2_#res.base| not constructed by VariableManager. Cannot ensure absence of name clashes. [2019-12-28 05:32:40,509 INFO L249 AbstractCegarLoop]: Starting to check reachability of 4 error locations. [2019-12-28 05:32:40,530 INFO L373 AbstractCegarLoop]: Interprodecural is true [2019-12-28 05:32:40,530 INFO L374 AbstractCegarLoop]: Hoare is true [2019-12-28 05:32:40,531 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2019-12-28 05:32:40,531 INFO L376 AbstractCegarLoop]: Backedges is MCR [2019-12-28 05:32:40,531 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2019-12-28 05:32:40,531 INFO L378 AbstractCegarLoop]: Difference is false [2019-12-28 05:32:40,531 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2019-12-28 05:32:40,531 INFO L383 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-12-28 05:32:40,551 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 170 places, 196 transitions [2019-12-28 05:32:52,621 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result 101069 states. [2019-12-28 05:32:52,622 INFO L276 IsEmpty]: Start isEmpty. Operand 101069 states. [2019-12-28 05:32:52,762 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2019-12-28 05:32:52,762 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:32:52,763 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:32:52,764 INFO L410 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:32:52,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:32:52,771 INFO L82 PathProgramCache]: Analyzing trace with hash 813058933, now seen corresponding path program 1 times [2019-12-28 05:32:52,785 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:32:52,786 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733560875] [2019-12-28 05:32:52,786 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:32:52,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:32:53,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:32:53,184 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733560875] [2019-12-28 05:32:53,185 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:32:53,185 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-28 05:32:53,186 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [745352781] [2019-12-28 05:32:53,187 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:32:53,203 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:32:53,239 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 81 states and 80 transitions. [2019-12-28 05:32:53,239 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:32:53,244 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 0 times. [2019-12-28 05:32:53,245 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-28 05:32:53,245 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:32:53,260 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-28 05:32:53,261 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-28 05:32:53,263 INFO L87 Difference]: Start difference. First operand 101069 states. Second operand 4 states. [2019-12-28 05:32:55,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:32:55,882 INFO L93 Difference]: Finished difference Result 155393 states and 683056 transitions. [2019-12-28 05:32:55,883 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-28 05:32:55,884 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 80 [2019-12-28 05:32:55,886 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:32:59,182 INFO L225 Difference]: With dead ends: 155393 [2019-12-28 05:32:59,182 INFO L226 Difference]: Without dead ends: 105193 [2019-12-28 05:32:59,184 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-28 05:33:00,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105193 states. [2019-12-28 05:33:03,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105193 to 101345. [2019-12-28 05:33:03,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101345 states. [2019-12-28 05:33:04,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101345 states to 101345 states and 456424 transitions. [2019-12-28 05:33:04,171 INFO L78 Accepts]: Start accepts. Automaton has 101345 states and 456424 transitions. Word has length 80 [2019-12-28 05:33:04,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:04,172 INFO L462 AbstractCegarLoop]: Abstraction has 101345 states and 456424 transitions. [2019-12-28 05:33:04,172 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-28 05:33:04,173 INFO L276 IsEmpty]: Start isEmpty. Operand 101345 states and 456424 transitions. [2019-12-28 05:33:04,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2019-12-28 05:33:04,261 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:04,262 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:04,262 INFO L410 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:04,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:04,263 INFO L82 PathProgramCache]: Analyzing trace with hash -326032991, now seen corresponding path program 1 times [2019-12-28 05:33:04,263 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:04,264 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425814803] [2019-12-28 05:33:04,264 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:04,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:04,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:04,487 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425814803] [2019-12-28 05:33:04,487 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:04,488 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-28 05:33:04,488 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [255288408] [2019-12-28 05:33:04,488 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:04,501 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:07,826 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 83 states and 82 transitions. [2019-12-28 05:33:07,827 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:07,827 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 0 times. [2019-12-28 05:33:07,830 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-28 05:33:07,831 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:07,831 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-28 05:33:07,831 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-28 05:33:07,831 INFO L87 Difference]: Start difference. First operand 101345 states and 456424 transitions. Second operand 6 states. [2019-12-28 05:33:09,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:09,387 INFO L93 Difference]: Finished difference Result 139693 states and 602621 transitions. [2019-12-28 05:33:09,388 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-28 05:33:09,388 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 82 [2019-12-28 05:33:09,388 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:10,704 INFO L225 Difference]: With dead ends: 139693 [2019-12-28 05:33:10,705 INFO L226 Difference]: Without dead ends: 139693 [2019-12-28 05:33:10,706 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2019-12-28 05:33:11,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139693 states. [2019-12-28 05:33:14,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139693 to 121677. [2019-12-28 05:33:14,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 121677 states. [2019-12-28 05:33:15,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121677 states to 121677 states and 533357 transitions. [2019-12-28 05:33:15,190 INFO L78 Accepts]: Start accepts. Automaton has 121677 states and 533357 transitions. Word has length 82 [2019-12-28 05:33:15,190 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:15,191 INFO L462 AbstractCegarLoop]: Abstraction has 121677 states and 533357 transitions. [2019-12-28 05:33:15,191 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-28 05:33:15,191 INFO L276 IsEmpty]: Start isEmpty. Operand 121677 states and 533357 transitions. [2019-12-28 05:33:15,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2019-12-28 05:33:15,234 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:15,234 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:15,234 INFO L410 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:15,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:15,234 INFO L82 PathProgramCache]: Analyzing trace with hash 871004482, now seen corresponding path program 1 times [2019-12-28 05:33:15,235 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:15,235 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [718324467] [2019-12-28 05:33:15,235 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:15,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:15,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:15,421 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [718324467] [2019-12-28 05:33:15,421 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:15,421 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-28 05:33:15,421 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1690653276] [2019-12-28 05:33:15,422 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:15,434 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:16,226 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 83 states and 82 transitions. [2019-12-28 05:33:16,227 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:16,227 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 0 times. [2019-12-28 05:33:16,228 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-28 05:33:16,228 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:16,228 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-28 05:33:16,229 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-28 05:33:16,229 INFO L87 Difference]: Start difference. First operand 121677 states and 533357 transitions. Second operand 4 states. [2019-12-28 05:33:16,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:16,838 INFO L93 Difference]: Finished difference Result 102295 states and 436661 transitions. [2019-12-28 05:33:16,839 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-28 05:33:16,839 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 82 [2019-12-28 05:33:16,839 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:17,131 INFO L225 Difference]: With dead ends: 102295 [2019-12-28 05:33:17,132 INFO L226 Difference]: Without dead ends: 99575 [2019-12-28 05:33:17,132 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-28 05:33:22,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99575 states. [2019-12-28 05:33:24,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99575 to 99575. [2019-12-28 05:33:24,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99575 states. [2019-12-28 05:33:24,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99575 states to 99575 states and 426978 transitions. [2019-12-28 05:33:24,730 INFO L78 Accepts]: Start accepts. Automaton has 99575 states and 426978 transitions. Word has length 82 [2019-12-28 05:33:24,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:24,731 INFO L462 AbstractCegarLoop]: Abstraction has 99575 states and 426978 transitions. [2019-12-28 05:33:24,731 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-28 05:33:24,731 INFO L276 IsEmpty]: Start isEmpty. Operand 99575 states and 426978 transitions. [2019-12-28 05:33:24,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2019-12-28 05:33:24,768 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:24,768 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:24,769 INFO L410 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:24,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:24,769 INFO L82 PathProgramCache]: Analyzing trace with hash -280324458, now seen corresponding path program 1 times [2019-12-28 05:33:24,770 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:24,770 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [980613744] [2019-12-28 05:33:24,770 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:24,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:24,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:24,955 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [980613744] [2019-12-28 05:33:24,955 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:24,956 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-28 05:33:24,956 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [203545600] [2019-12-28 05:33:24,956 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:24,972 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:24,996 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 88 states and 91 transitions. [2019-12-28 05:33:24,996 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:25,002 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 0 times. [2019-12-28 05:33:25,002 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-28 05:33:25,003 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:25,003 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-28 05:33:25,003 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2019-12-28 05:33:25,004 INFO L87 Difference]: Start difference. First operand 99575 states and 426978 transitions. Second operand 5 states. [2019-12-28 05:33:26,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:26,270 INFO L93 Difference]: Finished difference Result 28331 states and 108414 transitions. [2019-12-28 05:33:26,270 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-12-28 05:33:26,271 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 83 [2019-12-28 05:33:26,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:26,356 INFO L225 Difference]: With dead ends: 28331 [2019-12-28 05:33:26,357 INFO L226 Difference]: Without dead ends: 26114 [2019-12-28 05:33:26,358 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2019-12-28 05:33:26,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26114 states. [2019-12-28 05:33:26,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26114 to 26114. [2019-12-28 05:33:26,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26114 states. [2019-12-28 05:33:26,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26114 states to 26114 states and 99472 transitions. [2019-12-28 05:33:26,870 INFO L78 Accepts]: Start accepts. Automaton has 26114 states and 99472 transitions. Word has length 83 [2019-12-28 05:33:26,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:26,871 INFO L462 AbstractCegarLoop]: Abstraction has 26114 states and 99472 transitions. [2019-12-28 05:33:26,871 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-28 05:33:26,871 INFO L276 IsEmpty]: Start isEmpty. Operand 26114 states and 99472 transitions. [2019-12-28 05:33:26,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2019-12-28 05:33:26,893 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:26,893 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:26,893 INFO L410 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:26,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:26,894 INFO L82 PathProgramCache]: Analyzing trace with hash 1111812710, now seen corresponding path program 1 times [2019-12-28 05:33:26,894 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:26,895 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [5149554] [2019-12-28 05:33:26,895 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:26,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:27,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:27,039 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [5149554] [2019-12-28 05:33:27,039 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:27,039 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-28 05:33:27,039 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [255340883] [2019-12-28 05:33:27,039 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:27,062 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:27,094 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 99 states and 102 transitions. [2019-12-28 05:33:27,094 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:27,095 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 0 times. [2019-12-28 05:33:27,095 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-28 05:33:27,095 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:27,096 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-28 05:33:27,096 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-28 05:33:27,096 INFO L87 Difference]: Start difference. First operand 26114 states and 99472 transitions. Second operand 4 states. [2019-12-28 05:33:27,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:27,447 INFO L93 Difference]: Finished difference Result 25792 states and 96918 transitions. [2019-12-28 05:33:27,447 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-28 05:33:27,447 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 94 [2019-12-28 05:33:27,448 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:27,500 INFO L225 Difference]: With dead ends: 25792 [2019-12-28 05:33:27,500 INFO L226 Difference]: Without dead ends: 25792 [2019-12-28 05:33:27,500 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-28 05:33:27,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25792 states. [2019-12-28 05:33:29,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25792 to 24415. [2019-12-28 05:33:29,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24415 states. [2019-12-28 05:33:29,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24415 states to 24415 states and 92022 transitions. [2019-12-28 05:33:29,823 INFO L78 Accepts]: Start accepts. Automaton has 24415 states and 92022 transitions. Word has length 94 [2019-12-28 05:33:29,824 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:29,824 INFO L462 AbstractCegarLoop]: Abstraction has 24415 states and 92022 transitions. [2019-12-28 05:33:29,824 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-28 05:33:29,824 INFO L276 IsEmpty]: Start isEmpty. Operand 24415 states and 92022 transitions. [2019-12-28 05:33:29,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-12-28 05:33:29,846 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:29,846 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:29,847 INFO L410 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:29,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:29,847 INFO L82 PathProgramCache]: Analyzing trace with hash 823634256, now seen corresponding path program 1 times [2019-12-28 05:33:29,847 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:29,848 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476780720] [2019-12-28 05:33:29,848 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:29,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:29,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:29,951 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476780720] [2019-12-28 05:33:29,951 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:29,951 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-28 05:33:29,951 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1500057519] [2019-12-28 05:33:29,952 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:29,968 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:29,999 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 101 states and 104 transitions. [2019-12-28 05:33:30,000 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:30,001 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 0 times. [2019-12-28 05:33:30,001 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2019-12-28 05:33:30,001 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:30,001 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2019-12-28 05:33:30,001 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-12-28 05:33:30,002 INFO L87 Difference]: Start difference. First operand 24415 states and 92022 transitions. Second operand 5 states. [2019-12-28 05:33:30,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:30,751 INFO L93 Difference]: Finished difference Result 46463 states and 173591 transitions. [2019-12-28 05:33:30,751 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-28 05:33:30,751 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 96 [2019-12-28 05:33:30,752 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:30,848 INFO L225 Difference]: With dead ends: 46463 [2019-12-28 05:33:30,849 INFO L226 Difference]: Without dead ends: 46463 [2019-12-28 05:33:30,849 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-12-28 05:33:30,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46463 states. [2019-12-28 05:33:31,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46463 to 17662. [2019-12-28 05:33:31,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17662 states. [2019-12-28 05:33:31,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17662 states to 17662 states and 66369 transitions. [2019-12-28 05:33:31,326 INFO L78 Accepts]: Start accepts. Automaton has 17662 states and 66369 transitions. Word has length 96 [2019-12-28 05:33:31,326 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:31,326 INFO L462 AbstractCegarLoop]: Abstraction has 17662 states and 66369 transitions. [2019-12-28 05:33:31,326 INFO L463 AbstractCegarLoop]: Interpolant automaton has 5 states. [2019-12-28 05:33:31,327 INFO L276 IsEmpty]: Start isEmpty. Operand 17662 states and 66369 transitions. [2019-12-28 05:33:31,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-12-28 05:33:31,345 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:31,346 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:31,346 INFO L410 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:31,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:31,346 INFO L82 PathProgramCache]: Analyzing trace with hash -973317103, now seen corresponding path program 1 times [2019-12-28 05:33:31,347 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:31,347 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884541629] [2019-12-28 05:33:31,347 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:31,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:31,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:31,668 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [884541629] [2019-12-28 05:33:31,668 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:31,668 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-28 05:33:31,669 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1628203785] [2019-12-28 05:33:31,669 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:31,689 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:31,715 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 101 states and 104 transitions. [2019-12-28 05:33:31,715 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:31,716 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 0 times. [2019-12-28 05:33:31,716 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-28 05:33:31,716 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:31,716 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-28 05:33:31,716 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-28 05:33:31,716 INFO L87 Difference]: Start difference. First operand 17662 states and 66369 transitions. Second operand 4 states. [2019-12-28 05:33:31,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:31,945 INFO L93 Difference]: Finished difference Result 22410 states and 83383 transitions. [2019-12-28 05:33:31,946 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-28 05:33:31,946 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 96 [2019-12-28 05:33:31,946 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:31,989 INFO L225 Difference]: With dead ends: 22410 [2019-12-28 05:33:31,989 INFO L226 Difference]: Without dead ends: 22410 [2019-12-28 05:33:31,990 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-28 05:33:32,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22410 states. [2019-12-28 05:33:32,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22410 to 19476. [2019-12-28 05:33:32,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19476 states. [2019-12-28 05:33:32,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19476 states to 19476 states and 72568 transitions. [2019-12-28 05:33:32,322 INFO L78 Accepts]: Start accepts. Automaton has 19476 states and 72568 transitions. Word has length 96 [2019-12-28 05:33:32,322 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:32,322 INFO L462 AbstractCegarLoop]: Abstraction has 19476 states and 72568 transitions. [2019-12-28 05:33:32,322 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-28 05:33:32,322 INFO L276 IsEmpty]: Start isEmpty. Operand 19476 states and 72568 transitions. [2019-12-28 05:33:32,347 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-12-28 05:33:32,347 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:32,348 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:32,348 INFO L410 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:32,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:32,348 INFO L82 PathProgramCache]: Analyzing trace with hash -1970389456, now seen corresponding path program 1 times [2019-12-28 05:33:32,349 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:32,349 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510654196] [2019-12-28 05:33:32,349 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:32,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:32,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:32,466 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510654196] [2019-12-28 05:33:32,467 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:32,467 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-28 05:33:32,467 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [2062998617] [2019-12-28 05:33:32,467 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:32,485 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:32,508 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 101 states and 104 transitions. [2019-12-28 05:33:32,508 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:32,508 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 0 times. [2019-12-28 05:33:32,509 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-28 05:33:32,509 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:32,509 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-28 05:33:32,509 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-28 05:33:32,509 INFO L87 Difference]: Start difference. First operand 19476 states and 72568 transitions. Second operand 6 states. [2019-12-28 05:33:33,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:33,391 INFO L93 Difference]: Finished difference Result 32166 states and 118738 transitions. [2019-12-28 05:33:33,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-28 05:33:33,391 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 96 [2019-12-28 05:33:33,392 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:33,456 INFO L225 Difference]: With dead ends: 32166 [2019-12-28 05:33:33,456 INFO L226 Difference]: Without dead ends: 32166 [2019-12-28 05:33:33,457 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2019-12-28 05:33:33,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32166 states. [2019-12-28 05:33:34,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32166 to 27909. [2019-12-28 05:33:34,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27909 states. [2019-12-28 05:33:34,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27909 states to 27909 states and 103207 transitions. [2019-12-28 05:33:34,245 INFO L78 Accepts]: Start accepts. Automaton has 27909 states and 103207 transitions. Word has length 96 [2019-12-28 05:33:34,246 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:34,246 INFO L462 AbstractCegarLoop]: Abstraction has 27909 states and 103207 transitions. [2019-12-28 05:33:34,246 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-28 05:33:34,246 INFO L276 IsEmpty]: Start isEmpty. Operand 27909 states and 103207 transitions. [2019-12-28 05:33:34,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-12-28 05:33:34,271 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:34,271 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:34,272 INFO L410 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:34,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:34,272 INFO L82 PathProgramCache]: Analyzing trace with hash 517123377, now seen corresponding path program 1 times [2019-12-28 05:33:34,273 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:34,273 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469437847] [2019-12-28 05:33:34,273 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:34,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:34,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:34,462 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1469437847] [2019-12-28 05:33:34,463 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:34,463 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2019-12-28 05:33:34,463 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1027445319] [2019-12-28 05:33:34,463 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:34,481 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:34,506 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 101 states and 104 transitions. [2019-12-28 05:33:34,507 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:34,507 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 0 times. [2019-12-28 05:33:34,507 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2019-12-28 05:33:34,507 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:34,508 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2019-12-28 05:33:34,508 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2019-12-28 05:33:34,508 INFO L87 Difference]: Start difference. First operand 27909 states and 103207 transitions. Second operand 9 states. [2019-12-28 05:33:36,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:36,890 INFO L93 Difference]: Finished difference Result 67691 states and 245174 transitions. [2019-12-28 05:33:36,890 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2019-12-28 05:33:36,890 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 96 [2019-12-28 05:33:36,891 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:37,037 INFO L225 Difference]: With dead ends: 67691 [2019-12-28 05:33:37,038 INFO L226 Difference]: Without dead ends: 67691 [2019-12-28 05:33:37,038 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 107 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=145, Invalid=455, Unknown=0, NotChecked=0, Total=600 [2019-12-28 05:33:37,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67691 states. [2019-12-28 05:33:38,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67691 to 34404. [2019-12-28 05:33:38,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34404 states. [2019-12-28 05:33:38,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34404 states to 34404 states and 124809 transitions. [2019-12-28 05:33:38,241 INFO L78 Accepts]: Start accepts. Automaton has 34404 states and 124809 transitions. Word has length 96 [2019-12-28 05:33:38,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:38,242 INFO L462 AbstractCegarLoop]: Abstraction has 34404 states and 124809 transitions. [2019-12-28 05:33:38,242 INFO L463 AbstractCegarLoop]: Interpolant automaton has 9 states. [2019-12-28 05:33:38,242 INFO L276 IsEmpty]: Start isEmpty. Operand 34404 states and 124809 transitions. [2019-12-28 05:33:38,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-12-28 05:33:38,272 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:38,272 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:38,272 INFO L410 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:38,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:38,272 INFO L82 PathProgramCache]: Analyzing trace with hash 1478737394, now seen corresponding path program 1 times [2019-12-28 05:33:38,273 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:38,273 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [493723514] [2019-12-28 05:33:38,273 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:38,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:38,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:38,341 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [493723514] [2019-12-28 05:33:38,342 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:38,342 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-12-28 05:33:38,342 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1737995466] [2019-12-28 05:33:38,342 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:38,362 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:38,396 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 101 states and 104 transitions. [2019-12-28 05:33:38,397 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:38,397 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 0 times. [2019-12-28 05:33:38,397 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2019-12-28 05:33:38,398 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:38,398 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2019-12-28 05:33:38,398 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-12-28 05:33:38,399 INFO L87 Difference]: Start difference. First operand 34404 states and 124809 transitions. Second operand 4 states. [2019-12-28 05:33:38,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:38,879 INFO L93 Difference]: Finished difference Result 34278 states and 123966 transitions. [2019-12-28 05:33:38,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-12-28 05:33:38,880 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 96 [2019-12-28 05:33:38,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:38,945 INFO L225 Difference]: With dead ends: 34278 [2019-12-28 05:33:38,945 INFO L226 Difference]: Without dead ends: 33279 [2019-12-28 05:33:38,946 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-12-28 05:33:39,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33279 states. [2019-12-28 05:33:39,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33279 to 28027. [2019-12-28 05:33:39,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28027 states. [2019-12-28 05:33:39,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28027 states to 28027 states and 101374 transitions. [2019-12-28 05:33:39,829 INFO L78 Accepts]: Start accepts. Automaton has 28027 states and 101374 transitions. Word has length 96 [2019-12-28 05:33:39,829 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:39,829 INFO L462 AbstractCegarLoop]: Abstraction has 28027 states and 101374 transitions. [2019-12-28 05:33:39,829 INFO L463 AbstractCegarLoop]: Interpolant automaton has 4 states. [2019-12-28 05:33:39,829 INFO L276 IsEmpty]: Start isEmpty. Operand 28027 states and 101374 transitions. [2019-12-28 05:33:39,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-12-28 05:33:39,853 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:39,853 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:39,853 INFO L410 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:39,853 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:39,853 INFO L82 PathProgramCache]: Analyzing trace with hash -1302178446, now seen corresponding path program 1 times [2019-12-28 05:33:39,856 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:39,856 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486074558] [2019-12-28 05:33:39,857 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:39,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:39,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:39,974 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1486074558] [2019-12-28 05:33:39,974 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:39,974 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-28 05:33:39,974 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1230702470] [2019-12-28 05:33:39,975 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:39,998 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:40,037 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 101 states and 104 transitions. [2019-12-28 05:33:40,038 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:40,039 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 0 times. [2019-12-28 05:33:40,039 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-28 05:33:40,040 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:40,040 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-28 05:33:40,040 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2019-12-28 05:33:40,041 INFO L87 Difference]: Start difference. First operand 28027 states and 101374 transitions. Second operand 6 states. [2019-12-28 05:33:40,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:40,544 INFO L93 Difference]: Finished difference Result 32376 states and 116433 transitions. [2019-12-28 05:33:40,544 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2019-12-28 05:33:40,544 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 96 [2019-12-28 05:33:40,545 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:40,627 INFO L225 Difference]: With dead ends: 32376 [2019-12-28 05:33:40,628 INFO L226 Difference]: Without dead ends: 32376 [2019-12-28 05:33:40,628 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 3 SyntacticMatches, 4 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2019-12-28 05:33:40,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32376 states. [2019-12-28 05:33:41,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32376 to 28782. [2019-12-28 05:33:41,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28782 states. [2019-12-28 05:33:41,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28782 states to 28782 states and 103909 transitions. [2019-12-28 05:33:41,100 INFO L78 Accepts]: Start accepts. Automaton has 28782 states and 103909 transitions. Word has length 96 [2019-12-28 05:33:41,100 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:41,100 INFO L462 AbstractCegarLoop]: Abstraction has 28782 states and 103909 transitions. [2019-12-28 05:33:41,100 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-28 05:33:41,100 INFO L276 IsEmpty]: Start isEmpty. Operand 28782 states and 103909 transitions. [2019-12-28 05:33:41,126 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-12-28 05:33:41,126 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:41,126 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:41,127 INFO L410 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:41,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:41,127 INFO L82 PathProgramCache]: Analyzing trace with hash -57413965, now seen corresponding path program 1 times [2019-12-28 05:33:41,127 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:41,128 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1629296468] [2019-12-28 05:33:41,128 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:41,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:41,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:41,275 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1629296468] [2019-12-28 05:33:41,275 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:41,275 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2019-12-28 05:33:41,276 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [737805363] [2019-12-28 05:33:41,276 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:41,300 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:41,331 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 101 states and 104 transitions. [2019-12-28 05:33:41,332 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:41,332 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 0 times. [2019-12-28 05:33:41,332 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-28 05:33:41,333 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:41,333 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-28 05:33:41,333 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2019-12-28 05:33:41,333 INFO L87 Difference]: Start difference. First operand 28782 states and 103909 transitions. Second operand 8 states. [2019-12-28 05:33:42,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:42,058 INFO L93 Difference]: Finished difference Result 34527 states and 122631 transitions. [2019-12-28 05:33:42,058 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2019-12-28 05:33:42,058 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 96 [2019-12-28 05:33:42,058 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:42,125 INFO L225 Difference]: With dead ends: 34527 [2019-12-28 05:33:42,125 INFO L226 Difference]: Without dead ends: 34527 [2019-12-28 05:33:42,125 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2019-12-28 05:33:42,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34527 states. [2019-12-28 05:33:42,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34527 to 28837. [2019-12-28 05:33:42,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28837 states. [2019-12-28 05:33:42,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28837 states to 28837 states and 102790 transitions. [2019-12-28 05:33:42,861 INFO L78 Accepts]: Start accepts. Automaton has 28837 states and 102790 transitions. Word has length 96 [2019-12-28 05:33:42,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:42,861 INFO L462 AbstractCegarLoop]: Abstraction has 28837 states and 102790 transitions. [2019-12-28 05:33:42,861 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-28 05:33:42,861 INFO L276 IsEmpty]: Start isEmpty. Operand 28837 states and 102790 transitions. [2019-12-28 05:33:42,885 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2019-12-28 05:33:42,886 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:42,886 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:42,886 INFO L410 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:42,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:42,886 INFO L82 PathProgramCache]: Analyzing trace with hash -1864868428, now seen corresponding path program 1 times [2019-12-28 05:33:42,887 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:42,887 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [9120023] [2019-12-28 05:33:42,887 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:42,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:42,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:42,986 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [9120023] [2019-12-28 05:33:42,986 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:42,986 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2019-12-28 05:33:42,986 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1285898887] [2019-12-28 05:33:42,986 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:43,005 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:43,037 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 101 states and 104 transitions. [2019-12-28 05:33:43,038 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:43,038 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 0 times. [2019-12-28 05:33:43,038 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-28 05:33:43,039 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:43,039 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-28 05:33:43,039 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2019-12-28 05:33:43,039 INFO L87 Difference]: Start difference. First operand 28837 states and 102790 transitions. Second operand 6 states. [2019-12-28 05:33:43,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:43,144 INFO L93 Difference]: Finished difference Result 8911 states and 27784 transitions. [2019-12-28 05:33:43,144 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-28 05:33:43,144 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 96 [2019-12-28 05:33:43,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:43,161 INFO L225 Difference]: With dead ends: 8911 [2019-12-28 05:33:43,162 INFO L226 Difference]: Without dead ends: 7678 [2019-12-28 05:33:43,162 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2019-12-28 05:33:43,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7678 states. [2019-12-28 05:33:43,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7678 to 6646. [2019-12-28 05:33:43,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6646 states. [2019-12-28 05:33:43,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6646 states to 6646 states and 20237 transitions. [2019-12-28 05:33:43,325 INFO L78 Accepts]: Start accepts. Automaton has 6646 states and 20237 transitions. Word has length 96 [2019-12-28 05:33:43,325 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:43,325 INFO L462 AbstractCegarLoop]: Abstraction has 6646 states and 20237 transitions. [2019-12-28 05:33:43,326 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-28 05:33:43,326 INFO L276 IsEmpty]: Start isEmpty. Operand 6646 states and 20237 transitions. [2019-12-28 05:33:43,338 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-12-28 05:33:43,339 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:43,339 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:43,339 INFO L410 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:43,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:43,340 INFO L82 PathProgramCache]: Analyzing trace with hash -1126666891, now seen corresponding path program 1 times [2019-12-28 05:33:43,341 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:43,347 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774507021] [2019-12-28 05:33:43,347 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:43,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:43,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:43,448 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [774507021] [2019-12-28 05:33:43,448 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:43,449 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-28 05:33:43,449 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [817496648] [2019-12-28 05:33:43,449 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:43,482 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:43,646 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 234 states and 371 transitions. [2019-12-28 05:33:43,646 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:43,676 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 2 times. [2019-12-28 05:33:43,676 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2019-12-28 05:33:43,677 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:43,677 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2019-12-28 05:33:43,677 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2019-12-28 05:33:43,677 INFO L87 Difference]: Start difference. First operand 6646 states and 20237 transitions. Second operand 6 states. [2019-12-28 05:33:44,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:44,090 INFO L93 Difference]: Finished difference Result 22501 states and 69334 transitions. [2019-12-28 05:33:44,091 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2019-12-28 05:33:44,091 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 113 [2019-12-28 05:33:44,091 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:44,192 INFO L225 Difference]: With dead ends: 22501 [2019-12-28 05:33:44,193 INFO L226 Difference]: Without dead ends: 22501 [2019-12-28 05:33:44,193 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2019-12-28 05:33:44,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22501 states. [2019-12-28 05:33:44,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22501 to 8118. [2019-12-28 05:33:44,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8118 states. [2019-12-28 05:33:44,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8118 states to 8118 states and 24855 transitions. [2019-12-28 05:33:44,574 INFO L78 Accepts]: Start accepts. Automaton has 8118 states and 24855 transitions. Word has length 113 [2019-12-28 05:33:44,575 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:44,575 INFO L462 AbstractCegarLoop]: Abstraction has 8118 states and 24855 transitions. [2019-12-28 05:33:44,575 INFO L463 AbstractCegarLoop]: Interpolant automaton has 6 states. [2019-12-28 05:33:44,575 INFO L276 IsEmpty]: Start isEmpty. Operand 8118 states and 24855 transitions. [2019-12-28 05:33:44,600 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-12-28 05:33:44,601 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:44,601 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:44,601 INFO L410 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:44,601 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:44,601 INFO L82 PathProgramCache]: Analyzing trace with hash 1877825045, now seen corresponding path program 1 times [2019-12-28 05:33:44,602 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:44,602 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1424949008] [2019-12-28 05:33:44,603 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:44,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:44,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:44,787 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1424949008] [2019-12-28 05:33:44,788 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:44,788 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2019-12-28 05:33:44,788 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1170221395] [2019-12-28 05:33:44,788 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:44,833 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:45,117 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 234 states and 371 transitions. [2019-12-28 05:33:45,118 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:45,261 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 9 times. [2019-12-28 05:33:45,261 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2019-12-28 05:33:45,261 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:45,262 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2019-12-28 05:33:45,263 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=175, Unknown=0, NotChecked=0, Total=210 [2019-12-28 05:33:45,263 INFO L87 Difference]: Start difference. First operand 8118 states and 24855 transitions. Second operand 15 states. [2019-12-28 05:33:47,661 WARN L192 SmtUtils]: Spent 104.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 43 [2019-12-28 05:33:51,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:51,397 INFO L93 Difference]: Finished difference Result 50883 states and 151244 transitions. [2019-12-28 05:33:51,397 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 82 states. [2019-12-28 05:33:51,397 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 113 [2019-12-28 05:33:51,398 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:51,522 INFO L225 Difference]: With dead ends: 50883 [2019-12-28 05:33:51,522 INFO L226 Difference]: Without dead ends: 50883 [2019-12-28 05:33:51,529 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 13 SyntacticMatches, 3 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2500 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=1154, Invalid=6156, Unknown=0, NotChecked=0, Total=7310 [2019-12-28 05:33:51,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50883 states. [2019-12-28 05:33:52,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50883 to 11590. [2019-12-28 05:33:52,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11590 states. [2019-12-28 05:33:52,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11590 states to 11590 states and 35675 transitions. [2019-12-28 05:33:52,429 INFO L78 Accepts]: Start accepts. Automaton has 11590 states and 35675 transitions. Word has length 113 [2019-12-28 05:33:52,430 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:52,430 INFO L462 AbstractCegarLoop]: Abstraction has 11590 states and 35675 transitions. [2019-12-28 05:33:52,430 INFO L463 AbstractCegarLoop]: Interpolant automaton has 15 states. [2019-12-28 05:33:52,430 INFO L276 IsEmpty]: Start isEmpty. Operand 11590 states and 35675 transitions. [2019-12-28 05:33:52,465 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2019-12-28 05:33:52,465 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:52,465 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:52,465 INFO L410 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:52,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:52,466 INFO L82 PathProgramCache]: Analyzing trace with hash 70370582, now seen corresponding path program 1 times [2019-12-28 05:33:52,467 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:52,467 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082041831] [2019-12-28 05:33:52,467 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:52,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:52,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:52,542 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1082041831] [2019-12-28 05:33:52,542 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:52,542 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-12-28 05:33:52,542 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1547686343] [2019-12-28 05:33:52,543 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:52,577 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:52,762 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 234 states and 371 transitions. [2019-12-28 05:33:52,762 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:52,766 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 1 times. [2019-12-28 05:33:52,766 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2019-12-28 05:33:52,766 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:52,766 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2019-12-28 05:33:52,766 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-28 05:33:52,767 INFO L87 Difference]: Start difference. First operand 11590 states and 35675 transitions. Second operand 3 states. [2019-12-28 05:33:52,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:52,817 INFO L93 Difference]: Finished difference Result 11590 states and 35648 transitions. [2019-12-28 05:33:52,817 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2019-12-28 05:33:52,817 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 113 [2019-12-28 05:33:52,818 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:52,843 INFO L225 Difference]: With dead ends: 11590 [2019-12-28 05:33:52,843 INFO L226 Difference]: Without dead ends: 11590 [2019-12-28 05:33:52,843 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2019-12-28 05:33:52,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11590 states. [2019-12-28 05:33:53,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11590 to 11590. [2019-12-28 05:33:53,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11590 states. [2019-12-28 05:33:53,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11590 states to 11590 states and 35648 transitions. [2019-12-28 05:33:53,066 INFO L78 Accepts]: Start accepts. Automaton has 11590 states and 35648 transitions. Word has length 113 [2019-12-28 05:33:53,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:53,067 INFO L462 AbstractCegarLoop]: Abstraction has 11590 states and 35648 transitions. [2019-12-28 05:33:53,067 INFO L463 AbstractCegarLoop]: Interpolant automaton has 3 states. [2019-12-28 05:33:53,067 INFO L276 IsEmpty]: Start isEmpty. Operand 11590 states and 35648 transitions. [2019-12-28 05:33:53,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2019-12-28 05:33:53,100 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:53,101 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:53,101 INFO L410 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:53,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:53,101 INFO L82 PathProgramCache]: Analyzing trace with hash -1192348262, now seen corresponding path program 1 times [2019-12-28 05:33:53,102 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:53,103 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814867836] [2019-12-28 05:33:53,103 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:53,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:53,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:53,304 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1814867836] [2019-12-28 05:33:53,304 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:53,305 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-28 05:33:53,305 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [2098198747] [2019-12-28 05:33:53,305 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:53,340 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:53,534 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 236 states and 373 transitions. [2019-12-28 05:33:53,534 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:53,536 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 0 times. [2019-12-28 05:33:53,536 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-28 05:33:53,537 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:53,537 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-28 05:33:53,537 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2019-12-28 05:33:53,537 INFO L87 Difference]: Start difference. First operand 11590 states and 35648 transitions. Second operand 7 states. [2019-12-28 05:33:53,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:53,682 INFO L93 Difference]: Finished difference Result 13525 states and 41144 transitions. [2019-12-28 05:33:53,683 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-28 05:33:53,683 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 115 [2019-12-28 05:33:53,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:53,692 INFO L225 Difference]: With dead ends: 13525 [2019-12-28 05:33:53,692 INFO L226 Difference]: Without dead ends: 4912 [2019-12-28 05:33:53,693 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=77, Unknown=0, NotChecked=0, Total=110 [2019-12-28 05:33:53,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4912 states. [2019-12-28 05:33:53,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4912 to 4912. [2019-12-28 05:33:53,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4912 states. [2019-12-28 05:33:53,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4912 states to 4912 states and 12725 transitions. [2019-12-28 05:33:53,769 INFO L78 Accepts]: Start accepts. Automaton has 4912 states and 12725 transitions. Word has length 115 [2019-12-28 05:33:53,770 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:53,770 INFO L462 AbstractCegarLoop]: Abstraction has 4912 states and 12725 transitions. [2019-12-28 05:33:53,770 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-28 05:33:53,770 INFO L276 IsEmpty]: Start isEmpty. Operand 4912 states and 12725 transitions. [2019-12-28 05:33:53,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2019-12-28 05:33:53,777 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:53,777 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:53,777 INFO L410 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:53,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:53,778 INFO L82 PathProgramCache]: Analyzing trace with hash -212202412, now seen corresponding path program 2 times [2019-12-28 05:33:53,778 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:53,779 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080756649] [2019-12-28 05:33:53,779 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:53,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:53,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:53,906 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2080756649] [2019-12-28 05:33:53,907 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:53,907 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2019-12-28 05:33:53,907 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [817171063] [2019-12-28 05:33:53,907 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:53,941 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:54,166 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 209 states and 301 transitions. [2019-12-28 05:33:54,166 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:54,179 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 1 times. [2019-12-28 05:33:54,179 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2019-12-28 05:33:54,179 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:54,180 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2019-12-28 05:33:54,180 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2019-12-28 05:33:54,180 INFO L87 Difference]: Start difference. First operand 4912 states and 12725 transitions. Second operand 8 states. [2019-12-28 05:33:54,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:54,275 INFO L93 Difference]: Finished difference Result 6586 states and 17576 transitions. [2019-12-28 05:33:54,276 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2019-12-28 05:33:54,276 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 115 [2019-12-28 05:33:54,276 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:54,281 INFO L225 Difference]: With dead ends: 6586 [2019-12-28 05:33:54,281 INFO L226 Difference]: Without dead ends: 2830 [2019-12-28 05:33:54,281 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=40, Invalid=92, Unknown=0, NotChecked=0, Total=132 [2019-12-28 05:33:54,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2830 states. [2019-12-28 05:33:54,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2830 to 2830. [2019-12-28 05:33:54,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2830 states. [2019-12-28 05:33:54,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2830 states to 2830 states and 7403 transitions. [2019-12-28 05:33:54,311 INFO L78 Accepts]: Start accepts. Automaton has 2830 states and 7403 transitions. Word has length 115 [2019-12-28 05:33:54,311 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:54,311 INFO L462 AbstractCegarLoop]: Abstraction has 2830 states and 7403 transitions. [2019-12-28 05:33:54,311 INFO L463 AbstractCegarLoop]: Interpolant automaton has 8 states. [2019-12-28 05:33:54,311 INFO L276 IsEmpty]: Start isEmpty. Operand 2830 states and 7403 transitions. [2019-12-28 05:33:54,315 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2019-12-28 05:33:54,315 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:54,315 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:54,315 INFO L410 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:54,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:54,316 INFO L82 PathProgramCache]: Analyzing trace with hash 1053398540, now seen corresponding path program 3 times [2019-12-28 05:33:54,317 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:54,317 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957933178] [2019-12-28 05:33:54,317 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:54,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2019-12-28 05:33:54,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-12-28 05:33:54,428 INFO L348 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1957933178] [2019-12-28 05:33:54,428 INFO L220 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-12-28 05:33:54,428 INFO L233 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-12-28 05:33:54,428 INFO L156 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [409845034] [2019-12-28 05:33:54,429 INFO L132 pAbStrategyModuleMcr]: Constructing automaton for MCR equivalence class. [2019-12-28 05:33:54,464 INFO L197 pAbStrategyModuleMcr]: Started intersection. [2019-12-28 05:33:54,598 INFO L208 pAbStrategyModuleMcr]: Finished intersection with 182 states and 247 transitions. [2019-12-28 05:33:54,598 INFO L219 pAbStrategyModuleMcr]: Constructing interpolant automaton by labelling MCR automaton. [2019-12-28 05:33:54,675 INFO L288 pAbStrategyModuleMcr]: Construction finished. Needed to calculate wp 9 times. [2019-12-28 05:33:54,675 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2019-12-28 05:33:54,676 INFO L143 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2019-12-28 05:33:54,676 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2019-12-28 05:33:54,676 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-28 05:33:54,676 INFO L87 Difference]: Start difference. First operand 2830 states and 7403 transitions. Second operand 7 states. [2019-12-28 05:33:54,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2019-12-28 05:33:54,767 INFO L93 Difference]: Finished difference Result 2654 states and 6927 transitions. [2019-12-28 05:33:54,768 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-12-28 05:33:54,768 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 115 [2019-12-28 05:33:54,768 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2019-12-28 05:33:54,772 INFO L225 Difference]: With dead ends: 2654 [2019-12-28 05:33:54,772 INFO L226 Difference]: Without dead ends: 2654 [2019-12-28 05:33:54,772 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-12-28 05:33:54,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2654 states. [2019-12-28 05:33:54,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2654 to 2644. [2019-12-28 05:33:54,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2644 states. [2019-12-28 05:33:54,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2644 states to 2644 states and 6909 transitions. [2019-12-28 05:33:54,813 INFO L78 Accepts]: Start accepts. Automaton has 2644 states and 6909 transitions. Word has length 115 [2019-12-28 05:33:54,814 INFO L84 Accepts]: Finished accepts. word is rejected. [2019-12-28 05:33:54,814 INFO L462 AbstractCegarLoop]: Abstraction has 2644 states and 6909 transitions. [2019-12-28 05:33:54,814 INFO L463 AbstractCegarLoop]: Interpolant automaton has 7 states. [2019-12-28 05:33:54,814 INFO L276 IsEmpty]: Start isEmpty. Operand 2644 states and 6909 transitions. [2019-12-28 05:33:54,818 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2019-12-28 05:33:54,818 INFO L403 BasicCegarLoop]: Found error trace [2019-12-28 05:33:54,819 INFO L411 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-12-28 05:33:54,819 INFO L410 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr2INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2019-12-28 05:33:54,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2019-12-28 05:33:54,819 INFO L82 PathProgramCache]: Analyzing trace with hash 1976082123, now seen corresponding path program 1 times [2019-12-28 05:33:54,820 INFO L163 FreeRefinementEngine]: Executing refinement strategy CAMEL [2019-12-28 05:33:54,820 INFO L348 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [183277686] [2019-12-28 05:33:54,820 INFO L94 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2019-12-28 05:33:54,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-28 05:33:54,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2019-12-28 05:33:54,980 INFO L174 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2019-12-28 05:33:54,981 INFO L476 BasicCegarLoop]: Counterexample might be feasible [2019-12-28 05:33:55,258 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.12 05:33:55 BasicIcfg [2019-12-28 05:33:55,258 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2019-12-28 05:33:55,261 INFO L168 Benchmark]: Toolchain (without parser) took 76596.06 ms. Allocated memory was 137.9 MB in the beginning and 2.9 GB in the end (delta: 2.8 GB). Free memory was 98.9 MB in the beginning and 1.8 GB in the end (delta: -1.7 GB). Peak memory consumption was 1.1 GB. Max. memory is 7.1 GB. [2019-12-28 05:33:55,266 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 137.9 MB. Free memory was 119.8 MB in the beginning and 119.6 MB in the end (delta: 209.7 kB). Peak memory consumption was 209.7 kB. Max. memory is 7.1 GB. [2019-12-28 05:33:55,269 INFO L168 Benchmark]: CACSL2BoogieTranslator took 717.09 ms. Allocated memory was 137.9 MB in the beginning and 202.4 MB in the end (delta: 64.5 MB). Free memory was 98.7 MB in the beginning and 156.2 MB in the end (delta: -57.5 MB). Peak memory consumption was 25.0 MB. Max. memory is 7.1 GB. [2019-12-28 05:33:55,270 INFO L168 Benchmark]: Boogie Procedure Inliner took 63.90 ms. Allocated memory is still 202.4 MB. Free memory was 156.2 MB in the beginning and 153.5 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 7.1 GB. [2019-12-28 05:33:55,270 INFO L168 Benchmark]: Boogie Preprocessor took 40.01 ms. Allocated memory is still 202.4 MB. Free memory was 153.5 MB in the beginning and 151.5 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 7.1 GB. [2019-12-28 05:33:55,271 INFO L168 Benchmark]: RCFGBuilder took 822.69 ms. Allocated memory is still 202.4 MB. Free memory was 151.5 MB in the beginning and 102.5 MB in the end (delta: 49.0 MB). Peak memory consumption was 49.0 MB. Max. memory is 7.1 GB. [2019-12-28 05:33:55,272 INFO L168 Benchmark]: TraceAbstraction took 74946.79 ms. Allocated memory was 202.4 MB in the beginning and 2.9 GB in the end (delta: 2.7 GB). Free memory was 102.5 MB in the beginning and 1.8 GB in the end (delta: -1.7 GB). Peak memory consumption was 1.0 GB. Max. memory is 7.1 GB. [2019-12-28 05:33:55,279 INFO L335 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 137.9 MB. Free memory was 119.8 MB in the beginning and 119.6 MB in the end (delta: 209.7 kB). Peak memory consumption was 209.7 kB. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 717.09 ms. Allocated memory was 137.9 MB in the beginning and 202.4 MB in the end (delta: 64.5 MB). Free memory was 98.7 MB in the beginning and 156.2 MB in the end (delta: -57.5 MB). Peak memory consumption was 25.0 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 63.90 ms. Allocated memory is still 202.4 MB. Free memory was 156.2 MB in the beginning and 153.5 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 7.1 GB. * Boogie Preprocessor took 40.01 ms. Allocated memory is still 202.4 MB. Free memory was 153.5 MB in the beginning and 151.5 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 7.1 GB. * RCFGBuilder took 822.69 ms. Allocated memory is still 202.4 MB. Free memory was 151.5 MB in the beginning and 102.5 MB in the end (delta: 49.0 MB). Peak memory consumption was 49.0 MB. Max. memory is 7.1 GB. * TraceAbstraction took 74946.79 ms. Allocated memory was 202.4 MB in the beginning and 2.9 GB in the end (delta: 2.7 GB). Free memory was 102.5 MB in the beginning and 1.8 GB in the end (delta: -1.7 GB). Peak memory consumption was 1.0 GB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 5]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L696] 0 int __unbuffered_cnt = 0; VAL [__unbuffered_cnt=0] [L698] 0 int __unbuffered_p0_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0] [L699] 0 _Bool __unbuffered_p0_EAX$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0] [L700] 0 int __unbuffered_p0_EAX$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0] [L701] 0 _Bool __unbuffered_p0_EAX$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0] [L702] 0 _Bool __unbuffered_p0_EAX$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0] [L703] 0 _Bool __unbuffered_p0_EAX$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0] [L704] 0 _Bool __unbuffered_p0_EAX$r_buff0_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0] [L705] 0 _Bool __unbuffered_p0_EAX$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0] [L706] 0 _Bool __unbuffered_p0_EAX$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0] [L707] 0 _Bool __unbuffered_p0_EAX$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0] [L708] 0 _Bool __unbuffered_p0_EAX$r_buff1_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0] [L709] 0 _Bool __unbuffered_p0_EAX$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0] [L710] 0 int *__unbuffered_p0_EAX$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}] [L711] 0 int __unbuffered_p0_EAX$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0] [L712] 0 _Bool __unbuffered_p0_EAX$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0] [L713] 0 int __unbuffered_p0_EAX$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0] [L714] 0 _Bool __unbuffered_p0_EAX$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0] [L716] 0 int __unbuffered_p1_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0] [L718] 0 int __unbuffered_p2_EAX = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0] [L719] 0 _Bool main$tmp_guard0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0] [L720] 0 _Bool main$tmp_guard1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0] [L722] 0 int x = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0] [L724] 0 int y = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0] [L726] 0 int z = 0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}] [L727] 0 _Bool z$flush_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0] [L728] 0 int z$mem_tmp; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0] [L729] 0 _Bool z$r_buff0_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0] [L730] 0 _Bool z$r_buff0_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0] [L731] 0 _Bool z$r_buff0_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0] [L732] 0 _Bool z$r_buff0_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0] [L733] 0 _Bool z$r_buff1_thd0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0] [L734] 0 _Bool z$r_buff1_thd1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0] [L735] 0 _Bool z$r_buff1_thd2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0] [L736] 0 _Bool z$r_buff1_thd3; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0] [L737] 0 _Bool z$read_delayed; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0] [L738] 0 int *z$read_delayed_var; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}] [L739] 0 int z$w_buff0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0] [L740] 0 _Bool z$w_buff0_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0] [L741] 0 int z$w_buff1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0] [L742] 0 _Bool z$w_buff1_used; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L743] 0 _Bool weak$$choice0; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L744] 0 _Bool weak$$choice1; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L745] 0 _Bool weak$$choice2; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L822] 0 pthread_t t2696; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L823] FCALL, FORK 0 pthread_create(&t2696, ((void *)0), P0, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L824] 0 pthread_t t2697; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=0, weak$$choice1=0, weak$$choice2=0, x=0, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L749] 1 weak$$choice0 = __VERIFIER_nondet_bool() [L750] 1 weak$$choice2 = __VERIFIER_nondet_bool() [L751] 1 z$flush_delayed = weak$$choice2 [L752] EXPR 1 \read(z) [L752] 1 z$mem_tmp = z [L753] EXPR 1 !z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z : (z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : z$w_buff1) [L753] EXPR 1 \read(z) [L753] EXPR 1 !z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z : (z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : z$w_buff1) VAL [!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z : (z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : z$w_buff1)=0, \read(z)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=0, y=0, z={5:0}, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L825] FCALL, FORK 0 pthread_create(&t2697, ((void *)0), P1, ((void *)0)) VAL [!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z : (z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : z$w_buff1)=0, \read(z)=0, __unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=0, y=0, z={5:0}, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L753] 1 z = !z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z : (z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : z$w_buff1) [L754] EXPR 1 weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : z$w_buff0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : z$w_buff0))=0, x=0, y=0, z={5:0}, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L826] 0 pthread_t t2698; VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : z$w_buff0))=0, x=0, y=0, z={5:0}, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L827] FCALL, FORK 0 pthread_create(&t2698, ((void *)0), P2, ((void *)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : z$w_buff0))=0, x=0, y=0, z={5:0}, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L754] 1 z$w_buff0 = weak$$choice2 ? z$w_buff0 : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$w_buff0 : (z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff0 : z$w_buff0)) [L755] EXPR 1 weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff1 : z$w_buff1)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff1 : z$w_buff1))=0, x=0, y=0, z={5:0}, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L755] 1 z$w_buff1 = weak$$choice2 ? z$w_buff1 : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$w_buff1 : (z$w_buff0_used && z$r_buff0_thd1 ? z$w_buff1 : z$w_buff1)) [L756] EXPR 1 weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used))=0, x=0, y=0, z={5:0}, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L756] 1 z$w_buff0_used = weak$$choice2 ? z$w_buff0_used : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$w_buff0_used : (z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$w_buff0_used)) [L757] EXPR 1 weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : (_Bool)0))=0, x=0, y=0, z={5:0}, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L757] 1 z$w_buff1_used = weak$$choice2 ? z$w_buff1_used : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$w_buff1_used : (z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : (_Bool)0)) [L758] EXPR 1 weak$$choice2 ? z$r_buff0_thd1 : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$r_buff0_thd1 : (z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$r_buff0_thd1)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? z$r_buff0_thd1 : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$r_buff0_thd1 : (z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$r_buff0_thd1))=0, x=0, y=0, z={5:0}, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L758] 1 z$r_buff0_thd1 = weak$$choice2 ? z$r_buff0_thd1 : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$r_buff0_thd1 : (z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : z$r_buff0_thd1)) [L759] EXPR 1 weak$$choice2 ? z$r_buff1_thd1 : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$r_buff1_thd1 : (z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : (_Bool)0)) VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=0, __unbuffered_p0_EAX$read_delayed_var={0:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, weak$$choice2 ? z$r_buff1_thd1 : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$r_buff1_thd1 : (z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : (_Bool)0))=0, x=0, y=0, z={5:0}, z$flush_delayed=1, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L759] 1 z$r_buff1_thd1 = weak$$choice2 ? z$r_buff1_thd1 : (!z$w_buff0_used || !z$r_buff0_thd1 && !z$w_buff1_used || !z$r_buff0_thd1 && !z$r_buff1_thd1 ? z$r_buff1_thd1 : (z$w_buff0_used && z$r_buff0_thd1 ? (_Bool)0 : (_Bool)0)) [L760] 1 __unbuffered_p0_EAX$read_delayed = (_Bool)1 [L761] 1 __unbuffered_p0_EAX$read_delayed_var = &z [L762] EXPR 1 \read(z) [L762] 1 __unbuffered_p0_EAX = z [L763] EXPR 1 z$flush_delayed ? z$mem_tmp : z VAL [__unbuffered_cnt=0, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=0, y=0, z={5:0}, z$flush_delayed=1, z$flush_delayed ? z$mem_tmp : z=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L763] 1 z = z$flush_delayed ? z$mem_tmp : z [L764] 1 z$flush_delayed = (_Bool)0 [L767] 1 x = 1 [L772] 1 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=1, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=0, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=0, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L779] 2 __unbuffered_p1_EAX = x [L782] 2 y = 1 [L787] 2 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=0, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L794] 3 __unbuffered_p2_EAX = y [L797] 3 z = 1 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L800] EXPR 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L800] EXPR 3 z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z [L800] EXPR 3 \read(z) [L800] EXPR 3 z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z VAL [\read(z)=1, __unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z=1] [L800] EXPR 3 z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) VAL [\read(z)=1, __unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z)=1, z$w_buff1=0, z$w_buff1_used=0, z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z=1] [L800] 3 z = z$w_buff0_used && z$r_buff0_thd3 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd3 ? z$w_buff1 : z) [L801] EXPR 3 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L801] 3 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$w_buff0_used [L802] EXPR 3 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used=0, z$w_buff1=0, z$w_buff1_used=0] [L802] 3 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$w_buff1_used [L803] EXPR 3 z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3=0, z$w_buff1=0, z$w_buff1_used=0] [L803] 3 z$r_buff0_thd3 = z$w_buff0_used && z$r_buff0_thd3 ? (_Bool)0 : z$r_buff0_thd3 [L804] EXPR 3 z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 VAL [__unbuffered_cnt=2, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3=0, z$w_buff1=0, z$w_buff1_used=0] [L804] 3 z$r_buff1_thd3 = z$w_buff0_used && z$r_buff0_thd3 || z$w_buff1_used && z$r_buff1_thd3 ? (_Bool)0 : z$r_buff1_thd3 [L807] 3 __unbuffered_cnt = __unbuffered_cnt + 1 VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=0, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L829] 0 main$tmp_guard0 = __unbuffered_cnt == 3 VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L833] EXPR 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L833] EXPR 0 z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z [L833] EXPR 0 \read(z) [L833] EXPR 0 z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L833] EXPR 0 z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L833] 0 z = z$w_buff0_used && z$r_buff0_thd0 ? z$w_buff0 : (z$w_buff1_used && z$r_buff1_thd0 ? z$w_buff1 : z) [L834] EXPR 0 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L834] 0 z$w_buff0_used = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$w_buff0_used [L835] EXPR 0 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L835] 0 z$w_buff1_used = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$w_buff1_used [L836] EXPR 0 z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L836] 0 z$r_buff0_thd0 = z$w_buff0_used && z$r_buff0_thd0 ? (_Bool)0 : z$r_buff0_thd0 [L837] EXPR 0 z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=0, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L837] 0 z$r_buff1_thd0 = z$w_buff0_used && z$r_buff0_thd0 || z$w_buff1_used && z$r_buff1_thd0 ? (_Bool)0 : z$r_buff1_thd0 [L840] 0 weak$$choice1 = __VERIFIER_nondet_bool() [L841] EXPR 0 __unbuffered_p0_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p0_EAX$read_delayed_var : __unbuffered_p0_EAX) : __unbuffered_p0_EAX VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=1, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L841] EXPR 0 weak$$choice1 ? *__unbuffered_p0_EAX$read_delayed_var : __unbuffered_p0_EAX [L841] EXPR 0 \read(*__unbuffered_p0_EAX$read_delayed_var) [L841] EXPR 0 weak$$choice1 ? *__unbuffered_p0_EAX$read_delayed_var : __unbuffered_p0_EAX VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=1, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L841] EXPR 0 __unbuffered_p0_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p0_EAX$read_delayed_var : __unbuffered_p0_EAX) : __unbuffered_p0_EAX VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=0, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=1, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L841] 0 __unbuffered_p0_EAX = __unbuffered_p0_EAX$read_delayed ? (weak$$choice1 ? *__unbuffered_p0_EAX$read_delayed_var : __unbuffered_p0_EAX) : __unbuffered_p0_EAX [L842] 0 main$tmp_guard1 = !(__unbuffered_p0_EAX == 1 && __unbuffered_p1_EAX == 1 && __unbuffered_p2_EAX == 1) VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=1, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L5] COND TRUE 0 !expression VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=1, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] [L5] 0 __VERIFIER_error() VAL [__unbuffered_cnt=3, __unbuffered_p0_EAX=1, __unbuffered_p0_EAX$flush_delayed=0, __unbuffered_p0_EAX$mem_tmp=0, __unbuffered_p0_EAX$r_buff0_thd0=0, __unbuffered_p0_EAX$r_buff0_thd1=0, __unbuffered_p0_EAX$r_buff0_thd2=0, __unbuffered_p0_EAX$r_buff0_thd3=0, __unbuffered_p0_EAX$r_buff1_thd0=0, __unbuffered_p0_EAX$r_buff1_thd1=0, __unbuffered_p0_EAX$r_buff1_thd2=0, __unbuffered_p0_EAX$r_buff1_thd3=0, __unbuffered_p0_EAX$read_delayed=1, __unbuffered_p0_EAX$read_delayed_var={5:0}, __unbuffered_p0_EAX$w_buff0=0, __unbuffered_p0_EAX$w_buff0_used=0, __unbuffered_p0_EAX$w_buff1=0, __unbuffered_p0_EAX$w_buff1_used=0, __unbuffered_p1_EAX=1, __unbuffered_p2_EAX=1, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, arg={0:0}, main$tmp_guard0=1, main$tmp_guard1=0, weak$$choice0=2, weak$$choice1=1, weak$$choice2=1, x=1, y=1, z={5:0}, z$flush_delayed=0, z$mem_tmp=0, z$r_buff0_thd0=0, z$r_buff0_thd1=0, z$r_buff0_thd2=0, z$r_buff0_thd3=0, z$r_buff1_thd0=0, z$r_buff1_thd1=0, z$r_buff1_thd2=0, z$r_buff1_thd3=0, z$read_delayed=0, z$read_delayed_var={0:0}, z$w_buff0=0, z$w_buff0_used=0, z$w_buff1=0, z$w_buff1_used=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 161 locations, 1 error locations. Result: UNSAFE, OverallTime: 74.4s, OverallIterations: 20, TraceHistogramMax: 1, AutomataDifference: 25.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, HoareTripleCheckerStatistics: 5147 SDtfs, 7997 SDslu, 16359 SDs, 0 SdLazy, 6893 SolverSat, 457 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 291 GetRequests, 74 SyntacticMatches, 15 SemanticMatches, 202 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2645 ImplicationChecksByTransitivity, 4.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=121677occurred in iteration=2, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 26.5s AutomataMinimizationTime, 19 MinimizatonAttempts, 161774 StatesRemovedByMinimization, 14 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.7s SatisfiabilityAnalysisTime, 1.9s InterpolantComputationTime, 1988 NumberOfCodeBlocks, 1988 NumberOfCodeBlocksAsserted, 20 NumberOfCheckSat, 1854 ConstructedInterpolants, 0 QuantifiedInterpolants, 465699 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 19 InterpolantComputations, 19 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...