/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -s ../../../trunk/examples/settings/automizer/concurrent/svcomp-Reach-32bit-Automizer_Default-noMmResRef-FA-NoLbe.epf -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml -i ../../../trunk/examples/concurrent/bpl/weaver-benchmarks/generated/popl20/figure1-alt.wvr.bpl -------------------------------------------------------------------------------- This is Ultimate 0.2.1-2cf4d3f9dd5fed411db405f577e28237a543b59a-2cf4d3f [2021-08-12 19:28:09,190 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-08-12 19:28:09,193 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-08-12 19:28:09,234 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2021-08-12 19:28:09,628 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/concurrent/svcomp-Reach-32bit-Automizer_Default-noMmResRef-FA-NoLbe.epf [2021-08-12 19:28:09,666 INFO L113 SettingsManager]: Loading preferences was successful [2021-08-12 19:28:09,667 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-08-12 19:28:09,667 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-08-12 19:28:09,667 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-08-12 19:28:09,670 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-08-12 19:28:09,671 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-08-12 19:28:09,671 INFO L138 SettingsManager]: * Use SBE=true [2021-08-12 19:28:09,671 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-08-12 19:28:09,671 INFO L138 SettingsManager]: * sizeof long=4 [2021-08-12 19:28:09,671 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-08-12 19:28:09,672 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-08-12 19:28:09,672 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-08-12 19:28:09,672 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2021-08-12 19:28:09,672 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-08-12 19:28:09,672 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2021-08-12 19:28:09,673 INFO L138 SettingsManager]: * sizeof long double=12 [2021-08-12 19:28:09,673 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-08-12 19:28:09,673 INFO L138 SettingsManager]: * Use constant arrays=true [2021-08-12 19:28:09,673 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2021-08-12 19:28:09,673 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-08-12 19:28:09,673 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-08-12 19:28:09,673 INFO L138 SettingsManager]: * To the following directory=./dump/ [2021-08-12 19:28:09,673 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2021-08-12 19:28:09,674 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-08-12 19:28:09,674 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-08-12 19:28:09,674 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-08-12 19:28:09,674 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-08-12 19:28:09,674 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-08-12 19:28:09,674 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2021-08-12 19:28:09,675 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2021-08-12 19:28:09,675 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release [2021-08-12 19:28:09,953 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-08-12 19:28:09,971 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-08-12 19:28:09,974 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-08-12 19:28:09,975 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2021-08-12 19:28:09,976 INFO L275 PluginConnector]: Boogie PL CUP Parser initialized [2021-08-12 19:28:09,977 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/concurrent/bpl/weaver-benchmarks/generated/popl20/figure1-alt.wvr.bpl [2021-08-12 19:28:09,977 INFO L110 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/concurrent/bpl/weaver-benchmarks/generated/popl20/figure1-alt.wvr.bpl' [2021-08-12 19:28:10,000 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-08-12 19:28:10,002 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2021-08-12 19:28:10,003 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-08-12 19:28:10,003 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-08-12 19:28:10,003 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-08-12 19:28:10,014 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "figure1-alt.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 12.08 07:28:09" (1/1) ... [2021-08-12 19:28:10,019 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "figure1-alt.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 12.08 07:28:09" (1/1) ... [2021-08-12 19:28:10,024 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-08-12 19:28:10,025 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-08-12 19:28:10,025 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-08-12 19:28:10,025 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-08-12 19:28:10,032 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "figure1-alt.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 12.08 07:28:09" (1/1) ... [2021-08-12 19:28:10,032 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "figure1-alt.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 12.08 07:28:09" (1/1) ... [2021-08-12 19:28:10,033 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "figure1-alt.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 12.08 07:28:09" (1/1) ... [2021-08-12 19:28:10,033 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "figure1-alt.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 12.08 07:28:09" (1/1) ... [2021-08-12 19:28:10,034 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "figure1-alt.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 12.08 07:28:09" (1/1) ... [2021-08-12 19:28:10,036 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "figure1-alt.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 12.08 07:28:09" (1/1) ... [2021-08-12 19:28:10,037 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "figure1-alt.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 12.08 07:28:09" (1/1) ... [2021-08-12 19:28:10,038 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-08-12 19:28:10,039 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-08-12 19:28:10,039 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-08-12 19:28:10,039 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-08-12 19:28:10,040 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "figure1-alt.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 12.08 07:28:09" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-08-12 19:28:10,101 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread1 given in one single declaration [2021-08-12 19:28:10,102 INFO L130 BoogieDeclarations]: Found specification of procedure thread1 [2021-08-12 19:28:10,102 INFO L138 BoogieDeclarations]: Found implementation of procedure thread1 [2021-08-12 19:28:10,102 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread2 given in one single declaration [2021-08-12 19:28:10,102 INFO L130 BoogieDeclarations]: Found specification of procedure thread2 [2021-08-12 19:28:10,102 INFO L138 BoogieDeclarations]: Found implementation of procedure thread2 [2021-08-12 19:28:10,102 INFO L124 BoogieDeclarations]: Specification and implementation of procedure ULTIMATE.start given in one single declaration [2021-08-12 19:28:10,103 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-08-12 19:28:10,103 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-08-12 19:28:10,103 WARN L209 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2021-08-12 19:28:10,261 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-08-12 19:28:10,262 INFO L299 CfgBuilder]: Removed 0 assume(true) statements. [2021-08-12 19:28:10,263 INFO L202 PluginConnector]: Adding new model figure1-alt.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.08 07:28:10 BoogieIcfgContainer [2021-08-12 19:28:10,263 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-08-12 19:28:10,265 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2021-08-12 19:28:10,265 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2021-08-12 19:28:10,267 INFO L275 PluginConnector]: TraceAbstraction initialized [2021-08-12 19:28:10,267 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "figure1-alt.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 12.08 07:28:09" (1/2) ... [2021-08-12 19:28:10,268 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@73240c22 and model type figure1-alt.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.08 07:28:10, skipping insertion in model container [2021-08-12 19:28:10,268 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "figure1-alt.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.08 07:28:10" (2/2) ... [2021-08-12 19:28:10,269 INFO L111 eAbstractionObserver]: Analyzing ICFG figure1-alt.wvr.bpl [2021-08-12 19:28:10,274 INFO L206 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2021-08-12 19:28:10,274 INFO L154 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2021-08-12 19:28:10,275 INFO L445 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2021-08-12 19:28:10,300 INFO L149 ThreadInstanceAdder]: Constructed 2 joinOtherThreadTransitions. [2021-08-12 19:28:10,318 INFO L255 AbstractCegarLoop]: Starting to check reachability of 3 error locations. [2021-08-12 19:28:10,335 INFO L378 AbstractCegarLoop]: Interprodecural is true [2021-08-12 19:28:10,335 INFO L379 AbstractCegarLoop]: Hoare is true [2021-08-12 19:28:10,335 INFO L380 AbstractCegarLoop]: Compute interpolants for FPandBP [2021-08-12 19:28:10,335 INFO L381 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2021-08-12 19:28:10,336 INFO L382 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-08-12 19:28:10,336 INFO L383 AbstractCegarLoop]: Difference is false [2021-08-12 19:28:10,336 INFO L384 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-08-12 19:28:10,336 INFO L388 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2021-08-12 19:28:10,360 INFO L100 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 28 places, 23 transitions, 62 flow [2021-08-12 19:28:10,391 INFO L122 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result has 35 states, 33 states have (on average 1.7878787878787878) internal successors, (59), 34 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:10,393 INFO L276 IsEmpty]: Start isEmpty. Operand has 35 states, 33 states have (on average 1.7878787878787878) internal successors, (59), 34 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:10,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2021-08-12 19:28:10,399 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:10,399 INFO L550 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:10,399 INFO L430 AbstractCegarLoop]: === Iteration 1 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:10,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:10,404 INFO L82 PathProgramCache]: Analyzing trace with hash -1829606569, now seen corresponding path program 1 times [2021-08-12 19:28:10,427 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:10,428 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870561423] [2021-08-12 19:28:10,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:10,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:10,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:10,807 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:10,808 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1870561423] [2021-08-12 19:28:10,809 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1870561423] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-12 19:28:10,809 INFO L226 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-12 19:28:10,810 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2021-08-12 19:28:10,810 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2029963585] [2021-08-12 19:28:10,814 INFO L462 AbstractCegarLoop]: Interpolant automaton has 9 states [2021-08-12 19:28:10,814 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:10,833 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2021-08-12 19:28:10,834 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2021-08-12 19:28:10,836 INFO L87 Difference]: Start difference. First operand has 35 states, 33 states have (on average 1.7878787878787878) internal successors, (59), 34 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 9 states, 9 states have (on average 1.6666666666666667) internal successors, (15), 8 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:11,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:11,065 INFO L93 Difference]: Finished difference Result 92 states and 164 transitions. [2021-08-12 19:28:11,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-08-12 19:28:11,068 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 1.6666666666666667) internal successors, (15), 8 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 15 [2021-08-12 19:28:11,068 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:11,077 INFO L225 Difference]: With dead ends: 92 [2021-08-12 19:28:11,077 INFO L226 Difference]: Without dead ends: 52 [2021-08-12 19:28:11,081 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 252.2ms TimeCoverageRelationStatistics Valid=64, Invalid=118, Unknown=0, NotChecked=0, Total=182 [2021-08-12 19:28:11,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2021-08-12 19:28:11,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 39. [2021-08-12 19:28:11,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 38 states have (on average 1.8157894736842106) internal successors, (69), 38 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:11,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 69 transitions. [2021-08-12 19:28:11,110 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 69 transitions. Word has length 15 [2021-08-12 19:28:11,110 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:11,111 INFO L482 AbstractCegarLoop]: Abstraction has 39 states and 69 transitions. [2021-08-12 19:28:11,111 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 9 states, 9 states have (on average 1.6666666666666667) internal successors, (15), 8 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:11,111 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 69 transitions. [2021-08-12 19:28:11,112 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2021-08-12 19:28:11,112 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:11,112 INFO L550 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:11,112 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2021-08-12 19:28:11,112 INFO L430 AbstractCegarLoop]: === Iteration 2 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:11,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:11,113 INFO L82 PathProgramCache]: Analyzing trace with hash -1179537599, now seen corresponding path program 2 times [2021-08-12 19:28:11,114 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:11,114 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1516664718] [2021-08-12 19:28:11,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:11,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:11,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:11,224 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:11,225 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1516664718] [2021-08-12 19:28:11,226 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1516664718] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-12 19:28:11,226 INFO L226 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-12 19:28:11,226 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2021-08-12 19:28:11,226 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [967544421] [2021-08-12 19:28:11,228 INFO L462 AbstractCegarLoop]: Interpolant automaton has 9 states [2021-08-12 19:28:11,228 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:11,229 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2021-08-12 19:28:11,230 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2021-08-12 19:28:11,230 INFO L87 Difference]: Start difference. First operand 39 states and 69 transitions. Second operand has 9 states, 9 states have (on average 1.6666666666666667) internal successors, (15), 8 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:11,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:11,363 INFO L93 Difference]: Finished difference Result 52 states and 87 transitions. [2021-08-12 19:28:11,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-08-12 19:28:11,364 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 1.6666666666666667) internal successors, (15), 8 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 15 [2021-08-12 19:28:11,364 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:11,365 INFO L225 Difference]: With dead ends: 52 [2021-08-12 19:28:11,365 INFO L226 Difference]: Without dead ends: 43 [2021-08-12 19:28:11,366 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 144.8ms TimeCoverageRelationStatistics Valid=64, Invalid=118, Unknown=0, NotChecked=0, Total=182 [2021-08-12 19:28:11,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2021-08-12 19:28:11,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 41. [2021-08-12 19:28:11,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 40 states have (on average 1.8) internal successors, (72), 40 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:11,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 72 transitions. [2021-08-12 19:28:11,372 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 72 transitions. Word has length 15 [2021-08-12 19:28:11,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:11,372 INFO L482 AbstractCegarLoop]: Abstraction has 41 states and 72 transitions. [2021-08-12 19:28:11,372 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 9 states, 9 states have (on average 1.6666666666666667) internal successors, (15), 8 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:11,372 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 72 transitions. [2021-08-12 19:28:11,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2021-08-12 19:28:11,373 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:11,373 INFO L550 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:11,374 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2021-08-12 19:28:11,374 INFO L430 AbstractCegarLoop]: === Iteration 3 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:11,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:11,374 INFO L82 PathProgramCache]: Analyzing trace with hash 1059156761, now seen corresponding path program 1 times [2021-08-12 19:28:11,374 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:11,375 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905750653] [2021-08-12 19:28:11,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:11,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:11,523 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:11,524 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:11,524 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1905750653] [2021-08-12 19:28:11,524 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1905750653] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:11,524 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1002472448] [2021-08-12 19:28:11,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-08-12 19:28:11,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:11,576 INFO L263 TraceCheckSpWp]: Trace formula consists of 33 conjuncts, 13 conjunts are in the unsatisfiable core [2021-08-12 19:28:11,579 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:11,878 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:11,878 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1002472448] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:11,879 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:11,879 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 16 [2021-08-12 19:28:11,879 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1621088134] [2021-08-12 19:28:11,881 INFO L462 AbstractCegarLoop]: Interpolant automaton has 17 states [2021-08-12 19:28:11,881 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:11,882 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2021-08-12 19:28:11,882 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=210, Unknown=0, NotChecked=0, Total=272 [2021-08-12 19:28:11,883 INFO L87 Difference]: Start difference. First operand 41 states and 72 transitions. Second operand has 17 states, 17 states have (on average 1.8823529411764706) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:12,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:12,272 INFO L93 Difference]: Finished difference Result 109 states and 188 transitions. [2021-08-12 19:28:12,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-08-12 19:28:12,278 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.8823529411764706) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 17 [2021-08-12 19:28:12,279 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:12,284 INFO L225 Difference]: With dead ends: 109 [2021-08-12 19:28:12,285 INFO L226 Difference]: Without dead ends: 93 [2021-08-12 19:28:12,285 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 9 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 99 ImplicationChecksByTransitivity, 448.2ms TimeCoverageRelationStatistics Valid=143, Invalid=457, Unknown=0, NotChecked=0, Total=600 [2021-08-12 19:28:12,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2021-08-12 19:28:12,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 46. [2021-08-12 19:28:12,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 45 states have (on average 1.8666666666666667) internal successors, (84), 45 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:12,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 84 transitions. [2021-08-12 19:28:12,297 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 84 transitions. Word has length 17 [2021-08-12 19:28:12,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:12,297 INFO L482 AbstractCegarLoop]: Abstraction has 46 states and 84 transitions. [2021-08-12 19:28:12,298 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 17 states, 17 states have (on average 1.8823529411764706) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:12,298 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 84 transitions. [2021-08-12 19:28:12,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2021-08-12 19:28:12,298 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:12,298 INFO L550 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:12,517 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable2 [2021-08-12 19:28:12,517 INFO L430 AbstractCegarLoop]: === Iteration 4 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:12,517 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:12,518 INFO L82 PathProgramCache]: Analyzing trace with hash 1709225731, now seen corresponding path program 2 times [2021-08-12 19:28:12,518 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:12,518 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378231451] [2021-08-12 19:28:12,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:12,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:12,682 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:12,683 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:12,683 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1378231451] [2021-08-12 19:28:12,683 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1378231451] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:12,683 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1031171262] [2021-08-12 19:28:12,683 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:12,721 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-08-12 19:28:12,722 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:12,722 INFO L263 TraceCheckSpWp]: Trace formula consists of 33 conjuncts, 13 conjunts are in the unsatisfiable core [2021-08-12 19:28:12,725 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:12,948 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:12,949 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1031171262] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:12,949 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:12,949 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 16 [2021-08-12 19:28:12,949 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795593310] [2021-08-12 19:28:12,949 INFO L462 AbstractCegarLoop]: Interpolant automaton has 17 states [2021-08-12 19:28:12,949 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:12,950 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2021-08-12 19:28:12,950 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=210, Unknown=0, NotChecked=0, Total=272 [2021-08-12 19:28:12,950 INFO L87 Difference]: Start difference. First operand 46 states and 84 transitions. Second operand has 17 states, 17 states have (on average 1.8823529411764706) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:13,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:13,383 INFO L93 Difference]: Finished difference Result 119 states and 201 transitions. [2021-08-12 19:28:13,383 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-08-12 19:28:13,383 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.8823529411764706) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 17 [2021-08-12 19:28:13,384 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:13,384 INFO L225 Difference]: With dead ends: 119 [2021-08-12 19:28:13,385 INFO L226 Difference]: Without dead ends: 103 [2021-08-12 19:28:13,385 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 9 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 135 ImplicationChecksByTransitivity, 505.6ms TimeCoverageRelationStatistics Valid=188, Invalid=568, Unknown=0, NotChecked=0, Total=756 [2021-08-12 19:28:13,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2021-08-12 19:28:13,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 46. [2021-08-12 19:28:13,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 45 states have (on average 1.8666666666666667) internal successors, (84), 45 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:13,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 84 transitions. [2021-08-12 19:28:13,408 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 84 transitions. Word has length 17 [2021-08-12 19:28:13,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:13,408 INFO L482 AbstractCegarLoop]: Abstraction has 46 states and 84 transitions. [2021-08-12 19:28:13,408 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 17 states, 17 states have (on average 1.8823529411764706) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:13,409 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 84 transitions. [2021-08-12 19:28:13,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2021-08-12 19:28:13,409 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:13,409 INFO L550 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:13,610 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,3 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:13,610 INFO L430 AbstractCegarLoop]: === Iteration 5 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:13,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:13,611 INFO L82 PathProgramCache]: Analyzing trace with hash -351634071, now seen corresponding path program 3 times [2021-08-12 19:28:13,611 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:13,611 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1274069452] [2021-08-12 19:28:13,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:13,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:13,737 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:13,737 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:13,737 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1274069452] [2021-08-12 19:28:13,737 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1274069452] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:13,737 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [949759276] [2021-08-12 19:28:13,737 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:13,776 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2021-08-12 19:28:13,777 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:13,777 INFO L263 TraceCheckSpWp]: Trace formula consists of 33 conjuncts, 13 conjunts are in the unsatisfiable core [2021-08-12 19:28:13,778 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:14,012 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:14,012 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [949759276] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:14,012 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:14,013 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 16 [2021-08-12 19:28:14,013 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [318355154] [2021-08-12 19:28:14,013 INFO L462 AbstractCegarLoop]: Interpolant automaton has 17 states [2021-08-12 19:28:14,013 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:14,014 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2021-08-12 19:28:14,014 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=211, Unknown=0, NotChecked=0, Total=272 [2021-08-12 19:28:14,014 INFO L87 Difference]: Start difference. First operand 46 states and 84 transitions. Second operand has 17 states, 17 states have (on average 1.8823529411764706) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:14,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:14,384 INFO L93 Difference]: Finished difference Result 96 states and 159 transitions. [2021-08-12 19:28:14,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-08-12 19:28:14,384 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.8823529411764706) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 17 [2021-08-12 19:28:14,384 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:14,386 INFO L225 Difference]: With dead ends: 96 [2021-08-12 19:28:14,386 INFO L226 Difference]: Without dead ends: 80 [2021-08-12 19:28:14,387 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 9 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 116 ImplicationChecksByTransitivity, 454.3ms TimeCoverageRelationStatistics Valid=170, Invalid=532, Unknown=0, NotChecked=0, Total=702 [2021-08-12 19:28:14,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2021-08-12 19:28:14,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 52. [2021-08-12 19:28:14,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 51 states have (on average 1.8235294117647058) internal successors, (93), 51 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:14,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 93 transitions. [2021-08-12 19:28:14,399 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 93 transitions. Word has length 17 [2021-08-12 19:28:14,399 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:14,400 INFO L482 AbstractCegarLoop]: Abstraction has 52 states and 93 transitions. [2021-08-12 19:28:14,400 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 17 states, 17 states have (on average 1.8823529411764706) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:14,401 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 93 transitions. [2021-08-12 19:28:14,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2021-08-12 19:28:14,403 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:14,403 INFO L550 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:14,626 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:14,627 INFO L430 AbstractCegarLoop]: === Iteration 6 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:14,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:14,627 INFO L82 PathProgramCache]: Analyzing trace with hash -886863873, now seen corresponding path program 4 times [2021-08-12 19:28:14,627 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:14,627 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [495131166] [2021-08-12 19:28:14,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:14,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:14,744 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:14,747 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:14,747 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [495131166] [2021-08-12 19:28:14,747 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [495131166] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:14,747 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1659891184] [2021-08-12 19:28:14,747 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-08-12 19:28:14,783 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-08-12 19:28:14,783 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:14,784 INFO L263 TraceCheckSpWp]: Trace formula consists of 33 conjuncts, 13 conjunts are in the unsatisfiable core [2021-08-12 19:28:14,785 INFO L286 TraceCheckSpWp]: Computing forward predicates... Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:14,974 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:14,975 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1659891184] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:14,976 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:14,976 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 16 [2021-08-12 19:28:14,976 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1101285086] [2021-08-12 19:28:14,977 INFO L462 AbstractCegarLoop]: Interpolant automaton has 17 states [2021-08-12 19:28:14,977 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:14,977 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2021-08-12 19:28:14,977 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=213, Unknown=0, NotChecked=0, Total=272 [2021-08-12 19:28:14,978 INFO L87 Difference]: Start difference. First operand 52 states and 93 transitions. Second operand has 17 states, 17 states have (on average 1.8823529411764706) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:15,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:15,284 INFO L93 Difference]: Finished difference Result 89 states and 150 transitions. [2021-08-12 19:28:15,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-08-12 19:28:15,285 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.8823529411764706) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 17 [2021-08-12 19:28:15,285 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:15,286 INFO L225 Difference]: With dead ends: 89 [2021-08-12 19:28:15,286 INFO L226 Difference]: Without dead ends: 49 [2021-08-12 19:28:15,288 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 9 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 112 ImplicationChecksByTransitivity, 391.0ms TimeCoverageRelationStatistics Valid=175, Invalid=527, Unknown=0, NotChecked=0, Total=702 [2021-08-12 19:28:15,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2021-08-12 19:28:15,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 44. [2021-08-12 19:28:15,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 43 states have (on average 1.7906976744186047) internal successors, (77), 43 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:15,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 77 transitions. [2021-08-12 19:28:15,292 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 77 transitions. Word has length 17 [2021-08-12 19:28:15,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:15,292 INFO L482 AbstractCegarLoop]: Abstraction has 44 states and 77 transitions. [2021-08-12 19:28:15,292 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 17 states, 17 states have (on average 1.8823529411764706) internal successors, (32), 16 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:15,292 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 77 transitions. [2021-08-12 19:28:15,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2021-08-12 19:28:15,293 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:15,293 INFO L550 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:15,508 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,5 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:15,509 INFO L430 AbstractCegarLoop]: === Iteration 7 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:15,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:15,509 INFO L82 PathProgramCache]: Analyzing trace with hash -980318313, now seen corresponding path program 1 times [2021-08-12 19:28:15,509 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:15,509 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [337353915] [2021-08-12 19:28:15,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:15,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:15,639 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:15,639 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:15,639 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [337353915] [2021-08-12 19:28:15,639 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [337353915] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:15,639 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [266331137] [2021-08-12 19:28:15,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:15,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:15,666 INFO L263 TraceCheckSpWp]: Trace formula consists of 39 conjuncts, 17 conjunts are in the unsatisfiable core [2021-08-12 19:28:15,666 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:15,902 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:15,902 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [266331137] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:15,903 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:15,903 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 18 [2021-08-12 19:28:15,903 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1691251898] [2021-08-12 19:28:15,903 INFO L462 AbstractCegarLoop]: Interpolant automaton has 19 states [2021-08-12 19:28:15,903 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:15,904 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-08-12 19:28:15,904 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2021-08-12 19:28:15,904 INFO L87 Difference]: Start difference. First operand 44 states and 77 transitions. Second operand has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:16,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:16,259 INFO L93 Difference]: Finished difference Result 128 states and 225 transitions. [2021-08-12 19:28:16,259 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-08-12 19:28:16,259 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 19 [2021-08-12 19:28:16,260 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:16,260 INFO L225 Difference]: With dead ends: 128 [2021-08-12 19:28:16,260 INFO L226 Difference]: Without dead ends: 76 [2021-08-12 19:28:16,261 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 10 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 122 ImplicationChecksByTransitivity, 432.6ms TimeCoverageRelationStatistics Valid=141, Invalid=615, Unknown=0, NotChecked=0, Total=756 [2021-08-12 19:28:16,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2021-08-12 19:28:16,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 54. [2021-08-12 19:28:16,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54 states, 53 states have (on average 1.849056603773585) internal successors, (98), 53 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:16,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 98 transitions. [2021-08-12 19:28:16,265 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 98 transitions. Word has length 19 [2021-08-12 19:28:16,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:16,265 INFO L482 AbstractCegarLoop]: Abstraction has 54 states and 98 transitions. [2021-08-12 19:28:16,266 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:16,266 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 98 transitions. [2021-08-12 19:28:16,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2021-08-12 19:28:16,266 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:16,266 INFO L550 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:16,480 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable6 [2021-08-12 19:28:16,481 INFO L430 AbstractCegarLoop]: === Iteration 8 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:16,481 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:16,481 INFO L82 PathProgramCache]: Analyzing trace with hash 2049721123, now seen corresponding path program 2 times [2021-08-12 19:28:16,481 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:16,481 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1330516619] [2021-08-12 19:28:16,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:16,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:16,580 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:16,580 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:16,580 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1330516619] [2021-08-12 19:28:16,580 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1330516619] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:16,580 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2134004221] [2021-08-12 19:28:16,580 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-08-12 19:28:16,613 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-08-12 19:28:16,613 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:16,614 INFO L263 TraceCheckSpWp]: Trace formula consists of 39 conjuncts, 16 conjunts are in the unsatisfiable core Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:16,615 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:16,833 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:16,833 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2134004221] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:16,833 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:16,833 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 18 [2021-08-12 19:28:16,833 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1815915439] [2021-08-12 19:28:16,834 INFO L462 AbstractCegarLoop]: Interpolant automaton has 19 states [2021-08-12 19:28:16,834 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:16,834 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-08-12 19:28:16,834 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2021-08-12 19:28:16,834 INFO L87 Difference]: Start difference. First operand 54 states and 98 transitions. Second operand has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:17,212 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:17,212 INFO L93 Difference]: Finished difference Result 122 states and 205 transitions. [2021-08-12 19:28:17,213 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-08-12 19:28:17,213 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 19 [2021-08-12 19:28:17,213 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:17,214 INFO L225 Difference]: With dead ends: 122 [2021-08-12 19:28:17,214 INFO L226 Difference]: Without dead ends: 94 [2021-08-12 19:28:17,215 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 10 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 149 ImplicationChecksByTransitivity, 452.8ms TimeCoverageRelationStatistics Valid=175, Invalid=695, Unknown=0, NotChecked=0, Total=870 [2021-08-12 19:28:17,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2021-08-12 19:28:17,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 56. [2021-08-12 19:28:17,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 55 states have (on average 1.8363636363636364) internal successors, (101), 55 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:17,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 101 transitions. [2021-08-12 19:28:17,219 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 101 transitions. Word has length 19 [2021-08-12 19:28:17,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:17,219 INFO L482 AbstractCegarLoop]: Abstraction has 56 states and 101 transitions. [2021-08-12 19:28:17,220 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:17,220 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 101 transitions. [2021-08-12 19:28:17,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2021-08-12 19:28:17,220 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:17,220 INFO L550 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:17,421 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,7 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:17,421 INFO L430 AbstractCegarLoop]: === Iteration 9 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:17,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:17,422 INFO L82 PathProgramCache]: Analyzing trace with hash -1109060901, now seen corresponding path program 3 times [2021-08-12 19:28:17,422 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:17,422 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [120617573] [2021-08-12 19:28:17,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:17,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:17,522 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:17,522 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:17,522 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [120617573] [2021-08-12 19:28:17,522 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [120617573] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:17,522 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1785982185] [2021-08-12 19:28:17,522 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:17,553 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2021-08-12 19:28:17,554 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:17,554 INFO L263 TraceCheckSpWp]: Trace formula consists of 39 conjuncts, 17 conjunts are in the unsatisfiable core [2021-08-12 19:28:17,555 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:17,784 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:17,785 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1785982185] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:17,785 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:17,785 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 18 [2021-08-12 19:28:17,785 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527165904] [2021-08-12 19:28:17,785 INFO L462 AbstractCegarLoop]: Interpolant automaton has 19 states [2021-08-12 19:28:17,785 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:17,786 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-08-12 19:28:17,786 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=278, Unknown=0, NotChecked=0, Total=342 [2021-08-12 19:28:17,786 INFO L87 Difference]: Start difference. First operand 56 states and 101 transitions. Second operand has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:18,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:18,240 INFO L93 Difference]: Finished difference Result 158 states and 274 transitions. [2021-08-12 19:28:18,240 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2021-08-12 19:28:18,240 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 19 [2021-08-12 19:28:18,240 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:18,241 INFO L225 Difference]: With dead ends: 158 [2021-08-12 19:28:18,241 INFO L226 Difference]: Without dead ends: 110 [2021-08-12 19:28:18,242 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 10 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 191 ImplicationChecksByTransitivity, 503.1ms TimeCoverageRelationStatistics Valid=200, Invalid=792, Unknown=0, NotChecked=0, Total=992 [2021-08-12 19:28:18,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2021-08-12 19:28:18,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 65. [2021-08-12 19:28:18,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 64 states have (on average 1.875) internal successors, (120), 64 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:18,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 120 transitions. [2021-08-12 19:28:18,263 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 120 transitions. Word has length 19 [2021-08-12 19:28:18,263 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:18,263 INFO L482 AbstractCegarLoop]: Abstraction has 65 states and 120 transitions. [2021-08-12 19:28:18,263 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:18,263 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 120 transitions. [2021-08-12 19:28:18,264 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2021-08-12 19:28:18,264 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:18,264 INFO L550 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:18,477 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,8 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:18,477 INFO L430 AbstractCegarLoop]: === Iteration 10 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:18,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:18,477 INFO L82 PathProgramCache]: Analyzing trace with hash -458991931, now seen corresponding path program 4 times [2021-08-12 19:28:18,477 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:18,477 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [225833396] [2021-08-12 19:28:18,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:18,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:18,580 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:18,581 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:18,581 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [225833396] [2021-08-12 19:28:18,581 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [225833396] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:18,581 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [274638746] [2021-08-12 19:28:18,581 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:18,601 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-08-12 19:28:18,602 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:18,602 INFO L263 TraceCheckSpWp]: Trace formula consists of 39 conjuncts, 17 conjunts are in the unsatisfiable core [2021-08-12 19:28:18,603 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:18,815 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:18,816 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [274638746] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:18,816 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:18,816 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 18 [2021-08-12 19:28:18,816 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [297075797] [2021-08-12 19:28:18,816 INFO L462 AbstractCegarLoop]: Interpolant automaton has 19 states [2021-08-12 19:28:18,817 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:18,817 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-08-12 19:28:18,817 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=278, Unknown=0, NotChecked=0, Total=342 [2021-08-12 19:28:18,817 INFO L87 Difference]: Start difference. First operand 65 states and 120 transitions. Second operand has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:19,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:19,207 INFO L93 Difference]: Finished difference Result 108 states and 187 transitions. [2021-08-12 19:28:19,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-08-12 19:28:19,208 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 19 [2021-08-12 19:28:19,208 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:19,209 INFO L225 Difference]: With dead ends: 108 [2021-08-12 19:28:19,209 INFO L226 Difference]: Without dead ends: 92 [2021-08-12 19:28:19,209 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 10 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 174 ImplicationChecksByTransitivity, 450.6ms TimeCoverageRelationStatistics Valid=193, Invalid=737, Unknown=0, NotChecked=0, Total=930 [2021-08-12 19:28:19,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states. [2021-08-12 19:28:19,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 67. [2021-08-12 19:28:19,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 66 states have (on average 1.8636363636363635) internal successors, (123), 66 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:19,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 123 transitions. [2021-08-12 19:28:19,214 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 123 transitions. Word has length 19 [2021-08-12 19:28:19,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:19,214 INFO L482 AbstractCegarLoop]: Abstraction has 67 states and 123 transitions. [2021-08-12 19:28:19,214 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:19,214 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 123 transitions. [2021-08-12 19:28:19,215 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2021-08-12 19:28:19,215 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:19,215 INFO L550 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:19,428 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2021-08-12 19:28:19,429 INFO L430 AbstractCegarLoop]: === Iteration 11 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:19,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:19,429 INFO L82 PathProgramCache]: Analyzing trace with hash -2036952865, now seen corresponding path program 5 times [2021-08-12 19:28:19,429 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:19,429 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052246194] [2021-08-12 19:28:19,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:19,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:19,524 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:19,524 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:19,524 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052246194] [2021-08-12 19:28:19,524 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2052246194] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:19,524 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [285810434] [2021-08-12 19:28:19,525 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:19,545 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 3 check-sat command(s) [2021-08-12 19:28:19,546 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:19,546 INFO L263 TraceCheckSpWp]: Trace formula consists of 39 conjuncts, 17 conjunts are in the unsatisfiable core [2021-08-12 19:28:19,547 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:19,726 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:19,726 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [285810434] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:19,726 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:19,726 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 18 [2021-08-12 19:28:19,726 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1263997082] [2021-08-12 19:28:19,727 INFO L462 AbstractCegarLoop]: Interpolant automaton has 19 states [2021-08-12 19:28:19,727 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:19,727 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-08-12 19:28:19,727 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=277, Unknown=0, NotChecked=0, Total=342 [2021-08-12 19:28:19,727 INFO L87 Difference]: Start difference. First operand 67 states and 123 transitions. Second operand has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:19,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:19,923 INFO L93 Difference]: Finished difference Result 97 states and 166 transitions. [2021-08-12 19:28:19,923 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2021-08-12 19:28:19,923 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 19 [2021-08-12 19:28:19,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:19,924 INFO L225 Difference]: With dead ends: 97 [2021-08-12 19:28:19,924 INFO L226 Difference]: Without dead ends: 82 [2021-08-12 19:28:19,924 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 10 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 65 ImplicationChecksByTransitivity, 281.0ms TimeCoverageRelationStatistics Valid=94, Invalid=412, Unknown=0, NotChecked=0, Total=506 [2021-08-12 19:28:19,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2021-08-12 19:28:19,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 64. [2021-08-12 19:28:19,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 63 states have (on average 1.8571428571428572) internal successors, (117), 63 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:19,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 117 transitions. [2021-08-12 19:28:19,928 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 117 transitions. Word has length 19 [2021-08-12 19:28:19,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:19,928 INFO L482 AbstractCegarLoop]: Abstraction has 64 states and 117 transitions. [2021-08-12 19:28:19,929 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:19,929 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 117 transitions. [2021-08-12 19:28:19,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2021-08-12 19:28:19,929 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:19,929 INFO L550 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:20,144 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10,10 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:20,145 INFO L430 AbstractCegarLoop]: === Iteration 12 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:20,145 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:20,145 INFO L82 PathProgramCache]: Analyzing trace with hash -900767593, now seen corresponding path program 6 times [2021-08-12 19:28:20,145 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:20,145 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [400298929] [2021-08-12 19:28:20,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:20,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:20,264 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:20,264 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:20,264 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [400298929] [2021-08-12 19:28:20,264 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [400298929] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:20,264 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [247048105] [2021-08-12 19:28:20,264 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:20,286 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 3 check-sat command(s) [2021-08-12 19:28:20,287 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:20,287 INFO L263 TraceCheckSpWp]: Trace formula consists of 39 conjuncts, 16 conjunts are in the unsatisfiable core [2021-08-12 19:28:20,288 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:20,485 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:20,485 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [247048105] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:20,485 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:20,485 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 18 [2021-08-12 19:28:20,486 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2061436322] [2021-08-12 19:28:20,486 INFO L462 AbstractCegarLoop]: Interpolant automaton has 19 states [2021-08-12 19:28:20,486 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:20,486 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-08-12 19:28:20,487 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=273, Unknown=0, NotChecked=0, Total=342 [2021-08-12 19:28:20,487 INFO L87 Difference]: Start difference. First operand 64 states and 117 transitions. Second operand has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:20,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:20,631 INFO L93 Difference]: Finished difference Result 113 states and 199 transitions. [2021-08-12 19:28:20,631 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-08-12 19:28:20,631 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 19 [2021-08-12 19:28:20,631 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:20,632 INFO L225 Difference]: With dead ends: 113 [2021-08-12 19:28:20,632 INFO L226 Difference]: Without dead ends: 76 [2021-08-12 19:28:20,632 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 10 SyntacticMatches, 1 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 55 ImplicationChecksByTransitivity, 253.7ms TimeCoverageRelationStatistics Valid=86, Invalid=334, Unknown=0, NotChecked=0, Total=420 [2021-08-12 19:28:20,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2021-08-12 19:28:20,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 59. [2021-08-12 19:28:20,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 58 states have (on average 1.8275862068965518) internal successors, (106), 58 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:20,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 106 transitions. [2021-08-12 19:28:20,636 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 106 transitions. Word has length 19 [2021-08-12 19:28:20,636 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:20,636 INFO L482 AbstractCegarLoop]: Abstraction has 59 states and 106 transitions. [2021-08-12 19:28:20,636 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:20,636 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 106 transitions. [2021-08-12 19:28:20,636 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2021-08-12 19:28:20,636 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:20,637 INFO L550 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:20,844 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11,11 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:20,845 INFO L430 AbstractCegarLoop]: === Iteration 13 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:20,845 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:20,845 INFO L82 PathProgramCache]: Analyzing trace with hash -250698623, now seen corresponding path program 7 times [2021-08-12 19:28:20,845 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:20,846 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1470531985] [2021-08-12 19:28:20,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:20,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:20,951 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:20,952 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:20,952 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1470531985] [2021-08-12 19:28:20,952 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1470531985] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:20,952 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [261366373] [2021-08-12 19:28:20,952 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:20,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:20,972 INFO L263 TraceCheckSpWp]: Trace formula consists of 39 conjuncts, 17 conjunts are in the unsatisfiable core [2021-08-12 19:28:20,972 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:21,197 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:21,197 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [261366373] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:21,197 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:21,197 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 18 [2021-08-12 19:28:21,197 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190465749] [2021-08-12 19:28:21,198 INFO L462 AbstractCegarLoop]: Interpolant automaton has 19 states [2021-08-12 19:28:21,198 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:21,198 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-08-12 19:28:21,198 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=271, Unknown=0, NotChecked=0, Total=342 [2021-08-12 19:28:21,198 INFO L87 Difference]: Start difference. First operand 59 states and 106 transitions. Second operand has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:21,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:21,378 INFO L93 Difference]: Finished difference Result 76 states and 131 transitions. [2021-08-12 19:28:21,379 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-08-12 19:28:21,379 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 19 [2021-08-12 19:28:21,379 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:21,380 INFO L225 Difference]: With dead ends: 76 [2021-08-12 19:28:21,380 INFO L226 Difference]: Without dead ends: 67 [2021-08-12 19:28:21,380 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 10 SyntacticMatches, 1 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 292.2ms TimeCoverageRelationStatistics Valid=88, Invalid=332, Unknown=0, NotChecked=0, Total=420 [2021-08-12 19:28:21,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2021-08-12 19:28:21,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 56. [2021-08-12 19:28:21,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 55 states have (on average 1.8181818181818181) internal successors, (100), 55 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:21,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 100 transitions. [2021-08-12 19:28:21,383 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 100 transitions. Word has length 19 [2021-08-12 19:28:21,384 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:21,384 INFO L482 AbstractCegarLoop]: Abstraction has 56 states and 100 transitions. [2021-08-12 19:28:21,384 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 19 states, 19 states have (on average 1.894736842105263) internal successors, (36), 18 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:21,384 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 100 transitions. [2021-08-12 19:28:21,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2021-08-12 19:28:21,384 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:21,384 INFO L550 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:21,608 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable12 [2021-08-12 19:28:21,609 INFO L430 AbstractCegarLoop]: === Iteration 14 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:21,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:21,609 INFO L82 PathProgramCache]: Analyzing trace with hash 798154329, now seen corresponding path program 8 times [2021-08-12 19:28:21,609 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:21,609 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2064292148] [2021-08-12 19:28:21,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:21,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:21,698 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-08-12 19:28:21,698 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:21,698 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2064292148] [2021-08-12 19:28:21,698 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2064292148] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:21,699 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1782631497] [2021-08-12 19:28:21,699 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:21,726 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-08-12 19:28:21,726 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:21,727 INFO L263 TraceCheckSpWp]: Trace formula consists of 44 conjuncts, 21 conjunts are in the unsatisfiable core [2021-08-12 19:28:21,727 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:21,942 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:21,942 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1782631497] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:21,942 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:21,942 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11] total 19 [2021-08-12 19:28:21,942 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439647872] [2021-08-12 19:28:21,943 INFO L462 AbstractCegarLoop]: Interpolant automaton has 20 states [2021-08-12 19:28:21,943 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:21,943 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-08-12 19:28:21,943 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=318, Unknown=0, NotChecked=0, Total=380 [2021-08-12 19:28:21,943 INFO L87 Difference]: Start difference. First operand 56 states and 100 transitions. Second operand has 20 states, 20 states have (on average 2.0) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:22,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:22,477 INFO L93 Difference]: Finished difference Result 109 states and 193 transitions. [2021-08-12 19:28:22,477 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-08-12 19:28:22,478 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 2.0) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2021-08-12 19:28:22,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:22,478 INFO L225 Difference]: With dead ends: 109 [2021-08-12 19:28:22,479 INFO L226 Difference]: Without dead ends: 65 [2021-08-12 19:28:22,479 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 12 SyntacticMatches, 1 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 368 ImplicationChecksByTransitivity, 587.7ms TimeCoverageRelationStatistics Valid=271, Invalid=1289, Unknown=0, NotChecked=0, Total=1560 [2021-08-12 19:28:22,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2021-08-12 19:28:22,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 51. [2021-08-12 19:28:22,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 50 states have (on average 1.74) internal successors, (87), 50 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:22,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 87 transitions. [2021-08-12 19:28:22,483 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 87 transitions. Word has length 21 [2021-08-12 19:28:22,483 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:22,483 INFO L482 AbstractCegarLoop]: Abstraction has 51 states and 87 transitions. [2021-08-12 19:28:22,483 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 20 states, 20 states have (on average 2.0) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:22,483 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 87 transitions. [2021-08-12 19:28:22,483 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2021-08-12 19:28:22,484 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:22,484 INFO L550 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:22,692 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable13 [2021-08-12 19:28:22,693 INFO L430 AbstractCegarLoop]: === Iteration 15 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:22,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:22,693 INFO L82 PathProgramCache]: Analyzing trace with hash -466773531, now seen corresponding path program 9 times [2021-08-12 19:28:22,693 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:22,693 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [554549485] [2021-08-12 19:28:22,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:22,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:22,790 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-08-12 19:28:22,790 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:22,790 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [554549485] [2021-08-12 19:28:22,790 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [554549485] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:22,790 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [737677284] [2021-08-12 19:28:22,791 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:22,811 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2021-08-12 19:28:22,811 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:22,811 INFO L263 TraceCheckSpWp]: Trace formula consists of 44 conjuncts, 21 conjunts are in the unsatisfiable core [2021-08-12 19:28:22,812 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:23,027 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:23,028 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [737677284] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:23,028 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:23,028 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11] total 19 [2021-08-12 19:28:23,028 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [389497530] [2021-08-12 19:28:23,028 INFO L462 AbstractCegarLoop]: Interpolant automaton has 20 states [2021-08-12 19:28:23,028 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:23,029 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-08-12 19:28:23,029 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=318, Unknown=0, NotChecked=0, Total=380 [2021-08-12 19:28:23,029 INFO L87 Difference]: Start difference. First operand 51 states and 87 transitions. Second operand has 20 states, 20 states have (on average 2.0) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:23,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:23,685 INFO L93 Difference]: Finished difference Result 87 states and 144 transitions. [2021-08-12 19:28:23,685 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2021-08-12 19:28:23,686 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 2.0) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2021-08-12 19:28:23,686 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:23,686 INFO L225 Difference]: With dead ends: 87 [2021-08-12 19:28:23,686 INFO L226 Difference]: Without dead ends: 56 [2021-08-12 19:28:23,687 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 12 SyntacticMatches, 1 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 552 ImplicationChecksByTransitivity, 718.8ms TimeCoverageRelationStatistics Valid=359, Invalid=1711, Unknown=0, NotChecked=0, Total=2070 [2021-08-12 19:28:23,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2021-08-12 19:28:23,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 48. [2021-08-12 19:28:23,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48 states, 47 states have (on average 1.7234042553191489) internal successors, (81), 47 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:23,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 81 transitions. [2021-08-12 19:28:23,690 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 81 transitions. Word has length 21 [2021-08-12 19:28:23,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:23,691 INFO L482 AbstractCegarLoop]: Abstraction has 48 states and 81 transitions. [2021-08-12 19:28:23,691 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 20 states, 20 states have (on average 2.0) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:23,691 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 81 transitions. [2021-08-12 19:28:23,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2021-08-12 19:28:23,691 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:23,691 INFO L550 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:23,896 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable14 [2021-08-12 19:28:23,897 INFO L430 AbstractCegarLoop]: === Iteration 16 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:23,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:23,897 INFO L82 PathProgramCache]: Analyzing trace with hash 669411741, now seen corresponding path program 10 times [2021-08-12 19:28:23,897 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:23,897 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [107699201] [2021-08-12 19:28:23,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:23,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:23,990 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-08-12 19:28:23,990 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:23,990 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [107699201] [2021-08-12 19:28:23,990 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [107699201] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:23,990 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [244532910] [2021-08-12 19:28:23,990 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:24,010 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-08-12 19:28:24,010 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:24,010 INFO L263 TraceCheckSpWp]: Trace formula consists of 44 conjuncts, 21 conjunts are in the unsatisfiable core [2021-08-12 19:28:24,011 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:24,202 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:24,203 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [244532910] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:24,203 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:24,203 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11] total 19 [2021-08-12 19:28:24,203 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [235247760] [2021-08-12 19:28:24,203 INFO L462 AbstractCegarLoop]: Interpolant automaton has 20 states [2021-08-12 19:28:24,203 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:24,204 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-08-12 19:28:24,204 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=314, Unknown=0, NotChecked=0, Total=380 [2021-08-12 19:28:24,204 INFO L87 Difference]: Start difference. First operand 48 states and 81 transitions. Second operand has 20 states, 20 states have (on average 2.0) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:25,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:25,106 INFO L93 Difference]: Finished difference Result 92 states and 150 transitions. [2021-08-12 19:28:25,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2021-08-12 19:28:25,106 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 2.0) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2021-08-12 19:28:25,107 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:25,107 INFO L225 Difference]: With dead ends: 92 [2021-08-12 19:28:25,107 INFO L226 Difference]: Without dead ends: 70 [2021-08-12 19:28:25,108 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 12 SyntacticMatches, 1 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 694 ImplicationChecksByTransitivity, 895.9ms TimeCoverageRelationStatistics Valid=441, Invalid=2109, Unknown=0, NotChecked=0, Total=2550 [2021-08-12 19:28:25,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states. [2021-08-12 19:28:25,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 45. [2021-08-12 19:28:25,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 44 states have (on average 1.7045454545454546) internal successors, (75), 44 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:25,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 75 transitions. [2021-08-12 19:28:25,111 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 75 transitions. Word has length 21 [2021-08-12 19:28:25,111 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:25,111 INFO L482 AbstractCegarLoop]: Abstraction has 45 states and 75 transitions. [2021-08-12 19:28:25,111 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 20 states, 20 states have (on average 2.0) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:25,111 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 75 transitions. [2021-08-12 19:28:25,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2021-08-12 19:28:25,112 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:25,112 INFO L550 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:25,320 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15,15 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:25,321 INFO L430 AbstractCegarLoop]: === Iteration 17 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:25,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:25,321 INFO L82 PathProgramCache]: Analyzing trace with hash 1319480711, now seen corresponding path program 11 times [2021-08-12 19:28:25,321 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:25,321 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1959476812] [2021-08-12 19:28:25,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:25,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:25,420 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-08-12 19:28:25,421 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:25,421 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1959476812] [2021-08-12 19:28:25,421 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1959476812] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:25,421 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2054590330] [2021-08-12 19:28:25,421 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:25,441 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 3 check-sat command(s) [2021-08-12 19:28:25,442 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:25,442 INFO L263 TraceCheckSpWp]: Trace formula consists of 44 conjuncts, 21 conjunts are in the unsatisfiable core [2021-08-12 19:28:25,443 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:25,667 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:25,667 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2054590330] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:25,667 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:25,667 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11] total 19 [2021-08-12 19:28:25,668 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1996128675] [2021-08-12 19:28:25,668 INFO L462 AbstractCegarLoop]: Interpolant automaton has 20 states [2021-08-12 19:28:25,668 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:25,668 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-08-12 19:28:25,668 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=314, Unknown=0, NotChecked=0, Total=380 [2021-08-12 19:28:25,669 INFO L87 Difference]: Start difference. First operand 45 states and 75 transitions. Second operand has 20 states, 20 states have (on average 2.0) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:26,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:26,604 INFO L93 Difference]: Finished difference Result 81 states and 136 transitions. [2021-08-12 19:28:26,605 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2021-08-12 19:28:26,605 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 2.0) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2021-08-12 19:28:26,605 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:26,605 INFO L225 Difference]: With dead ends: 81 [2021-08-12 19:28:26,605 INFO L226 Difference]: Without dead ends: 65 [2021-08-12 19:28:26,606 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 12 SyntacticMatches, 1 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 690 ImplicationChecksByTransitivity, 944.0ms TimeCoverageRelationStatistics Valid=441, Invalid=2109, Unknown=0, NotChecked=0, Total=2550 [2021-08-12 19:28:26,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2021-08-12 19:28:26,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 45. [2021-08-12 19:28:26,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 44 states have (on average 1.7045454545454546) internal successors, (75), 44 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:26,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 75 transitions. [2021-08-12 19:28:26,609 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 75 transitions. Word has length 21 [2021-08-12 19:28:26,609 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:26,609 INFO L482 AbstractCegarLoop]: Abstraction has 45 states and 75 transitions. [2021-08-12 19:28:26,609 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 20 states, 20 states have (on average 2.0) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:26,609 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 75 transitions. [2021-08-12 19:28:26,609 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2021-08-12 19:28:26,609 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:26,609 INFO L550 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:26,810 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable16 [2021-08-12 19:28:26,810 INFO L430 AbstractCegarLoop]: === Iteration 18 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:26,810 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:26,810 INFO L82 PathProgramCache]: Analyzing trace with hash -1793458263, now seen corresponding path program 12 times [2021-08-12 19:28:26,810 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:26,810 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [104263212] [2021-08-12 19:28:26,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:26,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:26,934 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:26,934 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:26,935 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [104263212] [2021-08-12 19:28:26,935 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [104263212] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:26,935 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1269143701] [2021-08-12 19:28:26,935 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:26,963 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) [2021-08-12 19:28:26,963 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:26,963 INFO L263 TraceCheckSpWp]: Trace formula consists of 44 conjuncts, 20 conjunts are in the unsatisfiable core [2021-08-12 19:28:26,964 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:27,184 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:27,185 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1269143701] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:27,185 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:27,185 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 20 [2021-08-12 19:28:27,185 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [563987721] [2021-08-12 19:28:27,185 INFO L462 AbstractCegarLoop]: Interpolant automaton has 21 states [2021-08-12 19:28:27,185 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:27,186 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-08-12 19:28:27,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=355, Unknown=0, NotChecked=0, Total=420 [2021-08-12 19:28:27,186 INFO L87 Difference]: Start difference. First operand 45 states and 75 transitions. Second operand has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:27,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:27,627 INFO L93 Difference]: Finished difference Result 126 states and 210 transitions. [2021-08-12 19:28:27,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-08-12 19:28:27,628 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2021-08-12 19:28:27,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:27,629 INFO L225 Difference]: With dead ends: 126 [2021-08-12 19:28:27,629 INFO L226 Difference]: Without dead ends: 93 [2021-08-12 19:28:27,629 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 11 SyntacticMatches, 1 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 295 ImplicationChecksByTransitivity, 550.5ms TimeCoverageRelationStatistics Valid=224, Invalid=1108, Unknown=0, NotChecked=0, Total=1332 [2021-08-12 19:28:27,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2021-08-12 19:28:27,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 49. [2021-08-12 19:28:27,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 48 states have (on average 1.8125) internal successors, (87), 48 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:27,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 87 transitions. [2021-08-12 19:28:27,633 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 87 transitions. Word has length 21 [2021-08-12 19:28:27,634 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:27,634 INFO L482 AbstractCegarLoop]: Abstraction has 49 states and 87 transitions. [2021-08-12 19:28:27,634 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:27,634 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 87 transitions. [2021-08-12 19:28:27,634 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2021-08-12 19:28:27,634 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:27,634 INFO L550 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:27,840 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable17 [2021-08-12 19:28:27,841 INFO L430 AbstractCegarLoop]: === Iteration 19 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:27,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:27,841 INFO L82 PathProgramCache]: Analyzing trace with hash 1615710753, now seen corresponding path program 13 times [2021-08-12 19:28:27,841 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:27,841 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967867776] [2021-08-12 19:28:27,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:27,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:27,939 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:27,939 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:27,940 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967867776] [2021-08-12 19:28:27,940 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967867776] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:27,940 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [737595307] [2021-08-12 19:28:27,940 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:27,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:27,963 INFO L263 TraceCheckSpWp]: Trace formula consists of 44 conjuncts, 21 conjunts are in the unsatisfiable core [2021-08-12 19:28:27,964 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:28,220 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:28,221 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [737595307] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:28,221 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:28,221 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 20 [2021-08-12 19:28:28,221 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1585076936] [2021-08-12 19:28:28,222 INFO L462 AbstractCegarLoop]: Interpolant automaton has 21 states [2021-08-12 19:28:28,222 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:28,222 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-08-12 19:28:28,222 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=353, Unknown=0, NotChecked=0, Total=420 [2021-08-12 19:28:28,223 INFO L87 Difference]: Start difference. First operand 49 states and 87 transitions. Second operand has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:28,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:28,673 INFO L93 Difference]: Finished difference Result 116 states and 192 transitions. [2021-08-12 19:28:28,673 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-08-12 19:28:28,673 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2021-08-12 19:28:28,673 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:28,674 INFO L225 Difference]: With dead ends: 116 [2021-08-12 19:28:28,674 INFO L226 Difference]: Without dead ends: 100 [2021-08-12 19:28:28,675 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 11 SyntacticMatches, 1 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 294 ImplicationChecksByTransitivity, 537.8ms TimeCoverageRelationStatistics Valid=224, Invalid=1108, Unknown=0, NotChecked=0, Total=1332 [2021-08-12 19:28:28,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2021-08-12 19:28:28,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 50. [2021-08-12 19:28:28,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 49 states have (on average 1.816326530612245) internal successors, (89), 49 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:28,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 89 transitions. [2021-08-12 19:28:28,679 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 89 transitions. Word has length 21 [2021-08-12 19:28:28,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:28,679 INFO L482 AbstractCegarLoop]: Abstraction has 50 states and 89 transitions. [2021-08-12 19:28:28,679 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:28,679 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 89 transitions. [2021-08-12 19:28:28,679 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2021-08-12 19:28:28,679 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:28,679 INFO L550 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:28,901 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18,18 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:28,902 INFO L430 AbstractCegarLoop]: === Iteration 20 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:28,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:28,902 INFO L82 PathProgramCache]: Analyzing trace with hash 603018221, now seen corresponding path program 14 times [2021-08-12 19:28:28,902 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:28,902 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [930596408] [2021-08-12 19:28:28,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:28,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:28,993 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:28,993 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:28,993 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [930596408] [2021-08-12 19:28:28,993 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [930596408] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:28,993 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1729784124] [2021-08-12 19:28:28,993 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:29,013 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-08-12 19:28:29,013 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:29,014 INFO L263 TraceCheckSpWp]: Trace formula consists of 44 conjuncts, 20 conjunts are in the unsatisfiable core [2021-08-12 19:28:29,014 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:29,253 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:29,253 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1729784124] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:29,253 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:29,253 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 20 [2021-08-12 19:28:29,253 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1982317489] [2021-08-12 19:28:29,253 INFO L462 AbstractCegarLoop]: Interpolant automaton has 21 states [2021-08-12 19:28:29,253 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:29,254 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-08-12 19:28:29,254 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=356, Unknown=0, NotChecked=0, Total=420 [2021-08-12 19:28:29,254 INFO L87 Difference]: Start difference. First operand 50 states and 89 transitions. Second operand has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:29,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:29,907 INFO L93 Difference]: Finished difference Result 184 states and 301 transitions. [2021-08-12 19:28:29,907 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2021-08-12 19:28:29,907 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2021-08-12 19:28:29,908 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:29,909 INFO L225 Difference]: With dead ends: 184 [2021-08-12 19:28:29,909 INFO L226 Difference]: Without dead ends: 161 [2021-08-12 19:28:29,909 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 11 SyntacticMatches, 1 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 524 ImplicationChecksByTransitivity, 666.4ms TimeCoverageRelationStatistics Valid=338, Invalid=1732, Unknown=0, NotChecked=0, Total=2070 [2021-08-12 19:28:29,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2021-08-12 19:28:29,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 55. [2021-08-12 19:28:29,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 54 states have (on average 1.9259259259259258) internal successors, (104), 54 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:29,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 104 transitions. [2021-08-12 19:28:29,915 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 104 transitions. Word has length 21 [2021-08-12 19:28:29,915 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:29,915 INFO L482 AbstractCegarLoop]: Abstraction has 55 states and 104 transitions. [2021-08-12 19:28:29,915 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:29,915 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 104 transitions. [2021-08-12 19:28:29,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2021-08-12 19:28:29,915 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:29,915 INFO L550 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:30,128 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19,19 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:30,129 INFO L430 AbstractCegarLoop]: === Iteration 21 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:30,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:30,129 INFO L82 PathProgramCache]: Analyzing trace with hash 67788419, now seen corresponding path program 15 times [2021-08-12 19:28:30,129 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:30,129 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [658291358] [2021-08-12 19:28:30,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:30,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:30,251 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:30,251 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:30,251 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [658291358] [2021-08-12 19:28:30,251 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [658291358] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:30,251 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [926925739] [2021-08-12 19:28:30,252 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:30,287 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2021-08-12 19:28:30,287 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:30,288 INFO L263 TraceCheckSpWp]: Trace formula consists of 44 conjuncts, 21 conjunts are in the unsatisfiable core [2021-08-12 19:28:30,288 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:30,514 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:30,515 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [926925739] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:30,515 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:30,515 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 20 [2021-08-12 19:28:30,515 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1718563406] [2021-08-12 19:28:30,516 INFO L462 AbstractCegarLoop]: Interpolant automaton has 21 states [2021-08-12 19:28:30,516 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:30,517 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-08-12 19:28:30,517 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=356, Unknown=0, NotChecked=0, Total=420 [2021-08-12 19:28:30,517 INFO L87 Difference]: Start difference. First operand 55 states and 104 transitions. Second operand has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:31,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:31,102 INFO L93 Difference]: Finished difference Result 145 states and 242 transitions. [2021-08-12 19:28:31,102 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2021-08-12 19:28:31,102 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2021-08-12 19:28:31,103 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:31,103 INFO L225 Difference]: With dead ends: 145 [2021-08-12 19:28:31,103 INFO L226 Difference]: Without dead ends: 90 [2021-08-12 19:28:31,104 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 11 SyntacticMatches, 1 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 455 ImplicationChecksByTransitivity, 646.2ms TimeCoverageRelationStatistics Valid=326, Invalid=1566, Unknown=0, NotChecked=0, Total=1892 [2021-08-12 19:28:31,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2021-08-12 19:28:31,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 47. [2021-08-12 19:28:31,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 46 states have (on average 1.8043478260869565) internal successors, (83), 46 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:31,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 83 transitions. [2021-08-12 19:28:31,108 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 83 transitions. Word has length 21 [2021-08-12 19:28:31,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:31,108 INFO L482 AbstractCegarLoop]: Abstraction has 47 states and 83 transitions. [2021-08-12 19:28:31,108 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:31,108 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 83 transitions. [2021-08-12 19:28:31,108 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2021-08-12 19:28:31,108 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:31,108 INFO L550 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:31,316 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20,20 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:31,317 INFO L430 AbstractCegarLoop]: === Iteration 22 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:31,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:31,317 INFO L82 PathProgramCache]: Analyzing trace with hash 770739301, now seen corresponding path program 16 times [2021-08-12 19:28:31,317 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:31,317 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2000935907] [2021-08-12 19:28:31,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:31,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:31,419 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:31,420 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:31,420 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2000935907] [2021-08-12 19:28:31,420 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2000935907] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:31,420 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1508007798] [2021-08-12 19:28:31,420 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:31,447 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-08-12 19:28:31,447 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:31,447 INFO L263 TraceCheckSpWp]: Trace formula consists of 44 conjuncts, 21 conjunts are in the unsatisfiable core [2021-08-12 19:28:31,451 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:31,690 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:31,690 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1508007798] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:31,690 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:31,690 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 20 [2021-08-12 19:28:31,690 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [498626223] [2021-08-12 19:28:31,690 INFO L462 AbstractCegarLoop]: Interpolant automaton has 21 states [2021-08-12 19:28:31,690 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:31,691 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-08-12 19:28:31,691 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=352, Unknown=0, NotChecked=0, Total=420 [2021-08-12 19:28:31,691 INFO L87 Difference]: Start difference. First operand 47 states and 83 transitions. Second operand has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:32,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:32,080 INFO L93 Difference]: Finished difference Result 99 states and 168 transitions. [2021-08-12 19:28:32,081 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-08-12 19:28:32,081 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2021-08-12 19:28:32,081 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:32,081 INFO L225 Difference]: With dead ends: 99 [2021-08-12 19:28:32,082 INFO L226 Difference]: Without dead ends: 83 [2021-08-12 19:28:32,082 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 11 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 252 ImplicationChecksByTransitivity, 497.2ms TimeCoverageRelationStatistics Valid=216, Invalid=974, Unknown=0, NotChecked=0, Total=1190 [2021-08-12 19:28:32,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2021-08-12 19:28:32,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 63. [2021-08-12 19:28:32,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 62 states have (on average 1.8387096774193548) internal successors, (114), 62 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:32,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 114 transitions. [2021-08-12 19:28:32,088 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 114 transitions. Word has length 21 [2021-08-12 19:28:32,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:32,088 INFO L482 AbstractCegarLoop]: Abstraction has 63 states and 114 transitions. [2021-08-12 19:28:32,088 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:32,088 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 114 transitions. [2021-08-12 19:28:32,088 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2021-08-12 19:28:32,088 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:32,088 INFO L550 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:32,292 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable21 [2021-08-12 19:28:32,296 INFO L430 AbstractCegarLoop]: === Iteration 23 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:32,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:32,296 INFO L82 PathProgramCache]: Analyzing trace with hash -241953231, now seen corresponding path program 17 times [2021-08-12 19:28:32,296 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:32,296 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720216020] [2021-08-12 19:28:32,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:32,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:32,393 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:32,393 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:32,393 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1720216020] [2021-08-12 19:28:32,393 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1720216020] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:32,393 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1778143071] [2021-08-12 19:28:32,394 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:32,418 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 3 check-sat command(s) [2021-08-12 19:28:32,418 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:32,420 INFO L263 TraceCheckSpWp]: Trace formula consists of 44 conjuncts, 20 conjunts are in the unsatisfiable core [2021-08-12 19:28:32,421 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:32,627 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:32,628 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1778143071] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:32,628 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:32,628 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 20 [2021-08-12 19:28:32,628 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562212257] [2021-08-12 19:28:32,628 INFO L462 AbstractCegarLoop]: Interpolant automaton has 21 states [2021-08-12 19:28:32,628 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:32,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-08-12 19:28:32,628 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=353, Unknown=0, NotChecked=0, Total=420 [2021-08-12 19:28:32,629 INFO L87 Difference]: Start difference. First operand 63 states and 114 transitions. Second operand has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:33,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:33,201 INFO L93 Difference]: Finished difference Result 135 states and 230 transitions. [2021-08-12 19:28:33,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2021-08-12 19:28:33,202 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2021-08-12 19:28:33,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:33,203 INFO L225 Difference]: With dead ends: 135 [2021-08-12 19:28:33,203 INFO L226 Difference]: Without dead ends: 119 [2021-08-12 19:28:33,203 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 11 SyntacticMatches, 1 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 367 ImplicationChecksByTransitivity, 569.2ms TimeCoverageRelationStatistics Valid=250, Invalid=1310, Unknown=0, NotChecked=0, Total=1560 [2021-08-12 19:28:33,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2021-08-12 19:28:33,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 67. [2021-08-12 19:28:33,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 66 states have (on average 1.9090909090909092) internal successors, (126), 66 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:33,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 126 transitions. [2021-08-12 19:28:33,208 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 126 transitions. Word has length 21 [2021-08-12 19:28:33,208 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:33,208 INFO L482 AbstractCegarLoop]: Abstraction has 67 states and 126 transitions. [2021-08-12 19:28:33,208 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:33,208 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 126 transitions. [2021-08-12 19:28:33,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2021-08-12 19:28:33,208 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:33,209 INFO L550 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:33,415 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable22 [2021-08-12 19:28:33,415 INFO L430 AbstractCegarLoop]: === Iteration 24 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:33,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:33,415 INFO L82 PathProgramCache]: Analyzing trace with hash -777183033, now seen corresponding path program 18 times [2021-08-12 19:28:33,415 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:33,415 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982675506] [2021-08-12 19:28:33,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:33,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:33,521 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:33,521 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:33,521 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1982675506] [2021-08-12 19:28:33,521 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1982675506] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:33,521 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1490271132] [2021-08-12 19:28:33,521 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:33,550 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 3 check-sat command(s) [2021-08-12 19:28:33,550 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:33,551 INFO L263 TraceCheckSpWp]: Trace formula consists of 44 conjuncts, 20 conjunts are in the unsatisfiable core [2021-08-12 19:28:33,552 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:33,794 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:33,794 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1490271132] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:33,794 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:33,794 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 20 [2021-08-12 19:28:33,794 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231676450] [2021-08-12 19:28:33,795 INFO L462 AbstractCegarLoop]: Interpolant automaton has 21 states [2021-08-12 19:28:33,795 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:33,795 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-08-12 19:28:33,795 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=354, Unknown=0, NotChecked=0, Total=420 [2021-08-12 19:28:33,796 INFO L87 Difference]: Start difference. First operand 67 states and 126 transitions. Second operand has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:34,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:34,263 INFO L93 Difference]: Finished difference Result 113 states and 196 transitions. [2021-08-12 19:28:34,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2021-08-12 19:28:34,263 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2021-08-12 19:28:34,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:34,264 INFO L225 Difference]: With dead ends: 113 [2021-08-12 19:28:34,264 INFO L226 Difference]: Without dead ends: 73 [2021-08-12 19:28:34,264 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 11 SyntacticMatches, 1 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 258 ImplicationChecksByTransitivity, 564.3ms TimeCoverageRelationStatistics Valid=205, Invalid=1055, Unknown=0, NotChecked=0, Total=1260 [2021-08-12 19:28:34,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2021-08-12 19:28:34,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 57. [2021-08-12 19:28:34,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 56 states have (on average 1.7678571428571428) internal successors, (99), 56 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:34,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 99 transitions. [2021-08-12 19:28:34,269 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 99 transitions. Word has length 21 [2021-08-12 19:28:34,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:34,270 INFO L482 AbstractCegarLoop]: Abstraction has 57 states and 99 transitions. [2021-08-12 19:28:34,270 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 21 states, 21 states have (on average 1.9047619047619047) internal successors, (40), 20 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:34,270 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 99 transitions. [2021-08-12 19:28:34,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2021-08-12 19:28:34,270 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:34,270 INFO L550 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:34,480 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23,23 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:34,481 INFO L430 AbstractCegarLoop]: === Iteration 25 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:34,481 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:34,481 INFO L82 PathProgramCache]: Analyzing trace with hash -2078233109, now seen corresponding path program 19 times [2021-08-12 19:28:34,481 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:34,481 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469989112] [2021-08-12 19:28:34,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:34,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:34,575 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2021-08-12 19:28:34,576 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:34,576 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [469989112] [2021-08-12 19:28:34,576 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [469989112] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:34,576 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [554954127] [2021-08-12 19:28:34,576 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:34,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:34,595 WARN L261 TraceCheckSpWp]: Trace formula consists of 49 conjuncts, 25 conjunts are in the unsatisfiable core [2021-08-12 19:28:34,595 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:34,838 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:34,838 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [554954127] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:34,838 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:34,838 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2021-08-12 19:28:34,839 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1393685802] [2021-08-12 19:28:34,839 INFO L462 AbstractCegarLoop]: Interpolant automaton has 21 states [2021-08-12 19:28:34,839 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:34,839 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-08-12 19:28:34,839 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=351, Unknown=0, NotChecked=0, Total=420 [2021-08-12 19:28:34,845 INFO L87 Difference]: Start difference. First operand 57 states and 99 transitions. Second operand has 21 states, 21 states have (on average 2.0) internal successors, (42), 20 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:35,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:35,477 INFO L93 Difference]: Finished difference Result 111 states and 191 transitions. [2021-08-12 19:28:35,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2021-08-12 19:28:35,478 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 21 states have (on average 2.0) internal successors, (42), 20 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 23 [2021-08-12 19:28:35,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:35,479 INFO L225 Difference]: With dead ends: 111 [2021-08-12 19:28:35,479 INFO L226 Difference]: Without dead ends: 95 [2021-08-12 19:28:35,480 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 14 SyntacticMatches, 1 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 423 ImplicationChecksByTransitivity, 643.0ms TimeCoverageRelationStatistics Valid=266, Invalid=1374, Unknown=0, NotChecked=0, Total=1640 [2021-08-12 19:28:35,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2021-08-12 19:28:35,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 61. [2021-08-12 19:28:35,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 60 states have (on average 1.7833333333333334) internal successors, (107), 60 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:35,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 107 transitions. [2021-08-12 19:28:35,487 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 107 transitions. Word has length 23 [2021-08-12 19:28:35,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:35,487 INFO L482 AbstractCegarLoop]: Abstraction has 61 states and 107 transitions. [2021-08-12 19:28:35,487 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 21 states, 21 states have (on average 2.0) internal successors, (42), 20 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:35,487 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 107 transitions. [2021-08-12 19:28:35,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2021-08-12 19:28:35,487 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:35,488 INFO L550 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:35,711 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 24 z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable24 [2021-08-12 19:28:35,711 INFO L430 AbstractCegarLoop]: === Iteration 26 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:35,711 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:35,711 INFO L82 PathProgramCache]: Analyzing trace with hash 1330935907, now seen corresponding path program 20 times [2021-08-12 19:28:35,711 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:35,711 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [670627563] [2021-08-12 19:28:35,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:35,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:35,804 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-08-12 19:28:35,804 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:35,804 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [670627563] [2021-08-12 19:28:35,804 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [670627563] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:35,804 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1322063735] [2021-08-12 19:28:35,804 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:35,825 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-08-12 19:28:35,825 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:35,825 WARN L261 TraceCheckSpWp]: Trace formula consists of 49 conjuncts, 25 conjunts are in the unsatisfiable core [2021-08-12 19:28:35,826 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:36,039 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:36,039 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1322063735] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:36,039 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:36,039 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2021-08-12 19:28:36,039 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805071438] [2021-08-12 19:28:36,040 INFO L462 AbstractCegarLoop]: Interpolant automaton has 21 states [2021-08-12 19:28:36,040 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:36,040 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-08-12 19:28:36,040 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=351, Unknown=0, NotChecked=0, Total=420 [2021-08-12 19:28:36,040 INFO L87 Difference]: Start difference. First operand 61 states and 107 transitions. Second operand has 21 states, 21 states have (on average 2.0) internal successors, (42), 20 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:36,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:36,625 INFO L93 Difference]: Finished difference Result 122 states and 213 transitions. [2021-08-12 19:28:36,625 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2021-08-12 19:28:36,625 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 21 states have (on average 2.0) internal successors, (42), 20 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 23 [2021-08-12 19:28:36,625 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:36,626 INFO L225 Difference]: With dead ends: 122 [2021-08-12 19:28:36,626 INFO L226 Difference]: Without dead ends: 106 [2021-08-12 19:28:36,627 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 14 SyntacticMatches, 1 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 420 ImplicationChecksByTransitivity, 568.7ms TimeCoverageRelationStatistics Valid=254, Invalid=1386, Unknown=0, NotChecked=0, Total=1640 [2021-08-12 19:28:36,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2021-08-12 19:28:36,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 61. [2021-08-12 19:28:36,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 60 states have (on average 1.8) internal successors, (108), 60 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:36,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 108 transitions. [2021-08-12 19:28:36,632 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 108 transitions. Word has length 23 [2021-08-12 19:28:36,632 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:36,632 INFO L482 AbstractCegarLoop]: Abstraction has 61 states and 108 transitions. [2021-08-12 19:28:36,632 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 21 states, 21 states have (on average 2.0) internal successors, (42), 20 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:36,632 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 108 transitions. [2021-08-12 19:28:36,632 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2021-08-12 19:28:36,632 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:36,632 INFO L550 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:36,832 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable25,25 z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:36,833 INFO L430 AbstractCegarLoop]: === Iteration 27 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:36,833 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:36,833 INFO L82 PathProgramCache]: Analyzing trace with hash 318243375, now seen corresponding path program 21 times [2021-08-12 19:28:36,833 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:36,833 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361427184] [2021-08-12 19:28:36,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:36,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:36,923 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-08-12 19:28:36,923 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:36,923 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1361427184] [2021-08-12 19:28:36,923 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1361427184] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:36,924 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [353699386] [2021-08-12 19:28:36,924 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:36,949 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2021-08-12 19:28:36,949 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:36,950 WARN L261 TraceCheckSpWp]: Trace formula consists of 49 conjuncts, 25 conjunts are in the unsatisfiable core [2021-08-12 19:28:36,950 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:37,207 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:37,208 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [353699386] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:37,208 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:37,208 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2021-08-12 19:28:37,208 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1868944865] [2021-08-12 19:28:37,208 INFO L462 AbstractCegarLoop]: Interpolant automaton has 21 states [2021-08-12 19:28:37,208 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:37,209 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-08-12 19:28:37,209 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=354, Unknown=0, NotChecked=0, Total=420 [2021-08-12 19:28:37,209 INFO L87 Difference]: Start difference. First operand 61 states and 108 transitions. Second operand has 21 states, 21 states have (on average 2.0) internal successors, (42), 20 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:38,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:38,114 INFO L93 Difference]: Finished difference Result 118 states and 205 transitions. [2021-08-12 19:28:38,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2021-08-12 19:28:38,115 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 21 states have (on average 2.0) internal successors, (42), 20 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 23 [2021-08-12 19:28:38,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:38,116 INFO L225 Difference]: With dead ends: 118 [2021-08-12 19:28:38,116 INFO L226 Difference]: Without dead ends: 102 [2021-08-12 19:28:38,117 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 14 SyntacticMatches, 1 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 744 ImplicationChecksByTransitivity, 916.0ms TimeCoverageRelationStatistics Valid=406, Invalid=2246, Unknown=0, NotChecked=0, Total=2652 [2021-08-12 19:28:38,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2021-08-12 19:28:38,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 59. [2021-08-12 19:28:38,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 58 states have (on average 1.7586206896551724) internal successors, (102), 58 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:38,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 102 transitions. [2021-08-12 19:28:38,124 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 102 transitions. Word has length 23 [2021-08-12 19:28:38,124 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:38,124 INFO L482 AbstractCegarLoop]: Abstraction has 59 states and 102 transitions. [2021-08-12 19:28:38,124 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 21 states, 21 states have (on average 2.0) internal successors, (42), 20 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:38,124 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 102 transitions. [2021-08-12 19:28:38,124 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2021-08-12 19:28:38,124 INFO L542 BasicCegarLoop]: Found error trace [2021-08-12 19:28:38,124 INFO L550 BasicCegarLoop]: trace histogram [3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-12 19:28:38,349 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 26 z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable26 [2021-08-12 19:28:38,349 INFO L430 AbstractCegarLoop]: === Iteration 28 === [ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr0ASSERT_VIOLATIONASSERT]=== [2021-08-12 19:28:38,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-12 19:28:38,349 INFO L82 PathProgramCache]: Analyzing trace with hash -216986427, now seen corresponding path program 22 times [2021-08-12 19:28:38,349 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-12 19:28:38,349 INFO L361 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659984254] [2021-08-12 19:28:38,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-12 19:28:38,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-12 19:28:38,448 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-08-12 19:28:38,449 INFO L179 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-12 19:28:38,449 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [659984254] [2021-08-12 19:28:38,449 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [659984254] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:38,449 INFO L361 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [243789779] [2021-08-12 19:28:38,449 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-08-12 19:28:38,475 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-08-12 19:28:38,475 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-08-12 19:28:38,476 WARN L261 TraceCheckSpWp]: Trace formula consists of 49 conjuncts, 25 conjunts are in the unsatisfiable core [2021-08-12 19:28:38,478 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-08-12 19:28:38,718 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-12 19:28:38,718 INFO L200 FreeRefinementEngine]: IpTcStrategyModuleZ3 [243789779] provided 0 perfect and 1 imperfect interpolant sequences [2021-08-12 19:28:38,718 INFO L226 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-08-12 19:28:38,718 INFO L239 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2021-08-12 19:28:38,719 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1918412800] [2021-08-12 19:28:38,719 INFO L462 AbstractCegarLoop]: Interpolant automaton has 21 states [2021-08-12 19:28:38,719 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-12 19:28:38,720 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-08-12 19:28:38,720 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=354, Unknown=0, NotChecked=0, Total=420 [2021-08-12 19:28:38,720 INFO L87 Difference]: Start difference. First operand 59 states and 102 transitions. Second operand has 21 states, 21 states have (on average 2.0) internal successors, (42), 20 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:39,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-12 19:28:39,339 INFO L93 Difference]: Finished difference Result 94 states and 166 transitions. [2021-08-12 19:28:39,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-08-12 19:28:39,339 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 21 states have (on average 2.0) internal successors, (42), 20 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 23 [2021-08-12 19:28:39,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-08-12 19:28:39,339 INFO L225 Difference]: With dead ends: 94 [2021-08-12 19:28:39,339 INFO L226 Difference]: Without dead ends: 0 [2021-08-12 19:28:39,340 INFO L806 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 14 SyntacticMatches, 1 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 393 ImplicationChecksByTransitivity, 668.4ms TimeCoverageRelationStatistics Valid=260, Invalid=1380, Unknown=0, NotChecked=0, Total=1640 [2021-08-12 19:28:39,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2021-08-12 19:28:39,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2021-08-12 19:28:39,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 0 states, 0 states have (on average 0.0) internal successors, (0), 0 states have internal predecessors, (0), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:39,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2021-08-12 19:28:39,341 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 23 [2021-08-12 19:28:39,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-08-12 19:28:39,341 INFO L482 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2021-08-12 19:28:39,341 INFO L483 AbstractCegarLoop]: Interpolant automaton has has 21 states, 21 states have (on average 2.0) internal successors, (42), 20 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-12 19:28:39,341 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2021-08-12 19:28:39,341 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2021-08-12 19:28:39,552 WARN L519 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 27 z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable27 [2021-08-12 19:28:39,554 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 0 states and 0 transitions. [2021-08-12 19:28:39,709 WARN L205 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 113 DAG size of output: 101 [2021-08-12 19:28:40,320 WARN L205 SmtUtils]: Spent 608.00 ms on a formula simplification. DAG size of input: 235 DAG size of output: 151 [2021-08-12 19:28:40,900 WARN L205 SmtUtils]: Spent 579.00 ms on a formula simplification. DAG size of input: 171 DAG size of output: 142 [2021-08-12 19:28:41,287 WARN L205 SmtUtils]: Spent 385.00 ms on a formula simplification. DAG size of input: 161 DAG size of output: 132 [2021-08-12 19:28:41,970 WARN L205 SmtUtils]: Spent 476.00 ms on a formula simplification. DAG size of input: 171 DAG size of output: 142 [2021-08-12 19:28:42,549 WARN L205 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 174 DAG size of output: 90 [2021-08-12 19:28:42,793 WARN L205 SmtUtils]: Spent 242.00 ms on a formula simplification. DAG size of input: 187 DAG size of output: 143 [2021-08-12 19:28:43,042 WARN L205 SmtUtils]: Spent 247.00 ms on a formula simplification. DAG size of input: 161 DAG size of output: 132 [2021-08-12 19:28:43,444 WARN L205 SmtUtils]: Spent 311.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 41 [2021-08-12 19:28:43,734 WARN L205 SmtUtils]: Spent 289.00 ms on a formula simplification. DAG size of input: 143 DAG size of output: 15 [2021-08-12 19:28:44,314 WARN L205 SmtUtils]: Spent 578.00 ms on a formula simplification. DAG size of input: 141 DAG size of output: 23 [2021-08-12 19:28:44,886 WARN L205 SmtUtils]: Spent 571.00 ms on a formula simplification. DAG size of input: 128 DAG size of output: 22 [2021-08-12 19:28:45,320 WARN L205 SmtUtils]: Spent 259.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 41 [2021-08-12 19:28:45,582 WARN L205 SmtUtils]: Spent 261.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 41 [2021-08-12 19:28:46,135 WARN L205 SmtUtils]: Spent 552.00 ms on a formula simplification. DAG size of input: 141 DAG size of output: 23 [2021-08-12 19:28:46,485 WARN L205 SmtUtils]: Spent 272.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 41 [2021-08-12 19:28:46,744 WARN L205 SmtUtils]: Spent 258.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 41 [2021-08-12 19:28:47,007 WARN L205 SmtUtils]: Spent 262.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 41 [2021-08-12 19:28:47,269 WARN L205 SmtUtils]: Spent 261.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 41 [2021-08-12 19:28:47,638 WARN L205 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 12 [2021-08-12 19:28:48,077 WARN L205 SmtUtils]: Spent 168.00 ms on a formula simplification. DAG size of input: 89 DAG size of output: 15 [2021-08-12 19:28:48,298 WARN L205 SmtUtils]: Spent 219.00 ms on a formula simplification. DAG size of input: 141 DAG size of output: 14 [2021-08-12 19:28:48,869 WARN L205 SmtUtils]: Spent 570.00 ms on a formula simplification. DAG size of input: 128 DAG size of output: 22 [2021-08-12 19:28:49,001 INFO L1281 BasicCegarLoop]: Computed Owicki-Gries annotation of size 9787 in 9441257799ns [2021-08-12 19:28:49,003 INFO L113 kiGriesValidityCheck]: 10#false [2021-08-12 19:28:49,004 INFO L113 kiGriesValidityCheck]: 11#(or (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np1_1 (not v_np0_1)) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (<= (+ i1 1) (+ counter N2)) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (not v_np26_1) v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (<= (+ i1 1) (+ counter N2)) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1)) [2021-08-12 19:28:49,008 INFO L113 kiGriesValidityCheck]: 15#(and (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) v_np14_1 (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np0_1) v_np24_1) [2021-08-12 19:28:49,010 INFO L113 kiGriesValidityCheck]: 21#(or (and (<= (+ counter i2) i1) (not v_np25_1) (not v_np22_1) (not v_np23_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (<= counter i1) (not v_np26_1) v_np6_1 (not v_np0_1) (<= i1 counter) v_np24_1 v_np20_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 (not v_np0_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= counter i1) (<= i1 (+ counter i2)) (<= i1 counter) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) v_np24_1 v_np20_1) (and (<= (+ counter i2) i1) (not v_np25_1) (not v_np22_1) (not v_np23_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) (<= counter i1) v_np2_1 (not v_np26_1) (not v_np0_1) (<= i1 counter) v_np24_1 v_np20_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) (not v_np0_1) v_np8_1 (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= counter i1) (<= i1 (+ counter i2)) (<= i1 counter) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) v_np24_1 v_np20_1)) [2021-08-12 19:28:49,010 INFO L113 kiGriesValidityCheck]: 25#(or (and (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) v_np4_1 (not v_np0_1) v_np24_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np2_1) (not v_np17_1) v_np15_1 (not v_np21_1) (<= counter 0) (not v_np18_1) (not v_np19_1) (not v_np0_1) (<= i1 counter) (<= 0 i1) v_np24_1) (and (<= (+ counter i2) i1) (not v_np25_1) (not v_np22_1) (not v_np23_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (<= counter i1) (not v_np26_1) v_np6_1 (not v_np0_1) (<= i1 counter) v_np24_1 v_np20_1) (and (= i2 0) (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (<= (+ counter i2) 0) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) v_np16_1 (not v_np18_1) (not v_np19_1) (not v_np0_1) (<= i1 counter) (<= 0 i1) v_np24_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 (not v_np0_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= counter i1) (<= i1 (+ counter i2)) (<= i1 counter) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) v_np24_1 v_np20_1) (and (= i2 0) (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (<= (+ counter i2) 0) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) v_np19_1 (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np0_1) (<= i1 counter) v_np24_1 (<= 0 i1)) (and (<= (+ counter i2) i1) (not v_np25_1) (not v_np22_1) (not v_np23_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) (<= counter i1) v_np2_1 (not v_np26_1) (not v_np0_1) (<= i1 counter) v_np24_1 v_np20_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) (not v_np0_1) v_np8_1 (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= counter i1) (<= i1 (+ counter i2)) (<= i1 counter) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) v_np24_1 v_np20_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np12_1 (not v_np6_1) (not v_np4_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (<= i1 0) (not v_np19_1) (not v_np0_1) (<= 0 i1) v_np24_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) v_np14_1 (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np0_1) v_np24_1) (and (= i2 0) (not v_np25_1) (not v_np22_1) (not v_np20_1) v_np26_1 (<= 0 N2) (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (<= (+ counter i2) 0) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np0_1) (<= i1 counter) v_np23_1 (<= 0 i1) v_np24_1)) [2021-08-12 19:28:49,017 INFO L113 kiGriesValidityCheck]: 23#false [2021-08-12 19:28:49,018 INFO L113 kiGriesValidityCheck]: 21#(or (and (<= (+ counter i2) i1) (not v_np25_1) (not v_np22_1) (not v_np23_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (<= counter i1) (not v_np26_1) v_np6_1 (not v_np0_1) (<= i1 counter) v_np24_1 v_np20_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 (not v_np0_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= counter i1) (<= i1 (+ counter i2)) (<= i1 counter) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) v_np24_1 v_np20_1) (and (<= (+ counter i2) i1) (not v_np25_1) (not v_np22_1) (not v_np23_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) (<= counter i1) v_np2_1 (not v_np26_1) (not v_np0_1) (<= i1 counter) v_np24_1 v_np20_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) (not v_np0_1) v_np8_1 (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= counter i1) (<= i1 (+ counter i2)) (<= i1 counter) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) v_np24_1 v_np20_1)) [2021-08-12 19:28:49,018 INFO L113 kiGriesValidityCheck]: 26#(or (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (not v_np26_1) v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (<= (+ counter i2) i1) (<= counter i1) (<= (+ counter N2) i1) (<= i1 counter) (<= i1 (+ counter N2)) (<= (+ counter N2 1) N1)) (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (<= (+ counter i2 1) N1))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np3_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np8_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (<= (+ i1 1) (+ counter N2)) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (not v_np26_1) v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np5_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) v_np1_1 v_np7_1 (not v_np0_1)) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) v_np1_1 (not v_np0_1)) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np7_1 v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np1_1 (not v_np0_1)) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (<= (+ counter i2) i1) (<= counter i1) (<= (+ counter N2) i1) (<= i1 counter) (<= i1 (+ counter N2)) (<= (+ counter N2 1) N1)) (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (<= (+ counter i2 1) N1))) (not v_np19_1) (not v_np26_1) v_np6_1 v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) v_np1_1 v_np3_1 (not v_np0_1)) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np5_1 v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (<= (+ i1 1) (+ counter N2)) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1)) [2021-08-12 19:28:49,025 INFO L113 kiGriesValidityCheck]: 5#(and (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) v_np4_1 (not v_np0_1) v_np24_1) [2021-08-12 19:28:49,027 INFO L113 kiGriesValidityCheck]: 14#(or (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (not v_np26_1) v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) v_np1_1 (not v_np0_1)) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np8_1 v_np0_1)) [2021-08-12 19:28:49,031 INFO L113 kiGriesValidityCheck]: 16#(and (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np2_1) (not v_np17_1) v_np15_1 (not v_np21_1) (<= counter 0) (not v_np18_1) (not v_np19_1) (not v_np0_1) (<= i1 counter) (<= 0 i1) v_np24_1) [2021-08-12 19:28:49,033 INFO L113 kiGriesValidityCheck]: 24#(and (= i2 0) (not v_np25_1) (not v_np22_1) (not v_np20_1) v_np26_1 (<= 0 N2) (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (<= (+ counter i2) 0) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np0_1) (<= i1 counter) v_np23_1 (<= 0 i1) v_np24_1) [2021-08-12 19:28:49,034 INFO L113 kiGriesValidityCheck]: 27#(or (and (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) v_np4_1 (not v_np0_1) v_np24_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np2_1) (not v_np17_1) v_np15_1 (not v_np21_1) (<= counter 0) (not v_np18_1) (not v_np19_1) (not v_np0_1) (<= i1 counter) (<= 0 i1) v_np24_1) (and (= i2 0) (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (<= (+ counter i2) 0) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) v_np16_1 (not v_np18_1) (not v_np19_1) (not v_np0_1) (<= i1 counter) (<= 0 i1) v_np24_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np1_1 (not v_np0_1)) (and (= i2 0) (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (<= (+ counter i2) 0) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) v_np19_1 (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np0_1) (<= i1 counter) v_np24_1 (<= 0 i1)) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) v_np1_1 v_np3_1 (not v_np0_1)) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) v_np1_1 v_np7_1 (not v_np0_1)) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np12_1 (not v_np6_1) (not v_np4_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (<= i1 0) (not v_np19_1) (not v_np0_1) (<= 0 i1) v_np24_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) v_np14_1 (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np0_1) v_np24_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) v_np1_1 (not v_np0_1)) (and (= i2 0) (not v_np25_1) (not v_np22_1) (not v_np20_1) v_np26_1 (<= 0 N2) (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (<= (+ counter i2) 0) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np0_1) (<= i1 counter) v_np23_1 (<= 0 i1) v_np24_1)) [2021-08-12 19:28:49,038 INFO L113 kiGriesValidityCheck]: 2#(or (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np1_1 (not v_np0_1)) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) v_np1_1 v_np3_1 (not v_np0_1)) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) v_np1_1 v_np7_1 (not v_np0_1)) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) v_np1_1 (not v_np0_1))) [2021-08-12 19:28:49,038 INFO L113 kiGriesValidityCheck]: 8#(or (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (<= (+ counter i2) i1) (<= counter i1) (<= (+ counter N2) i1) (<= i1 counter) (<= i1 (+ counter N2)) (<= (+ counter N2 1) N1)) (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (<= (+ counter i2 1) N1))) (not v_np19_1) (not v_np26_1) v_np6_1 v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) v_np1_1 v_np7_1 (not v_np0_1)) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np5_1 v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np7_1 v_np8_1 v_np0_1)) [2021-08-12 19:28:49,039 INFO L113 kiGriesValidityCheck]: 26#(or (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (not v_np26_1) v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (<= (+ counter i2) i1) (<= counter i1) (<= (+ counter N2) i1) (<= i1 counter) (<= i1 (+ counter N2)) (<= (+ counter N2 1) N1)) (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (<= (+ counter i2 1) N1))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np3_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np8_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (<= (+ i1 1) (+ counter N2)) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (not v_np26_1) v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np5_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) v_np1_1 v_np7_1 (not v_np0_1)) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) v_np1_1 (not v_np0_1)) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np7_1 v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np1_1 (not v_np0_1)) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (<= (+ counter i2) i1) (<= counter i1) (<= (+ counter N2) i1) (<= i1 counter) (<= i1 (+ counter N2)) (<= (+ counter N2 1) N1)) (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (<= (+ counter i2 1) N1))) (not v_np19_1) (not v_np26_1) v_np6_1 v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) v_np1_1 v_np3_1 (not v_np0_1)) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np5_1 v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (<= (+ i1 1) (+ counter N2)) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1)) [2021-08-12 19:28:49,044 INFO L113 kiGriesValidityCheck]: 13#(and (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np12_1 (not v_np6_1) (not v_np4_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (<= i1 0) (not v_np19_1) (not v_np0_1) (<= 0 i1) v_np24_1) [2021-08-12 19:28:49,046 INFO L113 kiGriesValidityCheck]: 10#false [2021-08-12 19:28:49,046 INFO L113 kiGriesValidityCheck]: 3#(or (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np3_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np25_1) (not v_np22_1) (not v_np23_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) (<= counter i1) v_np2_1 (not v_np26_1) (not v_np0_1) (<= i1 counter) v_np24_1 v_np20_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np7_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (<= (+ i1 1) (+ counter N2)) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1)) [2021-08-12 19:28:49,050 INFO L113 kiGriesValidityCheck]: 6#(or (and (not v_np25_1) (not v_np22_1) (not v_np23_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 (not v_np0_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= counter i1) (<= i1 (+ counter i2)) (<= i1 counter) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) v_np24_1 v_np20_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np5_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np5_1 v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 v_np0_1)) [2021-08-12 19:28:49,053 INFO L113 kiGriesValidityCheck]: 7#(or (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (not v_np26_1) v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (<= (+ counter i2) i1) (<= counter i1) (<= (+ counter N2) i1) (<= i1 counter) (<= i1 (+ counter N2)) (<= (+ counter N2 1) N1)) (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (<= (+ counter i2 1) N1))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np6_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np25_1) (not v_np22_1) (not v_np23_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (<= counter i1) (not v_np26_1) v_np6_1 (not v_np0_1) (<= i1 counter) v_np24_1 v_np20_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (<= (+ counter i2) i1) (<= counter i1) (<= (+ counter N2) i1) (<= i1 counter) (<= i1 (+ counter N2)) (<= (+ counter N2 1) N1)) (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (<= (+ counter i2 1) N1))) (not v_np19_1) (not v_np26_1) v_np6_1 v_np7_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (<= (+ i1 1) (+ counter N2)) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (not v_np26_1) v_np6_1 v_np0_1)) [2021-08-12 19:28:49,057 INFO L113 kiGriesValidityCheck]: 3#(or (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np3_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np25_1) (not v_np22_1) (not v_np23_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) (<= counter i1) v_np2_1 (not v_np26_1) (not v_np0_1) (<= i1 counter) v_np24_1 v_np20_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np7_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (<= (+ i1 1) (+ counter N2)) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1)) [2021-08-12 19:28:49,060 INFO L113 kiGriesValidityCheck]: 17#(and (= i2 0) (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (<= (+ counter i2) 0) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) v_np16_1 (not v_np18_1) (not v_np19_1) (not v_np0_1) (<= i1 counter) (<= 0 i1) v_np24_1) [2021-08-12 19:28:49,062 INFO L113 kiGriesValidityCheck]: 24#(and (= i2 0) (not v_np25_1) (not v_np22_1) (not v_np20_1) v_np26_1 (<= 0 N2) (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (<= (+ counter i2) 0) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np0_1) (<= i1 counter) v_np23_1 (<= 0 i1) v_np24_1) [2021-08-12 19:28:49,062 INFO L113 kiGriesValidityCheck]: 28#(or (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (not v_np26_1) v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (<= (+ counter i2) i1) (<= counter i1) (<= (+ counter N2) i1) (<= i1 counter) (<= i1 (+ counter N2)) (<= (+ counter N2 1) N1)) (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (<= (+ counter i2 1) N1))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np3_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np8_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (<= (+ i1 1) (+ counter N2)) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (not v_np26_1) v_np6_1 v_np0_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) (not v_np0_1) v_np8_1 (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= counter i1) (<= i1 (+ counter i2)) (<= i1 counter) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) v_np24_1 v_np20_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np5_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np7_1 v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np8_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np25_1) (not v_np22_1) (not v_np23_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (<= counter i1) (not v_np26_1) v_np6_1 (not v_np0_1) (<= i1 counter) v_np24_1 v_np20_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (<= (+ counter i2) i1) (<= counter i1) (<= (+ counter N2) i1) (<= i1 counter) (<= i1 (+ counter N2)) (<= (+ counter N2 1) N1)) (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (<= (+ counter i2 1) N1))) (not v_np19_1) (not v_np26_1) v_np6_1 v_np7_1 v_np0_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 (not v_np0_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= counter i1) (<= i1 (+ counter i2)) (<= i1 counter) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) v_np24_1 v_np20_1) (and (<= (+ counter i2) i1) (not v_np25_1) (not v_np22_1) (not v_np23_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) (<= counter i1) v_np2_1 (not v_np26_1) (not v_np0_1) (<= i1 counter) v_np24_1 v_np20_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np5_1 v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (<= (+ i1 1) (+ counter N2)) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1)) [2021-08-12 19:28:49,065 INFO L113 kiGriesValidityCheck]: 1#(or (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (not v_np26_1) v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (<= (+ counter i2) i1) (<= counter i1) (<= (+ counter N2) i1) (<= i1 counter) (<= i1 (+ counter N2)) (<= (+ counter N2 1) N1)) (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (<= (+ counter i2 1) N1))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np3_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np8_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (<= (+ i1 1) (+ counter N2)) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (not v_np26_1) v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np5_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np7_1 v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (<= (+ counter i2) i1) (<= counter i1) (<= (+ counter N2) i1) (<= i1 counter) (<= i1 (+ counter N2)) (<= (+ counter N2 1) N1)) (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (<= (+ counter i2 1) N1))) (not v_np19_1) (not v_np26_1) v_np6_1 v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np5_1 v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (<= (+ i1 1) (+ counter N2)) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1)) [2021-08-12 19:28:49,066 INFO L113 kiGriesValidityCheck]: 9#(or (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np8_1 v_np0_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) (not v_np0_1) v_np8_1 (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= counter i1) (<= i1 (+ counter i2)) (<= i1 counter) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) v_np24_1 v_np20_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np7_1 v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np8_1 v_np0_1)) [2021-08-12 19:28:49,066 INFO L113 kiGriesValidityCheck]: 28#(or (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (not v_np26_1) v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (<= (+ counter i2) i1) (<= counter i1) (<= (+ counter N2) i1) (<= i1 counter) (<= i1 (+ counter N2)) (<= (+ counter N2 1) N1)) (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (<= (+ counter i2 1) N1))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np3_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np8_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (<= (+ i1 1) (+ counter N2)) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (not v_np26_1) v_np6_1 v_np0_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) (not v_np0_1) v_np8_1 (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= counter i1) (<= i1 (+ counter i2)) (<= i1 counter) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) v_np24_1 v_np20_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np5_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np7_1 v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np8_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np25_1) (not v_np22_1) (not v_np23_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (<= counter i1) (not v_np26_1) v_np6_1 (not v_np0_1) (<= i1 counter) v_np24_1 v_np20_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (<= (+ counter i2) i1) (<= counter i1) (<= (+ counter N2) i1) (<= i1 counter) (<= i1 (+ counter N2)) (<= (+ counter N2 1) N1)) (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (<= (+ counter i2 1) N1))) (not v_np19_1) (not v_np26_1) v_np6_1 v_np7_1 v_np0_1) (and (not v_np25_1) (not v_np22_1) (not v_np23_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 (not v_np0_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= counter i1) (<= i1 (+ counter i2)) (<= i1 counter) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) v_np24_1 v_np20_1) (and (<= (+ counter i2) i1) (not v_np25_1) (not v_np22_1) (not v_np23_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) (<= counter i1) v_np2_1 (not v_np26_1) (not v_np0_1) (<= i1 counter) v_np24_1 v_np20_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np5_1 v_np7_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (or (and (<= N1 N2) (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1)) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= (+ N1 1) (+ counter N2)))) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) v_np10_1 (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np16_1) (<= (+ i1 1) (+ counter N2)) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1)) [2021-08-12 19:28:49,071 INFO L113 kiGriesValidityCheck]: 20#(and (= i2 0) (not v_np25_1) (not v_np22_1) (not v_np23_1) (not v_np20_1) v_np26_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (<= (+ counter i2) 0) (not v_np6_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) v_np19_1 (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np0_1) (<= i1 counter) v_np24_1 (<= 0 i1)) [2021-08-12 19:28:49,073 INFO L113 kiGriesValidityCheck]: 4#(or (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np8_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (<= (+ counter i2) i1) (<= counter i1) (<= (+ counter N2) i1) (<= i1 counter) (<= i1 (+ counter N2)) (<= (+ counter N2 1) N1)) (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (<= (+ counter i2 1) N1))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (or (and (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= (+ counter N2) i1) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)))) (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np3_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) v_np1_1 v_np3_1 (not v_np0_1)) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np13_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (not v_np18_1) (or (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) N1) (<= (+ counter N2) N1)) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= (+ counter i2) i1) (<= counter i1) (<= i1 counter) (<= i1 (+ counter N2)) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (= counter 0) (< 0 N1) (<= i1 N2) (<= N1 1) (< 0 N2) (<= (+ counter i2) N1) (<= N2 1)) (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2))) (and (<= i1 N2) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (< (+ counter N2) (+ N1 1)) (<= N1 (+ counter N2)))) (not v_np19_1) (not v_np26_1) v_np3_1 v_np5_1 v_np0_1)) [2021-08-12 19:28:49,076 INFO L113 kiGriesValidityCheck]: 14#(or (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (<= (+ counter i2 1) N1) (not v_np19_1) (not v_np26_1) v_np6_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np5_1 v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np26_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np27_1) (not v_np9_1) (not v_np8_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) v_np1_1 (not v_np0_1)) (and (<= (+ counter i2) i1) (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) (<= i1 (+ counter i2)) v_np27_1 (<= (+ counter i2) N1) (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np8_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np17_1) (not v_np21_1) (<= i1 (+ counter N2)) (not v_np18_1) (not v_np19_1) v_np2_1 (not v_np26_1) v_np0_1) (and (not v_np22_1) (not v_np23_1) v_np25_1 (not v_np20_1) v_np27_1 (not v_np5_1) (not v_np7_1) (not v_np3_1) (not v_np9_1) (not v_np1_1) (not v_np11_1) (not v_np14_1) v_np13_1 (not v_np6_1) (not v_np24_1) (not v_np4_1) (not v_np12_1) (not v_np10_1) (not v_np16_1) (not v_np15_1) (not v_np2_1) (not v_np17_1) (not v_np21_1) (or (and (<= N1 (+ counter i2)) (<= (+ counter i2) i1) (<= i1 (+ counter i2)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (<= N1 (+ i2 1)) (<= i1 (+ i2 1)) (<= (+ counter i2) N1) (<= N1 (+ counter N2))) (and (< N1 (+ counter N2 1)) (<= counter 0) (<= i1 counter) (<= (+ counter i2) 0) (<= (+ counter i2) N1))) (not v_np18_1) (not v_np19_1) (not v_np26_1) v_np8_1 v_np0_1)) [2021-08-12 19:28:49,347 INFO L1287 BasicCegarLoop]: Checked inductivity and non-interference of Owicki-Gries annotation in 352944539ns [2021-08-12 19:28:49,349 INFO L239 ceAbstractionStarter]: Analysis of concurrent program completed with 1 thread instances [2021-08-12 19:28:49,351 INFO L202 PluginConnector]: Adding new model figure1-alt.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 12.08 07:28:49 BasicIcfg [2021-08-12 19:28:49,352 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2021-08-12 19:28:49,352 INFO L168 Benchmark]: Toolchain (without parser) took 39350.57 ms. Allocated memory was 155.2 MB in the beginning and 270.5 MB in the end (delta: 115.3 MB). Free memory was 134.8 MB in the beginning and 183.4 MB in the end (delta: -48.6 MB). Peak memory consumption was 67.7 MB. Max. memory is 8.0 GB. [2021-08-12 19:28:49,352 INFO L168 Benchmark]: Boogie PL CUP Parser took 0.16 ms. Allocated memory is still 155.2 MB. Free memory is still 135.9 MB. There was no memory consumed. Max. memory is 8.0 GB. [2021-08-12 19:28:49,352 INFO L168 Benchmark]: Boogie Procedure Inliner took 21.39 ms. Allocated memory is still 155.2 MB. Free memory was 134.7 MB in the beginning and 133.3 MB in the end (delta: 1.4 MB). There was no memory consumed. Max. memory is 8.0 GB. [2021-08-12 19:28:49,352 INFO L168 Benchmark]: Boogie Preprocessor took 13.01 ms. Allocated memory is still 155.2 MB. Free memory was 133.3 MB in the beginning and 132.3 MB in the end (delta: 951.7 kB). Peak memory consumption was 2.1 MB. Max. memory is 8.0 GB. [2021-08-12 19:28:49,352 INFO L168 Benchmark]: RCFGBuilder took 225.02 ms. Allocated memory is still 155.2 MB. Free memory was 132.3 MB in the beginning and 120.9 MB in the end (delta: 11.4 MB). Peak memory consumption was 11.5 MB. Max. memory is 8.0 GB. [2021-08-12 19:28:49,352 INFO L168 Benchmark]: TraceAbstraction took 39086.74 ms. Allocated memory was 155.2 MB in the beginning and 270.5 MB in the end (delta: 115.3 MB). Free memory was 120.4 MB in the beginning and 183.4 MB in the end (delta: -63.0 MB). Peak memory consumption was 53.1 MB. Max. memory is 8.0 GB. [2021-08-12 19:28:49,353 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.16 ms. Allocated memory is still 155.2 MB. Free memory is still 135.9 MB. There was no memory consumed. Max. memory is 8.0 GB. * Boogie Procedure Inliner took 21.39 ms. Allocated memory is still 155.2 MB. Free memory was 134.7 MB in the beginning and 133.3 MB in the end (delta: 1.4 MB). There was no memory consumed. Max. memory is 8.0 GB. * Boogie Preprocessor took 13.01 ms. Allocated memory is still 155.2 MB. Free memory was 133.3 MB in the beginning and 132.3 MB in the end (delta: 951.7 kB). Peak memory consumption was 2.1 MB. Max. memory is 8.0 GB. * RCFGBuilder took 225.02 ms. Allocated memory is still 155.2 MB. Free memory was 132.3 MB in the beginning and 120.9 MB in the end (delta: 11.4 MB). Peak memory consumption was 11.5 MB. Max. memory is 8.0 GB. * TraceAbstraction took 39086.74 ms. Allocated memory was 155.2 MB in the beginning and 270.5 MB in the end (delta: 115.3 MB). Free memory was 120.4 MB in the beginning and 183.4 MB in the end (delta: -63.0 MB). Peak memory consumption was 53.1 MB. Max. memory is 8.0 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - PositiveResult [Line: 51]: assertion always holds For all program executions holds that assertion always holds at this location - StatisticsResult: Ultimate Automizer benchmark data with 1 thread instances CFG has 5 procedures, 32 locations, 3 error locations. Started 1 CEGAR loops. VerificationResult: SAFE, OverallTime: 29220.0ms, OverallIterations: 28, TraceHistogramMax: 3, EmptinessCheckTime: 19.6ms, AutomataDifference: 13404.1ms, DeadEndRemovalTime: 0.0ms, HoareAnnotationTime: 0.0ms, InitialAbstractionConstructionTime: 55.7ms, PartialOrderReductionTime: 0.0ms, HoareTripleCheckerStatistics: 546 SDtfs, 2905 SDslu, 3887 SDs, 0 SdLazy, 7277 SolverSat, 415 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3290.7ms Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1218 GetRequests, 289 SyntacticMatches, 26 SemanticMatches, 903 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8019 ImplicationChecksByTransitivity, 14837.6ms Time, 0.0ms BasicInterpolantAutomatonTime, BiggestAbstraction: size=67occurred in iteration=10, InterpolantAutomatonStates: 642, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0ms DumpTime, AutomataMinimizationStatistics: 170.4ms AutomataMinimizationTime, 28 MinimizatonAttempts, 848 StatesRemovedByMinimization, 27 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 71.3ms SsaConstructionTime, 259.7ms SatisfiabilityAnalysisTime, 8958.8ms InterpolantComputationTime, 1078 NumberOfCodeBlocks, 1078 NumberOfCodeBlocksAsserted, 82 NumberOfCheckSat, 1024 ConstructedInterpolants, 0 QuantifiedInterpolants, 12797 SizeOfPredicates, 130 NumberOfNonLiveVariables, 1085 ConjunctsInSsa, 496 ConjunctsInUnsatCore, 54 InterpolantComputations, 2 PerfectInterpolantSequences, 14/226 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available - AllSpecificationsHoldResult: All specifications hold 1 specifications checked. All of them hold RESULT: Ultimate proved your program to be correct! Received shutdown request...