/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -s ../../../trunk/examples/settings/automizer/concurrent/svcomp-Reach-32bit-Automizer_Default-noMmResRef-MCRwithDepranks-Lazy.epf -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml -i ../../../trunk/examples/concurrent/bpl/regression/showcase/FischerWithBug.bpl -------------------------------------------------------------------------------- This is Ultimate 0.2.2-wip.dk.mcr-reduction-44898dd [2022-02-16 09:55:26,979 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-16 09:55:26,981 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-16 09:55:27,026 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2022-02-16 09:55:27,040 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-16 09:55:27,041 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-16 09:55:27,041 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-16 09:55:27,042 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-16 09:55:27,043 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-16 09:55:27,043 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-16 09:55:27,044 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-16 09:55:27,052 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-16 09:55:27,053 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-16 09:55:27,064 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-16 09:55:27,065 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-16 09:55:27,065 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-16 09:55:27,067 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-02-16 09:55:27,071 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-16 09:55:27,072 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-16 09:55:27,072 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-16 09:55:27,074 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/concurrent/svcomp-Reach-32bit-Automizer_Default-noMmResRef-MCRwithDepranks-Lazy.epf [2022-02-16 09:55:27,093 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-16 09:55:27,094 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-16 09:55:27,094 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-16 09:55:27,094 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-16 09:55:27,094 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-02-16 09:55:27,094 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-02-16 09:55:27,095 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-16 09:55:27,095 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-16 09:55:27,097 INFO L138 SettingsManager]: * Use SBE=true [2022-02-16 09:55:27,097 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-16 09:55:27,098 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-16 09:55:27,098 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-16 09:55:27,098 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-16 09:55:27,098 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-16 09:55:27,098 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-02-16 09:55:27,098 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-02-16 09:55:27,098 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-02-16 09:55:27,098 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-16 09:55:27,098 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-16 09:55:27,099 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-16 09:55:27,099 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-02-16 09:55:27,099 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-16 09:55:27,099 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-16 09:55:27,099 INFO L138 SettingsManager]: * To the following directory=./dump/ [2022-02-16 09:55:27,099 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-02-16 09:55:27,099 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-16 09:55:27,099 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-16 09:55:27,100 INFO L138 SettingsManager]: * Construct finite automaton lazily=true [2022-02-16 09:55:27,100 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-02-16 09:55:27,100 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-02-16 09:55:27,101 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-16 09:55:27,101 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-02-16 09:55:27,101 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=OFF [2022-02-16 09:55:27,101 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PARTIAL_ORDER_FA [2022-02-16 09:55:27,101 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-02-16 09:55:27,101 INFO L138 SettingsManager]: * Partial Order Reduction in concurrent analysis=MCR_WITH_DEPRANKS [2022-02-16 09:55:27,101 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release [2022-02-16 09:55:27,267 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-16 09:55:27,282 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-16 09:55:27,284 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-16 09:55:27,285 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2022-02-16 09:55:27,285 INFO L275 PluginConnector]: Boogie PL CUP Parser initialized [2022-02-16 09:55:27,286 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/concurrent/bpl/regression/showcase/FischerWithBug.bpl [2022-02-16 09:55:27,286 INFO L110 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/concurrent/bpl/regression/showcase/FischerWithBug.bpl' [2022-02-16 09:55:27,311 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-16 09:55:27,312 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2022-02-16 09:55:27,315 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-16 09:55:27,315 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-16 09:55:27,315 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-16 09:55:27,323 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "FischerWithBug.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 16.02 09:55:27" (1/1) ... [2022-02-16 09:55:27,327 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "FischerWithBug.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 16.02 09:55:27" (1/1) ... [2022-02-16 09:55:27,331 INFO L137 Inliner]: procedures = 4, calls = 3, calls flagged for inlining = 0, calls inlined = 0, statements flattened = 0 [2022-02-16 09:55:27,332 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-16 09:55:27,333 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-16 09:55:27,333 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-16 09:55:27,333 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-16 09:55:27,338 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "FischerWithBug.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 16.02 09:55:27" (1/1) ... [2022-02-16 09:55:27,338 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "FischerWithBug.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 16.02 09:55:27" (1/1) ... [2022-02-16 09:55:27,338 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "FischerWithBug.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 16.02 09:55:27" (1/1) ... [2022-02-16 09:55:27,339 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "FischerWithBug.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 16.02 09:55:27" (1/1) ... [2022-02-16 09:55:27,340 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "FischerWithBug.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 16.02 09:55:27" (1/1) ... [2022-02-16 09:55:27,342 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "FischerWithBug.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 16.02 09:55:27" (1/1) ... [2022-02-16 09:55:27,343 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "FischerWithBug.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 16.02 09:55:27" (1/1) ... [2022-02-16 09:55:27,343 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-16 09:55:27,344 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-16 09:55:27,344 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-16 09:55:27,344 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-16 09:55:27,345 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "FischerWithBug.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 16.02 09:55:27" (1/1) ... [2022-02-16 09:55:27,350 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-02-16 09:55:27,354 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-16 09:55:27,363 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-02-16 09:55:27,390 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-02-16 09:55:27,406 INFO L124 BoogieDeclarations]: Specification and implementation of procedure Process2 given in one single declaration [2022-02-16 09:55:27,406 INFO L130 BoogieDeclarations]: Found specification of procedure Process2 [2022-02-16 09:55:27,406 INFO L138 BoogieDeclarations]: Found implementation of procedure Process2 [2022-02-16 09:55:27,406 INFO L124 BoogieDeclarations]: Specification and implementation of procedure Process1 given in one single declaration [2022-02-16 09:55:27,407 INFO L130 BoogieDeclarations]: Found specification of procedure Process1 [2022-02-16 09:55:27,407 INFO L138 BoogieDeclarations]: Found implementation of procedure Process1 [2022-02-16 09:55:27,407 INFO L124 BoogieDeclarations]: Specification and implementation of procedure ULTIMATE.start given in one single declaration [2022-02-16 09:55:27,407 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-16 09:55:27,407 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-16 09:55:27,407 INFO L124 BoogieDeclarations]: Specification and implementation of procedure Clock given in one single declaration [2022-02-16 09:55:27,407 INFO L130 BoogieDeclarations]: Found specification of procedure Clock [2022-02-16 09:55:27,407 INFO L138 BoogieDeclarations]: Found implementation of procedure Clock [2022-02-16 09:55:27,408 WARN L208 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2022-02-16 09:55:27,440 INFO L234 CfgBuilder]: Building ICFG [2022-02-16 09:55:27,441 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-16 09:55:27,558 INFO L275 CfgBuilder]: Performing block encoding [2022-02-16 09:55:27,563 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-16 09:55:27,563 INFO L299 CfgBuilder]: Removed 3 assume(true) statements. [2022-02-16 09:55:27,564 INFO L202 PluginConnector]: Adding new model FischerWithBug.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.02 09:55:27 BoogieIcfgContainer [2022-02-16 09:55:27,564 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-16 09:55:27,565 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-02-16 09:55:27,566 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-02-16 09:55:27,588 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-02-16 09:55:27,588 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "FischerWithBug.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 16.02 09:55:27" (1/2) ... [2022-02-16 09:55:27,589 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@38c61b0d and model type FischerWithBug.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 16.02 09:55:27, skipping insertion in model container [2022-02-16 09:55:27,589 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "FischerWithBug.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.02 09:55:27" (2/2) ... [2022-02-16 09:55:27,590 INFO L111 eAbstractionObserver]: Analyzing ICFG FischerWithBug.bpl [2022-02-16 09:55:27,593 WARN L150 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2022-02-16 09:55:27,593 INFO L205 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-02-16 09:55:27,593 INFO L164 ceAbstractionStarter]: Applying trace abstraction to program that has 2 error locations. [2022-02-16 09:55:27,593 INFO L534 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2022-02-16 09:55:27,624 WARN L322 ript$VariableManager]: TermVariabe Process2Thread1of1ForFork2_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,625 WARN L322 ript$VariableManager]: TermVariabe Process2Thread1of1ForFork2_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,626 WARN L322 ript$VariableManager]: TermVariabe Process2Thread1of1ForFork2_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,626 WARN L322 ript$VariableManager]: TermVariabe Process2Thread1of1ForFork2_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,626 WARN L322 ript$VariableManager]: TermVariabe Process2Thread1of1ForFork2_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,626 WARN L322 ript$VariableManager]: TermVariabe Process2Thread1of1ForFork2_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,627 WARN L322 ript$VariableManager]: TermVariabe Process2Thread1of1ForFork2_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,627 WARN L322 ript$VariableManager]: TermVariabe Process2Thread1of1ForFork2_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,629 WARN L322 ript$VariableManager]: TermVariabe Process1Thread1of1ForFork1_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,629 WARN L322 ript$VariableManager]: TermVariabe Process1Thread1of1ForFork1_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,629 WARN L322 ript$VariableManager]: TermVariabe Process1Thread1of1ForFork1_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,630 WARN L322 ript$VariableManager]: TermVariabe Process1Thread1of1ForFork1_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,630 WARN L322 ript$VariableManager]: TermVariabe Process1Thread1of1ForFork1_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,630 WARN L322 ript$VariableManager]: TermVariabe Process1Thread1of1ForFork1_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,630 WARN L322 ript$VariableManager]: TermVariabe Process1Thread1of1ForFork1_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,631 WARN L322 ript$VariableManager]: TermVariabe Process1Thread1of1ForFork1_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,634 WARN L322 ript$VariableManager]: TermVariabe Process1Thread1of1ForFork1_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,635 WARN L322 ript$VariableManager]: TermVariabe Process2Thread1of1ForFork2_deadline not constructed by VariableManager. Cannot ensure absence of name clashes. [2022-02-16 09:55:27,635 INFO L148 ThreadInstanceAdder]: Constructed 0 joinOtherThreadTransitions. [2022-02-16 09:55:27,662 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 [2022-02-16 09:55:27,663 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-16 09:55:27,668 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (exit command is (exit), workingDir is null) [2022-02-16 09:55:27,670 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Waiting until timeout for monitored process [2022-02-16 09:55:27,696 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-02-16 09:55:27,705 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PARTIAL_ORDER_FA, mLazyFiniteAutomaton=true, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2022-02-16 09:55:27,705 INFO L340 AbstractCegarLoop]: Starting to check reachability of 7 error locations. [2022-02-16 09:55:27,771 INFO L104 alCausalityReduction]: MaximalCausalityReduction evaluated 55 transitions and produced 56 states. [2022-02-16 09:55:27,773 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting Process2Err0ASSERT_VIOLATIONASSERT === [Process2Err0ASSERT_VIOLATIONASSERT, Process1Err0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION (and 3 more)] === [2022-02-16 09:55:27,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-16 09:55:27,780 INFO L85 PathProgramCache]: Analyzing trace with hash 1615810858, now seen corresponding path program 1 times [2022-02-16 09:55:27,786 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-16 09:55:27,786 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926588727] [2022-02-16 09:55:27,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-16 09:55:27,787 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-16 09:55:27,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-16 09:55:27,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-16 09:55:27,885 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-16 09:55:27,885 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [926588727] [2022-02-16 09:55:27,886 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [926588727] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-16 09:55:27,886 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-16 09:55:27,886 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-16 09:55:27,887 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1051704440] [2022-02-16 09:55:27,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-16 09:55:27,893 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2022-02-16 09:55:27,894 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-16 09:55:27,914 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-02-16 09:55:27,915 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-02-16 09:55:27,915 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:27,917 INFO L470 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2022-02-16 09:55:27,917 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-16 09:55:27,917 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:27,936 INFO L104 alCausalityReduction]: MaximalCausalityReduction evaluated 47 transitions and produced 48 states. [2022-02-16 09:55:27,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:27,938 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-02-16 09:55:27,938 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting Process1Err0ASSERT_VIOLATIONASSERT === [Process2Err0ASSERT_VIOLATIONASSERT, Process1Err0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION (and 3 more)] === [2022-02-16 09:55:27,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-16 09:55:27,940 INFO L85 PathProgramCache]: Analyzing trace with hash -716527660, now seen corresponding path program 1 times [2022-02-16 09:55:27,940 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-16 09:55:27,941 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257511533] [2022-02-16 09:55:27,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-16 09:55:27,941 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-16 09:55:27,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-16 09:55:27,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-16 09:55:27,992 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-16 09:55:27,992 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [257511533] [2022-02-16 09:55:27,992 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [257511533] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-16 09:55:27,993 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-16 09:55:27,993 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2022-02-16 09:55:27,993 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [547675821] [2022-02-16 09:55:27,993 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-16 09:55:27,994 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-02-16 09:55:27,994 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-16 09:55:27,994 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-16 09:55:27,994 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-16 09:55:27,994 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:27,995 INFO L470 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2022-02-16 09:55:27,995 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 2 states have (on average 7.5) internal successors, (15), 2 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-16 09:55:27,995 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:27,995 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,093 INFO L104 alCausalityReduction]: MaximalCausalityReduction evaluated 1484 transitions and produced 1450 states. [2022-02-16 09:55:28,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,094 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,094 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-02-16 09:55:28,094 INFO L402 AbstractCegarLoop]: === Iteration 3 === Targeting Process2Err0ASSERT_VIOLATIONASSERT === [Process2Err0ASSERT_VIOLATIONASSERT, Process1Err0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION (and 3 more)] === [2022-02-16 09:55:28,095 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-16 09:55:28,095 INFO L85 PathProgramCache]: Analyzing trace with hash -1509141713, now seen corresponding path program 1 times [2022-02-16 09:55:28,095 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-16 09:55:28,095 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013230281] [2022-02-16 09:55:28,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-16 09:55:28,095 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-16 09:55:28,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-16 09:55:28,254 INFO L134 CoverageAnalysis]: Checked inductivity of 2201 backedges. 99 proven. 0 refuted. 0 times theorem prover too weak. 2102 trivial. 0 not checked. [2022-02-16 09:55:28,254 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-16 09:55:28,254 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2013230281] [2022-02-16 09:55:28,254 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2013230281] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-16 09:55:28,255 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-16 09:55:28,255 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-16 09:55:28,255 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [748842620] [2022-02-16 09:55:28,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-16 09:55:28,255 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-02-16 09:55:28,256 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-16 09:55:28,256 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-16 09:55:28,256 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-16 09:55:28,256 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,256 INFO L470 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2022-02-16 09:55:28,256 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 14.333333333333334) internal successors, (43), 3 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-16 09:55:28,256 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,256 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,257 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,335 INFO L104 alCausalityReduction]: MaximalCausalityReduction evaluated 1542 transitions and produced 1505 states. [2022-02-16 09:55:28,336 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,336 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,337 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,337 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2022-02-16 09:55:28,337 INFO L402 AbstractCegarLoop]: === Iteration 4 === Targeting Process2Err0ASSERT_VIOLATIONASSERT === [Process2Err0ASSERT_VIOLATIONASSERT, Process1Err0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION (and 3 more)] === [2022-02-16 09:55:28,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-16 09:55:28,338 INFO L85 PathProgramCache]: Analyzing trace with hash 730413376, now seen corresponding path program 1 times [2022-02-16 09:55:28,338 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-16 09:55:28,338 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189196667] [2022-02-16 09:55:28,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-16 09:55:28,338 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-16 09:55:28,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-16 09:55:28,420 INFO L134 CoverageAnalysis]: Checked inductivity of 2288 backedges. 66 proven. 0 refuted. 0 times theorem prover too weak. 2222 trivial. 0 not checked. [2022-02-16 09:55:28,420 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-16 09:55:28,421 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189196667] [2022-02-16 09:55:28,421 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1189196667] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-16 09:55:28,421 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-16 09:55:28,421 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-16 09:55:28,421 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1201806690] [2022-02-16 09:55:28,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-16 09:55:28,422 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-02-16 09:55:28,422 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-16 09:55:28,422 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-16 09:55:28,422 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-16 09:55:28,422 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,423 INFO L470 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2022-02-16 09:55:28,423 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-16 09:55:28,423 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,423 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,423 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,423 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,486 INFO L104 alCausalityReduction]: MaximalCausalityReduction evaluated 1742 transitions and produced 1649 states. [2022-02-16 09:55:28,486 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,486 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,487 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,487 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,487 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2022-02-16 09:55:28,488 INFO L402 AbstractCegarLoop]: === Iteration 5 === Targeting Process2Err0ASSERT_VIOLATIONASSERT === [Process2Err0ASSERT_VIOLATIONASSERT, Process1Err0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION (and 3 more)] === [2022-02-16 09:55:28,488 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-16 09:55:28,488 INFO L85 PathProgramCache]: Analyzing trace with hash -862436076, now seen corresponding path program 1 times [2022-02-16 09:55:28,489 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-16 09:55:28,489 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978082720] [2022-02-16 09:55:28,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-16 09:55:28,489 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-16 09:55:28,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-16 09:55:28,598 INFO L134 CoverageAnalysis]: Checked inductivity of 2244 backedges. 1003 proven. 0 refuted. 0 times theorem prover too weak. 1241 trivial. 0 not checked. [2022-02-16 09:55:28,598 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-16 09:55:28,598 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [978082720] [2022-02-16 09:55:28,598 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [978082720] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-16 09:55:28,598 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-16 09:55:28,598 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-16 09:55:28,599 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2125309617] [2022-02-16 09:55:28,599 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-16 09:55:28,599 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-02-16 09:55:28,599 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-16 09:55:28,599 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-16 09:55:28,600 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-16 09:55:28,600 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,600 INFO L470 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2022-02-16 09:55:28,600 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-16 09:55:28,600 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,600 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,600 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,600 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,600 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,698 INFO L104 alCausalityReduction]: MaximalCausalityReduction evaluated 3486 transitions and produced 3357 states. [2022-02-16 09:55:28,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,700 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2022-02-16 09:55:28,700 INFO L402 AbstractCegarLoop]: === Iteration 6 === Targeting Process2Err0ASSERT_VIOLATIONASSERT === [Process2Err0ASSERT_VIOLATIONASSERT, Process1Err0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION (and 3 more)] === [2022-02-16 09:55:28,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-16 09:55:28,701 INFO L85 PathProgramCache]: Analyzing trace with hash 1859957455, now seen corresponding path program 1 times [2022-02-16 09:55:28,701 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-16 09:55:28,701 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1381059606] [2022-02-16 09:55:28,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-16 09:55:28,701 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-16 09:55:28,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-16 09:55:28,910 INFO L134 CoverageAnalysis]: Checked inductivity of 15673 backedges. 63 proven. 0 refuted. 0 times theorem prover too weak. 15610 trivial. 0 not checked. [2022-02-16 09:55:28,910 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-16 09:55:28,910 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1381059606] [2022-02-16 09:55:28,911 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1381059606] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-16 09:55:28,911 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-16 09:55:28,911 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-02-16 09:55:28,911 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1528802792] [2022-02-16 09:55:28,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-16 09:55:28,912 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-02-16 09:55:28,912 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-16 09:55:28,912 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-16 09:55:28,913 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-16 09:55:28,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,913 INFO L470 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2022-02-16 09:55:28,913 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-16 09:55:28,913 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,913 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,913 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,913 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,913 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,913 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,994 INFO L104 alCausalityReduction]: MaximalCausalityReduction evaluated 2638 transitions and produced 2521 states. [2022-02-16 09:55:28,994 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:28,994 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,994 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,994 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,995 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:28,995 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-16 09:55:28,995 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2022-02-16 09:55:28,995 INFO L402 AbstractCegarLoop]: === Iteration 7 === Targeting Process2Err0ASSERT_VIOLATIONASSERT === [Process2Err0ASSERT_VIOLATIONASSERT, Process1Err0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION (and 3 more)] === [2022-02-16 09:55:28,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-16 09:55:28,996 INFO L85 PathProgramCache]: Analyzing trace with hash -810829820, now seen corresponding path program 2 times [2022-02-16 09:55:28,996 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-16 09:55:28,997 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215341251] [2022-02-16 09:55:28,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-16 09:55:28,997 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-16 09:55:29,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-16 09:55:29,082 INFO L134 CoverageAnalysis]: Checked inductivity of 10723 backedges. 306 proven. 0 refuted. 0 times theorem prover too weak. 10417 trivial. 0 not checked. [2022-02-16 09:55:29,082 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-16 09:55:29,082 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1215341251] [2022-02-16 09:55:29,082 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1215341251] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-16 09:55:29,085 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-16 09:55:29,085 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-02-16 09:55:29,085 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [695739309] [2022-02-16 09:55:29,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-16 09:55:29,086 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-02-16 09:55:29,086 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-16 09:55:29,087 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-16 09:55:29,087 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-16 09:55:29,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:29,093 INFO L470 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2022-02-16 09:55:29,093 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 13.0) internal successors, (52), 4 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-16 09:55:29,093 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:29,093 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:29,093 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:29,093 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:29,093 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:29,094 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2022-02-16 09:55:29,094 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:40,143 INFO L104 alCausalityReduction]: MaximalCausalityReduction evaluated 714997 transitions and produced 367093 states. [2022-02-16 09:55:40,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:40,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:40,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:40,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:40,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:40,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-16 09:55:40,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-16 09:55:40,144 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2022-02-16 09:55:40,144 INFO L402 AbstractCegarLoop]: === Iteration 8 === Targeting Process2Err0ASSERT_VIOLATIONASSERT === [Process2Err0ASSERT_VIOLATIONASSERT, Process1Err0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION (and 3 more)] === [2022-02-16 09:55:40,145 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-16 09:55:40,145 INFO L85 PathProgramCache]: Analyzing trace with hash -1536448066, now seen corresponding path program 1 times [2022-02-16 09:55:40,145 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-16 09:55:40,145 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1302262403] [2022-02-16 09:55:40,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-16 09:55:40,145 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-16 09:55:40,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-16 09:55:40,543 INFO L134 CoverageAnalysis]: Checked inductivity of 70036 backedges. 23136 proven. 0 refuted. 0 times theorem prover too weak. 46900 trivial. 0 not checked. [2022-02-16 09:55:40,544 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-16 09:55:40,544 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1302262403] [2022-02-16 09:55:40,544 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1302262403] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-16 09:55:40,544 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-16 09:55:40,544 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-16 09:55:40,544 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [589971019] [2022-02-16 09:55:40,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-16 09:55:40,545 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-02-16 09:55:40,545 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-16 09:55:40,545 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-16 09:55:40,545 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-16 09:55:40,546 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:40,546 INFO L470 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2022-02-16 09:55:40,546 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-16 09:55:40,546 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:40,546 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:40,546 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:40,546 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:40,546 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:40,546 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2022-02-16 09:55:40,546 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2022-02-16 09:55:40,546 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:40,926 INFO L104 alCausalityReduction]: MaximalCausalityReduction evaluated 17521 transitions and produced 11995 states. [2022-02-16 09:55:40,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:40,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:40,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:40,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:40,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:40,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-16 09:55:40,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-16 09:55:40,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:40,928 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2022-02-16 09:55:40,928 INFO L402 AbstractCegarLoop]: === Iteration 9 === Targeting Process2Err0ASSERT_VIOLATIONASSERT === [Process2Err0ASSERT_VIOLATIONASSERT, Process1Err0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION (and 3 more)] === [2022-02-16 09:55:40,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-16 09:55:40,929 INFO L85 PathProgramCache]: Analyzing trace with hash -335129799, now seen corresponding path program 3 times [2022-02-16 09:55:40,929 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-16 09:55:40,929 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [570254620] [2022-02-16 09:55:40,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-16 09:55:40,929 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-16 09:55:41,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-16 09:55:41,490 INFO L134 CoverageAnalysis]: Checked inductivity of 56465 backedges. 6964 proven. 2081 refuted. 0 times theorem prover too weak. 47420 trivial. 0 not checked. [2022-02-16 09:55:41,490 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-16 09:55:41,490 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [570254620] [2022-02-16 09:55:41,490 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [570254620] provided 0 perfect and 1 imperfect interpolant sequences [2022-02-16 09:55:41,490 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1763971676] [2022-02-16 09:55:41,490 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-02-16 09:55:41,491 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-02-16 09:55:41,491 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-16 09:55:41,492 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-02-16 09:55:41,493 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-02-16 09:55:41,615 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2022-02-16 09:55:41,615 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-02-16 09:55:41,618 INFO L263 TraceCheckSpWp]: Trace formula consists of 352 conjuncts, 8 conjunts are in the unsatisfiable core [2022-02-16 09:55:41,646 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-02-16 09:55:44,217 INFO L134 CoverageAnalysis]: Checked inductivity of 56465 backedges. 191 proven. 8879 refuted. 0 times theorem prover too weak. 47395 trivial. 0 not checked. [2022-02-16 09:55:44,217 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-02-16 09:55:49,128 INFO L134 CoverageAnalysis]: Checked inductivity of 56465 backedges. 6801 proven. 2269 refuted. 0 times theorem prover too weak. 47395 trivial. 0 not checked. [2022-02-16 09:55:49,128 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1763971676] provided 0 perfect and 2 imperfect interpolant sequences [2022-02-16 09:55:49,129 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-02-16 09:55:49,129 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 19 [2022-02-16 09:55:49,129 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1980266181] [2022-02-16 09:55:49,129 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-02-16 09:55:49,132 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2022-02-16 09:55:49,132 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-16 09:55:49,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-02-16 09:55:49,132 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=283, Unknown=0, NotChecked=0, Total=342 [2022-02-16 09:55:49,133 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:49,133 INFO L470 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2022-02-16 09:55:49,133 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 19 states have (on average 11.68421052631579) internal successors, (222), 19 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-16 09:55:49,133 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:55:49,133 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:49,133 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:49,133 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:49,133 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:49,133 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2022-02-16 09:55:49,133 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2022-02-16 09:55:49,133 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:55:49,133 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:56:03,636 INFO L104 alCausalityReduction]: MaximalCausalityReduction evaluated 643169 transitions and produced 226118 states. [2022-02-16 09:56:03,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-16 09:56:03,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:56:03,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:56:03,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:56:03,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:56:03,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-16 09:56:03,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-16 09:56:03,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-16 09:56:03,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2022-02-16 09:56:03,654 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-02-16 09:56:03,838 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable8 [2022-02-16 09:56:03,839 INFO L402 AbstractCegarLoop]: === Iteration 10 === Targeting Process2Err0ASSERT_VIOLATIONASSERT === [Process2Err0ASSERT_VIOLATIONASSERT, Process1Err0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION (and 3 more)] === [2022-02-16 09:56:03,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-16 09:56:03,839 INFO L85 PathProgramCache]: Analyzing trace with hash 256353287, now seen corresponding path program 4 times [2022-02-16 09:56:03,839 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-16 09:56:03,840 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520458353] [2022-02-16 09:56:03,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-16 09:56:03,842 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-16 09:56:04,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-16 09:56:04,008 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-16 09:56:04,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-16 09:56:04,289 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-16 09:56:04,289 INFO L628 BasicCegarLoop]: Counterexample is feasible [2022-02-16 09:56:04,290 INFO L764 garLoopResultBuilder]: Registering result UNSAFE for location Process2Err0ASSERT_VIOLATIONASSERT (6 of 7 remaining) [2022-02-16 09:56:04,291 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location Process2Err0ASSERT_VIOLATIONASSERT (5 of 7 remaining) [2022-02-16 09:56:04,291 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location Process1Err0ASSERT_VIOLATIONASSERT (4 of 7 remaining) [2022-02-16 09:56:04,291 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr0INUSE_VIOLATION (3 of 7 remaining) [2022-02-16 09:56:04,291 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr1INUSE_VIOLATION (2 of 7 remaining) [2022-02-16 09:56:04,291 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr2INUSE_VIOLATION (1 of 7 remaining) [2022-02-16 09:56:04,291 INFO L764 garLoopResultBuilder]: Registering result UNKNOWN for location Process1Err0ASSERT_VIOLATIONASSERT (0 of 7 remaining) [2022-02-16 09:56:04,291 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2022-02-16 09:56:04,302 INFO L732 BasicCegarLoop]: Path program histogram: [4, 1, 1, 1, 1, 1, 1] [2022-02-16 09:56:04,307 INFO L230 ceAbstractionStarter]: Analysis of concurrent program completed with 1 thread instances [2022-02-16 09:56:04,307 INFO L180 ceAbstractionStarter]: Computing trace abstraction results [2022-02-16 09:56:04,393 INFO L202 PluginConnector]: Adding new model FischerWithBug.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 16.02 09:56:04 BasicIcfg [2022-02-16 09:56:04,393 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-02-16 09:56:04,393 INFO L158 Benchmark]: Toolchain (without parser) took 37081.52ms. Allocated memory was 195.0MB in the beginning and 6.6GB in the end (delta: 6.4GB). Free memory was 160.1MB in the beginning and 4.9GB in the end (delta: -4.7GB). Peak memory consumption was 1.6GB. Max. memory is 8.0GB. [2022-02-16 09:56:04,393 INFO L158 Benchmark]: Boogie PL CUP Parser took 0.09ms. Allocated memory is still 195.0MB. Free memory is still 161.1MB. There was no memory consumed. Max. memory is 8.0GB. [2022-02-16 09:56:04,394 INFO L158 Benchmark]: Boogie Procedure Inliner took 16.91ms. Allocated memory is still 195.0MB. Free memory was 159.9MB in the beginning and 158.4MB in the end (delta: 1.5MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. [2022-02-16 09:56:04,394 INFO L158 Benchmark]: Boogie Preprocessor took 10.55ms. Allocated memory is still 195.0MB. Free memory was 158.4MB in the beginning and 157.4MB in the end (delta: 998.7kB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. [2022-02-16 09:56:04,394 INFO L158 Benchmark]: RCFGBuilder took 220.55ms. Allocated memory is still 195.0MB. Free memory was 157.4MB in the beginning and 148.0MB in the end (delta: 9.3MB). Peak memory consumption was 9.4MB. Max. memory is 8.0GB. [2022-02-16 09:56:04,395 INFO L158 Benchmark]: TraceAbstraction took 36827.52ms. Allocated memory was 195.0MB in the beginning and 6.6GB in the end (delta: 6.4GB). Free memory was 147.6MB in the beginning and 4.9GB in the end (delta: -4.8GB). Peak memory consumption was 1.6GB. Max. memory is 8.0GB. [2022-02-16 09:56:04,396 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.09ms. Allocated memory is still 195.0MB. Free memory is still 161.1MB. There was no memory consumed. Max. memory is 8.0GB. * Boogie Procedure Inliner took 16.91ms. Allocated memory is still 195.0MB. Free memory was 159.9MB in the beginning and 158.4MB in the end (delta: 1.5MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. * Boogie Preprocessor took 10.55ms. Allocated memory is still 195.0MB. Free memory was 158.4MB in the beginning and 157.4MB in the end (delta: 998.7kB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. * RCFGBuilder took 220.55ms. Allocated memory is still 195.0MB. Free memory was 157.4MB in the beginning and 148.0MB in the end (delta: 9.3MB). Peak memory consumption was 9.4MB. Max. memory is 8.0GB. * TraceAbstraction took 36827.52ms. Allocated memory was 195.0MB in the beginning and 6.6GB in the end (delta: 6.4GB). Free memory was 147.6MB in the beginning and 4.9GB in the end (delta: -4.8GB). Peak memory consumption was 1.6GB. Max. memory is 8.0GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Independence relation benchmarks ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 0, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 0, negative conditional: 0, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: ConditionTransformingIndependenceRelation.Independence Queries: [ total: 0, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 0, negative conditional: 0, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ConditionTransformingIndependenceRelation.Statistics on underlying relation: DisjunctiveConditionalIndependenceRelation.Independence Queries: [ total: 0, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 0, negative conditional: 0, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , DisjunctiveConditionalIndependenceRelation.Statistics on underlying relation: ConditionTransformingIndependenceRelation.Independence Queries: [ total: 0, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 0, negative conditional: 0, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ConditionTransformingIndependenceRelation.Statistics on underlying relation: SemanticConditionEliminator.Independence Queries: [ total: 0, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 0, negative conditional: 0, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , SemanticConditionEliminator.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 0, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 0, negative conditional: 0, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: UnionIndependenceRelation.Independence Queries: [ total: 0, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 0, negative conditional: 0, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , UnionIndependenceRelation.Statistics on underlying relations: [ SyntacticIndependenceRelation.Independence Queries: [ total: 0, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 0, negative conditional: 0, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , SemanticIndependenceRelation.Independence Queries: [ total: 0, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 0, negative conditional: 0, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , SemanticIndependenceRelation.Query Time [ms]: [ total: 0, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 0, negative conditional: 0, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] ], Cache Queries: [ total: 0, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 0, negative conditional: 0, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Statistics on independence cache: Total cache size (in pairs): 0, Positive cache size: 0, Positive conditional cache size: 0, Positive unconditional cache size: 0, Negative cache size: 0, Negative conditional cache size: 0, Negative unconditional cache size: 0, Eliminated conditions: 0, Maximal queried relation: -1, Independence queries for same thread: 0 - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 87]: assertion can be violated assertion can be violated We found a FailurePath: [L28] 0 critical := 0; VAL [critical=0] [L29] 0 clk := 0; VAL [clk=0, critical=0] [L30] 0 assume wait >= 1; VAL [clk=0, critical=0, wait=1] [L33] 0 assume wait >= delay; VAL [clk=0, critical=0, delay=1, wait=1] [L34] FORK 0 fork 0 Clock(); VAL [clk=0, critical=0, delay=1, wait=1] [L35] FORK 0 fork 1 Process1(); VAL [clk=0, critical=0, delay=1, wait=1] [L57] COND TRUE 2 lock != 1 VAL [clk=0, critical=0, delay=1, lock=0, wait=1] [L58] 2 deadline := clk + delay; VAL [clk=0, critical=0, deadline=1, delay=1, lock=0, wait=1] [L59] 2 assume lock == 0; VAL [clk=0, critical=0, deadline=1, delay=1, lock=0, wait=1] [L60] 2 lock := 1; VAL [clk=0, critical=0, deadline=1, delay=1, lock=1, wait=1] [L61] 2 assume clk <= deadline; VAL [clk=0, critical=0, deadline=1, delay=1, lock=1, wait=1] [L62] 2 deadline := clk + wait; VAL [clk=0, critical=0, deadline=1, delay=1, lock=1, wait=1] [L36] FORK 0 fork 2 Process2(); VAL [clk=0, critical=0, deadline=1, delay=1, lock=1, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=0, critical=0, deadline=1, delay=1, lock=1, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=0, critical=0, deadline=1, deadline=1, delay=1, lock=1, wait=1] [L44] 1 clk := clk + 1; VAL [clk=1, critical=0, deadline=1, deadline=1, delay=1, lock=1, wait=1] [L63] 2 assume clk >= deadline; VAL [clk=1, critical=0, deadline=1, deadline=1, delay=1, lock=1, wait=1] [L64] 2 assume lock == 1; VAL [clk=1, critical=0, deadline=1, deadline=1, delay=1, lock=1, wait=1] [L66] 2 assert critical == 0; VAL [clk=1, critical=0, deadline=1, deadline=1, delay=1, lock=1, wait=1] [L67] 2 critical := 1; VAL [clk=1, critical=1, deadline=1, deadline=1, delay=1, lock=1, wait=1] [L68] 2 critical := 0; VAL [clk=1, critical=0, deadline=1, deadline=1, delay=1, lock=1, wait=1] [L69] 2 lock := 0; VAL [clk=1, critical=0, deadline=1, deadline=1, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=1, critical=0, deadline=1, deadline=1, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=1, critical=0, deadline=1, deadline=1, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=1, critical=0, deadline=1, deadline=1, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=1, critical=0, deadline=2, deadline=1, delay=1, lock=2, wait=1] [L57] COND TRUE 2 lock != 1 VAL [clk=1, critical=0, deadline=2, deadline=1, delay=1, lock=2, wait=1] [L58] 2 deadline := clk + delay; VAL [clk=1, critical=0, deadline=2, deadline=2, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=2, critical=0, deadline=2, deadline=2, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=2, critical=0, deadline=2, deadline=2, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=2, critical=0, deadline=2, deadline=2, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=2, critical=0, deadline=2, deadline=2, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=2, critical=2, deadline=2, deadline=2, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=2, critical=0, deadline=2, deadline=2, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=2, critical=0, deadline=2, deadline=2, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=2, critical=0, deadline=2, deadline=2, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=2, critical=0, deadline=3, deadline=2, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=2, critical=0, deadline=3, deadline=2, delay=1, lock=0, wait=1] [L59] 2 assume lock == 0; VAL [clk=2, critical=0, deadline=3, deadline=2, delay=1, lock=0, wait=1] [L60] 2 lock := 1; VAL [clk=2, critical=0, deadline=3, deadline=2, delay=1, lock=1, wait=1] [L61] 2 assume clk <= deadline; VAL [clk=2, critical=0, deadline=3, deadline=2, delay=1, lock=1, wait=1] [L62] 2 deadline := clk + wait; VAL [clk=2, critical=0, deadline=3, deadline=3, delay=1, lock=1, wait=1] [L44] 1 clk := clk + 1; VAL [clk=3, critical=0, deadline=3, deadline=3, delay=1, lock=1, wait=1] [L63] 2 assume clk >= deadline; VAL [clk=3, critical=0, deadline=3, deadline=3, delay=1, lock=1, wait=1] [L64] 2 assume lock == 1; VAL [clk=3, critical=0, deadline=3, deadline=3, delay=1, lock=1, wait=1] [L81] 3 lock := 2; VAL [clk=3, critical=0, deadline=3, deadline=3, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=3, critical=0, deadline=3, deadline=3, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=3, critical=0, deadline=4, deadline=3, delay=1, lock=2, wait=1] [L66] 2 assert critical == 0; VAL [clk=3, critical=0, deadline=4, deadline=3, delay=1, lock=2, wait=1] [L67] 2 critical := 1; VAL [clk=3, critical=1, deadline=4, deadline=3, delay=1, lock=2, wait=1] [L68] 2 critical := 0; VAL [clk=3, critical=0, deadline=4, deadline=3, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=4, critical=0, deadline=4, deadline=3, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=4, critical=0, deadline=4, deadline=3, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=4, critical=0, deadline=4, deadline=3, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=4, critical=0, deadline=4, deadline=3, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=4, critical=2, deadline=4, deadline=3, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=4, critical=0, deadline=4, deadline=3, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=4, critical=0, deadline=4, deadline=3, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=4, critical=0, deadline=4, deadline=3, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=4, critical=0, deadline=5, deadline=3, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=4, critical=0, deadline=5, deadline=3, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=4, critical=0, deadline=5, deadline=3, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=4, critical=0, deadline=5, deadline=3, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=4, critical=0, deadline=5, deadline=3, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=5, critical=0, deadline=5, deadline=3, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=5, critical=0, deadline=5, deadline=3, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=5, critical=0, deadline=5, deadline=3, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=5, critical=0, deadline=5, deadline=3, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=5, critical=2, deadline=5, deadline=3, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=5, critical=0, deadline=5, deadline=3, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=5, critical=0, deadline=5, deadline=3, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=5, critical=0, deadline=5, deadline=3, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=5, critical=0, deadline=6, deadline=3, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=5, critical=0, deadline=6, deadline=3, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=5, critical=0, deadline=6, deadline=3, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=5, critical=0, deadline=6, deadline=3, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=5, critical=0, deadline=6, deadline=3, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=6, critical=0, deadline=6, deadline=3, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=6, critical=0, deadline=6, deadline=3, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=6, critical=0, deadline=6, deadline=3, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=6, critical=0, deadline=6, deadline=3, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=6, critical=2, deadline=6, deadline=3, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=6, critical=0, deadline=6, deadline=3, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=6, critical=0, deadline=6, deadline=3, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=6, critical=0, deadline=6, deadline=3, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=6, critical=0, deadline=7, deadline=3, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=6, critical=0, deadline=7, deadline=3, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=6, critical=0, deadline=7, deadline=3, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=6, critical=0, deadline=7, deadline=3, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=6, critical=0, deadline=7, deadline=3, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=7, critical=0, deadline=7, deadline=3, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=7, critical=0, deadline=7, deadline=3, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=7, critical=0, deadline=7, deadline=3, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=7, critical=0, deadline=7, deadline=3, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=7, critical=2, deadline=7, deadline=3, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=7, critical=0, deadline=7, deadline=3, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=7, critical=0, deadline=7, deadline=3, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=7, critical=0, deadline=7, deadline=3, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=7, critical=0, deadline=8, deadline=3, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=7, critical=0, deadline=8, deadline=3, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=7, critical=0, deadline=8, deadline=3, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=7, critical=0, deadline=8, deadline=3, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=7, critical=0, deadline=8, deadline=3, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=8, critical=0, deadline=8, deadline=3, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=8, critical=0, deadline=8, deadline=3, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=8, critical=0, deadline=8, deadline=3, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=8, critical=0, deadline=8, deadline=3, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=8, critical=2, deadline=8, deadline=3, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=8, critical=0, deadline=8, deadline=3, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=8, critical=0, deadline=8, deadline=3, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=8, critical=0, deadline=8, deadline=3, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=8, critical=0, deadline=9, deadline=3, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=8, critical=0, deadline=9, deadline=3, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=8, critical=0, deadline=9, deadline=3, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=8, critical=0, deadline=9, deadline=3, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=8, critical=0, deadline=9, deadline=3, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=9, critical=0, deadline=9, deadline=3, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=9, critical=0, deadline=9, deadline=3, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=9, critical=0, deadline=9, deadline=3, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=9, critical=0, deadline=9, deadline=3, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=9, critical=2, deadline=9, deadline=3, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=9, critical=0, deadline=9, deadline=3, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=9, critical=0, deadline=9, deadline=3, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=9, critical=0, deadline=9, deadline=3, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=9, critical=0, deadline=10, deadline=3, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=9, critical=0, deadline=10, deadline=3, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=9, critical=0, deadline=10, deadline=3, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=9, critical=0, deadline=10, deadline=3, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=9, critical=0, deadline=10, deadline=3, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=10, critical=0, deadline=10, deadline=3, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=10, critical=0, deadline=10, deadline=3, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=10, critical=0, deadline=10, deadline=3, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=10, critical=0, deadline=10, deadline=3, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=10, critical=2, deadline=10, deadline=3, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=10, critical=0, deadline=10, deadline=3, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=10, critical=0, deadline=10, deadline=3, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=10, critical=0, deadline=10, deadline=3, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=10, critical=0, deadline=11, deadline=3, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=10, critical=0, deadline=11, deadline=3, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=10, critical=0, deadline=11, deadline=3, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=10, critical=0, deadline=11, deadline=3, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=10, critical=0, deadline=11, deadline=3, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=11, critical=0, deadline=11, deadline=3, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=11, critical=0, deadline=11, deadline=3, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=11, critical=0, deadline=11, deadline=3, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=11, critical=0, deadline=11, deadline=3, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=11, critical=2, deadline=11, deadline=3, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=11, critical=0, deadline=11, deadline=3, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=11, critical=0, deadline=11, deadline=3, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=11, critical=0, deadline=11, deadline=3, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=11, critical=0, deadline=12, deadline=3, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=11, critical=0, deadline=12, deadline=3, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=11, critical=0, deadline=12, deadline=3, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=11, critical=0, deadline=12, deadline=3, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=11, critical=0, deadline=12, deadline=3, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=12, critical=0, deadline=12, deadline=3, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=12, critical=0, deadline=12, deadline=3, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=12, critical=0, deadline=12, deadline=3, delay=1, lock=2, wait=1] [L69] 2 lock := 0; VAL [clk=12, critical=0, deadline=12, deadline=3, delay=1, lock=0, wait=1] [L57] COND TRUE 2 lock != 1 VAL [clk=12, critical=0, deadline=12, deadline=3, delay=1, lock=0, wait=1] [L58] 2 deadline := clk + delay; VAL [clk=12, critical=0, deadline=12, deadline=13, delay=1, lock=0, wait=1] [L59] 2 assume lock == 0; VAL [clk=12, critical=0, deadline=12, deadline=13, delay=1, lock=0, wait=1] [L60] 2 lock := 1; VAL [clk=12, critical=0, deadline=12, deadline=13, delay=1, lock=1, wait=1] [L61] 2 assume clk <= deadline; VAL [clk=12, critical=0, deadline=12, deadline=13, delay=1, lock=1, wait=1] [L62] 2 deadline := clk + wait; VAL [clk=12, critical=0, deadline=12, deadline=13, delay=1, lock=1, wait=1] [L44] 1 clk := clk + 1; VAL [clk=13, critical=0, deadline=12, deadline=13, delay=1, lock=1, wait=1] [L63] 2 assume clk >= deadline; VAL [clk=13, critical=0, deadline=12, deadline=13, delay=1, lock=1, wait=1] [L64] 2 assume lock == 1; VAL [clk=13, critical=0, deadline=12, deadline=13, delay=1, lock=1, wait=1] [L66] 2 assert critical == 0; VAL [clk=13, critical=0, deadline=12, deadline=13, delay=1, lock=1, wait=1] [L87] 3 assert critical == 0; VAL [clk=13, critical=0, deadline=12, deadline=13, delay=1, lock=1, wait=1] [L88] 3 critical := 2; VAL [clk=13, critical=2, deadline=12, deadline=13, delay=1, lock=1, wait=1] [L89] 3 critical := 0; VAL [clk=13, critical=0, deadline=12, deadline=13, delay=1, lock=1, wait=1] [L90] 3 lock := 0; VAL [clk=13, critical=0, deadline=12, deadline=13, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=13, critical=0, deadline=12, deadline=13, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=13, critical=0, deadline=14, deadline=13, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=13, critical=0, deadline=14, deadline=13, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=13, critical=0, deadline=14, deadline=13, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=13, critical=0, deadline=14, deadline=13, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=13, critical=0, deadline=14, deadline=13, delay=1, lock=2, wait=1] [L67] 2 critical := 1; VAL [clk=13, critical=1, deadline=14, deadline=13, delay=1, lock=2, wait=1] [L68] 2 critical := 0; VAL [clk=13, critical=0, deadline=14, deadline=13, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=14, critical=0, deadline=14, deadline=13, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=14, critical=0, deadline=14, deadline=13, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=14, critical=0, deadline=14, deadline=13, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=14, critical=0, deadline=14, deadline=13, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=14, critical=2, deadline=14, deadline=13, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=14, critical=0, deadline=14, deadline=13, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=14, critical=0, deadline=14, deadline=13, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=14, critical=0, deadline=14, deadline=13, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=14, critical=0, deadline=15, deadline=13, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=14, critical=0, deadline=15, deadline=13, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=14, critical=0, deadline=15, deadline=13, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=14, critical=0, deadline=15, deadline=13, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=14, critical=0, deadline=15, deadline=13, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=15, critical=0, deadline=15, deadline=13, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=15, critical=0, deadline=15, deadline=13, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=15, critical=0, deadline=15, deadline=13, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=15, critical=0, deadline=15, deadline=13, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=15, critical=2, deadline=15, deadline=13, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=15, critical=0, deadline=15, deadline=13, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=15, critical=0, deadline=15, deadline=13, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=15, critical=0, deadline=15, deadline=13, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=15, critical=0, deadline=16, deadline=13, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=15, critical=0, deadline=16, deadline=13, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=15, critical=0, deadline=16, deadline=13, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=15, critical=0, deadline=16, deadline=13, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=15, critical=0, deadline=16, deadline=13, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=16, critical=0, deadline=16, deadline=13, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=16, critical=0, deadline=16, deadline=13, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=16, critical=0, deadline=16, deadline=13, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=16, critical=0, deadline=16, deadline=13, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=16, critical=2, deadline=16, deadline=13, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=16, critical=0, deadline=16, deadline=13, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=16, critical=0, deadline=16, deadline=13, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=16, critical=0, deadline=16, deadline=13, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=16, critical=0, deadline=17, deadline=13, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=16, critical=0, deadline=17, deadline=13, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=16, critical=0, deadline=17, deadline=13, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=16, critical=0, deadline=17, deadline=13, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=16, critical=0, deadline=17, deadline=13, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=17, critical=0, deadline=17, deadline=13, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=17, critical=0, deadline=17, deadline=13, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=17, critical=0, deadline=17, deadline=13, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=17, critical=0, deadline=17, deadline=13, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=17, critical=2, deadline=17, deadline=13, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=17, critical=0, deadline=17, deadline=13, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=17, critical=0, deadline=17, deadline=13, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=17, critical=0, deadline=17, deadline=13, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=17, critical=0, deadline=18, deadline=13, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=17, critical=0, deadline=18, deadline=13, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=17, critical=0, deadline=18, deadline=13, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=17, critical=0, deadline=18, deadline=13, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=17, critical=0, deadline=18, deadline=13, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=18, critical=0, deadline=18, deadline=13, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=18, critical=0, deadline=18, deadline=13, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=18, critical=0, deadline=18, deadline=13, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=18, critical=0, deadline=18, deadline=13, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=18, critical=2, deadline=18, deadline=13, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=18, critical=0, deadline=18, deadline=13, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=18, critical=0, deadline=18, deadline=13, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=18, critical=0, deadline=18, deadline=13, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=18, critical=0, deadline=19, deadline=13, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=18, critical=0, deadline=19, deadline=13, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=18, critical=0, deadline=19, deadline=13, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=18, critical=0, deadline=19, deadline=13, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=18, critical=0, deadline=19, deadline=13, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=19, critical=0, deadline=19, deadline=13, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=19, critical=0, deadline=19, deadline=13, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=19, critical=0, deadline=19, deadline=13, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=19, critical=0, deadline=19, deadline=13, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=19, critical=2, deadline=19, deadline=13, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=19, critical=0, deadline=19, deadline=13, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=19, critical=0, deadline=19, deadline=13, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=19, critical=0, deadline=19, deadline=13, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=19, critical=0, deadline=20, deadline=13, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=19, critical=0, deadline=20, deadline=13, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=19, critical=0, deadline=20, deadline=13, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=19, critical=0, deadline=20, deadline=13, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=19, critical=0, deadline=20, deadline=13, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=20, critical=0, deadline=20, deadline=13, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=20, critical=0, deadline=20, deadline=13, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=20, critical=0, deadline=20, deadline=13, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=20, critical=0, deadline=20, deadline=13, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=20, critical=2, deadline=20, deadline=13, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=20, critical=0, deadline=20, deadline=13, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=20, critical=0, deadline=20, deadline=13, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=20, critical=0, deadline=20, deadline=13, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=20, critical=0, deadline=21, deadline=13, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=20, critical=0, deadline=21, deadline=13, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=20, critical=0, deadline=21, deadline=13, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=20, critical=0, deadline=21, deadline=13, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=20, critical=0, deadline=21, deadline=13, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=21, critical=0, deadline=21, deadline=13, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=21, critical=0, deadline=21, deadline=13, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=21, critical=0, deadline=21, deadline=13, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=21, critical=0, deadline=21, deadline=13, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=21, critical=2, deadline=21, deadline=13, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=21, critical=0, deadline=21, deadline=13, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=21, critical=0, deadline=21, deadline=13, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=21, critical=0, deadline=21, deadline=13, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=21, critical=0, deadline=22, deadline=13, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=21, critical=0, deadline=22, deadline=13, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=21, critical=0, deadline=22, deadline=13, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=21, critical=0, deadline=22, deadline=13, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=21, critical=0, deadline=22, deadline=13, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=22, critical=0, deadline=22, deadline=13, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=22, critical=0, deadline=22, deadline=13, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=22, critical=0, deadline=22, deadline=13, delay=1, lock=2, wait=1] [L69] 2 lock := 0; VAL [clk=22, critical=0, deadline=22, deadline=13, delay=1, lock=0, wait=1] [L57] COND TRUE 2 lock != 1 VAL [clk=22, critical=0, deadline=22, deadline=13, delay=1, lock=0, wait=1] [L58] 2 deadline := clk + delay; VAL [clk=22, critical=0, deadline=22, deadline=23, delay=1, lock=0, wait=1] [L59] 2 assume lock == 0; VAL [clk=22, critical=0, deadline=22, deadline=23, delay=1, lock=0, wait=1] [L60] 2 lock := 1; VAL [clk=22, critical=0, deadline=22, deadline=23, delay=1, lock=1, wait=1] [L61] 2 assume clk <= deadline; VAL [clk=22, critical=0, deadline=22, deadline=23, delay=1, lock=1, wait=1] [L62] 2 deadline := clk + wait; VAL [clk=22, critical=0, deadline=22, deadline=23, delay=1, lock=1, wait=1] [L44] 1 clk := clk + 1; VAL [clk=23, critical=0, deadline=22, deadline=23, delay=1, lock=1, wait=1] [L63] 2 assume clk >= deadline; VAL [clk=23, critical=0, deadline=22, deadline=23, delay=1, lock=1, wait=1] [L64] 2 assume lock == 1; VAL [clk=23, critical=0, deadline=22, deadline=23, delay=1, lock=1, wait=1] [L66] 2 assert critical == 0; VAL [clk=23, critical=0, deadline=22, deadline=23, delay=1, lock=1, wait=1] [L87] 3 assert critical == 0; VAL [clk=23, critical=0, deadline=22, deadline=23, delay=1, lock=1, wait=1] [L88] 3 critical := 2; VAL [clk=23, critical=2, deadline=22, deadline=23, delay=1, lock=1, wait=1] [L89] 3 critical := 0; VAL [clk=23, critical=0, deadline=22, deadline=23, delay=1, lock=1, wait=1] [L90] 3 lock := 0; VAL [clk=23, critical=0, deadline=22, deadline=23, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=23, critical=0, deadline=22, deadline=23, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=23, critical=0, deadline=24, deadline=23, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=23, critical=0, deadline=24, deadline=23, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=23, critical=0, deadline=24, deadline=23, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=23, critical=0, deadline=24, deadline=23, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=23, critical=0, deadline=24, deadline=23, delay=1, lock=2, wait=1] [L67] 2 critical := 1; VAL [clk=23, critical=1, deadline=24, deadline=23, delay=1, lock=2, wait=1] [L68] 2 critical := 0; VAL [clk=23, critical=0, deadline=24, deadline=23, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=24, critical=0, deadline=24, deadline=23, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=24, critical=0, deadline=24, deadline=23, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=24, critical=0, deadline=24, deadline=23, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=24, critical=0, deadline=24, deadline=23, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=24, critical=2, deadline=24, deadline=23, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=24, critical=0, deadline=24, deadline=23, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=24, critical=0, deadline=24, deadline=23, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=24, critical=0, deadline=24, deadline=23, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=24, critical=0, deadline=25, deadline=23, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=24, critical=0, deadline=25, deadline=23, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=24, critical=0, deadline=25, deadline=23, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=24, critical=0, deadline=25, deadline=23, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=24, critical=0, deadline=25, deadline=23, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=25, critical=0, deadline=25, deadline=23, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=25, critical=0, deadline=25, deadline=23, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=25, critical=0, deadline=25, deadline=23, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=25, critical=0, deadline=25, deadline=23, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=25, critical=2, deadline=25, deadline=23, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=25, critical=0, deadline=25, deadline=23, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=25, critical=0, deadline=25, deadline=23, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=25, critical=0, deadline=25, deadline=23, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=25, critical=0, deadline=26, deadline=23, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=25, critical=0, deadline=26, deadline=23, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=25, critical=0, deadline=26, deadline=23, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=25, critical=0, deadline=26, deadline=23, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=25, critical=0, deadline=26, deadline=23, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=26, critical=0, deadline=26, deadline=23, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=26, critical=0, deadline=26, deadline=23, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=26, critical=0, deadline=26, deadline=23, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=26, critical=0, deadline=26, deadline=23, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=26, critical=2, deadline=26, deadline=23, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=26, critical=0, deadline=26, deadline=23, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=26, critical=0, deadline=26, deadline=23, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=26, critical=0, deadline=26, deadline=23, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=26, critical=0, deadline=27, deadline=23, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=26, critical=0, deadline=27, deadline=23, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=26, critical=0, deadline=27, deadline=23, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=26, critical=0, deadline=27, deadline=23, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=26, critical=0, deadline=27, deadline=23, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=27, critical=0, deadline=27, deadline=23, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=27, critical=0, deadline=27, deadline=23, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=27, critical=0, deadline=27, deadline=23, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=27, critical=0, deadline=27, deadline=23, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=27, critical=2, deadline=27, deadline=23, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=27, critical=0, deadline=27, deadline=23, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=27, critical=0, deadline=27, deadline=23, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=27, critical=0, deadline=27, deadline=23, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=27, critical=0, deadline=28, deadline=23, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=27, critical=0, deadline=28, deadline=23, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=27, critical=0, deadline=28, deadline=23, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=27, critical=0, deadline=28, deadline=23, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=27, critical=0, deadline=28, deadline=23, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=28, critical=0, deadline=28, deadline=23, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=28, critical=0, deadline=28, deadline=23, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=28, critical=0, deadline=28, deadline=23, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=28, critical=0, deadline=28, deadline=23, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=28, critical=2, deadline=28, deadline=23, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=28, critical=0, deadline=28, deadline=23, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=28, critical=0, deadline=28, deadline=23, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=28, critical=0, deadline=28, deadline=23, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=28, critical=0, deadline=29, deadline=23, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=28, critical=0, deadline=29, deadline=23, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=28, critical=0, deadline=29, deadline=23, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=28, critical=0, deadline=29, deadline=23, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=28, critical=0, deadline=29, deadline=23, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=29, critical=0, deadline=29, deadline=23, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=29, critical=0, deadline=29, deadline=23, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=29, critical=0, deadline=29, deadline=23, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=29, critical=0, deadline=29, deadline=23, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=29, critical=2, deadline=29, deadline=23, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=29, critical=0, deadline=29, deadline=23, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=29, critical=0, deadline=29, deadline=23, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=29, critical=0, deadline=29, deadline=23, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=29, critical=0, deadline=30, deadline=23, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=29, critical=0, deadline=30, deadline=23, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=29, critical=0, deadline=30, deadline=23, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=29, critical=0, deadline=30, deadline=23, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=29, critical=0, deadline=30, deadline=23, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=30, critical=0, deadline=30, deadline=23, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=30, critical=0, deadline=30, deadline=23, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=30, critical=0, deadline=30, deadline=23, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=30, critical=0, deadline=30, deadline=23, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=30, critical=2, deadline=30, deadline=23, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=30, critical=0, deadline=30, deadline=23, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=30, critical=0, deadline=30, deadline=23, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=30, critical=0, deadline=30, deadline=23, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=30, critical=0, deadline=31, deadline=23, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=30, critical=0, deadline=31, deadline=23, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=30, critical=0, deadline=31, deadline=23, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=30, critical=0, deadline=31, deadline=23, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=30, critical=0, deadline=31, deadline=23, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=31, critical=0, deadline=31, deadline=23, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=31, critical=0, deadline=31, deadline=23, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=31, critical=0, deadline=31, deadline=23, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=31, critical=0, deadline=31, deadline=23, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=31, critical=2, deadline=31, deadline=23, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=31, critical=0, deadline=31, deadline=23, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=31, critical=0, deadline=31, deadline=23, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=31, critical=0, deadline=31, deadline=23, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=31, critical=0, deadline=32, deadline=23, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=31, critical=0, deadline=32, deadline=23, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=31, critical=0, deadline=32, deadline=23, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=31, critical=0, deadline=32, deadline=23, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=31, critical=0, deadline=32, deadline=23, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=32, critical=0, deadline=32, deadline=23, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=32, critical=0, deadline=32, deadline=23, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=32, critical=0, deadline=32, deadline=23, delay=1, lock=2, wait=1] [L69] 2 lock := 0; VAL [clk=32, critical=0, deadline=32, deadline=23, delay=1, lock=0, wait=1] [L57] COND TRUE 2 lock != 1 VAL [clk=32, critical=0, deadline=32, deadline=23, delay=1, lock=0, wait=1] [L58] 2 deadline := clk + delay; VAL [clk=32, critical=0, deadline=32, deadline=33, delay=1, lock=0, wait=1] [L59] 2 assume lock == 0; VAL [clk=32, critical=0, deadline=32, deadline=33, delay=1, lock=0, wait=1] [L60] 2 lock := 1; VAL [clk=32, critical=0, deadline=32, deadline=33, delay=1, lock=1, wait=1] [L61] 2 assume clk <= deadline; VAL [clk=32, critical=0, deadline=32, deadline=33, delay=1, lock=1, wait=1] [L62] 2 deadline := clk + wait; VAL [clk=32, critical=0, deadline=32, deadline=33, delay=1, lock=1, wait=1] [L44] 1 clk := clk + 1; VAL [clk=33, critical=0, deadline=32, deadline=33, delay=1, lock=1, wait=1] [L63] 2 assume clk >= deadline; VAL [clk=33, critical=0, deadline=32, deadline=33, delay=1, lock=1, wait=1] [L64] 2 assume lock == 1; VAL [clk=33, critical=0, deadline=32, deadline=33, delay=1, lock=1, wait=1] [L66] 2 assert critical == 0; VAL [clk=33, critical=0, deadline=32, deadline=33, delay=1, lock=1, wait=1] [L87] 3 assert critical == 0; VAL [clk=33, critical=0, deadline=32, deadline=33, delay=1, lock=1, wait=1] [L88] 3 critical := 2; VAL [clk=33, critical=2, deadline=32, deadline=33, delay=1, lock=1, wait=1] [L89] 3 critical := 0; VAL [clk=33, critical=0, deadline=32, deadline=33, delay=1, lock=1, wait=1] [L90] 3 lock := 0; VAL [clk=33, critical=0, deadline=32, deadline=33, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=33, critical=0, deadline=32, deadline=33, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=33, critical=0, deadline=34, deadline=33, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=33, critical=0, deadline=34, deadline=33, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=33, critical=0, deadline=34, deadline=33, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=33, critical=0, deadline=34, deadline=33, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=33, critical=0, deadline=34, deadline=33, delay=1, lock=2, wait=1] [L67] 2 critical := 1; VAL [clk=33, critical=1, deadline=34, deadline=33, delay=1, lock=2, wait=1] [L68] 2 critical := 0; VAL [clk=33, critical=0, deadline=34, deadline=33, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=34, critical=0, deadline=34, deadline=33, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=34, critical=0, deadline=34, deadline=33, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=34, critical=0, deadline=34, deadline=33, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=34, critical=0, deadline=34, deadline=33, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=34, critical=2, deadline=34, deadline=33, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=34, critical=0, deadline=34, deadline=33, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=34, critical=0, deadline=34, deadline=33, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=34, critical=0, deadline=34, deadline=33, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=34, critical=0, deadline=35, deadline=33, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=34, critical=0, deadline=35, deadline=33, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=34, critical=0, deadline=35, deadline=33, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=34, critical=0, deadline=35, deadline=33, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=34, critical=0, deadline=35, deadline=33, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=35, critical=0, deadline=35, deadline=33, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=35, critical=0, deadline=35, deadline=33, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=35, critical=0, deadline=35, deadline=33, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=35, critical=0, deadline=35, deadline=33, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=35, critical=2, deadline=35, deadline=33, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=35, critical=0, deadline=35, deadline=33, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=35, critical=0, deadline=35, deadline=33, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=35, critical=0, deadline=35, deadline=33, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=35, critical=0, deadline=36, deadline=33, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=35, critical=0, deadline=36, deadline=33, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=35, critical=0, deadline=36, deadline=33, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=35, critical=0, deadline=36, deadline=33, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=35, critical=0, deadline=36, deadline=33, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=36, critical=0, deadline=36, deadline=33, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=36, critical=0, deadline=36, deadline=33, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=36, critical=0, deadline=36, deadline=33, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=36, critical=0, deadline=36, deadline=33, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=36, critical=2, deadline=36, deadline=33, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=36, critical=0, deadline=36, deadline=33, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=36, critical=0, deadline=36, deadline=33, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=36, critical=0, deadline=36, deadline=33, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=36, critical=0, deadline=37, deadline=33, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=36, critical=0, deadline=37, deadline=33, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=36, critical=0, deadline=37, deadline=33, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=36, critical=0, deadline=37, deadline=33, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=36, critical=0, deadline=37, deadline=33, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=37, critical=0, deadline=37, deadline=33, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=37, critical=0, deadline=37, deadline=33, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=37, critical=0, deadline=37, deadline=33, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=37, critical=0, deadline=37, deadline=33, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=37, critical=2, deadline=37, deadline=33, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=37, critical=0, deadline=37, deadline=33, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=37, critical=0, deadline=37, deadline=33, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=37, critical=0, deadline=37, deadline=33, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=37, critical=0, deadline=38, deadline=33, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=37, critical=0, deadline=38, deadline=33, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=37, critical=0, deadline=38, deadline=33, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=37, critical=0, deadline=38, deadline=33, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=37, critical=0, deadline=38, deadline=33, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=38, critical=0, deadline=38, deadline=33, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=38, critical=0, deadline=38, deadline=33, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=38, critical=0, deadline=38, deadline=33, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=38, critical=0, deadline=38, deadline=33, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=38, critical=2, deadline=38, deadline=33, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=38, critical=0, deadline=38, deadline=33, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=38, critical=0, deadline=38, deadline=33, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=38, critical=0, deadline=38, deadline=33, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=38, critical=0, deadline=39, deadline=33, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=38, critical=0, deadline=39, deadline=33, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=38, critical=0, deadline=39, deadline=33, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=38, critical=0, deadline=39, deadline=33, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=38, critical=0, deadline=39, deadline=33, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=39, critical=0, deadline=39, deadline=33, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=39, critical=0, deadline=39, deadline=33, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=39, critical=0, deadline=39, deadline=33, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=39, critical=0, deadline=39, deadline=33, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=39, critical=2, deadline=39, deadline=33, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=39, critical=0, deadline=39, deadline=33, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=39, critical=0, deadline=39, deadline=33, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=39, critical=0, deadline=39, deadline=33, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=39, critical=0, deadline=40, deadline=33, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=39, critical=0, deadline=40, deadline=33, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=39, critical=0, deadline=40, deadline=33, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=39, critical=0, deadline=40, deadline=33, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=39, critical=0, deadline=40, deadline=33, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=40, critical=0, deadline=40, deadline=33, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=40, critical=0, deadline=40, deadline=33, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=40, critical=0, deadline=40, deadline=33, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=40, critical=0, deadline=40, deadline=33, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=40, critical=2, deadline=40, deadline=33, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=40, critical=0, deadline=40, deadline=33, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=40, critical=0, deadline=40, deadline=33, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=40, critical=0, deadline=40, deadline=33, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=40, critical=0, deadline=41, deadline=33, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=40, critical=0, deadline=41, deadline=33, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=40, critical=0, deadline=41, deadline=33, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=40, critical=0, deadline=41, deadline=33, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=40, critical=0, deadline=41, deadline=33, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=41, critical=0, deadline=41, deadline=33, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=41, critical=0, deadline=41, deadline=33, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=41, critical=0, deadline=41, deadline=33, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=41, critical=0, deadline=41, deadline=33, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=41, critical=2, deadline=41, deadline=33, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=41, critical=0, deadline=41, deadline=33, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=41, critical=0, deadline=41, deadline=33, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=41, critical=0, deadline=41, deadline=33, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=41, critical=0, deadline=42, deadline=33, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=41, critical=0, deadline=42, deadline=33, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=41, critical=0, deadline=42, deadline=33, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=41, critical=0, deadline=42, deadline=33, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=41, critical=0, deadline=42, deadline=33, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=42, critical=0, deadline=42, deadline=33, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=42, critical=0, deadline=42, deadline=33, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=42, critical=0, deadline=42, deadline=33, delay=1, lock=2, wait=1] [L69] 2 lock := 0; VAL [clk=42, critical=0, deadline=42, deadline=33, delay=1, lock=0, wait=1] [L57] COND TRUE 2 lock != 1 VAL [clk=42, critical=0, deadline=42, deadline=33, delay=1, lock=0, wait=1] [L58] 2 deadline := clk + delay; VAL [clk=42, critical=0, deadline=42, deadline=43, delay=1, lock=0, wait=1] [L59] 2 assume lock == 0; VAL [clk=42, critical=0, deadline=42, deadline=43, delay=1, lock=0, wait=1] [L60] 2 lock := 1; VAL [clk=42, critical=0, deadline=42, deadline=43, delay=1, lock=1, wait=1] [L61] 2 assume clk <= deadline; VAL [clk=42, critical=0, deadline=42, deadline=43, delay=1, lock=1, wait=1] [L62] 2 deadline := clk + wait; VAL [clk=42, critical=0, deadline=42, deadline=43, delay=1, lock=1, wait=1] [L44] 1 clk := clk + 1; VAL [clk=43, critical=0, deadline=42, deadline=43, delay=1, lock=1, wait=1] [L63] 2 assume clk >= deadline; VAL [clk=43, critical=0, deadline=42, deadline=43, delay=1, lock=1, wait=1] [L64] 2 assume lock == 1; VAL [clk=43, critical=0, deadline=42, deadline=43, delay=1, lock=1, wait=1] [L66] 2 assert critical == 0; VAL [clk=43, critical=0, deadline=42, deadline=43, delay=1, lock=1, wait=1] [L87] 3 assert critical == 0; VAL [clk=43, critical=0, deadline=42, deadline=43, delay=1, lock=1, wait=1] [L88] 3 critical := 2; VAL [clk=43, critical=2, deadline=42, deadline=43, delay=1, lock=1, wait=1] [L89] 3 critical := 0; VAL [clk=43, critical=0, deadline=42, deadline=43, delay=1, lock=1, wait=1] [L90] 3 lock := 0; VAL [clk=43, critical=0, deadline=42, deadline=43, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=43, critical=0, deadline=42, deadline=43, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=43, critical=0, deadline=44, deadline=43, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=43, critical=0, deadline=44, deadline=43, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=43, critical=0, deadline=44, deadline=43, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=43, critical=0, deadline=44, deadline=43, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=43, critical=0, deadline=44, deadline=43, delay=1, lock=2, wait=1] [L67] 2 critical := 1; VAL [clk=43, critical=1, deadline=44, deadline=43, delay=1, lock=2, wait=1] [L68] 2 critical := 0; VAL [clk=43, critical=0, deadline=44, deadline=43, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=44, critical=0, deadline=44, deadline=43, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=44, critical=0, deadline=44, deadline=43, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=44, critical=0, deadline=44, deadline=43, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=44, critical=0, deadline=44, deadline=43, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=44, critical=2, deadline=44, deadline=43, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=44, critical=0, deadline=44, deadline=43, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=44, critical=0, deadline=44, deadline=43, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=44, critical=0, deadline=44, deadline=43, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=44, critical=0, deadline=45, deadline=43, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=44, critical=0, deadline=45, deadline=43, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=44, critical=0, deadline=45, deadline=43, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=44, critical=0, deadline=45, deadline=43, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=44, critical=0, deadline=45, deadline=43, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=45, critical=0, deadline=45, deadline=43, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=45, critical=0, deadline=45, deadline=43, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=45, critical=0, deadline=45, deadline=43, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=45, critical=0, deadline=45, deadline=43, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=45, critical=2, deadline=45, deadline=43, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=45, critical=0, deadline=45, deadline=43, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=45, critical=0, deadline=45, deadline=43, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=45, critical=0, deadline=45, deadline=43, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=45, critical=0, deadline=46, deadline=43, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=45, critical=0, deadline=46, deadline=43, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=45, critical=0, deadline=46, deadline=43, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=45, critical=0, deadline=46, deadline=43, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=45, critical=0, deadline=46, deadline=43, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=46, critical=0, deadline=46, deadline=43, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=46, critical=0, deadline=46, deadline=43, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=46, critical=0, deadline=46, deadline=43, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=46, critical=0, deadline=46, deadline=43, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=46, critical=2, deadline=46, deadline=43, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=46, critical=0, deadline=46, deadline=43, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=46, critical=0, deadline=46, deadline=43, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=46, critical=0, deadline=46, deadline=43, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=46, critical=0, deadline=47, deadline=43, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=46, critical=0, deadline=47, deadline=43, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=46, critical=0, deadline=47, deadline=43, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=46, critical=0, deadline=47, deadline=43, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=46, critical=0, deadline=47, deadline=43, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=47, critical=0, deadline=47, deadline=43, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=47, critical=0, deadline=47, deadline=43, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=47, critical=0, deadline=47, deadline=43, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=47, critical=0, deadline=47, deadline=43, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=47, critical=2, deadline=47, deadline=43, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=47, critical=0, deadline=47, deadline=43, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=47, critical=0, deadline=47, deadline=43, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=47, critical=0, deadline=47, deadline=43, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=47, critical=0, deadline=48, deadline=43, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=47, critical=0, deadline=48, deadline=43, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=47, critical=0, deadline=48, deadline=43, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=47, critical=0, deadline=48, deadline=43, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=47, critical=0, deadline=48, deadline=43, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=48, critical=0, deadline=48, deadline=43, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=48, critical=0, deadline=48, deadline=43, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=48, critical=0, deadline=48, deadline=43, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=48, critical=0, deadline=48, deadline=43, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=48, critical=2, deadline=48, deadline=43, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=48, critical=0, deadline=48, deadline=43, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=48, critical=0, deadline=48, deadline=43, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=48, critical=0, deadline=48, deadline=43, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=48, critical=0, deadline=49, deadline=43, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=48, critical=0, deadline=49, deadline=43, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=48, critical=0, deadline=49, deadline=43, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=48, critical=0, deadline=49, deadline=43, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=48, critical=0, deadline=49, deadline=43, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=49, critical=0, deadline=49, deadline=43, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=49, critical=0, deadline=49, deadline=43, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=49, critical=0, deadline=49, deadline=43, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=49, critical=0, deadline=49, deadline=43, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=49, critical=2, deadline=49, deadline=43, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=49, critical=0, deadline=49, deadline=43, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=49, critical=0, deadline=49, deadline=43, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=49, critical=0, deadline=49, deadline=43, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=49, critical=0, deadline=50, deadline=43, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=49, critical=0, deadline=50, deadline=43, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=49, critical=0, deadline=50, deadline=43, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=49, critical=0, deadline=50, deadline=43, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=49, critical=0, deadline=50, deadline=43, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=50, critical=0, deadline=50, deadline=43, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=50, critical=0, deadline=50, deadline=43, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=50, critical=0, deadline=50, deadline=43, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=50, critical=0, deadline=50, deadline=43, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=50, critical=2, deadline=50, deadline=43, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=50, critical=0, deadline=50, deadline=43, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=50, critical=0, deadline=50, deadline=43, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=50, critical=0, deadline=50, deadline=43, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=50, critical=0, deadline=51, deadline=43, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=50, critical=0, deadline=51, deadline=43, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=50, critical=0, deadline=51, deadline=43, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=50, critical=0, deadline=51, deadline=43, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=50, critical=0, deadline=51, deadline=43, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=51, critical=0, deadline=51, deadline=43, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=51, critical=0, deadline=51, deadline=43, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=51, critical=0, deadline=51, deadline=43, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=51, critical=0, deadline=51, deadline=43, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=51, critical=2, deadline=51, deadline=43, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=51, critical=0, deadline=51, deadline=43, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=51, critical=0, deadline=51, deadline=43, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=51, critical=0, deadline=51, deadline=43, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=51, critical=0, deadline=52, deadline=43, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=51, critical=0, deadline=52, deadline=43, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=51, critical=0, deadline=52, deadline=43, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=51, critical=0, deadline=52, deadline=43, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=51, critical=0, deadline=52, deadline=43, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=52, critical=0, deadline=52, deadline=43, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=52, critical=0, deadline=52, deadline=43, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=52, critical=0, deadline=52, deadline=43, delay=1, lock=2, wait=1] [L69] 2 lock := 0; VAL [clk=52, critical=0, deadline=52, deadline=43, delay=1, lock=0, wait=1] [L57] COND TRUE 2 lock != 1 VAL [clk=52, critical=0, deadline=52, deadline=43, delay=1, lock=0, wait=1] [L58] 2 deadline := clk + delay; VAL [clk=52, critical=0, deadline=52, deadline=53, delay=1, lock=0, wait=1] [L59] 2 assume lock == 0; VAL [clk=52, critical=0, deadline=52, deadline=53, delay=1, lock=0, wait=1] [L60] 2 lock := 1; VAL [clk=52, critical=0, deadline=52, deadline=53, delay=1, lock=1, wait=1] [L61] 2 assume clk <= deadline; VAL [clk=52, critical=0, deadline=52, deadline=53, delay=1, lock=1, wait=1] [L62] 2 deadline := clk + wait; VAL [clk=52, critical=0, deadline=52, deadline=53, delay=1, lock=1, wait=1] [L44] 1 clk := clk + 1; VAL [clk=53, critical=0, deadline=52, deadline=53, delay=1, lock=1, wait=1] [L63] 2 assume clk >= deadline; VAL [clk=53, critical=0, deadline=52, deadline=53, delay=1, lock=1, wait=1] [L64] 2 assume lock == 1; VAL [clk=53, critical=0, deadline=52, deadline=53, delay=1, lock=1, wait=1] [L66] 2 assert critical == 0; VAL [clk=53, critical=0, deadline=52, deadline=53, delay=1, lock=1, wait=1] [L87] 3 assert critical == 0; VAL [clk=53, critical=0, deadline=52, deadline=53, delay=1, lock=1, wait=1] [L88] 3 critical := 2; VAL [clk=53, critical=2, deadline=52, deadline=53, delay=1, lock=1, wait=1] [L89] 3 critical := 0; VAL [clk=53, critical=0, deadline=52, deadline=53, delay=1, lock=1, wait=1] [L90] 3 lock := 0; VAL [clk=53, critical=0, deadline=52, deadline=53, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=53, critical=0, deadline=52, deadline=53, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=53, critical=0, deadline=54, deadline=53, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=53, critical=0, deadline=54, deadline=53, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=53, critical=0, deadline=54, deadline=53, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=53, critical=0, deadline=54, deadline=53, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=53, critical=0, deadline=54, deadline=53, delay=1, lock=2, wait=1] [L67] 2 critical := 1; VAL [clk=53, critical=1, deadline=54, deadline=53, delay=1, lock=2, wait=1] [L68] 2 critical := 0; VAL [clk=53, critical=0, deadline=54, deadline=53, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=54, critical=0, deadline=54, deadline=53, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=54, critical=0, deadline=54, deadline=53, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=54, critical=0, deadline=54, deadline=53, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=54, critical=0, deadline=54, deadline=53, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=54, critical=2, deadline=54, deadline=53, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=54, critical=0, deadline=54, deadline=53, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=54, critical=0, deadline=54, deadline=53, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=54, critical=0, deadline=54, deadline=53, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=54, critical=0, deadline=55, deadline=53, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=54, critical=0, deadline=55, deadline=53, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=54, critical=0, deadline=55, deadline=53, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=54, critical=0, deadline=55, deadline=53, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=54, critical=0, deadline=55, deadline=53, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=55, critical=0, deadline=55, deadline=53, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=55, critical=0, deadline=55, deadline=53, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=55, critical=0, deadline=55, deadline=53, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=55, critical=0, deadline=55, deadline=53, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=55, critical=2, deadline=55, deadline=53, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=55, critical=0, deadline=55, deadline=53, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=55, critical=0, deadline=55, deadline=53, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=55, critical=0, deadline=55, deadline=53, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=55, critical=0, deadline=56, deadline=53, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=55, critical=0, deadline=56, deadline=53, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=55, critical=0, deadline=56, deadline=53, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=55, critical=0, deadline=56, deadline=53, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=55, critical=0, deadline=56, deadline=53, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=56, critical=0, deadline=56, deadline=53, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=56, critical=0, deadline=56, deadline=53, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=56, critical=0, deadline=56, deadline=53, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=56, critical=0, deadline=56, deadline=53, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=56, critical=2, deadline=56, deadline=53, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=56, critical=0, deadline=56, deadline=53, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=56, critical=0, deadline=56, deadline=53, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=56, critical=0, deadline=56, deadline=53, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=56, critical=0, deadline=57, deadline=53, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=56, critical=0, deadline=57, deadline=53, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=56, critical=0, deadline=57, deadline=53, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=56, critical=0, deadline=57, deadline=53, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=56, critical=0, deadline=57, deadline=53, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=57, critical=0, deadline=57, deadline=53, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=57, critical=0, deadline=57, deadline=53, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=57, critical=0, deadline=57, deadline=53, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=57, critical=0, deadline=57, deadline=53, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=57, critical=2, deadline=57, deadline=53, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=57, critical=0, deadline=57, deadline=53, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=57, critical=0, deadline=57, deadline=53, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=57, critical=0, deadline=57, deadline=53, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=57, critical=0, deadline=58, deadline=53, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=57, critical=0, deadline=58, deadline=53, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=57, critical=0, deadline=58, deadline=53, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=57, critical=0, deadline=58, deadline=53, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=57, critical=0, deadline=58, deadline=53, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=58, critical=0, deadline=58, deadline=53, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=58, critical=0, deadline=58, deadline=53, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=58, critical=0, deadline=58, deadline=53, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=58, critical=0, deadline=58, deadline=53, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=58, critical=2, deadline=58, deadline=53, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=58, critical=0, deadline=58, deadline=53, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=58, critical=0, deadline=58, deadline=53, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=58, critical=0, deadline=58, deadline=53, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=58, critical=0, deadline=59, deadline=53, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=58, critical=0, deadline=59, deadline=53, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=58, critical=0, deadline=59, deadline=53, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=58, critical=0, deadline=59, deadline=53, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=58, critical=0, deadline=59, deadline=53, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=59, critical=0, deadline=59, deadline=53, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=59, critical=0, deadline=59, deadline=53, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=59, critical=0, deadline=59, deadline=53, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=59, critical=0, deadline=59, deadline=53, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=59, critical=2, deadline=59, deadline=53, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=59, critical=0, deadline=59, deadline=53, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=59, critical=0, deadline=59, deadline=53, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=59, critical=0, deadline=59, deadline=53, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=59, critical=0, deadline=60, deadline=53, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=59, critical=0, deadline=60, deadline=53, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=59, critical=0, deadline=60, deadline=53, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=59, critical=0, deadline=60, deadline=53, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=59, critical=0, deadline=60, deadline=53, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=60, critical=0, deadline=60, deadline=53, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=60, critical=0, deadline=60, deadline=53, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=60, critical=0, deadline=60, deadline=53, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=60, critical=0, deadline=60, deadline=53, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=60, critical=2, deadline=60, deadline=53, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=60, critical=0, deadline=60, deadline=53, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=60, critical=0, deadline=60, deadline=53, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=60, critical=0, deadline=60, deadline=53, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=60, critical=0, deadline=61, deadline=53, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=60, critical=0, deadline=61, deadline=53, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=60, critical=0, deadline=61, deadline=53, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=60, critical=0, deadline=61, deadline=53, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=60, critical=0, deadline=61, deadline=53, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=61, critical=0, deadline=61, deadline=53, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=61, critical=0, deadline=61, deadline=53, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=61, critical=0, deadline=61, deadline=53, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=61, critical=0, deadline=61, deadline=53, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=61, critical=2, deadline=61, deadline=53, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=61, critical=0, deadline=61, deadline=53, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=61, critical=0, deadline=61, deadline=53, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=61, critical=0, deadline=61, deadline=53, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=61, critical=0, deadline=62, deadline=53, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=61, critical=0, deadline=62, deadline=53, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=61, critical=0, deadline=62, deadline=53, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=61, critical=0, deadline=62, deadline=53, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=61, critical=0, deadline=62, deadline=53, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=62, critical=0, deadline=62, deadline=53, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=62, critical=0, deadline=62, deadline=53, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=62, critical=0, deadline=62, deadline=53, delay=1, lock=2, wait=1] [L69] 2 lock := 0; VAL [clk=62, critical=0, deadline=62, deadline=53, delay=1, lock=0, wait=1] [L57] COND TRUE 2 lock != 1 VAL [clk=62, critical=0, deadline=62, deadline=53, delay=1, lock=0, wait=1] [L58] 2 deadline := clk + delay; VAL [clk=62, critical=0, deadline=62, deadline=63, delay=1, lock=0, wait=1] [L59] 2 assume lock == 0; VAL [clk=62, critical=0, deadline=62, deadline=63, delay=1, lock=0, wait=1] [L60] 2 lock := 1; VAL [clk=62, critical=0, deadline=62, deadline=63, delay=1, lock=1, wait=1] [L61] 2 assume clk <= deadline; VAL [clk=62, critical=0, deadline=62, deadline=63, delay=1, lock=1, wait=1] [L62] 2 deadline := clk + wait; VAL [clk=62, critical=0, deadline=62, deadline=63, delay=1, lock=1, wait=1] [L44] 1 clk := clk + 1; VAL [clk=63, critical=0, deadline=62, deadline=63, delay=1, lock=1, wait=1] [L63] 2 assume clk >= deadline; VAL [clk=63, critical=0, deadline=62, deadline=63, delay=1, lock=1, wait=1] [L64] 2 assume lock == 1; VAL [clk=63, critical=0, deadline=62, deadline=63, delay=1, lock=1, wait=1] [L66] 2 assert critical == 0; VAL [clk=63, critical=0, deadline=62, deadline=63, delay=1, lock=1, wait=1] [L87] 3 assert critical == 0; VAL [clk=63, critical=0, deadline=62, deadline=63, delay=1, lock=1, wait=1] [L88] 3 critical := 2; VAL [clk=63, critical=2, deadline=62, deadline=63, delay=1, lock=1, wait=1] [L89] 3 critical := 0; VAL [clk=63, critical=0, deadline=62, deadline=63, delay=1, lock=1, wait=1] [L90] 3 lock := 0; VAL [clk=63, critical=0, deadline=62, deadline=63, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=63, critical=0, deadline=62, deadline=63, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=63, critical=0, deadline=64, deadline=63, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=63, critical=0, deadline=64, deadline=63, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=63, critical=0, deadline=64, deadline=63, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=63, critical=0, deadline=64, deadline=63, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=63, critical=0, deadline=64, deadline=63, delay=1, lock=2, wait=1] [L67] 2 critical := 1; VAL [clk=63, critical=1, deadline=64, deadline=63, delay=1, lock=2, wait=1] [L68] 2 critical := 0; VAL [clk=63, critical=0, deadline=64, deadline=63, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=64, critical=0, deadline=64, deadline=63, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=64, critical=0, deadline=64, deadline=63, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=64, critical=0, deadline=64, deadline=63, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=64, critical=0, deadline=64, deadline=63, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=64, critical=2, deadline=64, deadline=63, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=64, critical=0, deadline=64, deadline=63, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=64, critical=0, deadline=64, deadline=63, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=64, critical=0, deadline=64, deadline=63, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=64, critical=0, deadline=65, deadline=63, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=64, critical=0, deadline=65, deadline=63, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=64, critical=0, deadline=65, deadline=63, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=64, critical=0, deadline=65, deadline=63, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=64, critical=0, deadline=65, deadline=63, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=65, critical=0, deadline=65, deadline=63, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=65, critical=0, deadline=65, deadline=63, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=65, critical=0, deadline=65, deadline=63, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=65, critical=0, deadline=65, deadline=63, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=65, critical=2, deadline=65, deadline=63, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=65, critical=0, deadline=65, deadline=63, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=65, critical=0, deadline=65, deadline=63, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=65, critical=0, deadline=65, deadline=63, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=65, critical=0, deadline=66, deadline=63, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=65, critical=0, deadline=66, deadline=63, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=65, critical=0, deadline=66, deadline=63, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=65, critical=0, deadline=66, deadline=63, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=65, critical=0, deadline=66, deadline=63, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=66, critical=0, deadline=66, deadline=63, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=66, critical=0, deadline=66, deadline=63, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=66, critical=0, deadline=66, deadline=63, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=66, critical=0, deadline=66, deadline=63, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=66, critical=2, deadline=66, deadline=63, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=66, critical=0, deadline=66, deadline=63, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=66, critical=0, deadline=66, deadline=63, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=66, critical=0, deadline=66, deadline=63, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=66, critical=0, deadline=67, deadline=63, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=66, critical=0, deadline=67, deadline=63, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=66, critical=0, deadline=67, deadline=63, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=66, critical=0, deadline=67, deadline=63, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=66, critical=0, deadline=67, deadline=63, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=67, critical=0, deadline=67, deadline=63, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=67, critical=0, deadline=67, deadline=63, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=67, critical=0, deadline=67, deadline=63, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=67, critical=0, deadline=67, deadline=63, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=67, critical=2, deadline=67, deadline=63, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=67, critical=0, deadline=67, deadline=63, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=67, critical=0, deadline=67, deadline=63, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=67, critical=0, deadline=67, deadline=63, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=67, critical=0, deadline=68, deadline=63, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=67, critical=0, deadline=68, deadline=63, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=67, critical=0, deadline=68, deadline=63, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=67, critical=0, deadline=68, deadline=63, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=67, critical=0, deadline=68, deadline=63, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=68, critical=0, deadline=68, deadline=63, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=68, critical=0, deadline=68, deadline=63, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=68, critical=0, deadline=68, deadline=63, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=68, critical=0, deadline=68, deadline=63, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=68, critical=2, deadline=68, deadline=63, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=68, critical=0, deadline=68, deadline=63, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=68, critical=0, deadline=68, deadline=63, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=68, critical=0, deadline=68, deadline=63, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=68, critical=0, deadline=69, deadline=63, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=68, critical=0, deadline=69, deadline=63, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=68, critical=0, deadline=69, deadline=63, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=68, critical=0, deadline=69, deadline=63, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=68, critical=0, deadline=69, deadline=63, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=69, critical=0, deadline=69, deadline=63, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=69, critical=0, deadline=69, deadline=63, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=69, critical=0, deadline=69, deadline=63, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=69, critical=0, deadline=69, deadline=63, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=69, critical=2, deadline=69, deadline=63, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=69, critical=0, deadline=69, deadline=63, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=69, critical=0, deadline=69, deadline=63, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=69, critical=0, deadline=69, deadline=63, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=69, critical=0, deadline=70, deadline=63, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=69, critical=0, deadline=70, deadline=63, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=69, critical=0, deadline=70, deadline=63, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=69, critical=0, deadline=70, deadline=63, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=69, critical=0, deadline=70, deadline=63, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=70, critical=0, deadline=70, deadline=63, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=70, critical=0, deadline=70, deadline=63, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=70, critical=0, deadline=70, deadline=63, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=70, critical=0, deadline=70, deadline=63, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=70, critical=2, deadline=70, deadline=63, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=70, critical=0, deadline=70, deadline=63, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=70, critical=0, deadline=70, deadline=63, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=70, critical=0, deadline=70, deadline=63, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=70, critical=0, deadline=71, deadline=63, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=70, critical=0, deadline=71, deadline=63, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=70, critical=0, deadline=71, deadline=63, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=70, critical=0, deadline=71, deadline=63, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=70, critical=0, deadline=71, deadline=63, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=71, critical=0, deadline=71, deadline=63, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=71, critical=0, deadline=71, deadline=63, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=71, critical=0, deadline=71, deadline=63, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=71, critical=0, deadline=71, deadline=63, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=71, critical=2, deadline=71, deadline=63, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=71, critical=0, deadline=71, deadline=63, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=71, critical=0, deadline=71, deadline=63, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=71, critical=0, deadline=71, deadline=63, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=71, critical=0, deadline=72, deadline=63, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=71, critical=0, deadline=72, deadline=63, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=71, critical=0, deadline=72, deadline=63, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=71, critical=0, deadline=72, deadline=63, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=71, critical=0, deadline=72, deadline=63, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=72, critical=0, deadline=72, deadline=63, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=72, critical=0, deadline=72, deadline=63, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=72, critical=0, deadline=72, deadline=63, delay=1, lock=2, wait=1] [L69] 2 lock := 0; VAL [clk=72, critical=0, deadline=72, deadline=63, delay=1, lock=0, wait=1] [L57] COND TRUE 2 lock != 1 VAL [clk=72, critical=0, deadline=72, deadline=63, delay=1, lock=0, wait=1] [L58] 2 deadline := clk + delay; VAL [clk=72, critical=0, deadline=72, deadline=73, delay=1, lock=0, wait=1] [L59] 2 assume lock == 0; VAL [clk=72, critical=0, deadline=72, deadline=73, delay=1, lock=0, wait=1] [L60] 2 lock := 1; VAL [clk=72, critical=0, deadline=72, deadline=73, delay=1, lock=1, wait=1] [L61] 2 assume clk <= deadline; VAL [clk=72, critical=0, deadline=72, deadline=73, delay=1, lock=1, wait=1] [L62] 2 deadline := clk + wait; VAL [clk=72, critical=0, deadline=72, deadline=73, delay=1, lock=1, wait=1] [L44] 1 clk := clk + 1; VAL [clk=73, critical=0, deadline=72, deadline=73, delay=1, lock=1, wait=1] [L63] 2 assume clk >= deadline; VAL [clk=73, critical=0, deadline=72, deadline=73, delay=1, lock=1, wait=1] [L64] 2 assume lock == 1; VAL [clk=73, critical=0, deadline=72, deadline=73, delay=1, lock=1, wait=1] [L66] 2 assert critical == 0; VAL [clk=73, critical=0, deadline=72, deadline=73, delay=1, lock=1, wait=1] [L87] 3 assert critical == 0; VAL [clk=73, critical=0, deadline=72, deadline=73, delay=1, lock=1, wait=1] [L88] 3 critical := 2; VAL [clk=73, critical=2, deadline=72, deadline=73, delay=1, lock=1, wait=1] [L89] 3 critical := 0; VAL [clk=73, critical=0, deadline=72, deadline=73, delay=1, lock=1, wait=1] [L90] 3 lock := 0; VAL [clk=73, critical=0, deadline=72, deadline=73, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=73, critical=0, deadline=72, deadline=73, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=73, critical=0, deadline=74, deadline=73, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=73, critical=0, deadline=74, deadline=73, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=73, critical=0, deadline=74, deadline=73, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=73, critical=0, deadline=74, deadline=73, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=73, critical=0, deadline=74, deadline=73, delay=1, lock=2, wait=1] [L67] 2 critical := 1; VAL [clk=73, critical=1, deadline=74, deadline=73, delay=1, lock=2, wait=1] [L68] 2 critical := 0; VAL [clk=73, critical=0, deadline=74, deadline=73, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=74, critical=0, deadline=74, deadline=73, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=74, critical=0, deadline=74, deadline=73, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=74, critical=0, deadline=74, deadline=73, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=74, critical=0, deadline=74, deadline=73, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=74, critical=2, deadline=74, deadline=73, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=74, critical=0, deadline=74, deadline=73, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=74, critical=0, deadline=74, deadline=73, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=74, critical=0, deadline=74, deadline=73, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=74, critical=0, deadline=75, deadline=73, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=74, critical=0, deadline=75, deadline=73, delay=1, lock=0, wait=1] [L69] 2 lock := 0; VAL [clk=74, critical=0, deadline=75, deadline=73, delay=1, lock=0, wait=1] [L57] COND TRUE 2 lock != 1 VAL [clk=74, critical=0, deadline=75, deadline=73, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=74, critical=0, deadline=75, deadline=73, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=74, critical=0, deadline=75, deadline=73, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=74, critical=0, deadline=75, deadline=73, delay=1, lock=2, wait=1] [L58] 2 deadline := clk + delay; VAL [clk=74, critical=0, deadline=75, deadline=75, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=75, critical=0, deadline=75, deadline=75, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=75, critical=0, deadline=75, deadline=75, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=75, critical=0, deadline=75, deadline=75, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=75, critical=0, deadline=75, deadline=75, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=75, critical=2, deadline=75, deadline=75, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=75, critical=0, deadline=75, deadline=75, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=75, critical=0, deadline=75, deadline=75, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=75, critical=0, deadline=75, deadline=75, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=75, critical=0, deadline=76, deadline=75, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=75, critical=0, deadline=76, deadline=75, delay=1, lock=0, wait=1] [L59] 2 assume lock == 0; VAL [clk=75, critical=0, deadline=76, deadline=75, delay=1, lock=0, wait=1] [L60] 2 lock := 1; VAL [clk=75, critical=0, deadline=76, deadline=75, delay=1, lock=1, wait=1] [L61] 2 assume clk <= deadline; VAL [clk=75, critical=0, deadline=76, deadline=75, delay=1, lock=1, wait=1] [L62] 2 deadline := clk + wait; VAL [clk=75, critical=0, deadline=76, deadline=76, delay=1, lock=1, wait=1] [L44] 1 clk := clk + 1; VAL [clk=76, critical=0, deadline=76, deadline=76, delay=1, lock=1, wait=1] [L63] 2 assume clk >= deadline; VAL [clk=76, critical=0, deadline=76, deadline=76, delay=1, lock=1, wait=1] [L64] 2 assume lock == 1; VAL [clk=76, critical=0, deadline=76, deadline=76, delay=1, lock=1, wait=1] [L81] 3 lock := 2; VAL [clk=76, critical=0, deadline=76, deadline=76, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=76, critical=0, deadline=76, deadline=76, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=76, critical=0, deadline=77, deadline=76, delay=1, lock=2, wait=1] [L66] 2 assert critical == 0; VAL [clk=76, critical=0, deadline=77, deadline=76, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=77, critical=0, deadline=77, deadline=76, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=77, critical=0, deadline=77, deadline=76, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=77, critical=0, deadline=77, deadline=76, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=77, critical=0, deadline=77, deadline=76, delay=1, lock=2, wait=1] [L88] 3 critical := 2; VAL [clk=77, critical=2, deadline=77, deadline=76, delay=1, lock=2, wait=1] [L89] 3 critical := 0; VAL [clk=77, critical=0, deadline=77, deadline=76, delay=1, lock=2, wait=1] [L90] 3 lock := 0; VAL [clk=77, critical=0, deadline=77, deadline=76, delay=1, lock=0, wait=1] [L78] COND TRUE 3 lock != 2 VAL [clk=77, critical=0, deadline=77, deadline=76, delay=1, lock=0, wait=1] [L79] 3 deadline := clk + delay; VAL [clk=77, critical=0, deadline=78, deadline=76, delay=1, lock=0, wait=1] [L80] 3 assume lock == 0; VAL [clk=77, critical=0, deadline=78, deadline=76, delay=1, lock=0, wait=1] [L81] 3 lock := 2; VAL [clk=77, critical=0, deadline=78, deadline=76, delay=1, lock=2, wait=1] [L82] 3 assume clk <= deadline; VAL [clk=77, critical=0, deadline=78, deadline=76, delay=1, lock=2, wait=1] [L83] 3 deadline := clk + wait; VAL [clk=77, critical=0, deadline=78, deadline=76, delay=1, lock=2, wait=1] [L67] 2 critical := 1; VAL [clk=77, critical=1, deadline=78, deadline=76, delay=1, lock=2, wait=1] [L44] 1 clk := clk + 1; VAL [clk=78, critical=1, deadline=78, deadline=76, delay=1, lock=2, wait=1] [L84] 3 assume clk >= deadline; VAL [clk=78, critical=1, deadline=78, deadline=76, delay=1, lock=2, wait=1] [L85] 3 assume lock == 2; VAL [clk=78, critical=1, deadline=78, deadline=76, delay=1, lock=2, wait=1] [L87] 3 assert critical == 0; VAL [clk=78, critical=1, deadline=78, deadline=76, delay=1, lock=2, wait=1] - UnprovableResult [Line: 66]: Unable to prove that assertion always holds Unable to prove that assertion always holds Reason: Not analyzed. - UnprovableResult [Line: 34]: Unable to prove that petrification did provide enough thread instances (tool internal message, not intended for end users) Unable to prove that petrification did provide enough thread instances (tool internal message, not intended for end users) Reason: Not analyzed. - UnprovableResult [Line: 35]: Unable to prove that petrification did provide enough thread instances (tool internal message, not intended for end users) Unable to prove that petrification did provide enough thread instances (tool internal message, not intended for end users) Reason: Not analyzed. - UnprovableResult [Line: 34]: Unable to prove that petrification did provide enough thread instances (tool internal message, not intended for end users) Unable to prove that petrification did provide enough thread instances (tool internal message, not intended for end users) Reason: Not analyzed. - StatisticsResult: Ultimate Automizer benchmark data with 1 thread instances CFG has 7 procedures, 78 locations, 7 error locations. Started 1 CEGAR loops. OverallTime: 36.6s, OverallIterations: 10, TraceHistogramMax: 0, PathProgramHistogramMax: 4, EmptinessCheckTime: 0.0s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, PartialOrderReductionTime: 26.4s, HoareTripleCheckerStatistics: , PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=0occurred in iteration=0, InterpolantAutomatonStates: 57, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.7s SatisfiabilityAnalysisTime, 8.5s InterpolantComputationTime, 7639 NumberOfCodeBlocks, 6429 NumberOfCodeBlocksAsserted, 20 NumberOfCheckSat, 8020 ConstructedInterpolants, 0 QuantifiedInterpolants, 26499 SizeOfPredicates, 6 NumberOfNonLiveVariables, 352 ConjunctsInSsa, 8 ConjunctsInUnsatCore, 11 InterpolantComputations, 8 PerfectInterpolantSequences, 259331/272560 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2022-02-16 09:56:04,419 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Ended with exit code 0 [2022-02-16 09:56:04,634 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Ended with exit code 0 Received shutdown request...