/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -s ../../../trunk/examples/settings/automizer/mcr/svcomp-Reach-32bit-Automizer_Default-noMmResRef-FA-McrAutomaton-WP.epf -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml -i ../../../trunk/examples/concurrent/bpl/weaver-benchmarks/generated/popl20/prod-cons.wvr.bpl -------------------------------------------------------------------------------- This is Ultimate 0.2.2-wip.dk.mcr-reduction-c7b2d19 [2022-03-15 21:33:50,440 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-03-15 21:33:50,442 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-03-15 21:33:50,483 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2022-03-15 21:33:50,492 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-03-15 21:33:50,492 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-03-15 21:33:50,493 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-03-15 21:33:50,494 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-03-15 21:33:50,494 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-03-15 21:33:50,495 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-03-15 21:33:50,496 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-03-15 21:33:50,497 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-03-15 21:33:50,498 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-03-15 21:33:50,511 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-03-15 21:33:50,512 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-03-15 21:33:50,512 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-03-15 21:33:50,514 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-03-15 21:33:50,518 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-03-15 21:33:50,518 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-03-15 21:33:50,519 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-03-15 21:33:50,524 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/mcr/svcomp-Reach-32bit-Automizer_Default-noMmResRef-FA-McrAutomaton-WP.epf [2022-03-15 21:33:50,548 INFO L113 SettingsManager]: Loading preferences was successful [2022-03-15 21:33:50,548 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-03-15 21:33:50,549 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-03-15 21:33:50,549 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-03-15 21:33:50,550 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-03-15 21:33:50,550 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-03-15 21:33:50,550 INFO L138 SettingsManager]: * Use SBE=true [2022-03-15 21:33:50,550 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-03-15 21:33:50,550 INFO L138 SettingsManager]: * sizeof long=4 [2022-03-15 21:33:50,550 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-03-15 21:33:50,551 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-03-15 21:33:50,551 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-03-15 21:33:50,551 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-03-15 21:33:50,551 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-03-15 21:33:50,551 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-03-15 21:33:50,551 INFO L138 SettingsManager]: * sizeof long double=12 [2022-03-15 21:33:50,551 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-03-15 21:33:50,551 INFO L138 SettingsManager]: * Use constant arrays=true [2022-03-15 21:33:50,551 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-03-15 21:33:50,551 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-03-15 21:33:50,552 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-03-15 21:33:50,552 INFO L138 SettingsManager]: * To the following directory=./dump/ [2022-03-15 21:33:50,552 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-03-15 21:33:50,552 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-03-15 21:33:50,552 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-03-15 21:33:50,552 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_NestedInterpolation [2022-03-15 21:33:50,552 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-03-15 21:33:50,553 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-03-15 21:33:50,553 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-03-15 21:33:50,553 INFO L138 SettingsManager]: * Override the interpolant automaton setting of the refinement strategy=true [2022-03-15 21:33:50,553 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=VARIABLE_BASED_MOVER_CHECK [2022-03-15 21:33:50,553 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-03-15 21:33:50,553 INFO L138 SettingsManager]: * Interpolant automaton=MCR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release [2022-03-15 21:33:50,723 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-03-15 21:33:50,741 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-03-15 21:33:50,742 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-03-15 21:33:50,743 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2022-03-15 21:33:50,743 INFO L275 PluginConnector]: Boogie PL CUP Parser initialized [2022-03-15 21:33:50,744 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/concurrent/bpl/weaver-benchmarks/generated/popl20/prod-cons.wvr.bpl [2022-03-15 21:33:50,744 INFO L110 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/concurrent/bpl/weaver-benchmarks/generated/popl20/prod-cons.wvr.bpl' [2022-03-15 21:33:50,759 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-03-15 21:33:50,760 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2022-03-15 21:33:50,761 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-03-15 21:33:50,761 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-03-15 21:33:50,761 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-03-15 21:33:50,768 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "prod-cons.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:33:50" (1/1) ... [2022-03-15 21:33:50,773 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "prod-cons.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:33:50" (1/1) ... [2022-03-15 21:33:50,777 INFO L137 Inliner]: procedures = 4, calls = 3, calls flagged for inlining = 0, calls inlined = 0, statements flattened = 0 [2022-03-15 21:33:50,778 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-03-15 21:33:50,778 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-03-15 21:33:50,778 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-03-15 21:33:50,779 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-03-15 21:33:50,783 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "prod-cons.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:33:50" (1/1) ... [2022-03-15 21:33:50,783 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "prod-cons.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:33:50" (1/1) ... [2022-03-15 21:33:50,784 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "prod-cons.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:33:50" (1/1) ... [2022-03-15 21:33:50,784 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "prod-cons.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:33:50" (1/1) ... [2022-03-15 21:33:50,786 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "prod-cons.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:33:50" (1/1) ... [2022-03-15 21:33:50,789 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "prod-cons.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:33:50" (1/1) ... [2022-03-15 21:33:50,789 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "prod-cons.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:33:50" (1/1) ... [2022-03-15 21:33:50,790 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-03-15 21:33:50,791 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-03-15 21:33:50,792 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-03-15 21:33:50,792 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-03-15 21:33:50,793 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "prod-cons.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:33:50" (1/1) ... [2022-03-15 21:33:50,797 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-03-15 21:33:50,810 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:33:50,822 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-03-15 21:33:50,844 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-03-15 21:33:50,854 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread1 given in one single declaration [2022-03-15 21:33:50,854 INFO L130 BoogieDeclarations]: Found specification of procedure thread1 [2022-03-15 21:33:50,854 INFO L138 BoogieDeclarations]: Found implementation of procedure thread1 [2022-03-15 21:33:50,854 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread2 given in one single declaration [2022-03-15 21:33:50,854 INFO L130 BoogieDeclarations]: Found specification of procedure thread2 [2022-03-15 21:33:50,854 INFO L138 BoogieDeclarations]: Found implementation of procedure thread2 [2022-03-15 21:33:50,854 INFO L124 BoogieDeclarations]: Specification and implementation of procedure ULTIMATE.start given in one single declaration [2022-03-15 21:33:50,854 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-03-15 21:33:50,854 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-03-15 21:33:50,854 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread3 given in one single declaration [2022-03-15 21:33:50,854 INFO L130 BoogieDeclarations]: Found specification of procedure thread3 [2022-03-15 21:33:50,855 INFO L138 BoogieDeclarations]: Found implementation of procedure thread3 [2022-03-15 21:33:50,855 WARN L208 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2022-03-15 21:33:50,889 INFO L234 CfgBuilder]: Building ICFG [2022-03-15 21:33:50,890 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-03-15 21:33:50,983 INFO L275 CfgBuilder]: Performing block encoding [2022-03-15 21:33:50,992 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-03-15 21:33:50,993 INFO L299 CfgBuilder]: Removed 0 assume(true) statements. [2022-03-15 21:33:50,994 INFO L202 PluginConnector]: Adding new model prod-cons.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.03 09:33:50 BoogieIcfgContainer [2022-03-15 21:33:50,994 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-03-15 21:33:50,995 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-03-15 21:33:50,995 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-03-15 21:33:50,998 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-03-15 21:33:50,999 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "prod-cons.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:33:50" (1/2) ... [2022-03-15 21:33:50,999 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@537bab8b and model type prod-cons.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.03 09:33:50, skipping insertion in model container [2022-03-15 21:33:50,999 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "prod-cons.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.03 09:33:50" (2/2) ... [2022-03-15 21:33:51,000 INFO L111 eAbstractionObserver]: Analyzing ICFG prod-cons.wvr.bpl [2022-03-15 21:33:51,003 WARN L150 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2022-03-15 21:33:51,003 INFO L205 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_NestedInterpolation Determinization: PREDICATE_ABSTRACTION [2022-03-15 21:33:51,003 INFO L164 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-03-15 21:33:51,003 INFO L534 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2022-03-15 21:33:51,038 INFO L148 ThreadInstanceAdder]: Constructed 3 joinOtherThreadTransitions. [2022-03-15 21:33:51,075 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-03-15 21:33:51,082 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=Craig_NestedInterpolation, mInterpolantAutomaton=MCR, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mLazyFiniteAutomaton=false, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=true, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR, mMcrOptimizeForkJoin=true, mMcrOverapproximateWrwc=true [2022-03-15 21:33:51,082 INFO L340 AbstractCegarLoop]: Starting to check reachability of 4 error locations. [2022-03-15 21:33:51,093 INFO L126 etLargeBlockEncoding]: Petri net LBE is using variable-based independence relation. [2022-03-15 21:33:51,100 INFO L133 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 38 places, 30 transitions, 84 flow [2022-03-15 21:33:51,103 INFO L110 LiptonReduction]: Starting Lipton reduction on Petri net that has 38 places, 30 transitions, 84 flow [2022-03-15 21:33:51,104 INFO L74 FinitePrefix]: Start finitePrefix. Operand has 38 places, 30 transitions, 84 flow [2022-03-15 21:33:51,136 INFO L129 PetriNetUnfolder]: 2/27 cut-off events. [2022-03-15 21:33:51,136 INFO L130 PetriNetUnfolder]: For 3/3 co-relation queries the response was YES. [2022-03-15 21:33:51,141 INFO L84 FinitePrefix]: Finished finitePrefix Result has 40 conditions, 27 events. 2/27 cut-off events. For 3/3 co-relation queries the response was YES. Maximal size of possible extension queue 5. Compared 38 event pairs, 0 based on Foata normal form. 0/24 useless extension candidates. Maximal degree in co-relation 21. Up to 2 conditions per place. [2022-03-15 21:33:51,141 INFO L116 LiptonReduction]: Number of co-enabled transitions 138 [2022-03-15 21:33:51,344 INFO L131 LiptonReduction]: Checked pairs total: 321 [2022-03-15 21:33:51,344 INFO L133 LiptonReduction]: Total number of compositions: 11 [2022-03-15 21:33:51,355 INFO L111 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 28 places, 20 transitions, 64 flow [2022-03-15 21:33:51,372 INFO L133 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result has 53 states, 52 states have (on average 2.480769230769231) internal successors, (129), 52 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:51,374 INFO L276 IsEmpty]: Start isEmpty. Operand has 53 states, 52 states have (on average 2.480769230769231) internal successors, (129), 52 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:51,378 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2022-03-15 21:33:51,378 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:33:51,378 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:33:51,378 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:33:51,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:33:51,385 INFO L85 PathProgramCache]: Analyzing trace with hash -79435797, now seen corresponding path program 1 times [2022-03-15 21:33:51,398 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:33:51,399 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [810446748] [2022-03-15 21:33:51,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:33:51,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:33:51,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:33:51,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:33:51,535 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:33:51,536 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [810446748] [2022-03-15 21:33:51,536 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [810446748] provided 1 perfect and 0 imperfect interpolant sequences [2022-03-15 21:33:51,536 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-03-15 21:33:51,536 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-03-15 21:33:51,537 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [995173875] [2022-03-15 21:33:51,538 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:33:51,542 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:33:51,557 INFO L252 McrAutomatonBuilder]: Finished intersection with 16 states and 19 transitions. [2022-03-15 21:33:51,558 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:33:51,647 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 0 new interpolants: [] [2022-03-15 21:33:51,648 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-03-15 21:33:51,648 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:33:51,663 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-03-15 21:33:51,663 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-03-15 21:33:51,665 INFO L87 Difference]: Start difference. First operand has 53 states, 52 states have (on average 2.480769230769231) internal successors, (129), 52 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 3 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:51,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:33:51,734 INFO L93 Difference]: Finished difference Result 96 states and 223 transitions. [2022-03-15 21:33:51,737 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-03-15 21:33:51,739 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 3.25) internal successors, (13), 3 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 11 [2022-03-15 21:33:51,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:33:51,745 INFO L225 Difference]: With dead ends: 96 [2022-03-15 21:33:51,746 INFO L226 Difference]: Without dead ends: 66 [2022-03-15 21:33:51,746 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-03-15 21:33:51,750 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 21 mSDsluCounter, 16 mSDsCounter, 0 mSdLazyCounter, 42 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 21 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 48 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 42 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:33:51,750 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [21 Valid, 1 Invalid, 48 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 42 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-03-15 21:33:51,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2022-03-15 21:33:51,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 66. [2022-03-15 21:33:51,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 65 states have (on average 2.292307692307692) internal successors, (149), 65 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:51,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 149 transitions. [2022-03-15 21:33:51,774 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 149 transitions. Word has length 11 [2022-03-15 21:33:51,774 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:33:51,775 INFO L470 AbstractCegarLoop]: Abstraction has 66 states and 149 transitions. [2022-03-15 21:33:51,775 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 3.25) internal successors, (13), 3 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:51,775 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 149 transitions. [2022-03-15 21:33:51,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2022-03-15 21:33:51,776 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:33:51,776 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:33:51,776 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-03-15 21:33:51,776 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:33:51,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:33:51,777 INFO L85 PathProgramCache]: Analyzing trace with hash 1412530366, now seen corresponding path program 1 times [2022-03-15 21:33:51,778 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:33:51,778 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077112626] [2022-03-15 21:33:51,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:33:51,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:33:51,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:33:51,805 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:33:51,805 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:33:51,805 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077112626] [2022-03-15 21:33:51,805 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1077112626] provided 1 perfect and 0 imperfect interpolant sequences [2022-03-15 21:33:51,806 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-03-15 21:33:51,806 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-03-15 21:33:51,806 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1286023930] [2022-03-15 21:33:51,806 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:33:51,807 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:33:51,809 INFO L252 McrAutomatonBuilder]: Finished intersection with 31 states and 49 transitions. [2022-03-15 21:33:51,809 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:33:51,991 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 0 new interpolants: [] [2022-03-15 21:33:51,992 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-03-15 21:33:51,992 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:33:51,992 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-03-15 21:33:51,993 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-03-15 21:33:51,993 INFO L87 Difference]: Start difference. First operand 66 states and 149 transitions. Second operand has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 2 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:52,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:33:52,023 INFO L93 Difference]: Finished difference Result 83 states and 182 transitions. [2022-03-15 21:33:52,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-03-15 21:33:52,023 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 2 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 14 [2022-03-15 21:33:52,023 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:33:52,024 INFO L225 Difference]: With dead ends: 83 [2022-03-15 21:33:52,024 INFO L226 Difference]: Without dead ends: 76 [2022-03-15 21:33:52,025 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 11 SyntacticMatches, 6 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-03-15 21:33:52,026 INFO L933 BasicCegarLoop]: 3 mSDtfsCounter, 1 mSDsluCounter, 12 mSDsCounter, 0 mSdLazyCounter, 24 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 6 SdHoareTripleChecker+Invalid, 24 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 24 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:33:52,026 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1 Valid, 6 Invalid, 24 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 24 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-03-15 21:33:52,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2022-03-15 21:33:52,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 76. [2022-03-15 21:33:52,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 75 states have (on average 2.2533333333333334) internal successors, (169), 75 states have internal predecessors, (169), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:52,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 169 transitions. [2022-03-15 21:33:52,034 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 169 transitions. Word has length 14 [2022-03-15 21:33:52,034 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:33:52,034 INFO L470 AbstractCegarLoop]: Abstraction has 76 states and 169 transitions. [2022-03-15 21:33:52,034 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 2 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:52,034 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 169 transitions. [2022-03-15 21:33:52,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-03-15 21:33:52,035 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:33:52,035 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:33:52,035 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-03-15 21:33:52,036 INFO L402 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:33:52,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:33:52,036 INFO L85 PathProgramCache]: Analyzing trace with hash 1139884501, now seen corresponding path program 1 times [2022-03-15 21:33:52,040 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:33:52,040 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1146755563] [2022-03-15 21:33:52,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:33:52,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:33:52,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:33:52,172 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:33:52,173 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:33:52,173 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1146755563] [2022-03-15 21:33:52,173 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1146755563] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:33:52,173 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2026878420] [2022-03-15 21:33:52,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:33:52,173 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:33:52,174 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:33:52,183 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:33:52,184 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-03-15 21:33:52,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:33:52,217 INFO L263 TraceCheckSpWp]: Trace formula consists of 54 conjuncts, 10 conjunts are in the unsatisfiable core [2022-03-15 21:33:52,220 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:33:52,363 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-03-15 21:33:52,457 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:33:52,458 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:33:52,517 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:33:52,518 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 14 treesize of output 18 [2022-03-15 21:33:52,611 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:33:52,613 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2026878420] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:33:52,613 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:33:52,613 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 16 [2022-03-15 21:33:52,613 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [332498691] [2022-03-15 21:33:52,613 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:33:52,616 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:33:52,624 INFO L252 McrAutomatonBuilder]: Finished intersection with 41 states and 69 transitions. [2022-03-15 21:33:52,624 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:33:53,116 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 4 new interpolants: [729#(and (or (not v_assert) (<= (+ d 1) w) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (not (< 0 w)) (= (+ (* (- 1) w) W) 0))), 727#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 726#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 728#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert))] [2022-03-15 21:33:53,116 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2022-03-15 21:33:53,116 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:33:53,117 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-03-15 21:33:53,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=76, Invalid=344, Unknown=0, NotChecked=0, Total=420 [2022-03-15 21:33:53,118 INFO L87 Difference]: Start difference. First operand 76 states and 169 transitions. Second operand has 12 states, 12 states have (on average 3.4166666666666665) internal successors, (41), 11 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:53,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:33:53,638 INFO L93 Difference]: Finished difference Result 168 states and 372 transitions. [2022-03-15 21:33:53,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-03-15 21:33:53,638 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 3.4166666666666665) internal successors, (41), 11 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 16 [2022-03-15 21:33:53,639 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:33:53,640 INFO L225 Difference]: With dead ends: 168 [2022-03-15 21:33:53,640 INFO L226 Difference]: Without dead ends: 140 [2022-03-15 21:33:53,640 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 37 SyntacticMatches, 5 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 258 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=221, Invalid=969, Unknown=0, NotChecked=0, Total=1190 [2022-03-15 21:33:53,641 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 77 mSDsluCounter, 92 mSDsCounter, 0 mSdLazyCounter, 281 mSolverCounterSat, 32 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 77 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 313 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 32 IncrementalHoareTripleChecker+Valid, 281 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-03-15 21:33:53,641 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [77 Valid, 1 Invalid, 313 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [32 Valid, 281 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-03-15 21:33:53,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2022-03-15 21:33:53,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 97. [2022-03-15 21:33:53,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 96 states have (on average 2.2916666666666665) internal successors, (220), 96 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:53,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 220 transitions. [2022-03-15 21:33:53,648 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 220 transitions. Word has length 16 [2022-03-15 21:33:53,649 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:33:53,649 INFO L470 AbstractCegarLoop]: Abstraction has 97 states and 220 transitions. [2022-03-15 21:33:53,649 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 3.4166666666666665) internal successors, (41), 11 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:53,649 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 220 transitions. [2022-03-15 21:33:53,649 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-03-15 21:33:53,650 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:33:53,650 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:33:53,666 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2022-03-15 21:33:53,867 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:33:53,872 INFO L402 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:33:53,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:33:53,872 INFO L85 PathProgramCache]: Analyzing trace with hash -649861484, now seen corresponding path program 2 times [2022-03-15 21:33:53,873 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:33:53,873 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2125354910] [2022-03-15 21:33:53,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:33:53,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:33:53,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:33:53,926 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:33:53,927 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:33:53,927 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2125354910] [2022-03-15 21:33:53,928 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2125354910] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:33:53,929 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1753521927] [2022-03-15 21:33:53,929 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:33:53,929 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:33:53,929 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:33:53,931 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:33:53,938 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-03-15 21:33:53,976 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:33:53,976 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:33:53,976 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 4 conjunts are in the unsatisfiable core [2022-03-15 21:33:53,978 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:33:54,008 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:33:54,008 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:33:54,060 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:33:54,060 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1753521927] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:33:54,060 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:33:54,060 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 3, 3] total 4 [2022-03-15 21:33:54,060 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [41369070] [2022-03-15 21:33:54,060 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:33:54,062 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:33:54,067 INFO L252 McrAutomatonBuilder]: Finished intersection with 56 states and 99 transitions. [2022-03-15 21:33:54,068 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:33:54,282 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 0 new interpolants: [] [2022-03-15 21:33:54,283 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-03-15 21:33:54,283 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:33:54,283 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-03-15 21:33:54,283 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2022-03-15 21:33:54,283 INFO L87 Difference]: Start difference. First operand 97 states and 220 transitions. Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:54,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:33:54,318 INFO L93 Difference]: Finished difference Result 250 states and 558 transitions. [2022-03-15 21:33:54,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-03-15 21:33:54,319 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 5.6) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 19 [2022-03-15 21:33:54,319 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:33:54,320 INFO L225 Difference]: With dead ends: 250 [2022-03-15 21:33:54,320 INFO L226 Difference]: Without dead ends: 228 [2022-03-15 21:33:54,320 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 67 SyntacticMatches, 6 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2022-03-15 21:33:54,321 INFO L933 BasicCegarLoop]: 3 mSDtfsCounter, 18 mSDsluCounter, 46 mSDsCounter, 0 mSdLazyCounter, 58 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 18 SdHoareTripleChecker+Valid, 12 SdHoareTripleChecker+Invalid, 60 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 58 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:33:54,321 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [18 Valid, 12 Invalid, 60 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 58 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-03-15 21:33:54,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states. [2022-03-15 21:33:54,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 194. [2022-03-15 21:33:54,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 194 states, 193 states have (on average 2.4093264248704664) internal successors, (465), 193 states have internal predecessors, (465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:54,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 465 transitions. [2022-03-15 21:33:54,336 INFO L78 Accepts]: Start accepts. Automaton has 194 states and 465 transitions. Word has length 19 [2022-03-15 21:33:54,336 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:33:54,336 INFO L470 AbstractCegarLoop]: Abstraction has 194 states and 465 transitions. [2022-03-15 21:33:54,336 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 5.6) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:54,337 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 465 transitions. [2022-03-15 21:33:54,338 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2022-03-15 21:33:54,338 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:33:54,338 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:33:54,354 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-03-15 21:33:54,538 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-03-15 21:33:54,539 INFO L402 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:33:54,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:33:54,539 INFO L85 PathProgramCache]: Analyzing trace with hash 50648689, now seen corresponding path program 3 times [2022-03-15 21:33:54,543 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:33:54,543 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265306822] [2022-03-15 21:33:54,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:33:54,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:33:54,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:33:54,684 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:33:54,684 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:33:54,684 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265306822] [2022-03-15 21:33:54,684 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1265306822] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:33:54,684 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [881314698] [2022-03-15 21:33:54,684 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:33:54,685 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:33:54,685 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:33:54,700 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:33:54,701 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-03-15 21:33:54,724 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-03-15 21:33:54,725 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:33:54,725 INFO L263 TraceCheckSpWp]: Trace formula consists of 70 conjuncts, 18 conjunts are in the unsatisfiable core [2022-03-15 21:33:54,726 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:33:55,094 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:33:55,095 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:33:55,095 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 13 [2022-03-15 21:33:55,156 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:33:55,157 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:33:55,339 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:33:55,340 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:33:55,354 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:33:55,354 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 2 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 4 case distinctions, treesize of input 23 treesize of output 47 [2022-03-15 21:33:55,533 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:33:55,533 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [881314698] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:33:55,533 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:33:55,533 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 25 [2022-03-15 21:33:55,533 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1276225301] [2022-03-15 21:33:55,534 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:33:55,535 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:33:55,542 INFO L252 McrAutomatonBuilder]: Finished intersection with 66 states and 121 transitions. [2022-03-15 21:33:55,542 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:33:56,888 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 9 new interpolants: [2019#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 2020#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not (= (select queue back) 1)) v_assert) (or (<= (+ d 1) W) (< 1 w) (not (= (select queue back) 1))) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1))), 2018#(and (or (= temp 1) (< 0 w)) (or (<= (+ d 1) W) (< 0 w)) (or v_assert (= temp 1)) (or (<= (+ d 1) W) v_assert)), 2025#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 2017#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 2022#(and (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)))), 2024#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 2023#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)))), 2021#(and (or (not v_assert) (<= (+ 2 d) W)) (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:33:56,889 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 20 states [2022-03-15 21:33:56,889 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:33:56,889 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-03-15 21:33:56,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=178, Invalid=1012, Unknown=0, NotChecked=0, Total=1190 [2022-03-15 21:33:56,890 INFO L87 Difference]: Start difference. First operand 194 states and 465 transitions. Second operand has 20 states, 20 states have (on average 3.35) internal successors, (67), 19 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:58,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:33:58,587 INFO L93 Difference]: Finished difference Result 545 states and 1274 transitions. [2022-03-15 21:33:58,587 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2022-03-15 21:33:58,588 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 3.35) internal successors, (67), 19 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2022-03-15 21:33:58,588 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:33:58,590 INFO L225 Difference]: With dead ends: 545 [2022-03-15 21:33:58,590 INFO L226 Difference]: Without dead ends: 475 [2022-03-15 21:33:58,592 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 54 SyntacticMatches, 7 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1277 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=949, Invalid=4163, Unknown=0, NotChecked=0, Total=5112 [2022-03-15 21:33:58,592 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 176 mSDsluCounter, 200 mSDsCounter, 0 mSdLazyCounter, 624 mSolverCounterSat, 112 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 176 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 736 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 112 IncrementalHoareTripleChecker+Valid, 624 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-03-15 21:33:58,592 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [176 Valid, 1 Invalid, 736 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [112 Valid, 624 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-03-15 21:33:58,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 475 states. [2022-03-15 21:33:58,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 475 to 233. [2022-03-15 21:33:58,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 233 states, 232 states have (on average 2.4094827586206895) internal successors, (559), 232 states have internal predecessors, (559), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:58,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233 states to 233 states and 559 transitions. [2022-03-15 21:33:58,604 INFO L78 Accepts]: Start accepts. Automaton has 233 states and 559 transitions. Word has length 21 [2022-03-15 21:33:58,604 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:33:58,604 INFO L470 AbstractCegarLoop]: Abstraction has 233 states and 559 transitions. [2022-03-15 21:33:58,604 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 20 states, 20 states have (on average 3.35) internal successors, (67), 19 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:33:58,604 INFO L276 IsEmpty]: Start isEmpty. Operand 233 states and 559 transitions. [2022-03-15 21:33:58,605 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2022-03-15 21:33:58,605 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:33:58,606 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:33:58,624 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2022-03-15 21:33:58,819 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:33:58,820 INFO L402 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:33:58,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:33:58,820 INFO L85 PathProgramCache]: Analyzing trace with hash -1288901501, now seen corresponding path program 4 times [2022-03-15 21:33:58,821 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:33:58,821 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296669560] [2022-03-15 21:33:58,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:33:58,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:33:58,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:33:58,945 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:33:58,945 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:33:58,945 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [296669560] [2022-03-15 21:33:58,946 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [296669560] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:33:58,946 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [783429375] [2022-03-15 21:33:58,946 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:33:58,946 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:33:58,946 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:33:58,960 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:33:59,004 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:33:59,004 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:33:59,005 INFO L263 TraceCheckSpWp]: Trace formula consists of 70 conjuncts, 18 conjunts are in the unsatisfiable core [2022-03-15 21:33:59,006 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:33:59,019 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-03-15 21:33:59,187 INFO L353 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2022-03-15 21:33:59,188 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 13 [2022-03-15 21:33:59,249 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:33:59,249 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:33:59,394 INFO L353 Elim1Store]: treesize reduction 24, result has 60.7 percent of original size [2022-03-15 21:33:59,394 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 27 treesize of output 51 [2022-03-15 21:33:59,564 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:33:59,565 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [783429375] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:33:59,565 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:33:59,565 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 25 [2022-03-15 21:33:59,565 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [387393786] [2022-03-15 21:33:59,565 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:33:59,567 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:33:59,571 INFO L252 McrAutomatonBuilder]: Finished intersection with 53 states and 91 transitions. [2022-03-15 21:33:59,571 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:00,312 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 8 new interpolants: [3260#(and (or (not v_assert) (<= (+ d temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 3258#(and (or (not v_assert) (<= (+ 2 d) W)) (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (= (select queue front) 1))), 3259#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 3262#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)))), 3263#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 3264#(and v_assert (< 0 w)), 3261#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 3257#(and (or (<= (+ d 1) W) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)))] [2022-03-15 21:34:00,313 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2022-03-15 21:34:00,313 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:00,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-03-15 21:34:00,314 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=988, Unknown=0, NotChecked=0, Total=1122 [2022-03-15 21:34:00,314 INFO L87 Difference]: Start difference. First operand 233 states and 559 transitions. Second operand has 19 states, 19 states have (on average 3.0) internal successors, (57), 18 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:01,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:01,635 INFO L93 Difference]: Finished difference Result 439 states and 1025 transitions. [2022-03-15 21:34:01,636 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2022-03-15 21:34:01,636 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 3.0) internal successors, (57), 18 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2022-03-15 21:34:01,636 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:01,638 INFO L225 Difference]: With dead ends: 439 [2022-03-15 21:34:01,638 INFO L226 Difference]: Without dead ends: 416 [2022-03-15 21:34:01,640 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 42 SyntacticMatches, 7 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1021 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=597, Invalid=3693, Unknown=0, NotChecked=0, Total=4290 [2022-03-15 21:34:01,640 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 169 mSDsluCounter, 211 mSDsCounter, 0 mSdLazyCounter, 693 mSolverCounterSat, 93 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 169 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 786 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 93 IncrementalHoareTripleChecker+Valid, 693 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:01,641 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [169 Valid, 1 Invalid, 786 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [93 Valid, 693 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-03-15 21:34:01,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 416 states. [2022-03-15 21:34:01,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 416 to 225. [2022-03-15 21:34:01,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225 states, 224 states have (on average 2.4017857142857144) internal successors, (538), 224 states have internal predecessors, (538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:01,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 538 transitions. [2022-03-15 21:34:01,650 INFO L78 Accepts]: Start accepts. Automaton has 225 states and 538 transitions. Word has length 21 [2022-03-15 21:34:01,650 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:01,650 INFO L470 AbstractCegarLoop]: Abstraction has 225 states and 538 transitions. [2022-03-15 21:34:01,651 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 19 states have (on average 3.0) internal successors, (57), 18 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:01,651 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 538 transitions. [2022-03-15 21:34:01,652 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2022-03-15 21:34:01,652 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:01,652 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:01,684 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-03-15 21:34:01,871 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:01,871 INFO L402 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:34:01,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:01,872 INFO L85 PathProgramCache]: Analyzing trace with hash -1644429525, now seen corresponding path program 5 times [2022-03-15 21:34:01,872 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:01,873 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1974592913] [2022-03-15 21:34:01,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:01,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:01,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:01,992 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:01,992 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:01,992 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1974592913] [2022-03-15 21:34:01,993 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1974592913] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:01,993 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1146557374] [2022-03-15 21:34:01,993 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:34:01,993 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:01,993 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:01,994 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:01,995 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-03-15 21:34:02,018 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 3 check-sat command(s) [2022-03-15 21:34:02,018 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:34:02,018 INFO L263 TraceCheckSpWp]: Trace formula consists of 70 conjuncts, 20 conjunts are in the unsatisfiable core [2022-03-15 21:34:02,019 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:02,199 INFO L353 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2022-03-15 21:34:02,200 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 13 [2022-03-15 21:34:02,257 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:02,257 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:34:02,392 INFO L353 Elim1Store]: treesize reduction 24, result has 60.7 percent of original size [2022-03-15 21:34:02,392 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 26 treesize of output 50 [2022-03-15 21:34:02,538 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:02,538 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1146557374] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:34:02,538 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:34:02,538 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 25 [2022-03-15 21:34:02,538 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [112025669] [2022-03-15 21:34:02,538 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:02,541 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:02,546 INFO L252 McrAutomatonBuilder]: Finished intersection with 66 states and 119 transitions. [2022-03-15 21:34:02,546 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:03,734 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 8 new interpolants: [4366#(and (or (= temp 1) (< 0 w)) (or (<= (+ d 1) W) (< 0 w)) (or v_assert (= temp 1)) (or (<= (+ d 1) W) v_assert)), 4364#(and (or (not v_assert) (<= (+ 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 4368#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 4367#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 4365#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 4371#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 4370#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 4369#(and (or (not v_assert) (<= (+ 2 d) W)) (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:34:03,734 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2022-03-15 21:34:03,734 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:03,735 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-03-15 21:34:03,735 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=146, Invalid=976, Unknown=0, NotChecked=0, Total=1122 [2022-03-15 21:34:03,735 INFO L87 Difference]: Start difference. First operand 225 states and 538 transitions. Second operand has 19 states, 19 states have (on average 3.473684210526316) internal successors, (66), 18 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:04,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:04,666 INFO L93 Difference]: Finished difference Result 495 states and 1139 transitions. [2022-03-15 21:34:04,667 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2022-03-15 21:34:04,667 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 3.473684210526316) internal successors, (66), 18 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 21 [2022-03-15 21:34:04,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:04,669 INFO L225 Difference]: With dead ends: 495 [2022-03-15 21:34:04,669 INFO L226 Difference]: Without dead ends: 463 [2022-03-15 21:34:04,669 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 121 GetRequests, 56 SyntacticMatches, 6 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 839 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=548, Invalid=3112, Unknown=0, NotChecked=0, Total=3660 [2022-03-15 21:34:04,670 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 134 mSDsluCounter, 216 mSDsCounter, 0 mSdLazyCounter, 723 mSolverCounterSat, 63 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 134 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 786 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 63 IncrementalHoareTripleChecker+Valid, 723 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:04,670 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [134 Valid, 1 Invalid, 786 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [63 Valid, 723 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-03-15 21:34:04,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463 states. [2022-03-15 21:34:04,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463 to 239. [2022-03-15 21:34:04,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 239 states, 238 states have (on average 2.403361344537815) internal successors, (572), 238 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:04,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 239 states to 239 states and 572 transitions. [2022-03-15 21:34:04,679 INFO L78 Accepts]: Start accepts. Automaton has 239 states and 572 transitions. Word has length 21 [2022-03-15 21:34:04,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:04,679 INFO L470 AbstractCegarLoop]: Abstraction has 239 states and 572 transitions. [2022-03-15 21:34:04,679 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 19 states have (on average 3.473684210526316) internal successors, (66), 18 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:04,679 INFO L276 IsEmpty]: Start isEmpty. Operand 239 states and 572 transitions. [2022-03-15 21:34:04,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2022-03-15 21:34:04,680 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:04,680 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:04,697 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-03-15 21:34:04,896 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:04,897 INFO L402 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:34:04,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:04,897 INFO L85 PathProgramCache]: Analyzing trace with hash 554377598, now seen corresponding path program 6 times [2022-03-15 21:34:04,898 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:04,898 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1432671549] [2022-03-15 21:34:04,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:04,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:04,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:04,948 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 10 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:04,948 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:04,948 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1432671549] [2022-03-15 21:34:04,948 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1432671549] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:04,948 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1313997588] [2022-03-15 21:34:04,949 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:34:04,949 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:04,949 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:04,964 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:04,965 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-03-15 21:34:04,991 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 3 check-sat command(s) [2022-03-15 21:34:04,992 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:34:04,992 INFO L263 TraceCheckSpWp]: Trace formula consists of 78 conjuncts, 6 conjunts are in the unsatisfiable core [2022-03-15 21:34:04,993 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:05,028 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 10 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:34:05,028 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:34:05,076 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 10 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:34:05,076 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1313997588] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:34:05,076 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:34:05,077 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4, 4] total 5 [2022-03-15 21:34:05,077 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1463060679] [2022-03-15 21:34:05,077 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:05,078 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:05,087 INFO L252 McrAutomatonBuilder]: Finished intersection with 81 states and 149 transitions. [2022-03-15 21:34:05,088 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:05,370 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 0 new interpolants: [] [2022-03-15 21:34:05,370 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-03-15 21:34:05,370 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:05,371 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-03-15 21:34:05,371 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2022-03-15 21:34:05,371 INFO L87 Difference]: Start difference. First operand 239 states and 572 transitions. Second operand has 6 states, 6 states have (on average 6.166666666666667) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:05,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:05,401 INFO L93 Difference]: Finished difference Result 502 states and 1170 transitions. [2022-03-15 21:34:05,401 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-03-15 21:34:05,401 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 6.166666666666667) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 24 [2022-03-15 21:34:05,401 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:05,403 INFO L225 Difference]: With dead ends: 502 [2022-03-15 21:34:05,403 INFO L226 Difference]: Without dead ends: 471 [2022-03-15 21:34:05,403 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 98 SyntacticMatches, 6 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2022-03-15 21:34:05,403 INFO L933 BasicCegarLoop]: 3 mSDtfsCounter, 31 mSDsluCounter, 48 mSDsCounter, 0 mSdLazyCounter, 62 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 31 SdHoareTripleChecker+Valid, 12 SdHoareTripleChecker+Invalid, 66 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 62 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:05,404 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [31 Valid, 12 Invalid, 66 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 62 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-03-15 21:34:05,405 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 471 states. [2022-03-15 21:34:05,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 471 to 319. [2022-03-15 21:34:05,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 319 states, 318 states have (on average 2.4465408805031448) internal successors, (778), 318 states have internal predecessors, (778), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:05,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 319 states to 319 states and 778 transitions. [2022-03-15 21:34:05,411 INFO L78 Accepts]: Start accepts. Automaton has 319 states and 778 transitions. Word has length 24 [2022-03-15 21:34:05,412 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:05,412 INFO L470 AbstractCegarLoop]: Abstraction has 319 states and 778 transitions. [2022-03-15 21:34:05,413 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 6.166666666666667) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:05,413 INFO L276 IsEmpty]: Start isEmpty. Operand 319 states and 778 transitions. [2022-03-15 21:34:05,413 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2022-03-15 21:34:05,414 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:05,414 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:05,445 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-03-15 21:34:05,630 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:05,630 INFO L402 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:34:05,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:05,631 INFO L85 PathProgramCache]: Analyzing trace with hash -800511665, now seen corresponding path program 7 times [2022-03-15 21:34:05,631 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:05,631 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741302844] [2022-03-15 21:34:05,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:05,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:05,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:05,829 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 1 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:05,830 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:05,830 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [741302844] [2022-03-15 21:34:05,830 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [741302844] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:05,830 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [104400507] [2022-03-15 21:34:05,830 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-03-15 21:34:05,830 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:05,830 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:05,831 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:05,832 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-03-15 21:34:05,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:05,855 INFO L263 TraceCheckSpWp]: Trace formula consists of 86 conjuncts, 26 conjunts are in the unsatisfiable core [2022-03-15 21:34:05,856 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:06,186 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:34:06,186 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:34:06,242 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 2 proven. 19 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:06,242 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:34:06,532 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:34:06,533 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 40 treesize of output 104 [2022-03-15 21:34:07,022 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 2 proven. 19 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:07,022 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [104400507] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:34:07,022 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:34:07,022 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 34 [2022-03-15 21:34:07,022 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [775377531] [2022-03-15 21:34:07,022 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:07,024 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:07,032 INFO L252 McrAutomatonBuilder]: Finished intersection with 93 states and 177 transitions. [2022-03-15 21:34:07,032 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:10,272 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 11 new interpolants: [6872#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 6876#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 6871#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 6873#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (<= (+ 2 d) W) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 6868#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 6870#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 6875#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ 2 d) W) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)))), 6869#(and (or (= temp 1) (< 0 w)) (or (<= (+ d 1) W) (< 0 w)) (or v_assert (= temp 1)) (or (<= (+ d 1) W) v_assert)), 6874#(and (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1))), 6878#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 6877#(and (or (not v_assert) (not (< 0 w)) (<= front back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W)) (or (not v_assert) (not (< 0 w)) (<= back front)))] [2022-03-15 21:34:10,272 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 25 states [2022-03-15 21:34:10,272 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:10,273 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-03-15 21:34:10,273 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=250, Invalid=1820, Unknown=0, NotChecked=0, Total=2070 [2022-03-15 21:34:10,273 INFO L87 Difference]: Start difference. First operand 319 states and 778 transitions. Second operand has 25 states, 25 states have (on average 3.48) internal successors, (87), 24 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:13,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:13,550 INFO L93 Difference]: Finished difference Result 1715 states and 4212 transitions. [2022-03-15 21:34:13,550 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2022-03-15 21:34:13,550 INFO L78 Accepts]: Start accepts. Automaton has has 25 states, 25 states have (on average 3.48) internal successors, (87), 24 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 26 [2022-03-15 21:34:13,550 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:13,555 INFO L225 Difference]: With dead ends: 1715 [2022-03-15 21:34:13,555 INFO L226 Difference]: Without dead ends: 1454 [2022-03-15 21:34:13,557 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 186 GetRequests, 70 SyntacticMatches, 15 SemanticMatches, 101 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3201 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=1686, Invalid=8820, Unknown=0, NotChecked=0, Total=10506 [2022-03-15 21:34:13,559 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 264 mSDsluCounter, 333 mSDsCounter, 0 mSdLazyCounter, 1355 mSolverCounterSat, 236 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 264 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 1591 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 236 IncrementalHoareTripleChecker+Valid, 1355 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:13,559 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [264 Valid, 1 Invalid, 1591 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [236 Valid, 1355 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-03-15 21:34:13,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1454 states. [2022-03-15 21:34:13,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1454 to 396. [2022-03-15 21:34:13,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 396 states, 395 states have (on average 2.4658227848101264) internal successors, (974), 395 states have internal predecessors, (974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:13,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 396 states to 396 states and 974 transitions. [2022-03-15 21:34:13,573 INFO L78 Accepts]: Start accepts. Automaton has 396 states and 974 transitions. Word has length 26 [2022-03-15 21:34:13,573 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:13,573 INFO L470 AbstractCegarLoop]: Abstraction has 396 states and 974 transitions. [2022-03-15 21:34:13,573 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 25 states, 25 states have (on average 3.48) internal successors, (87), 24 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:13,573 INFO L276 IsEmpty]: Start isEmpty. Operand 396 states and 974 transitions. [2022-03-15 21:34:13,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2022-03-15 21:34:13,575 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:13,575 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:13,591 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2022-03-15 21:34:13,790 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:13,791 INFO L402 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:34:13,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:13,791 INFO L85 PathProgramCache]: Analyzing trace with hash 117900693, now seen corresponding path program 8 times [2022-03-15 21:34:13,792 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:13,792 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646444043] [2022-03-15 21:34:13,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:13,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:13,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:13,994 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 1 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:13,994 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:13,994 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [646444043] [2022-03-15 21:34:13,994 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [646444043] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:13,994 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1943520393] [2022-03-15 21:34:13,994 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:34:13,994 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:13,994 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:13,995 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:13,996 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-03-15 21:34:14,018 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:34:14,019 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:34:14,019 INFO L263 TraceCheckSpWp]: Trace formula consists of 86 conjuncts, 26 conjunts are in the unsatisfiable core [2022-03-15 21:34:14,020 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:14,359 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:34:14,360 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:34:14,413 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 2 proven. 19 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:14,413 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:34:14,713 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:34:14,714 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 40 treesize of output 104 [2022-03-15 21:34:15,178 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:15,178 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1943520393] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:34:15,178 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:34:15,178 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 34 [2022-03-15 21:34:15,178 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [997364388] [2022-03-15 21:34:15,178 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:15,180 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:15,188 INFO L252 McrAutomatonBuilder]: Finished intersection with 90 states and 171 transitions. [2022-03-15 21:34:15,188 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:16,903 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 11 new interpolants: [9688#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)))), 9685#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 9686#(and (or (not v_assert) (<= (+ d temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 9692#(and (or (= temp 1) (< 0 w)) (or (<= (+ d 1) W) (< 0 w)) (or v_assert (= temp 1)) (or (<= (+ d 1) W) v_assert)), 9695#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 9687#(and (or (<= (+ d 1) W) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0))), 9689#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)))), 9691#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 9693#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 9690#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= front back)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 1 w)) (not (= (select queue back) 1)))), 9694#(and (or (not v_assert) (not (< 0 w)) (<= front back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W)) (or (not v_assert) (not (< 0 w)) (<= back front)))] [2022-03-15 21:34:16,903 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 25 states [2022-03-15 21:34:16,903 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:16,903 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-03-15 21:34:16,904 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=232, Invalid=1838, Unknown=0, NotChecked=0, Total=2070 [2022-03-15 21:34:16,904 INFO L87 Difference]: Start difference. First operand 396 states and 974 transitions. Second operand has 25 states, 25 states have (on average 3.44) internal successors, (86), 24 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:18,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:18,785 INFO L93 Difference]: Finished difference Result 1186 states and 2952 transitions. [2022-03-15 21:34:18,786 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2022-03-15 21:34:18,786 INFO L78 Accepts]: Start accepts. Automaton has has 25 states, 25 states have (on average 3.44) internal successors, (86), 24 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 26 [2022-03-15 21:34:18,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:18,790 INFO L225 Difference]: With dead ends: 1186 [2022-03-15 21:34:18,790 INFO L226 Difference]: Without dead ends: 1076 [2022-03-15 21:34:18,792 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 169 GetRequests, 64 SyntacticMatches, 18 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2429 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=1196, Invalid=6636, Unknown=0, NotChecked=0, Total=7832 [2022-03-15 21:34:18,792 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 229 mSDsluCounter, 249 mSDsCounter, 0 mSdLazyCounter, 830 mSolverCounterSat, 148 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 229 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 978 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 148 IncrementalHoareTripleChecker+Valid, 830 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:18,793 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [229 Valid, 2 Invalid, 978 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [148 Valid, 830 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-03-15 21:34:18,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1076 states. [2022-03-15 21:34:18,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1076 to 368. [2022-03-15 21:34:18,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 368 states, 367 states have (on average 2.444141689373297) internal successors, (897), 367 states have internal predecessors, (897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:18,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 897 transitions. [2022-03-15 21:34:18,821 INFO L78 Accepts]: Start accepts. Automaton has 368 states and 897 transitions. Word has length 26 [2022-03-15 21:34:18,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:18,822 INFO L470 AbstractCegarLoop]: Abstraction has 368 states and 897 transitions. [2022-03-15 21:34:18,822 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 25 states, 25 states have (on average 3.44) internal successors, (86), 24 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:18,822 INFO L276 IsEmpty]: Start isEmpty. Operand 368 states and 897 transitions. [2022-03-15 21:34:18,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2022-03-15 21:34:18,823 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:18,823 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:18,857 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-03-15 21:34:19,024 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2022-03-15 21:34:19,024 INFO L402 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:34:19,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:19,024 INFO L85 PathProgramCache]: Analyzing trace with hash -259152169, now seen corresponding path program 9 times [2022-03-15 21:34:19,026 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:19,026 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800222408] [2022-03-15 21:34:19,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:19,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:19,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:19,174 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:34:19,174 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:19,174 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800222408] [2022-03-15 21:34:19,174 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800222408] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:19,174 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [552346146] [2022-03-15 21:34:19,175 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:34:19,175 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:19,175 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:19,176 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:19,177 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-03-15 21:34:19,225 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2022-03-15 21:34:19,225 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:34:19,226 INFO L263 TraceCheckSpWp]: Trace formula consists of 86 conjuncts, 27 conjunts are in the unsatisfiable core [2022-03-15 21:34:19,229 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:19,454 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:34:19,455 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:34:19,500 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:19,500 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:34:19,707 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:34:19,707 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 40 treesize of output 104 [2022-03-15 21:34:20,046 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:20,046 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [552346146] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:34:20,046 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:34:20,047 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13, 13] total 33 [2022-03-15 21:34:20,047 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [112048802] [2022-03-15 21:34:20,047 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:20,049 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:20,056 INFO L252 McrAutomatonBuilder]: Finished intersection with 71 states and 126 transitions. [2022-03-15 21:34:20,056 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:21,002 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 10 new interpolants: [11890#(and (or (not v_assert) (<= (+ 2 d) W)) (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (= (select queue front) 1))), 11889#(and (or (not v_assert) (<= (+ 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 11888#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 11894#(and (or (not v_assert) (not (< 0 w)) (<= front back)) (or (not v_assert) (<= (+ d w) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= back front))), 11893#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 11895#(and (or (not v_assert) (not (< 0 w)) (<= front back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W)) (or (not v_assert) (not (< 0 w)) (<= back front))), 11892#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ 2 d temp) W)) (or (not v_assert) (= (select queue front) 1))), 11891#(and (or (not v_assert) (<= (+ 2 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 11897#(and v_assert (< 0 w)), 11896#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w)))] [2022-03-15 21:34:21,003 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2022-03-15 21:34:21,003 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:21,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-03-15 21:34:21,003 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=184, Invalid=1708, Unknown=0, NotChecked=0, Total=1892 [2022-03-15 21:34:21,003 INFO L87 Difference]: Start difference. First operand 368 states and 897 transitions. Second operand has 23 states, 23 states have (on average 3.0869565217391304) internal successors, (71), 22 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:23,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:23,121 INFO L93 Difference]: Finished difference Result 1330 states and 3178 transitions. [2022-03-15 21:34:23,121 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2022-03-15 21:34:23,121 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 23 states have (on average 3.0869565217391304) internal successors, (71), 22 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 26 [2022-03-15 21:34:23,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:23,125 INFO L225 Difference]: With dead ends: 1330 [2022-03-15 21:34:23,125 INFO L226 Difference]: Without dead ends: 1074 [2022-03-15 21:34:23,127 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 155 GetRequests, 62 SyntacticMatches, 3 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1980 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1096, Invalid=7276, Unknown=0, NotChecked=0, Total=8372 [2022-03-15 21:34:23,127 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 234 mSDsluCounter, 371 mSDsCounter, 0 mSdLazyCounter, 1510 mSolverCounterSat, 165 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 234 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 1675 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 165 IncrementalHoareTripleChecker+Valid, 1510 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:23,127 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [234 Valid, 1 Invalid, 1675 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [165 Valid, 1510 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-03-15 21:34:23,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1074 states. [2022-03-15 21:34:23,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1074 to 326. [2022-03-15 21:34:23,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 326 states, 325 states have (on average 2.4584615384615383) internal successors, (799), 325 states have internal predecessors, (799), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:23,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 326 states to 326 states and 799 transitions. [2022-03-15 21:34:23,136 INFO L78 Accepts]: Start accepts. Automaton has 326 states and 799 transitions. Word has length 26 [2022-03-15 21:34:23,137 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:23,137 INFO L470 AbstractCegarLoop]: Abstraction has 326 states and 799 transitions. [2022-03-15 21:34:23,137 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 23 states have (on average 3.0869565217391304) internal successors, (71), 22 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:23,137 INFO L276 IsEmpty]: Start isEmpty. Operand 326 states and 799 transitions. [2022-03-15 21:34:23,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2022-03-15 21:34:23,137 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:23,137 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:23,164 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2022-03-15 21:34:23,354 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10,10 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:23,355 INFO L402 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:34:23,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:23,355 INFO L85 PathProgramCache]: Analyzing trace with hash 86075969, now seen corresponding path program 10 times [2022-03-15 21:34:23,355 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:23,356 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1734697682] [2022-03-15 21:34:23,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:23,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:23,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:23,556 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:23,556 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:23,556 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1734697682] [2022-03-15 21:34:23,556 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1734697682] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:23,556 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1616719578] [2022-03-15 21:34:23,556 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:34:23,557 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:23,557 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:23,558 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:23,588 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:34:23,588 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:34:23,588 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-03-15 21:34:23,589 INFO L263 TraceCheckSpWp]: Trace formula consists of 86 conjuncts, 26 conjunts are in the unsatisfiable core [2022-03-15 21:34:23,591 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:23,929 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:34:23,930 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:34:23,979 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:23,979 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:34:24,218 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:34:24,218 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 40 treesize of output 104 [2022-03-15 21:34:24,535 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 1 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:24,536 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1616719578] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:34:24,536 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:34:24,536 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 34 [2022-03-15 21:34:24,537 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1262785177] [2022-03-15 21:34:24,537 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:24,538 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:24,547 INFO L252 McrAutomatonBuilder]: Finished intersection with 91 states and 171 transitions. [2022-03-15 21:34:24,547 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:26,876 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 12 new interpolants: [14171#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 14162#(and (or (= temp 1) (< 0 w)) (or (<= (+ d 1) W) (< 0 w)) (or v_assert (= temp 1)) (or (<= (+ d 1) W) v_assert)), 14164#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 14165#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 14169#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 14172#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 14166#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (<= (+ 2 d) W) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 14168#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 14170#(and (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1))), 14163#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 14161#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 14167#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 3 d) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:34:26,876 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 26 states [2022-03-15 21:34:26,876 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:26,876 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-03-15 21:34:26,877 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=246, Invalid=1916, Unknown=0, NotChecked=0, Total=2162 [2022-03-15 21:34:26,877 INFO L87 Difference]: Start difference. First operand 326 states and 799 transitions. Second operand has 26 states, 26 states have (on average 3.423076923076923) internal successors, (89), 25 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:29,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:29,047 INFO L93 Difference]: Finished difference Result 1235 states and 3064 transitions. [2022-03-15 21:34:29,047 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2022-03-15 21:34:29,048 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 3.423076923076923) internal successors, (89), 25 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 26 [2022-03-15 21:34:29,048 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:29,052 INFO L225 Difference]: With dead ends: 1235 [2022-03-15 21:34:29,052 INFO L226 Difference]: Without dead ends: 1168 [2022-03-15 21:34:29,053 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 176 GetRequests, 73 SyntacticMatches, 9 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2257 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=1532, Invalid=7588, Unknown=0, NotChecked=0, Total=9120 [2022-03-15 21:34:29,053 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 224 mSDsluCounter, 322 mSDsCounter, 0 mSdLazyCounter, 1064 mSolverCounterSat, 138 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 224 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1202 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 138 IncrementalHoareTripleChecker+Valid, 1064 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:29,054 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [224 Valid, 2 Invalid, 1202 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [138 Valid, 1064 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-03-15 21:34:29,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1168 states. [2022-03-15 21:34:29,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1168 to 376. [2022-03-15 21:34:29,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 376 states, 375 states have (on average 2.456) internal successors, (921), 375 states have internal predecessors, (921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:29,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 376 states to 376 states and 921 transitions. [2022-03-15 21:34:29,063 INFO L78 Accepts]: Start accepts. Automaton has 376 states and 921 transitions. Word has length 26 [2022-03-15 21:34:29,063 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:29,063 INFO L470 AbstractCegarLoop]: Abstraction has 376 states and 921 transitions. [2022-03-15 21:34:29,063 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 26 states, 26 states have (on average 3.423076923076923) internal successors, (89), 25 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:29,063 INFO L276 IsEmpty]: Start isEmpty. Operand 376 states and 921 transitions. [2022-03-15 21:34:29,064 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2022-03-15 21:34:29,064 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:29,064 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:29,080 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-03-15 21:34:29,279 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable11 [2022-03-15 21:34:29,279 INFO L402 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:34:29,280 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:29,280 INFO L85 PathProgramCache]: Analyzing trace with hash -154284849, now seen corresponding path program 11 times [2022-03-15 21:34:29,280 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:29,280 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345851978] [2022-03-15 21:34:29,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:29,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:29,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:29,450 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:29,450 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:29,450 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345851978] [2022-03-15 21:34:29,450 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [345851978] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:29,450 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1701663436] [2022-03-15 21:34:29,450 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:34:29,450 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:29,450 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:29,451 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:29,452 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-03-15 21:34:29,480 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2022-03-15 21:34:29,480 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:34:29,481 INFO L263 TraceCheckSpWp]: Trace formula consists of 86 conjuncts, 26 conjunts are in the unsatisfiable core [2022-03-15 21:34:29,481 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:29,768 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:34:29,768 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:34:29,805 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:29,805 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:34:30,008 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:34:30,009 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 40 treesize of output 104 [2022-03-15 21:34:30,350 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 1 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:30,351 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1701663436] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:34:30,351 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:34:30,351 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 34 [2022-03-15 21:34:30,351 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1712377717] [2022-03-15 21:34:30,351 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:30,352 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:30,360 INFO L252 McrAutomatonBuilder]: Finished intersection with 88 states and 165 transitions. [2022-03-15 21:34:30,360 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:32,273 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 12 new interpolants: [16443#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 16453#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 16451#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 16449#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 3 d) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 16454#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 16452#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)))), 16447#(and (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)))), 16448#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)))), 16445#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 16444#(and (or (= temp 1) (< 0 w)) (or (<= (+ d 1) W) (< 0 w)) (or v_assert (= temp 1)) (or (<= (+ d 1) W) v_assert)), 16446#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not (= (select queue back) 1)) v_assert) (or (<= (+ d 1) W) (< 1 w) (not (= (select queue back) 1))) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1))), 16450#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:34:32,273 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 26 states [2022-03-15 21:34:32,273 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:32,274 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-03-15 21:34:32,274 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=246, Invalid=1916, Unknown=0, NotChecked=0, Total=2162 [2022-03-15 21:34:32,274 INFO L87 Difference]: Start difference. First operand 376 states and 921 transitions. Second operand has 26 states, 26 states have (on average 3.3461538461538463) internal successors, (87), 25 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:34,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:34,338 INFO L93 Difference]: Finished difference Result 1367 states and 3375 transitions. [2022-03-15 21:34:34,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2022-03-15 21:34:34,338 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 3.3461538461538463) internal successors, (87), 25 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 26 [2022-03-15 21:34:34,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:34,343 INFO L225 Difference]: With dead ends: 1367 [2022-03-15 21:34:34,343 INFO L226 Difference]: Without dead ends: 1314 [2022-03-15 21:34:34,343 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 171 GetRequests, 70 SyntacticMatches, 9 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2204 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=1349, Invalid=7393, Unknown=0, NotChecked=0, Total=8742 [2022-03-15 21:34:34,344 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 275 mSDsluCounter, 268 mSDsCounter, 0 mSdLazyCounter, 886 mSolverCounterSat, 175 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 275 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1061 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 175 IncrementalHoareTripleChecker+Valid, 886 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:34,344 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [275 Valid, 2 Invalid, 1061 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [175 Valid, 886 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-03-15 21:34:34,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1314 states. [2022-03-15 21:34:34,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1314 to 388. [2022-03-15 21:34:34,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 388 states, 387 states have (on average 2.44702842377261) internal successors, (947), 387 states have internal predecessors, (947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:34,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 388 states to 388 states and 947 transitions. [2022-03-15 21:34:34,353 INFO L78 Accepts]: Start accepts. Automaton has 388 states and 947 transitions. Word has length 26 [2022-03-15 21:34:34,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:34,353 INFO L470 AbstractCegarLoop]: Abstraction has 388 states and 947 transitions. [2022-03-15 21:34:34,353 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 26 states, 26 states have (on average 3.3461538461538463) internal successors, (87), 25 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:34,353 INFO L276 IsEmpty]: Start isEmpty. Operand 388 states and 947 transitions. [2022-03-15 21:34:34,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2022-03-15 21:34:34,354 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:34,354 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:34,389 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2022-03-15 21:34:34,570 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable12 [2022-03-15 21:34:34,570 INFO L402 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:34:34,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:34,570 INFO L85 PathProgramCache]: Analyzing trace with hash -1493835039, now seen corresponding path program 12 times [2022-03-15 21:34:34,571 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:34,571 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1491029135] [2022-03-15 21:34:34,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:34,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:34,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:34,761 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:34,761 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:34,762 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1491029135] [2022-03-15 21:34:34,762 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1491029135] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:34,762 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [478114699] [2022-03-15 21:34:34,762 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:34:34,762 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:34,762 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:34,771 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:34,809 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-03-15 21:34:34,815 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) [2022-03-15 21:34:34,815 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:34:34,815 INFO L263 TraceCheckSpWp]: Trace formula consists of 86 conjuncts, 26 conjunts are in the unsatisfiable core [2022-03-15 21:34:34,821 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:35,144 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:34:35,144 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:34:35,202 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:35,202 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:34:35,507 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:34:35,507 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 40 treesize of output 104 [2022-03-15 21:34:35,816 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 1 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:35,816 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [478114699] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:34:35,816 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:34:35,816 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 34 [2022-03-15 21:34:35,816 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [711709902] [2022-03-15 21:34:35,816 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:35,818 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:35,825 INFO L252 McrAutomatonBuilder]: Finished intersection with 75 states and 135 transitions. [2022-03-15 21:34:35,825 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:36,936 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 11 new interpolants: [18885#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 18878#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 18884#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)))), 18877#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 3 d) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 18881#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 18887#(and v_assert (< 0 w)), 18882#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 18886#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 18880#(and (or (<= (+ d 1) W) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0))), 18879#(and (or (not v_assert) (<= (+ d temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 18883#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))))] [2022-03-15 21:34:36,936 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 25 states [2022-03-15 21:34:36,936 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:36,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-03-15 21:34:36,937 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=207, Invalid=1863, Unknown=0, NotChecked=0, Total=2070 [2022-03-15 21:34:36,938 INFO L87 Difference]: Start difference. First operand 388 states and 947 transitions. Second operand has 25 states, 25 states have (on average 3.08) internal successors, (77), 24 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:38,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:38,312 INFO L93 Difference]: Finished difference Result 1075 states and 2633 transitions. [2022-03-15 21:34:38,312 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2022-03-15 21:34:38,312 INFO L78 Accepts]: Start accepts. Automaton has has 25 states, 25 states have (on average 3.08) internal successors, (77), 24 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 26 [2022-03-15 21:34:38,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:38,316 INFO L225 Difference]: With dead ends: 1075 [2022-03-15 21:34:38,316 INFO L226 Difference]: Without dead ends: 1058 [2022-03-15 21:34:38,318 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 58 SyntacticMatches, 9 SemanticMatches, 83 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1723 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=875, Invalid=6265, Unknown=0, NotChecked=0, Total=7140 [2022-03-15 21:34:38,318 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 215 mSDsluCounter, 393 mSDsCounter, 0 mSdLazyCounter, 1253 mSolverCounterSat, 132 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 215 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1385 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 132 IncrementalHoareTripleChecker+Valid, 1253 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:38,319 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [215 Valid, 2 Invalid, 1385 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [132 Valid, 1253 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-03-15 21:34:38,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1058 states. [2022-03-15 21:34:38,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1058 to 388. [2022-03-15 21:34:38,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 388 states, 387 states have (on average 2.44702842377261) internal successors, (947), 387 states have internal predecessors, (947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:38,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 388 states to 388 states and 947 transitions. [2022-03-15 21:34:38,335 INFO L78 Accepts]: Start accepts. Automaton has 388 states and 947 transitions. Word has length 26 [2022-03-15 21:34:38,335 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:38,335 INFO L470 AbstractCegarLoop]: Abstraction has 388 states and 947 transitions. [2022-03-15 21:34:38,336 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 25 states, 25 states have (on average 3.08) internal successors, (77), 24 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:38,336 INFO L276 IsEmpty]: Start isEmpty. Operand 388 states and 947 transitions. [2022-03-15 21:34:38,336 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2022-03-15 21:34:38,336 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:38,336 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:38,358 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2022-03-15 21:34:38,559 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable13 [2022-03-15 21:34:38,559 INFO L402 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:34:38,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:38,560 INFO L85 PathProgramCache]: Analyzing trace with hash -1507076343, now seen corresponding path program 13 times [2022-03-15 21:34:38,560 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:38,561 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563843996] [2022-03-15 21:34:38,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:38,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:38,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:38,772 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:38,772 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:38,772 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1563843996] [2022-03-15 21:34:38,772 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1563843996] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:38,772 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1578826451] [2022-03-15 21:34:38,772 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-03-15 21:34:38,772 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:38,772 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:38,788 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:38,843 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-03-15 21:34:38,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:38,864 INFO L263 TraceCheckSpWp]: Trace formula consists of 86 conjuncts, 26 conjunts are in the unsatisfiable core [2022-03-15 21:34:38,865 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:39,185 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:34:39,185 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:34:39,245 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:39,245 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:34:39,505 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:34:39,505 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 40 treesize of output 104 [2022-03-15 21:34:39,976 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 1 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:39,976 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1578826451] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:34:39,977 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:34:39,977 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 34 [2022-03-15 21:34:39,977 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [329552882] [2022-03-15 21:34:39,977 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:39,978 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:39,985 INFO L252 McrAutomatonBuilder]: Finished intersection with 69 states and 120 transitions. [2022-03-15 21:34:39,985 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:41,029 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 9 new interpolants: [21007#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)))), 21003#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 21005#(and (or (not v_assert) (<= (+ 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 21009#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 21010#(and v_assert (< 0 w)), 21004#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 21006#(and (or (not v_assert) (<= (+ 2 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 21008#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 21002#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 3 d) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:34:41,030 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2022-03-15 21:34:41,030 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:41,030 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-03-15 21:34:41,030 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=1702, Unknown=0, NotChecked=0, Total=1892 [2022-03-15 21:34:41,030 INFO L87 Difference]: Start difference. First operand 388 states and 947 transitions. Second operand has 23 states, 23 states have (on average 3.0434782608695654) internal successors, (70), 22 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:42,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:42,322 INFO L93 Difference]: Finished difference Result 947 states and 2323 transitions. [2022-03-15 21:34:42,322 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2022-03-15 21:34:42,330 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 23 states have (on average 3.0434782608695654) internal successors, (70), 22 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 26 [2022-03-15 21:34:42,330 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:42,333 INFO L225 Difference]: With dead ends: 947 [2022-03-15 21:34:42,333 INFO L226 Difference]: Without dead ends: 930 [2022-03-15 21:34:42,334 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 141 GetRequests, 60 SyntacticMatches, 3 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1225 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=841, Invalid=5479, Unknown=0, NotChecked=0, Total=6320 [2022-03-15 21:34:42,334 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 202 mSDsluCounter, 278 mSDsCounter, 0 mSdLazyCounter, 863 mSolverCounterSat, 108 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 202 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 971 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 108 IncrementalHoareTripleChecker+Valid, 863 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:42,334 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [202 Valid, 2 Invalid, 971 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [108 Valid, 863 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-03-15 21:34:42,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 930 states. [2022-03-15 21:34:42,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 930 to 374. [2022-03-15 21:34:42,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 374 states, 373 states have (on average 2.442359249329759) internal successors, (911), 373 states have internal predecessors, (911), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:42,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 374 states to 374 states and 911 transitions. [2022-03-15 21:34:42,341 INFO L78 Accepts]: Start accepts. Automaton has 374 states and 911 transitions. Word has length 26 [2022-03-15 21:34:42,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:42,341 INFO L470 AbstractCegarLoop]: Abstraction has 374 states and 911 transitions. [2022-03-15 21:34:42,342 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 23 states have (on average 3.0434782608695654) internal successors, (70), 22 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:42,342 INFO L276 IsEmpty]: Start isEmpty. Operand 374 states and 911 transitions. [2022-03-15 21:34:42,342 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2022-03-15 21:34:42,342 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:42,342 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:42,359 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2022-03-15 21:34:42,558 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable14 [2022-03-15 21:34:42,559 INFO L402 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:34:42,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:42,559 INFO L85 PathProgramCache]: Analyzing trace with hash -2058498233, now seen corresponding path program 14 times [2022-03-15 21:34:42,560 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:42,560 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [478930551] [2022-03-15 21:34:42,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:42,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:42,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:42,733 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:42,734 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:42,734 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [478930551] [2022-03-15 21:34:42,734 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [478930551] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:42,734 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [829267746] [2022-03-15 21:34:42,734 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:34:42,734 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:42,734 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:42,735 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:42,736 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-03-15 21:34:42,758 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:34:42,758 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:34:42,759 INFO L263 TraceCheckSpWp]: Trace formula consists of 86 conjuncts, 28 conjunts are in the unsatisfiable core [2022-03-15 21:34:42,759 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:43,081 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:34:43,082 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:34:43,082 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:34:43,083 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:34:43,083 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 3 disjoint index pairs (out of 6 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 18 [2022-03-15 21:34:43,139 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:43,139 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:34:43,438 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:34:43,439 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:34:43,441 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:34:43,441 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:34:43,441 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:34:43,442 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:34:43,442 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:34:43,443 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:34:43,443 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:34:43,457 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:34:43,457 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 9 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 6 case distinctions, treesize of input 38 treesize of output 78 [2022-03-15 21:34:43,702 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:43,702 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [829267746] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:34:43,702 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:34:43,702 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 34 [2022-03-15 21:34:43,702 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1825325446] [2022-03-15 21:34:43,703 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:43,704 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:43,712 INFO L252 McrAutomatonBuilder]: Finished intersection with 91 states and 169 transitions. [2022-03-15 21:34:43,712 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:45,256 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 11 new interpolants: [22971#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 22967#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 22973#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 22964#(and (or (= temp 1) (< 0 w)) (or (<= (+ d 1) W) (< 0 w)) (or v_assert (= temp 1)) (or (<= (+ d 1) W) v_assert)), 22972#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 22966#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 22970#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 3 d) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 22963#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 22965#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 22969#(and (or (not v_assert) (<= (+ 3 d) W)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 22968#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (+ (- 1) temp) 0) v_assert) (or v_assert (<= (+ 2 d temp) W)) (or (= (select queue front) 1) (< 0 w)) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ 2 d temp) W) (< 0 w)))] [2022-03-15 21:34:45,256 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 25 states [2022-03-15 21:34:45,256 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:45,256 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-03-15 21:34:45,257 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=267, Invalid=1803, Unknown=0, NotChecked=0, Total=2070 [2022-03-15 21:34:45,257 INFO L87 Difference]: Start difference. First operand 374 states and 911 transitions. Second operand has 25 states, 25 states have (on average 3.52) internal successors, (88), 24 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:47,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:47,351 INFO L93 Difference]: Finished difference Result 1403 states and 3287 transitions. [2022-03-15 21:34:47,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2022-03-15 21:34:47,361 INFO L78 Accepts]: Start accepts. Automaton has has 25 states, 25 states have (on average 3.52) internal successors, (88), 24 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 26 [2022-03-15 21:34:47,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:47,365 INFO L225 Difference]: With dead ends: 1403 [2022-03-15 21:34:47,365 INFO L226 Difference]: Without dead ends: 1367 [2022-03-15 21:34:47,366 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 173 GetRequests, 75 SyntacticMatches, 8 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2059 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=1403, Invalid=6969, Unknown=0, NotChecked=0, Total=8372 [2022-03-15 21:34:47,366 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 187 mSDsluCounter, 322 mSDsCounter, 0 mSdLazyCounter, 1102 mSolverCounterSat, 107 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 187 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 1209 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 107 IncrementalHoareTripleChecker+Valid, 1102 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:47,368 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [187 Valid, 1 Invalid, 1209 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [107 Valid, 1102 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-03-15 21:34:47,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1367 states. [2022-03-15 21:34:47,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1367 to 388. [2022-03-15 21:34:47,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 388 states, 387 states have (on average 2.441860465116279) internal successors, (945), 387 states have internal predecessors, (945), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:47,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 388 states to 388 states and 945 transitions. [2022-03-15 21:34:47,407 INFO L78 Accepts]: Start accepts. Automaton has 388 states and 945 transitions. Word has length 26 [2022-03-15 21:34:47,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:47,407 INFO L470 AbstractCegarLoop]: Abstraction has 388 states and 945 transitions. [2022-03-15 21:34:47,407 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 25 states, 25 states have (on average 3.52) internal successors, (88), 24 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:47,407 INFO L276 IsEmpty]: Start isEmpty. Operand 388 states and 945 transitions. [2022-03-15 21:34:47,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2022-03-15 21:34:47,411 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:47,411 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:47,430 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Forceful destruction successful, exit code 0 [2022-03-15 21:34:47,612 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15,15 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:47,612 INFO L402 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:34:47,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:47,612 INFO L85 PathProgramCache]: Analyzing trace with hash 179571682, now seen corresponding path program 15 times [2022-03-15 21:34:47,613 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:47,613 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635770290] [2022-03-15 21:34:47,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:47,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:47,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:47,640 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 19 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:47,640 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:47,641 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1635770290] [2022-03-15 21:34:47,641 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1635770290] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:47,641 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1750595068] [2022-03-15 21:34:47,641 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:34:47,641 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:47,641 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:47,655 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:47,656 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-03-15 21:34:47,678 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2022-03-15 21:34:47,679 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:34:47,679 INFO L263 TraceCheckSpWp]: Trace formula consists of 94 conjuncts, 8 conjunts are in the unsatisfiable core [2022-03-15 21:34:47,679 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:47,709 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 19 proven. 11 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:34:47,709 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:34:47,740 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 19 proven. 11 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:34:47,740 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1750595068] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:34:47,740 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:34:47,740 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5] total 6 [2022-03-15 21:34:47,740 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1618769796] [2022-03-15 21:34:47,740 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:47,742 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:47,752 INFO L252 McrAutomatonBuilder]: Finished intersection with 106 states and 199 transitions. [2022-03-15 21:34:47,753 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:48,111 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 0 new interpolants: [] [2022-03-15 21:34:48,112 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-03-15 21:34:48,112 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:48,112 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-03-15 21:34:48,112 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2022-03-15 21:34:48,112 INFO L87 Difference]: Start difference. First operand 388 states and 945 transitions. Second operand has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 6 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:48,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:48,164 INFO L93 Difference]: Finished difference Result 782 states and 1854 transitions. [2022-03-15 21:34:48,164 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-03-15 21:34:48,164 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 6 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 29 [2022-03-15 21:34:48,164 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:48,166 INFO L225 Difference]: With dead ends: 782 [2022-03-15 21:34:48,166 INFO L226 Difference]: Without dead ends: 742 [2022-03-15 21:34:48,167 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 140 GetRequests, 129 SyntacticMatches, 6 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2022-03-15 21:34:48,167 INFO L933 BasicCegarLoop]: 3 mSDtfsCounter, 40 mSDsluCounter, 74 mSDsCounter, 0 mSdLazyCounter, 88 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 18 SdHoareTripleChecker+Invalid, 94 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 88 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:48,167 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [40 Valid, 18 Invalid, 94 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 88 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-03-15 21:34:48,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 742 states. [2022-03-15 21:34:48,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 742 to 489. [2022-03-15 21:34:48,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 489 states, 488 states have (on average 2.4631147540983607) internal successors, (1202), 488 states have internal predecessors, (1202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:48,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 489 states to 489 states and 1202 transitions. [2022-03-15 21:34:48,188 INFO L78 Accepts]: Start accepts. Automaton has 489 states and 1202 transitions. Word has length 29 [2022-03-15 21:34:48,188 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:48,188 INFO L470 AbstractCegarLoop]: Abstraction has 489 states and 1202 transitions. [2022-03-15 21:34:48,188 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 6 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:48,188 INFO L276 IsEmpty]: Start isEmpty. Operand 489 states and 1202 transitions. [2022-03-15 21:34:48,190 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:34:48,190 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:48,190 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:48,209 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Forceful destruction successful, exit code 0 [2022-03-15 21:34:48,409 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable16 [2022-03-15 21:34:48,410 INFO L402 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:34:48,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:48,410 INFO L85 PathProgramCache]: Analyzing trace with hash 1608586851, now seen corresponding path program 16 times [2022-03-15 21:34:48,411 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:48,411 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1295608776] [2022-03-15 21:34:48,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:48,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:48,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:48,646 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 1 proven. 37 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:48,646 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:48,646 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1295608776] [2022-03-15 21:34:48,647 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1295608776] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:48,647 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [99755875] [2022-03-15 21:34:48,647 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:34:48,647 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:48,647 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:48,648 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:48,649 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-03-15 21:34:48,673 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:34:48,673 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:34:48,673 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:34:48,674 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:49,207 INFO L353 Elim1Store]: treesize reduction 66, result has 1.5 percent of original size [2022-03-15 21:34:49,207 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 50 treesize of output 22 [2022-03-15 21:34:49,270 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 2 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:49,270 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:34:49,775 INFO L353 Elim1Store]: treesize reduction 156, result has 49.5 percent of original size [2022-03-15 21:34:49,776 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 53 treesize of output 177 [2022-03-15 21:34:51,160 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 6 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:51,160 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [99755875] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:34:51,160 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:34:51,160 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:34:51,160 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1074231908] [2022-03-15 21:34:51,160 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:51,162 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:51,187 INFO L252 McrAutomatonBuilder]: Finished intersection with 120 states and 233 transitions. [2022-03-15 21:34:51,187 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:55,974 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 14 new interpolants: [27416#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 27417#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 27408#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 27404#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 27414#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)))), 27411#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (= (select queue (+ 2 front)) 1)) (or (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not (= (select queue back) 1)) v_assert (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 27412#(and (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W))), 27413#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 27407#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 27410#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w))), 27409#(and (or (= temp 1) (< 0 w)) (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w)) (or v_assert (= temp 1))), 27406#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 27415#(and (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (= (select queue (+ 2 front)) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1)))), 27405#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert))] [2022-03-15 21:34:55,975 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 31 states [2022-03-15 21:34:55,975 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:55,975 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2022-03-15 21:34:55,975 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=361, Invalid=2945, Unknown=0, NotChecked=0, Total=3306 [2022-03-15 21:34:55,975 INFO L87 Difference]: Start difference. First operand 489 states and 1202 transitions. Second operand has 31 states, 31 states have (on average 3.5161290322580645) internal successors, (109), 30 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:02,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:35:02,929 INFO L93 Difference]: Finished difference Result 2442 states and 5984 transitions. [2022-03-15 21:35:02,929 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-03-15 21:35:02,929 INFO L78 Accepts]: Start accepts. Automaton has has 31 states, 31 states have (on average 3.5161290322580645) internal successors, (109), 30 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:35:02,930 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:35:02,936 INFO L225 Difference]: With dead ends: 2442 [2022-03-15 21:35:02,937 INFO L226 Difference]: Without dead ends: 2343 [2022-03-15 21:35:02,938 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 256 GetRequests, 83 SyntacticMatches, 25 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7082 ImplicationChecksByTransitivity, 7.8s TimeCoverageRelationStatistics Valid=3507, Invalid=18843, Unknown=0, NotChecked=0, Total=22350 [2022-03-15 21:35:02,939 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 350 mSDsluCounter, 437 mSDsCounter, 0 mSdLazyCounter, 1546 mSolverCounterSat, 307 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 350 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 1853 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 307 IncrementalHoareTripleChecker+Valid, 1546 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:35:02,939 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [350 Valid, 1 Invalid, 1853 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [307 Valid, 1546 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:35:02,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2343 states. [2022-03-15 21:35:02,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2343 to 612. [2022-03-15 21:35:02,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 612 states, 611 states have (on average 2.5155482815057284) internal successors, (1537), 611 states have internal predecessors, (1537), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:02,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 612 states to 612 states and 1537 transitions. [2022-03-15 21:35:02,956 INFO L78 Accepts]: Start accepts. Automaton has 612 states and 1537 transitions. Word has length 31 [2022-03-15 21:35:02,956 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:35:02,956 INFO L470 AbstractCegarLoop]: Abstraction has 612 states and 1537 transitions. [2022-03-15 21:35:02,956 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 31 states, 31 states have (on average 3.5161290322580645) internal successors, (109), 30 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:02,956 INFO L276 IsEmpty]: Start isEmpty. Operand 612 states and 1537 transitions. [2022-03-15 21:35:02,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:35:02,957 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:35:02,957 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:35:02,975 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Forceful destruction successful, exit code 0 [2022-03-15 21:35:03,171 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable17 [2022-03-15 21:35:03,171 INFO L402 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:35:03,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:35:03,172 INFO L85 PathProgramCache]: Analyzing trace with hash 729940245, now seen corresponding path program 17 times [2022-03-15 21:35:03,172 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:35:03,172 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1509939233] [2022-03-15 21:35:03,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:35:03,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:35:03,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:35:03,369 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 1 proven. 37 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:03,369 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:35:03,369 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1509939233] [2022-03-15 21:35:03,369 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1509939233] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:35:03,369 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [435091883] [2022-03-15 21:35:03,369 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:35:03,369 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:03,369 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:35:03,370 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:35:03,371 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-03-15 21:35:03,398 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2022-03-15 21:35:03,398 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:35:03,399 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 37 conjunts are in the unsatisfiable core [2022-03-15 21:35:03,399 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:35:04,002 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:35:04,003 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:35:04,007 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:35:04,008 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:35:04,008 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,009 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:35:04,009 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:35:04,010 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:35:04,011 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 6 disjoint index pairs (out of 10 index pairs), introduced 4 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 22 [2022-03-15 21:35:04,076 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 2 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:04,076 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:35:04,638 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,639 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,640 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,640 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,641 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,641 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,643 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,643 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,644 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,644 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,645 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,645 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,646 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,647 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,647 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,650 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,650 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,650 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:35:04,685 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:35:04,685 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 18 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 10 case distinctions, treesize of input 51 treesize of output 127 [2022-03-15 21:35:05,214 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:05,214 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [435091883] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:35:05,214 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:35:05,214 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:35:05,215 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [673556577] [2022-03-15 21:35:05,215 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:35:05,217 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:35:05,230 INFO L252 McrAutomatonBuilder]: Finished intersection with 117 states and 227 transitions. [2022-03-15 21:35:05,231 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:35:08,121 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 14 new interpolants: [31500#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 31499#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (= temp 1))), 31504#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 31493#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 31496#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 31503#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 31495#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 31498#(and (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1))), 31494#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 31492#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 31501#(and (or (not v_assert) (<= (+ front 1) back) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ front 1)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 3 d) W))), 31505#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 31502#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (<= front back) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ 3 d) W)) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= back front))), 31497#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (<= (+ 2 d) W) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1))))] [2022-03-15 21:35:08,122 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 31 states [2022-03-15 21:35:08,122 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:35:08,122 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2022-03-15 21:35:08,122 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=410, Invalid=2896, Unknown=0, NotChecked=0, Total=3306 [2022-03-15 21:35:08,122 INFO L87 Difference]: Start difference. First operand 612 states and 1537 transitions. Second operand has 31 states, 31 states have (on average 3.4516129032258065) internal successors, (107), 30 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:11,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:35:11,641 INFO L93 Difference]: Finished difference Result 2152 states and 5392 transitions. [2022-03-15 21:35:11,641 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2022-03-15 21:35:11,642 INFO L78 Accepts]: Start accepts. Automaton has has 31 states, 31 states have (on average 3.4516129032258065) internal successors, (107), 30 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:35:11,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:35:11,648 INFO L225 Difference]: With dead ends: 2152 [2022-03-15 21:35:11,648 INFO L226 Difference]: Without dead ends: 2094 [2022-03-15 21:35:11,650 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 231 GetRequests, 86 SyntacticMatches, 19 SemanticMatches, 126 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5031 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=2493, Invalid=13763, Unknown=0, NotChecked=0, Total=16256 [2022-03-15 21:35:11,651 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 316 mSDsluCounter, 355 mSDsCounter, 0 mSdLazyCounter, 1251 mSolverCounterSat, 274 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 316 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1525 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 274 IncrementalHoareTripleChecker+Valid, 1251 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-03-15 21:35:11,651 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [316 Valid, 2 Invalid, 1525 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [274 Valid, 1251 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-03-15 21:35:11,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2094 states. [2022-03-15 21:35:11,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2094 to 624. [2022-03-15 21:35:11,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 624 states, 623 states have (on average 2.5152487961476724) internal successors, (1567), 623 states have internal predecessors, (1567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:11,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 624 states to 624 states and 1567 transitions. [2022-03-15 21:35:11,665 INFO L78 Accepts]: Start accepts. Automaton has 624 states and 1567 transitions. Word has length 31 [2022-03-15 21:35:11,665 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:35:11,665 INFO L470 AbstractCegarLoop]: Abstraction has 624 states and 1567 transitions. [2022-03-15 21:35:11,665 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 31 states, 31 states have (on average 3.4516129032258065) internal successors, (107), 30 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:11,665 INFO L276 IsEmpty]: Start isEmpty. Operand 624 states and 1567 transitions. [2022-03-15 21:35:11,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:35:11,666 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:35:11,667 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:35:11,683 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Forceful destruction successful, exit code 0 [2022-03-15 21:35:11,882 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18,18 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:11,883 INFO L402 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:35:11,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:35:11,883 INFO L85 PathProgramCache]: Analyzing trace with hash 489579427, now seen corresponding path program 18 times [2022-03-15 21:35:11,884 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:35:11,884 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737296531] [2022-03-15 21:35:11,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:35:11,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:35:11,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:35:12,122 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 1 proven. 37 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:12,122 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:35:12,122 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [737296531] [2022-03-15 21:35:12,122 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [737296531] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:35:12,122 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1432673977] [2022-03-15 21:35:12,122 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:35:12,122 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:12,122 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:35:12,123 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:35:12,124 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-03-15 21:35:12,156 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2022-03-15 21:35:12,157 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:35:12,157 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:35:12,158 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:35:12,554 INFO L353 Elim1Store]: treesize reduction 66, result has 1.5 percent of original size [2022-03-15 21:35:12,555 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 50 treesize of output 22 [2022-03-15 21:35:12,602 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 2 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:12,602 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:35:13,023 INFO L353 Elim1Store]: treesize reduction 156, result has 49.5 percent of original size [2022-03-15 21:35:13,023 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 53 treesize of output 177 [2022-03-15 21:35:14,171 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 2 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:14,171 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1432673977] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:35:14,171 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:35:14,171 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:35:14,171 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [993897963] [2022-03-15 21:35:14,171 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:35:14,173 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:35:14,208 INFO L252 McrAutomatonBuilder]: Finished intersection with 114 states and 221 transitions. [2022-03-15 21:35:14,208 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:35:16,734 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 14 new interpolants: [35270#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 35279#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 35280#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ (select queue front) 2 d) W)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (+ 2 front) (+ back 1)))), 35282#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 35274#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 35278#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 35272#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 35283#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 35281#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (+ 2 back) (+ 2 front)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (<= (+ (select queue front) 2 d) W) (not (= (select queue (+ back 1)) 1)))), 35276#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 35271#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 35273#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not (= (select queue back) 1)) v_assert) (or (<= (+ d 1) W) (< 1 w) (not (= (select queue back) 1))) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1))), 35275#(and (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)))), 35277#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)))] [2022-03-15 21:35:16,734 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 31 states [2022-03-15 21:35:16,734 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:35:16,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2022-03-15 21:35:16,734 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=2965, Unknown=0, NotChecked=0, Total=3306 [2022-03-15 21:35:16,735 INFO L87 Difference]: Start difference. First operand 624 states and 1567 transitions. Second operand has 31 states, 31 states have (on average 3.3870967741935485) internal successors, (105), 30 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:20,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:35:20,127 INFO L93 Difference]: Finished difference Result 2100 states and 5216 transitions. [2022-03-15 21:35:20,127 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2022-03-15 21:35:20,127 INFO L78 Accepts]: Start accepts. Automaton has has 31 states, 31 states have (on average 3.3870967741935485) internal successors, (105), 30 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:35:20,127 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:35:20,134 INFO L225 Difference]: With dead ends: 2100 [2022-03-15 21:35:20,135 INFO L226 Difference]: Without dead ends: 2047 [2022-03-15 21:35:20,136 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 226 GetRequests, 79 SyntacticMatches, 23 SemanticMatches, 124 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4775 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=2159, Invalid=13591, Unknown=0, NotChecked=0, Total=15750 [2022-03-15 21:35:20,136 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 327 mSDsluCounter, 342 mSDsCounter, 0 mSdLazyCounter, 1139 mSolverCounterSat, 261 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 327 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1400 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 261 IncrementalHoareTripleChecker+Valid, 1139 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-03-15 21:35:20,136 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [327 Valid, 2 Invalid, 1400 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [261 Valid, 1139 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-03-15 21:35:20,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states. [2022-03-15 21:35:20,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 636. [2022-03-15 21:35:20,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 636 states, 635 states have (on average 2.5086614173228345) internal successors, (1593), 635 states have internal predecessors, (1593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:20,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 636 states to 636 states and 1593 transitions. [2022-03-15 21:35:20,156 INFO L78 Accepts]: Start accepts. Automaton has 636 states and 1593 transitions. Word has length 31 [2022-03-15 21:35:20,156 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:35:20,156 INFO L470 AbstractCegarLoop]: Abstraction has 636 states and 1593 transitions. [2022-03-15 21:35:20,157 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 31 states, 31 states have (on average 3.3870967741935485) internal successors, (105), 30 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:20,157 INFO L276 IsEmpty]: Start isEmpty. Operand 636 states and 1593 transitions. [2022-03-15 21:35:20,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:35:20,158 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:35:20,158 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:35:20,196 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Forceful destruction successful, exit code 0 [2022-03-15 21:35:20,371 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19,19 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:20,371 INFO L402 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:35:20,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:35:20,372 INFO L85 PathProgramCache]: Analyzing trace with hash -849970763, now seen corresponding path program 19 times [2022-03-15 21:35:20,373 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:35:20,373 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936682726] [2022-03-15 21:35:20,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:35:20,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:35:20,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:35:20,618 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 1 proven. 37 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:20,618 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:35:20,618 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [936682726] [2022-03-15 21:35:20,618 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [936682726] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:35:20,618 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1296563565] [2022-03-15 21:35:20,619 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-03-15 21:35:20,619 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:20,619 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:35:20,620 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:35:20,624 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-03-15 21:35:20,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:35:20,656 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:35:20,657 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:35:21,165 INFO L353 Elim1Store]: treesize reduction 66, result has 1.5 percent of original size [2022-03-15 21:35:21,165 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 50 treesize of output 22 [2022-03-15 21:35:21,231 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 2 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:21,231 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:35:21,795 INFO L353 Elim1Store]: treesize reduction 156, result has 49.5 percent of original size [2022-03-15 21:35:21,795 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 53 treesize of output 177 [2022-03-15 21:35:22,801 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 2 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:22,801 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1296563565] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:35:22,801 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:35:22,801 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:35:22,801 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [677485380] [2022-03-15 21:35:22,801 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:35:22,804 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:35:22,815 INFO L252 McrAutomatonBuilder]: Finished intersection with 101 states and 191 transitions. [2022-03-15 21:35:22,815 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:35:25,796 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 13 new interpolants: [39027#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 39022#(and (or (not v_assert) (<= (+ d temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 39017#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 39016#(and (or (<= (+ d 1) W) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= back front))), 39025#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 39018#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 39021#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 39020#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 39024#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (+ 2 back) (+ 2 front)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (<= (+ (select queue front) 2 d) W) (not (= (select queue (+ back 1)) 1)))), 39023#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ (select queue front) 2 d) W)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (+ 2 front) (+ back 1)))), 39028#(and v_assert (< 0 w)), 39019#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 39026#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:35:25,797 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 30 states [2022-03-15 21:35:25,797 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:35:25,797 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2022-03-15 21:35:25,797 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=296, Invalid=2896, Unknown=0, NotChecked=0, Total=3192 [2022-03-15 21:35:25,798 INFO L87 Difference]: Start difference. First operand 636 states and 1593 transitions. Second operand has 30 states, 30 states have (on average 3.1666666666666665) internal successors, (95), 29 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:28,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:35:28,760 INFO L93 Difference]: Finished difference Result 1617 states and 3996 transitions. [2022-03-15 21:35:28,760 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2022-03-15 21:35:28,760 INFO L78 Accepts]: Start accepts. Automaton has has 30 states, 30 states have (on average 3.1666666666666665) internal successors, (95), 29 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:35:28,761 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:35:28,764 INFO L225 Difference]: With dead ends: 1617 [2022-03-15 21:35:28,764 INFO L226 Difference]: Without dead ends: 1600 [2022-03-15 21:35:28,765 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 205 GetRequests, 68 SyntacticMatches, 22 SemanticMatches, 115 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4026 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=1501, Invalid=12071, Unknown=0, NotChecked=0, Total=13572 [2022-03-15 21:35:28,766 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 296 mSDsluCounter, 365 mSDsCounter, 0 mSdLazyCounter, 1183 mSolverCounterSat, 206 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 296 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1389 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 206 IncrementalHoareTripleChecker+Valid, 1183 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-03-15 21:35:28,766 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [296 Valid, 2 Invalid, 1389 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [206 Valid, 1183 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-03-15 21:35:28,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1600 states. [2022-03-15 21:35:28,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1600 to 624. [2022-03-15 21:35:28,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 624 states, 623 states have (on average 2.5152487961476724) internal successors, (1567), 623 states have internal predecessors, (1567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:28,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 624 states to 624 states and 1567 transitions. [2022-03-15 21:35:28,805 INFO L78 Accepts]: Start accepts. Automaton has 624 states and 1567 transitions. Word has length 31 [2022-03-15 21:35:28,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:35:28,806 INFO L470 AbstractCegarLoop]: Abstraction has 624 states and 1567 transitions. [2022-03-15 21:35:28,806 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 30 states, 30 states have (on average 3.1666666666666665) internal successors, (95), 29 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:28,806 INFO L276 IsEmpty]: Start isEmpty. Operand 624 states and 1567 transitions. [2022-03-15 21:35:28,807 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:35:28,807 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:35:28,807 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:35:28,841 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Forceful destruction successful, exit code 0 [2022-03-15 21:35:29,023 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20,20 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:29,023 INFO L402 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:35:29,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:35:29,023 INFO L85 PathProgramCache]: Analyzing trace with hash -863212067, now seen corresponding path program 20 times [2022-03-15 21:35:29,024 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:35:29,024 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1422909452] [2022-03-15 21:35:29,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:35:29,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:35:29,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:35:29,277 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 1 proven. 37 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:29,278 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:35:29,278 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1422909452] [2022-03-15 21:35:29,278 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1422909452] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:35:29,278 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2061309136] [2022-03-15 21:35:29,278 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:35:29,278 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:29,278 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:35:29,279 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:35:29,280 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-03-15 21:35:29,308 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:35:29,308 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:35:29,309 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:35:29,312 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:35:29,813 INFO L353 Elim1Store]: treesize reduction 66, result has 1.5 percent of original size [2022-03-15 21:35:29,813 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 50 treesize of output 22 [2022-03-15 21:35:29,891 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 2 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:29,891 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:35:30,379 INFO L353 Elim1Store]: treesize reduction 156, result has 49.5 percent of original size [2022-03-15 21:35:30,379 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 53 treesize of output 177 [2022-03-15 21:35:31,114 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 2 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:31,114 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2061309136] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:35:31,114 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:35:31,114 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:35:31,114 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1104334120] [2022-03-15 21:35:31,114 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:35:31,116 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:35:31,127 INFO L252 McrAutomatonBuilder]: Finished intersection with 95 states and 176 transitions. [2022-03-15 21:35:31,127 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:35:33,446 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 11 new interpolants: [42243#(and (or (not v_assert) (<= (+ front 1) back) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ front 1)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 3 d) W))), 42248#(and v_assert (< 0 w)), 42244#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (<= front back) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ 3 d) W)) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= back front))), 42245#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 42242#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 42246#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 42240#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)))), 42241#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 42238#(and (or (not v_assert) (<= (+ 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 42239#(and (or (not v_assert) (<= (+ 2 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 42247#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w)))] [2022-03-15 21:35:33,446 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 28 states [2022-03-15 21:35:33,447 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:35:33,447 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2022-03-15 21:35:33,447 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=2694, Unknown=0, NotChecked=0, Total=2970 [2022-03-15 21:35:33,447 INFO L87 Difference]: Start difference. First operand 624 states and 1567 transitions. Second operand has 28 states, 28 states have (on average 3.142857142857143) internal successors, (88), 27 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:35,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:35:35,885 INFO L93 Difference]: Finished difference Result 1481 states and 3670 transitions. [2022-03-15 21:35:35,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2022-03-15 21:35:35,885 INFO L78 Accepts]: Start accepts. Automaton has has 28 states, 28 states have (on average 3.142857142857143) internal successors, (88), 27 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:35:35,886 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:35:35,893 INFO L225 Difference]: With dead ends: 1481 [2022-03-15 21:35:35,893 INFO L226 Difference]: Without dead ends: 1464 [2022-03-15 21:35:35,894 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 197 GetRequests, 69 SyntacticMatches, 17 SemanticMatches, 111 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3497 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=1456, Invalid=11200, Unknown=0, NotChecked=0, Total=12656 [2022-03-15 21:35:35,894 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 330 mSDsluCounter, 318 mSDsCounter, 0 mSdLazyCounter, 1058 mSolverCounterSat, 267 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 330 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1325 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 267 IncrementalHoareTripleChecker+Valid, 1058 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-03-15 21:35:35,895 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [330 Valid, 2 Invalid, 1325 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [267 Valid, 1058 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-03-15 21:35:35,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1464 states. [2022-03-15 21:35:35,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1464 to 612. [2022-03-15 21:35:35,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 612 states, 611 states have (on average 2.5155482815057284) internal successors, (1537), 611 states have internal predecessors, (1537), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:35,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 612 states to 612 states and 1537 transitions. [2022-03-15 21:35:35,905 INFO L78 Accepts]: Start accepts. Automaton has 612 states and 1537 transitions. Word has length 31 [2022-03-15 21:35:35,905 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:35:35,905 INFO L470 AbstractCegarLoop]: Abstraction has 612 states and 1537 transitions. [2022-03-15 21:35:35,905 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 28 states, 28 states have (on average 3.142857142857143) internal successors, (88), 27 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:35,905 INFO L276 IsEmpty]: Start isEmpty. Operand 612 states and 1537 transitions. [2022-03-15 21:35:35,906 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:35:35,906 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:35:35,906 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:35:35,922 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Forceful destruction successful, exit code 0 [2022-03-15 21:35:36,119 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable21 [2022-03-15 21:35:36,119 INFO L402 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:35:36,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:35:36,120 INFO L85 PathProgramCache]: Analyzing trace with hash -197908299, now seen corresponding path program 21 times [2022-03-15 21:35:36,120 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:35:36,120 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436644092] [2022-03-15 21:35:36,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:35:36,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:35:36,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:35:36,360 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 1 proven. 37 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:36,361 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:35:36,361 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1436644092] [2022-03-15 21:35:36,361 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1436644092] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:35:36,361 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [221676351] [2022-03-15 21:35:36,361 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:35:36,361 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:36,361 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:35:36,362 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:35:36,363 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2022-03-15 21:35:36,389 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-03-15 21:35:36,389 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:35:36,390 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:35:36,391 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:35:36,895 INFO L353 Elim1Store]: treesize reduction 66, result has 1.5 percent of original size [2022-03-15 21:35:36,896 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 50 treesize of output 22 [2022-03-15 21:35:36,961 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 2 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:36,962 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:35:37,466 INFO L353 Elim1Store]: treesize reduction 156, result has 49.5 percent of original size [2022-03-15 21:35:37,467 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 53 treesize of output 177 [2022-03-15 21:35:39,017 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 2 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:39,018 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [221676351] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:35:39,018 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:35:39,018 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:35:39,018 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1798711591] [2022-03-15 21:35:39,018 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:35:39,020 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:35:39,031 INFO L252 McrAutomatonBuilder]: Finished intersection with 89 states and 161 transitions. [2022-03-15 21:35:39,031 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:35:41,614 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 9 new interpolants: [45295#(and (or (not v_assert) (<= (+ front 1) back) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ front 1)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 3 d) W))), 45296#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (<= front back) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ 3 d) W)) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= back front))), 45301#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 45298#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 45294#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 45302#(and v_assert (< 0 w)), 45297#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 45299#(and (or (not v_assert) (<= (+ 3 d) W)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 45300#(and (or (not v_assert) (<= (+ 3 d temp) W)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:35:41,614 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 26 states [2022-03-15 21:35:41,614 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:35:41,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-03-15 21:35:41,615 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=259, Invalid=2497, Unknown=0, NotChecked=0, Total=2756 [2022-03-15 21:35:41,615 INFO L87 Difference]: Start difference. First operand 612 states and 1537 transitions. Second operand has 26 states, 26 states have (on average 3.1153846153846154) internal successors, (81), 25 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:44,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:35:44,301 INFO L93 Difference]: Finished difference Result 1431 states and 3550 transitions. [2022-03-15 21:35:44,302 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2022-03-15 21:35:44,302 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 3.1153846153846154) internal successors, (81), 25 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:35:44,302 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:35:44,304 INFO L225 Difference]: With dead ends: 1431 [2022-03-15 21:35:44,304 INFO L226 Difference]: Without dead ends: 1414 [2022-03-15 21:35:44,305 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 192 GetRequests, 66 SyntacticMatches, 16 SemanticMatches, 110 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3321 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=1481, Invalid=10951, Unknown=0, NotChecked=0, Total=12432 [2022-03-15 21:35:44,305 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 296 mSDsluCounter, 426 mSDsCounter, 0 mSdLazyCounter, 1460 mSolverCounterSat, 232 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 296 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1692 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 232 IncrementalHoareTripleChecker+Valid, 1460 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-03-15 21:35:44,305 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [296 Valid, 2 Invalid, 1692 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [232 Valid, 1460 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-03-15 21:35:44,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1414 states. [2022-03-15 21:35:44,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1414 to 528. [2022-03-15 21:35:44,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 528 states, 527 states have (on average 2.4573055028463) internal successors, (1295), 527 states have internal predecessors, (1295), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:44,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 528 states to 528 states and 1295 transitions. [2022-03-15 21:35:44,324 INFO L78 Accepts]: Start accepts. Automaton has 528 states and 1295 transitions. Word has length 31 [2022-03-15 21:35:44,324 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:35:44,324 INFO L470 AbstractCegarLoop]: Abstraction has 528 states and 1295 transitions. [2022-03-15 21:35:44,324 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 26 states, 26 states have (on average 3.1153846153846154) internal successors, (81), 25 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:44,325 INFO L276 IsEmpty]: Start isEmpty. Operand 528 states and 1295 transitions. [2022-03-15 21:35:44,325 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:35:44,325 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:35:44,326 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:35:44,341 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Ended with exit code 0 [2022-03-15 21:35:44,531 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable22 [2022-03-15 21:35:44,531 INFO L402 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:35:44,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:35:44,531 INFO L85 PathProgramCache]: Analyzing trace with hash 1160092849, now seen corresponding path program 22 times [2022-03-15 21:35:44,532 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:35:44,532 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1326488234] [2022-03-15 21:35:44,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:35:44,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:35:44,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:35:44,774 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 2 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:44,774 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:35:44,774 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1326488234] [2022-03-15 21:35:44,774 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1326488234] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:35:44,774 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1764653798] [2022-03-15 21:35:44,774 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:35:44,775 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:44,775 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:35:44,776 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:35:44,776 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2022-03-15 21:35:44,800 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:35:44,801 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:35:44,801 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:35:44,802 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:35:45,241 INFO L353 Elim1Store]: treesize reduction 66, result has 1.5 percent of original size [2022-03-15 21:35:45,242 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 50 treesize of output 22 [2022-03-15 21:35:45,296 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 2 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:45,296 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:35:45,729 INFO L353 Elim1Store]: treesize reduction 156, result has 49.5 percent of original size [2022-03-15 21:35:45,729 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 53 treesize of output 177 [2022-03-15 21:35:47,401 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 3 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:47,401 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1764653798] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:35:47,401 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:35:47,401 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:35:47,401 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [584325892] [2022-03-15 21:35:47,402 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:35:47,404 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:35:47,416 INFO L252 McrAutomatonBuilder]: Finished intersection with 118 states and 227 transitions. [2022-03-15 21:35:47,417 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:35:51,314 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 14 new interpolants: [48135#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 48136#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 48141#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)))), 48133#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 48138#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w))), 48140#(and (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W))), 48144#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 48143#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 48139#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (= (select queue (+ 2 front)) 1)) (or (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not (= (select queue back) 1)) v_assert (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 48142#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 48145#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 48132#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 48134#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 48137#(and (or (= temp 1) (< 0 w)) (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w)) (or v_assert (= temp 1)))] [2022-03-15 21:35:51,315 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 31 states [2022-03-15 21:35:51,315 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:35:51,315 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2022-03-15 21:35:51,315 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=349, Invalid=2957, Unknown=0, NotChecked=0, Total=3306 [2022-03-15 21:35:51,315 INFO L87 Difference]: Start difference. First operand 528 states and 1295 transitions. Second operand has 31 states, 31 states have (on average 3.5161290322580645) internal successors, (109), 30 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:55,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:35:55,056 INFO L93 Difference]: Finished difference Result 2974 states and 7466 transitions. [2022-03-15 21:35:55,056 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2022-03-15 21:35:55,057 INFO L78 Accepts]: Start accepts. Automaton has has 31 states, 31 states have (on average 3.5161290322580645) internal successors, (109), 30 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:35:55,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:35:55,061 INFO L225 Difference]: With dead ends: 2974 [2022-03-15 21:35:55,061 INFO L226 Difference]: Without dead ends: 2712 [2022-03-15 21:35:55,062 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 226 GetRequests, 88 SyntacticMatches, 18 SemanticMatches, 120 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4523 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=2366, Invalid=12396, Unknown=0, NotChecked=0, Total=14762 [2022-03-15 21:35:55,063 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 269 mSDsluCounter, 364 mSDsCounter, 0 mSdLazyCounter, 1454 mSolverCounterSat, 213 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 269 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1667 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 213 IncrementalHoareTripleChecker+Valid, 1454 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-03-15 21:35:55,063 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [269 Valid, 2 Invalid, 1667 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [213 Valid, 1454 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-03-15 21:35:55,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2712 states. [2022-03-15 21:35:55,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2712 to 580. [2022-03-15 21:35:55,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 580 states, 579 states have (on average 2.461139896373057) internal successors, (1425), 579 states have internal predecessors, (1425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:55,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 580 states to 580 states and 1425 transitions. [2022-03-15 21:35:55,086 INFO L78 Accepts]: Start accepts. Automaton has 580 states and 1425 transitions. Word has length 31 [2022-03-15 21:35:55,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:35:55,086 INFO L470 AbstractCegarLoop]: Abstraction has 580 states and 1425 transitions. [2022-03-15 21:35:55,086 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 31 states, 31 states have (on average 3.5161290322580645) internal successors, (109), 30 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:55,086 INFO L276 IsEmpty]: Start isEmpty. Operand 580 states and 1425 transitions. [2022-03-15 21:35:55,087 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:35:55,087 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:35:55,087 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:35:55,105 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Forceful destruction successful, exit code 0 [2022-03-15 21:35:55,305 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23,23 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:55,306 INFO L402 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:35:55,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:35:55,308 INFO L85 PathProgramCache]: Analyzing trace with hash 41085425, now seen corresponding path program 23 times [2022-03-15 21:35:55,309 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:35:55,309 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [420281411] [2022-03-15 21:35:55,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:35:55,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:35:55,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:35:55,542 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 2 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:55,542 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:35:55,542 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [420281411] [2022-03-15 21:35:55,542 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [420281411] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:35:55,543 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1102807068] [2022-03-15 21:35:55,543 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:35:55,543 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:55,543 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:35:55,550 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:35:55,585 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-03-15 21:35:55,592 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2022-03-15 21:35:55,592 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:35:55,593 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:35:55,594 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:35:55,969 INFO L353 Elim1Store]: treesize reduction 66, result has 1.5 percent of original size [2022-03-15 21:35:55,969 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 50 treesize of output 22 [2022-03-15 21:35:56,022 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 2 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:56,022 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:35:56,403 INFO L353 Elim1Store]: treesize reduction 156, result has 49.5 percent of original size [2022-03-15 21:35:56,404 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 53 treesize of output 177 [2022-03-15 21:35:57,295 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 1 proven. 37 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:57,295 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1102807068] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:35:57,295 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:35:57,295 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:35:57,296 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1799595301] [2022-03-15 21:35:57,296 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:35:57,298 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:35:57,312 INFO L252 McrAutomatonBuilder]: Finished intersection with 112 states and 215 transitions. [2022-03-15 21:35:57,312 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:35:59,812 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 14 new interpolants: [52638#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 52634#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 52639#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 52640#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 52642#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 52644#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 52645#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 52635#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not (= (select queue back) 1)) v_assert) (or (<= (+ d 1) W) (< 1 w) (not (= (select queue back) 1))) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1))), 52637#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 52636#(and (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)))), 52643#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 52641#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ (select queue front) 2 d) W)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (+ 2 front) (+ back 1)))), 52632#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 52633#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert))] [2022-03-15 21:35:59,813 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 31 states [2022-03-15 21:35:59,814 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:35:59,814 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2022-03-15 21:35:59,814 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=337, Invalid=2969, Unknown=0, NotChecked=0, Total=3306 [2022-03-15 21:35:59,818 INFO L87 Difference]: Start difference. First operand 580 states and 1425 transitions. Second operand has 31 states, 31 states have (on average 3.3870967741935485) internal successors, (105), 30 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:01,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:36:01,726 INFO L93 Difference]: Finished difference Result 2129 states and 5257 transitions. [2022-03-15 21:36:01,726 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2022-03-15 21:36:01,727 INFO L78 Accepts]: Start accepts. Automaton has has 31 states, 31 states have (on average 3.3870967741935485) internal successors, (105), 30 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:36:01,727 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:36:01,730 INFO L225 Difference]: With dead ends: 2129 [2022-03-15 21:36:01,730 INFO L226 Difference]: Without dead ends: 2076 [2022-03-15 21:36:01,731 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 208 GetRequests, 82 SyntacticMatches, 18 SemanticMatches, 108 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3632 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1767, Invalid=10223, Unknown=0, NotChecked=0, Total=11990 [2022-03-15 21:36:01,731 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 273 mSDsluCounter, 356 mSDsCounter, 0 mSdLazyCounter, 1141 mSolverCounterSat, 181 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 273 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1322 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 181 IncrementalHoareTripleChecker+Valid, 1141 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-03-15 21:36:01,732 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [273 Valid, 2 Invalid, 1322 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [181 Valid, 1141 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-03-15 21:36:01,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2076 states. [2022-03-15 21:36:01,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2076 to 600. [2022-03-15 21:36:01,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 600 states, 599 states have (on average 2.4574290484140233) internal successors, (1472), 599 states have internal predecessors, (1472), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:01,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 600 states to 600 states and 1472 transitions. [2022-03-15 21:36:01,754 INFO L78 Accepts]: Start accepts. Automaton has 600 states and 1472 transitions. Word has length 31 [2022-03-15 21:36:01,754 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:36:01,754 INFO L470 AbstractCegarLoop]: Abstraction has 600 states and 1472 transitions. [2022-03-15 21:36:01,754 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 31 states, 31 states have (on average 3.3870967741935485) internal successors, (105), 30 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:01,755 INFO L276 IsEmpty]: Start isEmpty. Operand 600 states and 1472 transitions. [2022-03-15 21:36:01,755 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:36:01,756 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:36:01,756 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:36:01,773 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Forceful destruction successful, exit code 0 [2022-03-15 21:36:01,971 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable24,24 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:36:01,972 INFO L402 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:36:01,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:36:01,972 INFO L85 PathProgramCache]: Analyzing trace with hash -1298464765, now seen corresponding path program 24 times [2022-03-15 21:36:01,973 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:36:01,973 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2035715016] [2022-03-15 21:36:01,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:36:01,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:36:01,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:36:02,229 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 2 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:02,229 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:36:02,229 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2035715016] [2022-03-15 21:36:02,229 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2035715016] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:36:02,229 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1970227855] [2022-03-15 21:36:02,230 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:36:02,230 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:36:02,230 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:36:02,231 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:36:02,232 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2022-03-15 21:36:02,257 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2022-03-15 21:36:02,257 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:36:02,257 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 36 conjunts are in the unsatisfiable core [2022-03-15 21:36:02,258 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:36:02,623 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:02,634 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:02,635 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:02,636 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:02,636 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:02,637 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:02,637 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:02,638 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 6 disjoint index pairs (out of 10 index pairs), introduced 4 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 22 [2022-03-15 21:36:02,694 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 1 proven. 37 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:02,694 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:36:03,074 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:03,076 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:03,077 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:03,078 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:03,078 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:03,078 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:03,079 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:03,079 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:03,080 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:03,080 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:03,080 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:03,080 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:03,081 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:03,082 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:03,084 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:03,119 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:36:03,120 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 15 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 13 case distinctions, treesize of input 51 treesize of output 161 [2022-03-15 21:36:03,396 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:03,396 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1970227855] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:36:03,396 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:36:03,396 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:36:03,396 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [585892815] [2022-03-15 21:36:03,396 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:36:03,398 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:36:03,409 INFO L252 McrAutomatonBuilder]: Finished intersection with 99 states and 185 transitions. [2022-03-15 21:36:03,410 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:36:05,813 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 13 new interpolants: [56304#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 56308#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 56306#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 56305#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 56312#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 56311#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ (select queue front) 2 d) W)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (+ 2 front) (+ back 1)))), 56314#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 56309#(and (or (not v_assert) (<= (+ d temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 56303#(and (or (<= (+ d 1) W) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= back front))), 56313#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 56310#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 56315#(and v_assert (< 0 w)), 56307#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))))] [2022-03-15 21:36:05,813 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 30 states [2022-03-15 21:36:05,813 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:36:05,813 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2022-03-15 21:36:05,813 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=370, Invalid=2822, Unknown=0, NotChecked=0, Total=3192 [2022-03-15 21:36:05,813 INFO L87 Difference]: Start difference. First operand 600 states and 1472 transitions. Second operand has 30 states, 30 states have (on average 3.1666666666666665) internal successors, (95), 29 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:07,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:36:07,439 INFO L93 Difference]: Finished difference Result 1534 states and 3766 transitions. [2022-03-15 21:36:07,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2022-03-15 21:36:07,439 INFO L78 Accepts]: Start accepts. Automaton has has 30 states, 30 states have (on average 3.1666666666666665) internal successors, (95), 29 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:36:07,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:36:07,456 INFO L225 Difference]: With dead ends: 1534 [2022-03-15 21:36:07,456 INFO L226 Difference]: Without dead ends: 1517 [2022-03-15 21:36:07,456 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 186 GetRequests, 71 SyntacticMatches, 17 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2854 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=1333, Invalid=8567, Unknown=0, NotChecked=0, Total=9900 [2022-03-15 21:36:07,457 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 239 mSDsluCounter, 402 mSDsCounter, 0 mSdLazyCounter, 1300 mSolverCounterSat, 148 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 239 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1448 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 148 IncrementalHoareTripleChecker+Valid, 1300 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-03-15 21:36:07,458 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [239 Valid, 2 Invalid, 1448 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [148 Valid, 1300 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-03-15 21:36:07,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1517 states. [2022-03-15 21:36:07,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1517 to 560. [2022-03-15 21:36:07,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 560 states, 559 states have (on average 2.4597495527728084) internal successors, (1375), 559 states have internal predecessors, (1375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:07,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 560 states to 560 states and 1375 transitions. [2022-03-15 21:36:07,467 INFO L78 Accepts]: Start accepts. Automaton has 560 states and 1375 transitions. Word has length 31 [2022-03-15 21:36:07,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:36:07,467 INFO L470 AbstractCegarLoop]: Abstraction has 560 states and 1375 transitions. [2022-03-15 21:36:07,468 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 30 states, 30 states have (on average 3.1666666666666665) internal successors, (95), 29 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:07,468 INFO L276 IsEmpty]: Start isEmpty. Operand 560 states and 1375 transitions. [2022-03-15 21:36:07,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:36:07,468 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:36:07,468 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:36:07,486 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Forceful destruction successful, exit code 0 [2022-03-15 21:36:07,683 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 25 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable25 [2022-03-15 21:36:07,683 INFO L402 AbstractCegarLoop]: === Iteration 27 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:36:07,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:36:07,684 INFO L85 PathProgramCache]: Analyzing trace with hash 1645313457, now seen corresponding path program 25 times [2022-03-15 21:36:07,684 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:36:07,685 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187991082] [2022-03-15 21:36:07,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:36:07,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:36:07,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:36:07,840 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 1 proven. 37 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:07,841 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:36:07,841 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [187991082] [2022-03-15 21:36:07,841 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [187991082] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:36:07,841 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1814379734] [2022-03-15 21:36:07,841 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-03-15 21:36:07,841 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:36:07,841 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:36:07,842 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:36:07,855 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2022-03-15 21:36:07,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:36:07,879 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:36:07,880 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:36:08,315 INFO L353 Elim1Store]: treesize reduction 66, result has 1.5 percent of original size [2022-03-15 21:36:08,316 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 50 treesize of output 22 [2022-03-15 21:36:08,357 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:08,357 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:36:08,944 INFO L353 Elim1Store]: treesize reduction 156, result has 49.5 percent of original size [2022-03-15 21:36:08,945 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 53 treesize of output 177 [2022-03-15 21:36:10,072 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 3 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:10,072 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1814379734] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:36:10,072 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:36:10,073 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 16, 16] total 41 [2022-03-15 21:36:10,073 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1549392413] [2022-03-15 21:36:10,073 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:36:10,075 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:36:10,087 INFO L252 McrAutomatonBuilder]: Finished intersection with 115 states and 221 transitions. [2022-03-15 21:36:10,087 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:36:13,028 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 14 new interpolants: [59281#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 59282#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 59287#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ 2 d) W) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)))), 59286#(and (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1))), 59291#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 59289#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 59283#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 59279#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 59288#(and (or (not v_assert) (not (< 0 w)) (<= front back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W)) (or (not v_assert) (not (< 0 w)) (<= back front))), 59280#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 59290#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (<= (+ d w temp 1) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 59284#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 59278#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 59285#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (<= (+ 2 d) W) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1))))] [2022-03-15 21:36:13,029 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 29 states [2022-03-15 21:36:13,029 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:36:13,029 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-03-15 21:36:13,030 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=303, Invalid=2777, Unknown=0, NotChecked=0, Total=3080 [2022-03-15 21:36:13,030 INFO L87 Difference]: Start difference. First operand 560 states and 1375 transitions. Second operand has 29 states, 29 states have (on average 3.6206896551724137) internal successors, (105), 28 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:16,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:36:16,593 INFO L93 Difference]: Finished difference Result 3983 states and 10076 transitions. [2022-03-15 21:36:16,593 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2022-03-15 21:36:16,593 INFO L78 Accepts]: Start accepts. Automaton has has 29 states, 29 states have (on average 3.6206896551724137) internal successors, (105), 28 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:36:16,593 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:36:16,614 INFO L225 Difference]: With dead ends: 3983 [2022-03-15 21:36:16,614 INFO L226 Difference]: Without dead ends: 3653 [2022-03-15 21:36:16,615 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 237 GetRequests, 90 SyntacticMatches, 15 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5029 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=2795, Invalid=15027, Unknown=0, NotChecked=0, Total=17822 [2022-03-15 21:36:16,615 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 366 mSDsluCounter, 369 mSDsCounter, 0 mSdLazyCounter, 1483 mSolverCounterSat, 333 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 366 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1816 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 333 IncrementalHoareTripleChecker+Valid, 1483 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-03-15 21:36:16,615 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [366 Valid, 2 Invalid, 1816 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [333 Valid, 1483 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-03-15 21:36:16,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3653 states. [2022-03-15 21:36:16,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3653 to 816. [2022-03-15 21:36:16,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 816 states, 815 states have (on average 2.5607361963190183) internal successors, (2087), 815 states have internal predecessors, (2087), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:16,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 816 states to 816 states and 2087 transitions. [2022-03-15 21:36:16,636 INFO L78 Accepts]: Start accepts. Automaton has 816 states and 2087 transitions. Word has length 31 [2022-03-15 21:36:16,636 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:36:16,636 INFO L470 AbstractCegarLoop]: Abstraction has 816 states and 2087 transitions. [2022-03-15 21:36:16,636 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 29 states, 29 states have (on average 3.6206896551724137) internal successors, (105), 28 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:16,636 INFO L276 IsEmpty]: Start isEmpty. Operand 816 states and 2087 transitions. [2022-03-15 21:36:16,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:36:16,637 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:36:16,637 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:36:16,671 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Forceful destruction successful, exit code 0 [2022-03-15 21:36:16,867 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 26 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable26 [2022-03-15 21:36:16,867 INFO L402 AbstractCegarLoop]: === Iteration 28 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:36:16,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:36:16,868 INFO L85 PathProgramCache]: Analyzing trace with hash -1731241481, now seen corresponding path program 26 times [2022-03-15 21:36:16,869 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:36:16,869 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2062284695] [2022-03-15 21:36:16,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:36:16,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:36:16,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:36:17,012 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 1 proven. 37 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:17,012 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:36:17,012 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2062284695] [2022-03-15 21:36:17,012 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2062284695] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:36:17,012 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [769302453] [2022-03-15 21:36:17,012 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:36:17,012 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:36:17,012 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:36:17,013 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:36:17,014 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2022-03-15 21:36:17,045 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:36:17,045 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:36:17,048 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:36:17,049 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:36:17,405 INFO L353 Elim1Store]: treesize reduction 66, result has 1.5 percent of original size [2022-03-15 21:36:17,406 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 50 treesize of output 22 [2022-03-15 21:36:17,448 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:17,448 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:36:17,938 INFO L353 Elim1Store]: treesize reduction 156, result has 49.5 percent of original size [2022-03-15 21:36:17,938 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 53 treesize of output 177 [2022-03-15 21:36:19,572 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 1 proven. 37 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:19,572 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [769302453] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:36:19,572 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:36:19,572 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 16, 16] total 41 [2022-03-15 21:36:19,572 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [2097375602] [2022-03-15 21:36:19,572 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:36:19,574 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:36:19,587 INFO L252 McrAutomatonBuilder]: Finished intersection with 112 states and 215 transitions. [2022-03-15 21:36:19,587 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:36:22,394 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 14 new interpolants: [65294#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 65290#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 65285#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 65297#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 65288#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 65287#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 65298#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 65286#(and (or (not v_assert) (<= (+ d temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 65289#(and (or (<= (+ d 1) W) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= back front))), 65291#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 65293#(and (or (not v_assert) (not (< 0 w)) (<= front back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W)) (or (not v_assert) (not (< 0 w)) (<= back front))), 65295#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (<= (+ d w temp 1) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 65296#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 65292#(and (or (not v_assert) (= (+ front 1) (+ back 1)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (<= (+ 2 d) W) (not (< 1 w)) (not (= (select queue back) 1))))] [2022-03-15 21:36:22,394 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 29 states [2022-03-15 21:36:22,394 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:36:22,395 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-03-15 21:36:22,395 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=279, Invalid=2801, Unknown=0, NotChecked=0, Total=3080 [2022-03-15 21:36:22,395 INFO L87 Difference]: Start difference. First operand 816 states and 2087 transitions. Second operand has 29 states, 29 states have (on average 3.586206896551724) internal successors, (104), 28 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:25,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:36:25,307 INFO L93 Difference]: Finished difference Result 2799 states and 7014 transitions. [2022-03-15 21:36:25,307 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2022-03-15 21:36:25,307 INFO L78 Accepts]: Start accepts. Automaton has has 29 states, 29 states have (on average 3.586206896551724) internal successors, (104), 28 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:36:25,307 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:36:25,311 INFO L225 Difference]: With dead ends: 2799 [2022-03-15 21:36:25,311 INFO L226 Difference]: Without dead ends: 2670 [2022-03-15 21:36:25,312 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 224 GetRequests, 83 SyntacticMatches, 19 SemanticMatches, 122 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4417 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=2094, Invalid=13158, Unknown=0, NotChecked=0, Total=15252 [2022-03-15 21:36:25,312 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 313 mSDsluCounter, 343 mSDsCounter, 0 mSdLazyCounter, 1187 mSolverCounterSat, 245 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 313 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1432 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 245 IncrementalHoareTripleChecker+Valid, 1187 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-03-15 21:36:25,312 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [313 Valid, 2 Invalid, 1432 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [245 Valid, 1187 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-03-15 21:36:25,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2670 states. [2022-03-15 21:36:25,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2670 to 764. [2022-03-15 21:36:25,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 764 states, 763 states have (on average 2.5583224115334207) internal successors, (1952), 763 states have internal predecessors, (1952), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:25,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 764 states to 764 states and 1952 transitions. [2022-03-15 21:36:25,327 INFO L78 Accepts]: Start accepts. Automaton has 764 states and 1952 transitions. Word has length 31 [2022-03-15 21:36:25,327 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:36:25,327 INFO L470 AbstractCegarLoop]: Abstraction has 764 states and 1952 transitions. [2022-03-15 21:36:25,328 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 29 states, 29 states have (on average 3.586206896551724) internal successors, (104), 28 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:25,328 INFO L276 IsEmpty]: Start isEmpty. Operand 764 states and 1952 transitions. [2022-03-15 21:36:25,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:36:25,329 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:36:25,329 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:36:25,345 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Forceful destruction successful, exit code 0 [2022-03-15 21:36:25,545 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 27 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable27 [2022-03-15 21:36:25,545 INFO L402 AbstractCegarLoop]: === Iteration 29 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:36:25,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:36:25,545 INFO L85 PathProgramCache]: Analyzing trace with hash -2108294343, now seen corresponding path program 27 times [2022-03-15 21:36:25,546 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:36:25,546 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282934578] [2022-03-15 21:36:25,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:36:25,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:36:25,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:36:25,748 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 37 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:36:25,748 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:36:25,748 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [282934578] [2022-03-15 21:36:25,748 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [282934578] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:36:25,748 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1415752698] [2022-03-15 21:36:25,748 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:36:25,748 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:36:25,748 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:36:25,751 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:36:25,753 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2022-03-15 21:36:25,783 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2022-03-15 21:36:25,783 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:36:25,784 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:36:25,784 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:36:26,382 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:26,383 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:26,383 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,384 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:26,384 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:26,385 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:26,385 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:26,385 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:26,386 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:26,386 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,386 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,387 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:26,387 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 7 select indices, 7 select index equivalence classes, 6 disjoint index pairs (out of 21 index pairs), introduced 4 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 22 [2022-03-15 21:36:26,435 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:26,436 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:36:26,989 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,990 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,991 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,992 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,992 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,992 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,993 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,993 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,994 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,995 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,996 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,996 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,997 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,998 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:26,999 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:27,035 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:36:27,036 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 15 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 13 case distinctions, treesize of input 49 treesize of output 153 [2022-03-15 21:36:27,558 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:27,558 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1415752698] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:36:27,558 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:36:27,559 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 16, 16] total 41 [2022-03-15 21:36:27,559 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1559804724] [2022-03-15 21:36:27,559 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:36:27,561 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:36:27,571 INFO L252 McrAutomatonBuilder]: Finished intersection with 93 states and 170 transitions. [2022-03-15 21:36:27,571 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:36:29,924 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 13 new interpolants: [69987#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (<= (+ d w temp 1) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 69996#(and v_assert (< 0 w)), 69994#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 69988#(and (or (not v_assert) (<= (+ 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 69990#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 69992#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ 2 d temp) W)) (or (not v_assert) (= (select queue front) 1))), 69991#(and (or (not v_assert) (<= (+ 2 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 69985#(and (or (not v_assert) (not (< 0 w)) (<= front back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W)) (or (not v_assert) (not (< 0 w)) (<= back front))), 69995#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 69984#(and (or (not v_assert) (not (< 0 w)) (<= front back)) (or (not v_assert) (<= (+ d w) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= back front))), 69993#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 69989#(and (or (not v_assert) (<= (+ 2 d) W)) (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (= (select queue front) 1))), 69986#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W)))] [2022-03-15 21:36:29,925 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 28 states [2022-03-15 21:36:29,925 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:36:29,925 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2022-03-15 21:36:29,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=302, Invalid=2668, Unknown=0, NotChecked=0, Total=2970 [2022-03-15 21:36:29,925 INFO L87 Difference]: Start difference. First operand 764 states and 1952 transitions. Second operand has 28 states, 28 states have (on average 3.2142857142857144) internal successors, (90), 27 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:32,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:36:32,682 INFO L93 Difference]: Finished difference Result 2768 states and 6921 transitions. [2022-03-15 21:36:32,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2022-03-15 21:36:32,682 INFO L78 Accepts]: Start accepts. Automaton has has 28 states, 28 states have (on average 3.2142857142857144) internal successors, (90), 27 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:36:32,682 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:36:32,686 INFO L225 Difference]: With dead ends: 2768 [2022-03-15 21:36:32,686 INFO L226 Difference]: Without dead ends: 2518 [2022-03-15 21:36:32,686 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 187 GetRequests, 78 SyntacticMatches, 6 SemanticMatches, 103 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2352 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=1557, Invalid=9363, Unknown=0, NotChecked=0, Total=10920 [2022-03-15 21:36:32,687 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 254 mSDsluCounter, 550 mSDsCounter, 0 mSdLazyCounter, 2052 mSolverCounterSat, 182 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 254 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2234 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 182 IncrementalHoareTripleChecker+Valid, 2052 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:36:32,687 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [254 Valid, 2 Invalid, 2234 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [182 Valid, 2052 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:36:32,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2518 states. [2022-03-15 21:36:32,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2518 to 596. [2022-03-15 21:36:32,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 596 states, 595 states have (on average 2.46218487394958) internal successors, (1465), 595 states have internal predecessors, (1465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:32,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 596 states and 1465 transitions. [2022-03-15 21:36:32,700 INFO L78 Accepts]: Start accepts. Automaton has 596 states and 1465 transitions. Word has length 31 [2022-03-15 21:36:32,700 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:36:32,700 INFO L470 AbstractCegarLoop]: Abstraction has 596 states and 1465 transitions. [2022-03-15 21:36:32,700 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 28 states, 28 states have (on average 3.2142857142857144) internal successors, (90), 27 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:32,700 INFO L276 IsEmpty]: Start isEmpty. Operand 596 states and 1465 transitions. [2022-03-15 21:36:32,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:36:32,701 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:36:32,701 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:36:32,717 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Forceful destruction successful, exit code 0 [2022-03-15 21:36:32,917 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 28 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable28 [2022-03-15 21:36:32,917 INFO L402 AbstractCegarLoop]: === Iteration 30 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:36:32,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:36:32,918 INFO L85 PathProgramCache]: Analyzing trace with hash -556573057, now seen corresponding path program 28 times [2022-03-15 21:36:32,918 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:36:32,918 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [48374441] [2022-03-15 21:36:32,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:36:32,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:36:32,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:36:33,166 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:33,166 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:36:33,166 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [48374441] [2022-03-15 21:36:33,166 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [48374441] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:36:33,166 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1499205489] [2022-03-15 21:36:33,166 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:36:33,166 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:36:33,166 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:36:33,167 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:36:33,183 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2022-03-15 21:36:33,207 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:36:33,207 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:36:33,207 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:36:33,208 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:36:33,743 INFO L353 Elim1Store]: treesize reduction 66, result has 1.5 percent of original size [2022-03-15 21:36:33,743 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 50 treesize of output 22 [2022-03-15 21:36:33,809 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:33,810 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:36:34,320 INFO L353 Elim1Store]: treesize reduction 156, result has 49.5 percent of original size [2022-03-15 21:36:34,320 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 53 treesize of output 177 [2022-03-15 21:36:35,635 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 4 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:35,635 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1499205489] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:36:35,635 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:36:35,635 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:36:35,636 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [739098765] [2022-03-15 21:36:35,636 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:36:35,638 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:36:35,650 INFO L252 McrAutomatonBuilder]: Finished intersection with 116 states and 221 transitions. [2022-03-15 21:36:35,650 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:36:39,321 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 15 new interpolants: [74281#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 74293#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 74291#(and (or (not v_assert) (<= back (+ 3 front))) (or (not v_assert) (<= (+ d 4) W)) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 74288#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 74283#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 74285#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 74286#(and (or (= temp 1) (< 0 w)) (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w)) (or v_assert (= temp 1))), 74287#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w))), 74294#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 74284#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 74289#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (= (select queue (+ 2 front)) 1)) (or (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not (= (select queue back) 1)) v_assert (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 74292#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 74295#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 74282#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 74290#(and (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W)))] [2022-03-15 21:36:39,322 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 32 states [2022-03-15 21:36:39,322 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:36:39,322 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-03-15 21:36:39,322 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=353, Invalid=3069, Unknown=0, NotChecked=0, Total=3422 [2022-03-15 21:36:39,323 INFO L87 Difference]: Start difference. First operand 596 states and 1465 transitions. Second operand has 32 states, 32 states have (on average 3.46875) internal successors, (111), 31 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:42,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:36:42,969 INFO L93 Difference]: Finished difference Result 2871 states and 7146 transitions. [2022-03-15 21:36:42,969 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2022-03-15 21:36:42,970 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 32 states have (on average 3.46875) internal successors, (111), 31 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:36:42,970 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:36:42,973 INFO L225 Difference]: With dead ends: 2871 [2022-03-15 21:36:42,973 INFO L226 Difference]: Without dead ends: 2781 [2022-03-15 21:36:42,974 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 232 GetRequests, 91 SyntacticMatches, 12 SemanticMatches, 129 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4514 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=2839, Invalid=14191, Unknown=0, NotChecked=0, Total=17030 [2022-03-15 21:36:42,975 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 281 mSDsluCounter, 526 mSDsCounter, 0 mSdLazyCounter, 1777 mSolverCounterSat, 195 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 281 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1972 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 195 IncrementalHoareTripleChecker+Valid, 1777 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-03-15 21:36:42,975 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [281 Valid, 2 Invalid, 1972 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [195 Valid, 1777 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-03-15 21:36:42,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2781 states. [2022-03-15 21:36:43,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2781 to 644. [2022-03-15 21:36:43,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 644 states, 643 states have (on average 2.4665629860031104) internal successors, (1586), 643 states have internal predecessors, (1586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:43,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 644 states to 644 states and 1586 transitions. [2022-03-15 21:36:43,002 INFO L78 Accepts]: Start accepts. Automaton has 644 states and 1586 transitions. Word has length 31 [2022-03-15 21:36:43,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:36:43,002 INFO L470 AbstractCegarLoop]: Abstraction has 644 states and 1586 transitions. [2022-03-15 21:36:43,002 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 32 states, 32 states have (on average 3.46875) internal successors, (111), 31 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:43,002 INFO L276 IsEmpty]: Start isEmpty. Operand 644 states and 1586 transitions. [2022-03-15 21:36:43,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:36:43,006 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:36:43,006 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:36:43,022 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Ended with exit code 0 [2022-03-15 21:36:43,222 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29,29 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:36:43,222 INFO L402 AbstractCegarLoop]: === Iteration 31 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:36:43,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:36:43,223 INFO L85 PathProgramCache]: Analyzing trace with hash -1435219663, now seen corresponding path program 29 times [2022-03-15 21:36:43,223 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:36:43,223 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [180269729] [2022-03-15 21:36:43,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:36:43,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:36:43,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:36:43,439 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:43,439 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:36:43,439 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [180269729] [2022-03-15 21:36:43,440 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [180269729] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:36:43,440 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1975936998] [2022-03-15 21:36:43,440 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:36:43,440 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:36:43,440 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:36:43,441 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:36:43,442 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2022-03-15 21:36:43,472 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2022-03-15 21:36:43,472 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:36:43,473 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 30 conjunts are in the unsatisfiable core [2022-03-15 21:36:43,474 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:36:47,468 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:47,469 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:47,470 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:47,470 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:47,471 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:47,472 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:47,472 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:47,473 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:47,474 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:47,474 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:47,491 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:47,491 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:47,492 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:47,494 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 7 select indices, 7 select index equivalence classes, 6 disjoint index pairs (out of 21 index pairs), introduced 4 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 22 [2022-03-15 21:36:47,567 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:47,568 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:36:50,592 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:50,595 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:50,596 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:50,596 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:50,596 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:50,597 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:50,597 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:50,598 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:50,598 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:50,600 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:50,600 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:50,601 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:50,655 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:36:50,656 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 12 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 16 case distinctions, treesize of input 41 treesize of output 153 [2022-03-15 21:36:51,674 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:51,675 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1975936998] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:36:51,675 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:36:51,675 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:36:51,675 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1765153213] [2022-03-15 21:36:51,675 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:36:51,678 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:36:51,692 INFO L252 McrAutomatonBuilder]: Finished intersection with 113 states and 215 transitions. [2022-03-15 21:36:51,692 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:36:54,813 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 15 new interpolants: [78829#(and (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1))), 78825#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 78826#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 78824#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 78833#(and (or (not v_assert) (<= back (+ 3 front))) (or (not v_assert) (<= (+ d 4) W)) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 78831#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 78836#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 78835#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 78832#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 78830#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (= temp 1))), 78837#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 78823#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 78827#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 78834#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 78828#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (<= (+ 2 d) W) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1))))] [2022-03-15 21:36:54,813 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 32 states [2022-03-15 21:36:54,813 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:36:54,814 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-03-15 21:36:54,814 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=3014, Unknown=2, NotChecked=0, Total=3422 [2022-03-15 21:36:54,814 INFO L87 Difference]: Start difference. First operand 644 states and 1586 transitions. Second operand has 32 states, 32 states have (on average 3.40625) internal successors, (109), 31 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:58,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:36:58,709 INFO L93 Difference]: Finished difference Result 2716 states and 6741 transitions. [2022-03-15 21:36:58,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2022-03-15 21:36:58,709 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 32 states have (on average 3.40625) internal successors, (109), 31 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:36:58,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:36:58,712 INFO L225 Difference]: With dead ends: 2716 [2022-03-15 21:36:58,712 INFO L226 Difference]: Without dead ends: 2643 [2022-03-15 21:36:58,714 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 220 GetRequests, 94 SyntacticMatches, 6 SemanticMatches, 120 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3574 ImplicationChecksByTransitivity, 9.9s TimeCoverageRelationStatistics Valid=2426, Invalid=12334, Unknown=2, NotChecked=0, Total=14762 [2022-03-15 21:36:58,714 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 273 mSDsluCounter, 458 mSDsCounter, 0 mSdLazyCounter, 1537 mSolverCounterSat, 193 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 273 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1730 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 193 IncrementalHoareTripleChecker+Valid, 1537 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-03-15 21:36:58,714 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [273 Valid, 2 Invalid, 1730 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [193 Valid, 1537 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-03-15 21:36:58,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2643 states. [2022-03-15 21:36:58,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2643 to 656. [2022-03-15 21:36:58,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 656 states, 655 states have (on average 2.467175572519084) internal successors, (1616), 655 states have internal predecessors, (1616), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:58,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 656 states to 656 states and 1616 transitions. [2022-03-15 21:36:58,741 INFO L78 Accepts]: Start accepts. Automaton has 656 states and 1616 transitions. Word has length 31 [2022-03-15 21:36:58,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:36:58,741 INFO L470 AbstractCegarLoop]: Abstraction has 656 states and 1616 transitions. [2022-03-15 21:36:58,741 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 32 states, 32 states have (on average 3.40625) internal successors, (109), 31 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:58,741 INFO L276 IsEmpty]: Start isEmpty. Operand 656 states and 1616 transitions. [2022-03-15 21:36:58,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:36:58,742 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:36:58,742 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:36:58,758 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Forceful destruction successful, exit code 0 [2022-03-15 21:36:58,955 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30,30 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:36:58,955 INFO L402 AbstractCegarLoop]: === Iteration 32 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:36:58,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:36:58,956 INFO L85 PathProgramCache]: Analyzing trace with hash -1675580481, now seen corresponding path program 30 times [2022-03-15 21:36:58,956 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:36:58,956 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556871876] [2022-03-15 21:36:58,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:36:58,957 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:36:58,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:36:59,216 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:59,217 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:36:59,217 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1556871876] [2022-03-15 21:36:59,217 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1556871876] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:36:59,217 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [401431776] [2022-03-15 21:36:59,217 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:36:59,217 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:36:59,217 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:36:59,218 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:36:59,219 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2022-03-15 21:36:59,253 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2022-03-15 21:36:59,253 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:36:59,256 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:36:59,256 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:36:59,832 INFO L353 Elim1Store]: treesize reduction 66, result has 1.5 percent of original size [2022-03-15 21:36:59,832 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 50 treesize of output 22 [2022-03-15 21:36:59,901 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:59,901 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:37:00,456 INFO L353 Elim1Store]: treesize reduction 156, result has 49.5 percent of original size [2022-03-15 21:37:00,456 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 53 treesize of output 177 [2022-03-15 21:37:01,708 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 4 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:01,708 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [401431776] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:37:01,708 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:37:01,709 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:37:01,709 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1097723174] [2022-03-15 21:37:01,709 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:37:01,711 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:37:01,723 INFO L252 McrAutomatonBuilder]: Finished intersection with 110 states and 209 transitions. [2022-03-15 21:37:01,723 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:37:04,260 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 15 new interpolants: [83230#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 83217#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 83221#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 83227#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 83228#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 83229#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 83225#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d temp) W)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 83226#(and (or (not v_assert) (<= back (+ 3 front))) (or (not v_assert) (<= (+ d 4) W)) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 83224#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 83218#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 83223#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 83220#(and (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)))), 83216#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 83222#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 83219#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not (= (select queue back) 1)) v_assert) (or (<= (+ d 1) W) (< 1 w) (not (= (select queue back) 1))) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)))] [2022-03-15 21:37:04,260 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 32 states [2022-03-15 21:37:04,260 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:37:04,260 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-03-15 21:37:04,261 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=3081, Unknown=0, NotChecked=0, Total=3422 [2022-03-15 21:37:04,261 INFO L87 Difference]: Start difference. First operand 656 states and 1616 transitions. Second operand has 32 states, 32 states have (on average 3.34375) internal successors, (107), 31 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:07,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:37:07,028 INFO L93 Difference]: Finished difference Result 2591 states and 6408 transitions. [2022-03-15 21:37:07,028 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2022-03-15 21:37:07,028 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 32 states have (on average 3.34375) internal successors, (107), 31 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:37:07,028 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:37:07,031 INFO L225 Difference]: With dead ends: 2591 [2022-03-15 21:37:07,031 INFO L226 Difference]: Without dead ends: 2538 [2022-03-15 21:37:07,032 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 214 GetRequests, 85 SyntacticMatches, 12 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3603 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=1935, Invalid=12107, Unknown=0, NotChecked=0, Total=14042 [2022-03-15 21:37:07,032 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 256 mSDsluCounter, 515 mSDsCounter, 0 mSdLazyCounter, 1656 mSolverCounterSat, 186 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 256 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1842 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 186 IncrementalHoareTripleChecker+Valid, 1656 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-03-15 21:37:07,032 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [256 Valid, 2 Invalid, 1842 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [186 Valid, 1656 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-03-15 21:37:07,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2538 states. [2022-03-15 21:37:07,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2538 to 668. [2022-03-15 21:37:07,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 668 states, 667 states have (on average 2.4617691154422787) internal successors, (1642), 667 states have internal predecessors, (1642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:07,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668 states to 668 states and 1642 transitions. [2022-03-15 21:37:07,045 INFO L78 Accepts]: Start accepts. Automaton has 668 states and 1642 transitions. Word has length 31 [2022-03-15 21:37:07,045 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:37:07,045 INFO L470 AbstractCegarLoop]: Abstraction has 668 states and 1642 transitions. [2022-03-15 21:37:07,045 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 32 states, 32 states have (on average 3.34375) internal successors, (107), 31 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:07,045 INFO L276 IsEmpty]: Start isEmpty. Operand 668 states and 1642 transitions. [2022-03-15 21:37:07,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:37:07,046 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:37:07,046 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:37:07,062 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Ended with exit code 0 [2022-03-15 21:37:07,253 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 31 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable31 [2022-03-15 21:37:07,253 INFO L402 AbstractCegarLoop]: === Iteration 33 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:37:07,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:37:07,254 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836625, now seen corresponding path program 31 times [2022-03-15 21:37:07,255 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:37:07,255 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [470591504] [2022-03-15 21:37:07,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:37:07,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:37:07,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:37:07,507 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:07,507 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:37:07,507 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [470591504] [2022-03-15 21:37:07,507 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [470591504] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:37:07,508 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [628275047] [2022-03-15 21:37:07,508 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-03-15 21:37:07,508 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:37:07,508 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:37:07,509 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:37:07,510 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2022-03-15 21:37:07,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:37:07,534 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:37:07,534 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:37:07,997 INFO L353 Elim1Store]: treesize reduction 66, result has 1.5 percent of original size [2022-03-15 21:37:07,998 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 50 treesize of output 22 [2022-03-15 21:37:08,054 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:08,055 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:37:08,511 INFO L353 Elim1Store]: treesize reduction 156, result has 49.5 percent of original size [2022-03-15 21:37:08,513 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 53 treesize of output 177 [2022-03-15 21:37:09,893 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 4 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:09,893 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [628275047] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:37:09,893 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:37:09,893 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:37:09,893 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [696313365] [2022-03-15 21:37:09,894 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:37:09,896 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:37:09,906 INFO L252 McrAutomatonBuilder]: Finished intersection with 97 states and 179 transitions. [2022-03-15 21:37:09,906 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:37:11,970 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 14 new interpolants: [87509#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 87513#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 87506#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 87505#(and (or (<= (+ d 1) W) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= back front))), 87503#(and (or (not v_assert) (<= (+ d temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 87515#(and v_assert (< 0 w)), 87514#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 87508#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 87507#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 87502#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 87512#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 87511#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 87510#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d temp) W)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 87504#(and (or (not v_assert) (<= back (+ 3 front))) (or (not v_assert) (<= (+ d 4) W)) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:37:11,970 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 31 states [2022-03-15 21:37:11,971 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:37:11,971 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2022-03-15 21:37:11,971 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=291, Invalid=3015, Unknown=0, NotChecked=0, Total=3306 [2022-03-15 21:37:11,971 INFO L87 Difference]: Start difference. First operand 668 states and 1642 transitions. Second operand has 31 states, 31 states have (on average 3.129032258064516) internal successors, (97), 30 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:14,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:37:14,481 INFO L93 Difference]: Finished difference Result 2019 states and 4967 transitions. [2022-03-15 21:37:14,481 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2022-03-15 21:37:14,481 INFO L78 Accepts]: Start accepts. Automaton has has 31 states, 31 states have (on average 3.129032258064516) internal successors, (97), 30 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:37:14,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:37:14,483 INFO L225 Difference]: With dead ends: 2019 [2022-03-15 21:37:14,483 INFO L226 Difference]: Without dead ends: 2002 [2022-03-15 21:37:14,486 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 195 GetRequests, 74 SyntacticMatches, 11 SemanticMatches, 110 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3160 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=1359, Invalid=11073, Unknown=0, NotChecked=0, Total=12432 [2022-03-15 21:37:14,486 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 278 mSDsluCounter, 557 mSDsCounter, 0 mSdLazyCounter, 1734 mSolverCounterSat, 186 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 278 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1920 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 186 IncrementalHoareTripleChecker+Valid, 1734 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-03-15 21:37:14,486 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [278 Valid, 2 Invalid, 1920 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [186 Valid, 1734 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-03-15 21:37:14,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2002 states. [2022-03-15 21:37:14,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2002 to 656. [2022-03-15 21:37:14,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 656 states, 655 states have (on average 2.467175572519084) internal successors, (1616), 655 states have internal predecessors, (1616), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:14,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 656 states to 656 states and 1616 transitions. [2022-03-15 21:37:14,498 INFO L78 Accepts]: Start accepts. Automaton has 656 states and 1616 transitions. Word has length 31 [2022-03-15 21:37:14,498 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:37:14,498 INFO L470 AbstractCegarLoop]: Abstraction has 656 states and 1616 transitions. [2022-03-15 21:37:14,499 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 31 states, 31 states have (on average 3.129032258064516) internal successors, (97), 30 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:14,499 INFO L276 IsEmpty]: Start isEmpty. Operand 656 states and 1616 transitions. [2022-03-15 21:37:14,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:37:14,499 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:37:14,499 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:37:14,516 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Forceful destruction successful, exit code 0 [2022-03-15 21:37:14,715 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable32,32 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:37:14,716 INFO L402 AbstractCegarLoop]: === Iteration 34 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:37:14,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:37:14,716 INFO L85 PathProgramCache]: Analyzing trace with hash 1266595321, now seen corresponding path program 32 times [2022-03-15 21:37:14,717 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:37:14,717 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929163617] [2022-03-15 21:37:14,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:37:14,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:37:14,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:37:14,972 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:14,972 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:37:14,972 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [929163617] [2022-03-15 21:37:14,972 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [929163617] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:37:14,973 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [386376117] [2022-03-15 21:37:14,973 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:37:14,973 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:37:14,973 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:37:14,974 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:37:14,975 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2022-03-15 21:37:14,998 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:37:14,998 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:37:14,998 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:37:14,999 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:37:15,449 INFO L353 Elim1Store]: treesize reduction 66, result has 1.5 percent of original size [2022-03-15 21:37:15,450 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 50 treesize of output 22 [2022-03-15 21:37:15,511 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:15,511 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:37:16,009 INFO L353 Elim1Store]: treesize reduction 156, result has 49.5 percent of original size [2022-03-15 21:37:16,010 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 53 treesize of output 177 [2022-03-15 21:37:17,690 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 4 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:17,691 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [386376117] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:37:17,691 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:37:17,691 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:37:17,691 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1736514275] [2022-03-15 21:37:17,691 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:37:17,693 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:37:17,703 INFO L252 McrAutomatonBuilder]: Finished intersection with 91 states and 164 transitions. [2022-03-15 21:37:17,703 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:37:19,757 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 12 new interpolants: [91189#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 91190#(and v_assert (< 0 w)), 91182#(and (or (not v_assert) (<= (+ 2 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 91186#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 91188#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 91181#(and (or (not v_assert) (<= (+ 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 91179#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 91180#(and (or (not v_assert) (<= back (+ 3 front))) (or (not v_assert) (<= (+ d 4) W)) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 91187#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 91184#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 91183#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)))), 91185#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))))] [2022-03-15 21:37:19,757 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 29 states [2022-03-15 21:37:19,757 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:37:19,758 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-03-15 21:37:19,758 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=277, Invalid=2803, Unknown=0, NotChecked=0, Total=3080 [2022-03-15 21:37:19,758 INFO L87 Difference]: Start difference. First operand 656 states and 1616 transitions. Second operand has 29 states, 29 states have (on average 3.103448275862069) internal successors, (90), 28 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:22,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:37:22,579 INFO L93 Difference]: Finished difference Result 1895 states and 4671 transitions. [2022-03-15 21:37:22,579 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2022-03-15 21:37:22,580 INFO L78 Accepts]: Start accepts. Automaton has has 29 states, 29 states have (on average 3.103448275862069) internal successors, (90), 28 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:37:22,580 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:37:22,582 INFO L225 Difference]: With dead ends: 1895 [2022-03-15 21:37:22,582 INFO L226 Difference]: Without dead ends: 1878 [2022-03-15 21:37:22,582 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 185 GetRequests, 77 SyntacticMatches, 4 SemanticMatches, 104 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2313 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=1355, Invalid=9775, Unknown=0, NotChecked=0, Total=11130 [2022-03-15 21:37:22,583 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 224 mSDsluCounter, 578 mSDsCounter, 0 mSdLazyCounter, 1873 mSolverCounterSat, 138 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 224 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2011 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 138 IncrementalHoareTripleChecker+Valid, 1873 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:37:22,583 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [224 Valid, 2 Invalid, 2011 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [138 Valid, 1873 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:37:22,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1878 states. [2022-03-15 21:37:22,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1878 to 644. [2022-03-15 21:37:22,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 644 states, 643 states have (on average 2.4665629860031104) internal successors, (1586), 643 states have internal predecessors, (1586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:22,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 644 states to 644 states and 1586 transitions. [2022-03-15 21:37:22,595 INFO L78 Accepts]: Start accepts. Automaton has 644 states and 1586 transitions. Word has length 31 [2022-03-15 21:37:22,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:37:22,595 INFO L470 AbstractCegarLoop]: Abstraction has 644 states and 1586 transitions. [2022-03-15 21:37:22,595 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 29 states, 29 states have (on average 3.103448275862069) internal successors, (90), 28 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:22,595 INFO L276 IsEmpty]: Start isEmpty. Operand 644 states and 1586 transitions. [2022-03-15 21:37:22,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:37:22,596 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:37:22,596 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:37:22,612 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Forceful destruction successful, exit code 0 [2022-03-15 21:37:22,812 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable33,33 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:37:22,812 INFO L402 AbstractCegarLoop]: === Iteration 35 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:37:22,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:37:22,812 INFO L85 PathProgramCache]: Analyzing trace with hash 1931899089, now seen corresponding path program 33 times [2022-03-15 21:37:22,813 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:37:22,813 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170740118] [2022-03-15 21:37:22,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:37:22,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:37:22,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:37:23,096 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:23,097 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:37:23,097 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170740118] [2022-03-15 21:37:23,097 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1170740118] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:37:23,097 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1552311371] [2022-03-15 21:37:23,097 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:37:23,097 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:37:23,097 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:37:23,098 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:37:23,099 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2022-03-15 21:37:23,130 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-03-15 21:37:23,130 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:37:23,133 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:37:23,134 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:37:23,527 INFO L353 Elim1Store]: treesize reduction 66, result has 1.5 percent of original size [2022-03-15 21:37:23,528 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 50 treesize of output 22 [2022-03-15 21:37:23,593 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:23,593 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:37:24,164 INFO L353 Elim1Store]: treesize reduction 156, result has 49.5 percent of original size [2022-03-15 21:37:24,165 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 53 treesize of output 177 [2022-03-15 21:37:25,603 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 4 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:25,608 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1552311371] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:37:25,608 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:37:25,608 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:37:25,608 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [745321385] [2022-03-15 21:37:25,608 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:37:25,610 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:37:25,620 INFO L252 McrAutomatonBuilder]: Finished intersection with 85 states and 149 transitions. [2022-03-15 21:37:25,620 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:37:27,797 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 10 new interpolants: [94702#(and (or (not v_assert) (<= (+ 3 d) W)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 94701#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 94699#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 94706#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 94698#(and (or (not v_assert) (<= back (+ 3 front))) (or (not v_assert) (<= (+ d 4) W)) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 94707#(and v_assert (< 0 w)), 94705#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 94704#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 94703#(and (or (not v_assert) (<= (+ 3 d temp) W)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 94700#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:37:27,798 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 27 states [2022-03-15 21:37:27,798 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:37:27,798 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2022-03-15 21:37:27,798 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=265, Invalid=2597, Unknown=0, NotChecked=0, Total=2862 [2022-03-15 21:37:27,798 INFO L87 Difference]: Start difference. First operand 644 states and 1586 transitions. Second operand has 27 states, 27 states have (on average 3.074074074074074) internal successors, (83), 26 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:30,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:37:30,169 INFO L93 Difference]: Finished difference Result 1827 states and 4501 transitions. [2022-03-15 21:37:30,169 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2022-03-15 21:37:30,169 INFO L78 Accepts]: Start accepts. Automaton has has 27 states, 27 states have (on average 3.074074074074074) internal successors, (83), 26 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:37:30,169 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:37:30,173 INFO L225 Difference]: With dead ends: 1827 [2022-03-15 21:37:30,173 INFO L226 Difference]: Without dead ends: 1810 [2022-03-15 21:37:30,174 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 178 GetRequests, 74 SyntacticMatches, 3 SemanticMatches, 101 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2034 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=1346, Invalid=9160, Unknown=0, NotChecked=0, Total=10506 [2022-03-15 21:37:30,175 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 199 mSDsluCounter, 425 mSDsCounter, 0 mSdLazyCounter, 1352 mSolverCounterSat, 112 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 199 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1464 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 112 IncrementalHoareTripleChecker+Valid, 1352 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-03-15 21:37:30,175 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [199 Valid, 2 Invalid, 1464 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [112 Valid, 1352 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-03-15 21:37:30,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1810 states. [2022-03-15 21:37:30,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1810 to 612. [2022-03-15 21:37:30,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 612 states, 611 states have (on average 2.463175122749591) internal successors, (1505), 611 states have internal predecessors, (1505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:30,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 612 states to 612 states and 1505 transitions. [2022-03-15 21:37:30,190 INFO L78 Accepts]: Start accepts. Automaton has 612 states and 1505 transitions. Word has length 31 [2022-03-15 21:37:30,190 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:37:30,190 INFO L470 AbstractCegarLoop]: Abstraction has 612 states and 1505 transitions. [2022-03-15 21:37:30,190 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 27 states, 27 states have (on average 3.074074074074074) internal successors, (83), 26 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:30,190 INFO L276 IsEmpty]: Start isEmpty. Operand 612 states and 1505 transitions. [2022-03-15 21:37:30,191 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-03-15 21:37:30,191 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:37:30,191 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:37:30,214 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Forceful destruction successful, exit code 0 [2022-03-15 21:37:30,391 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 34 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable34 [2022-03-15 21:37:30,392 INFO L402 AbstractCegarLoop]: === Iteration 36 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:37:30,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:37:30,392 INFO L85 PathProgramCache]: Analyzing trace with hash -1928096839, now seen corresponding path program 34 times [2022-03-15 21:37:30,396 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:37:30,396 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545060842] [2022-03-15 21:37:30,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:37:30,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:37:30,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:37:30,647 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:30,647 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:37:30,647 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [545060842] [2022-03-15 21:37:30,647 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [545060842] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:37:30,647 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1989216752] [2022-03-15 21:37:30,647 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:37:30,647 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:37:30,647 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:37:30,648 INFO L229 MonitoredProcess]: Starting monitored process 35 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:37:30,649 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2022-03-15 21:37:30,672 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:37:30,673 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:37:30,673 INFO L263 TraceCheckSpWp]: Trace formula consists of 102 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:37:30,674 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:37:31,218 INFO L353 Elim1Store]: treesize reduction 66, result has 1.5 percent of original size [2022-03-15 21:37:31,218 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 50 treesize of output 22 [2022-03-15 21:37:31,286 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:31,286 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:37:31,806 INFO L353 Elim1Store]: treesize reduction 156, result has 49.5 percent of original size [2022-03-15 21:37:31,806 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 0 disjoint index pairs (out of 28 index pairs), introduced 8 new quantified variables, introduced 28 case distinctions, treesize of input 53 treesize of output 177 [2022-03-15 21:37:33,249 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 9 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:33,250 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1989216752] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:37:33,250 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:37:33,250 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 43 [2022-03-15 21:37:33,250 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1233825095] [2022-03-15 21:37:33,250 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:37:33,262 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:37:33,275 INFO L252 McrAutomatonBuilder]: Finished intersection with 116 states and 219 transitions. [2022-03-15 21:37:33,275 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:37:36,571 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 14 new interpolants: [98081#(and (or (not v_assert) (= (select queue (+ 3 front)) 1)) (or (not v_assert) (<= (+ d 4) W)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 98084#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 98094#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 98088#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 98092#(and (or v_assert (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (< 0 w) (<= (+ d 4) W)) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (= (+ (- 1) temp) 0) (< 0 w))), 98086#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 98093#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 98085#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 98090#(and (or (= temp 1) (< 0 w)) (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w)) (or v_assert (= temp 1))), 98083#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 98082#(and (or (not v_assert) (<= back (+ 3 front))) (or (not v_assert) (<= (+ d 4) W)) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 98091#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w))), 98087#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 98089#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert))] [2022-03-15 21:37:36,572 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 31 states [2022-03-15 21:37:36,572 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:37:36,572 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2022-03-15 21:37:36,573 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=340, Invalid=2966, Unknown=0, NotChecked=0, Total=3306 [2022-03-15 21:37:36,573 INFO L87 Difference]: Start difference. First operand 612 states and 1505 transitions. Second operand has 31 states, 31 states have (on average 3.5483870967741935) internal successors, (110), 30 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:40,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:37:40,071 INFO L93 Difference]: Finished difference Result 2789 states and 6599 transitions. [2022-03-15 21:37:40,072 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2022-03-15 21:37:40,072 INFO L78 Accepts]: Start accepts. Automaton has has 31 states, 31 states have (on average 3.5483870967741935) internal successors, (110), 30 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 31 [2022-03-15 21:37:40,072 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:37:40,075 INFO L225 Difference]: With dead ends: 2789 [2022-03-15 21:37:40,075 INFO L226 Difference]: Without dead ends: 2749 [2022-03-15 21:37:40,076 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 226 GetRequests, 95 SyntacticMatches, 9 SemanticMatches, 122 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3722 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=2420, Invalid=12832, Unknown=0, NotChecked=0, Total=15252 [2022-03-15 21:37:40,083 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 201 mSDsluCounter, 437 mSDsCounter, 0 mSdLazyCounter, 1566 mSolverCounterSat, 140 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 201 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 1706 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 140 IncrementalHoareTripleChecker+Valid, 1566 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-03-15 21:37:40,083 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [201 Valid, 1 Invalid, 1706 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [140 Valid, 1566 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-03-15 21:37:40,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2749 states. [2022-03-15 21:37:40,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2749 to 626. [2022-03-15 21:37:40,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 625 states have (on average 2.4624) internal successors, (1539), 625 states have internal predecessors, (1539), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:40,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 1539 transitions. [2022-03-15 21:37:40,098 INFO L78 Accepts]: Start accepts. Automaton has 626 states and 1539 transitions. Word has length 31 [2022-03-15 21:37:40,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:37:40,098 INFO L470 AbstractCegarLoop]: Abstraction has 626 states and 1539 transitions. [2022-03-15 21:37:40,098 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 31 states, 31 states have (on average 3.5483870967741935) internal successors, (110), 30 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:40,098 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 1539 transitions. [2022-03-15 21:37:40,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2022-03-15 21:37:40,099 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:37:40,099 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:37:40,116 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Ended with exit code 0 [2022-03-15 21:37:40,315 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 35 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable35 [2022-03-15 21:37:40,315 INFO L402 AbstractCegarLoop]: === Iteration 37 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:37:40,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:37:40,316 INFO L85 PathProgramCache]: Analyzing trace with hash -1977902544, now seen corresponding path program 35 times [2022-03-15 21:37:40,316 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:37:40,317 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981259997] [2022-03-15 21:37:40,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:37:40,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:37:40,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:37:40,348 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 31 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:40,348 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:37:40,348 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [981259997] [2022-03-15 21:37:40,348 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [981259997] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:37:40,348 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1692378903] [2022-03-15 21:37:40,348 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:37:40,348 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:37:40,348 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:37:40,354 INFO L229 MonitoredProcess]: Starting monitored process 36 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:37:40,396 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2022-03-15 21:37:40,400 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2022-03-15 21:37:40,400 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:37:40,401 INFO L263 TraceCheckSpWp]: Trace formula consists of 110 conjuncts, 10 conjunts are in the unsatisfiable core [2022-03-15 21:37:40,401 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:37:40,438 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 31 proven. 19 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:37:40,439 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:37:40,471 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 31 proven. 19 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:37:40,471 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1692378903] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:37:40,471 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:37:40,471 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 7 [2022-03-15 21:37:40,478 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1533824031] [2022-03-15 21:37:40,478 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:37:40,481 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:37:40,496 INFO L252 McrAutomatonBuilder]: Finished intersection with 131 states and 249 transitions. [2022-03-15 21:37:40,496 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:37:40,812 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 0 new interpolants: [] [2022-03-15 21:37:40,812 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-03-15 21:37:40,812 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:37:40,812 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-03-15 21:37:40,813 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2022-03-15 21:37:40,813 INFO L87 Difference]: Start difference. First operand 626 states and 1539 transitions. Second operand has 8 states, 8 states have (on average 6.875) internal successors, (55), 7 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:40,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:37:40,849 INFO L93 Difference]: Finished difference Result 1172 states and 2810 transitions. [2022-03-15 21:37:40,850 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-03-15 21:37:40,850 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 6.875) internal successors, (55), 7 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 34 [2022-03-15 21:37:40,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:37:40,851 INFO L225 Difference]: With dead ends: 1172 [2022-03-15 21:37:40,851 INFO L226 Difference]: Without dead ends: 1123 [2022-03-15 21:37:40,851 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 172 GetRequests, 160 SyntacticMatches, 6 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2022-03-15 21:37:40,851 INFO L933 BasicCegarLoop]: 3 mSDtfsCounter, 61 mSDsluCounter, 71 mSDsCounter, 0 mSdLazyCounter, 87 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 61 SdHoareTripleChecker+Valid, 18 SdHoareTripleChecker+Invalid, 94 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 87 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:37:40,851 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [61 Valid, 18 Invalid, 94 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 87 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-03-15 21:37:40,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1123 states. [2022-03-15 21:37:40,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1123 to 748. [2022-03-15 21:37:40,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 748 states, 747 states have (on average 2.4725568942436413) internal successors, (1847), 747 states have internal predecessors, (1847), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:40,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 748 states to 748 states and 1847 transitions. [2022-03-15 21:37:40,859 INFO L78 Accepts]: Start accepts. Automaton has 748 states and 1847 transitions. Word has length 34 [2022-03-15 21:37:40,859 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:37:40,859 INFO L470 AbstractCegarLoop]: Abstraction has 748 states and 1847 transitions. [2022-03-15 21:37:40,859 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 6.875) internal successors, (55), 7 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:40,859 INFO L276 IsEmpty]: Start isEmpty. Operand 748 states and 1847 transitions. [2022-03-15 21:37:40,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:37:40,860 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:37:40,860 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:37:40,876 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Forceful destruction successful, exit code 0 [2022-03-15 21:37:41,075 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 36 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable36 [2022-03-15 21:37:41,075 INFO L402 AbstractCegarLoop]: === Iteration 38 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:37:41,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:37:41,076 INFO L85 PathProgramCache]: Analyzing trace with hash -570840227, now seen corresponding path program 36 times [2022-03-15 21:37:41,076 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:37:41,076 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [276197271] [2022-03-15 21:37:41,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:37:41,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:37:41,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:37:41,402 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 1 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:41,403 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:37:41,403 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [276197271] [2022-03-15 21:37:41,403 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [276197271] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:37:41,403 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [970585906] [2022-03-15 21:37:41,403 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:37:41,403 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:37:41,403 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:37:41,405 INFO L229 MonitoredProcess]: Starting monitored process 37 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:37:41,406 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2022-03-15 21:37:41,429 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2022-03-15 21:37:41,430 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:37:41,430 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:37:41,431 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:37:42,133 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:37:42,133 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:37:42,216 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:42,216 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:37:42,934 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:37:42,934 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:37:47,855 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 12 proven. 48 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:47,855 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [970585906] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:37:47,855 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:37:47,855 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:37:47,855 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [342325206] [2022-03-15 21:37:47,855 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:37:47,858 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:37:47,879 INFO L252 McrAutomatonBuilder]: Finished intersection with 147 states and 289 transitions. [2022-03-15 21:37:47,879 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:37:57,264 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [105419#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 105411#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w))), 105407#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 105409#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 105420#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 105418#(and (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (= (select queue (+ 3 front)) 1) (not (= (select queue (+ 3 back)) 1)) (not (= (select queue back) 1)) (< 4 w) (not (= (select queue (+ back 1)) 1)) (not (< 3 w))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue (+ 3 back)) 1)) (not (= (select queue back) 1)) (< 4 w) (= (select queue (+ 2 front)) 1) (not (= (select queue (+ back 1)) 1)) (not (< 3 w))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue (+ 3 back)) 1)) (not (= (select queue back) 1)) (< 4 w) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W) (not (< 3 w))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue (+ 3 back)) 1)) (not (= (select queue back) 1)) (= (select queue front) 1) (< 4 w) (not (= (select queue (+ back 1)) 1)) (not (< 3 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue (+ 3 back)) 1)) (not (= (select queue back) 1)) (< 4 w) (not (= (select queue (+ back 1)) 1)) (not (< 3 w)))), 105414#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ 3 front)) 1) (not (= (select queue back) 1)) v_assert) (or (= (select queue (+ 3 front)) 1) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (< 1 w) (not (= (select queue back) 1)) (<= (+ d 4) W)) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (<= (+ d 4) W)) (or (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 105417#(and (or (= (select queue (+ front 1)) 1) (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (= (select queue (+ 3 front)) 1) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (= (select queue (+ 2 front)) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W)) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1)))), 105412#(and (or v_assert (<= (+ d 4) W)) (or (= temp 1) (< 0 w)) (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (< 0 w) (<= (+ d 4) W)) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (= (select queue front) 1) (< 0 w)) (or v_assert (= temp 1))), 105415#(and (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (not (< 0 w)) (= (select queue (+ 3 front)) 1) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (<= (+ d 4) W))), 105416#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (= (select queue (+ 3 front)) 1) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W))), 105405#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 105421#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 105413#(and (or v_assert (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (< 0 w) (<= (+ d 4) W)) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ 3 front)) 1) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (= (select queue (+ 3 front)) 1) (< 0 w))), 105408#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 105406#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 105410#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (+ (- 1) temp) 0) v_assert) (or v_assert (<= (+ 2 d temp) W)) (or (= (select queue front) 1) (< 0 w)) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ 2 d temp) W) (< 0 w)))] [2022-03-15 21:37:57,264 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-03-15 21:37:57,264 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:37:57,265 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-03-15 21:37:57,265 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=491, Invalid=4339, Unknown=0, NotChecked=0, Total=4830 [2022-03-15 21:37:57,265 INFO L87 Difference]: Start difference. First operand 748 states and 1847 transitions. Second operand has 37 states, 37 states have (on average 3.5405405405405403) internal successors, (131), 36 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:38:09,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:38:09,178 INFO L93 Difference]: Finished difference Result 4333 states and 10661 transitions. [2022-03-15 21:38:09,178 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 133 states. [2022-03-15 21:38:09,179 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 3.5405405405405403) internal successors, (131), 36 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:38:09,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:38:09,184 INFO L225 Difference]: With dead ends: 4333 [2022-03-15 21:38:09,184 INFO L226 Difference]: Without dead ends: 4214 [2022-03-15 21:38:09,186 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 328 GetRequests, 97 SyntacticMatches, 34 SemanticMatches, 197 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12984 ImplicationChecksByTransitivity, 13.6s TimeCoverageRelationStatistics Valid=6367, Invalid=33035, Unknown=0, NotChecked=0, Total=39402 [2022-03-15 21:38:09,187 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 456 mSDsluCounter, 523 mSDsCounter, 0 mSdLazyCounter, 1944 mSolverCounterSat, 437 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 456 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 2381 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 437 IncrementalHoareTripleChecker+Valid, 1944 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:38:09,187 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [456 Valid, 1 Invalid, 2381 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [437 Valid, 1944 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2022-03-15 21:38:09,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4214 states. [2022-03-15 21:38:09,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4214 to 895. [2022-03-15 21:38:09,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 895 states, 894 states have (on average 2.523489932885906) internal successors, (2256), 894 states have internal predecessors, (2256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:38:09,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 895 states to 895 states and 2256 transitions. [2022-03-15 21:38:09,221 INFO L78 Accepts]: Start accepts. Automaton has 895 states and 2256 transitions. Word has length 36 [2022-03-15 21:38:09,222 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:38:09,224 INFO L470 AbstractCegarLoop]: Abstraction has 895 states and 2256 transitions. [2022-03-15 21:38:09,225 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 3.5405405405405403) internal successors, (131), 36 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:38:09,225 INFO L276 IsEmpty]: Start isEmpty. Operand 895 states and 2256 transitions. [2022-03-15 21:38:09,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:38:09,226 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:38:09,226 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:38:09,249 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Ended with exit code 0 [2022-03-15 21:38:09,428 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable37,37 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:38:09,428 INFO L402 AbstractCegarLoop]: === Iteration 39 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:38:09,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:38:09,429 INFO L85 PathProgramCache]: Analyzing trace with hash 1493789547, now seen corresponding path program 37 times [2022-03-15 21:38:09,429 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:38:09,430 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520562288] [2022-03-15 21:38:09,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:38:09,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:38:09,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:38:09,827 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 1 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:38:09,827 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:38:09,827 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1520562288] [2022-03-15 21:38:09,828 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1520562288] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:38:09,828 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1111008101] [2022-03-15 21:38:09,828 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-03-15 21:38:09,828 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:38:09,828 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:38:09,852 INFO L229 MonitoredProcess]: Starting monitored process 38 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:38:09,853 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2022-03-15 21:38:09,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:38:09,880 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:38:09,881 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:38:10,699 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:38:10,699 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:38:10,766 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:38:10,767 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:38:11,427 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:38:11,428 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:38:14,856 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:38:14,857 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1111008101] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:38:14,857 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:38:14,857 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:38:14,857 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1721700886] [2022-03-15 21:38:14,857 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:38:14,859 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:38:14,898 INFO L252 McrAutomatonBuilder]: Finished intersection with 144 states and 283 transitions. [2022-03-15 21:38:14,898 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:38:20,423 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [112071#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (+ (- 1) temp) 0) v_assert) (or v_assert (<= (+ 2 d temp) W)) (or (= (select queue front) 1) (< 0 w)) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ 2 d temp) W) (< 0 w))), 112067#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 112081#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 112070#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 112080#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 112076#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 112075#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 112077#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ d 4) W))), 112079#(and (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (<= front back) (not (= (select queue (+ back 1)) 1)) (not (< 3 w))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W) (not (< 3 w))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (not (= (select queue (+ back 1)) 1)) (not (< 3 w)) (<= back front))), 112082#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 112072#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w))), 112068#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 112066#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 112073#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (= (select queue (+ 2 front)) 1)) (or (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not (= (select queue back) 1)) v_assert (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 112069#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 112074#(and (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W))), 112078#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= back (+ front 1)) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ front 1) back) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W)))] [2022-03-15 21:38:20,423 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-03-15 21:38:20,423 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:38:20,424 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-03-15 21:38:20,424 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=455, Invalid=4375, Unknown=0, NotChecked=0, Total=4830 [2022-03-15 21:38:20,424 INFO L87 Difference]: Start difference. First operand 895 states and 2256 transitions. Second operand has 37 states, 37 states have (on average 3.4864864864864864) internal successors, (129), 36 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:38:28,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:38:28,019 INFO L93 Difference]: Finished difference Result 3960 states and 9969 transitions. [2022-03-15 21:38:28,019 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 109 states. [2022-03-15 21:38:28,019 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 3.4864864864864864) internal successors, (129), 36 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:38:28,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:38:28,024 INFO L225 Difference]: With dead ends: 3960 [2022-03-15 21:38:28,024 INFO L226 Difference]: Without dead ends: 3888 [2022-03-15 21:38:28,026 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 302 GetRequests, 96 SyntacticMatches, 32 SemanticMatches, 174 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10078 ImplicationChecksByTransitivity, 9.1s TimeCoverageRelationStatistics Valid=4313, Invalid=26487, Unknown=0, NotChecked=0, Total=30800 [2022-03-15 21:38:28,026 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 348 mSDsluCounter, 558 mSDsCounter, 0 mSdLazyCounter, 2036 mSolverCounterSat, 359 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 348 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2395 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 359 IncrementalHoareTripleChecker+Valid, 2036 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-03-15 21:38:28,026 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [348 Valid, 2 Invalid, 2395 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [359 Valid, 2036 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-03-15 21:38:28,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3888 states. [2022-03-15 21:38:28,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3888 to 953. [2022-03-15 21:38:28,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 953 states, 952 states have (on average 2.55672268907563) internal successors, (2434), 952 states have internal predecessors, (2434), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:38:28,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 953 states to 953 states and 2434 transitions. [2022-03-15 21:38:28,047 INFO L78 Accepts]: Start accepts. Automaton has 953 states and 2434 transitions. Word has length 36 [2022-03-15 21:38:28,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:38:28,047 INFO L470 AbstractCegarLoop]: Abstraction has 953 states and 2434 transitions. [2022-03-15 21:38:28,047 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 3.4864864864864864) internal successors, (129), 36 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:38:28,047 INFO L276 IsEmpty]: Start isEmpty. Operand 953 states and 2434 transitions. [2022-03-15 21:38:28,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:38:28,048 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:38:28,048 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:38:28,066 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Forceful destruction successful, exit code 0 [2022-03-15 21:38:28,263 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 38 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable38 [2022-03-15 21:38:28,264 INFO L402 AbstractCegarLoop]: === Iteration 40 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:38:28,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:38:28,264 INFO L85 PathProgramCache]: Analyzing trace with hash 615142941, now seen corresponding path program 38 times [2022-03-15 21:38:28,264 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:38:28,265 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1830891672] [2022-03-15 21:38:28,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:38:28,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:38:28,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:38:28,576 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 1 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:38:28,577 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:38:28,577 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1830891672] [2022-03-15 21:38:28,577 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1830891672] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:38:28,577 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [679079761] [2022-03-15 21:38:28,577 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:38:28,577 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:38:28,577 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:38:28,578 INFO L229 MonitoredProcess]: Starting monitored process 39 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:38:28,579 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2022-03-15 21:38:28,608 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:38:28,608 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:38:28,609 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:38:28,611 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:38:29,225 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:38:29,225 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:38:29,280 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:38:29,280 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:38:30,011 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:38:30,012 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:38:34,897 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:38:34,898 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [679079761] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:38:34,898 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:38:34,898 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:38:34,898 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1784128939] [2022-03-15 21:38:34,898 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:38:34,900 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:38:34,919 INFO L252 McrAutomatonBuilder]: Finished intersection with 141 states and 277 transitions. [2022-03-15 21:38:34,919 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:38:40,907 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [118432#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 118429#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (<= (+ 2 d) W) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 118437#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= back (+ front 1)) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ front 1) back) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W))), 118434#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 118436#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 118439#(and (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (<= front back) (not (= (select queue (+ back 1)) 1)) (not (< 3 w))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W) (not (< 3 w))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (not (= (select queue (+ back 1)) 1)) (not (< 3 w)) (<= back front))), 118431#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 118438#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 118433#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 118440#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 118424#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 118427#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 118425#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 118430#(and (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1))), 118435#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ d 4) W))), 118426#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 118428#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert))] [2022-03-15 21:38:40,907 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-03-15 21:38:40,907 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:38:40,907 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-03-15 21:38:40,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=446, Invalid=4384, Unknown=0, NotChecked=0, Total=4830 [2022-03-15 21:38:40,908 INFO L87 Difference]: Start difference. First operand 953 states and 2434 transitions. Second operand has 37 states, 37 states have (on average 3.4324324324324325) internal successors, (127), 36 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:38:47,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:38:47,607 INFO L93 Difference]: Finished difference Result 3850 states and 9654 transitions. [2022-03-15 21:38:47,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 97 states. [2022-03-15 21:38:47,607 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 3.4324324324324325) internal successors, (127), 36 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:38:47,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:38:47,612 INFO L225 Difference]: With dead ends: 3850 [2022-03-15 21:38:47,612 INFO L226 Difference]: Without dead ends: 3792 [2022-03-15 21:38:47,613 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 287 GetRequests, 91 SyntacticMatches, 34 SemanticMatches, 162 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8703 ImplicationChecksByTransitivity, 8.5s TimeCoverageRelationStatistics Valid=3510, Invalid=23222, Unknown=0, NotChecked=0, Total=26732 [2022-03-15 21:38:47,614 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 422 mSDsluCounter, 435 mSDsCounter, 0 mSdLazyCounter, 1525 mSolverCounterSat, 402 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 422 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1927 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 402 IncrementalHoareTripleChecker+Valid, 1525 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:38:47,614 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [422 Valid, 2 Invalid, 1927 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [402 Valid, 1525 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:38:47,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3792 states. [2022-03-15 21:38:47,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3792 to 965. [2022-03-15 21:38:47,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 965 states, 964 states have (on average 2.5560165975103732) internal successors, (2464), 964 states have internal predecessors, (2464), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:38:47,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 965 states to 965 states and 2464 transitions. [2022-03-15 21:38:47,633 INFO L78 Accepts]: Start accepts. Automaton has 965 states and 2464 transitions. Word has length 36 [2022-03-15 21:38:47,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:38:47,633 INFO L470 AbstractCegarLoop]: Abstraction has 965 states and 2464 transitions. [2022-03-15 21:38:47,633 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 3.4324324324324325) internal successors, (127), 36 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:38:47,634 INFO L276 IsEmpty]: Start isEmpty. Operand 965 states and 2464 transitions. [2022-03-15 21:38:47,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:38:47,635 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:38:47,635 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:38:47,663 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Ended with exit code 0 [2022-03-15 21:38:47,851 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 39 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable39 [2022-03-15 21:38:47,851 INFO L402 AbstractCegarLoop]: === Iteration 41 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:38:47,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:38:47,851 INFO L85 PathProgramCache]: Analyzing trace with hash 374782123, now seen corresponding path program 39 times [2022-03-15 21:38:47,852 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:38:47,852 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798560760] [2022-03-15 21:38:47,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:38:47,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:38:47,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:38:48,228 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 1 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:38:48,229 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:38:48,229 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [798560760] [2022-03-15 21:38:48,229 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [798560760] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:38:48,229 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [920830457] [2022-03-15 21:38:48,229 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:38:48,229 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:38:48,229 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:38:48,230 INFO L229 MonitoredProcess]: Starting monitored process 40 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:38:48,231 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2022-03-15 21:38:48,259 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-03-15 21:38:48,259 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:38:48,260 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:38:48,261 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:38:48,946 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:38:48,946 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:38:49,001 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:38:49,001 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:38:49,823 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:38:49,824 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:38:54,597 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:38:54,598 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [920830457] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:38:54,598 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:38:54,598 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:38:54,598 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [275142672] [2022-03-15 21:38:54,598 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:38:54,600 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:38:54,619 INFO L252 McrAutomatonBuilder]: Finished intersection with 138 states and 271 transitions. [2022-03-15 21:38:54,619 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:39:00,428 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [124676#(and (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)))), 124682#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 124683#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ d 4) W))), 124679#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 124684#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= back (+ front 1)) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ front 1) back) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W))), 124685#(and (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (<= front back) (not (= (select queue (+ back 1)) 1)) (not (< 3 w))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W) (not (< 3 w))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (not (= (select queue (+ back 1)) 1)) (not (< 3 w)) (<= back front))), 124686#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 124681#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d temp) W)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 124674#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 124678#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 124673#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 124675#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not (= (select queue back) 1)) v_assert) (or (<= (+ d 1) W) (< 1 w) (not (= (select queue back) 1))) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1))), 124680#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 124688#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 124677#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 124687#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 124672#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w)))] [2022-03-15 21:39:00,428 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-03-15 21:39:00,428 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:39:00,430 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-03-15 21:39:00,430 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=442, Invalid=4388, Unknown=0, NotChecked=0, Total=4830 [2022-03-15 21:39:00,430 INFO L87 Difference]: Start difference. First operand 965 states and 2464 transitions. Second operand has 37 states, 37 states have (on average 3.3783783783783785) internal successors, (125), 36 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:39:06,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:39:06,311 INFO L93 Difference]: Finished difference Result 3515 states and 8767 transitions. [2022-03-15 21:39:06,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 91 states. [2022-03-15 21:39:06,311 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 3.3783783783783785) internal successors, (125), 36 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:39:06,316 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:39:06,321 INFO L225 Difference]: With dead ends: 3515 [2022-03-15 21:39:06,321 INFO L226 Difference]: Without dead ends: 3462 [2022-03-15 21:39:06,322 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 278 GetRequests, 86 SyntacticMatches, 36 SemanticMatches, 156 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8059 ImplicationChecksByTransitivity, 7.8s TimeCoverageRelationStatistics Valid=2973, Invalid=21833, Unknown=0, NotChecked=0, Total=24806 [2022-03-15 21:39:06,322 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 407 mSDsluCounter, 546 mSDsCounter, 0 mSdLazyCounter, 1787 mSolverCounterSat, 368 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 407 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2155 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 368 IncrementalHoareTripleChecker+Valid, 1787 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:39:06,323 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [407 Valid, 2 Invalid, 2155 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [368 Valid, 1787 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:39:06,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3462 states. [2022-03-15 21:39:06,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3462 to 977. [2022-03-15 21:39:06,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 977 states, 976 states have (on average 2.5512295081967213) internal successors, (2490), 976 states have internal predecessors, (2490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:39:06,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 977 states to 977 states and 2490 transitions. [2022-03-15 21:39:06,350 INFO L78 Accepts]: Start accepts. Automaton has 977 states and 2490 transitions. Word has length 36 [2022-03-15 21:39:06,350 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:39:06,350 INFO L470 AbstractCegarLoop]: Abstraction has 977 states and 2490 transitions. [2022-03-15 21:39:06,350 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 3.3783783783783785) internal successors, (125), 36 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:39:06,351 INFO L276 IsEmpty]: Start isEmpty. Operand 977 states and 2490 transitions. [2022-03-15 21:39:06,352 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:39:06,352 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:39:06,352 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:39:06,368 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Forceful destruction successful, exit code 0 [2022-03-15 21:39:06,553 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable40,40 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:39:06,554 INFO L402 AbstractCegarLoop]: === Iteration 42 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:39:06,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:39:06,554 INFO L85 PathProgramCache]: Analyzing trace with hash -964768067, now seen corresponding path program 40 times [2022-03-15 21:39:06,554 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:39:06,554 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1580249082] [2022-03-15 21:39:06,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:39:06,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:39:06,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:39:06,849 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 1 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:39:06,849 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:39:06,850 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1580249082] [2022-03-15 21:39:06,850 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1580249082] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:39:06,850 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1094096404] [2022-03-15 21:39:06,850 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:39:06,850 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:39:06,850 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:39:06,864 INFO L229 MonitoredProcess]: Starting monitored process 41 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:39:06,868 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2022-03-15 21:39:06,892 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:39:06,892 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:39:06,893 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:39:06,894 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:39:07,488 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:39:07,488 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:39:07,676 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:39:07,676 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:39:08,562 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:39:08,563 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:39:12,190 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:39:12,190 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1094096404] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:39:12,191 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:39:12,191 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:39:12,191 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1537568557] [2022-03-15 21:39:12,191 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:39:12,193 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:39:12,210 INFO L252 McrAutomatonBuilder]: Finished intersection with 125 states and 241 transitions. [2022-03-15 21:39:12,210 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:39:17,727 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 16 new interpolants: [130607#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 130603#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 130600#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 130601#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 130612#(and v_assert (< 0 w)), 130608#(and (or (not v_assert) (<= (+ d temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 130610#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 130604#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ d 4) W))), 130606#(and (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (<= front back) (not (= (select queue (+ back 1)) 1)) (not (< 3 w))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W) (not (< 3 w))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (not (= (select queue (+ back 1)) 1)) (not (< 3 w)) (<= back front))), 130597#(and (or (<= (+ d 1) W) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= back front))), 130605#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= back (+ front 1)) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ front 1) back) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W))), 130598#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 130611#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 130599#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 130602#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d temp) W)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 130609#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W)))] [2022-03-15 21:39:17,727 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2022-03-15 21:39:17,727 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:39:17,728 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-03-15 21:39:17,728 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=387, Invalid=4305, Unknown=0, NotChecked=0, Total=4692 [2022-03-15 21:39:17,728 INFO L87 Difference]: Start difference. First operand 977 states and 2490 transitions. Second operand has 36 states, 36 states have (on average 3.1944444444444446) internal successors, (115), 35 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:39:22,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:39:22,693 INFO L93 Difference]: Finished difference Result 2663 states and 6631 transitions. [2022-03-15 21:39:22,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 87 states. [2022-03-15 21:39:22,693 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 36 states have (on average 3.1944444444444446) internal successors, (115), 35 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:39:22,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:39:22,696 INFO L225 Difference]: With dead ends: 2663 [2022-03-15 21:39:22,697 INFO L226 Difference]: Without dead ends: 2646 [2022-03-15 21:39:22,698 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 260 GetRequests, 75 SyntacticMatches, 35 SemanticMatches, 150 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7219 ImplicationChecksByTransitivity, 7.0s TimeCoverageRelationStatistics Valid=2205, Invalid=20747, Unknown=0, NotChecked=0, Total=22952 [2022-03-15 21:39:22,698 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 409 mSDsluCounter, 597 mSDsCounter, 0 mSdLazyCounter, 1928 mSolverCounterSat, 346 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 409 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2274 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 346 IncrementalHoareTripleChecker+Valid, 1928 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:39:22,698 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [409 Valid, 2 Invalid, 2274 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [346 Valid, 1928 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:39:22,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2646 states. [2022-03-15 21:39:22,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2646 to 965. [2022-03-15 21:39:22,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 965 states, 964 states have (on average 2.5560165975103732) internal successors, (2464), 964 states have internal predecessors, (2464), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:39:22,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 965 states to 965 states and 2464 transitions. [2022-03-15 21:39:22,712 INFO L78 Accepts]: Start accepts. Automaton has 965 states and 2464 transitions. Word has length 36 [2022-03-15 21:39:22,712 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:39:22,712 INFO L470 AbstractCegarLoop]: Abstraction has 965 states and 2464 transitions. [2022-03-15 21:39:22,713 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 36 states have (on average 3.1944444444444446) internal successors, (115), 35 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:39:22,713 INFO L276 IsEmpty]: Start isEmpty. Operand 965 states and 2464 transitions. [2022-03-15 21:39:22,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:39:22,714 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:39:22,714 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:39:22,745 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Ended with exit code 0 [2022-03-15 21:39:22,927 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 41 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable41 [2022-03-15 21:39:22,927 INFO L402 AbstractCegarLoop]: === Iteration 43 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:39:22,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:39:22,928 INFO L85 PathProgramCache]: Analyzing trace with hash -978009371, now seen corresponding path program 41 times [2022-03-15 21:39:22,928 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:39:22,928 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1515932487] [2022-03-15 21:39:22,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:39:22,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:39:22,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:39:23,267 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 1 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:39:23,268 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:39:23,268 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1515932487] [2022-03-15 21:39:23,268 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1515932487] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:39:23,268 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [26772060] [2022-03-15 21:39:23,268 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:39:23,268 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:39:23,268 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:39:23,269 INFO L229 MonitoredProcess]: Starting monitored process 42 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:39:23,270 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2022-03-15 21:39:23,301 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2022-03-15 21:39:23,301 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:39:23,302 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:39:23,303 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:39:24,159 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,159 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,160 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,161 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,161 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,162 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,162 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,163 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,164 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,164 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,165 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,165 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,166 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,166 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,167 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,167 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,168 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,169 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,169 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,170 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:39:24,170 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 9 select indices, 9 select index equivalence classes, 10 disjoint index pairs (out of 36 index pairs), introduced 5 new quantified variables, introduced 0 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:39:24,253 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:39:24,253 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:39:24,925 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,925 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,926 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,926 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,927 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,928 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,928 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,929 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,929 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,931 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,931 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,932 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,932 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,932 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,932 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,935 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,935 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,935 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,936 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,936 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,937 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,937 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,938 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,939 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,941 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:24,943 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:39:25,025 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:39:25,026 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 26 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 19 case distinctions, treesize of input 64 treesize of output 228 [2022-03-15 21:39:27,186 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:39:27,186 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [26772060] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:39:27,186 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:39:27,186 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:39:27,187 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [733675287] [2022-03-15 21:39:27,187 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:39:27,189 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:39:27,205 INFO L252 McrAutomatonBuilder]: Finished intersection with 119 states and 226 transitions. [2022-03-15 21:39:27,205 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:39:32,101 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 14 new interpolants: [135647#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 135635#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)))), 135645#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 135644#(and (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (<= front back) (not (= (select queue (+ back 1)) 1)) (not (< 3 w))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (not (= (select queue (+ back 1)) 1)) (not (< 3 w))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (not (= (select queue (+ back 1)) 1)) (not (< 3 w)) (<= back front))), 135648#(and v_assert (< 0 w)), 135641#(and (or (not v_assert) (<= (+ 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 135642#(and (or (not v_assert) (<= (+ 2 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 135637#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 135646#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 135639#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 135638#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 135640#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (< 1 w)) (not (= (select queue back) 1)))), 135636#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 135643#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= back (+ front 1)) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ front 1) back) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))))] [2022-03-15 21:39:32,101 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 34 states [2022-03-15 21:39:32,101 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:39:32,101 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2022-03-15 21:39:32,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=374, Invalid=4048, Unknown=0, NotChecked=0, Total=4422 [2022-03-15 21:39:32,102 INFO L87 Difference]: Start difference. First operand 965 states and 2464 transitions. Second operand has 34 states, 34 states have (on average 3.176470588235294) internal successors, (108), 33 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:39:38,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:39:38,070 INFO L93 Difference]: Finished difference Result 2696 states and 6724 transitions. [2022-03-15 21:39:38,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2022-03-15 21:39:38,070 INFO L78 Accepts]: Start accepts. Automaton has has 34 states, 34 states have (on average 3.176470588235294) internal successors, (108), 33 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:39:38,070 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:39:38,074 INFO L225 Difference]: With dead ends: 2696 [2022-03-15 21:39:38,074 INFO L226 Difference]: Without dead ends: 2679 [2022-03-15 21:39:38,075 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 251 GetRequests, 79 SyntacticMatches, 27 SemanticMatches, 145 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6255 ImplicationChecksByTransitivity, 7.6s TimeCoverageRelationStatistics Valid=2210, Invalid=19252, Unknown=0, NotChecked=0, Total=21462 [2022-03-15 21:39:38,076 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 396 mSDsluCounter, 532 mSDsCounter, 0 mSdLazyCounter, 1737 mSolverCounterSat, 331 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 396 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2068 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 331 IncrementalHoareTripleChecker+Valid, 1737 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-03-15 21:39:38,081 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [396 Valid, 2 Invalid, 2068 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [331 Valid, 1737 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-03-15 21:39:38,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2679 states. [2022-03-15 21:39:38,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2679 to 953. [2022-03-15 21:39:38,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 953 states, 952 states have (on average 2.55672268907563) internal successors, (2434), 952 states have internal predecessors, (2434), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:39:38,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 953 states to 953 states and 2434 transitions. [2022-03-15 21:39:38,102 INFO L78 Accepts]: Start accepts. Automaton has 953 states and 2434 transitions. Word has length 36 [2022-03-15 21:39:38,103 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:39:38,103 INFO L470 AbstractCegarLoop]: Abstraction has 953 states and 2434 transitions. [2022-03-15 21:39:38,103 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 34 states, 34 states have (on average 3.176470588235294) internal successors, (108), 33 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:39:38,103 INFO L276 IsEmpty]: Start isEmpty. Operand 953 states and 2434 transitions. [2022-03-15 21:39:38,104 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:39:38,104 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:39:38,104 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:39:38,122 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Forceful destruction successful, exit code 0 [2022-03-15 21:39:38,320 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable42,42 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:39:38,320 INFO L402 AbstractCegarLoop]: === Iteration 44 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:39:38,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:39:38,320 INFO L85 PathProgramCache]: Analyzing trace with hash -312705603, now seen corresponding path program 42 times [2022-03-15 21:39:38,321 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:39:38,321 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581061550] [2022-03-15 21:39:38,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:39:38,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:39:38,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:39:38,734 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 1 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:39:38,734 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:39:38,734 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1581061550] [2022-03-15 21:39:38,734 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1581061550] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:39:38,734 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1937594897] [2022-03-15 21:39:38,734 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:39:38,734 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:39:38,734 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:39:38,735 INFO L229 MonitoredProcess]: Starting monitored process 43 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:39:38,738 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2022-03-15 21:39:38,769 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2022-03-15 21:39:38,769 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:39:38,770 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 46 conjunts are in the unsatisfiable core [2022-03-15 21:39:38,771 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:39:39,481 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:39:39,481 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:39:39,532 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:39:39,532 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:39:40,214 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:39:40,214 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:39:42,633 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:39:42,634 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1937594897] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:39:42,634 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:39:42,634 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:39:42,634 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1948846707] [2022-03-15 21:39:42,634 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:39:42,636 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:39:42,652 INFO L252 McrAutomatonBuilder]: Finished intersection with 113 states and 211 transitions. [2022-03-15 21:39:42,652 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:39:46,676 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 12 new interpolants: [140675#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 140685#(and v_assert (< 0 w)), 140680#(and (or (not v_assert) (<= (+ 3 d temp) W)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 140681#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= back (+ front 1)) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ front 1) back) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)))), 140683#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 140677#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 140674#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 140679#(and (or (not v_assert) (<= (+ 3 d) W)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 140684#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 140678#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (< 1 w)) (not (= (select queue back) 1)))), 140682#(and (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (<= front back) (not (= (select queue (+ back 1)) 1)) (not (< 3 w))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (not (= (select queue (+ back 1)) 1)) (not (< 3 w))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (not (= (select queue (+ back 1)) 1)) (not (< 3 w)) (<= back front))), 140676#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))))] [2022-03-15 21:39:46,677 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 32 states [2022-03-15 21:39:46,677 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:39:46,677 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-03-15 21:39:46,677 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=375, Invalid=3785, Unknown=0, NotChecked=0, Total=4160 [2022-03-15 21:39:46,677 INFO L87 Difference]: Start difference. First operand 953 states and 2434 transitions. Second operand has 32 states, 32 states have (on average 3.15625) internal successors, (101), 31 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:39:52,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:39:52,033 INFO L93 Difference]: Finished difference Result 2575 states and 6423 transitions. [2022-03-15 21:39:52,033 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2022-03-15 21:39:52,033 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 32 states have (on average 3.15625) internal successors, (101), 31 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:39:52,033 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:39:52,036 INFO L225 Difference]: With dead ends: 2575 [2022-03-15 21:39:52,036 INFO L226 Difference]: Without dead ends: 2558 [2022-03-15 21:39:52,037 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 244 GetRequests, 76 SyntacticMatches, 26 SemanticMatches, 142 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6147 ImplicationChecksByTransitivity, 6.6s TimeCoverageRelationStatistics Valid=2229, Invalid=18363, Unknown=0, NotChecked=0, Total=20592 [2022-03-15 21:39:52,038 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 355 mSDsluCounter, 543 mSDsCounter, 0 mSdLazyCounter, 1824 mSolverCounterSat, 292 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 355 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2116 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 292 IncrementalHoareTripleChecker+Valid, 1824 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:39:52,038 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [355 Valid, 2 Invalid, 2116 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [292 Valid, 1824 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:39:52,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2558 states. [2022-03-15 21:39:52,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2558 to 941. [2022-03-15 21:39:52,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 941 states, 940 states have (on average 2.557446808510638) internal successors, (2404), 940 states have internal predecessors, (2404), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:39:52,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 941 states to 941 states and 2404 transitions. [2022-03-15 21:39:52,057 INFO L78 Accepts]: Start accepts. Automaton has 941 states and 2404 transitions. Word has length 36 [2022-03-15 21:39:52,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:39:52,057 INFO L470 AbstractCegarLoop]: Abstraction has 941 states and 2404 transitions. [2022-03-15 21:39:52,057 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 32 states, 32 states have (on average 3.15625) internal successors, (101), 31 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:39:52,057 INFO L276 IsEmpty]: Start isEmpty. Operand 941 states and 2404 transitions. [2022-03-15 21:39:52,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:39:52,058 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:39:52,058 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:39:52,074 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Forceful destruction successful, exit code 0 [2022-03-15 21:39:52,271 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable43,43 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:39:52,271 INFO L402 AbstractCegarLoop]: === Iteration 45 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:39:52,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:39:52,272 INFO L85 PathProgramCache]: Analyzing trace with hash -1522224155, now seen corresponding path program 43 times [2022-03-15 21:39:52,273 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:39:52,273 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792292943] [2022-03-15 21:39:52,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:39:52,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:39:52,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:39:52,540 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 1 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:39:52,540 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:39:52,540 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [792292943] [2022-03-15 21:39:52,540 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [792292943] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:39:52,540 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [426609601] [2022-03-15 21:39:52,540 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-03-15 21:39:52,541 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:39:52,541 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:39:52,546 INFO L229 MonitoredProcess]: Starting monitored process 44 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:39:52,547 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2022-03-15 21:39:52,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:39:52,579 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:39:52,580 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:39:53,201 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:39:53,202 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:39:53,262 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:39:53,262 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:39:54,132 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:39:54,132 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:39:57,215 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:39:57,216 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [426609601] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:39:57,216 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:39:57,216 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:39:57,216 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1894293991] [2022-03-15 21:39:57,216 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:39:57,219 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:39:57,233 INFO L252 McrAutomatonBuilder]: Finished intersection with 107 states and 196 transitions. [2022-03-15 21:39:57,234 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:40:01,212 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 10 new interpolants: [145568#(and (or (not v_assert) (= (select queue (+ 3 front)) 1)) (or (not v_assert) (<= (+ d 4) W)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 145572#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 145565#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ d 4) W))), 145570#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 145569#(and (or (not v_assert) (<= (+ d temp 4) W)) (or (not v_assert) (= (select queue (+ 3 front)) 1)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 145566#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= back (+ front 1)) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ front 1) back) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W))), 145573#(and v_assert (< 0 w)), 145564#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 145571#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 145567#(and (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (<= front back) (not (= (select queue (+ back 1)) 1)) (not (< 3 w))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W) (not (< 3 w))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (not (= (select queue (+ back 1)) 1)) (not (< 3 w)) (<= back front)))] [2022-03-15 21:40:01,212 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 30 states [2022-03-15 21:40:01,212 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:40:01,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2022-03-15 21:40:01,213 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=343, Invalid=3563, Unknown=0, NotChecked=0, Total=3906 [2022-03-15 21:40:01,213 INFO L87 Difference]: Start difference. First operand 941 states and 2404 transitions. Second operand has 30 states, 30 states have (on average 3.1333333333333333) internal successors, (94), 29 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:06,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:40:06,130 INFO L93 Difference]: Finished difference Result 2569 states and 6412 transitions. [2022-03-15 21:40:06,130 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2022-03-15 21:40:06,130 INFO L78 Accepts]: Start accepts. Automaton has has 30 states, 30 states have (on average 3.1333333333333333) internal successors, (94), 29 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:40:06,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:40:06,133 INFO L225 Difference]: With dead ends: 2569 [2022-03-15 21:40:06,133 INFO L226 Difference]: Without dead ends: 2552 [2022-03-15 21:40:06,134 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 240 GetRequests, 72 SyntacticMatches, 26 SemanticMatches, 142 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5723 ImplicationChecksByTransitivity, 6.1s TimeCoverageRelationStatistics Valid=2307, Invalid=18285, Unknown=0, NotChecked=0, Total=20592 [2022-03-15 21:40:06,134 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 323 mSDsluCounter, 678 mSDsCounter, 0 mSdLazyCounter, 2226 mSolverCounterSat, 263 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 323 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2489 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 263 IncrementalHoareTripleChecker+Valid, 2226 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-03-15 21:40:06,134 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [323 Valid, 2 Invalid, 2489 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [263 Valid, 2226 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-03-15 21:40:06,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2552 states. [2022-03-15 21:40:06,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2552 to 829. [2022-03-15 21:40:06,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 829 states, 828 states have (on average 2.5144927536231885) internal successors, (2082), 828 states have internal predecessors, (2082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:06,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 829 states to 829 states and 2082 transitions. [2022-03-15 21:40:06,161 INFO L78 Accepts]: Start accepts. Automaton has 829 states and 2082 transitions. Word has length 36 [2022-03-15 21:40:06,161 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:40:06,161 INFO L470 AbstractCegarLoop]: Abstraction has 829 states and 2082 transitions. [2022-03-15 21:40:06,161 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 30 states, 30 states have (on average 3.1333333333333333) internal successors, (94), 29 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:06,161 INFO L276 IsEmpty]: Start isEmpty. Operand 829 states and 2082 transitions. [2022-03-15 21:40:06,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:40:06,162 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:40:06,162 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:40:06,181 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Forceful destruction successful, exit code 0 [2022-03-15 21:40:06,378 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 44 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable44 [2022-03-15 21:40:06,378 INFO L402 AbstractCegarLoop]: === Iteration 46 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:40:06,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:40:06,378 INFO L85 PathProgramCache]: Analyzing trace with hash 2071341661, now seen corresponding path program 44 times [2022-03-15 21:40:06,379 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:40:06,379 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927805161] [2022-03-15 21:40:06,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:40:06,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:40:06,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:40:06,695 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 1 proven. 57 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-03-15 21:40:06,695 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:40:06,695 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1927805161] [2022-03-15 21:40:06,695 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1927805161] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:40:06,695 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1098910050] [2022-03-15 21:40:06,696 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:40:06,696 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:40:06,696 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:40:06,701 INFO L229 MonitoredProcess]: Starting monitored process 45 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:40:06,702 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2022-03-15 21:40:06,728 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:40:06,728 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:40:06,729 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:40:06,730 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:40:07,478 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:40:07,478 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:40:07,552 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:40:07,553 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:40:08,389 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:40:08,390 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:40:11,784 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 4 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:40:11,784 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1098910050] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:40:11,784 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:40:11,784 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 19, 19] total 50 [2022-03-15 21:40:11,784 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1901222433] [2022-03-15 21:40:11,784 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:40:11,787 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:40:11,805 INFO L252 McrAutomatonBuilder]: Finished intersection with 144 states and 283 transitions. [2022-03-15 21:40:11,805 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:40:16,889 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [150228#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 150225#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 150229#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (+ (- 1) temp) 0) v_assert) (or v_assert (<= (+ 2 d temp) W)) (or (= (select queue front) 1) (< 0 w)) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ 2 d temp) W) (< 0 w))), 150226#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 150236#(and (or (not v_assert) (<= (+ front 1) back) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (<= (+ d w 1) W) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ front 1)) (not (< 1 w)) (not (= (select queue back) 1)))), 150237#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (<= front back) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= back front)) (or (not v_assert) (<= (+ d w) W) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)))), 150227#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 150232#(and (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W))), 150233#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)))), 150224#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 150230#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w))), 150240#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 150234#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 150239#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 150238#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 150235#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 150231#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (= (select queue (+ 2 front)) 1)) (or (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not (= (select queue back) 1)) v_assert (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1))))] [2022-03-15 21:40:16,889 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 35 states [2022-03-15 21:40:16,890 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:40:16,890 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-03-15 21:40:16,890 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=4150, Unknown=0, NotChecked=0, Total=4556 [2022-03-15 21:40:16,890 INFO L87 Difference]: Start difference. First operand 829 states and 2082 transitions. Second operand has 35 states, 35 states have (on average 3.6285714285714286) internal successors, (127), 34 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:22,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:40:22,278 INFO L93 Difference]: Finished difference Result 4602 states and 11688 transitions. [2022-03-15 21:40:22,278 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2022-03-15 21:40:22,278 INFO L78 Accepts]: Start accepts. Automaton has has 35 states, 35 states have (on average 3.6285714285714286) internal successors, (127), 34 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:40:22,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:40:22,285 INFO L225 Difference]: With dead ends: 4602 [2022-03-15 21:40:22,285 INFO L226 Difference]: Without dead ends: 4258 [2022-03-15 21:40:22,286 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 284 GetRequests, 95 SyntacticMatches, 35 SemanticMatches, 154 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7870 ImplicationChecksByTransitivity, 7.0s TimeCoverageRelationStatistics Valid=3307, Invalid=20873, Unknown=0, NotChecked=0, Total=24180 [2022-03-15 21:40:22,287 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 394 mSDsluCounter, 398 mSDsCounter, 0 mSdLazyCounter, 1790 mSolverCounterSat, 390 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 394 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2180 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 390 IncrementalHoareTripleChecker+Valid, 1790 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:40:22,287 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [394 Valid, 2 Invalid, 2180 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [390 Valid, 1790 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:40:22,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4258 states. [2022-03-15 21:40:22,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4258 to 937. [2022-03-15 21:40:22,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 937 states, 936 states have (on average 2.5117521367521367) internal successors, (2351), 936 states have internal predecessors, (2351), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:22,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 937 states to 937 states and 2351 transitions. [2022-03-15 21:40:22,317 INFO L78 Accepts]: Start accepts. Automaton has 937 states and 2351 transitions. Word has length 36 [2022-03-15 21:40:22,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:40:22,317 INFO L470 AbstractCegarLoop]: Abstraction has 937 states and 2351 transitions. [2022-03-15 21:40:22,317 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 35 states, 35 states have (on average 3.6285714285714286) internal successors, (127), 34 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:22,318 INFO L276 IsEmpty]: Start isEmpty. Operand 937 states and 2351 transitions. [2022-03-15 21:40:22,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:40:22,319 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:40:22,319 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:40:22,341 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Forceful destruction successful, exit code 0 [2022-03-15 21:40:22,532 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 45 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable45 [2022-03-15 21:40:22,533 INFO L402 AbstractCegarLoop]: === Iteration 47 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:40:22,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:40:22,533 INFO L85 PathProgramCache]: Analyzing trace with hash 2111107413, now seen corresponding path program 45 times [2022-03-15 21:40:22,534 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:40:22,534 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542546142] [2022-03-15 21:40:22,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:40:22,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:40:22,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:40:22,840 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 1 proven. 57 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-03-15 21:40:22,840 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:40:22,840 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542546142] [2022-03-15 21:40:22,840 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1542546142] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:40:22,841 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1638818746] [2022-03-15 21:40:22,841 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:40:22,841 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:40:22,841 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:40:22,851 INFO L229 MonitoredProcess]: Starting monitored process 46 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:40:22,861 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2022-03-15 21:40:22,890 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-03-15 21:40:22,890 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:40:22,891 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 43 conjunts are in the unsatisfiable core [2022-03-15 21:40:22,892 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:40:23,743 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,743 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,744 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,759 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,760 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,760 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,761 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,762 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,762 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,763 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,763 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,764 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,764 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:23,765 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:23,765 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,766 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,767 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,767 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:23,768 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:23,768 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 10 disjoint index pairs (out of 28 index pairs), introduced 5 new quantified variables, introduced 0 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:40:23,864 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 1 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:40:23,865 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:40:24,688 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,688 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,689 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,691 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,691 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,691 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,692 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,692 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,693 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,693 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,693 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,693 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,694 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,695 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,695 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,696 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,696 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,697 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,702 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,703 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,704 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,704 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,704 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,705 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:24,819 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:40:24,820 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 24 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 21 case distinctions, treesize of input 64 treesize of output 254 [2022-03-15 21:40:26,419 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:40:26,419 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1638818746] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:40:26,419 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:40:26,419 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 19, 19] total 50 [2022-03-15 21:40:26,419 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [364563239] [2022-03-15 21:40:26,419 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:40:26,422 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:40:26,441 INFO L252 McrAutomatonBuilder]: Finished intersection with 138 states and 271 transitions. [2022-03-15 21:40:26,442 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:40:31,072 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [157154#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 157164#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (<= front back) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= back front)) (or (not v_assert) (<= (+ d w) W) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)))), 157162#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 157159#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 157166#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 157170#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 157169#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 157158#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 157167#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 157155#(and (or (<= (+ d 1) W) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= back front))), 157163#(and (or (not v_assert) (<= (+ front 1) back) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (<= (+ d w 1) W) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ front 1)) (not (< 1 w)) (not (= (select queue back) 1)))), 157157#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 157165#(and (or (not v_assert) (<= (+ d temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 157161#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 157160#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ (select queue front) 2 d) W)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (+ 2 front) (+ back 1)))), 157156#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 157168#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:40:31,073 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 35 states [2022-03-15 21:40:31,073 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:40:31,073 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-03-15 21:40:31,073 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=486, Invalid=4070, Unknown=0, NotChecked=0, Total=4556 [2022-03-15 21:40:31,073 INFO L87 Difference]: Start difference. First operand 937 states and 2351 transitions. Second operand has 35 states, 35 states have (on average 3.5428571428571427) internal successors, (124), 34 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:35,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:40:35,531 INFO L93 Difference]: Finished difference Result 3721 states and 9373 transitions. [2022-03-15 21:40:35,531 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2022-03-15 21:40:35,531 INFO L78 Accepts]: Start accepts. Automaton has has 35 states, 35 states have (on average 3.5428571428571427) internal successors, (124), 34 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:40:35,532 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:40:35,536 INFO L225 Difference]: With dead ends: 3721 [2022-03-15 21:40:35,536 INFO L226 Difference]: Without dead ends: 3486 [2022-03-15 21:40:35,538 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 258 GetRequests, 86 SyntacticMatches, 38 SemanticMatches, 134 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5607 ImplicationChecksByTransitivity, 6.7s TimeCoverageRelationStatistics Valid=2708, Invalid=15652, Unknown=0, NotChecked=0, Total=18360 [2022-03-15 21:40:35,541 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 328 mSDsluCounter, 443 mSDsCounter, 0 mSdLazyCounter, 1781 mSolverCounterSat, 254 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 328 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2035 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 254 IncrementalHoareTripleChecker+Valid, 1781 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:40:35,541 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [328 Valid, 2 Invalid, 2035 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [254 Valid, 1781 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:40:35,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3486 states. [2022-03-15 21:40:35,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3486 to 1015. [2022-03-15 21:40:35,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1015 states, 1014 states have (on average 2.516765285996055) internal successors, (2552), 1014 states have internal predecessors, (2552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:35,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1015 states to 1015 states and 2552 transitions. [2022-03-15 21:40:35,559 INFO L78 Accepts]: Start accepts. Automaton has 1015 states and 2552 transitions. Word has length 36 [2022-03-15 21:40:35,559 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:40:35,559 INFO L470 AbstractCegarLoop]: Abstraction has 1015 states and 2552 transitions. [2022-03-15 21:40:35,559 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 35 states, 35 states have (on average 3.5428571428571427) internal successors, (124), 34 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:35,559 INFO L276 IsEmpty]: Start isEmpty. Operand 1015 states and 2552 transitions. [2022-03-15 21:40:35,560 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:40:35,560 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:40:35,560 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:40:35,576 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Ended with exit code 0 [2022-03-15 21:40:35,775 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 46 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable46 [2022-03-15 21:40:35,775 INFO L402 AbstractCegarLoop]: === Iteration 48 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:40:35,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:40:35,776 INFO L85 PathProgramCache]: Analyzing trace with hash 155745963, now seen corresponding path program 46 times [2022-03-15 21:40:35,776 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:40:35,776 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463897612] [2022-03-15 21:40:35,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:40:35,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:40:35,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:40:36,025 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 1 proven. 57 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-03-15 21:40:36,025 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:40:36,025 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1463897612] [2022-03-15 21:40:36,025 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1463897612] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:40:36,025 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1329821204] [2022-03-15 21:40:36,026 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:40:36,026 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:40:36,026 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:40:36,027 INFO L229 MonitoredProcess]: Starting monitored process 47 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:40:36,027 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2022-03-15 21:40:36,057 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:40:36,057 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:40:36,058 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:40:36,058 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:40:36,841 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:40:36,841 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:40:36,913 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:40:36,913 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:40:37,836 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:40:37,836 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:40:41,601 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:40:41,601 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1329821204] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:40:41,601 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:40:41,601 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 19, 19] total 48 [2022-03-15 21:40:41,601 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1077110016] [2022-03-15 21:40:41,601 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:40:41,604 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:40:41,622 INFO L252 McrAutomatonBuilder]: Finished intersection with 138 states and 271 transitions. [2022-03-15 21:40:41,622 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:40:46,557 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 18 new interpolants: [163329#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 163334#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (<= front back) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= back front)) (or (not v_assert) (<= (+ d w) W) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)))), 163324#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 163317#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 163330#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (<= (+ d w temp 1) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 163331#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 163326#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 163319#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 163327#(and (or (not v_assert) (not (< 0 w)) (<= front back)) (or (not v_assert) (<= (+ d w) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= back front))), 163333#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 163322#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 163318#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 163320#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not (= (select queue back) 1)) v_assert) (or (<= (+ d 1) W) (< 1 w) (not (= (select queue back) 1))) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1))), 163332#(and (or (not v_assert) (<= (+ front 1) back) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (<= (+ d w 1) W) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ front 1)) (not (< 1 w)) (not (= (select queue back) 1)))), 163328#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 163321#(and (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)))), 163323#(and (or (not v_assert) (<= (+ 2 d) W)) (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (= (select queue front) 1))), 163325#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ 2 d temp) W)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:40:46,557 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 34 states [2022-03-15 21:40:46,557 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:40:46,557 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2022-03-15 21:40:46,557 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=4044, Unknown=0, NotChecked=0, Total=4422 [2022-03-15 21:40:46,558 INFO L87 Difference]: Start difference. First operand 1015 states and 2552 transitions. Second operand has 34 states, 34 states have (on average 3.6176470588235294) internal successors, (123), 33 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:50,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:40:50,511 INFO L93 Difference]: Finished difference Result 4176 states and 10369 transitions. [2022-03-15 21:40:50,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2022-03-15 21:40:50,511 INFO L78 Accepts]: Start accepts. Automaton has has 34 states, 34 states have (on average 3.6176470588235294) internal successors, (123), 33 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:40:50,511 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:40:50,516 INFO L225 Difference]: With dead ends: 4176 [2022-03-15 21:40:50,516 INFO L226 Difference]: Without dead ends: 3959 [2022-03-15 21:40:50,517 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 262 GetRequests, 93 SyntacticMatches, 32 SemanticMatches, 137 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6022 ImplicationChecksByTransitivity, 5.6s TimeCoverageRelationStatistics Valid=2629, Invalid=16553, Unknown=0, NotChecked=0, Total=19182 [2022-03-15 21:40:50,517 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 468 mSDsluCounter, 469 mSDsCounter, 0 mSdLazyCounter, 1796 mSolverCounterSat, 338 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 468 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2134 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 338 IncrementalHoareTripleChecker+Valid, 1796 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:40:50,518 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [468 Valid, 2 Invalid, 2134 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [338 Valid, 1796 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:40:50,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3959 states. [2022-03-15 21:40:50,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3959 to 1263. [2022-03-15 21:40:50,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1263 states, 1262 states have (on average 2.5269413629160065) internal successors, (3189), 1262 states have internal predecessors, (3189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:50,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1263 states to 1263 states and 3189 transitions. [2022-03-15 21:40:50,537 INFO L78 Accepts]: Start accepts. Automaton has 1263 states and 3189 transitions. Word has length 36 [2022-03-15 21:40:50,538 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:40:50,538 INFO L470 AbstractCegarLoop]: Abstraction has 1263 states and 3189 transitions. [2022-03-15 21:40:50,538 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 34 states, 34 states have (on average 3.6176470588235294) internal successors, (123), 33 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:50,538 INFO L276 IsEmpty]: Start isEmpty. Operand 1263 states and 3189 transitions. [2022-03-15 21:40:50,539 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:40:50,539 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:40:50,539 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:40:50,555 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Ended with exit code 0 [2022-03-15 21:40:50,752 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable47,47 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:40:50,753 INFO L402 AbstractCegarLoop]: === Iteration 49 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:40:50,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:40:50,753 INFO L85 PathProgramCache]: Analyzing trace with hash -1539332251, now seen corresponding path program 47 times [2022-03-15 21:40:50,755 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:40:50,755 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1734884038] [2022-03-15 21:40:50,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:40:50,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:40:50,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:40:50,986 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 1 proven. 57 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-03-15 21:40:50,986 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:40:50,986 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1734884038] [2022-03-15 21:40:50,986 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1734884038] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:40:50,986 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [677312359] [2022-03-15 21:40:50,986 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:40:50,986 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:40:50,986 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:40:50,987 INFO L229 MonitoredProcess]: Starting monitored process 48 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:40:50,989 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2022-03-15 21:40:51,018 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2022-03-15 21:40:51,018 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:40:51,018 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:40:51,031 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:40:51,805 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,806 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,807 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:51,807 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,808 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,808 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,809 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,810 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,810 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,811 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,811 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,812 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,812 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:51,813 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,813 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,814 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,815 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,815 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:51,816 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,816 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,817 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,817 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,818 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:40:51,818 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:51,819 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:51,819 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 10 disjoint index pairs (out of 45 index pairs), introduced 5 new quantified variables, introduced 0 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:40:51,893 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:40:51,893 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:40:52,625 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,625 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,625 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,626 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,628 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,629 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,629 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,629 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,630 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,631 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,631 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,631 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,632 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,632 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,633 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,634 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,634 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,634 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,635 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,635 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,636 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,636 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,637 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,637 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,638 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,640 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,640 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,641 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,642 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,642 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:40:52,698 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:40:52,698 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 30 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 15 case distinctions, treesize of input 66 treesize of output 198 [2022-03-15 21:40:53,436 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:40:53,436 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [677312359] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:40:53,436 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:40:53,436 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 19, 19] total 48 [2022-03-15 21:40:53,436 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [251812260] [2022-03-15 21:40:53,436 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:40:53,439 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:40:53,457 INFO L252 McrAutomatonBuilder]: Finished intersection with 141 states and 277 transitions. [2022-03-15 21:40:53,458 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:40:58,089 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 18 new interpolants: [170452#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 170448#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 170450#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 170455#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 170444#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 170454#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ 2 d temp) W)) (or (not v_assert) (= (select queue front) 1))), 170445#(and (or (not v_assert) (<= (+ front 1) back) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (<= (+ d w 1) W) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ front 1)) (not (< 1 w)) (not (= (select queue back) 1)))), 170441#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 170457#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (<= front back) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= back front)) (or (not v_assert) (<= (+ d w) W) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)))), 170456#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 170451#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 170442#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 170446#(and (or (not v_assert) (<= (+ 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 170440#(and (or (not v_assert) (not (< 0 w)) (<= front back)) (or (not v_assert) (<= (+ d w) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= back front))), 170443#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (<= (+ d w temp 1) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 170453#(and (or (not v_assert) (<= (+ 2 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 170449#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 170447#(and (or (not v_assert) (<= (+ 2 d) W)) (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:40:58,090 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 34 states [2022-03-15 21:40:58,090 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:40:58,090 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2022-03-15 21:40:58,090 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=386, Invalid=4036, Unknown=0, NotChecked=0, Total=4422 [2022-03-15 21:40:58,090 INFO L87 Difference]: Start difference. First operand 1263 states and 3189 transitions. Second operand has 34 states, 34 states have (on average 3.7058823529411766) internal successors, (126), 33 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:01,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:41:01,554 INFO L93 Difference]: Finished difference Result 3661 states and 9074 transitions. [2022-03-15 21:41:01,554 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2022-03-15 21:41:01,554 INFO L78 Accepts]: Start accepts. Automaton has has 34 states, 34 states have (on average 3.7058823529411766) internal successors, (126), 33 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:41:01,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:41:01,560 INFO L225 Difference]: With dead ends: 3661 [2022-03-15 21:41:01,560 INFO L226 Difference]: Without dead ends: 3560 [2022-03-15 21:41:01,562 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 260 GetRequests, 97 SyntacticMatches, 31 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5472 ImplicationChecksByTransitivity, 5.3s TimeCoverageRelationStatistics Valid=2577, Invalid=15245, Unknown=0, NotChecked=0, Total=17822 [2022-03-15 21:41:01,562 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 387 mSDsluCounter, 544 mSDsCounter, 0 mSdLazyCounter, 1850 mSolverCounterSat, 251 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 387 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2101 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 251 IncrementalHoareTripleChecker+Valid, 1850 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-03-15 21:41:01,562 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [387 Valid, 2 Invalid, 2101 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [251 Valid, 1850 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-03-15 21:41:01,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3560 states. [2022-03-15 21:41:01,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3560 to 1105. [2022-03-15 21:41:01,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1105 states, 1104 states have (on average 2.472826086956522) internal successors, (2730), 1104 states have internal predecessors, (2730), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:01,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1105 states to 1105 states and 2730 transitions. [2022-03-15 21:41:01,588 INFO L78 Accepts]: Start accepts. Automaton has 1105 states and 2730 transitions. Word has length 36 [2022-03-15 21:41:01,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:41:01,588 INFO L470 AbstractCegarLoop]: Abstraction has 1105 states and 2730 transitions. [2022-03-15 21:41:01,588 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 34 states, 34 states have (on average 3.7058823529411766) internal successors, (126), 33 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:01,588 INFO L276 IsEmpty]: Start isEmpty. Operand 1105 states and 2730 transitions. [2022-03-15 21:41:01,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:41:01,590 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:41:01,590 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:41:01,612 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Forceful destruction successful, exit code 0 [2022-03-15 21:41:01,791 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 48 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable48 [2022-03-15 21:41:01,791 INFO L402 AbstractCegarLoop]: === Iteration 50 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:41:01,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:41:01,792 INFO L85 PathProgramCache]: Analyzing trace with hash -350546545, now seen corresponding path program 48 times [2022-03-15 21:41:01,792 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:41:01,792 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020975982] [2022-03-15 21:41:01,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:41:01,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:41:01,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:41:02,079 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 3 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:02,079 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:41:02,079 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2020975982] [2022-03-15 21:41:02,079 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2020975982] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:41:02,079 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [548415363] [2022-03-15 21:41:02,079 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:41:02,079 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:41:02,079 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:41:02,081 INFO L229 MonitoredProcess]: Starting monitored process 49 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:41:02,119 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2022-03-15 21:41:02,124 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2022-03-15 21:41:02,124 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:41:02,124 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 47 conjunts are in the unsatisfiable core [2022-03-15 21:41:02,125 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:41:02,786 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,787 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,787 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,788 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,788 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,789 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,789 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,789 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,790 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,790 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,791 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,791 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,791 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,792 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,792 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,793 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,793 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:02,793 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,794 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,794 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:02,794 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:02,795 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:02,795 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 10 disjoint index pairs (out of 28 index pairs), introduced 5 new quantified variables, introduced 0 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:41:02,850 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:02,850 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:41:03,525 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,526 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,527 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,527 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,529 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,529 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,530 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,531 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,531 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,531 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,531 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,532 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,532 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,532 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,533 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,533 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,534 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,534 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,534 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,535 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,537 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,539 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,539 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,539 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:03,605 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:41:03,605 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 24 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 21 case distinctions, treesize of input 64 treesize of output 254 [2022-03-15 21:41:04,433 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:04,433 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [548415363] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:41:04,433 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:41:04,433 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 19] total 51 [2022-03-15 21:41:04,433 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [887472535] [2022-03-15 21:41:04,433 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:41:04,438 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:41:04,457 INFO L252 McrAutomatonBuilder]: Finished intersection with 144 states and 283 transitions. [2022-03-15 21:41:04,457 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:41:09,860 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [176732#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (= (select queue (+ 2 front)) 1)) (or (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not (= (select queue back) 1)) v_assert (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 176739#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 176728#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 176735#(and (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (= (select queue (+ 2 front)) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1)))), 176725#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 176736#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 176729#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 176741#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 176726#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 176737#(and (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 176730#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (+ (- 1) temp) 0) v_assert) (or v_assert (<= (+ 2 d temp) W)) (or (= (select queue front) 1) (< 0 w)) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ 2 d temp) W) (< 0 w))), 176733#(and (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W))), 176734#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)))), 176740#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (<= (+ d w) W) (not (< 0 w)))), 176727#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 176731#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w))), 176738#(and (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w temp 1) W)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:41:09,861 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2022-03-15 21:41:09,861 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:41:09,861 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-03-15 21:41:09,861 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=560, Invalid=4132, Unknown=0, NotChecked=0, Total=4692 [2022-03-15 21:41:09,861 INFO L87 Difference]: Start difference. First operand 1105 states and 2730 transitions. Second operand has 36 states, 36 states have (on average 3.5833333333333335) internal successors, (129), 35 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:16,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:41:16,737 INFO L93 Difference]: Finished difference Result 4967 states and 12127 transitions. [2022-03-15 21:41:16,737 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 87 states. [2022-03-15 21:41:16,738 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 36 states have (on average 3.5833333333333335) internal successors, (129), 35 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:41:16,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:41:16,744 INFO L225 Difference]: With dead ends: 4967 [2022-03-15 21:41:16,744 INFO L226 Difference]: Without dead ends: 4868 [2022-03-15 21:41:16,745 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 279 GetRequests, 104 SyntacticMatches, 25 SemanticMatches, 150 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7006 ImplicationChecksByTransitivity, 8.4s TimeCoverageRelationStatistics Valid=3599, Invalid=19353, Unknown=0, NotChecked=0, Total=22952 [2022-03-15 21:41:16,745 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 364 mSDsluCounter, 516 mSDsCounter, 0 mSdLazyCounter, 1866 mSolverCounterSat, 337 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 364 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 2203 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 337 IncrementalHoareTripleChecker+Valid, 1866 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-03-15 21:41:16,745 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [364 Valid, 1 Invalid, 2203 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [337 Valid, 1866 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-03-15 21:41:16,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4868 states. [2022-03-15 21:41:16,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4868 to 1253. [2022-03-15 21:41:16,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1253 states, 1252 states have (on average 2.5151757188498403) internal successors, (3149), 1252 states have internal predecessors, (3149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:16,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1253 states to 1253 states and 3149 transitions. [2022-03-15 21:41:16,771 INFO L78 Accepts]: Start accepts. Automaton has 1253 states and 3149 transitions. Word has length 36 [2022-03-15 21:41:16,771 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:41:16,771 INFO L470 AbstractCegarLoop]: Abstraction has 1253 states and 3149 transitions. [2022-03-15 21:41:16,771 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 36 states have (on average 3.5833333333333335) internal successors, (129), 35 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:16,771 INFO L276 IsEmpty]: Start isEmpty. Operand 1253 states and 3149 transitions. [2022-03-15 21:41:16,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:41:16,773 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:41:16,773 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:41:16,790 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Forceful destruction successful, exit code 0 [2022-03-15 21:41:16,987 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 49 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable49 [2022-03-15 21:41:16,987 INFO L402 AbstractCegarLoop]: === Iteration 51 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:41:16,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:41:16,988 INFO L85 PathProgramCache]: Analyzing trace with hash -1229193151, now seen corresponding path program 49 times [2022-03-15 21:41:16,989 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:41:16,989 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859900981] [2022-03-15 21:41:16,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:41:16,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:41:16,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:41:17,294 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 3 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:17,294 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:41:17,294 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1859900981] [2022-03-15 21:41:17,294 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1859900981] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:41:17,294 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [369646385] [2022-03-15 21:41:17,294 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-03-15 21:41:17,295 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:41:17,295 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:41:17,296 INFO L229 MonitoredProcess]: Starting monitored process 50 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:41:17,297 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2022-03-15 21:41:17,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:41:17,324 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:41:17,325 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:41:18,049 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:41:18,050 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:41:18,099 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:18,099 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:41:18,864 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:41:18,864 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:41:21,867 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:21,868 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [369646385] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:41:21,868 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:41:21,868 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 19] total 51 [2022-03-15 21:41:21,868 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1769289661] [2022-03-15 21:41:21,868 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:41:21,874 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:41:21,893 INFO L252 McrAutomatonBuilder]: Finished intersection with 141 states and 277 transitions. [2022-03-15 21:41:21,893 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:41:27,498 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [184650#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (<= (+ 2 d) W) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 184648#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 184659#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 184645#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 184643#(and (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 184646#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 184652#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 184653#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 184649#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 184644#(and (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 184651#(and (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1))), 184655#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (<= front back) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ 3 d) W)) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= back front))), 184654#(and (or (not v_assert) (<= (+ front 1) back) (not (< 1 w)) (not (= (select queue back) 1))) (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (<= back (+ front 1)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 3 d) W))), 184658#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (<= (+ d w) W) (not (< 0 w)))), 184656#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 184647#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 184657#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w)))] [2022-03-15 21:41:27,498 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2022-03-15 21:41:27,498 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:41:27,499 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-03-15 21:41:27,499 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=422, Invalid=4270, Unknown=0, NotChecked=0, Total=4692 [2022-03-15 21:41:27,499 INFO L87 Difference]: Start difference. First operand 1253 states and 3149 transitions. Second operand has 36 states, 36 states have (on average 3.5277777777777777) internal successors, (127), 35 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:30,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:41:30,634 INFO L93 Difference]: Finished difference Result 4047 states and 10030 transitions. [2022-03-15 21:41:30,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2022-03-15 21:41:30,634 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 36 states have (on average 3.5277777777777777) internal successors, (127), 35 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:41:30,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:41:30,640 INFO L225 Difference]: With dead ends: 4047 [2022-03-15 21:41:30,640 INFO L226 Difference]: Without dead ends: 4020 [2022-03-15 21:41:30,641 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 252 GetRequests, 97 SyntacticMatches, 29 SemanticMatches, 126 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5412 ImplicationChecksByTransitivity, 5.0s TimeCoverageRelationStatistics Valid=2192, Invalid=14064, Unknown=0, NotChecked=0, Total=16256 [2022-03-15 21:41:30,641 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 334 mSDsluCounter, 467 mSDsCounter, 0 mSdLazyCounter, 1515 mSolverCounterSat, 249 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 334 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1764 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 249 IncrementalHoareTripleChecker+Valid, 1515 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-03-15 21:41:30,641 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [334 Valid, 2 Invalid, 1764 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [249 Valid, 1515 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-03-15 21:41:30,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4020 states. [2022-03-15 21:41:30,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4020 to 1273. [2022-03-15 21:41:30,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1273 states, 1272 states have (on average 2.5157232704402515) internal successors, (3200), 1272 states have internal predecessors, (3200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:30,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1273 states to 1273 states and 3200 transitions. [2022-03-15 21:41:30,663 INFO L78 Accepts]: Start accepts. Automaton has 1273 states and 3200 transitions. Word has length 36 [2022-03-15 21:41:30,664 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:41:30,664 INFO L470 AbstractCegarLoop]: Abstraction has 1273 states and 3200 transitions. [2022-03-15 21:41:30,664 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 36 states have (on average 3.5277777777777777) internal successors, (127), 35 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:30,664 INFO L276 IsEmpty]: Start isEmpty. Operand 1273 states and 3200 transitions. [2022-03-15 21:41:30,665 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:41:30,665 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:41:30,665 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:41:30,684 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Forceful destruction successful, exit code 0 [2022-03-15 21:41:30,882 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable50,50 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:41:30,882 INFO L402 AbstractCegarLoop]: === Iteration 52 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:41:30,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:41:30,883 INFO L85 PathProgramCache]: Analyzing trace with hash -1469553969, now seen corresponding path program 50 times [2022-03-15 21:41:30,883 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:41:30,883 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [855781791] [2022-03-15 21:41:30,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:41:30,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:41:30,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:41:31,193 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 3 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:31,193 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:41:31,193 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [855781791] [2022-03-15 21:41:31,193 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [855781791] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:41:31,193 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [728234428] [2022-03-15 21:41:31,193 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:41:31,193 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:41:31,194 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:41:31,197 INFO L229 MonitoredProcess]: Starting monitored process 51 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:41:31,198 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2022-03-15 21:41:31,252 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:41:31,252 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:41:31,253 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:41:31,254 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:41:32,017 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:41:32,017 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:41:32,083 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:32,083 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:41:32,819 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:41:32,819 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:41:36,552 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:36,552 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [728234428] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:41:36,552 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:41:36,552 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 19] total 51 [2022-03-15 21:41:36,552 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [214390919] [2022-03-15 21:41:36,552 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:41:36,555 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:41:36,574 INFO L252 McrAutomatonBuilder]: Finished intersection with 138 states and 271 transitions. [2022-03-15 21:41:36,575 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:41:40,559 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [191640#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 191644#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ (select queue front) 2 d) W)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (+ 2 front) (+ back 1)))), 191642#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 191638#(and (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 191639#(and (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)))), 191634#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 191646#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 191645#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (+ 2 back) (+ 2 front)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (<= (+ (select queue front) 2 d) W) (not (= (select queue (+ back 1)) 1)))), 191633#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 191649#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 191641#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 191647#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (<= (+ d w) W) (not (< 0 w)))), 191635#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 191637#(and (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 191648#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 191643#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 191636#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not (= (select queue back) 1)) v_assert) (or (<= (+ d 1) W) (< 1 w) (not (= (select queue back) 1))) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)))] [2022-03-15 21:41:40,560 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2022-03-15 21:41:40,560 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:41:40,560 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-03-15 21:41:40,560 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=430, Invalid=4262, Unknown=0, NotChecked=0, Total=4692 [2022-03-15 21:41:40,560 INFO L87 Difference]: Start difference. First operand 1273 states and 3200 transitions. Second operand has 36 states, 36 states have (on average 3.4722222222222223) internal successors, (125), 35 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:43,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:41:43,956 INFO L93 Difference]: Finished difference Result 3628 states and 8967 transitions. [2022-03-15 21:41:43,956 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2022-03-15 21:41:43,957 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 36 states have (on average 3.4722222222222223) internal successors, (125), 35 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:41:43,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:41:43,961 INFO L225 Difference]: With dead ends: 3628 [2022-03-15 21:41:43,961 INFO L226 Difference]: Without dead ends: 3596 [2022-03-15 21:41:43,962 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 248 GetRequests, 97 SyntacticMatches, 26 SemanticMatches, 125 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5018 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=2100, Invalid=13902, Unknown=0, NotChecked=0, Total=16002 [2022-03-15 21:41:43,963 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 318 mSDsluCounter, 457 mSDsCounter, 0 mSdLazyCounter, 1462 mSolverCounterSat, 230 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 318 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1692 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 230 IncrementalHoareTripleChecker+Valid, 1462 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-03-15 21:41:43,963 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [318 Valid, 2 Invalid, 1692 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [230 Valid, 1462 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-03-15 21:41:43,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3596 states. [2022-03-15 21:41:43,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3596 to 1285. [2022-03-15 21:41:43,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1285 states, 1284 states have (on average 2.514018691588785) internal successors, (3228), 1284 states have internal predecessors, (3228), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:43,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1285 states to 1285 states and 3228 transitions. [2022-03-15 21:41:43,997 INFO L78 Accepts]: Start accepts. Automaton has 1285 states and 3228 transitions. Word has length 36 [2022-03-15 21:41:43,997 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:41:43,997 INFO L470 AbstractCegarLoop]: Abstraction has 1285 states and 3228 transitions. [2022-03-15 21:41:43,997 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 36 states have (on average 3.4722222222222223) internal successors, (125), 35 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:43,997 INFO L276 IsEmpty]: Start isEmpty. Operand 1285 states and 3228 transitions. [2022-03-15 21:41:43,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:41:43,999 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:41:43,999 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:41:44,027 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Forceful destruction successful, exit code 0 [2022-03-15 21:41:44,215 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 51 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable51 [2022-03-15 21:41:44,215 INFO L402 AbstractCegarLoop]: === Iteration 53 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:41:44,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:41:44,216 INFO L85 PathProgramCache]: Analyzing trace with hash 1485863137, now seen corresponding path program 51 times [2022-03-15 21:41:44,216 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:41:44,216 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998510116] [2022-03-15 21:41:44,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:41:44,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:41:44,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:41:44,514 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 3 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:44,514 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:41:44,514 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [998510116] [2022-03-15 21:41:44,514 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [998510116] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:41:44,514 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1918249008] [2022-03-15 21:41:44,514 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:41:44,514 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:41:44,515 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:41:44,520 INFO L229 MonitoredProcess]: Starting monitored process 52 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:41:44,523 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2022-03-15 21:41:44,549 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-03-15 21:41:44,549 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:41:44,550 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:41:44,551 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:41:45,140 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:41:45,141 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:41:45,193 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:45,193 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:41:46,013 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:41:46,014 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:41:50,439 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:50,439 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1918249008] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:41:50,439 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:41:50,439 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 19] total 51 [2022-03-15 21:41:50,440 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [205453900] [2022-03-15 21:41:50,440 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:41:50,442 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:41:50,459 INFO L252 McrAutomatonBuilder]: Finished intersection with 125 states and 241 transitions. [2022-03-15 21:41:50,459 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:41:54,255 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 16 new interpolants: [198236#(and (or (not v_assert) (<= (+ d temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 198227#(and (or (<= (+ d 1) W) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= back front))), 198231#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 198241#(and v_assert (< 0 w)), 198240#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 198239#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 198235#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 198229#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 198230#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 198237#(and (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 198233#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ (select queue front) 2 d) W)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (+ 2 front) (+ back 1)))), 198238#(and (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 198228#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 198234#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (+ 2 back) (+ 2 front)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (<= (+ (select queue front) 2 d) W) (not (= (select queue (+ back 1)) 1)))), 198232#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 198226#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (<= (+ d w) W) (not (< 0 w))))] [2022-03-15 21:41:54,255 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 35 states [2022-03-15 21:41:54,255 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:41:54,255 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-03-15 21:41:54,255 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=383, Invalid=4173, Unknown=0, NotChecked=0, Total=4556 [2022-03-15 21:41:54,256 INFO L87 Difference]: Start difference. First operand 1285 states and 3228 transitions. Second operand has 35 states, 35 states have (on average 3.2857142857142856) internal successors, (115), 34 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:56,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:41:56,925 INFO L93 Difference]: Finished difference Result 2841 states and 7032 transitions. [2022-03-15 21:41:56,925 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2022-03-15 21:41:56,926 INFO L78 Accepts]: Start accepts. Automaton has has 35 states, 35 states have (on average 3.2857142857142856) internal successors, (115), 34 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:41:56,926 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:41:56,929 INFO L225 Difference]: With dead ends: 2841 [2022-03-15 21:41:56,929 INFO L226 Difference]: Without dead ends: 2838 [2022-03-15 21:41:56,929 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 227 GetRequests, 86 SyntacticMatches, 25 SemanticMatches, 116 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4341 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=1477, Invalid=12329, Unknown=0, NotChecked=0, Total=13806 [2022-03-15 21:41:56,929 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 297 mSDsluCounter, 388 mSDsCounter, 0 mSdLazyCounter, 1232 mSolverCounterSat, 203 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 297 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1435 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 203 IncrementalHoareTripleChecker+Valid, 1232 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-03-15 21:41:56,929 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [297 Valid, 2 Invalid, 1435 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [203 Valid, 1232 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-03-15 21:41:56,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2838 states. [2022-03-15 21:41:56,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2838 to 1273. [2022-03-15 21:41:56,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1273 states, 1272 states have (on average 2.5157232704402515) internal successors, (3200), 1272 states have internal predecessors, (3200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:56,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1273 states to 1273 states and 3200 transitions. [2022-03-15 21:41:56,946 INFO L78 Accepts]: Start accepts. Automaton has 1273 states and 3200 transitions. Word has length 36 [2022-03-15 21:41:56,946 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:41:56,946 INFO L470 AbstractCegarLoop]: Abstraction has 1273 states and 3200 transitions. [2022-03-15 21:41:56,946 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 35 states, 35 states have (on average 3.2857142857142856) internal successors, (115), 34 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:56,946 INFO L276 IsEmpty]: Start isEmpty. Operand 1273 states and 3200 transitions. [2022-03-15 21:41:56,948 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:41:56,948 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:41:56,948 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:41:56,964 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Ended with exit code 0 [2022-03-15 21:41:57,163 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable52,52 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:41:57,163 INFO L402 AbstractCegarLoop]: === Iteration 54 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:41:57,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:41:57,164 INFO L85 PathProgramCache]: Analyzing trace with hash 1472621833, now seen corresponding path program 52 times [2022-03-15 21:41:57,175 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:41:57,175 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694084131] [2022-03-15 21:41:57,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:41:57,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:41:57,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:41:57,454 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 3 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:57,454 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:41:57,454 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [694084131] [2022-03-15 21:41:57,454 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [694084131] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:41:57,454 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [296585329] [2022-03-15 21:41:57,454 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:41:57,455 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:41:57,455 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:41:57,456 INFO L229 MonitoredProcess]: Starting monitored process 53 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:41:57,456 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2022-03-15 21:41:57,484 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:41:57,484 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:41:57,485 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:41:57,486 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:41:58,185 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:41:58,186 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:41:58,256 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:58,257 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:41:59,099 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:41:59,100 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:42:02,442 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:02,442 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [296585329] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:42:02,442 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:42:02,442 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 19] total 51 [2022-03-15 21:42:02,442 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1284700113] [2022-03-15 21:42:02,442 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:42:02,460 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:42:02,486 INFO L252 McrAutomatonBuilder]: Finished intersection with 119 states and 226 transitions. [2022-03-15 21:42:02,486 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:42:05,831 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 14 new interpolants: [203993#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 203998#(and (or (not v_assert) (<= (+ 2 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 203996#(and (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 203992#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 203999#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 204003#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 203995#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (<= front back) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ 3 d) W)) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= back front))), 204000#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 204002#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (<= (+ d w) W) (not (< 0 w)))), 203991#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)))), 203994#(and (or (not v_assert) (<= (+ front 1) back) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ front 1)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 3 d) W))), 203997#(and (or (not v_assert) (<= (+ 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 204004#(and v_assert (< 0 w)), 204001#(and (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w temp 1) W)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:42:05,831 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 33 states [2022-03-15 21:42:05,831 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:42:05,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2022-03-15 21:42:05,832 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=359, Invalid=3931, Unknown=0, NotChecked=0, Total=4290 [2022-03-15 21:42:05,832 INFO L87 Difference]: Start difference. First operand 1273 states and 3200 transitions. Second operand has 33 states, 33 states have (on average 3.272727272727273) internal successors, (108), 32 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:08,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:42:08,695 INFO L93 Difference]: Finished difference Result 2971 states and 7358 transitions. [2022-03-15 21:42:08,695 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2022-03-15 21:42:08,695 INFO L78 Accepts]: Start accepts. Automaton has has 33 states, 33 states have (on average 3.272727272727273) internal successors, (108), 32 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:42:08,695 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:42:08,699 INFO L225 Difference]: With dead ends: 2971 [2022-03-15 21:42:08,699 INFO L226 Difference]: Without dead ends: 2968 [2022-03-15 21:42:08,700 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 220 GetRequests, 87 SyntacticMatches, 20 SemanticMatches, 113 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3840 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=1457, Invalid=11653, Unknown=0, NotChecked=0, Total=13110 [2022-03-15 21:42:08,707 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 283 mSDsluCounter, 472 mSDsCounter, 0 mSdLazyCounter, 1471 mSolverCounterSat, 191 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 283 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1662 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 191 IncrementalHoareTripleChecker+Valid, 1471 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-03-15 21:42:08,708 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [283 Valid, 2 Invalid, 1662 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [191 Valid, 1471 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-03-15 21:42:08,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2968 states. [2022-03-15 21:42:08,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2968 to 1259. [2022-03-15 21:42:08,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1259 states, 1258 states have (on average 2.5151033386327506) internal successors, (3164), 1258 states have internal predecessors, (3164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:08,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1259 states to 1259 states and 3164 transitions. [2022-03-15 21:42:08,737 INFO L78 Accepts]: Start accepts. Automaton has 1259 states and 3164 transitions. Word has length 36 [2022-03-15 21:42:08,737 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:42:08,737 INFO L470 AbstractCegarLoop]: Abstraction has 1259 states and 3164 transitions. [2022-03-15 21:42:08,737 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 33 states, 33 states have (on average 3.272727272727273) internal successors, (108), 32 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:08,737 INFO L276 IsEmpty]: Start isEmpty. Operand 1259 states and 3164 transitions. [2022-03-15 21:42:08,739 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:42:08,739 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:42:08,739 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:42:08,755 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Ended with exit code 0 [2022-03-15 21:42:08,954 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 53 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable53 [2022-03-15 21:42:08,954 INFO L402 AbstractCegarLoop]: === Iteration 55 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:42:08,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:42:08,955 INFO L85 PathProgramCache]: Analyzing trace with hash 2137925601, now seen corresponding path program 53 times [2022-03-15 21:42:08,979 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:42:08,979 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15323455] [2022-03-15 21:42:08,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:42:08,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:42:08,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:42:09,291 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 3 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:09,291 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:42:09,291 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [15323455] [2022-03-15 21:42:09,292 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [15323455] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:42:09,292 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [706646418] [2022-03-15 21:42:09,292 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:42:09,292 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:42:09,292 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:42:09,293 INFO L229 MonitoredProcess]: Starting monitored process 54 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:42:09,294 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2022-03-15 21:42:09,323 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2022-03-15 21:42:09,323 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:42:09,324 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:42:09,325 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:42:10,155 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,156 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,156 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,157 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,157 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,158 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,158 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,159 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,159 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,160 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,160 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,161 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,161 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,162 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,162 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,163 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,163 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,163 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,164 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,165 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,165 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,165 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,166 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,166 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:42:10,167 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,168 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 10 disjoint index pairs (out of 45 index pairs), introduced 5 new quantified variables, introduced 0 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:42:10,240 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:10,240 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:42:10,849 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,850 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,850 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,851 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,852 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,852 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,853 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,853 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,853 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,854 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,854 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,854 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,854 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,855 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,856 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,856 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,856 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,857 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,857 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,857 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,858 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,858 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,859 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,859 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,860 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,861 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,861 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,862 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,862 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,862 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:42:10,906 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:42:10,906 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 30 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 15 case distinctions, treesize of input 66 treesize of output 198 [2022-03-15 21:42:11,373 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:11,373 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [706646418] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:42:11,373 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:42:11,373 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 19] total 51 [2022-03-15 21:42:11,373 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1763151575] [2022-03-15 21:42:11,373 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:42:11,375 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:42:11,420 INFO L252 McrAutomatonBuilder]: Finished intersection with 113 states and 211 transitions. [2022-03-15 21:42:11,420 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:42:14,478 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 12 new interpolants: [209857#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 209864#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (<= (+ d w) W) (not (< 0 w)))), 209856#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (<= front back) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ 3 d) W)) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= back front))), 209863#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 209855#(and (or (not v_assert) (<= (+ front 1) back) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ front 1)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 3 d) W))), 209861#(and (or (not v_assert) (<= (+ 3 d temp) W)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 209858#(and (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 209859#(and (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 209854#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 209862#(and (or (not v_assert) (not (< 0 w)) (= (+ back (* (- 1) front)) 0)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 209860#(and (or (not v_assert) (<= (+ 3 d) W)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 209865#(and v_assert (< 0 w))] [2022-03-15 21:42:14,479 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 31 states [2022-03-15 21:42:14,479 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:42:14,479 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2022-03-15 21:42:14,479 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=345, Invalid=3687, Unknown=0, NotChecked=0, Total=4032 [2022-03-15 21:42:14,479 INFO L87 Difference]: Start difference. First operand 1259 states and 3164 transitions. Second operand has 31 states, 31 states have (on average 3.2580645161290325) internal successors, (101), 30 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:17,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:42:17,667 INFO L93 Difference]: Finished difference Result 3166 states and 7875 transitions. [2022-03-15 21:42:17,668 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2022-03-15 21:42:17,668 INFO L78 Accepts]: Start accepts. Automaton has has 31 states, 31 states have (on average 3.2580645161290325) internal successors, (101), 30 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:42:17,668 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:42:17,672 INFO L225 Difference]: With dead ends: 3166 [2022-03-15 21:42:17,672 INFO L226 Difference]: Without dead ends: 3149 [2022-03-15 21:42:17,673 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 218 GetRequests, 84 SyntacticMatches, 19 SemanticMatches, 115 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3709 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=1551, Invalid=12021, Unknown=0, NotChecked=0, Total=13572 [2022-03-15 21:42:17,677 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 265 mSDsluCounter, 513 mSDsCounter, 0 mSdLazyCounter, 1656 mSolverCounterSat, 192 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 265 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1848 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 192 IncrementalHoareTripleChecker+Valid, 1656 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-03-15 21:42:17,678 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [265 Valid, 2 Invalid, 1848 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [192 Valid, 1656 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-03-15 21:42:17,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3149 states. [2022-03-15 21:42:17,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3149 to 1183. [2022-03-15 21:42:17,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1183 states, 1182 states have (on average 2.469543147208122) internal successors, (2919), 1182 states have internal predecessors, (2919), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:17,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1183 states to 1183 states and 2919 transitions. [2022-03-15 21:42:17,699 INFO L78 Accepts]: Start accepts. Automaton has 1183 states and 2919 transitions. Word has length 36 [2022-03-15 21:42:17,699 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:42:17,699 INFO L470 AbstractCegarLoop]: Abstraction has 1183 states and 2919 transitions. [2022-03-15 21:42:17,699 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 31 states, 31 states have (on average 3.2580645161290325) internal successors, (101), 30 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:17,699 INFO L276 IsEmpty]: Start isEmpty. Operand 1183 states and 2919 transitions. [2022-03-15 21:42:17,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:42:17,700 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:42:17,700 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:42:17,742 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Forceful destruction successful, exit code 0 [2022-03-15 21:42:17,915 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 54 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable54 [2022-03-15 21:42:17,916 INFO L402 AbstractCegarLoop]: === Iteration 56 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:42:17,916 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:42:17,916 INFO L85 PathProgramCache]: Analyzing trace with hash -776804913, now seen corresponding path program 54 times [2022-03-15 21:42:17,917 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:42:17,917 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961861778] [2022-03-15 21:42:17,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:42:17,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:42:17,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:42:18,256 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:18,256 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:42:18,256 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961861778] [2022-03-15 21:42:18,256 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [961861778] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:42:18,256 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [427517679] [2022-03-15 21:42:18,256 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:42:18,256 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:42:18,256 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:42:18,257 INFO L229 MonitoredProcess]: Starting monitored process 55 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:42:18,258 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2022-03-15 21:42:18,291 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2022-03-15 21:42:18,292 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:42:18,295 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:42:18,296 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:42:18,915 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:42:18,915 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:42:18,979 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:18,979 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:42:19,641 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:42:19,642 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:42:23,907 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 7 proven. 53 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:23,908 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [427517679] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:42:23,908 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:42:23,908 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:42:23,908 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [717845822] [2022-03-15 21:42:23,908 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:42:23,911 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:42:23,934 INFO L252 McrAutomatonBuilder]: Finished intersection with 145 states and 283 transitions. [2022-03-15 21:42:23,934 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:42:31,765 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [215767#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 215776#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ 3 front)) 1) (not (= (select queue back) 1)) v_assert) (or (= (select queue (+ 3 front)) 1) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (< 1 w) (not (= (select queue back) 1)) (<= (+ d 4) W)) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (<= (+ d 4) W)) (or (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 215772#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (+ (- 1) temp) 0) v_assert) (or v_assert (<= (+ 2 d temp) W)) (or (= (select queue front) 1) (< 0 w)) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ 2 d temp) W) (< 0 w))), 215782#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 215774#(and (or v_assert (<= (+ d 4) W)) (or (= temp 1) (< 0 w)) (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (< 0 w) (<= (+ d 4) W)) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (= (select queue front) 1) (< 0 w)) (or v_assert (= temp 1))), 215778#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (= (select queue (+ 3 front)) 1) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W))), 215777#(and (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (not (< 0 w)) (= (select queue (+ 3 front)) 1) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (<= (+ d 4) W))), 215773#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w))), 215769#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 215781#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 215768#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 215783#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 215780#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 215779#(and (or (= (select queue (+ front 1)) 1) (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (= (select queue (+ 3 front)) 1) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (= (select queue (+ 2 front)) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W)) (or (not v_assert) (not (= (select queue (+ 2 back)) 1)) (not (= (select queue back) 1)) (< 3 w) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1)))), 215771#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 215775#(and (or v_assert (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (< 0 w) (<= (+ d 4) W)) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ 3 front)) 1) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (= (select queue (+ 3 front)) 1) (< 0 w))), 215770#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)))] [2022-03-15 21:42:31,765 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-03-15 21:42:31,765 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:42:31,765 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-03-15 21:42:31,765 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=477, Invalid=4353, Unknown=0, NotChecked=0, Total=4830 [2022-03-15 21:42:31,766 INFO L87 Difference]: Start difference. First operand 1183 states and 2919 transitions. Second operand has 37 states, 37 states have (on average 3.5405405405405403) internal successors, (131), 36 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:38,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:42:38,530 INFO L93 Difference]: Finished difference Result 4502 states and 11247 transitions. [2022-03-15 21:42:38,530 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2022-03-15 21:42:38,531 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 3.5405405405405403) internal successors, (131), 36 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:42:38,531 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:42:38,537 INFO L225 Difference]: With dead ends: 4502 [2022-03-15 21:42:38,537 INFO L226 Difference]: Without dead ends: 4422 [2022-03-15 21:42:38,538 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 292 GetRequests, 104 SyntacticMatches, 25 SemanticMatches, 163 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8589 ImplicationChecksByTransitivity, 8.3s TimeCoverageRelationStatistics Valid=4361, Invalid=22699, Unknown=0, NotChecked=0, Total=27060 [2022-03-15 21:42:38,542 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 352 mSDsluCounter, 607 mSDsCounter, 0 mSdLazyCounter, 2137 mSolverCounterSat, 265 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 352 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2402 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 265 IncrementalHoareTripleChecker+Valid, 2137 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-03-15 21:42:38,543 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [352 Valid, 2 Invalid, 2402 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [265 Valid, 2137 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-03-15 21:42:38,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4422 states. [2022-03-15 21:42:38,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4422 to 1323. [2022-03-15 21:42:38,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1323 states, 1322 states have (on average 2.5015128593040847) internal successors, (3307), 1322 states have internal predecessors, (3307), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:38,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1323 states to 1323 states and 3307 transitions. [2022-03-15 21:42:38,571 INFO L78 Accepts]: Start accepts. Automaton has 1323 states and 3307 transitions. Word has length 36 [2022-03-15 21:42:38,571 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:42:38,571 INFO L470 AbstractCegarLoop]: Abstraction has 1323 states and 3307 transitions. [2022-03-15 21:42:38,572 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 3.5405405405405403) internal successors, (131), 36 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:38,572 INFO L276 IsEmpty]: Start isEmpty. Operand 1323 states and 3307 transitions. [2022-03-15 21:42:38,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:42:38,574 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:42:38,574 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:42:38,591 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Forceful destruction successful, exit code 0 [2022-03-15 21:42:38,789 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable55,55 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:42:38,790 INFO L402 AbstractCegarLoop]: === Iteration 57 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:42:38,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:42:38,790 INFO L85 PathProgramCache]: Analyzing trace with hash 1287824861, now seen corresponding path program 55 times [2022-03-15 21:42:38,791 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:42:38,791 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [580570972] [2022-03-15 21:42:38,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:42:38,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:42:38,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:42:39,234 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:39,234 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:42:39,234 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [580570972] [2022-03-15 21:42:39,234 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [580570972] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:42:39,234 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [192340473] [2022-03-15 21:42:39,234 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-03-15 21:42:39,234 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:42:39,234 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:42:39,236 INFO L229 MonitoredProcess]: Starting monitored process 56 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:42:39,236 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2022-03-15 21:42:39,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:42:39,265 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:42:39,265 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:42:39,876 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:42:39,876 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:42:39,952 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:39,953 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:42:40,784 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:42:40,785 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:42:43,579 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 3 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:43,579 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [192340473] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:42:43,579 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:42:43,579 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:42:43,579 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [770335226] [2022-03-15 21:42:43,579 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:42:43,581 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:42:43,601 INFO L252 McrAutomatonBuilder]: Finished intersection with 142 states and 277 transitions. [2022-03-15 21:42:43,601 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:42:48,870 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [223398#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 223394#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 223389#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 223392#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (= (select queue (+ 2 front)) 1)) (or (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not (= (select queue back) 1)) v_assert (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 223387#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 223395#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 223391#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w))), 223401#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 223388#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 223390#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (+ (- 1) temp) 0) v_assert) (or v_assert (<= (+ 2 d temp) W)) (or (= (select queue front) 1) (< 0 w)) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ 2 d temp) W) (< 0 w))), 223385#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 223396#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ d 4) W))), 223393#(and (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W))), 223397#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 223386#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 223399#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= back (+ front 1)) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ front 1) back) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W))), 223400#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w))))] [2022-03-15 21:42:48,870 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-03-15 21:42:48,871 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:42:48,871 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-03-15 21:42:48,871 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=452, Invalid=4378, Unknown=0, NotChecked=0, Total=4830 [2022-03-15 21:42:48,871 INFO L87 Difference]: Start difference. First operand 1323 states and 3307 transitions. Second operand has 37 states, 37 states have (on average 3.4864864864864864) internal successors, (129), 36 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:53,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:42:53,207 INFO L93 Difference]: Finished difference Result 4465 states and 11107 transitions. [2022-03-15 21:42:53,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2022-03-15 21:42:53,207 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 3.4864864864864864) internal successors, (129), 36 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:42:53,208 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:42:53,214 INFO L225 Difference]: With dead ends: 4465 [2022-03-15 21:42:53,214 INFO L226 Difference]: Without dead ends: 4399 [2022-03-15 21:42:53,215 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 268 GetRequests, 103 SyntacticMatches, 23 SemanticMatches, 142 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6328 ImplicationChecksByTransitivity, 5.9s TimeCoverageRelationStatistics Valid=3128, Invalid=17464, Unknown=0, NotChecked=0, Total=20592 [2022-03-15 21:42:53,216 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 307 mSDsluCounter, 538 mSDsCounter, 0 mSdLazyCounter, 1832 mSolverCounterSat, 241 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 307 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2073 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 241 IncrementalHoareTripleChecker+Valid, 1832 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:42:53,216 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [307 Valid, 2 Invalid, 2073 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [241 Valid, 1832 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:42:53,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4399 states. [2022-03-15 21:42:53,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4399 to 1335. [2022-03-15 21:42:53,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1335 states, 1334 states have (on average 2.501499250374813) internal successors, (3337), 1334 states have internal predecessors, (3337), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:53,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1335 states to 1335 states and 3337 transitions. [2022-03-15 21:42:53,247 INFO L78 Accepts]: Start accepts. Automaton has 1335 states and 3337 transitions. Word has length 36 [2022-03-15 21:42:53,247 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:42:53,247 INFO L470 AbstractCegarLoop]: Abstraction has 1335 states and 3337 transitions. [2022-03-15 21:42:53,247 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 3.4864864864864864) internal successors, (129), 36 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:53,247 INFO L276 IsEmpty]: Start isEmpty. Operand 1335 states and 3337 transitions. [2022-03-15 21:42:53,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:42:53,249 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:42:53,249 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:42:53,265 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Forceful destruction successful, exit code 0 [2022-03-15 21:42:53,464 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable56,56 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:42:53,465 INFO L402 AbstractCegarLoop]: === Iteration 58 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:42:53,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:42:53,465 INFO L85 PathProgramCache]: Analyzing trace with hash 409178255, now seen corresponding path program 56 times [2022-03-15 21:42:53,466 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:42:53,466 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1375956061] [2022-03-15 21:42:53,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:42:53,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:42:53,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:42:53,942 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:53,942 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:42:53,942 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1375956061] [2022-03-15 21:42:53,943 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1375956061] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:42:53,943 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1886835365] [2022-03-15 21:42:53,943 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:42:53,943 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:42:53,943 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:42:53,944 INFO L229 MonitoredProcess]: Starting monitored process 57 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:42:53,944 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2022-03-15 21:42:53,981 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:42:53,981 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:42:53,982 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:42:53,983 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:42:54,802 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:42:54,802 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:42:54,878 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:54,878 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:42:55,700 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:42:55,700 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:43:00,726 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 3 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:43:00,726 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1886835365] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:43:00,726 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:43:00,726 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:43:00,727 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [341842913] [2022-03-15 21:43:00,727 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:43:00,736 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:43:00,758 INFO L252 McrAutomatonBuilder]: Finished intersection with 139 states and 271 transitions. [2022-03-15 21:43:00,758 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:43:05,566 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [230959#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ d 4) W))), 230950#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 230958#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 230955#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 230956#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 230961#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 230953#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (<= (+ 2 d) W) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 230964#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 230960#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= back (+ front 1)) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ front 1) back) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W))), 230952#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 230962#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 230949#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 230951#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 230954#(and (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1))), 230957#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 230963#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 230948#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w)))] [2022-03-15 21:43:05,566 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-03-15 21:43:05,566 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:43:05,566 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-03-15 21:43:05,567 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=447, Invalid=4383, Unknown=0, NotChecked=0, Total=4830 [2022-03-15 21:43:05,567 INFO L87 Difference]: Start difference. First operand 1335 states and 3337 transitions. Second operand has 37 states, 37 states have (on average 3.4324324324324325) internal successors, (127), 36 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:43:09,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:43:09,718 INFO L93 Difference]: Finished difference Result 4429 states and 10997 transitions. [2022-03-15 21:43:09,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2022-03-15 21:43:09,718 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 3.4324324324324325) internal successors, (127), 36 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:43:09,718 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:43:09,724 INFO L225 Difference]: With dead ends: 4429 [2022-03-15 21:43:09,724 INFO L226 Difference]: Without dead ends: 4356 [2022-03-15 21:43:09,740 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 260 GetRequests, 98 SyntacticMatches, 25 SemanticMatches, 137 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5902 ImplicationChecksByTransitivity, 5.9s TimeCoverageRelationStatistics Valid=2793, Invalid=16389, Unknown=0, NotChecked=0, Total=19182 [2022-03-15 21:43:09,740 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 319 mSDsluCounter, 549 mSDsCounter, 0 mSdLazyCounter, 1835 mSolverCounterSat, 234 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 319 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2069 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 234 IncrementalHoareTripleChecker+Valid, 1835 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:43:09,740 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [319 Valid, 2 Invalid, 2069 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [234 Valid, 1835 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:43:09,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4356 states. [2022-03-15 21:43:09,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4356 to 1347. [2022-03-15 21:43:09,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1347 states, 1346 states have (on average 2.50148588410104) internal successors, (3367), 1346 states have internal predecessors, (3367), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:43:09,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1347 states to 1347 states and 3367 transitions. [2022-03-15 21:43:09,786 INFO L78 Accepts]: Start accepts. Automaton has 1347 states and 3367 transitions. Word has length 36 [2022-03-15 21:43:09,786 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:43:09,786 INFO L470 AbstractCegarLoop]: Abstraction has 1347 states and 3367 transitions. [2022-03-15 21:43:09,786 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 3.4324324324324325) internal successors, (127), 36 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:43:09,786 INFO L276 IsEmpty]: Start isEmpty. Operand 1347 states and 3367 transitions. [2022-03-15 21:43:09,787 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:43:09,787 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:43:09,790 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:43:09,808 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Forceful destruction successful, exit code 0 [2022-03-15 21:43:10,004 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable57,57 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:43:10,004 INFO L402 AbstractCegarLoop]: === Iteration 59 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:43:10,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:43:10,004 INFO L85 PathProgramCache]: Analyzing trace with hash 168817437, now seen corresponding path program 57 times [2022-03-15 21:43:10,005 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:43:10,005 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430628832] [2022-03-15 21:43:10,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:43:10,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:43:10,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:43:10,344 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:43:10,344 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:43:10,344 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [430628832] [2022-03-15 21:43:10,344 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [430628832] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:43:10,344 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1043059792] [2022-03-15 21:43:10,344 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:43:10,344 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:43:10,344 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:43:10,345 INFO L229 MonitoredProcess]: Starting monitored process 58 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:43:10,346 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2022-03-15 21:43:10,374 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-03-15 21:43:10,374 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:43:10,375 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:43:10,375 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:43:11,214 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:43:11,215 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:43:11,311 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:43:11,311 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:43:12,217 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:43:12,217 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:43:17,349 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 3 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:43:17,349 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1043059792] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:43:17,349 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:43:17,349 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:43:17,349 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1129894756] [2022-03-15 21:43:17,349 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:43:17,351 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:43:17,369 INFO L252 McrAutomatonBuilder]: Finished intersection with 136 states and 265 transitions. [2022-03-15 21:43:17,369 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:43:22,886 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [238490#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 238489#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 238500#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 238503#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 238495#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 238494#(and (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)))), 238502#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= back (+ front 1)) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ front 1) back) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W))), 238498#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 238501#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ d 4) W))), 238505#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 238496#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 238491#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 238493#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not (= (select queue back) 1)) v_assert) (or (<= (+ d 1) W) (< 1 w) (not (= (select queue back) 1))) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1))), 238499#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d temp) W)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 238504#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 238492#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 238497#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W)))] [2022-03-15 21:43:22,886 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-03-15 21:43:22,886 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:43:22,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-03-15 21:43:22,887 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=439, Invalid=4391, Unknown=0, NotChecked=0, Total=4830 [2022-03-15 21:43:22,887 INFO L87 Difference]: Start difference. First operand 1347 states and 3367 transitions. Second operand has 37 states, 37 states have (on average 3.3783783783783785) internal successors, (125), 36 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:43:26,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:43:26,976 INFO L93 Difference]: Finished difference Result 4489 states and 11101 transitions. [2022-03-15 21:43:26,977 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2022-03-15 21:43:26,977 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 3.3783783783783785) internal successors, (125), 36 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:43:26,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:43:26,982 INFO L225 Difference]: With dead ends: 4489 [2022-03-15 21:43:26,983 INFO L226 Difference]: Without dead ends: 4436 [2022-03-15 21:43:26,983 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 256 GetRequests, 93 SyntacticMatches, 27 SemanticMatches, 136 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5770 ImplicationChecksByTransitivity, 6.0s TimeCoverageRelationStatistics Valid=2500, Invalid=16406, Unknown=0, NotChecked=0, Total=18906 [2022-03-15 21:43:26,984 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 338 mSDsluCounter, 473 mSDsCounter, 0 mSdLazyCounter, 1549 mSolverCounterSat, 267 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 338 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1816 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 267 IncrementalHoareTripleChecker+Valid, 1549 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-03-15 21:43:26,984 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [338 Valid, 2 Invalid, 1816 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [267 Valid, 1549 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-03-15 21:43:26,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4436 states. [2022-03-15 21:43:27,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4436 to 1359. [2022-03-15 21:43:27,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1359 states, 1358 states have (on average 2.4985272459499264) internal successors, (3393), 1358 states have internal predecessors, (3393), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:43:27,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1359 states to 1359 states and 3393 transitions. [2022-03-15 21:43:27,007 INFO L78 Accepts]: Start accepts. Automaton has 1359 states and 3393 transitions. Word has length 36 [2022-03-15 21:43:27,007 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:43:27,007 INFO L470 AbstractCegarLoop]: Abstraction has 1359 states and 3393 transitions. [2022-03-15 21:43:27,007 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 3.3783783783783785) internal successors, (125), 36 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:43:27,007 INFO L276 IsEmpty]: Start isEmpty. Operand 1359 states and 3393 transitions. [2022-03-15 21:43:27,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:43:27,008 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:43:27,008 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:43:27,027 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Ended with exit code 0 [2022-03-15 21:43:27,216 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 58 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable58 [2022-03-15 21:43:27,217 INFO L402 AbstractCegarLoop]: === Iteration 60 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:43:27,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:43:27,217 INFO L85 PathProgramCache]: Analyzing trace with hash -1170732753, now seen corresponding path program 58 times [2022-03-15 21:43:27,219 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:43:27,219 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1570652627] [2022-03-15 21:43:27,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:43:27,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:43:27,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:43:27,597 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:43:27,597 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:43:27,597 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1570652627] [2022-03-15 21:43:27,597 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1570652627] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:43:27,597 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1572794941] [2022-03-15 21:43:27,598 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:43:27,598 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:43:27,598 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:43:27,599 INFO L229 MonitoredProcess]: Starting monitored process 59 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:43:27,600 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2022-03-15 21:43:27,629 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:43:27,629 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:43:27,629 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:43:27,630 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:43:28,444 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:43:28,445 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:43:28,527 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:43:28,527 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:43:29,471 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:43:29,472 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:43:34,074 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 3 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:43:34,075 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1572794941] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:43:34,075 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:43:34,075 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:43:34,075 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [775386744] [2022-03-15 21:43:34,075 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:43:34,077 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:43:34,093 INFO L252 McrAutomatonBuilder]: Finished intersection with 123 states and 235 transitions. [2022-03-15 21:43:34,093 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:43:38,202 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 16 new interpolants: [246124#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 246112#(and (or (<= (+ d 1) W) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= back front))), 246113#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 246127#(and v_assert (< 0 w)), 246122#(and (or (not v_assert) (<= (+ d temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 246121#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 246115#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 246126#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 246119#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ d 4) W))), 246118#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 246117#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d temp) W)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 246116#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 246114#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 246120#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= back (+ front 1)) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ front 1) back) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W))), 246123#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 246125#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:43:38,203 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2022-03-15 21:43:38,203 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:43:38,203 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-03-15 21:43:38,203 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=381, Invalid=4311, Unknown=0, NotChecked=0, Total=4692 [2022-03-15 21:43:38,203 INFO L87 Difference]: Start difference. First operand 1359 states and 3393 transitions. Second operand has 36 states, 36 states have (on average 3.1944444444444446) internal successors, (115), 35 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:43:41,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:43:41,665 INFO L93 Difference]: Finished difference Result 3645 states and 9008 transitions. [2022-03-15 21:43:41,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2022-03-15 21:43:41,665 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 36 states have (on average 3.1944444444444446) internal successors, (115), 35 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:43:41,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:43:41,670 INFO L225 Difference]: With dead ends: 3645 [2022-03-15 21:43:41,670 INFO L226 Difference]: Without dead ends: 3628 [2022-03-15 21:43:41,671 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 236 GetRequests, 82 SyntacticMatches, 26 SemanticMatches, 128 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5194 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=1725, Invalid=15045, Unknown=0, NotChecked=0, Total=16770 [2022-03-15 21:43:41,671 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 309 mSDsluCounter, 540 mSDsCounter, 0 mSdLazyCounter, 1759 mSolverCounterSat, 234 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 309 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1993 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 234 IncrementalHoareTripleChecker+Valid, 1759 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:43:41,671 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [309 Valid, 2 Invalid, 1993 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [234 Valid, 1759 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:43:41,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3628 states. [2022-03-15 21:43:41,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3628 to 1347. [2022-03-15 21:43:41,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1347 states, 1346 states have (on average 2.50148588410104) internal successors, (3367), 1346 states have internal predecessors, (3367), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:43:41,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1347 states to 1347 states and 3367 transitions. [2022-03-15 21:43:41,690 INFO L78 Accepts]: Start accepts. Automaton has 1347 states and 3367 transitions. Word has length 36 [2022-03-15 21:43:41,690 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:43:41,690 INFO L470 AbstractCegarLoop]: Abstraction has 1347 states and 3367 transitions. [2022-03-15 21:43:41,690 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 36 states have (on average 3.1944444444444446) internal successors, (115), 35 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:43:41,690 INFO L276 IsEmpty]: Start isEmpty. Operand 1347 states and 3367 transitions. [2022-03-15 21:43:41,692 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:43:41,692 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:43:41,692 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:43:41,707 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Forceful destruction successful, exit code 0 [2022-03-15 21:43:41,895 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 59 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable59 [2022-03-15 21:43:41,895 INFO L402 AbstractCegarLoop]: === Iteration 61 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:43:41,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:43:41,895 INFO L85 PathProgramCache]: Analyzing trace with hash -1183974057, now seen corresponding path program 59 times [2022-03-15 21:43:41,896 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:43:41,896 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248394974] [2022-03-15 21:43:41,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:43:41,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:43:41,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:43:42,263 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:43:42,263 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:43:42,263 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248394974] [2022-03-15 21:43:42,264 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1248394974] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:43:42,264 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1171330064] [2022-03-15 21:43:42,264 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:43:42,264 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:43:42,264 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:43:42,279 INFO L229 MonitoredProcess]: Starting monitored process 60 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:43:42,280 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2022-03-15 21:43:42,309 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2022-03-15 21:43:42,310 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:43:42,310 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 41 conjunts are in the unsatisfiable core [2022-03-15 21:43:42,311 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:43:46,193 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,194 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,195 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,195 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,196 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,196 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,197 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:46,198 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,198 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:46,199 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,199 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,200 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,200 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,201 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,202 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,203 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:46,204 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,205 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,205 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,206 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:46,206 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:46,210 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 9 select indices, 9 select index equivalence classes, 10 disjoint index pairs (out of 36 index pairs), introduced 5 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 26 [2022-03-15 21:43:46,301 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:43:46,302 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:43:47,408 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,409 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,409 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,411 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,411 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,413 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,413 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,414 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,416 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,417 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,418 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,418 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,420 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,421 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,421 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,421 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,422 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,423 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,423 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,423 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,424 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,426 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,427 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,427 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,428 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,428 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:47,512 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:43:47,513 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 26 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 19 case distinctions, treesize of input 60 treesize of output 214 [2022-03-15 21:43:50,467 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:43:50,467 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1171330064] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:43:50,467 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:43:50,467 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:43:50,468 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [527056131] [2022-03-15 21:43:50,468 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:43:50,469 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:43:50,516 INFO L252 McrAutomatonBuilder]: Finished intersection with 117 states and 220 transitions. [2022-03-15 21:43:50,516 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:43:54,818 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 14 new interpolants: [252862#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 252857#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (< 1 w)) (not (= (select queue back) 1)))), 252854#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 252853#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 252852#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)))), 252861#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 252863#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 252864#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 252855#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 252858#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= back (+ front 1)) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ front 1) back) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)))), 252859#(and (or (not v_assert) (<= (+ 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 252865#(and v_assert (< 0 w)), 252860#(and (or (not v_assert) (<= (+ 2 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 252856#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))))] [2022-03-15 21:43:54,819 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 34 states [2022-03-15 21:43:54,819 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:43:54,819 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2022-03-15 21:43:54,819 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=477, Invalid=3945, Unknown=0, NotChecked=0, Total=4422 [2022-03-15 21:43:54,819 INFO L87 Difference]: Start difference. First operand 1347 states and 3367 transitions. Second operand has 34 states, 34 states have (on average 3.176470588235294) internal successors, (108), 33 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:43:57,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:43:57,622 INFO L93 Difference]: Finished difference Result 3102 states and 7687 transitions. [2022-03-15 21:43:57,622 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2022-03-15 21:43:57,623 INFO L78 Accepts]: Start accepts. Automaton has has 34 states, 34 states have (on average 3.176470588235294) internal successors, (108), 33 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:43:57,623 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:43:57,626 INFO L225 Difference]: With dead ends: 3102 [2022-03-15 21:43:57,626 INFO L226 Difference]: Without dead ends: 3085 [2022-03-15 21:43:57,627 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 224 GetRequests, 84 SyntacticMatches, 20 SemanticMatches, 120 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3727 ImplicationChecksByTransitivity, 8.1s TimeCoverageRelationStatistics Valid=1908, Invalid=12854, Unknown=0, NotChecked=0, Total=14762 [2022-03-15 21:43:57,627 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 285 mSDsluCounter, 476 mSDsCounter, 0 mSdLazyCounter, 1518 mSolverCounterSat, 208 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 285 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1726 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 208 IncrementalHoareTripleChecker+Valid, 1518 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-03-15 21:43:57,627 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [285 Valid, 2 Invalid, 1726 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [208 Valid, 1518 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-03-15 21:43:57,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3085 states. [2022-03-15 21:43:57,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3085 to 1335. [2022-03-15 21:43:57,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1335 states, 1334 states have (on average 2.501499250374813) internal successors, (3337), 1334 states have internal predecessors, (3337), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:43:57,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1335 states to 1335 states and 3337 transitions. [2022-03-15 21:43:57,644 INFO L78 Accepts]: Start accepts. Automaton has 1335 states and 3337 transitions. Word has length 36 [2022-03-15 21:43:57,645 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:43:57,645 INFO L470 AbstractCegarLoop]: Abstraction has 1335 states and 3337 transitions. [2022-03-15 21:43:57,645 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 34 states, 34 states have (on average 3.176470588235294) internal successors, (108), 33 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:43:57,645 INFO L276 IsEmpty]: Start isEmpty. Operand 1335 states and 3337 transitions. [2022-03-15 21:43:57,646 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:43:57,646 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:43:57,646 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:43:57,664 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Ended with exit code 0 [2022-03-15 21:43:57,859 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable60,60 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:43:57,859 INFO L402 AbstractCegarLoop]: === Iteration 62 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:43:57,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:43:57,860 INFO L85 PathProgramCache]: Analyzing trace with hash -518670289, now seen corresponding path program 60 times [2022-03-15 21:43:57,860 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:43:57,860 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373860098] [2022-03-15 21:43:57,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:43:57,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:43:57,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:43:58,125 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:43:58,125 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:43:58,125 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [373860098] [2022-03-15 21:43:58,125 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [373860098] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:43:58,125 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1338045229] [2022-03-15 21:43:58,125 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:43:58,125 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:43:58,125 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:43:58,126 INFO L229 MonitoredProcess]: Starting monitored process 61 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:43:58,128 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2022-03-15 21:43:58,153 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2022-03-15 21:43:58,153 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:43:58,154 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:43:58,155 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:43:58,812 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:43:58,812 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:43:58,868 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:43:58,868 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:43:59,540 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:43:59,541 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:44:03,016 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 3 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:44:03,017 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1338045229] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:44:03,017 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:44:03,017 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:44:03,017 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [551126189] [2022-03-15 21:44:03,017 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:44:03,019 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:44:03,034 INFO L252 McrAutomatonBuilder]: Finished intersection with 111 states and 205 transitions. [2022-03-15 21:44:03,034 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:44:06,985 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 12 new interpolants: [259013#(and (or (not v_assert) (<= (+ 3 d temp) W)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 259018#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= back (+ front 1)) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ front 1) back) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)))), 259012#(and (or (not v_assert) (<= (+ 3 d) W)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 259020#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 259021#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 259011#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 259019#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 259015#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 259014#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 259017#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (< 1 w)) (not (= (select queue back) 1)))), 259016#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 259022#(and v_assert (< 0 w))] [2022-03-15 21:44:06,985 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 32 states [2022-03-15 21:44:06,986 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:44:06,986 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-03-15 21:44:06,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=355, Invalid=3805, Unknown=0, NotChecked=0, Total=4160 [2022-03-15 21:44:06,986 INFO L87 Difference]: Start difference. First operand 1335 states and 3337 transitions. Second operand has 32 states, 32 states have (on average 3.15625) internal successors, (101), 31 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:44:09,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:44:09,823 INFO L93 Difference]: Finished difference Result 2874 states and 7127 transitions. [2022-03-15 21:44:09,823 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2022-03-15 21:44:09,823 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 32 states have (on average 3.15625) internal successors, (101), 31 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:44:09,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:44:09,827 INFO L225 Difference]: With dead ends: 2874 [2022-03-15 21:44:09,827 INFO L226 Difference]: Without dead ends: 2857 [2022-03-15 21:44:09,828 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 218 GetRequests, 81 SyntacticMatches, 19 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3942 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=1717, Invalid=12563, Unknown=0, NotChecked=0, Total=14280 [2022-03-15 21:44:09,828 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 284 mSDsluCounter, 467 mSDsCounter, 0 mSdLazyCounter, 1496 mSolverCounterSat, 186 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 284 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1682 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 186 IncrementalHoareTripleChecker+Valid, 1496 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-03-15 21:44:09,828 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [284 Valid, 2 Invalid, 1682 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [186 Valid, 1496 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-03-15 21:44:09,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2857 states. [2022-03-15 21:44:09,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2857 to 1323. [2022-03-15 21:44:09,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1323 states, 1322 states have (on average 2.5015128593040847) internal successors, (3307), 1322 states have internal predecessors, (3307), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:44:09,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1323 states to 1323 states and 3307 transitions. [2022-03-15 21:44:09,846 INFO L78 Accepts]: Start accepts. Automaton has 1323 states and 3307 transitions. Word has length 36 [2022-03-15 21:44:09,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:44:09,846 INFO L470 AbstractCegarLoop]: Abstraction has 1323 states and 3307 transitions. [2022-03-15 21:44:09,846 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 32 states, 32 states have (on average 3.15625) internal successors, (101), 31 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:44:09,846 INFO L276 IsEmpty]: Start isEmpty. Operand 1323 states and 3307 transitions. [2022-03-15 21:44:09,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:44:09,848 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:44:09,848 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:44:09,863 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Ended with exit code 0 [2022-03-15 21:44:10,064 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable61,61 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:44:10,064 INFO L402 AbstractCegarLoop]: === Iteration 63 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:44:10,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:44:10,064 INFO L85 PathProgramCache]: Analyzing trace with hash -1728188841, now seen corresponding path program 61 times [2022-03-15 21:44:10,073 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:44:10,073 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749200379] [2022-03-15 21:44:10,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:44:10,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:44:10,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:44:10,417 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:44:10,418 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:44:10,418 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [749200379] [2022-03-15 21:44:10,418 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [749200379] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:44:10,418 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [91990683] [2022-03-15 21:44:10,418 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-03-15 21:44:10,418 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:44:10,418 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:44:10,419 INFO L229 MonitoredProcess]: Starting monitored process 62 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:44:10,420 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2022-03-15 21:44:10,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:44:10,444 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:44:10,445 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:44:11,215 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:44:11,215 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:44:11,292 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:44:11,292 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:44:12,152 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:44:12,153 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:44:16,629 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 3 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:44:16,629 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [91990683] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:44:16,629 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:44:16,629 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:44:16,630 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1497872413] [2022-03-15 21:44:16,630 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:44:16,631 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:44:16,646 INFO L252 McrAutomatonBuilder]: Finished intersection with 105 states and 190 transitions. [2022-03-15 21:44:16,646 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:44:19,413 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 10 new interpolants: [264917#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 264923#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 264919#(and (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (= (select queue front) 1) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= back (+ front 1)) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ front 1) back) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (= (select queue back) 1)) (not (< 2 w)) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W))), 264925#(and v_assert (< 0 w)), 264922#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 264924#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 264920#(and (or (not v_assert) (= (select queue (+ 3 front)) 1)) (or (not v_assert) (<= (+ d 4) W)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 264918#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ d 4) W))), 264921#(and (or (not v_assert) (<= (+ d temp 4) W)) (or (not v_assert) (= (select queue (+ 3 front)) 1)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 264916#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:44:19,414 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 30 states [2022-03-15 21:44:19,414 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:44:19,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2022-03-15 21:44:19,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=338, Invalid=3568, Unknown=0, NotChecked=0, Total=3906 [2022-03-15 21:44:19,414 INFO L87 Difference]: Start difference. First operand 1323 states and 3307 transitions. Second operand has 30 states, 30 states have (on average 3.1333333333333333) internal successors, (94), 29 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:44:22,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:44:22,361 INFO L93 Difference]: Finished difference Result 2852 states and 7075 transitions. [2022-03-15 21:44:22,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2022-03-15 21:44:22,362 INFO L78 Accepts]: Start accepts. Automaton has has 30 states, 30 states have (on average 3.1333333333333333) internal successors, (94), 29 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:44:22,362 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:44:22,365 INFO L225 Difference]: With dead ends: 2852 [2022-03-15 21:44:22,365 INFO L226 Difference]: Without dead ends: 2835 [2022-03-15 21:44:22,366 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 216 GetRequests, 79 SyntacticMatches, 17 SemanticMatches, 120 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3840 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=1823, Invalid=12939, Unknown=0, NotChecked=0, Total=14762 [2022-03-15 21:44:22,367 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 255 mSDsluCounter, 535 mSDsCounter, 0 mSdLazyCounter, 1723 mSolverCounterSat, 176 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 255 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1899 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 176 IncrementalHoareTripleChecker+Valid, 1723 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-03-15 21:44:22,367 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [255 Valid, 2 Invalid, 1899 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [176 Valid, 1723 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-03-15 21:44:22,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2835 states. [2022-03-15 21:44:22,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2835 to 1235. [2022-03-15 21:44:22,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1235 states, 1234 states have (on average 2.4708265802269045) internal successors, (3049), 1234 states have internal predecessors, (3049), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:44:22,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1235 states to 1235 states and 3049 transitions. [2022-03-15 21:44:22,382 INFO L78 Accepts]: Start accepts. Automaton has 1235 states and 3049 transitions. Word has length 36 [2022-03-15 21:44:22,382 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:44:22,382 INFO L470 AbstractCegarLoop]: Abstraction has 1235 states and 3049 transitions. [2022-03-15 21:44:22,382 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 30 states, 30 states have (on average 3.1333333333333333) internal successors, (94), 29 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:44:22,383 INFO L276 IsEmpty]: Start isEmpty. Operand 1235 states and 3049 transitions. [2022-03-15 21:44:22,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:44:22,384 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:44:22,384 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:44:22,399 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Forceful destruction successful, exit code 0 [2022-03-15 21:44:22,592 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable62,62 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:44:22,593 INFO L402 AbstractCegarLoop]: === Iteration 64 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:44:22,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:44:22,593 INFO L85 PathProgramCache]: Analyzing trace with hash -218360639, now seen corresponding path program 62 times [2022-03-15 21:44:22,594 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:44:22,594 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [5648942] [2022-03-15 21:44:22,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:44:22,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:44:22,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:44:22,937 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:44:22,938 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:44:22,938 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [5648942] [2022-03-15 21:44:22,938 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [5648942] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:44:22,938 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [559301040] [2022-03-15 21:44:22,938 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:44:22,938 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:44:22,938 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:44:22,939 INFO L229 MonitoredProcess]: Starting monitored process 63 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:44:22,940 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2022-03-15 21:44:22,966 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:44:22,966 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:44:22,967 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:44:22,968 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:44:23,856 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:44:23,856 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:44:23,950 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:44:23,950 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:44:24,762 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:44:24,762 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:44:29,955 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:44:29,955 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [559301040] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:44:29,955 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:44:29,955 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:44:29,956 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1783152214] [2022-03-15 21:44:29,956 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:44:29,957 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:44:29,976 INFO L252 McrAutomatonBuilder]: Finished intersection with 143 states and 277 transitions. [2022-03-15 21:44:29,977 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:44:35,769 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [270632#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 270635#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w))), 270642#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 270629#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 270631#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 270637#(and (or v_assert (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (< 0 w) (<= (+ d 4) W)) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ 3 front)) 1) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (= (select queue (+ 3 front)) 1) (< 0 w))), 270644#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 270633#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 270630#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 270634#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (+ (- 1) temp) 0) v_assert) (or v_assert (<= (+ 2 d temp) W)) (or (= (select queue front) 1) (< 0 w)) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ 2 d temp) W) (< 0 w))), 270639#(and (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (not (< 0 w)) (= (select queue (+ 3 front)) 1) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (<= (+ d 4) W))), 270645#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 270636#(and (or v_assert (<= (+ d 4) W)) (or (= temp 1) (< 0 w)) (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (< 0 w) (<= (+ d 4) W)) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (= (select queue front) 1) (< 0 w)) (or v_assert (= temp 1))), 270638#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ 3 front)) 1) (not (= (select queue back) 1)) v_assert) (or (= (select queue (+ 3 front)) 1) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (< 1 w) (not (= (select queue back) 1)) (<= (+ d 4) W)) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (<= (+ d 4) W)) (or (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 270643#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 270640#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (= (select queue (+ 3 front)) 1) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)) (<= (+ d 4) W))), 270641#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w))))] [2022-03-15 21:44:35,769 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-03-15 21:44:35,769 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:44:35,770 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-03-15 21:44:35,770 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=468, Invalid=4362, Unknown=0, NotChecked=0, Total=4830 [2022-03-15 21:44:35,770 INFO L87 Difference]: Start difference. First operand 1235 states and 3049 transitions. Second operand has 37 states, 37 states have (on average 3.5405405405405403) internal successors, (131), 36 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:44:42,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:44:42,739 INFO L93 Difference]: Finished difference Result 7001 states and 17734 transitions. [2022-03-15 21:44:42,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 97 states. [2022-03-15 21:44:42,740 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 3.5405405405405403) internal successors, (131), 36 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:44:42,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:44:42,749 INFO L225 Difference]: With dead ends: 7001 [2022-03-15 21:44:42,749 INFO L226 Difference]: Without dead ends: 6566 [2022-03-15 21:44:42,750 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 289 GetRequests, 110 SyntacticMatches, 17 SemanticMatches, 162 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8015 ImplicationChecksByTransitivity, 7.8s TimeCoverageRelationStatistics Valid=4347, Invalid=22385, Unknown=0, NotChecked=0, Total=26732 [2022-03-15 21:44:42,750 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 352 mSDsluCounter, 752 mSDsCounter, 0 mSdLazyCounter, 3187 mSolverCounterSat, 287 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 352 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 3474 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 287 IncrementalHoareTripleChecker+Valid, 3187 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.4s IncrementalHoareTripleChecker+Time [2022-03-15 21:44:42,750 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [352 Valid, 2 Invalid, 3474 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [287 Valid, 3187 Invalid, 0 Unknown, 0 Unchecked, 1.4s Time] [2022-03-15 21:44:42,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6566 states. [2022-03-15 21:44:42,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6566 to 1387. [2022-03-15 21:44:42,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1387 states, 1386 states have (on average 2.528860028860029) internal successors, (3505), 1386 states have internal predecessors, (3505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:44:42,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1387 states to 1387 states and 3505 transitions. [2022-03-15 21:44:42,784 INFO L78 Accepts]: Start accepts. Automaton has 1387 states and 3505 transitions. Word has length 36 [2022-03-15 21:44:42,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:44:42,784 INFO L470 AbstractCegarLoop]: Abstraction has 1387 states and 3505 transitions. [2022-03-15 21:44:42,784 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 3.5405405405405403) internal successors, (131), 36 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:44:42,784 INFO L276 IsEmpty]: Start isEmpty. Operand 1387 states and 3505 transitions. [2022-03-15 21:44:42,786 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:44:42,786 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:44:42,786 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:44:42,807 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Forceful destruction successful, exit code 0 [2022-03-15 21:44:43,009 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable63,63 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:44:43,009 INFO L402 AbstractCegarLoop]: === Iteration 65 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:44:43,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:44:43,010 INFO L85 PathProgramCache]: Analyzing trace with hash 967622529, now seen corresponding path program 63 times [2022-03-15 21:44:43,010 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:44:43,010 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621469698] [2022-03-15 21:44:43,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:44:43,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:44:43,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:44:43,310 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:44:43,310 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:44:43,310 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1621469698] [2022-03-15 21:44:43,310 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1621469698] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:44:43,310 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [731298180] [2022-03-15 21:44:43,311 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:44:43,314 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:44:43,314 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:44:43,315 INFO L229 MonitoredProcess]: Starting monitored process 64 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:44:43,316 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2022-03-15 21:44:43,350 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-03-15 21:44:43,351 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:44:43,351 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:44:43,352 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:44:44,079 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:44:44,080 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:44:44,141 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:44:44,141 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:44:44,788 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:44:44,788 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:44:48,143 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 4 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:44:48,144 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [731298180] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:44:48,144 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:44:48,144 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:44:48,144 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1302786355] [2022-03-15 21:44:48,144 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:44:48,164 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:44:48,195 INFO L252 McrAutomatonBuilder]: Finished intersection with 137 states and 265 transitions. [2022-03-15 21:44:48,195 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:44:53,341 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [280888#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 280880#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 280883#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ d 4) W))), 280872#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 280877#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (<= (+ 2 d) W) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 280882#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 280879#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 280874#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 280873#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 280884#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 280885#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 280875#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 280876#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 280887#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 280886#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 280881#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 280878#(and (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)))] [2022-03-15 21:44:53,342 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-03-15 21:44:53,342 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:44:53,342 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-03-15 21:44:53,342 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=447, Invalid=4383, Unknown=0, NotChecked=0, Total=4830 [2022-03-15 21:44:53,342 INFO L87 Difference]: Start difference. First operand 1387 states and 3505 transitions. Second operand has 37 states, 37 states have (on average 3.4324324324324325) internal successors, (127), 36 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:44:57,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:44:57,934 INFO L93 Difference]: Finished difference Result 4715 states and 11743 transitions. [2022-03-15 21:44:57,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2022-03-15 21:44:57,935 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 3.4324324324324325) internal successors, (127), 36 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:44:57,935 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:44:57,952 INFO L225 Difference]: With dead ends: 4715 [2022-03-15 21:44:57,952 INFO L226 Difference]: Without dead ends: 4648 [2022-03-15 21:44:57,953 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 254 GetRequests, 101 SyntacticMatches, 20 SemanticMatches, 133 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5201 ImplicationChecksByTransitivity, 6.1s TimeCoverageRelationStatistics Valid=2665, Invalid=15425, Unknown=0, NotChecked=0, Total=18090 [2022-03-15 21:44:57,953 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 324 mSDsluCounter, 541 mSDsCounter, 0 mSdLazyCounter, 1877 mSolverCounterSat, 231 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 324 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2108 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 231 IncrementalHoareTripleChecker+Valid, 1877 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-03-15 21:44:57,953 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [324 Valid, 2 Invalid, 2108 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [231 Valid, 1877 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-03-15 21:44:57,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4648 states. [2022-03-15 21:44:57,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4648 to 1407. [2022-03-15 21:44:57,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1407 states, 1406 states have (on average 2.52773826458037) internal successors, (3554), 1406 states have internal predecessors, (3554), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:44:57,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1407 states to 1407 states and 3554 transitions. [2022-03-15 21:44:57,980 INFO L78 Accepts]: Start accepts. Automaton has 1407 states and 3554 transitions. Word has length 36 [2022-03-15 21:44:57,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:44:57,980 INFO L470 AbstractCegarLoop]: Abstraction has 1407 states and 3554 transitions. [2022-03-15 21:44:57,980 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 3.4324324324324325) internal successors, (127), 36 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:44:57,980 INFO L276 IsEmpty]: Start isEmpty. Operand 1407 states and 3554 transitions. [2022-03-15 21:44:57,984 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:44:57,984 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:44:57,984 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:44:58,001 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Ended with exit code 0 [2022-03-15 21:44:58,190 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 64 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable64 [2022-03-15 21:44:58,190 INFO L402 AbstractCegarLoop]: === Iteration 66 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:44:58,191 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:44:58,191 INFO L85 PathProgramCache]: Analyzing trace with hash 727261711, now seen corresponding path program 64 times [2022-03-15 21:44:58,192 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:44:58,192 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1279325492] [2022-03-15 21:44:58,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:44:58,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:44:58,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:44:58,575 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:44:58,575 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:44:58,575 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1279325492] [2022-03-15 21:44:58,576 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1279325492] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:44:58,576 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1998942950] [2022-03-15 21:44:58,576 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:44:58,576 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:44:58,576 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:44:58,577 INFO L229 MonitoredProcess]: Starting monitored process 65 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:44:58,578 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2022-03-15 21:44:58,610 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:44:58,610 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:44:58,611 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:44:58,612 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:44:59,452 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:44:59,452 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:44:59,528 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:44:59,528 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:45:00,231 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:45:00,232 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:45:06,128 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 4 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:06,128 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1998942950] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:45:06,129 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:45:06,129 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:45:06,129 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [279241266] [2022-03-15 21:45:06,129 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:45:06,130 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:45:06,149 INFO L252 McrAutomatonBuilder]: Finished intersection with 134 states and 259 transitions. [2022-03-15 21:45:06,149 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:45:10,582 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [288815#(and (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)))), 288813#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 288823#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 288827#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 288812#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 288816#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 288826#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 288822#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ d 4) W))), 288824#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 288814#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not (= (select queue back) 1)) v_assert) (or (<= (+ d 1) W) (< 1 w) (not (= (select queue back) 1))) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1))), 288825#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 288817#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 288819#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 288818#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 288811#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 288821#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 288820#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d temp) W)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))))] [2022-03-15 21:45:10,583 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-03-15 21:45:10,583 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:45:10,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-03-15 21:45:10,583 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=437, Invalid=4393, Unknown=0, NotChecked=0, Total=4830 [2022-03-15 21:45:10,583 INFO L87 Difference]: Start difference. First operand 1407 states and 3554 transitions. Second operand has 37 states, 37 states have (on average 3.3783783783783785) internal successors, (125), 36 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:45:13,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:45:13,626 INFO L93 Difference]: Finished difference Result 4441 states and 11023 transitions. [2022-03-15 21:45:13,627 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2022-03-15 21:45:13,627 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 3.3783783783783785) internal successors, (125), 36 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:45:13,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:45:13,633 INFO L225 Difference]: With dead ends: 4441 [2022-03-15 21:45:13,633 INFO L226 Difference]: Without dead ends: 4388 [2022-03-15 21:45:13,634 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 248 GetRequests, 96 SyntacticMatches, 22 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5170 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=2241, Invalid=15051, Unknown=0, NotChecked=0, Total=17292 [2022-03-15 21:45:13,639 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 304 mSDsluCounter, 551 mSDsCounter, 0 mSdLazyCounter, 1783 mSolverCounterSat, 233 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 304 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2016 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 233 IncrementalHoareTripleChecker+Valid, 1783 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-03-15 21:45:13,639 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [304 Valid, 2 Invalid, 2016 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [233 Valid, 1783 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-03-15 21:45:13,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4388 states. [2022-03-15 21:45:13,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4388 to 1419. [2022-03-15 21:45:13,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1419 states, 1418 states have (on average 2.524682651622003) internal successors, (3580), 1418 states have internal predecessors, (3580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:45:13,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1419 states to 1419 states and 3580 transitions. [2022-03-15 21:45:13,669 INFO L78 Accepts]: Start accepts. Automaton has 1419 states and 3580 transitions. Word has length 36 [2022-03-15 21:45:13,669 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:45:13,669 INFO L470 AbstractCegarLoop]: Abstraction has 1419 states and 3580 transitions. [2022-03-15 21:45:13,669 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 3.3783783783783785) internal successors, (125), 36 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:45:13,669 INFO L276 IsEmpty]: Start isEmpty. Operand 1419 states and 3580 transitions. [2022-03-15 21:45:13,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:45:13,671 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:45:13,671 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:45:13,689 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Forceful destruction successful, exit code 0 [2022-03-15 21:45:13,887 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable65,65 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:45:13,887 INFO L402 AbstractCegarLoop]: === Iteration 67 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:45:13,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:45:13,887 INFO L85 PathProgramCache]: Analyzing trace with hash -612288479, now seen corresponding path program 65 times [2022-03-15 21:45:13,888 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:45:13,888 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [644217723] [2022-03-15 21:45:13,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:45:13,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:45:13,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:45:14,153 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:14,153 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:45:14,153 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [644217723] [2022-03-15 21:45:14,153 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [644217723] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:45:14,153 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [495619904] [2022-03-15 21:45:14,153 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:45:14,154 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:45:14,154 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:45:14,154 INFO L229 MonitoredProcess]: Starting monitored process 66 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:45:14,155 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2022-03-15 21:45:14,184 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2022-03-15 21:45:14,184 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:45:14,185 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:45:14,186 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:45:14,907 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,908 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:14,908 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,909 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,910 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,910 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,910 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,911 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,911 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,912 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:14,912 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,913 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,913 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,914 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,914 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,915 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,915 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,928 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:14,928 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,929 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,929 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,930 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,930 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:14,931 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:45:14,931 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:14,932 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 10 disjoint index pairs (out of 45 index pairs), introduced 5 new quantified variables, introduced 0 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:45:15,001 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:15,001 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:45:15,711 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,711 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,712 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,712 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,714 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,714 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,715 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,715 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,715 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,716 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,716 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,717 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,717 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,718 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,719 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,719 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,719 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,720 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,720 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,721 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,721 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,721 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,722 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,722 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,723 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,725 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,726 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,727 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,727 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,727 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:15,783 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:45:15,783 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 30 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 15 case distinctions, treesize of input 66 treesize of output 198 [2022-03-15 21:45:16,381 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:16,381 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [495619904] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:45:16,381 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:45:16,381 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:45:16,381 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [876033390] [2022-03-15 21:45:16,382 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:45:16,383 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:45:16,401 INFO L252 McrAutomatonBuilder]: Finished intersection with 121 states and 229 transitions. [2022-03-15 21:45:16,402 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:45:21,047 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 16 new interpolants: [296495#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 296502#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 296500#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 296508#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 296507#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 296503#(and (or (not v_assert) (<= (+ d temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 296499#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d temp) W)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 296504#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 296494#(and (or (<= (+ d 1) W) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= back front))), 296506#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 296496#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 296497#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 296501#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ d 4) W))), 296509#(and v_assert (< 0 w)), 296498#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 296505#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:45:21,047 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2022-03-15 21:45:21,047 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:45:21,047 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-03-15 21:45:21,047 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=488, Invalid=4204, Unknown=0, NotChecked=0, Total=4692 [2022-03-15 21:45:21,047 INFO L87 Difference]: Start difference. First operand 1419 states and 3580 transitions. Second operand has 36 states, 36 states have (on average 3.1944444444444446) internal successors, (115), 35 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:45:23,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:45:23,973 INFO L93 Difference]: Finished difference Result 3543 states and 8791 transitions. [2022-03-15 21:45:23,973 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2022-03-15 21:45:23,973 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 36 states have (on average 3.1944444444444446) internal successors, (115), 35 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:45:23,973 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:45:23,978 INFO L225 Difference]: With dead ends: 3543 [2022-03-15 21:45:23,978 INFO L226 Difference]: Without dead ends: 3526 [2022-03-15 21:45:23,980 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 227 GetRequests, 85 SyntacticMatches, 21 SemanticMatches, 121 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4268 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=1840, Invalid=13166, Unknown=0, NotChecked=0, Total=15006 [2022-03-15 21:45:23,980 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 312 mSDsluCounter, 621 mSDsCounter, 0 mSdLazyCounter, 1945 mSolverCounterSat, 214 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 312 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2159 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 214 IncrementalHoareTripleChecker+Valid, 1945 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:45:23,980 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [312 Valid, 2 Invalid, 2159 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [214 Valid, 1945 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:45:23,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3526 states. [2022-03-15 21:45:24,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3526 to 1407. [2022-03-15 21:45:24,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1407 states, 1406 states have (on average 2.52773826458037) internal successors, (3554), 1406 states have internal predecessors, (3554), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:45:24,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1407 states to 1407 states and 3554 transitions. [2022-03-15 21:45:24,019 INFO L78 Accepts]: Start accepts. Automaton has 1407 states and 3554 transitions. Word has length 36 [2022-03-15 21:45:24,019 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:45:24,019 INFO L470 AbstractCegarLoop]: Abstraction has 1407 states and 3554 transitions. [2022-03-15 21:45:24,019 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 36 states have (on average 3.1944444444444446) internal successors, (115), 35 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:45:24,020 INFO L276 IsEmpty]: Start isEmpty. Operand 1407 states and 3554 transitions. [2022-03-15 21:45:24,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:45:24,021 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:45:24,021 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:45:24,039 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Forceful destruction successful, exit code 0 [2022-03-15 21:45:24,239 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 66 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable66 [2022-03-15 21:45:24,239 INFO L402 AbstractCegarLoop]: === Iteration 68 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:45:24,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:45:24,240 INFO L85 PathProgramCache]: Analyzing trace with hash -625529783, now seen corresponding path program 66 times [2022-03-15 21:45:24,247 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:45:24,247 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436603898] [2022-03-15 21:45:24,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:45:24,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:45:24,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:45:24,525 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:24,525 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:45:24,525 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1436603898] [2022-03-15 21:45:24,525 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1436603898] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:45:24,525 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [439402066] [2022-03-15 21:45:24,525 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:45:24,525 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:45:24,525 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:45:24,526 INFO L229 MonitoredProcess]: Starting monitored process 67 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:45:24,527 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2022-03-15 21:45:24,553 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2022-03-15 21:45:24,554 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:45:24,554 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:45:24,555 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:45:25,178 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:45:25,178 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:45:25,233 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:25,233 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:45:25,998 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:45:25,999 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:45:29,321 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 4 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:29,322 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [439402066] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:45:29,322 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:45:29,322 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:45:29,322 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [17168784] [2022-03-15 21:45:29,322 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:45:29,324 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:45:29,339 INFO L252 McrAutomatonBuilder]: Finished intersection with 115 states and 214 transitions. [2022-03-15 21:45:29,340 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:45:32,836 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 14 new interpolants: [303245#(and (or (not v_assert) (<= (+ 2 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 303240#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 303247#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 303242#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 303248#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 303250#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 303241#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 303243#(and (or (not v_assert) (<= back (+ 2 front)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (<= (+ (select queue front) 3 d) W) (not (< 1 w)) (not (= (select queue back) 1)))), 303249#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 303251#(and v_assert (< 0 w)), 303239#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 303244#(and (or (not v_assert) (<= (+ 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 303246#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 303238#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))))] [2022-03-15 21:45:32,836 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 34 states [2022-03-15 21:45:32,836 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:45:32,836 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2022-03-15 21:45:32,837 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=366, Invalid=4056, Unknown=0, NotChecked=0, Total=4422 [2022-03-15 21:45:32,837 INFO L87 Difference]: Start difference. First operand 1407 states and 3554 transitions. Second operand has 34 states, 34 states have (on average 3.176470588235294) internal successors, (108), 33 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:45:35,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:45:35,700 INFO L93 Difference]: Finished difference Result 3227 states and 8036 transitions. [2022-03-15 21:45:35,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2022-03-15 21:45:35,700 INFO L78 Accepts]: Start accepts. Automaton has has 34 states, 34 states have (on average 3.176470588235294) internal successors, (108), 33 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:45:35,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:45:35,704 INFO L225 Difference]: With dead ends: 3227 [2022-03-15 21:45:35,704 INFO L226 Difference]: Without dead ends: 3210 [2022-03-15 21:45:35,706 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 218 GetRequests, 88 SyntacticMatches, 14 SemanticMatches, 116 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3658 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=1589, Invalid=12217, Unknown=0, NotChecked=0, Total=13806 [2022-03-15 21:45:35,706 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 249 mSDsluCounter, 495 mSDsCounter, 0 mSdLazyCounter, 1614 mSolverCounterSat, 160 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 249 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 1774 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 160 IncrementalHoareTripleChecker+Valid, 1614 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-03-15 21:45:35,706 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [249 Valid, 2 Invalid, 1774 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [160 Valid, 1614 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-03-15 21:45:35,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3210 states. [2022-03-15 21:45:35,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3210 to 1361. [2022-03-15 21:45:35,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1360 states have (on average 2.527941176470588) internal successors, (3438), 1360 states have internal predecessors, (3438), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:45:35,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 3438 transitions. [2022-03-15 21:45:35,729 INFO L78 Accepts]: Start accepts. Automaton has 1361 states and 3438 transitions. Word has length 36 [2022-03-15 21:45:35,729 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:45:35,729 INFO L470 AbstractCegarLoop]: Abstraction has 1361 states and 3438 transitions. [2022-03-15 21:45:35,729 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 34 states, 34 states have (on average 3.176470588235294) internal successors, (108), 33 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:45:35,729 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 3438 transitions. [2022-03-15 21:45:35,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:45:35,731 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:45:35,731 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:45:35,748 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Forceful destruction successful, exit code 0 [2022-03-15 21:45:35,939 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 67 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable67 [2022-03-15 21:45:35,939 INFO L402 AbstractCegarLoop]: === Iteration 69 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:45:35,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:45:35,939 INFO L85 PathProgramCache]: Analyzing trace with hash -1871146047, now seen corresponding path program 67 times [2022-03-15 21:45:35,940 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:45:35,940 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1471121149] [2022-03-15 21:45:35,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:45:35,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:45:35,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:45:36,173 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 2 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:36,173 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:45:36,173 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1471121149] [2022-03-15 21:45:36,173 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1471121149] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:45:36,173 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1858960436] [2022-03-15 21:45:36,173 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-03-15 21:45:36,173 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:45:36,173 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:45:36,174 INFO L229 MonitoredProcess]: Starting monitored process 68 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:45:36,175 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2022-03-15 21:45:36,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:45:36,202 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:45:36,202 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:45:36,795 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:45:36,795 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:45:36,848 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:36,848 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:45:37,523 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:45:37,523 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:45:42,611 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:42,612 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1858960436] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:45:42,612 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:45:42,612 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 19, 19] total 50 [2022-03-15 21:45:42,612 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1236542530] [2022-03-15 21:45:42,612 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:45:42,614 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:45:42,632 INFO L252 McrAutomatonBuilder]: Finished intersection with 140 states and 271 transitions. [2022-03-15 21:45:42,632 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:45:47,856 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [309570#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w))), 309572#(and (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W))), 309565#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 309566#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 309567#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 309569#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (+ (- 1) temp) 0) v_assert) (or v_assert (<= (+ 2 d temp) W)) (or (= (select queue front) 1) (< 0 w)) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ 2 d temp) W) (< 0 w))), 309578#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 309573#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)))), 309575#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 309580#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 309568#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 309579#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 309574#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (= temp 1))), 309577#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 309571#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (= (select queue (+ 2 front)) 1)) (or (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not (= (select queue back) 1)) v_assert (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 309564#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 309576#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:45:47,856 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 35 states [2022-03-15 21:45:47,856 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:45:47,856 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-03-15 21:45:47,856 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=405, Invalid=4151, Unknown=0, NotChecked=0, Total=4556 [2022-03-15 21:45:47,857 INFO L87 Difference]: Start difference. First operand 1361 states and 3438 transitions. Second operand has 35 states, 35 states have (on average 3.6285714285714286) internal successors, (127), 34 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:45:53,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:45:53,595 INFO L93 Difference]: Finished difference Result 7181 states and 18246 transitions. [2022-03-15 21:45:53,595 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2022-03-15 21:45:53,595 INFO L78 Accepts]: Start accepts. Automaton has has 35 states, 35 states have (on average 3.6285714285714286) internal successors, (127), 34 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:45:53,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:45:53,605 INFO L225 Difference]: With dead ends: 7181 [2022-03-15 21:45:53,605 INFO L226 Difference]: Without dead ends: 6753 [2022-03-15 21:45:53,606 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 279 GetRequests, 108 SyntacticMatches, 18 SemanticMatches, 153 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6781 ImplicationChecksByTransitivity, 6.8s TimeCoverageRelationStatistics Valid=3702, Invalid=20168, Unknown=0, NotChecked=0, Total=23870 [2022-03-15 21:45:53,607 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 380 mSDsluCounter, 459 mSDsCounter, 0 mSdLazyCounter, 1890 mSolverCounterSat, 352 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 380 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2242 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 352 IncrementalHoareTripleChecker+Valid, 1890 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-03-15 21:45:53,607 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [380 Valid, 2 Invalid, 2242 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [352 Valid, 1890 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-03-15 21:45:53,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6753 states. [2022-03-15 21:45:53,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6753 to 1619. [2022-03-15 21:45:53,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1619 states, 1618 states have (on average 2.553770086526576) internal successors, (4132), 1618 states have internal predecessors, (4132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:45:53,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1619 states to 1619 states and 4132 transitions. [2022-03-15 21:45:53,641 INFO L78 Accepts]: Start accepts. Automaton has 1619 states and 4132 transitions. Word has length 36 [2022-03-15 21:45:53,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:45:53,642 INFO L470 AbstractCegarLoop]: Abstraction has 1619 states and 4132 transitions. [2022-03-15 21:45:53,642 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 35 states, 35 states have (on average 3.6285714285714286) internal successors, (127), 34 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:45:53,642 INFO L276 IsEmpty]: Start isEmpty. Operand 1619 states and 4132 transitions. [2022-03-15 21:45:53,643 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:45:53,644 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:45:53,644 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:45:53,660 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Forceful destruction successful, exit code 0 [2022-03-15 21:45:53,851 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 68 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable68 [2022-03-15 21:45:53,851 INFO L402 AbstractCegarLoop]: === Iteration 70 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:45:53,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:45:53,852 INFO L85 PathProgramCache]: Analyzing trace with hash 1304813825, now seen corresponding path program 68 times [2022-03-15 21:45:53,859 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:45:53,860 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572903352] [2022-03-15 21:45:53,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:45:53,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:45:53,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:45:54,279 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:54,279 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:45:54,279 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1572903352] [2022-03-15 21:45:54,279 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1572903352] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:45:54,279 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [436490847] [2022-03-15 21:45:54,279 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:45:54,279 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:45:54,280 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:45:54,280 INFO L229 MonitoredProcess]: Starting monitored process 69 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:45:54,282 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2022-03-15 21:45:54,311 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:45:54,311 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:45:54,312 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:45:54,312 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:45:55,058 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:45:55,058 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:45:55,138 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:55,138 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:45:55,918 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:45:55,919 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:45:58,970 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 4 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:58,970 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [436490847] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:45:58,970 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:45:58,970 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:45:58,970 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [705846507] [2022-03-15 21:45:58,970 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:45:58,972 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:45:58,998 INFO L252 McrAutomatonBuilder]: Finished intersection with 134 states and 259 transitions. [2022-03-15 21:45:58,998 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:46:02,631 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [320439#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 320445#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (= (select queue front) (select queue (+ front 1))) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1))), 320449#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 320450#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 320446#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ front 1)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 3 d) W))), 320447#(and (or (not v_assert) (<= back (+ 3 front))) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 320451#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 320452#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 320440#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not (= (select queue back) 1)) v_assert) (or (<= (+ d 1) W) (< 1 w) (not (= (select queue back) 1))) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1))), 320437#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 320441#(and (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)))), 320443#(and (or (not v_assert) (not (< front back)) (not (< 0 w)) (= (+ front 1) back)) (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< front back)) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)))), 320453#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 320442#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 320438#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 320444#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) temp) (<= back front)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 320448#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:46:02,631 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-03-15 21:46:02,631 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:46:02,631 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-03-15 21:46:02,632 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=365, Invalid=4465, Unknown=0, NotChecked=0, Total=4830 [2022-03-15 21:46:02,632 INFO L87 Difference]: Start difference. First operand 1619 states and 4132 transitions. Second operand has 37 states, 37 states have (on average 3.3783783783783785) internal successors, (125), 36 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:46:09,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:46:09,198 INFO L93 Difference]: Finished difference Result 5390 states and 13281 transitions. [2022-03-15 21:46:09,198 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 107 states. [2022-03-15 21:46:09,199 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 3.3783783783783785) internal successors, (125), 36 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:46:09,199 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:46:09,206 INFO L225 Difference]: With dead ends: 5390 [2022-03-15 21:46:09,206 INFO L226 Difference]: Without dead ends: 5331 [2022-03-15 21:46:09,208 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 290 GetRequests, 97 SyntacticMatches, 21 SemanticMatches, 172 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8737 ImplicationChecksByTransitivity, 7.8s TimeCoverageRelationStatistics Valid=3826, Invalid=26276, Unknown=0, NotChecked=0, Total=30102 [2022-03-15 21:46:09,208 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 297 mSDsluCounter, 625 mSDsCounter, 0 mSdLazyCounter, 2064 mSolverCounterSat, 306 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 297 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 2370 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 306 IncrementalHoareTripleChecker+Valid, 2064 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-03-15 21:46:09,208 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [297 Valid, 1 Invalid, 2370 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [306 Valid, 2064 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-03-15 21:46:09,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5331 states. [2022-03-15 21:46:09,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5331 to 1729. [2022-03-15 21:46:09,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1729 states, 1728 states have (on average 2.548611111111111) internal successors, (4404), 1728 states have internal predecessors, (4404), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:46:09,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1729 states to 1729 states and 4404 transitions. [2022-03-15 21:46:09,242 INFO L78 Accepts]: Start accepts. Automaton has 1729 states and 4404 transitions. Word has length 36 [2022-03-15 21:46:09,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:46:09,243 INFO L470 AbstractCegarLoop]: Abstraction has 1729 states and 4404 transitions. [2022-03-15 21:46:09,243 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 3.3783783783783785) internal successors, (125), 36 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:46:09,243 INFO L276 IsEmpty]: Start isEmpty. Operand 1729 states and 4404 transitions. [2022-03-15 21:46:09,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:46:09,245 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:46:09,245 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:46:09,261 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Forceful destruction successful, exit code 0 [2022-03-15 21:46:09,459 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 69 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable69 [2022-03-15 21:46:09,459 INFO L402 AbstractCegarLoop]: === Iteration 71 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:46:09,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:46:09,460 INFO L85 PathProgramCache]: Analyzing trace with hash -34736365, now seen corresponding path program 69 times [2022-03-15 21:46:09,460 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:46:09,460 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1455384579] [2022-03-15 21:46:09,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:46:09,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:46:09,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:46:09,772 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 7 proven. 53 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:46:09,772 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:46:09,772 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1455384579] [2022-03-15 21:46:09,772 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1455384579] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:46:09,772 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [812242284] [2022-03-15 21:46:09,772 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:46:09,772 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:46:09,772 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:46:09,773 INFO L229 MonitoredProcess]: Starting monitored process 70 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:46:09,774 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2022-03-15 21:46:09,800 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-03-15 21:46:09,800 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:46:09,801 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:46:09,802 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:46:10,579 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:46:10,580 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:46:10,652 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:46:10,652 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:46:11,514 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:46:11,515 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:46:15,806 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 4 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:46:15,807 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [812242284] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:46:15,807 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:46:15,807 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:46:15,807 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1736749509] [2022-03-15 21:46:15,807 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:46:15,808 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:46:15,825 INFO L252 McrAutomatonBuilder]: Finished intersection with 121 states and 229 transitions. [2022-03-15 21:46:15,826 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:46:18,682 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 16 new interpolants: [329781#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (= temp 1))), 329775#(and (or (not v_assert) (<= back (+ front 1)) (<= w 0)) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) d 1) W) (<= back front))), 329782#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 329783#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 329779#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 329777#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (< back (+ 2 front)) (not (< 0 w)) (= (select queue front) (select queue (+ front 1)))) (or (not v_assert) (< back (+ 2 front)) (not (< 0 w)) (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (< back (+ 2 front)) (not (< 0 w)))), 329780#(and (or (not v_assert) (<= (+ d temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 329773#(and (or (<= (+ d 1) W) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= back front))), 329785#(and (or (not v_assert) (<= back (+ 3 front))) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 329788#(and v_assert (< 0 w)), 329776#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1) (<= back front)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W) (<= back front)) (or (not v_assert) (not (< 0 w)) (= (select queue front) temp) (<= back front)) (or (not v_assert) (<= back (+ front 1)) (<= w 0))), 329784#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 329786#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 329787#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 329778#(and (or (not v_assert) (< back (+ front 1)) (= (select queue front) (select queue (+ front 1))) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (< back (+ front 1)) (not (< 1 w)) (not (= (select queue back) 1)) (<= (+ 3 d) W)) (or (not v_assert) (<= back (+ front 1)) (not (< 1 w)) (not (= (select queue back) 1)))), 329774#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (not (< 0 w)) (<= (+ d temp 1) W)))] [2022-03-15 21:46:18,683 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2022-03-15 21:46:18,683 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:46:18,683 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-03-15 21:46:18,684 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=4295, Unknown=0, NotChecked=0, Total=4692 [2022-03-15 21:46:18,684 INFO L87 Difference]: Start difference. First operand 1729 states and 4404 transitions. Second operand has 36 states, 36 states have (on average 3.1944444444444446) internal successors, (115), 35 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:46:25,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:46:25,239 INFO L93 Difference]: Finished difference Result 4467 states and 10927 transitions. [2022-03-15 21:46:25,240 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 128 states. [2022-03-15 21:46:25,240 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 36 states have (on average 3.1944444444444446) internal successors, (115), 35 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:46:25,240 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:46:25,246 INFO L225 Difference]: With dead ends: 4467 [2022-03-15 21:46:25,246 INFO L226 Difference]: Without dead ends: 4440 [2022-03-15 21:46:25,248 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 297 GetRequests, 92 SyntacticMatches, 14 SemanticMatches, 191 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12024 ImplicationChecksByTransitivity, 7.6s TimeCoverageRelationStatistics Valid=4035, Invalid=33021, Unknown=0, NotChecked=0, Total=37056 [2022-03-15 21:46:25,249 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 372 mSDsluCounter, 523 mSDsCounter, 0 mSdLazyCounter, 1737 mSolverCounterSat, 337 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 372 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 2074 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 337 IncrementalHoareTripleChecker+Valid, 1737 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:46:25,249 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [372 Valid, 1 Invalid, 2074 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [337 Valid, 1737 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:46:25,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4440 states. [2022-03-15 21:46:25,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4440 to 1713. [2022-03-15 21:46:25,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1713 states, 1712 states have (on average 2.5490654205607477) internal successors, (4364), 1712 states have internal predecessors, (4364), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:46:25,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1713 states to 1713 states and 4364 transitions. [2022-03-15 21:46:25,277 INFO L78 Accepts]: Start accepts. Automaton has 1713 states and 4364 transitions. Word has length 36 [2022-03-15 21:46:25,277 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:46:25,277 INFO L470 AbstractCegarLoop]: Abstraction has 1713 states and 4364 transitions. [2022-03-15 21:46:25,277 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 36 states have (on average 3.1944444444444446) internal successors, (115), 35 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:46:25,277 INFO L276 IsEmpty]: Start isEmpty. Operand 1713 states and 4364 transitions. [2022-03-15 21:46:25,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:46:25,279 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:46:25,279 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:46:25,297 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Forceful destruction successful, exit code 0 [2022-03-15 21:46:25,483 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable70,70 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:46:25,483 INFO L402 AbstractCegarLoop]: === Iteration 72 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:46:25,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:46:25,484 INFO L85 PathProgramCache]: Analyzing trace with hash -1385925439, now seen corresponding path program 70 times [2022-03-15 21:46:25,484 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:46:25,484 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86737513] [2022-03-15 21:46:25,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:46:25,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:46:25,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:46:25,784 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 1 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:46:25,784 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:46:25,784 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [86737513] [2022-03-15 21:46:25,784 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [86737513] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:46:25,799 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [181958356] [2022-03-15 21:46:25,799 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:46:25,799 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:46:25,799 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:46:25,800 INFO L229 MonitoredProcess]: Starting monitored process 71 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:46:25,801 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Waiting until timeout for monitored process [2022-03-15 21:46:25,829 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:46:25,829 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:46:25,829 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:46:25,830 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:46:26,498 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:46:26,498 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:46:26,551 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:46:26,551 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:46:27,260 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:46:27,261 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:46:32,005 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:46:32,005 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [181958356] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:46:32,005 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:46:32,005 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 19, 19] total 49 [2022-03-15 21:46:32,005 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [468619646] [2022-03-15 21:46:32,005 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:46:32,007 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:46:32,025 INFO L252 McrAutomatonBuilder]: Finished intersection with 137 states and 265 transitions. [2022-03-15 21:46:32,025 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:46:36,590 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [338190#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 338196#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (<= (+ 2 d) W) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 338201#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (<= (+ d w temp 1) W) (not (< 0 w)))), 338199#(and (or (not v_assert) (not (< 0 w)) (<= front back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W)) (or (not v_assert) (not (< 0 w)) (<= back front))), 338193#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 338206#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 338191#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 338200#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 338197#(and (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1))), 338202#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 338203#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 338192#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 338198#(and (or (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (= (select queue front) 1) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (not v_assert) (<= (+ 2 d) W) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 1 w)) (not (= (select queue back) 1)) (< 2 w) (not (= (select queue (+ back 1)) 1)))), 338205#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 338194#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 338204#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 338195#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert))] [2022-03-15 21:46:36,590 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 34 states [2022-03-15 21:46:36,590 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:46:36,591 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2022-03-15 21:46:36,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=377, Invalid=4045, Unknown=0, NotChecked=0, Total=4422 [2022-03-15 21:46:36,591 INFO L87 Difference]: Start difference. First operand 1713 states and 4364 transitions. Second operand has 34 states, 34 states have (on average 3.6470588235294117) internal successors, (124), 33 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:46:42,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:46:42,848 INFO L93 Difference]: Finished difference Result 7648 states and 19404 transitions. [2022-03-15 21:46:42,848 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 110 states. [2022-03-15 21:46:42,848 INFO L78 Accepts]: Start accepts. Automaton has has 34 states, 34 states have (on average 3.6470588235294117) internal successors, (124), 33 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:46:42,848 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:46:42,859 INFO L225 Difference]: With dead ends: 7648 [2022-03-15 21:46:42,859 INFO L226 Difference]: Without dead ends: 7236 [2022-03-15 21:46:42,860 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 292 GetRequests, 105 SyntacticMatches, 19 SemanticMatches, 168 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8386 ImplicationChecksByTransitivity, 7.3s TimeCoverageRelationStatistics Valid=4172, Invalid=24558, Unknown=0, NotChecked=0, Total=28730 [2022-03-15 21:46:42,861 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 423 mSDsluCounter, 627 mSDsCounter, 0 mSdLazyCounter, 2493 mSolverCounterSat, 394 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 423 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2887 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 394 IncrementalHoareTripleChecker+Valid, 2493 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:46:42,861 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [423 Valid, 2 Invalid, 2887 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [394 Valid, 2493 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2022-03-15 21:46:42,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7236 states. [2022-03-15 21:46:42,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7236 to 2257. [2022-03-15 21:46:42,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2257 states, 2256 states have (on average 2.5775709219858154) internal successors, (5815), 2256 states have internal predecessors, (5815), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:46:42,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2257 states to 2257 states and 5815 transitions. [2022-03-15 21:46:42,914 INFO L78 Accepts]: Start accepts. Automaton has 2257 states and 5815 transitions. Word has length 36 [2022-03-15 21:46:42,914 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:46:42,914 INFO L470 AbstractCegarLoop]: Abstraction has 2257 states and 5815 transitions. [2022-03-15 21:46:42,914 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 34 states, 34 states have (on average 3.6470588235294117) internal successors, (124), 33 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:46:42,914 INFO L276 IsEmpty]: Start isEmpty. Operand 2257 states and 5815 transitions. [2022-03-15 21:46:42,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:46:42,917 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:46:42,917 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:46:42,933 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Forceful destruction successful, exit code 0 [2022-03-15 21:46:43,123 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable71,71 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:46:43,123 INFO L402 AbstractCegarLoop]: === Iteration 73 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:46:43,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:46:43,123 INFO L85 PathProgramCache]: Analyzing trace with hash 1329130849, now seen corresponding path program 71 times [2022-03-15 21:46:43,124 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:46:43,124 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1675166459] [2022-03-15 21:46:43,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:46:43,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:46:43,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:46:43,365 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 1 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:46:43,365 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:46:43,366 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1675166459] [2022-03-15 21:46:43,366 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1675166459] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:46:43,366 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1876878886] [2022-03-15 21:46:43,366 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:46:43,366 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:46:43,366 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:46:43,367 INFO L229 MonitoredProcess]: Starting monitored process 72 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:46:43,368 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Waiting until timeout for monitored process [2022-03-15 21:46:43,397 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2022-03-15 21:46:43,397 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:46:43,398 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:46:43,399 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:46:44,276 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,276 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:44,277 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,277 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,278 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,279 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,279 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,280 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,280 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,281 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,282 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,282 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,283 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:44,283 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,284 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,284 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,285 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,286 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,286 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,287 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:44,287 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,288 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,288 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:44,289 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:44,289 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:44,290 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 10 disjoint index pairs (out of 45 index pairs), introduced 5 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 26 [2022-03-15 21:46:44,373 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:46:44,373 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:46:45,308 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,308 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,309 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,309 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,310 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,311 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,311 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,311 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,312 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,312 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,313 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,313 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,314 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,314 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,315 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,315 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,315 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,316 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,316 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,317 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,319 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,320 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,320 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,321 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,322 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,322 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:45,385 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:46:45,385 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 26 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 19 case distinctions, treesize of input 64 treesize of output 234 [2022-03-15 21:46:46,442 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:46:46,442 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1876878886] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:46:46,443 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:46:46,443 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 19, 19] total 49 [2022-03-15 21:46:46,443 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1155146335] [2022-03-15 21:46:46,443 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:46:46,444 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:46:46,461 INFO L252 McrAutomatonBuilder]: Finished intersection with 121 states and 229 transitions. [2022-03-15 21:46:46,461 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:46:49,533 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 16 new interpolants: [350846#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 350839#(and (or (not v_assert) (not (< 0 w)) (<= front back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W)) (or (not v_assert) (not (< 0 w)) (<= back front))), 350837#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 350847#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 350842#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 350850#(and v_assert (< 0 w)), 350838#(and (or (not v_assert) (= (+ front 1) (+ back 1)) (not (< 1 w)) (not (= (select queue back) 1))) (or (not v_assert) (<= (+ 2 d) W) (not (< 1 w)) (not (= (select queue back) 1)))), 350840#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 350843#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 350848#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 350845#(and (or (not v_assert) (<= (+ d temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 350844#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 350849#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 350841#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (<= (+ d w temp 1) W) (not (< 0 w)))), 350835#(and (or (<= (+ d 1) W) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= back front))), 350836#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w))))] [2022-03-15 21:46:49,533 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 33 states [2022-03-15 21:46:49,533 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:46:49,534 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2022-03-15 21:46:49,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=443, Invalid=3847, Unknown=0, NotChecked=0, Total=4290 [2022-03-15 21:46:49,534 INFO L87 Difference]: Start difference. First operand 2257 states and 5815 transitions. Second operand has 33 states, 33 states have (on average 3.393939393939394) internal successors, (112), 32 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:46:53,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:46:53,442 INFO L93 Difference]: Finished difference Result 5505 states and 13911 transitions. [2022-03-15 21:46:53,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 82 states. [2022-03-15 21:46:53,442 INFO L78 Accepts]: Start accepts. Automaton has has 33 states, 33 states have (on average 3.393939393939394) internal successors, (112), 32 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:46:53,443 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:46:53,448 INFO L225 Difference]: With dead ends: 5505 [2022-03-15 21:46:53,449 INFO L226 Difference]: Without dead ends: 5341 [2022-03-15 21:46:53,449 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 251 GetRequests, 89 SyntacticMatches, 20 SemanticMatches, 142 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5757 ImplicationChecksByTransitivity, 5.6s TimeCoverageRelationStatistics Valid=2812, Invalid=17780, Unknown=0, NotChecked=0, Total=20592 [2022-03-15 21:46:53,449 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 384 mSDsluCounter, 514 mSDsCounter, 0 mSdLazyCounter, 1827 mSolverCounterSat, 294 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 384 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2121 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 294 IncrementalHoareTripleChecker+Valid, 1827 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-03-15 21:46:53,449 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [384 Valid, 2 Invalid, 2121 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [294 Valid, 1827 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-03-15 21:46:53,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5341 states. [2022-03-15 21:46:53,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5341 to 1993. [2022-03-15 21:46:53,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1993 states, 1992 states have (on average 2.573293172690763) internal successors, (5126), 1992 states have internal predecessors, (5126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:46:53,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1993 states to 1993 states and 5126 transitions. [2022-03-15 21:46:53,482 INFO L78 Accepts]: Start accepts. Automaton has 1993 states and 5126 transitions. Word has length 36 [2022-03-15 21:46:53,482 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:46:53,482 INFO L470 AbstractCegarLoop]: Abstraction has 1993 states and 5126 transitions. [2022-03-15 21:46:53,483 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 33 states, 33 states have (on average 3.393939393939394) internal successors, (112), 32 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:46:53,483 INFO L276 IsEmpty]: Start isEmpty. Operand 1993 states and 5126 transitions. [2022-03-15 21:46:53,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:46:53,487 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:46:53,487 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:46:53,511 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Forceful destruction successful, exit code 0 [2022-03-15 21:46:53,693 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable72,72 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:46:53,693 INFO L402 AbstractCegarLoop]: === Iteration 74 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:46:53,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:46:53,693 INFO L85 PathProgramCache]: Analyzing trace with hash -844565943, now seen corresponding path program 72 times [2022-03-15 21:46:53,694 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:46:53,694 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232728762] [2022-03-15 21:46:53,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:46:53,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:46:53,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:46:54,003 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 59 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:46:54,003 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:46:54,003 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1232728762] [2022-03-15 21:46:54,003 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1232728762] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:46:54,004 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [490069249] [2022-03-15 21:46:54,004 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:46:54,004 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:46:54,004 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:46:54,005 INFO L229 MonitoredProcess]: Starting monitored process 73 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:46:54,005 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Waiting until timeout for monitored process [2022-03-15 21:46:54,035 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2022-03-15 21:46:54,035 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:46:54,036 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 44 conjunts are in the unsatisfiable core [2022-03-15 21:46:54,037 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:46:54,869 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:54,870 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:54,871 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:54,871 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:54,871 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:54,872 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:54,872 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:54,873 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:54,873 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:54,873 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:54,874 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:54,874 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:54,875 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:46:54,876 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 10 disjoint index pairs (out of 15 index pairs), introduced 5 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 26 [2022-03-15 21:46:54,949 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:46:54,949 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:46:55,900 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,901 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,901 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,903 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,903 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,904 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,905 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,906 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,906 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,906 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,907 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,907 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,907 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,907 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,908 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,913 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,914 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,915 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,932 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,932 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,932 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,933 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,933 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,934 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,935 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,935 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:46:55,998 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:46:55,999 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 26 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 19 case distinctions, treesize of input 62 treesize of output 224 [2022-03-15 21:46:56,724 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:46:56,724 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [490069249] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:46:56,724 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:46:56,724 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 19, 19] total 49 [2022-03-15 21:46:56,724 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1552616084] [2022-03-15 21:46:56,724 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:46:56,726 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:46:56,742 INFO L252 McrAutomatonBuilder]: Finished intersection with 115 states and 214 transitions. [2022-03-15 21:46:56,742 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:46:59,831 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 16 new interpolants: [360759#(and (or (not v_assert) (<= (+ 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 360765#(and (or (not v_assert) (not (< 0 w)) (<= front back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W)) (or (not v_assert) (not (< 0 w)) (<= back front))), 360758#(and (or (not v_assert) (not (< 0 w)) (<= front back)) (or (not v_assert) (<= (+ d w) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= back front))), 360766#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ d w 1) W))), 360772#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 360773#(and v_assert (< 0 w)), 360770#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 360769#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 360767#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 360761#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 360771#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 360763#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ 2 d temp) W)) (or (not v_assert) (= (select queue front) 1))), 360762#(and (or (not v_assert) (<= (+ 2 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 360760#(and (or (not v_assert) (<= (+ 2 d) W)) (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (= (select queue front) 1))), 360768#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (<= (+ d w temp 1) W) (not (< 0 w)))), 360764#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w temp 1) W)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:46:59,831 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 33 states [2022-03-15 21:46:59,831 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:46:59,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2022-03-15 21:46:59,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=436, Invalid=3854, Unknown=0, NotChecked=0, Total=4290 [2022-03-15 21:46:59,832 INFO L87 Difference]: Start difference. First operand 1993 states and 5126 transitions. Second operand has 33 states, 33 states have (on average 3.303030303030303) internal successors, (109), 32 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:47:04,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:47:04,464 INFO L93 Difference]: Finished difference Result 5073 states and 12818 transitions. [2022-03-15 21:47:04,464 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2022-03-15 21:47:04,464 INFO L78 Accepts]: Start accepts. Automaton has has 33 states, 33 states have (on average 3.303030303030303) internal successors, (109), 32 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:47:04,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:47:04,470 INFO L225 Difference]: With dead ends: 5073 [2022-03-15 21:47:04,470 INFO L226 Difference]: Without dead ends: 4804 [2022-03-15 21:47:04,470 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 95 SyntacticMatches, 8 SemanticMatches, 135 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4645 ImplicationChecksByTransitivity, 5.8s TimeCoverageRelationStatistics Valid=2564, Invalid=16068, Unknown=0, NotChecked=0, Total=18632 [2022-03-15 21:47:04,470 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 388 mSDsluCounter, 724 mSDsCounter, 0 mSdLazyCounter, 2466 mSolverCounterSat, 310 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 388 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2776 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 310 IncrementalHoareTripleChecker+Valid, 2466 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:47:04,471 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [388 Valid, 2 Invalid, 2776 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [310 Valid, 2466 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2022-03-15 21:47:04,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4804 states. [2022-03-15 21:47:04,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4804 to 1307. [2022-03-15 21:47:04,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1307 states, 1306 states have (on average 2.5696784073506893) internal successors, (3356), 1306 states have internal predecessors, (3356), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:47:04,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1307 states to 1307 states and 3356 transitions. [2022-03-15 21:47:04,494 INFO L78 Accepts]: Start accepts. Automaton has 1307 states and 3356 transitions. Word has length 36 [2022-03-15 21:47:04,494 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:47:04,494 INFO L470 AbstractCegarLoop]: Abstraction has 1307 states and 3356 transitions. [2022-03-15 21:47:04,494 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 33 states, 33 states have (on average 3.303030303030303) internal successors, (109), 32 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:47:04,494 INFO L276 IsEmpty]: Start isEmpty. Operand 1307 states and 3356 transitions. [2022-03-15 21:47:04,495 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:47:04,495 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:47:04,495 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:47:04,511 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Forceful destruction successful, exit code 0 [2022-03-15 21:47:04,709 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 73 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable73 [2022-03-15 21:47:04,710 INFO L402 AbstractCegarLoop]: === Iteration 75 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:47:04,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:47:04,710 INFO L85 PathProgramCache]: Analyzing trace with hash -1236772813, now seen corresponding path program 73 times [2022-03-15 21:47:04,711 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:47:04,711 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [801171607] [2022-03-15 21:47:04,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:47:04,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:47:04,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:47:05,058 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:47:05,058 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:47:05,058 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [801171607] [2022-03-15 21:47:05,058 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [801171607] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:47:05,058 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [638919137] [2022-03-15 21:47:05,058 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-03-15 21:47:05,058 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:47:05,059 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:47:05,060 INFO L229 MonitoredProcess]: Starting monitored process 74 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:47:05,061 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (74)] Waiting until timeout for monitored process [2022-03-15 21:47:05,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:47:05,087 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:47:05,088 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:47:05,703 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:47:05,704 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:47:05,761 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:47:05,761 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:47:06,390 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:47:06,390 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:47:11,907 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 9 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:47:11,908 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [638919137] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:47:11,908 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:47:11,908 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:47:11,908 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1598501175] [2022-03-15 21:47:11,908 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:47:11,910 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:47:11,928 INFO L252 McrAutomatonBuilder]: Finished intersection with 141 states and 271 transitions. [2022-03-15 21:47:11,928 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:47:16,864 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 18 new interpolants: [368874#(and (or v_assert (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (< 0 w) (<= (+ d 4) W)) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ 3 front)) 1) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (= (select queue (+ 3 front)) 1) (< 0 w))), 368870#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 368871#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (+ (- 1) temp) 0) v_assert) (or v_assert (<= (+ 2 d temp) W)) (or (= (select queue front) 1) (< 0 w)) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ 2 d temp) W) (< 0 w))), 368876#(and (or (not v_assert) (<= (+ d w 4) W)) (or (not v_assert) (= (select queue (+ 3 front)) 1)) (or (not v_assert) (<= back (+ front 4))) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)) (or (not v_assert) (<= (+ front 4) back))), 368868#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 368875#(and (or (not v_assert) (<= (+ 5 d) W)) (or (not v_assert) (= (select queue (+ 3 front)) 1)) (or (not v_assert) (<= back (+ front 4))) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)) (or (not v_assert) (<= (+ front 4) back))), 368866#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 368877#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 368872#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w))), 368878#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ 3 front)) 1) (not (= (select queue back) 1)) v_assert) (or (= (select queue (+ 3 front)) 1) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (< 1 w) (not (= (select queue back) 1)) (<= (+ d 4) W)) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (<= (+ d 4) W)) (or (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 368879#(and (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (not (< 0 w)) (= (select queue (+ 3 front)) 1) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (<= (+ d 4) W))), 368882#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 368867#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 368880#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ 5 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 368881#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 368869#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 368883#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 368873#(and (or v_assert (<= (+ d 4) W)) (or (= temp 1) (< 0 w)) (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (< 0 w) (<= (+ d 4) W)) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (= (select queue front) 1) (< 0 w)) (or v_assert (= temp 1)))] [2022-03-15 21:47:16,864 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 38 states [2022-03-15 21:47:16,864 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:47:16,864 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-03-15 21:47:16,864 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=478, Invalid=4492, Unknown=0, NotChecked=0, Total=4970 [2022-03-15 21:47:16,865 INFO L87 Difference]: Start difference. First operand 1307 states and 3356 transitions. Second operand has 38 states, 38 states have (on average 3.5) internal successors, (133), 37 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:47:22,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:47:22,798 INFO L93 Difference]: Finished difference Result 5826 states and 14707 transitions. [2022-03-15 21:47:22,798 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2022-03-15 21:47:22,798 INFO L78 Accepts]: Start accepts. Automaton has has 38 states, 38 states have (on average 3.5) internal successors, (133), 37 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:47:22,799 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:47:22,805 INFO L225 Difference]: With dead ends: 5826 [2022-03-15 21:47:22,805 INFO L226 Difference]: Without dead ends: 5713 [2022-03-15 21:47:22,806 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 288 GetRequests, 113 SyntacticMatches, 11 SemanticMatches, 164 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7179 ImplicationChecksByTransitivity, 7.0s TimeCoverageRelationStatistics Valid=4517, Invalid=22873, Unknown=0, NotChecked=0, Total=27390 [2022-03-15 21:47:22,806 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 319 mSDsluCounter, 686 mSDsCounter, 0 mSdLazyCounter, 2368 mSolverCounterSat, 240 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 319 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2608 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 240 IncrementalHoareTripleChecker+Valid, 2368 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-03-15 21:47:22,806 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [319 Valid, 2 Invalid, 2608 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [240 Valid, 2368 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-03-15 21:47:22,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5713 states. [2022-03-15 21:47:22,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5713 to 1353. [2022-03-15 21:47:22,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1353 states, 1352 states have (on average 2.5680473372781063) internal successors, (3472), 1352 states have internal predecessors, (3472), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:47:22,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1353 states to 1353 states and 3472 transitions. [2022-03-15 21:47:22,832 INFO L78 Accepts]: Start accepts. Automaton has 1353 states and 3472 transitions. Word has length 36 [2022-03-15 21:47:22,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:47:22,832 INFO L470 AbstractCegarLoop]: Abstraction has 1353 states and 3472 transitions. [2022-03-15 21:47:22,832 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 38 states, 38 states have (on average 3.5) internal successors, (133), 37 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:47:22,832 INFO L276 IsEmpty]: Start isEmpty. Operand 1353 states and 3472 transitions. [2022-03-15 21:47:22,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:47:22,834 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:47:22,834 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:47:22,850 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (74)] Ended with exit code 0 [2022-03-15 21:47:23,049 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable74,74 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:47:23,050 INFO L402 AbstractCegarLoop]: === Iteration 76 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:47:23,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:47:23,050 INFO L85 PathProgramCache]: Analyzing trace with hash 827856961, now seen corresponding path program 74 times [2022-03-15 21:47:23,050 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:47:23,050 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091143265] [2022-03-15 21:47:23,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:47:23,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:47:23,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:47:23,431 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:47:23,432 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:47:23,432 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1091143265] [2022-03-15 21:47:23,432 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1091143265] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:47:23,432 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [711097431] [2022-03-15 21:47:23,432 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:47:23,432 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:47:23,432 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:47:23,433 INFO L229 MonitoredProcess]: Starting monitored process 75 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:47:23,434 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (75)] Waiting until timeout for monitored process [2022-03-15 21:47:23,461 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:47:23,462 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:47:23,462 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:47:23,463 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:47:24,299 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:47:24,300 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:47:24,378 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:47:24,379 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:47:25,273 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:47:25,273 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:47:29,842 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 9 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:47:29,842 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [711097431] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:47:29,842 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:47:29,842 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:47:29,842 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1850127510] [2022-03-15 21:47:29,842 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:47:29,844 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:47:29,862 INFO L252 McrAutomatonBuilder]: Finished intersection with 138 states and 265 transitions. [2022-03-15 21:47:29,862 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:47:34,781 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 18 new interpolants: [377878#(and (or (not v_assert) (<= (+ 5 d) W)) (or (not v_assert) (= (select queue (+ 3 front)) 1)) (or (not v_assert) (<= back (+ front 4))) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)) (or (not v_assert) (<= (+ front 4) back))), 377872#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 377870#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 377873#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 377877#(and (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W))), 377881#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 377886#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 377871#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 377874#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (+ (- 1) temp) 0) v_assert) (or v_assert (<= (+ 2 d temp) W)) (or (= (select queue front) 1) (< 0 w)) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ 2 d temp) W) (< 0 w))), 377879#(and (or (not v_assert) (<= (+ d w 4) W)) (or (not v_assert) (= (select queue (+ 3 front)) 1)) (or (not v_assert) (<= back (+ front 4))) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)) (or (not v_assert) (<= (+ front 4) back))), 377875#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (= (select queue (+ 2 front)) 1) (< 0 w)) (or v_assert (= (select queue (+ 2 front)) 1)) (or (< 0 w) (<= (+ 3 d) W)) (or v_assert (<= (+ 3 d) W)) (or (= (select queue front) 1) (< 0 w))), 377884#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (<= (+ d temp 4) W) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 377885#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 377882#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 377869#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 377880#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 377876#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (not (= (select queue back) 1)) v_assert (= (select queue (+ 2 front)) 1)) (or (< 1 w) (not (= (select queue back) 1)) (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (< 1 w) (not (= (select queue back) 1)) (= (select queue (+ 2 front)) 1)) (or (not (= (select queue back) 1)) v_assert (<= (+ 3 d) W)) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 377883#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w))))] [2022-03-15 21:47:34,781 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 38 states [2022-03-15 21:47:34,782 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:47:34,782 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-03-15 21:47:34,782 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=469, Invalid=4501, Unknown=0, NotChecked=0, Total=4970 [2022-03-15 21:47:34,782 INFO L87 Difference]: Start difference. First operand 1353 states and 3472 transitions. Second operand has 38 states, 38 states have (on average 3.4473684210526314) internal successors, (131), 37 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:47:39,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:47:39,855 INFO L93 Difference]: Finished difference Result 5663 states and 14287 transitions. [2022-03-15 21:47:39,855 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2022-03-15 21:47:39,855 INFO L78 Accepts]: Start accepts. Automaton has has 38 states, 38 states have (on average 3.4473684210526314) internal successors, (131), 37 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:47:39,855 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:47:39,862 INFO L225 Difference]: With dead ends: 5663 [2022-03-15 21:47:39,863 INFO L226 Difference]: Without dead ends: 5573 [2022-03-15 21:47:39,864 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 275 GetRequests, 111 SyntacticMatches, 10 SemanticMatches, 154 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6080 ImplicationChecksByTransitivity, 6.6s TimeCoverageRelationStatistics Valid=3764, Invalid=20416, Unknown=0, NotChecked=0, Total=24180 [2022-03-15 21:47:39,864 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 339 mSDsluCounter, 573 mSDsCounter, 0 mSdLazyCounter, 2003 mSolverCounterSat, 263 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 339 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2266 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 263 IncrementalHoareTripleChecker+Valid, 2003 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:47:39,864 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [339 Valid, 2 Invalid, 2266 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [263 Valid, 2003 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:47:39,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5573 states. [2022-03-15 21:47:39,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5573 to 1365. [2022-03-15 21:47:39,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1365 states, 1364 states have (on average 2.567448680351906) internal successors, (3502), 1364 states have internal predecessors, (3502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:47:39,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1365 states to 1365 states and 3502 transitions. [2022-03-15 21:47:39,893 INFO L78 Accepts]: Start accepts. Automaton has 1365 states and 3502 transitions. Word has length 36 [2022-03-15 21:47:39,893 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:47:39,893 INFO L470 AbstractCegarLoop]: Abstraction has 1365 states and 3502 transitions. [2022-03-15 21:47:39,893 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 38 states, 38 states have (on average 3.4473684210526314) internal successors, (131), 37 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:47:39,893 INFO L276 IsEmpty]: Start isEmpty. Operand 1365 states and 3502 transitions. [2022-03-15 21:47:39,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:47:39,894 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:47:39,894 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:47:39,911 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (75)] Forceful destruction successful, exit code 0 [2022-03-15 21:47:40,109 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable75,75 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:47:40,109 INFO L402 AbstractCegarLoop]: === Iteration 77 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:47:40,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:47:40,109 INFO L85 PathProgramCache]: Analyzing trace with hash -50789645, now seen corresponding path program 75 times [2022-03-15 21:47:40,110 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:47:40,110 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2071715357] [2022-03-15 21:47:40,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:47:40,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:47:40,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:47:40,380 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:47:40,380 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:47:40,380 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2071715357] [2022-03-15 21:47:40,380 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2071715357] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:47:40,380 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [235514774] [2022-03-15 21:47:40,380 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:47:40,380 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:47:40,381 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:47:40,382 INFO L229 MonitoredProcess]: Starting monitored process 76 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:47:40,383 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (76)] Waiting until timeout for monitored process [2022-03-15 21:47:40,419 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-03-15 21:47:40,419 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:47:40,423 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:47:40,424 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:47:41,073 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:47:41,073 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:47:41,130 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:47:41,130 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:47:41,800 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:47:41,800 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:47:46,307 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 9 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:47:46,307 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [235514774] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:47:46,307 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:47:46,307 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:47:46,307 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1565185736] [2022-03-15 21:47:46,307 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:47:46,309 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:47:46,327 INFO L252 McrAutomatonBuilder]: Finished intersection with 135 states and 259 transitions. [2022-03-15 21:47:46,327 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:47:50,288 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 18 new interpolants: [386724#(and (or (not v_assert) (<= (+ d w 4) W)) (or (not v_assert) (= (select queue (+ 3 front)) 1)) (or (not v_assert) (<= back (+ front 4))) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)) (or (not v_assert) (<= (+ front 4) back))), 386730#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 386713#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 386718#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) (not (= (select queue back) 1)) v_assert) (or (<= (+ 2 d) W) (not (= (select queue back) 1)) v_assert) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (< 1 w) (not (= (select queue back) 1)))), 386723#(and (or (not v_assert) (<= (+ 5 d) W)) (or (not v_assert) (= (select queue (+ 3 front)) 1)) (or (not v_assert) (<= back (+ front 4))) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)) (or (not v_assert) (<= (+ front 4) back))), 386720#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (<= back (+ front 1))) (or (not v_assert) (not (< 0 w)) (<= (+ front 1) back)) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 386717#(and (or (= (select queue (+ front 1)) 1) (< 0 w)) (or v_assert (= (select queue front) 1)) (or (= (select queue (+ front 1)) 1) v_assert) (or (<= (+ 2 d) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert)), 386719#(and (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1))) (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1))), 386727#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 386716#(and (or v_assert (= (select queue front) 1)) (or (<= (+ 2 d) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ 2 d) W) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w))), 386726#(and (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ 3 d temp) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 386721#(and (or (not v_assert) (not (< 0 w)) (<= (+ 3 d) W)) (or (not v_assert) (not (< 0 w)) (<= back (+ 2 front))) (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 386729#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 386722#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 386715#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 386728#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (<= (+ d temp 4) W) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 386725#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 386714#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert))] [2022-03-15 21:47:50,288 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 38 states [2022-03-15 21:47:50,288 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:47:50,288 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-03-15 21:47:50,288 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=457, Invalid=4513, Unknown=0, NotChecked=0, Total=4970 [2022-03-15 21:47:50,288 INFO L87 Difference]: Start difference. First operand 1365 states and 3502 transitions. Second operand has 38 states, 38 states have (on average 3.3947368421052633) internal successors, (129), 37 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:47:56,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:47:56,286 INFO L93 Difference]: Finished difference Result 5346 states and 13496 transitions. [2022-03-15 21:47:56,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 82 states. [2022-03-15 21:47:56,286 INFO L78 Accepts]: Start accepts. Automaton has has 38 states, 38 states have (on average 3.3947368421052633) internal successors, (129), 37 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:47:56,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:47:56,293 INFO L225 Difference]: With dead ends: 5346 [2022-03-15 21:47:56,293 INFO L226 Difference]: Without dead ends: 5273 [2022-03-15 21:47:56,294 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 266 GetRequests, 106 SyntacticMatches, 12 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5684 ImplicationChecksByTransitivity, 6.9s TimeCoverageRelationStatistics Valid=3175, Invalid=19175, Unknown=0, NotChecked=0, Total=22350 [2022-03-15 21:47:56,294 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 338 mSDsluCounter, 658 mSDsCounter, 0 mSdLazyCounter, 2233 mSolverCounterSat, 259 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 338 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2492 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 259 IncrementalHoareTripleChecker+Valid, 2233 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2022-03-15 21:47:56,295 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [338 Valid, 2 Invalid, 2492 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [259 Valid, 2233 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2022-03-15 21:47:56,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5273 states. [2022-03-15 21:47:56,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5273 to 1377. [2022-03-15 21:47:56,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1376 states have (on average 2.566860465116279) internal successors, (3532), 1376 states have internal predecessors, (3532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:47:56,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 3532 transitions. [2022-03-15 21:47:56,321 INFO L78 Accepts]: Start accepts. Automaton has 1377 states and 3532 transitions. Word has length 36 [2022-03-15 21:47:56,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:47:56,321 INFO L470 AbstractCegarLoop]: Abstraction has 1377 states and 3532 transitions. [2022-03-15 21:47:56,321 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 38 states, 38 states have (on average 3.3947368421052633) internal successors, (129), 37 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:47:56,321 INFO L276 IsEmpty]: Start isEmpty. Operand 1377 states and 3532 transitions. [2022-03-15 21:47:56,323 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:47:56,323 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:47:56,323 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:47:56,338 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (76)] Forceful destruction successful, exit code 0 [2022-03-15 21:47:56,537 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 76 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable76 [2022-03-15 21:47:56,537 INFO L402 AbstractCegarLoop]: === Iteration 78 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:47:56,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:47:56,537 INFO L85 PathProgramCache]: Analyzing trace with hash -291150463, now seen corresponding path program 76 times [2022-03-15 21:47:56,538 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:47:56,538 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116565356] [2022-03-15 21:47:56,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:47:56,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:47:56,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:47:56,796 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:47:56,796 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:47:56,796 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116565356] [2022-03-15 21:47:56,797 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1116565356] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:47:56,797 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [822311838] [2022-03-15 21:47:56,797 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:47:56,797 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:47:56,797 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:47:56,798 INFO L229 MonitoredProcess]: Starting monitored process 77 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:47:56,798 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (77)] Waiting until timeout for monitored process [2022-03-15 21:47:56,825 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:47:56,825 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:47:56,825 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 42 conjunts are in the unsatisfiable core [2022-03-15 21:47:56,826 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:47:57,487 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:47:57,487 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:47:57,546 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:47:57,546 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:47:58,324 INFO L353 Elim1Store]: treesize reduction 264, result has 47.7 percent of original size [2022-03-15 21:47:58,324 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 0 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 45 case distinctions, treesize of input 66 treesize of output 270 [2022-03-15 21:48:01,647 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 9 proven. 51 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:48:01,647 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [822311838] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:48:01,647 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:48:01,647 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:48:01,647 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [900869816] [2022-03-15 21:48:01,647 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:48:01,649 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:48:01,667 INFO L252 McrAutomatonBuilder]: Finished intersection with 132 states and 253 transitions. [2022-03-15 21:48:01,667 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:48:05,800 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 18 new interpolants: [395265#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 395269#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 395261#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 395259#(and (or (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not v_assert) (not (< 0 w)) (< 1 w) (not (= (select queue back) 1)))), 395255#(and (or (<= d W) v_assert) (or (<= d W) (< 0 w))), 395266#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (<= (+ d temp 4) W) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 395257#(and (or v_assert (= (select queue front) 1)) (or (<= (+ d 1) W) (< 0 w)) (or (= (select queue front) 1) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 395256#(and (or (<= (+ d 1) W) (< 0 w)) (or (= (+ (- 1) temp) 0) v_assert) (or (= (+ (- 1) temp) 0) (< 0 w)) (or (<= (+ d 1) W) v_assert)), 395262#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 395267#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 395263#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 395264#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d temp) W)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 395268#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 395258#(and (or (< 1 w) (not (= (select queue back) 1)) (= (select queue front) 1)) (or (<= (+ d 1) W) (not (= (select queue back) 1)) v_assert) (or (<= (+ d 1) W) (< 1 w) (not (= (select queue back) 1))) (or (not (= (select queue back) 1)) v_assert (= (select queue front) 1))), 395260#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 395253#(and (or (not v_assert) (<= (+ d w 4) W)) (or (not v_assert) (= (select queue (+ 3 front)) 1)) (or (not v_assert) (<= back (+ front 4))) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)) (or (not v_assert) (<= (+ front 4) back))), 395254#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 395252#(and (or (not v_assert) (<= (+ 5 d) W)) (or (not v_assert) (= (select queue (+ 3 front)) 1)) (or (not v_assert) (<= back (+ front 4))) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)) (or (not v_assert) (<= (+ front 4) back)))] [2022-03-15 21:48:05,800 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 38 states [2022-03-15 21:48:05,800 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:48:05,801 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-03-15 21:48:05,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=445, Invalid=4525, Unknown=0, NotChecked=0, Total=4970 [2022-03-15 21:48:05,801 INFO L87 Difference]: Start difference. First operand 1377 states and 3532 transitions. Second operand has 38 states, 38 states have (on average 3.3421052631578947) internal successors, (127), 37 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:48:10,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:48:10,037 INFO L93 Difference]: Finished difference Result 4761 states and 11950 transitions. [2022-03-15 21:48:10,037 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2022-03-15 21:48:10,037 INFO L78 Accepts]: Start accepts. Automaton has has 38 states, 38 states have (on average 3.3421052631578947) internal successors, (127), 37 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:48:10,038 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:48:10,044 INFO L225 Difference]: With dead ends: 4761 [2022-03-15 21:48:10,044 INFO L226 Difference]: Without dead ends: 4708 [2022-03-15 21:48:10,045 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 101 SyntacticMatches, 14 SemanticMatches, 142 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5183 ImplicationChecksByTransitivity, 5.6s TimeCoverageRelationStatistics Valid=2552, Invalid=18040, Unknown=0, NotChecked=0, Total=20592 [2022-03-15 21:48:10,045 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 371 mSDsluCounter, 661 mSDsCounter, 0 mSdLazyCounter, 2096 mSolverCounterSat, 291 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 371 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2387 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 291 IncrementalHoareTripleChecker+Valid, 2096 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-03-15 21:48:10,045 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [371 Valid, 2 Invalid, 2387 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [291 Valid, 2096 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-03-15 21:48:10,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4708 states. [2022-03-15 21:48:10,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4708 to 1389. [2022-03-15 21:48:10,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1389 states, 1388 states have (on average 2.563400576368876) internal successors, (3558), 1388 states have internal predecessors, (3558), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:48:10,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1389 states to 1389 states and 3558 transitions. [2022-03-15 21:48:10,081 INFO L78 Accepts]: Start accepts. Automaton has 1389 states and 3558 transitions. Word has length 36 [2022-03-15 21:48:10,081 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:48:10,081 INFO L470 AbstractCegarLoop]: Abstraction has 1389 states and 3558 transitions. [2022-03-15 21:48:10,081 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 38 states, 38 states have (on average 3.3421052631578947) internal successors, (127), 37 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:48:10,081 INFO L276 IsEmpty]: Start isEmpty. Operand 1389 states and 3558 transitions. [2022-03-15 21:48:10,082 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:48:10,082 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:48:10,082 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:48:10,098 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (77)] Forceful destruction successful, exit code 0 [2022-03-15 21:48:10,295 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 77 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable77 [2022-03-15 21:48:10,295 INFO L402 AbstractCegarLoop]: === Iteration 79 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:48:10,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:48:10,296 INFO L85 PathProgramCache]: Analyzing trace with hash -1630700653, now seen corresponding path program 77 times [2022-03-15 21:48:10,297 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:48:10,297 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1953242634] [2022-03-15 21:48:10,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:48:10,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:48:10,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:48:10,574 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:48:10,574 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:48:10,574 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1953242634] [2022-03-15 21:48:10,574 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1953242634] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:48:10,574 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [744502271] [2022-03-15 21:48:10,574 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:48:10,574 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:48:10,575 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:48:10,576 INFO L229 MonitoredProcess]: Starting monitored process 78 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:48:10,576 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (78)] Waiting until timeout for monitored process [2022-03-15 21:48:10,605 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2022-03-15 21:48:10,605 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:48:10,606 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 41 conjunts are in the unsatisfiable core [2022-03-15 21:48:10,606 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:48:11,384 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,384 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,385 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,385 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,386 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,386 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:11,386 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,387 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,387 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,387 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:11,388 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,388 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,389 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,389 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,389 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,390 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:11,390 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,390 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,391 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:11,391 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:48:11,391 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 9 select indices, 9 select index equivalence classes, 10 disjoint index pairs (out of 36 index pairs), introduced 5 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 26 [2022-03-15 21:48:11,452 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:48:11,452 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:48:12,236 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,236 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,237 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,237 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,237 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,238 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,238 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,240 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,240 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,242 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,243 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,244 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,244 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,244 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,245 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,245 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,246 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,246 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,247 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,250 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,251 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,251 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,252 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,253 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,254 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,255 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:12,334 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:48:12,335 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 26 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 19 case distinctions, treesize of input 62 treesize of output 224 [2022-03-15 21:48:13,195 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:48:13,195 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [744502271] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:48:13,195 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:48:13,195 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:48:13,195 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1806742240] [2022-03-15 21:48:13,195 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:48:13,197 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:48:13,213 INFO L252 McrAutomatonBuilder]: Finished intersection with 119 states and 223 transitions. [2022-03-15 21:48:13,214 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:48:16,619 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 17 new interpolants: [403234#(and v_assert (< 0 w)), 403225#(and (or (= (+ (- 1) (select queue front)) 0) (not v_assert) (not (< 0 w))) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back))), 403228#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d temp) W)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 403226#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (not (< 0 w)) (= (+ front 1) back)) (or (not v_assert) (not (< 0 w)) (<= (+ 2 d temp) W))), 403232#(and (or (not v_assert) (<= (+ front 1) back)) (or (not v_assert) (<= back (+ front 1))) (or (not v_assert) (<= (+ d w 1) W)) (or (not v_assert) (= (select queue front) 1))), 403229#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ d 4) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 403222#(and (or (not v_assert) (<= (+ d temp 1) W)) (or (not v_assert) (= (select queue front) 1))), 403219#(and (or (not v_assert) (<= (+ d w 4) W)) (or (not v_assert) (= (select queue (+ 3 front)) 1)) (or (not v_assert) (<= back (+ front 4))) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)) (or (not v_assert) (<= (+ front 4) back))), 403220#(and (or (not v_assert) (<= back (+ 3 front))) (or (<= (+ 3 front) back) (not v_assert)) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (not v_assert) (<= (+ 3 d w) W)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 403218#(and (or (not v_assert) (<= (+ 5 d) W)) (or (not v_assert) (= (select queue (+ 3 front)) 1)) (or (not v_assert) (<= back (+ front 4))) (or (not v_assert) (= (select queue (+ 2 front)) 1)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1)) (or (not v_assert) (<= (+ front 4) back))), 403223#(and (or (<= (+ d 1) W) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= back front))), 403231#(and (or (not v_assert) (<= back (+ 2 front))) (or (not v_assert) (<= (+ 2 d w) W)) (or (not v_assert) (<= (+ 2 front) back)) (or (= (select queue (+ front 1)) 1) (not v_assert)) (or (not v_assert) (= (select queue front) 1))), 403227#(and (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (= (+ 2 front) back) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (<= (+ (select queue front) 2 d) W)) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 403230#(and (or (not v_assert) (not (< 0 w)) (= (select queue (+ 2 front)) 1)) (or (<= (+ 3 front) back) (not v_assert) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= (select queue front) 1)) (or (not v_assert) (not (< 0 w)) (= temp 1)) (or (not v_assert) (<= back (+ 3 front)) (not (< 0 w))) (or (not v_assert) (<= (+ d temp 4) W) (not (< 0 w))) (or (= (select queue (+ front 1)) 1) (not v_assert) (not (< 0 w)))), 403224#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= (+ 2 d) W) (not (< 0 w))) (or (not v_assert) (= (+ (- 1) temp) 0) (not (< 0 w)))), 403233#(and (or (not v_assert) (not (< 0 w)) (= back front)) (or (not v_assert) (<= d 0) (not (< 0 w))) (or (not v_assert) (not (< 0 w)) (= W w))), 403221#(and (or (<= (+ d 1) W) (not v_assert)) (or (not v_assert) (= (select queue front) 1)))] [2022-03-15 21:48:16,619 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-03-15 21:48:16,619 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:48:16,619 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-03-15 21:48:16,619 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=507, Invalid=4323, Unknown=0, NotChecked=0, Total=4830 [2022-03-15 21:48:16,620 INFO L87 Difference]: Start difference. First operand 1389 states and 3558 transitions. Second operand has 37 states, 37 states have (on average 3.1621621621621623) internal successors, (117), 36 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:48:20,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:48:20,036 INFO L93 Difference]: Finished difference Result 3899 states and 9776 transitions. [2022-03-15 21:48:20,037 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2022-03-15 21:48:20,037 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 3.1621621621621623) internal successors, (117), 36 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:48:20,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:48:20,042 INFO L225 Difference]: With dead ends: 3899 [2022-03-15 21:48:20,042 INFO L226 Difference]: Without dead ends: 3882 [2022-03-15 21:48:20,042 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 240 GetRequests, 90 SyntacticMatches, 13 SemanticMatches, 137 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4701 ImplicationChecksByTransitivity, 5.0s TimeCoverageRelationStatistics Valid=2237, Invalid=16945, Unknown=0, NotChecked=0, Total=19182 [2022-03-15 21:48:20,042 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 317 mSDsluCounter, 727 mSDsCounter, 0 mSdLazyCounter, 2252 mSolverCounterSat, 241 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 317 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 2493 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 241 IncrementalHoareTripleChecker+Valid, 2252 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:48:20,043 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [317 Valid, 2 Invalid, 2493 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [241 Valid, 2252 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-03-15 21:48:20,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3882 states. [2022-03-15 21:48:20,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3882 to 1377. [2022-03-15 21:48:20,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1376 states have (on average 2.566860465116279) internal successors, (3532), 1376 states have internal predecessors, (3532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:48:20,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 3532 transitions. [2022-03-15 21:48:20,062 INFO L78 Accepts]: Start accepts. Automaton has 1377 states and 3532 transitions. Word has length 36 [2022-03-15 21:48:20,062 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:48:20,062 INFO L470 AbstractCegarLoop]: Abstraction has 1377 states and 3532 transitions. [2022-03-15 21:48:20,062 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 3.1621621621621623) internal successors, (117), 36 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:48:20,062 INFO L276 IsEmpty]: Start isEmpty. Operand 1377 states and 3532 transitions. [2022-03-15 21:48:20,063 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:48:20,063 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:48:20,063 INFO L514 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:48:20,079 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (78)] Forceful destruction successful, exit code 0 [2022-03-15 21:48:20,267 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable78,78 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:48:20,267 INFO L402 AbstractCegarLoop]: === Iteration 80 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION] === [2022-03-15 21:48:20,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:48:20,267 INFO L85 PathProgramCache]: Analyzing trace with hash -1643941957, now seen corresponding path program 78 times [2022-03-15 21:48:20,268 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:48:20,268 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095125200] [2022-03-15 21:48:20,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:48:20,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:48:20,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:48:20,583 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:48:20,583 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:48:20,583 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095125200] [2022-03-15 21:48:20,583 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1095125200] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:48:20,583 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1109645214] [2022-03-15 21:48:20,583 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:48:20,584 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:48:20,584 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:48:20,585 INFO L229 MonitoredProcess]: Starting monitored process 79 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:48:20,585 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (79)] Waiting until timeout for monitored process [2022-03-15 21:48:20,611 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2022-03-15 21:48:20,611 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:48:20,612 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 44 conjunts are in the unsatisfiable core [2022-03-15 21:48:20,612 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:48:21,205 INFO L353 Elim1Store]: treesize reduction 112, result has 0.9 percent of original size [2022-03-15 21:48:21,205 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 5 new quantified variables, introduced 10 case distinctions, treesize of input 62 treesize of output 26 [2022-03-15 21:48:21,263 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:48:21,263 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:48:21,841 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,842 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,842 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,842 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,843 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,844 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,844 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,845 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,845 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,845 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,846 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,846 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,846 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,847 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,847 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,847 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,848 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,848 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,848 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,849 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,849 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,849 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,850 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,850 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,850 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,851 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,852 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,853 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,853 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,853 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:48:21,894 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:48:21,894 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 10 select indices, 10 select index equivalence classes, 30 disjoint index pairs (out of 45 index pairs), introduced 10 new quantified variables, introduced 15 case distinctions, treesize of input 66 treesize of output 198 [2022-03-15 21:48:22,717 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:48:22,717 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1109645214] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:48:22,717 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:48:22,717 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 52 [2022-03-15 21:48:22,717 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [654957582] [2022-03-15 21:48:22,717 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:48:22,719 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:48:22,735 INFO L252 McrAutomatonBuilder]: Finished intersection with 113 states and 208 transitions. [2022-03-15 21:48:22,735 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider Received shutdown request... [2022-03-15 21:48:26,694 WARN L244 SmtUtils]: Removed 2 from assertion stack [2022-03-15 21:48:26,695 INFO L764 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr0ASSERT_VIOLATIONASSERT (3 of 4 remaining) [2022-03-15 21:48:26,711 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (79)] Forceful destruction successful, exit code 0 [2022-03-15 21:48:26,715 WARN L340 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Timeout while monitored process is still running, waiting 1000 ms for graceful end [2022-03-15 21:48:26,715 WARN L340 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (79)] Timeout while monitored process is still running, waiting 1000 ms for graceful end [2022-03-15 21:48:26,905 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable79,79 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:48:26,905 WARN L594 AbstractCegarLoop]: Verification canceled: while BasicCegarLoop was analyzing trace of length 37 with TraceHistMax 5,while SimplifyDDAWithTimeout was simplifying term of DAG size 2 for 3ms.. [2022-03-15 21:48:26,906 INFO L764 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr0INUSE_VIOLATION (2 of 4 remaining) [2022-03-15 21:48:26,906 INFO L764 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr1INUSE_VIOLATION (1 of 4 remaining) [2022-03-15 21:48:26,906 INFO L764 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr2INUSE_VIOLATION (0 of 4 remaining) [2022-03-15 21:48:26,908 INFO L732 BasicCegarLoop]: Path program histogram: [78, 1, 1] [2022-03-15 21:48:26,910 INFO L230 ceAbstractionStarter]: Analysis of concurrent program completed with 1 thread instances [2022-03-15 21:48:26,910 INFO L180 ceAbstractionStarter]: Computing trace abstraction results [2022-03-15 21:48:26,911 INFO L202 PluginConnector]: Adding new model prod-cons.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 15.03 09:48:26 BasicIcfg [2022-03-15 21:48:26,911 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-03-15 21:48:26,911 INFO L158 Benchmark]: Toolchain (without parser) took 876151.31ms. Allocated memory was 199.2MB in the beginning and 676.3MB in the end (delta: 477.1MB). Free memory was 164.2MB in the beginning and 327.5MB in the end (delta: -163.4MB). Peak memory consumption was 315.3MB. Max. memory is 8.0GB. [2022-03-15 21:48:26,911 INFO L158 Benchmark]: Boogie PL CUP Parser took 0.09ms. Allocated memory is still 199.2MB. Free memory is still 165.3MB. There was no memory consumed. Max. memory is 8.0GB. [2022-03-15 21:48:26,911 INFO L158 Benchmark]: Boogie Procedure Inliner took 16.70ms. Allocated memory is still 199.2MB. Free memory was 164.1MB in the beginning and 162.6MB in the end (delta: 1.5MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. [2022-03-15 21:48:26,911 INFO L158 Benchmark]: Boogie Preprocessor took 12.25ms. Allocated memory is still 199.2MB. Free memory was 162.6MB in the beginning and 161.6MB in the end (delta: 977.8kB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. [2022-03-15 21:48:26,911 INFO L158 Benchmark]: RCFGBuilder took 202.63ms. Allocated memory is still 199.2MB. Free memory was 161.5MB in the beginning and 152.2MB in the end (delta: 9.3MB). Peak memory consumption was 9.4MB. Max. memory is 8.0GB. [2022-03-15 21:48:26,911 INFO L158 Benchmark]: TraceAbstraction took 875915.96ms. Allocated memory was 199.2MB in the beginning and 676.3MB in the end (delta: 477.1MB). Free memory was 151.7MB in the beginning and 327.5MB in the end (delta: -175.9MB). Peak memory consumption was 302.7MB. Max. memory is 8.0GB. [2022-03-15 21:48:26,912 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.09ms. Allocated memory is still 199.2MB. Free memory is still 165.3MB. There was no memory consumed. Max. memory is 8.0GB. * Boogie Procedure Inliner took 16.70ms. Allocated memory is still 199.2MB. Free memory was 164.1MB in the beginning and 162.6MB in the end (delta: 1.5MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. * Boogie Preprocessor took 12.25ms. Allocated memory is still 199.2MB. Free memory was 162.6MB in the beginning and 161.6MB in the end (delta: 977.8kB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. * RCFGBuilder took 202.63ms. Allocated memory is still 199.2MB. Free memory was 161.5MB in the beginning and 152.2MB in the end (delta: 9.3MB). Peak memory consumption was 9.4MB. Max. memory is 8.0GB. * TraceAbstraction took 875915.96ms. Allocated memory was 199.2MB in the beginning and 676.3MB in the end (delta: 477.1MB). Free memory was 151.7MB in the beginning and 327.5MB in the end (delta: -175.9MB). Peak memory consumption was 302.7MB. Max. memory is 8.0GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks Lipton Reduction Statistics: ReductionTime: 0.2s, 38 PlacesBefore, 28 PlacesAfterwards, 30 TransitionsBefore, 20 TransitionsAfterwards, 138 CoEnabledTransitionPairs, 3 FixpointIterations, 7 TrivialSequentialCompositions, 4 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 0 ConcurrentYvCompositions, 0 ChoiceCompositions, 11 TotalNumberOfCompositions, 321 MoverChecksTotal, Independence Relation Statistics: CachedIndependenceRelation.Independence Queries: [ total: 237, positive: 202, positive conditional: 0, positive unconditional: 202, negative: 35, negative conditional: 0, negative unconditional: 35, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 84, positive: 72, positive conditional: 0, positive unconditional: 72, negative: 12, negative conditional: 0, negative unconditional: 12, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 237, positive: 130, positive conditional: 0, positive unconditional: 130, negative: 23, negative conditional: 0, negative unconditional: 23, unknown: 84, unknown conditional: 0, unknown unconditional: 84] , Statistics on independence cache: Total cache size (in pairs): 33, Positive cache size: 27, Positive conditional cache size: 0, Positive unconditional cache size: 27, Negative cache size: 6, Negative conditional cache size: 0, Negative unconditional cache size: 6 - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - TimeoutResultAtElement [Line: 64]: Timeout (TraceAbstraction) Unable to prove that assertion always holds Cancelled while BasicCegarLoop was analyzing trace of length 37 with TraceHistMax 5,while SimplifyDDAWithTimeout was simplifying term of DAG size 2 for 3ms.. - TimeoutResultAtElement [Line: 58]: Timeout (TraceAbstraction) Unable to prove that petrification did provide enough thread instances (tool internal message, not intended for end users) Cancelled while BasicCegarLoop was analyzing trace of length 37 with TraceHistMax 5,while SimplifyDDAWithTimeout was simplifying term of DAG size 2 for 3ms.. - TimeoutResultAtElement [Line: 57]: Timeout (TraceAbstraction) Unable to prove that petrification did provide enough thread instances (tool internal message, not intended for end users) Cancelled while BasicCegarLoop was analyzing trace of length 37 with TraceHistMax 5,while SimplifyDDAWithTimeout was simplifying term of DAG size 2 for 3ms.. - TimeoutResultAtElement [Line: 57]: Timeout (TraceAbstraction) Unable to prove that petrification did provide enough thread instances (tool internal message, not intended for end users) Cancelled while BasicCegarLoop was analyzing trace of length 37 with TraceHistMax 5,while SimplifyDDAWithTimeout was simplifying term of DAG size 2 for 3ms.. - StatisticsResult: Ultimate Automizer benchmark data with 1 thread instances CFG has 7 procedures, 45 locations, 4 error locations. Started 1 CEGAR loops. OverallTime: 875.8s, OverallIterations: 80, TraceHistogramMax: 5, PathProgramHistogramMax: 78, EmptinessCheckTime: 0.1s, AutomataDifference: 284.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.3s, PartialOrderReductionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 22371 SdHoareTripleChecker+Valid, 50.8s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 22371 mSDsluCounter, 200 SdHoareTripleChecker+Invalid, 43.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 34646 mSDsCounter, 17189 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 118404 IncrementalHoareTripleChecker+Invalid, 135593 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 17189 mSolverCounterUnsat, 15 mSDtfsCounter, 118404 mSolverCounterSat, 0.3s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 17185 GetRequests, 6633 SyntacticMatches, 1367 SemanticMatches, 9185 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 358252 ImplicationChecksByTransitivity, 373.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=2257occurred in iteration=72, InterpolantAutomatonStates: 5174, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 1.7s AutomataMinimizationTime, 79 MinimizatonAttempts, 157917 StatesRemovedByMinimization, 77 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.3s SsaConstructionTime, 1.3s SatisfiabilityAnalysisTime, 292.5s InterpolantComputationTime, 5013 NumberOfCodeBlocks, 5013 NumberOfCodeBlocksAsserted, 342 NumberOfCheckSat, 7274 ConstructedInterpolants, 224 QuantifiedInterpolants, 152407 SizeOfPredicates, 693 NumberOfNonLiveVariables, 8190 ConjunctsInSsa, 2726 ConjunctsInUnsatCore, 233 InterpolantComputations, 2 PerfectInterpolantSequences, 592/10630 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Completed graceful shutdown